diff --git a/src/intel/vulkan_hasvk/anv_device.c b/src/intel/vulkan_hasvk/anv_device.c
index 416b061..a199ab3 100644
--- a/src/intel/vulkan_hasvk/anv_device.c
+++ b/src/intel/vulkan_hasvk/anv_device.c
@@ -2110,7 +2110,12 @@ void anv_GetPhysicalDeviceQueueFamilyProperties2(
             case VK_STRUCTURE_TYPE_QUEUE_FAMILY_QUERY_RESULT_STATUS_PROPERTIES_KHR: {
                VkQueueFamilyQueryResultStatusPropertiesKHR *prop =
                   (VkQueueFamilyQueryResultStatusPropertiesKHR *)ext;
-               prop->queryResultStatusSupport = VK_TRUE;
+               /* Result status queries require the queue's command streamer
+                * to write the query result to memory. The VCS seemingly
+                * cannot do a posted memory write. */
+               prop->queryResultStatusSupport =
+                  (queue_family->queueFlags & VK_QUEUE_VIDEO_DECODE_BIT_KHR) ?
+                  VK_FALSE : VK_TRUE;
                break;
             }
             case VK_STRUCTURE_TYPE_QUEUE_FAMILY_VIDEO_PROPERTIES_KHR: {
diff --git a/src/intel/vulkan_hasvk/anv_genX.h b/src/intel/vulkan_hasvk/anv_genX.h
index 3ff7439..69b320a 100644
--- a/src/intel/vulkan_hasvk/anv_genX.h
+++ b/src/intel/vulkan_hasvk/anv_genX.h
@@ -160,3 +160,8 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
 
 void
 genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline);
+
+void
+genX(emit_query_mi_flush_availability)(struct anv_cmd_buffer *cmd_buffer,
+                                       struct anv_address addr,
+                                       bool available);
diff --git a/src/intel/vulkan_hasvk/anv_private.h b/src/intel/vulkan_hasvk/anv_private.h
index 9eec925..d7a7d63 100644
--- a/src/intel/vulkan_hasvk/anv_private.h
+++ b/src/intel/vulkan_hasvk/anv_private.h
@@ -3700,6 +3700,9 @@ struct anv_query_pool {
    struct intel_perf_counter_pass                *counter_pass;
    uint32_t                                     n_passes;
    struct intel_perf_query_info                 **pass_query;
+
+   /* Video encoding queries */
+   VkVideoCodecOperationFlagsKHR                codec;
 };
 
 #define ANV_MB_WIDTH 16
diff --git a/src/intel/vulkan_hasvk/genX_query.c b/src/intel/vulkan_hasvk/genX_query.c
index a1cb1b1..2220223 100644
--- a/src/intel/vulkan_hasvk/genX_query.c
+++ b/src/intel/vulkan_hasvk/genX_query.c
@@ -59,10 +59,10 @@ anv_query_address(struct anv_query_pool *pool, uint32_t query)
    };
 }
 
-static void
-emit_query_mi_flush_availability(struct anv_cmd_buffer *cmd_buffer,
-                                 struct anv_address addr,
-                                 bool available)
+void
+genX(emit_query_mi_flush_availability)(struct anv_cmd_buffer *cmd_buffer,
+                                       struct anv_address addr,
+                                       bool available)
 {
    anv_batch_emit(&cmd_buffer->batch, GENX(MI_FLUSH_DW), flush) {
       flush.PostSyncOperation = WriteImmediateData;
@@ -815,7 +815,7 @@ void genX(CmdResetQueryPool)(
    }
    case VK_QUERY_TYPE_RESULT_STATUS_ONLY_KHR:
       for (uint32_t i = 0; i < queryCount; i++)
-         emit_query_mi_flush_availability(cmd_buffer, anv_query_address(pool, firstQuery + i), false);
+         genX(emit_query_mi_flush_availability)(cmd_buffer, anv_query_address(pool, firstQuery + i), false);
       break;
 
    default:
@@ -1117,7 +1117,7 @@ void genX(CmdBeginQueryIndexedEXT)(
       break;
    }
    case VK_QUERY_TYPE_RESULT_STATUS_ONLY_KHR:
-      emit_query_mi_flush_availability(cmd_buffer, query_addr, false);
+      genX(emit_query_mi_flush_availability)(cmd_buffer, query_addr, false);
       break;
    default:
       UNREACHABLE("");
@@ -1287,7 +1287,7 @@ void genX(CmdEndQueryIndexedEXT)(
       break;
    }
    case VK_QUERY_TYPE_RESULT_STATUS_ONLY_KHR:
-      emit_query_mi_flush_availability(cmd_buffer, query_addr, true);
+      genX(emit_query_mi_flush_availability)(cmd_buffer, query_addr, true);
       break;
 
    default: