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https://github.com/elwrcl/intel-hard-graphics.git
synced 2026-10-31 19:08:03 +03:00
hasvk: Without a QPitch override gen7 can't reliably handle layered DPB.
Just accept corruption and avoid intermittent hangs when not tile aligned. Breaks: dEQP-VK.video.decode.h264.interleaved_layered_dpb_video_layout Assisted-by: Claude
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2 files changed
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@@ -3619,9 +3619,6 @@ anv_image_dpb_address(const struct anv_image_view *iv,
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&x_offset_sa,
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&x_offset_sa,
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&y_offset_sa);
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&y_offset_sa);
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if (x_offset_sa || y_offset_sa)
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mesa_logw_once("QPitch restrictions on gen7 can result in corruption.");
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return anv_address_add(addr, offset_B);
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return anv_address_add(addr, offset_B);
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}
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}
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@@ -163,6 +163,31 @@ anv_h264_sane_field_pocs(const int32_t poc[2], int32_t *top, int32_t *bottom)
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*top = t; *bottom = b;
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*top = t; *bottom = b;
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}
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}
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static inline struct anv_address
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anv_h264_dpb_addr(const struct anv_image_view *iv, uint32_t layer, bool clamp0)
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{
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if (clamp0)
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return anv_image_address(iv->image,
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&iv->image->planes[0].primary_surface.memory_range);
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return anv_image_dpb_address(iv, layer);
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}
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static inline struct anv_address
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anv_h264_dmv_top(const struct anv_image_view *iv, uint32_t layer, bool clamp0)
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{
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if (clamp0)
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return anv_image_address(iv->image, &iv->image->vid_dmv_top_surface);
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return anv_image_dmv_top_address(iv, layer);
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}
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static inline struct anv_address
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anv_h264_dmv_bottom(const struct anv_image_view *iv, uint32_t layer, bool clamp0)
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{
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if (clamp0)
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return anv_image_address(iv->image, &iv->image->vid_dmv_bottom_surface);
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return anv_image_dmv_bottom_address(iv, layer);
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}
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static void
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static void
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anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
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anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
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const VkVideoDecodeInfoKHR *frame_info)
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const VkVideoDecodeInfoKHR *frame_info)
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@@ -225,6 +250,14 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
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const struct anv_image_view *iv = anv_image_view_from_handle(frame_info->dstPictureResource.imageViewBinding);
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const struct anv_image_view *iv = anv_image_view_from_handle(frame_info->dstPictureResource.imageViewBinding);
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const struct anv_image *img = iv->image;
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const struct anv_image *img = iv->image;
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#if GFX_VER < 8
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const bool gen7_layered_clamp = img->vk.array_layers > 1;
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if (gen7_layered_clamp)
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mesa_logw_once("hasvk/video: Layered DPB is broken on gen7 when the array pitch is not tile aligned.");
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#else
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const bool gen7_layered_clamp = false;
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#endif
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if (INTEL_DEBUG(DEBUG_PERF)) {
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if (INTEL_DEBUG(DEBUG_PERF)) {
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const StdVideoDecodeH264PictureInfo *p = h264_pic_info->pStdPictureInfo;
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const StdVideoDecodeH264PictureInfo *p = h264_pic_info->pStdPictureInfo;
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mesa_logw("hasvk/video: VID f_num=%d poc=%d/%d field=%u bot=%u idr=%u ref=%u "
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mesa_logw("hasvk/video: VID f_num=%d poc=%d/%d field=%u bot=%u idr=%u ref=%u "
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@@ -308,7 +341,7 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
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buf.CommandType = 3;
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buf.CommandType = 3;
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struct anv_address dst_addr =
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struct anv_address dst_addr =
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anv_image_dpb_address(iv, frame_info->dstPictureResource.baseArrayLayer);
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anv_h264_dpb_addr(iv, frame_info->dstPictureResource.baseArrayLayer, gen7_layered_clamp);
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#if GFX_VERx10 == 70
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#if GFX_VERx10 == 70
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buf.PostDeblockingDestinationAddress = dst_addr;
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buf.PostDeblockingDestinationAddress = dst_addr;
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buf.PostDeblockingDestinationCacheabilityControl = 2;
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buf.PostDeblockingDestinationCacheabilityControl = 2;
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@@ -360,8 +393,9 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
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continue;
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continue;
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const struct anv_image_view *ref_iv = anv_image_view_from_handle(frame_info->pReferenceSlots[i].pPictureResource->imageViewBinding);
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const struct anv_image_view *ref_iv = anv_image_view_from_handle(frame_info->pReferenceSlots[i].pPictureResource->imageViewBinding);
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struct anv_address ref_addr =
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struct anv_address ref_addr =
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anv_image_dpb_address(ref_iv,
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anv_h264_dpb_addr(ref_iv,
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frame_info->pReferenceSlots[i].pPictureResource->baseArrayLayer);
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frame_info->pReferenceSlots[i].pPictureResource->baseArrayLayer,
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gen7_layered_clamp);
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buf.ReferencePictureAddress[hw] = ref_addr;
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buf.ReferencePictureAddress[hw] = ref_addr;
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#if GFX_VERx10 == 70
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#if GFX_VERx10 == 70
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@@ -640,7 +674,7 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
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uint32_t ref_layer =
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uint32_t ref_layer =
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frame_info->pReferenceSlots[i].pPictureResource->baseArrayLayer;
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frame_info->pReferenceSlots[i].pPictureResource->baseArrayLayer;
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if (i == 0)
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if (i == 0)
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dmv_bo = anv_image_dmv_top_address(ref_iv, ref_layer).bo;
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dmv_bo = anv_h264_dmv_top(ref_iv, ref_layer, gen7_layered_clamp).bo;
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#if GFX_VERx10 == 70
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#if GFX_VERx10 == 70
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{
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{
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bool ref_is_field = ref_info &&
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bool ref_is_field = ref_info &&
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@@ -648,16 +682,16 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
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bool ref_dmv_bottom = ref_is_field &&
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bool ref_dmv_bottom = ref_is_field &&
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!sps->flags.direct_8x8_inference_flag;
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!sps->flags.direct_8x8_inference_flag;
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avc_directmode.DirectMVBufferAddress[hw * 2] =
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avc_directmode.DirectMVBufferAddress[hw * 2] =
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anv_image_dmv_top_address(ref_iv, ref_layer);
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anv_h264_dmv_top(ref_iv, ref_layer, gen7_layered_clamp);
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avc_directmode.DirectMVBufferAddress[hw * 2 + 1] = ref_dmv_bottom ?
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avc_directmode.DirectMVBufferAddress[hw * 2 + 1] = ref_dmv_bottom ?
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anv_image_dmv_bottom_address(ref_iv, ref_layer) :
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anv_h264_dmv_bottom(ref_iv, ref_layer, gen7_layered_clamp) :
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anv_image_dmv_top_address(ref_iv, ref_layer);
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anv_h264_dmv_top(ref_iv, ref_layer, gen7_layered_clamp);
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}
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}
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avc_directmode.DirectMVBufferCacheabilityControl[hw * 2] = 2;
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avc_directmode.DirectMVBufferCacheabilityControl[hw * 2] = 2;
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avc_directmode.DirectMVBufferCacheabilityControl[hw * 2 + 1] = 2;
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avc_directmode.DirectMVBufferCacheabilityControl[hw * 2 + 1] = 2;
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#elif GFX_VERx10 == 75
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#elif GFX_VERx10 == 75
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{
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{
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struct anv_address dmv_addr = anv_image_dmv_top_address(ref_iv, ref_layer);
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struct anv_address dmv_addr = anv_h264_dmv_top(ref_iv, ref_layer, gen7_layered_clamp);
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if (hw == 0) {
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if (hw == 0) {
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avc_directmode.DirectMVBuffer0Address = dmv_addr;
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avc_directmode.DirectMVBuffer0Address = dmv_addr;
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avc_directmode.DirectMVBufferMOCS = anv_mocs(cmd_buffer->device, dmv_addr.bo, 0);
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avc_directmode.DirectMVBufferMOCS = anv_mocs(cmd_buffer->device, dmv_addr.bo, 0);
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@@ -667,7 +701,7 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
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}
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}
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}
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}
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#elif GFX_VERx10 == 80
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#elif GFX_VERx10 == 80
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avc_directmode.DirectMVBufferAddress[hw] = anv_image_dmv_top_address(ref_iv, ref_layer);
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avc_directmode.DirectMVBufferAddress[hw] = anv_h264_dmv_top(ref_iv, ref_layer, gen7_layered_clamp);
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#endif
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#endif
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{
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{
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int32_t ref_top, ref_bot;
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int32_t ref_top, ref_bot;
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@@ -681,21 +715,21 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
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{
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{
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bool cur_dmv_bottom = field_pic && !sps->flags.direct_8x8_inference_flag;
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bool cur_dmv_bottom = field_pic && !sps->flags.direct_8x8_inference_flag;
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avc_directmode.DirectMVBufferWriteAddress[0] =
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avc_directmode.DirectMVBufferWriteAddress[0] =
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anv_image_dmv_top_address(iv, dst_layer);
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anv_h264_dmv_top(iv, dst_layer, gen7_layered_clamp);
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avc_directmode.DirectMVBufferWriteAddress[1] = cur_dmv_bottom ?
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avc_directmode.DirectMVBufferWriteAddress[1] = cur_dmv_bottom ?
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anv_image_dmv_bottom_address(iv, dst_layer) :
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anv_h264_dmv_bottom(iv, dst_layer, gen7_layered_clamp) :
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anv_image_dmv_top_address(iv, dst_layer);
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anv_h264_dmv_top(iv, dst_layer, gen7_layered_clamp);
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}
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}
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avc_directmode.DirectMVBufferWriteCacheabilityControl[0] = 2;
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avc_directmode.DirectMVBufferWriteCacheabilityControl[0] = 2;
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avc_directmode.DirectMVBufferWriteCacheabilityControl[1] = 2;
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avc_directmode.DirectMVBufferWriteCacheabilityControl[1] = 2;
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#elif GFX_VERx10 == 75
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#elif GFX_VERx10 == 75
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avc_directmode.DirectMVBufferWriteAddress = anv_image_dmv_top_address(iv, dst_layer);
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avc_directmode.DirectMVBufferWriteAddress = anv_h264_dmv_top(iv, dst_layer, gen7_layered_clamp);
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avc_directmode.DirectMVBufferWriteMOCS = anv_mocs(cmd_buffer->device, avc_directmode.DirectMVBufferWriteAddress.bo, 0);
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avc_directmode.DirectMVBufferWriteMOCS = anv_mocs(cmd_buffer->device, avc_directmode.DirectMVBufferWriteAddress.bo, 0);
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if (!avc_directmode.DirectMVBufferMOCS)
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if (!avc_directmode.DirectMVBufferMOCS)
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avc_directmode.DirectMVBufferMOCS = anv_mocs(cmd_buffer->device, avc_directmode.DirectMVBufferWriteAddress.bo, 0);
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avc_directmode.DirectMVBufferMOCS = anv_mocs(cmd_buffer->device, avc_directmode.DirectMVBufferWriteAddress.bo, 0);
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#elif GFX_VERx10 == 80
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#elif GFX_VERx10 == 80
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avc_directmode.DirectMVBufferAttributes.TargetCache = 2; /* LLC/eLLC */
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avc_directmode.DirectMVBufferAttributes.TargetCache = 2; /* LLC/eLLC */
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avc_directmode.DirectMVBufferWriteAddress = anv_image_dmv_top_address(iv, dst_layer);
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avc_directmode.DirectMVBufferWriteAddress = anv_h264_dmv_top(iv, dst_layer, gen7_layered_clamp);
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avc_directmode.DirectMVBufferWriteAttributes.TargetCache = 2;
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avc_directmode.DirectMVBufferWriteAttributes.TargetCache = 2;
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#endif
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#endif
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{
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{
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