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bunch of wip gfx75 fixes

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[dancingmirrors: Adapt for the current genxml format.]
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Dave Airlie authored and elwrcl committed 2026-07-21 22:08:57 +03:00
1 parent 67635d1925
commit 5d68b51dca
2 files changed
+26 -5
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src/intel/genxml/gen75.xml
+8 -3
View File
@@ -1507,10 +1507,15 @@
<field name="Media Command Opcode" dword="0" bits="26:24" type="uint" default="1" /> <field name="Media Command Opcode" dword="0" bits="26:24" type="uint" default="1" />
<field name="Pipeline" dword="0" bits="28:27" type="uint" default="2" /> <field name="Pipeline" dword="0" bits="28:27" type="uint" default="2" />
<field name="Command Type" dword="0" bits="31:29" type="uint" default="3" /> <field name="Command Type" dword="0" bits="31:29" type="uint" default="3" />
<group count="16" dword="1" size="64"> <field name="Direct MV Buffer - MOCS" dword="1" bits="3:0" type="uint" nonzero="true"/>
<field name="Direct MV Buffer - Address" dword="0" bits="63:0" type="address" /> <field name="Direct MV Buffer - Arbitration Priority Control" dword="1" bits="5:4" type="uint"/>
<field name="Direct MV Buffer 0 - Address" dword="1" bits="31:6" type="address"/>
<group count="15" dword="2" size="64">
<field name="Direct MV Buffer - Address 1" dword="0" bits="31:6" type="address" />
</group> </group>
<field name="Direct MV Buffer (Write) - Address" dword="34" bits="63:0" type="address" /> <field name="Direct MV Buffer Write - MOCS" dword="34" bits="2:0" type="uint" nonzero="true"/>
<field name="Direct MV Buffer Write - Arbitration Priority Control" dword="34" bits="4:3" type="uint"/>
<field name="Direct MV Buffer (Write) - Address" dword="34" bits="31:5" type="address" />
<group count="34" dword="37" size="32"> <group count="34" dword="37" size="32">
<field name="POC List" dword="0" bits="31:0" type="uint" /> <field name="POC List" dword="0" bits="31:0" type="uint" />
</group> </group>
src/intel/vulkan_hasvk/genX_video.c
+18 -2
View File
@@ -156,7 +156,7 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
anv_batch_emit(&cmd_buffer->batch, GENX(MFX_IND_OBJ_BASE_ADDR_STATE), index_obj) { anv_batch_emit(&cmd_buffer->batch, GENX(MFX_IND_OBJ_BASE_ADDR_STATE), index_obj) {
index_obj.MFXIndirectBitstreamObjectAddress = anv_address_add(src_buffer->address, index_obj.MFXIndirectBitstreamObjectAddress = anv_address_add(src_buffer->address,
frame_info->srcBufferOffset); frame_info->srcBufferOffset & ~4095);
#if GFX_VERx10 == 75 #if GFX_VERx10 == 75
index_obj.MFXIndirectBitstreamObjectMOCS = anv_mocs(cmd_buffer->device, src_buffer->address.bo, index_obj.MFXIndirectBitstreamObjectMOCS = anv_mocs(cmd_buffer->device, src_buffer->address.bo,
0); 0);
@@ -342,14 +342,26 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
anv_batch_emit(&cmd_buffer->batch, GENX(MFX_AVC_DIRECTMODE_STATE), avc_directmode) { anv_batch_emit(&cmd_buffer->batch, GENX(MFX_AVC_DIRECTMODE_STATE), avc_directmode) {
/* bind reference frame DMV */ /* bind reference frame DMV */
struct anv_bo *dmv_bo = NULL;
for (unsigned i = 0; i < frame_info->referenceSlotCount; i++) { for (unsigned i = 0; i < frame_info->referenceSlotCount; i++) {
int idx = frame_info->pReferenceSlots[i].slotIndex; int idx = frame_info->pReferenceSlots[i].slotIndex;
const struct VkVideoDecodeH264DpbSlotInfoKHR *dpb_slot = const struct VkVideoDecodeH264DpbSlotInfoKHR *dpb_slot =
vk_find_struct_const(frame_info->pReferenceSlots[i].pNext, VIDEO_DECODE_H264_DPB_SLOT_INFO_KHR); vk_find_struct_const(frame_info->pReferenceSlots[i].pNext, VIDEO_DECODE_H264_DPB_SLOT_INFO_KHR);
const struct anv_image_view *ref_iv = anv_image_view_from_handle(frame_info->pReferenceSlots[i].pPictureResource->imageViewBinding); const struct anv_image_view *ref_iv = anv_image_view_from_handle(frame_info->pReferenceSlots[i].pPictureResource->imageViewBinding);
const StdVideoDecodeH264ReferenceInfo *ref_info = dpb_slot->pStdReferenceInfo; const StdVideoDecodeH264ReferenceInfo *ref_info = dpb_slot->pStdReferenceInfo;
avc_directmode.DirectMVBufferAddress[idx] = anv_image_address(ref_iv->image, if (i == 0) {
dmv_bo = anv_image_address(ref_iv->image,
&ref_iv->image->vid_dmv_top_surface).bo;
}
#if GFX_VERx10 == 75
if (idx == 0)
avc_directmode.DirectMVBuffer0Address = anv_image_address(ref_iv->image,
&ref_iv->image->vid_dmv_top_surface); &ref_iv->image->vid_dmv_top_surface);
else
avc_directmode.DirectMVBufferAddress1[idx - 1] = anv_image_address(ref_iv->image,
&ref_iv->image->vid_dmv_top_surface);
#endif
avc_directmode.POCList[2 * idx] = ref_info->PicOrderCnt[0]; avc_directmode.POCList[2 * idx] = ref_info->PicOrderCnt[0];
avc_directmode.POCList[2 * idx + 1] = ref_info->PicOrderCnt[1]; avc_directmode.POCList[2 * idx + 1] = ref_info->PicOrderCnt[1];
} }
@@ -359,6 +371,10 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer,
#else #else
avc_directmode.DirectMVBufferWriteAddress = anv_image_address(img, avc_directmode.DirectMVBufferWriteAddress = anv_image_address(img,
&img->vid_dmv_top_surface); &img->vid_dmv_top_surface);
#if GFX_VERx10 == 75
avc_directmode.DirectMVBufferMOCS = anv_mocs(cmd_buffer->device, dmv_bo, 0);
avc_directmode.DirectMVBufferWriteMOCS = anv_mocs(cmd_buffer->device, avc_directmode.DirectMVBufferWriteAddress.bo, 0);
#endif
#endif #endif
avc_directmode.POCList[32] = h264_pic_info->pStdPictureInfo->PicOrderCnt[0]; avc_directmode.POCList[32] = h264_pic_info->pStdPictureInfo->PicOrderCnt[0];
avc_directmode.POCList[33] = h264_pic_info->pStdPictureInfo->PicOrderCnt[1]; avc_directmode.POCList[33] = h264_pic_info->pStdPictureInfo->PicOrderCnt[1];