hasvk: Add host_image_copy, H.264 encode and a batch of gen7 fixes.

Squashed work that had been sitting in the working tree. Grouped by area:

Extensions
  VK_EXT_host_image_copy, with a MEMCPY_BIT path that reads and writes the
  image's own tiled layout, VkSubresourceHostMemcpySizeEXT filled in, and
  VkHostImageCopyDevicePerformanceQueryEXT answered.  Depth/stencil and
  non-power-of-two bpb stay NotSupported.
  VK_EXT_pipeline_robustness, VK_KHR_shader_float_controls2,
  VK_KHR_shader_subgroup_rotate, VK_EXT_vertex_input_dynamic_state,
  VK_EXT_conditional_rendering (an MI_PREDICATE path for gen7, which has no
  GPRs), custom_border_color, border_color_swizzle, map_memory2,
  load_store_op_none, depth_clamp_zero_one,
  dynamic_rendering_unused_attachments, index_type_uint8,
  line_rasterization, vertex_attribute_divisor, mutable_descriptor_type.

H.264 encode
  MFC command emission and a bitstream writer, driving intra-only encode
  through the video queue.  Video profile reporting was also corrected from
  270 combinations down to the 11 that actually exist.

Correctness
  gfx7 routes typed surface writes through the render cache, so
  VK_ACCESS_SHADER_WRITE barriers have to flush it -- without that, nothing a
  fragment shader stored was visible.
  nir_opt_algebraic's fadd->flrp fusion rules dropped signed zero; '~' only
  excludes nir_fp_exact, not preserve_signed_zero, so reflect() with a -0
  input came out wrong.  Guarded with (nsz).
  Stop advertising STORAGE_READ_WITHOUT_FORMAT: shaderStorageImageReadWithout-
  Format is false here, and since Vulkan 1.3 the per-format bit is what grants
  permission, so reporting it while rejecting the pipeline is a contradiction.
  gfx7's typed data port ignores SURFTYPE_NULL -- the null surface still has
  one addressable texel, which read and wrote graphics address zero.  Bounds
  check typed image access against the image param when nullDescriptor is
  enabled, the same trick lower_image_atomic_instr already used on IVB.
  Formats that require a sampler Y'CbCr conversion no longer report
  BLIT_SRC/BLIT_DST/STORAGE_IMAGE.  Video decode does not need them.
  Check the surface state allocations in emit_binding_table() and in the push
  descriptor path instead of writing through a NULL map in release builds.

Co-Authored-By: Claude Opus 5 <[email protected]>

src/intel/vulkan_hasvk/anv_genX.h

@@ -69,8 +69,40 @@ void genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(struct anv_cmd_buffer *
                                                          uint64_t vb_used);
 
 void genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer);
+void genX(flush_pipeline_select_media)(struct anv_cmd_buffer *cmd_buffer);
 void genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer);
 
+/* Emits the MFC/MFX static state and per-MB PAK objects for one H.264 encode.
+ * Defined in anv_video_mfc.c (a separate TU due to the genX_pack.h /
+ * genX_video_pack.h include-guard collision; see that file's header). */
+/* Emits the frame-level MFC/MFX static state (everything up to but not
+ * including the slices). Call once per frame, before emitting any slice. */
+void genX(hasvk_mfc_emit_static_state)(struct anv_cmd_buffer *cmd_buffer,
+                                       const struct anv_image *source_image,
+                                       struct anv_address recon_address,
+                                       const StdVideoH264SequenceParameterSet *sps,
+                                       const StdVideoH264PictureParameterSet *pps,
+                                       struct anv_address dst_address,
+                                       uint32_t dst_page_offset,
+                                       uint64_t dst_buffer_range,
+                                       uint32_t width_in_mbs, uint32_t height_in_mbs,
+                                       bool is_p, struct anv_address ref_address);
+
+/* Emits one slice: MFX_AVC_SLICE_STATE, the slice-header insert, the per-MB
+ * PAK objects for the macroblock range [slice_start_mb, slice_end_mb), and the
+ * slice tail. Call once per slice, after the frame-level static state. Intra
+ * neighbour availability is computed relative to slice_start_mb so it matches
+ * the decoder (intra prediction does not cross slice boundaries). */
+void genX(hasvk_mfc_emit_slice)(struct anv_cmd_buffer *cmd_buffer,
+                                const StdVideoH264SequenceParameterSet *sps,
+                                const StdVideoH264PictureParameterSet *pps,
+                                const StdVideoEncodeH264PictureInfo *pic_info,
+                                const StdVideoEncodeH264SliceHeader *slice_hdr,
+                                uint32_t slice_start_mb, uint32_t slice_end_mb,
+                                uint32_t width_in_mbs, uint32_t height_in_mbs,
+                                uint32_t qp, bool is_last_slice,
+                                uint32_t dst_page_offset);
+
 enum anv_pipe_bits
 genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
                               struct anv_device *device,
@@ -115,6 +147,11 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
                      VkShaderStageFlags active_stages,
                      const unsigned entry_size[4]);
 
+void
+genX(emit_vertex_input)(struct anv_graphics_pipeline *pipeline,
+                        struct anv_batch *batch,
+                        const struct vk_vertex_input_state *vi);
+
 void genX(emit_multisample)(struct anv_batch *batch, uint32_t samples,
                             const struct vk_sample_locations_state *sl);
 
@@ -165,3 +202,13 @@ void
 genX(emit_query_mi_flush_availability)(struct anv_cmd_buffer *cmd_buffer,
                                        struct anv_address addr,
                                        bool available);
+
+void
+genX(emit_query_mi_write_u64)(struct anv_cmd_buffer *cmd_buffer,
+                              struct anv_address addr,
+                              uint64_t value);
+
+void
+genX(emit_query_mi_write_reg32)(struct anv_cmd_buffer *cmd_buffer,
+                                struct anv_address addr,
+                                uint32_t reg);