hasvk: Add host_image_copy, H.264 encode and a batch of gen7 fixes.

Squashed work that had been sitting in the working tree. Grouped by area:

Extensions
  VK_EXT_host_image_copy, with a MEMCPY_BIT path that reads and writes the
  image's own tiled layout, VkSubresourceHostMemcpySizeEXT filled in, and
  VkHostImageCopyDevicePerformanceQueryEXT answered.  Depth/stencil and
  non-power-of-two bpb stay NotSupported.
  VK_EXT_pipeline_robustness, VK_KHR_shader_float_controls2,
  VK_KHR_shader_subgroup_rotate, VK_EXT_vertex_input_dynamic_state,
  VK_EXT_conditional_rendering (an MI_PREDICATE path for gen7, which has no
  GPRs), custom_border_color, border_color_swizzle, map_memory2,
  load_store_op_none, depth_clamp_zero_one,
  dynamic_rendering_unused_attachments, index_type_uint8,
  line_rasterization, vertex_attribute_divisor, mutable_descriptor_type.

H.264 encode
  MFC command emission and a bitstream writer, driving intra-only encode
  through the video queue.  Video profile reporting was also corrected from
  270 combinations down to the 11 that actually exist.

Correctness
  gfx7 routes typed surface writes through the render cache, so
  VK_ACCESS_SHADER_WRITE barriers have to flush it -- without that, nothing a
  fragment shader stored was visible.
  nir_opt_algebraic's fadd->flrp fusion rules dropped signed zero; '~' only
  excludes nir_fp_exact, not preserve_signed_zero, so reflect() with a -0
  input came out wrong.  Guarded with (nsz).
  Stop advertising STORAGE_READ_WITHOUT_FORMAT: shaderStorageImageReadWithout-
  Format is false here, and since Vulkan 1.3 the per-format bit is what grants
  permission, so reporting it while rejecting the pipeline is a contradiction.
  gfx7's typed data port ignores SURFTYPE_NULL -- the null surface still has
  one addressable texel, which read and wrote graphics address zero.  Bounds
  check typed image access against the image param when nullDescriptor is
  enabled, the same trick lower_image_atomic_instr already used on IVB.
  Formats that require a sampler Y'CbCr conversion no longer report
  BLIT_SRC/BLIT_DST/STORAGE_IMAGE.  Video decode does not need them.
  Check the surface state allocations in emit_binding_table() and in the push
  descriptor path instead of writing through a NULL map in release builds.

Co-Authored-By: Claude Opus 5 <[email protected]>

src/intel/vulkan_hasvk/anv_private.h

@@ -103,7 +103,6 @@ struct anv_buffer_view;
 struct anv_image;
 struct anv_image_view;
 struct anv_instance;
-
 struct intel_perf_config;
 struct intel_perf_counter_pass;
 struct intel_perf_query_result;
@@ -806,7 +805,7 @@ struct anv_queue_family {
    enum intel_engine_class engine_class;
 };
 
-#define ANV_MAX_QUEUE_FAMILIES 3
+#define ANV_MAX_QUEUE_FAMILIES 4
 
 struct anv_memory_type {
    /* Standard bits passed on to the client */
@@ -944,6 +943,7 @@ struct anv_instance {
 enum anv_debug {
    ANV_DEBUG_VIDEO_DECODE               = BITFIELD_BIT(0),
    ANV_DEBUG_VIDEO_DEBUG                = BITFIELD_BIT(1),
+   ANV_DEBUG_VIDEO_ENCODE               = BITFIELD_BIT(2),
 };
 
 extern enum anv_debug anv_debug;
@@ -1872,7 +1872,7 @@ anv_descriptor_set_write_buffer_view(struct anv_device *device,
                                      uint32_t binding,
                                      uint32_t element);
 
-void
+VkResult
 anv_descriptor_set_write_buffer(struct anv_device *device,
                                 struct anv_descriptor_set *set,
                                 struct anv_state_stream *alloc_stream,
@@ -1891,7 +1891,7 @@ anv_descriptor_set_write_inline_uniform_data(struct anv_device *device,
                                              size_t offset,
                                              size_t size);
 
-void
+VkResult
 anv_descriptor_set_write_template(struct anv_device *device,
                                   struct anv_descriptor_set *set,
                                   struct anv_state_stream *alloc_stream,
@@ -2079,6 +2079,14 @@ anv_pipe_flush_bits_for_access_flags(struct anv_device *device,
           */
          pipe_bits |= ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
          pipe_bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
+         /* On gfx7, typed surface writes (image stores) are serviced by the
+          * render cache rather than the data cache, so it has to be flushed
+          * as well or the writes stay invisible to subsequent operations.
+          * This only shows up from the fragment stage, where the render cache
+          * is actually in use.
+          */
+         if (device->info->ver <= 7)
+            pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
          break;
       case VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT:
          /* We're transitioning a buffer that was previously used as render
@@ -2481,6 +2489,13 @@ struct anv_cmd_graphics_state {
 
    struct vk_sample_locations_state sample_locations;
 
+   /** Backing storage for vk_dynamic_graphics_state::vi
+    *
+    * The common runtime requires the driver to provide this whenever
+    * VK_EXT_vertex_input_dynamic_state is supported.
+    */
+   struct vk_vertex_input_state vertex_input;
+
    bool has_uint_rt;
 };
 
@@ -2541,6 +2556,11 @@ struct anv_cmd_state {
    bool                                         hiz_enabled;
 
    bool                                         conditional_render_enabled;
+   /* Gen7: buffer address + inverted flag, re-evaluated before every draw
+    * since IVB has no GPR to latch a precomputed result like Gfx7.5+ does.
+    */
+   struct anv_address                           conditional_render_value_addr;
+   bool                                         conditional_render_inverted;
 
    /**
     * Last rendering scale argument provided to
@@ -2651,6 +2671,12 @@ struct anv_cmd_buffer {
    struct {
       struct anv_video_session                  *vid;
       struct anv_video_session_params           *params;
+
+      /* ENCODE — destination for VK_QUERY_TYPE_VIDEO_ENCODE_FEEDBACK_KHR.
+       * Carried from CmdBeginQueryIndexedEXT to CmdEncodeVideoKHR, since only
+       * the encode command knows the final bitstream offset/size and does the
+       * actual write. NULL bo means no active feedback query. */
+      struct anv_address                         encode_feedback_query_addr;
    } video;
 };
 
@@ -2874,6 +2900,13 @@ struct anv_graphics_pipeline {
    bool                                         force_fragment_thread_dispatch;
    bool                                         negative_one_to_one;
 
+   /** True if VK_DYNAMIC_STATE_VERTEX_INPUT_EXT is in use.
+    *
+    * When set, vb_used and vb[] below are not filled in at pipeline-creation
+    * time; the vertex input is emitted from the command buffer instead.
+    */
+   bool                                         dynamic_vertex_input;
+
    uint32_t                                     vb_used;
    struct anv_pipeline_vertex_binding {
       uint32_t                                  stride;
@@ -3795,6 +3828,16 @@ enum {
    ANV_VID_MEM_H264_DEBLOCK_FILTER_ROW_STORE,
    ANV_VID_MEM_H264_BSD_MPC_ROW_SCRATCH,
    ANV_VID_MEM_H264_MPR_ROW_SCRATCH,
+   /* Encode-only scratch buffers (MB status, MFX_AVC_DIRECTMODE_STATE MV
+    * buffers). Exposed as separate memoryBindIndex values and bound through
+    * the same path as decode. */
+   ANV_VID_MEM_H264_ENC_MB_STATUS,
+   ANV_VID_MEM_H264_ENC_DIRECT_MV_TOP,
+   ANV_VID_MEM_H264_ENC_DIRECT_MV_BOTTOM,
+   /* Input motion-vector data read by the PAK for inter/P macroblocks
+    * (MFX_IND_OBJ_BASE_ADDR_STATE MFXIndirectMVObjectAddress). Kept separate
+    * from the DIRECTMODE write buffers so the PAK does not clobber it. */
+   ANV_VID_MEM_H264_ENC_INPUT_MV,
    ANV_VID_MEM_H264_MAX,
 };