wip: crocus/rusticl/elk/hasvk local changes before h264 cherry-pick

src/intel/vulkan_hasvk/anv_private.h

@@ -1339,6 +1339,17 @@ struct anv_batch {
 
 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
+
+/* Like anv_batch_emit_batch(), but only copies the suffix of @other
+ * starting at byte offset @skip_bytes (and only appends/rebases the
+ * relocations that fall within that suffix). Gen7-only: used to skip
+ * re-emitting a pipeline's VS-stage instruction group when it is
+ * byte-identical to what's already programmed for the previous bind
+ * (see cmd_buffer_flush_gfx_state).
+ */
+void anv_batch_emit_batch_suffix(struct anv_batch *batch,
+                                 struct anv_batch *other,
+                                 uint32_t skip_bytes);
 struct anv_address anv_batch_address(struct anv_batch *batch, void *batch_location);
 
 static inline void
@@ -2399,6 +2410,30 @@ struct anv_cmd_graphics_state {
 
    struct anv_graphics_pipeline *pipeline;
 
+   /** Last emitted URB configuration (Gen7 stall optimization) */
+   struct intel_urb_config                       last_urb_cfg;
+   bool                                         urb_cfg_valid;
+
+   /**
+    * Gen7 VS-stage instruction group cache. Tracks the VS/TCS/TES/GS
+    * shader binaries AND the effective URB config (see last_urb_cfg
+    * above) of the pipeline for which the group (URB + VS + HS + DS +
+    * GS, plus the PRM-mandated depth-stall PIPE_CONTROL before them) was
+    * last fully emitted into this command buffer, so a subsequent bind
+    * can skip re-emitting the whole group when both match the previous
+    * bind. Shader pointers alone are not sufficient -- URB layout also
+    * depends on l3_config. Always present (not #if-guarded) so this
+    * struct's layout doesn't depend on GFX_VER; only read/written by
+    * Gen7 code paths, inert everywhere else.
+    */
+   struct anv_shader_bin                       *vs_stage_key[4];
+   bool                                         vs_stage_key_valid;
+   /** True once a stall satisfying the PRM's VS-associated-3DSTATE rule
+    * has been emitted for the *current* draw's pipeline flush. Used to
+    * decide whether a later VS-descriptor/push-constant update still
+    * needs its own stall (see cmd_buffer_flush_gfx_state). */
+   bool                                         vs_stage_stall_emitted;
+
    VkRenderingFlags rendering_flags;
    VkRect2D render_area;
    uint32_t layer_count;
@@ -2790,6 +2825,22 @@ struct anv_pipeline {
 struct anv_graphics_pipeline {
    struct anv_pipeline                          base;
 
+   /* URB configuration computed at pipeline creation time.
+    * Used to skip redundant URB re-emission and PIPE_CONTROL stalls on Gen7.
+    */
+   struct intel_urb_config                       urb_cfg;
+
+   /* Byte length, from the start of base.batch, of the VS-stage
+    * instruction group (3DSTATE_URB_* + 3DSTATE_VS + 3DSTATE_HS +
+    * 3DSTATE_DS + 3DSTATE_GS, plus the PRM-mandated depth-stall
+    * PIPE_CONTROL emitted just before them). Computed unconditionally in
+    * genX(graphics_pipeline_emit) so this struct's layout doesn't depend
+    * on GFX_VER; only meaningful/consumed on Gen7 (0 elsewhere, since the
+    * reordering that makes the group a contiguous prefix of base.batch
+    * only happens for GFX_VER <= 7).
+    */
+   uint32_t                                     vs_stage_batch_size;
+
    /* Shaders */
    struct anv_shader_bin *                      shaders[ANV_GRAPHICS_SHADER_STAGE_COUNT];