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src/.clang-format
+354
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@@ -0,0 +1,354 @@
AlignAfterOpenBracket: Align
AlignConsecutiveMacros: Consecutive
AllowAllArgumentsOnNextLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: None
AlwaysBreakAfterReturnType: TopLevelDefinitions
BraceWrapping:
AfterControlStatement: Never
AfterEnum: false
AfterFunction: true
AfterStruct: false
BeforeElse: false
SplitEmptyFunction: true
BinPackArguments: true
BinPackParameters: true
BreakBeforeBraces: Custom
ColumnLimit: 0
PenaltyBreakBeforeFirstCallParameter: 1
PenaltyExcessCharacter: 100
ContinuationIndentWidth: 3
IndentWidth: 3
UseTab: Never
Cpp11BracedListStyle: true
SpaceAfterCStyleCast: false
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: false
SpacesInContainerLiterals: false
PointerAlignment: Right
IncludeBlocks: Preserve
IncludeCategories:
- Regex: '<[[:alnum:].]+>'
Priority: 1
- Regex: '.*\/.*'
Priority: 2
- Regex: '.*'
Priority: 3
ForEachMacros:
# There is no way to extend ForEachMacros
# The issue tracker https://github.com/llvm/llvm-project/issues/84359
# util
- u_foreach_bit
- u_foreach_bit64
- u_vector_foreach
- BITSET_FOREACH_SET
- BITSET_FOREACH_RANGE
- hash_table_foreach
- hash_table_foreach_remove
- hash_table_u64_foreach
- rb_tree_foreach
- rb_tree_foreach_rev
- rb_tree_foreach_rev_safe
- rb_tree_foreach_safe
- uinterval_tree_foreach
- set_foreach
- set_foreach_remove
- util_dynarray_foreach
- util_dynarray_foreach_reverse
- util_idalloc_foreach
- LIST_FOR_EACH_ENTRY
- LIST_FOR_EACH_ENTRY_FROM
- LIST_FOR_EACH_ENTRY_FROM_REV
- LIST_FOR_EACH_ENTRY_SAFE
- LIST_FOR_EACH_ENTRY_SAFE_REV
- list_for_each_entry
- list_for_each_entry_from
- list_for_each_entry_from_rev
- list_for_each_entry_from_safe
- list_for_each_entry_rev
- list_for_each_entry_rev_safe
- list_for_each_entry_safe
- list_pair_for_each_entry
- foreach_in_list
- foreach_in_list_reverse
- foreach_in_list_reverse_safe
- foreach_in_list_safe
- foreach_in_list_use_after
- foreach_list_typed
- foreach_list_typed_from
- foreach_list_typed_reverse
- foreach_list_typed_reverse_safe
- foreach_list_typed_safe
- foreach_two_lists
- U_SPARSE_BITSET_FOREACH_SET
# nir
- nir_foreach_function_temp_variable
- nir_foreach_function_temp_variable_safe
- nir_foreach_image_variable
- nir_foreach_image_variable_safe
- nir_foreach_shader_in_variable
- nir_foreach_shader_in_variable_safe
- nir_foreach_shader_out_variable
- nir_foreach_shader_out_variable_safe
- nir_foreach_uniform_variable
- nir_foreach_uniform_variable_safe
- nir_foreach_variable
- nir_foreach_variable_in_list
- nir_foreach_variable_in_list_safe
- nir_foreach_variable_in_shader
- nir_foreach_variable_in_shader_safe
- nir_foreach_variable_safe
- nir_foreach_variable_with_modes
- nir_foreach_variable_with_modes_safe
- nir_foreach_reg_decl
- nir_foreach_reg_decl_safe
- nir_foreach_reg_load
- nir_foreach_reg_load_safe
- nir_foreach_reg_store
- nir_foreach_reg_store_safe
- nir_foreach_if_use
- nir_foreach_if_use_safe
- nir_foreach_use
- nir_foreach_use_including_if
- nir_foreach_use_including_if_safe
- nir_foreach_use_safe
- nir_foreach_phi_src
- nir_foreach_phi_src_safe
- nir_foreach_parallel_copy_entry
- nir_foreach_instr
- nir_foreach_instr_in_worklist
- nir_foreach_instr_reverse
- nir_foreach_instr_reverse_safe
- nir_foreach_instr_safe
- nir_foreach_phi
- nir_foreach_phi_safe
- nir_foreach_function
- nir_foreach_function_safe
- nir_foreach_function_with_impl
- nir_foreach_function_impl
- nir_foreach_entrypoint
- nir_foreach_entrypoint_safe
- nir_foreach_block_unstructured
- nir_foreach_block_unstructured_safe
- nir_foreach_block
- nir_foreach_block_in_cf_node
- nir_foreach_block_in_cf_node_reverse
- nir_foreach_block_reverse
- nir_foreach_block_reverse_safe
- nir_foreach_block_safe
- nir_foreach_pred
- nir_precomp_foreach_arg
- nir_precomp_foreach_variant_param
- foreach_pair
# egl
- egl_relax
# wayland
- wl_list_for_each
- wl_list_for_each_safe
- wl_list_for_each_reverse
- wl_list_for_each_reverse_safe
- wl_array_for_each
# vulkan
- vk_foreach_queue
- vk_foreach_queue_safe
- vk_foreach_struct
- vk_foreach_struct_const
- vk_foreach_multi_draw
- vk_foreach_multi_draw_indexed
# asahi
- foreach_active
- foreach_submitted
- hk_foreach_view
- hk_foreach_variant
- AGX_BATCH_FOREACH_BO_HANDLE
- agx_pack
- agx_push
- agx_usc_pack
- agx_ppp_push
- agx_ppp_push_merged
- agx_foreach_block
- agx_foreach_block_safe
- agx_foreach_block_from
- agx_foreach_block_from_rev
- agx_foreach_block_rev
- agx_foreach_dest
- agx_foreach_dest_rev
- agx_foreach_instr_global
- agx_foreach_instr_global_rev
- agx_foreach_instr_global_safe
- agx_foreach_instr_global_safe_rev
- agx_foreach_instr_in_block
- agx_foreach_instr_in_block_from
- agx_foreach_instr_in_block_from_rev
- agx_foreach_instr_in_block_rev
- agx_foreach_instr_in_block_safe
- agx_foreach_instr_in_block_safe_rev
- agx_foreach_non_phi_in_block_rev
- agx_foreach_phi_in_block
- agx_foreach_phi_in_block_safe
- agx_foreach_predecessor
- agx_foreach_src
- agx_foreach_src_rev
- agx_foreach_ssa_dest
- agx_foreach_ssa_dest_rev
- agx_foreach_ssa_src
- agx_foreach_ssa_src_rev
- agx_foreach_reg_src
- agx_foreach_reg_dest
- agx_foreach_successor
- foreach_next_use
# poly
- poly_foreach_xfb
# radv
- PHASE
- radv_foreach_stage
# freedreno
- ir2_foreach_instr
- ir2_foreach_live_reg
- ir2_foreach_avail
- ir2_foreach_src
- foreach_batch
- perf_time
- perf_time_ctx
- foreach_sched_node
- foreach_src
- foreach_src_n
- foreach_src_if
- foreach_src_with_alias_n
- foreach_src_in_alias_group_n
- foreach_src_in_alias_group
- foreach_dst
- foreach_dst_n
- foreach_dst_if
- ra_foreach_dst
- ra_foreach_src
- ra_foreach_src_rev
- foreach_ssa_use
- foreach_ssa_srcp_n
- foreach_ssa_srcp
- foreach_ssa_src_n
- foreach_ssa_src
- foreach_input_n
- foreach_input
- foreach_instr
- foreach_instr_rev
- foreach_instr_safe
- foreach_instr_from
- foreach_instr_from_safe
- foreach_block
- foreach_block_safe
- foreach_block_rev
- foreach_array
- foreach_array_safe
- foreach_interval
- foreach_interval_safe
- foreach_interval_rev
- foreach_interval_rev_safe
- foreach_line_in_section
- foreach_submit
- foreach_submit_safe
- foreach_instr_rpt
- foreach_instr_rpt_excl
- foreach_instr_rpt_excl_safe
- foreach_bo
- foreach_bo_safe
# intel
- jay_foreach_ssa_file
- jay_foreach_function
- jay_foreach_block
- jay_foreach_block_safe
- jay_foreach_block_rev
- jay_foreach_block_from
- jay_foreach_block_from_rev
- jay_foreach_dst
- jay_foreach_dst_index
- jay_foreach_inst_in_block
- jay_foreach_inst_in_block_rev
- jay_foreach_inst_in_block_safe
- jay_foreach_inst_in_block_safe_rev
- jay_foreach_inst_in_block_from
- jay_foreach_inst_in_block_from_rev
- jay_foreach_inst_in_shader
- jay_foreach_inst_in_shader_rev
- jay_foreach_inst_in_shader_safe
- jay_foreach_inst_in_shader_safe_rev
- jay_foreach_inst_in_func
- jay_foreach_inst_in_func_rev
- jay_foreach_inst_in_func_safe
- jay_foreach_inst_in_func_safe_rev
- jay_foreach_successor
- jay_foreach_predecessor
- jay_foreach_comp
- jay_foreach_comp_rev
- jay_foreach_src
- jay_foreach_src_rev
- jay_foreach_ssa_src
- jay_foreach_ssa_src_rev
- jay_foreach_ssa_src_comp
- jay_foreach_index
- jay_foreach_index_rev
- jay_foreach_src_index
- jay_foreach_src_index_rev
- jay_repair_foreach_phi
- jay_foreach_phi_src_in_block
- jay_foreach_phi_dst_in_block
- jay_foreach_preload
- jay_foreach_killed
- jay_foreach_ra_src
- jay_foreach_ra_file
- jay_foreach_pipe
# Disable clang formatting by default. Drivers that use clang-format
# inherit from this .clang-format file and re-enable formatting:
#
# DisableFormat: false
#
DisableFormat: true
src/amd/addrlib/inc/addrinterface.h
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src/amd/addrlib/inc/addrtypes.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2026 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
****************************************************************************************************
* @file addrtypes.h
* @brief Contains the helper function and constants
****************************************************************************************************
*/
#ifndef __ADDR_TYPES_H__
#define __ADDR_TYPES_H__
#if defined(__APPLE__) && !defined(HAVE_TSERVER)
// External definitions header maintained by Apple driver team, but not for diag team under Mac.
// Helps address compilation issues & reduces code covered by NDA
#include "addrExtDef.h"
#else
// Windows and/or Linux
#if !defined(VOID)
typedef void VOID;
#endif
#if !defined(FLOAT)
typedef float FLOAT;
#endif
#if !defined(DOUBLE)
typedef double DOUBLE;
#endif
#if !defined(CHAR)
typedef char CHAR;
#endif
#if !defined(INT)
typedef int INT;
#endif
#include <stdarg.h> // va_list...etc need this header
#endif // defined (__APPLE__) && !defined(HAVE_TSERVER)
/**
****************************************************************************************************
* Calling conventions
****************************************************************************************************
*/
#ifndef ADDR_CDECL
#if defined(__GNUC__)
#if defined(__i386__)
#define ADDR_CDECL __attribute__((cdecl))
#else
#define ADDR_CDECL
#endif
#else
#define ADDR_CDECL __cdecl
#endif
#endif
#ifndef ADDR_STDCALL
#if defined(__GNUC__)
#if defined(__i386__)
#define ADDR_STDCALL __attribute__((stdcall))
#else
#define ADDR_STDCALL
#endif
#else
#define ADDR_STDCALL __stdcall
#endif
#endif
#ifndef ADDR_FASTCALL
#if defined(__GNUC__)
#if defined(__i386__) || defined(__amd64__) || defined(__x86_64__)
#define ADDR_FASTCALL __attribute__((regparm(0)))
#else
#define ADDR_FASTCALL
#endif
#else
#define ADDR_FASTCALL __fastcall
#endif
#endif
#ifndef GC_CDECL
#define GC_CDECL ADDR_CDECL
#endif
#ifndef GC_STDCALL
#define GC_STDCALL ADDR_STDCALL
#endif
#ifndef GC_FASTCALL
#define GC_FASTCALL ADDR_FASTCALL
#endif
#if defined(__GNUC__)
#define ADDR_INLINE static inline // inline needs to be static to link
#else
// win32, win64, other platforms
#define ADDR_INLINE __inline
#endif // #if defined(__GNUC__)
#define ADDR_API ADDR_FASTCALL //default call convention is fast call
/**
****************************************************************************************************
* Global defines used by other modules
****************************************************************************************************
*/
#if !defined(TILEINDEX_INVALID)
#define TILEINDEX_INVALID -1
#endif
#if !defined(TILEINDEX_LINEAR_GENERAL)
#define TILEINDEX_LINEAR_GENERAL -2
#endif
#if !defined(TILEINDEX_LINEAR_ALIGNED)
#define TILEINDEX_LINEAR_ALIGNED 8
#endif
/**
****************************************************************************************************
* Return codes
****************************************************************************************************
*/
typedef enum _ADDR_E_RETURNCODE
{
// General Return
ADDR_OK = 0,
ADDR_ERROR = 1,
// Specific Errors
ADDR_OUTOFMEMORY,
ADDR_INVALIDPARAMS,
ADDR_NOTSUPPORTED,
ADDR_NOTIMPLEMENTED,
ADDR_PARAMSIZEMISMATCH,
ADDR_INVALIDGBREGVALUES,
} ADDR_E_RETURNCODE;
/**
****************************************************************************************************
* @brief
* Neutral enums that define tile modes for all H/W
* @note
* R600/R800 tiling mode can be cast to hw enums directly but never cast into HW enum from
* ADDR_TM_2D_TILED_XTHICK
*
****************************************************************************************************
*/
typedef enum _AddrTileMode
{
ADDR_TM_LINEAR_GENERAL = 0, ///< Least restrictions, pitch: multiple of 8 if not buffer
ADDR_TM_LINEAR_ALIGNED = 1, ///< Requests pitch or slice to be multiple of 64 pixels
ADDR_TM_1D_TILED_THIN1 = 2, ///< Linear array of 8x8 tiles
ADDR_TM_1D_TILED_THICK = 3, ///< Linear array of 8x8x4 tiles
ADDR_TM_2D_TILED_THIN1 = 4, ///< A set of macro tiles consist of 8x8 tiles
ADDR_TM_2D_TILED_THIN2 = 5, ///< 600 HWL only, macro tile ratio is 1:4
ADDR_TM_2D_TILED_THIN4 = 6, ///< 600 HWL only, macro tile ratio is 1:16
ADDR_TM_2D_TILED_THICK = 7, ///< A set of macro tiles consist of 8x8x4 tiles
ADDR_TM_2B_TILED_THIN1 = 8, ///< 600 HWL only, with bank swap
ADDR_TM_2B_TILED_THIN2 = 9, ///< 600 HWL only, with bank swap and ratio is 1:4
ADDR_TM_2B_TILED_THIN4 = 10, ///< 600 HWL only, with bank swap and ratio is 1:16
ADDR_TM_2B_TILED_THICK = 11, ///< 600 HWL only, with bank swap, consists of 8x8x4 tiles
ADDR_TM_3D_TILED_THIN1 = 12, ///< Macro tiling w/ pipe rotation between slices
ADDR_TM_3D_TILED_THICK = 13, ///< Macro tiling w/ pipe rotation bwtween slices, thick
ADDR_TM_3B_TILED_THIN1 = 14, ///< 600 HWL only, with bank swap
ADDR_TM_3B_TILED_THICK = 15, ///< 600 HWL only, with bank swap, thick
ADDR_TM_2D_TILED_XTHICK = 16, ///< Tile is 8x8x8, valid from NI
ADDR_TM_3D_TILED_XTHICK = 17, ///< Tile is 8x8x8, valid from NI
ADDR_TM_POWER_SAVE = 18, ///< Power save mode, only used by KMD on NI
ADDR_TM_PRT_TILED_THIN1 = 19, ///< No bank/pipe rotation or hashing beyond macrotile size
ADDR_TM_PRT_2D_TILED_THIN1 = 20, ///< Same as 2D_TILED_THIN1, PRT only
ADDR_TM_PRT_3D_TILED_THIN1 = 21, ///< Same as 3D_TILED_THIN1, PRT only
ADDR_TM_PRT_TILED_THICK = 22, ///< No bank/pipe rotation or hashing beyond macrotile size
ADDR_TM_PRT_2D_TILED_THICK = 23, ///< Same as 2D_TILED_THICK, PRT only
ADDR_TM_PRT_3D_TILED_THICK = 24, ///< Same as 3D_TILED_THICK, PRT only
ADDR_TM_UNKNOWN = 25, ///< Unkown tile mode, should be decided by address lib
ADDR_TM_COUNT = 26, ///< Must be the value of the last tile mode
} AddrTileMode;
/**
****************************************************************************************************
* @brief
* Neutral enums that define swizzle modes for Gfx9+ ASIC
* @note
*
* ADDR_SW_LINEAR linear aligned addressing mode, for 1D/2D/3D resource
* ADDR_SW_256B_* addressing block aligned size is 256B, for 2D resource
* ADDR_SW_4KB_* addressing block aligned size is 4KB, for 2D/3D resource
* ADDR_SW_64KB_* addressing block aligned size is 64KB, for 1D/2D/3D resource
* ADDR_SW_VAR_* addressing block aligned size is ASIC specific
*
* ADDR_SW_*_Z For GFX9:
- for 2D resource, represents Z-order swizzle mode for depth/stencil/FMask
- for 3D resource, represents a swizzle mode similar to legacy thick tile mode
For GFX10:
- represents Z-order swizzle mode for depth/stencil/FMask
* ADDR_SW_*_S For GFX9+:
- represents standard swizzle mode defined by MS
* ADDR_SW_*_D For GFX9:
- for 2D resource, represents a swizzle mode for displayable resource
* - for 3D resource, represents a swizzle mode which places each slice in order & pixel
For GFX10:
- for 2D resource, represents a swizzle mode for displayable resource
- for 3D resource, represents a swizzle mode similar to legacy thick tile mode
within slice is placed as 2D ADDR_SW_*_S. Don't use this combination if possible!
* ADDR_SW_*_R For GFX9:
- 2D resource only, represents a swizzle mode for rotated displayable resource
For GFX10:
- represents a swizzle mode for render target resource
*
****************************************************************************************************
*/
typedef enum _AddrSwizzleMode
{
ADDR_SW_LINEAR = 0,
ADDR_SW_256B_S = 1,
ADDR_SW_256B_D = 2,
ADDR_SW_256B_R = 3,
ADDR_SW_4KB_Z = 4,
ADDR_SW_4KB_S = 5,
ADDR_SW_4KB_D = 6,
ADDR_SW_4KB_R = 7,
ADDR_SW_64KB_Z = 8,
ADDR_SW_64KB_S = 9,
ADDR_SW_64KB_D = 10,
ADDR_SW_64KB_R = 11,
ADDR_SW_MISCDEF12 = 12,
ADDR_SW_MISCDEF13 = 13,
ADDR_SW_MISCDEF14 = 14,
ADDR_SW_MISCDEF15 = 15,
ADDR_SW_64KB_Z_T = 16,
ADDR_SW_64KB_S_T = 17,
ADDR_SW_64KB_D_T = 18,
ADDR_SW_64KB_R_T = 19,
ADDR_SW_4KB_Z_X = 20,
ADDR_SW_4KB_S_X = 21,
ADDR_SW_4KB_D_X = 22,
ADDR_SW_4KB_R_X = 23,
ADDR_SW_64KB_Z_X = 24,
ADDR_SW_64KB_S_X = 25,
ADDR_SW_64KB_D_X = 26,
ADDR_SW_64KB_R_X = 27,
ADDR_SW_MISCDEF28 = 28,
ADDR_SW_MISCDEF29 = 29,
ADDR_SW_MISCDEF30 = 30,
ADDR_SW_MISCDEF31 = 31,
ADDR_SW_LINEAR_GENERAL = 32,
ADDR_SW_MAX_TYPE = 33,
ADDR_SW_RESERVED0 = ADDR_SW_MISCDEF12,
ADDR_SW_RESERVED1 = ADDR_SW_MISCDEF13,
ADDR_SW_RESERVED2 = ADDR_SW_MISCDEF14,
ADDR_SW_RESERVED3 = ADDR_SW_MISCDEF15,
ADDR_SW_RESERVED4 = ADDR_SW_MISCDEF29,
ADDR_SW_RESERVED5 = ADDR_SW_MISCDEF30,
ADDR_SW_VAR_Z_X = ADDR_SW_MISCDEF28,
ADDR_SW_VAR_R_X = ADDR_SW_MISCDEF31,
ADDR_SW_256KB_Z_X = ADDR_SW_MISCDEF28,
ADDR_SW_256KB_S_X = ADDR_SW_MISCDEF29,
ADDR_SW_256KB_D_X = ADDR_SW_MISCDEF30,
ADDR_SW_256KB_R_X = ADDR_SW_MISCDEF31,
} AddrSwizzleMode;
/**
****************************************************************************************************
* @brief
* Neutral enums that define swizzle modes for Gfx12+ ASIC
*
****************************************************************************************************
*/
typedef enum _Addr3SwizzleMode
{
ADDR3_LINEAR = 0,
ADDR3_256B_2D = 1,
ADDR3_4KB_2D = 2,
ADDR3_64KB_2D = 3,
ADDR3_256KB_2D = 4,
ADDR3_4KB_3D = 5,
ADDR3_64KB_3D = 6,
ADDR3_256KB_3D = 7,
ADDR3_MAX_TYPE,
} Addr3SwizzleMode;
/**
****************************************************************************************************
* @brief
* Neutral enums that define image type
* @note
* this is new for address library interface version 2
*
****************************************************************************************************
*/
typedef enum _AddrResourceType
{
ADDR_RSRC_TEX_1D = 0,
ADDR_RSRC_TEX_2D = 1,
ADDR_RSRC_TEX_3D = 2,
ADDR_RSRC_MAX_TYPE = 3,
} AddrResourceType;
/**
****************************************************************************************************
* @brief
* Neutral enums that define resource heap location
* @note
* this is new for address library interface version 2
*
****************************************************************************************************
*/
typedef enum _AddrResrouceLocation
{
ADDR_RSRC_LOC_UNDEF = 0, // Resource heap is undefined/unknown
ADDR_RSRC_LOC_LOCAL = 1, // CPU visable and CPU invisable local heap
ADDR_RSRC_LOC_USWC = 2, // CPU write-combined non-cached nonlocal heap
ADDR_RSRC_LOC_CACHED = 3, // CPU cached nonlocal heap
ADDR_RSRC_LOC_INVIS = 4, // CPU invisable local heap only
ADDR_RSRC_LOC_MAX_TYPE = 5,
} AddrResrouceLocation;
/**
****************************************************************************************************
* @brief
* Neutral enums that define resource basic swizzle mode
* @note
* this is new for address library interface version 2
*
****************************************************************************************************
*/
typedef enum _AddrSwType
{
ADDR_SW_Z = 0, // Resource basic swizzle mode is ZOrder
ADDR_SW_S = 1, // Resource basic swizzle mode is Standard
ADDR_SW_D = 2, // Resource basic swizzle mode is Display
ADDR_SW_R = 3, // Resource basic swizzle mode is Rotated/Render optimized
ADDR_SW_L = 4, // Resource basic swizzle mode is Linear
ADDR_SW_MAX_SWTYPE
} AddrSwType;
/**
****************************************************************************************************
* @brief
* Neutral enums that define mipmap major mode
* @note
* this is new for address library interface version 2
*
****************************************************************************************************
*/
typedef enum _AddrMajorMode
{
ADDR_MAJOR_X = 0,
ADDR_MAJOR_Y = 1,
ADDR_MAJOR_Z = 2,
ADDR_MAJOR_MAX_TYPE = 3,
} AddrMajorMode;
/**
****************************************************************************************************
* AddrFormat
*
* @brief
* Neutral enum for SurfaceFormat
*
****************************************************************************************************
*/
typedef enum _AddrFormat {
ADDR_FMT_INVALID = 0x00000000,
ADDR_FMT_8 = 0x00000001,
ADDR_FMT_4_4 = 0x00000002,
ADDR_FMT_3_3_2 = 0x00000003,
ADDR_FMT_RESERVED_4 = 0x00000004,
ADDR_FMT_16 = 0x00000005,
ADDR_FMT_16_FLOAT = ADDR_FMT_16,
ADDR_FMT_8_8 = 0x00000007,
ADDR_FMT_5_6_5 = 0x00000008,
ADDR_FMT_6_5_5 = 0x00000009,
ADDR_FMT_1_5_5_5 = 0x0000000a,
ADDR_FMT_4_4_4_4 = 0x0000000b,
ADDR_FMT_5_5_5_1 = 0x0000000c,
ADDR_FMT_32 = 0x0000000d,
ADDR_FMT_32_FLOAT = ADDR_FMT_32,
ADDR_FMT_16_16 = 0x0000000f,
ADDR_FMT_16_16_FLOAT = ADDR_FMT_16_16,
ADDR_FMT_8_24 = 0x00000011,
ADDR_FMT_8_24_FLOAT = ADDR_FMT_8_24,
ADDR_FMT_24_8 = 0x00000013,
ADDR_FMT_24_8_FLOAT = ADDR_FMT_24_8,
ADDR_FMT_10_11_11 = 0x00000015,
ADDR_FMT_10_11_11_FLOAT = ADDR_FMT_10_11_11,
ADDR_FMT_11_11_10 = 0x00000017,
ADDR_FMT_11_11_10_FLOAT = ADDR_FMT_11_11_10,
ADDR_FMT_2_10_10_10 = 0x00000019,
ADDR_FMT_8_8_8_8 = 0x0000001a,
ADDR_FMT_10_10_10_2 = 0x0000001b,
ADDR_FMT_X24_8_32_FLOAT = 0x0000001c,
ADDR_FMT_32_32 = 0x0000001d,
ADDR_FMT_32_32_FLOAT = ADDR_FMT_32_32,
ADDR_FMT_16_16_16_16 = 0x0000001f,
ADDR_FMT_16_16_16_16_FLOAT = ADDR_FMT_16_16_16_16,
ADDR_FMT_RESERVED_33 = 0x00000021,
ADDR_FMT_32_32_32_32 = 0x00000022,
ADDR_FMT_32_32_32_32_FLOAT = ADDR_FMT_32_32_32_32,
ADDR_FMT_RESERVED_36 = 0x00000024,
ADDR_FMT_1 = 0x00000025,
ADDR_FMT_1_REVERSED = 0x00000026,
ADDR_FMT_GB_GR = 0x00000027,
ADDR_FMT_BG_RG = 0x00000028,
ADDR_FMT_32_AS_8 = 0x00000029,
ADDR_FMT_32_AS_8_8 = 0x0000002a,
ADDR_FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
ADDR_FMT_8_8_8 = 0x0000002c,
ADDR_FMT_16_16_16 = 0x0000002d,
ADDR_FMT_16_16_16_FLOAT = ADDR_FMT_16_16_16,
ADDR_FMT_32_32_32 = 0x0000002f,
ADDR_FMT_32_32_32_FLOAT = ADDR_FMT_32_32_32,
ADDR_FMT_BC1 = 0x00000031,
ADDR_FMT_BC2 = 0x00000032,
ADDR_FMT_BC3 = 0x00000033,
ADDR_FMT_BC4 = 0x00000034,
ADDR_FMT_BC5 = 0x00000035,
ADDR_FMT_BC6 = 0x00000036,
ADDR_FMT_BC7 = 0x00000037,
ADDR_FMT_32_AS_32_32_32_32 = 0x00000038,
ADDR_FMT_APC3 = 0x00000039,
ADDR_FMT_APC4 = 0x0000003a,
ADDR_FMT_APC5 = 0x0000003b,
ADDR_FMT_APC6 = 0x0000003c,
ADDR_FMT_APC7 = 0x0000003d,
ADDR_FMT_CTX1 = 0x0000003e,
ADDR_FMT_RESERVED_63 = 0x0000003f,
ADDR_FMT_ASTC_4x4 = 0x00000040,
ADDR_FMT_ASTC_5x4 = 0x00000041,
ADDR_FMT_ASTC_5x5 = 0x00000042,
ADDR_FMT_ASTC_6x5 = 0x00000043,
ADDR_FMT_ASTC_6x6 = 0x00000044,
ADDR_FMT_ASTC_8x5 = 0x00000045,
ADDR_FMT_ASTC_8x6 = 0x00000046,
ADDR_FMT_ASTC_8x8 = 0x00000047,
ADDR_FMT_ASTC_10x5 = 0x00000048,
ADDR_FMT_ASTC_10x6 = 0x00000049,
ADDR_FMT_ASTC_10x8 = 0x0000004a,
ADDR_FMT_ASTC_10x10 = 0x0000004b,
ADDR_FMT_ASTC_12x10 = 0x0000004c,
ADDR_FMT_ASTC_12x12 = 0x0000004d,
ADDR_FMT_ETC2_64BPP = 0x0000004e,
ADDR_FMT_ETC2_128BPP = 0x0000004f,
ADDR_FMT_BG_RG_16_16_16_16 = 0x00000050,
} AddrFormat;
/**
****************************************************************************************************
* AddrDepthFormat
*
* @brief
* Neutral enum for addrFlt32ToDepthPixel
*
****************************************************************************************************
*/
typedef enum _AddrDepthFormat
{
ADDR_DEPTH_INVALID = 0x00000000,
ADDR_DEPTH_16 = 0x00000001,
ADDR_DEPTH_X8_24 = 0x00000002,
ADDR_DEPTH_8_24 = 0x00000003,
ADDR_DEPTH_X8_24_FLOAT = 0x00000004,
ADDR_DEPTH_8_24_FLOAT = 0x00000005,
ADDR_DEPTH_32_FLOAT = 0x00000006,
ADDR_DEPTH_X24_8_32_FLOAT = 0x00000007,
} AddrDepthFormat;
/**
****************************************************************************************************
* AddrColorFormat
*
* @brief
* Neutral enum for ColorFormat
*
****************************************************************************************************
*/
typedef enum _AddrColorFormat
{
ADDR_COLOR_INVALID = 0x00000000,
ADDR_COLOR_8 = 0x00000001,
ADDR_COLOR_4_4 = 0x00000002,
ADDR_COLOR_3_3_2 = 0x00000003,
ADDR_COLOR_RESERVED_4 = 0x00000004,
ADDR_COLOR_16 = 0x00000005,
ADDR_COLOR_16_FLOAT = 0x00000006,
ADDR_COLOR_8_8 = 0x00000007,
ADDR_COLOR_5_6_5 = 0x00000008,
ADDR_COLOR_6_5_5 = 0x00000009,
ADDR_COLOR_1_5_5_5 = 0x0000000a,
ADDR_COLOR_4_4_4_4 = 0x0000000b,
ADDR_COLOR_5_5_5_1 = 0x0000000c,
ADDR_COLOR_32 = 0x0000000d,
ADDR_COLOR_32_FLOAT = 0x0000000e,
ADDR_COLOR_16_16 = 0x0000000f,
ADDR_COLOR_16_16_FLOAT = 0x00000010,
ADDR_COLOR_8_24 = 0x00000011,
ADDR_COLOR_8_24_FLOAT = 0x00000012,
ADDR_COLOR_24_8 = 0x00000013,
ADDR_COLOR_24_8_FLOAT = 0x00000014,
ADDR_COLOR_10_11_11 = 0x00000015,
ADDR_COLOR_10_11_11_FLOAT = 0x00000016,
ADDR_COLOR_11_11_10 = 0x00000017,
ADDR_COLOR_11_11_10_FLOAT = 0x00000018,
ADDR_COLOR_2_10_10_10 = 0x00000019,
ADDR_COLOR_8_8_8_8 = 0x0000001a,
ADDR_COLOR_10_10_10_2 = 0x0000001b,
ADDR_COLOR_X24_8_32_FLOAT = 0x0000001c,
ADDR_COLOR_32_32 = 0x0000001d,
ADDR_COLOR_32_32_FLOAT = 0x0000001e,
ADDR_COLOR_16_16_16_16 = 0x0000001f,
ADDR_COLOR_16_16_16_16_FLOAT = 0x00000020,
ADDR_COLOR_RESERVED_33 = 0x00000021,
ADDR_COLOR_32_32_32_32 = 0x00000022,
ADDR_COLOR_32_32_32_32_FLOAT = 0x00000023,
} AddrColorFormat;
/**
****************************************************************************************************
* AddrSurfaceNumber
*
* @brief
* Neutral enum for SurfaceNumber
*
****************************************************************************************************
*/
typedef enum _AddrSurfaceNumber {
ADDR_NUMBER_UNORM = 0x00000000,
ADDR_NUMBER_SNORM = 0x00000001,
ADDR_NUMBER_USCALED = 0x00000002,
ADDR_NUMBER_SSCALED = 0x00000003,
ADDR_NUMBER_UINT = 0x00000004,
ADDR_NUMBER_SINT = 0x00000005,
ADDR_NUMBER_SRGB = 0x00000006,
ADDR_NUMBER_FLOAT = 0x00000007,
} AddrSurfaceNumber;
/**
****************************************************************************************************
* AddrSurfaceSwap
*
* @brief
* Neutral enum for SurfaceSwap
*
****************************************************************************************************
*/
typedef enum _AddrSurfaceSwap {
ADDR_SWAP_STD = 0x00000000,
ADDR_SWAP_ALT = 0x00000001,
ADDR_SWAP_STD_REV = 0x00000002,
ADDR_SWAP_ALT_REV = 0x00000003,
} AddrSurfaceSwap;
/**
****************************************************************************************************
* AddrHtileBlockSize
*
* @brief
* Size of HTILE blocks, valid values are 4 or 8 for now
****************************************************************************************************
*/
typedef enum _AddrHtileBlockSize
{
ADDR_HTILE_BLOCKSIZE_4 = 4,
ADDR_HTILE_BLOCKSIZE_8 = 8,
} AddrHtileBlockSize;
/**
****************************************************************************************************
* AddrPipeCfg
*
* @brief
* The pipe configuration field specifies both the number of pipes and
* how pipes are interleaved on the surface.
* The expression of number of pipes, the shader engine tile size, and packer tile size
* is encoded in a PIPE_CONFIG register field.
* In general the number of pipes usually matches the number of memory channels of the
* hardware configuration.
* For hw configurations w/ non-pow2 memory number of memory channels, it usually matches
* the number of ROP units(? TODO: which registers??)
* The enum value = hw enum + 1 which is to reserve 0 for requesting default.
****************************************************************************************************
*/
typedef enum _AddrPipeCfg
{
ADDR_PIPECFG_INVALID = 0,
ADDR_PIPECFG_P2 = 1, /// 2 pipes,
ADDR_PIPECFG_P4_8x16 = 5, /// 4 pipes,
ADDR_PIPECFG_P4_16x16 = 6,
ADDR_PIPECFG_P4_16x32 = 7,
ADDR_PIPECFG_P4_32x32 = 8,
ADDR_PIPECFG_P8_16x16_8x16 = 9, /// 8 pipes
ADDR_PIPECFG_P8_16x32_8x16 = 10,
ADDR_PIPECFG_P8_32x32_8x16 = 11,
ADDR_PIPECFG_P8_16x32_16x16 = 12,
ADDR_PIPECFG_P8_32x32_16x16 = 13,
ADDR_PIPECFG_P8_32x32_16x32 = 14,
ADDR_PIPECFG_P8_32x64_32x32 = 15,
ADDR_PIPECFG_P16_32x32_8x16 = 17, /// 16 pipes
ADDR_PIPECFG_P16_32x32_16x16 = 18,
ADDR_PIPECFG_UNUSED = 19,
ADDR_PIPECFG_MAX = 20,
} AddrPipeCfg;
/**
****************************************************************************************************
* AddrTileType
*
* @brief
* Neutral enums that specifies micro tile type (MICRO_TILE_MODE)
****************************************************************************************************
*/
typedef enum _AddrTileType
{
ADDR_DISPLAYABLE = 0, ///< Displayable tiling
ADDR_NON_DISPLAYABLE = 1, ///< Non-displayable tiling, a.k.a thin micro tiling
ADDR_DEPTH_SAMPLE_ORDER = 2, ///< Same as non-displayable plus depth-sample-order
ADDR_ROTATED = 3, ///< Rotated displayable tiling
ADDR_THICK = 4, ///< Thick micro-tiling, only valid for THICK and XTHICK
} AddrTileType;
////////////////////////////////////////////////////////////////////////////////////////////////////
//
// Type definitions: short system-independent names for address library types
//
////////////////////////////////////////////////////////////////////////////////////////////////////
#if !defined(__APPLE__) || defined(HAVE_TSERVER)
#ifndef BOOL_32 // no bool type in C
/// @brief Boolean type, since none is defined in C
/// @ingroup type
#define BOOL_32 int
#endif
#ifndef INT_32
#define INT_32 int
#endif
#ifndef UINT_32
#define UINT_32 unsigned int
#endif
#ifndef INT_16
#define INT_16 short
#endif
#ifndef UINT_16
#define UINT_16 unsigned short
#endif
#ifndef INT_8
#define INT_8 signed char // signed must be used because of aarch64
#endif
#ifndef UINT_8
#define UINT_8 unsigned char
#endif
#ifndef NULL
#define NULL 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
//
// 64-bit integer types depend on the compiler
//
#if defined( __GNUC__ ) || defined( __WATCOMC__ )
#define INT_64 long long
#define UINT_64 unsigned long long
#elif defined( _WIN32 )
#define INT_64 __int64
#define UINT_64 unsigned __int64
#else
#error Unsupported compiler and/or operating system for 64-bit integers
/// @brief 64-bit signed integer type (compiler dependent)
/// @ingroup type
///
/// The addrlib defines a 64-bit signed integer type for either
/// Gnu/Watcom compilers (which use the first syntax) or for
/// the Windows VCC compiler (which uses the second syntax).
#define INT_64 long long OR __int64
/// @brief 64-bit unsigned integer type (compiler dependent)
/// @ingroup type
///
/// The addrlib defines a 64-bit unsigned integer type for either
/// Gnu/Watcom compilers (which use the first syntax) or for
/// the Windows VCC compiler (which uses the second syntax).
///
#define UINT_64 unsigned long long OR unsigned __int64
#endif
#endif // #if !defined(__APPLE__) || defined(HAVE_TSERVER)
// ADDR64X is used to print addresses in hex form on both Windows and Linux
//
#if defined( __GNUC__ ) || defined( __WATCOMC__ )
#define ADDR64X "llx"
#define ADDR64D "lld"
#elif defined( _WIN32 )
#define ADDR64X "I64x"
#define ADDR64D "I64d"
#else
#error Unsupported compiler and/or operating system for 64-bit integers
/// @brief Addrlib device address 64-bit printf tag (compiler dependent)
/// @ingroup type
///
/// This allows printf to display an ADDR_64 for either the Windows VCC compiler
/// (which used this value) or the Gnu/Watcom compilers (which use "llx".
/// An example of use is printf("addr 0x%"ADDR64X"\n", address);
///
#define ADDR64X "llx" OR "I64x"
#define ADDR64D "lld" OR "I64d"
#endif
/// @brief Union for storing a 32-bit float or 32-bit integer
/// @ingroup type
///
/// This union provides a simple way to convert between a 32-bit float
/// and a 32-bit integer. It also prevents the compiler from producing
/// code that alters NaN values when assiging or coying floats.
/// Therefore, all address library routines that pass or return 32-bit
/// floating point data do so by passing or returning a FLT_32.
///
typedef union {
INT_32 i;
UINT_32 u;
float f;
} ADDR_FLT_32;
////////////////////////////////////////////////////////////////////////////////////////////////////
//
// Macros for controlling linking and building on multiple systems
//
////////////////////////////////////////////////////////////////////////////////////////////////////
#if defined(_MSC_VER)
#if defined(va_copy)
#undef va_copy //redefine va_copy to support VC2013
#endif
#endif
#if !defined(va_copy)
#define va_copy(dst, src) \
((void) memcpy(&(dst), &(src), sizeof(va_list)))
#endif
#endif // __ADDR_TYPES_H__
src/amd/addrlib/meson.build
+84
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@@ -0,0 +1,84 @@
# Copyright © 2017 Intel Corporation
# SPDX-License-Identifier: MIT
files_addrlib = files(
'inc/addrinterface.h',
'inc/addrtypes.h',
'src/addrinterface.cpp',
'src/core/addrcommon.h',
'src/core/addrelemlib.cpp',
'src/core/addrelemlib.h',
'src/core/addrlib.cpp',
'src/core/addrlib.h',
'src/core/addrlib1.cpp',
'src/core/addrlib1.h',
'src/core/addrlib2.cpp',
'src/core/addrlib2.h',
'src/core/addrlib3.cpp',
'src/core/addrlib3.h',
'src/core/addrobject.cpp',
'src/core/addrobject.h',
'src/core/addrswizzler.cpp',
'src/core/addrswizzler.h',
'src/core/addrswizzlersimd.h',
'src/core/coord.cpp',
'src/core/coord.h',
'src/gfx9/gfx9addrlib.cpp',
'src/gfx9/gfx9addrlib.h',
'src/gfx10/gfx10addrlib.cpp',
'src/gfx10/gfx10addrlib.h',
'src/gfx10/gfx10SwizzlePattern.h',
'src/gfx11/gfx11addrlib.cpp',
'src/gfx11/gfx11addrlib.h',
'src/gfx11/gfx11SwizzlePattern.h',
'src/gfx12/gfx12addrlib.cpp',
'src/gfx12/gfx12addrlib.h',
'src/gfx12/gfx12SwizzlePattern.h',
'src/amdgpu_asic_addr.h',
'src/chip/gfx10/gfx10_gb_reg.h',
'src/chip/gfx11/gfx11_gb_reg.h',
'src/chip/gfx12/gfx12_gb_reg.h',
'src/chip/gfx9/gfx9_gb_reg.h',
'src/chip/r800/si_gb_reg.h',
'src/r800/ciaddrlib.cpp',
'src/r800/ciaddrlib.h',
'src/r800/egbaddrlib.cpp',
'src/r800/egbaddrlib.h',
'src/r800/siaddrlib.cpp',
'src/r800/siaddrlib.h',
)
# Skip the addrlib definition of ADDR_FASTCALL so as not to use regparm.
cpp_args_addrlib = ['-DADDR_FASTCALL=', '-DADDR_ALLOW_SIMD=1']
if host_machine.endian() == 'little'
cpp_args_addrlib += '-DLITTLEENDIAN_CPU'
else
cpp_args_addrlib += '-DBIGENDIAN_CPU'
endif
if with_mesa_ndebug
cpp_args_addrlib += '-DDEBUG=0'
else
cpp_args_addrlib += '-DDEBUG=1'
endif
cpp_args_addrlib += cpp.get_supported_arguments(
['-Wno-unused-variable', '-Wno-unused-local-typedefs',
'-Wno-unused-but-set-variable', '-Wno-maybe-uninitialized',
'-Wno-self-assign', '/wd4189', '-Wno-uninitialized']
)
libamdgpu_addrlib = static_library(
'addrlib',
files_addrlib,
include_directories : [
include_directories(
'inc', 'src', 'src/core', 'src/chip/gfx9', 'src/chip/r800',
'src/chip/gfx10', 'src/chip/gfx11', 'src/chip/gfx12',
),
inc_amd_common, inc_include, inc_src
],
cpp_args : cpp_args_addrlib,
gnu_symbol_visibility : 'hidden',
)
src/amd/addrlib/src/addrinterface.cpp
+2412
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File diff suppressed because it is too large. Load diff
src/amd/addrlib/src/amdgpu_asic_addr.h
+202
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@@ -0,0 +1,202 @@
/*
************************************************************************************************************************
*
* Copyright (C) 2017-2026 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
#ifndef _AMDGPU_ASIC_ADDR_H
#define _AMDGPU_ASIC_ADDR_H
#define ATI_VENDOR_ID 0x1002
#define AMD_VENDOR_ID 0x1022
// AMDGPU_VENDOR_IS_AMD(vendorId)
#define AMDGPU_VENDOR_IS_AMD(v) ((v == ATI_VENDOR_ID) || (v == AMD_VENDOR_ID))
#define FAMILY_UNKNOWN 0x00
#define FAMILY_TN 0x69 //# 105 / Trinity APUs
#define FAMILY_SI 0x6E //# 110 / Southern Islands: Tahiti, Pitcairn, CapeVerde, Oland, Hainan
#define FAMILY_CI 0x78 //# 120 / Sea Islands: Bonaire, Hawaii
#define FAMILY_KV 0x7D //# 125 / Kaveri APUs: Spectre, Spooky, Kalindi, Godavari
#define FAMILY_VI 0x82 //# 130 / Volcanic Islands: Iceland, Tonga, Fiji
#define FAMILY_CZ 0x87 //# 135 / Carrizo APUs: Carrizo, Stoney
#define FAMILY_AI 0x8D //# 141 / Vega: 10, 20
#define FAMILY_RV 0x8E //# 142 / Raven
#define FAMILY_NV 0x8F //# 143 / Navi: 10
#define FAMILY_VGH 0x90 //# 144 / Van Gogh
#define FAMILY_NV3 0x91 //# 145 / Navi: 3x
#define FAMILY_STX 0x96
#define FAMILY_PHX 0x94 //# 148 / Phoenix
#define FAMILY_GFX1170 0x9A
#define FAMILY_RMB 0x92 //# 146 / Rembrandt
#define FAMILY_RPL 0x95 //# 149 / Raphael
#define FAMILY_MDN 0x97 //# 151 / Mendocino
#define FAMILY_NV4 0x98
// AMDGPU_FAMILY_IS(familyId, familyName)
#define FAMILY_IS(f, fn) (f == FAMILY_##fn)
#define FAMILY_IS_TN(f) FAMILY_IS(f, TN)
#define FAMILY_IS_SI(f) FAMILY_IS(f, SI)
#define FAMILY_IS_CI(f) FAMILY_IS(f, CI)
#define FAMILY_IS_KV(f) FAMILY_IS(f, KV)
#define FAMILY_IS_VI(f) FAMILY_IS(f, VI)
#define FAMILY_IS_POLARIS(f) FAMILY_IS(f, POLARIS)
#define FAMILY_IS_CZ(f) FAMILY_IS(f, CZ)
#define FAMILY_IS_AI(f) FAMILY_IS(f, AI)
#define FAMILY_IS_RV(f) FAMILY_IS(f, RV)
#define FAMILY_IS_NV(f) FAMILY_IS(f, NV)
#define FAMILY_IS_RMB(f) FAMILY_IS(f, RMB)
#define FAMILY_IS_NV3(f) FAMILY_IS(f, NV3)
#define FAMILY_IS_GFX12(f) FAMILY_IS(f, GFX12)
#define AMDGPU_UNKNOWN 0xFF
#define AMDGPU_TAHITI_RANGE 0x05, 0x14 //# 5 <= x < 20
#define AMDGPU_PITCAIRN_RANGE 0x15, 0x28 //# 21 <= x < 40
#define AMDGPU_CAPEVERDE_RANGE 0x29, 0x3C //# 41 <= x < 60
#define AMDGPU_OLAND_RANGE 0x3C, 0x46 //# 60 <= x < 70
#define AMDGPU_HAINAN_RANGE 0x46, 0xFF //# 70 <= x < max
#define AMDGPU_BONAIRE_RANGE 0x14, 0x28 //# 20 <= x < 40
#define AMDGPU_HAWAII_RANGE 0x28, 0x3C //# 40 <= x < 60
#define AMDGPU_SPECTRE_RANGE 0x01, 0x41 //# 1 <= x < 65
#define AMDGPU_SPOOKY_RANGE 0x41, 0x81 //# 65 <= x < 129
#define AMDGPU_KALINDI_RANGE 0x81, 0xA1 //# 129 <= x < 161
#define AMDGPU_GODAVARI_RANGE 0xA1, 0xFF //# 161 <= x < max
#define AMDGPU_ICELAND_RANGE 0x01, 0x14 //# 1 <= x < 20
#define AMDGPU_TONGA_RANGE 0x14, 0x28 //# 20 <= x < 40
#define AMDGPU_FIJI_RANGE 0x3C, 0x50 //# 60 <= x < 80
#define AMDGPU_POLARIS10_RANGE 0x50, 0x5A //# 80 <= x < 90
#define AMDGPU_POLARIS11_RANGE 0x5A, 0x64 //# 90 <= x < 100
#define AMDGPU_POLARIS12_RANGE 0x64, 0x6E //# 100 <= x < 110
#define AMDGPU_VEGAM_RANGE 0x6E, 0xFF //# 110 <= x < max
#define AMDGPU_CARRIZO_RANGE 0x01, 0x21 //# 1 <= x < 33
#define AMDGPU_BRISTOL_RANGE 0x10, 0x21 //# 16 <= x < 33
#define AMDGPU_STONEY_RANGE 0x61, 0xFF //# 97 <= x < max
#define AMDGPU_VEGA10_RANGE 0x01, 0x14 //# 1 <= x < 20
#define AMDGPU_VEGA12_RANGE 0x14, 0x28 //# 20 <= x < 40
#define AMDGPU_VEGA20_RANGE 0x28, 0x31 //# 40 <= x < 49
#define AMDGPU_RAVEN_RANGE 0x01, 0x81 //# 1 <= x < 129
#define AMDGPU_RAVEN2_RANGE 0x81, 0x90 //# 129 <= x < 144
#define AMDGPU_RENOIR_RANGE 0x91, 0xFF //# 145 <= x < max
#define AMDGPU_NAVI10_RANGE 0x01, 0x0A //# 1 <= x < 10
#define AMDGPU_NAVI12_RANGE 0x0A, 0x14 //# 10 <= x < 20
#define AMDGPU_NAVI14_RANGE 0x14, 0x28 //# 20 <= x < 40
#define AMDGPU_GFX1013_RANGE 0x82, 0x86 //# 130 <= x < 134
#define AMDGPU_NAVI21_RANGE 0x28, 0x32 //# 40 <= x < 50
#define AMDGPU_NAVI22_RANGE 0x32, 0x3C //# 50 <= x < 60
#define AMDGPU_NAVI23_RANGE 0x3C, 0x46 //# 60 <= x < 70
#define AMDGPU_NAVI24_RANGE 0x46, 0x50 //# 70 <= x < 80
#define AMDGPU_VANGOGH_RANGE 0x01, 0xFF //# 1 <= x < max
#define AMDGPU_NAVI31_RANGE 0x01, 0x10 //# 01 <= x < 16
#define AMDGPU_NAVI32_RANGE 0x20, 0xFF //# 32 <= x < 255
#define AMDGPU_NAVI33_RANGE 0x10, 0x20 //# 16 <= x < 32
#define AMDGPU_STRIX1_RANGE 0x01, 0x40 //# 1 <= x < 64
#define AMDGPU_STRIX_HALO_RANGE 0xC0, 0xFF //# 192 <= x < 255
#define AMDGPU_KRACKAN1_RANGE 0x40, 0x50 //# 64 <= x < 80
#define AMDGPU_GFX1153_RANGE 0x50, 0xC0 //# 80 <= x < 192
#define AMDGPU_PHOENIX1_RANGE 0x01, 0x80 //# 1 <= x < 128
#define AMDGPU_PHOENIX2_RANGE 0x80, 0xC0 //# 128 <= x < 192
#define AMDGPU_HAWK_POINT1_RANGE 0xC0, 0xF0 //# 192 <= x < 240
#define AMDGPU_HAWK_POINT2_RANGE 0xF0, 0xFF //# 240 <= x < 255
#define AMDGPU_GFX1170_RANGE 0x01, 0x40 //# 1 <= x < 64
#define AMDGPU_REMBRANDT_RANGE 0x01, 0xFF //# 01 <= x < 255
#define AMDGPU_RAPHAEL_RANGE 0x01, 0xFF //# 1 <= x < max
#define AMDGPU_MENDOCINO_RANGE 0x01, 0xFF //# 1 <= x < max
#define AMDGPU_GFX1200_RANGE 0x40, 0x50
#define AMDGPU_GFX1201_RANGE 0x50, 0xFF
#define AMDGPU_EXPAND_FIX(x) x
#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
#define AMDGPU_IN_RANGE(val, ...) AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
// ASICREV_IS(eRevisionId, revisionName)
#define ASICREV_IS(r, rn) AMDGPU_IN_RANGE(r, AMDGPU_##rn##_RANGE)
#define ASICREV_IS_TAHITI_P(r) ASICREV_IS(r, TAHITI)
#define ASICREV_IS_PITCAIRN_PM(r) ASICREV_IS(r, PITCAIRN)
#define ASICREV_IS_CAPEVERDE_M(r) ASICREV_IS(r, CAPEVERDE)
#define ASICREV_IS_OLAND_M(r) ASICREV_IS(r, OLAND)
#define ASICREV_IS_HAINAN_V(r) ASICREV_IS(r, HAINAN)
#define ASICREV_IS_BONAIRE_M(r) ASICREV_IS(r, BONAIRE)
#define ASICREV_IS_HAWAII_P(r) ASICREV_IS(r, HAWAII)
#define ASICREV_IS_SPECTRE(r) ASICREV_IS(r, SPECTRE)
#define ASICREV_IS_SPOOKY(r) ASICREV_IS(r, SPOOKY)
#define ASICREV_IS_KALINDI(r) ASICREV_IS(r, KALINDI)
#define ASICREV_IS_KALINDI_GODAVARI(r) ASICREV_IS(r, GODAVARI)
#define ASICREV_IS_ICELAND_M(r) ASICREV_IS(r, ICELAND)
#define ASICREV_IS_TONGA_P(r) ASICREV_IS(r, TONGA)
#define ASICREV_IS_FIJI_P(r) ASICREV_IS(r, FIJI)
#define ASICREV_IS_POLARIS10_P(r) ASICREV_IS(r, POLARIS10)
#define ASICREV_IS_POLARIS11_M(r) ASICREV_IS(r, POLARIS11)
#define ASICREV_IS_POLARIS12_V(r) ASICREV_IS(r, POLARIS12)
#define ASICREV_IS_VEGAM_P(r) ASICREV_IS(r, VEGAM)
#define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO)
#define ASICREV_IS_CARRIZO_BRISTOL(r) ASICREV_IS(r, BRISTOL)
#define ASICREV_IS_STONEY(r) ASICREV_IS(r, STONEY)
#define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10)
#define ASICREV_IS_VEGA10_P(r) ASICREV_IS(r, VEGA10)
#define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12)
#define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12)
#define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20)
#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
#define ASICREV_IS_RENOIR(r) ASICREV_IS(r, RENOIR)
#define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10)
#define ASICREV_IS_NAVI12_P(r) ASICREV_IS(r, NAVI12)
#define ASICREV_IS_NAVI14_M(r) ASICREV_IS(r, NAVI14)
#define ASICREV_IS_NAVI21_M(r) ASICREV_IS(r, NAVI21)
#define ASICREV_IS_NAVI22_P(r) ASICREV_IS(r, NAVI22)
#define ASICREV_IS_NAVI23_P(r) ASICREV_IS(r, NAVI23)
#define ASICREV_IS_NAVI24_P(r) ASICREV_IS(r, NAVI24)
#define ASICREV_IS_VANGOGH(r) ASICREV_IS(r, VANGOGH)
#define ASICREV_IS_NAVI31_P(r) ASICREV_IS(r, NAVI31)
#define ASICREV_IS_NAVI32_P(r) ASICREV_IS(r, NAVI32)
#define ASICREV_IS_NAVI33_P(r) ASICREV_IS(r, NAVI33)
#define ASICREV_IS_STRIX1(r) ASICREV_IS(r, STRIX1)
#define ASICREV_IS_STRIX_HALO(r) ASICREV_IS(r, STRIX_HALO)
#define ASICREV_IS_KRACKAN1(r) ASICREV_IS(r, KRACKAN1)
#define ASICREV_IS_GFX1153(r) ASICREV_IS(r, GFX1153)
#define ASICREV_IS_PHOENIX(r) ASICREV_IS(r, PHOENIX)
#define ASICREV_IS_PHOENIX2(r) ASICREV_IS(r, PHOENIX2)
#define ASICREV_IS_HAWK_POINT1(r) ASICREV_IS(r, HAWK_POINT1)
#define ASICREV_IS_HAWK_POINT2(r) ASICREV_IS(r, HAWK_POINT2)
#define ASICREV_IS_GFX1170(r) ASICREV_IS(r, GFX1170)
#define ASICREV_IS_REMBRANDT(r) ASICREV_IS(r, REMBRANDT)
#define ASICREV_IS_RAPHAEL(r) ASICREV_IS(r, RAPHAEL)
#define ASICREV_IS_MENDOCINO(r) ASICREV_IS(r, MENDOCINO)
#define ASICREV_IS_GFX1200(r) ASICREV_IS(r, GFX1200)
#endif // _AMDGPU_ASIC_ADDR_H
src/amd/addrlib/src/chip/gfx10/gfx10_gb_reg.h
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@@ -0,0 +1,52 @@
/*
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
#if !defined (__GFX10_GB_REG_H__)
#define __GFX10_GB_REG_H__
/*
* gfx10_gb_reg.h
*
* Register Spec Release: 1.0
*
*/
//
// Make sure the necessary endian defines are there.
//
#if defined(LITTLEENDIAN_CPU)
#elif defined(BIGENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif
union GB_ADDR_CONFIG_GFX10
{
struct
{
#if defined(LITTLEENDIAN_CPU)
unsigned int NUM_PIPES : 3;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int NUM_PKRS : 3;
unsigned int : 21;
#elif defined(BIGENDIAN_CPU)
unsigned int : 21;
unsigned int NUM_PKRS : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int NUM_PIPES : 3;
#endif
} bitfields, bits;
unsigned int u32All;
int i32All;
float f32All;
};
#endif
src/amd/addrlib/src/chip/gfx11/gfx11_gb_reg.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
#if !defined (__GFX11_GB_REG_H__)
#define __GFX11_GB_REG_H__
/*
* gfx11_gb_reg.h
*
* Register Spec Release: 1.0
*
*/
//
// Make sure the necessary endian defines are there.
//
#if defined(LITTLEENDIAN_CPU)
#elif defined(BIGENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif
union GB_ADDR_CONFIG_GFX11
{
struct
{
#if defined(LITTLEENDIAN_CPU)
unsigned int NUM_PIPES : 3;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int NUM_PKRS : 3;
unsigned int : 8;
unsigned int NUM_SHADER_ENGINES : 2;
unsigned int : 5;
unsigned int NUM_RB_PER_SE : 2;
unsigned int : 4;
#elif defined(BIGENDIAN_CPU)
unsigned int : 4;
unsigned int NUM_RB_PER_SE : 2;
unsigned int : 5;
unsigned int NUM_SHADER_ENGINES : 2;
unsigned int : 8;
unsigned int NUM_PKRS : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int NUM_PIPES : 3;
#endif
} bitfields, bits;
unsigned int u32All;
int i32All;
float f32All;
};
#endif
src/amd/addrlib/src/chip/gfx12/gfx12_gb_reg.h
+57
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
#if !defined (__GFX12_GB_REG_H__)
#define __GFX12_GB_REG_H__
/*
* gfx12_gb_reg.h
*
* Register Spec Release: 1.0
*
*/
//
// Make sure the necessary endian defines are there.
//
#if defined(LITTLEENDIAN_CPU)
#elif defined(BIGENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif
union GB_ADDR_CONFIG_GFX12 {
struct {
#if defined(LITTLEENDIAN_CPU)
unsigned int NUM_PIPES : 3;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int NUM_PKRS : 3;
unsigned int : 8;
unsigned int NUM_SHADER_ENGINES : 4;
unsigned int : 3;
unsigned int NUM_RB_PER_SE : 2;
unsigned int : 4;
#elif defined(BIGENDIAN_CPU)
unsigned int : 4;
unsigned int NUM_RB_PER_SE : 2;
unsigned int : 3;
unsigned int NUM_SHADER_ENGINES : 4;
unsigned int : 8;
unsigned int NUM_PKRS : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int NUM_PIPES : 3;
#endif
} bitfields, bits;
unsigned int u32All;
int i32All;
float f32All;
};
#endif
src/amd/addrlib/src/chip/gfx9/gfx9_gb_reg.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
#if !defined (__GFX9_GB_REG_H__)
#define __GFX9_GB_REG_H__
/*
* gfx9_gb_reg.h
*
* Register Spec Release: 1.0
*
*/
//
// Make sure the necessary endian defines are there.
//
#if defined(LITTLEENDIAN_CPU)
#elif defined(BIGENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif
union GB_ADDR_CONFIG_GFX9 {
struct {
#if defined(LITTLEENDIAN_CPU)
unsigned int NUM_PIPES : 3;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int BANK_INTERLEAVE_SIZE : 3;
unsigned int : 1;
unsigned int NUM_BANKS : 3;
unsigned int : 1;
unsigned int SHADER_ENGINE_TILE_SIZE : 3;
unsigned int NUM_SHADER_ENGINES : 2;
unsigned int NUM_GPUS : 3;
unsigned int MULTI_GPU_TILE_SIZE : 2;
unsigned int NUM_RB_PER_SE : 2;
unsigned int ROW_SIZE : 2;
unsigned int NUM_LOWER_PIPES : 1;
unsigned int SE_ENABLE : 1;
#elif defined(BIGENDIAN_CPU)
unsigned int SE_ENABLE : 1;
unsigned int NUM_LOWER_PIPES : 1;
unsigned int ROW_SIZE : 2;
unsigned int NUM_RB_PER_SE : 2;
unsigned int MULTI_GPU_TILE_SIZE : 2;
unsigned int NUM_GPUS : 3;
unsigned int NUM_SHADER_ENGINES : 2;
unsigned int SHADER_ENGINE_TILE_SIZE : 3;
unsigned int : 1;
unsigned int NUM_BANKS : 3;
unsigned int : 1;
unsigned int BANK_INTERLEAVE_SIZE : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int NUM_PIPES : 3;
#endif
} bitfields, bits;
unsigned int u32All;
signed int i32All;
float f32All;
};
#endif
src/amd/addrlib/src/chip/r800/si_gb_reg.h
+194
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
#if !defined (__SI_GB_REG_H__)
#define __SI_GB_REG_H__
/*****************************************************************************************************************
*
* si_gb_reg.h
*
* Register Spec Release: Chip Spec 0.28
*
*****************************************************************************************************************/
//
// Make sure the necessary endian defines are there.
//
#if defined(LITTLEENDIAN_CPU)
#elif defined(BIGENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif
/*
* GB_ADDR_CONFIG struct
*/
#if defined(LITTLEENDIAN_CPU)
typedef struct _GB_ADDR_CONFIG_T {
unsigned int num_pipes : 3;
unsigned int : 1;
unsigned int pipe_interleave_size : 3;
unsigned int : 1;
unsigned int bank_interleave_size : 3;
unsigned int : 1;
unsigned int num_shader_engines : 2;
unsigned int : 2;
unsigned int shader_engine_tile_size : 3;
unsigned int : 1;
unsigned int num_gpus : 3;
unsigned int : 1;
unsigned int multi_gpu_tile_size : 2;
unsigned int : 2;
unsigned int row_size : 2;
unsigned int num_lower_pipes : 1;
unsigned int : 1;
} GB_ADDR_CONFIG_T;
#elif defined(BIGENDIAN_CPU)
typedef struct _GB_ADDR_CONFIG_T {
unsigned int : 1;
unsigned int num_lower_pipes : 1;
unsigned int row_size : 2;
unsigned int : 2;
unsigned int multi_gpu_tile_size : 2;
unsigned int : 1;
unsigned int num_gpus : 3;
unsigned int : 1;
unsigned int shader_engine_tile_size : 3;
unsigned int : 2;
unsigned int num_shader_engines : 2;
unsigned int : 1;
unsigned int bank_interleave_size : 3;
unsigned int : 1;
unsigned int pipe_interleave_size : 3;
unsigned int : 1;
unsigned int num_pipes : 3;
} GB_ADDR_CONFIG_T;
#endif
#if defined(LITTLEENDIAN_CPU)
typedef struct _GB_ADDR_CONFIG_N {
unsigned int num_pipes : 3;
unsigned int pipe_interleave_size : 3;
unsigned int max_compressed_frags : 2;
unsigned int bank_interleave_size : 3;
unsigned int : 1;
unsigned int num_banks : 3;
unsigned int : 1;
unsigned int shader_engine_tile_size : 3;
unsigned int num_shader_engines : 2;
unsigned int num_gpus : 3;
unsigned int multi_gpu_tile_size : 2;
unsigned int num_rb_per_se : 2;
unsigned int row_size : 2;
unsigned int num_lower_pipes : 1;
unsigned int se_enable : 1;
} GB_ADDR_CONFIG_N;
#elif defined(BIGENDIAN_CPU)
typedef struct _GB_ADDR_CONFIG_N {
unsigned int se_enable : 1;
unsigned int num_lower_pipes : 1;
unsigned int row_size : 2;
unsigned int num_rb_per_se : 2;
unsigned int multi_gpu_tile_size : 2;
unsigned int num_gpus : 3;
unsigned int num_shader_engines : 2;
unsigned int shader_engine_tile_size : 3;
unsigned int : 1;
unsigned int num_banks : 3;
unsigned int : 1;
unsigned int bank_interleave_size : 3;
unsigned int max_compressed_frags : 2;
unsigned int pipe_interleave_size : 3;
unsigned int num_pipes : 3;
} GB_ADDR_CONFIG_N;
#endif
typedef union {
unsigned int val : 32;
GB_ADDR_CONFIG_T f;
GB_ADDR_CONFIG_N n;
} GB_ADDR_CONFIG;
#if defined(LITTLEENDIAN_CPU)
typedef struct _GB_TILE_MODE_T {
unsigned int micro_tile_mode : 2;
unsigned int array_mode : 4;
unsigned int pipe_config : 5;
unsigned int tile_split : 3;
unsigned int bank_width : 2;
unsigned int bank_height : 2;
unsigned int macro_tile_aspect : 2;
unsigned int num_banks : 2;
unsigned int micro_tile_mode_new : 3;
unsigned int sample_split : 2;
unsigned int alt_pipe_config : 5;
} GB_TILE_MODE_T;
typedef struct _GB_MACROTILE_MODE_T {
unsigned int bank_width : 2;
unsigned int bank_height : 2;
unsigned int macro_tile_aspect : 2;
unsigned int num_banks : 2;
unsigned int alt_bank_height : 2;
unsigned int alt_macro_tile_aspect : 2;
unsigned int alt_num_banks : 2;
unsigned int : 18;
} GB_MACROTILE_MODE_T;
#elif defined(BIGENDIAN_CPU)
typedef struct _GB_TILE_MODE_T {
unsigned int alt_pipe_config : 5;
unsigned int sample_split : 2;
unsigned int micro_tile_mode_new : 3;
unsigned int num_banks : 2;
unsigned int macro_tile_aspect : 2;
unsigned int bank_height : 2;
unsigned int bank_width : 2;
unsigned int tile_split : 3;
unsigned int pipe_config : 5;
unsigned int array_mode : 4;
unsigned int micro_tile_mode : 2;
} GB_TILE_MODE_T;
typedef struct _GB_MACROTILE_MODE_T {
unsigned int : 18;
unsigned int alt_num_banks : 2;
unsigned int alt_macro_tile_aspect : 2;
unsigned int alt_bank_height : 2;
unsigned int num_banks : 2;
unsigned int macro_tile_aspect : 2;
unsigned int bank_height : 2;
unsigned int bank_width : 2;
} GB_MACROTILE_MODE_T;
#endif
typedef union {
unsigned int val : 32;
GB_TILE_MODE_T f;
} GB_TILE_MODE;
typedef union {
unsigned int val : 32;
GB_MACROTILE_MODE_T f;
} GB_MACROTILE_MODE;
#endif
src/amd/addrlib/src/core/addrcommon.h
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src/amd/addrlib/src/core/addrelemlib.cpp
+1818
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src/amd/addrlib/src/core/addrelemlib.h
+262
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
****************************************************************************************************
* @file addrelemlib.h
* @brief Contains the class for element/pixel related functions.
****************************************************************************************************
*/
#ifndef __ELEM_LIB_H__
#define __ELEM_LIB_H__
#include "addrinterface.h"
#include "addrobject.h"
#include "addrcommon.h"
namespace Addr
{
class Lib;
// The masks for property bits within the Properties INT_32
union ComponentFlags
{
struct
{
UINT_32 byteAligned : 1; ///< all components are byte aligned
UINT_32 exportNorm : 1; ///< components support R6xx NORM compression
UINT_32 floatComp : 1; ///< there is at least one floating point component
};
UINT_32 value;
};
// Copy from legacy lib's NumberType
enum NumberType
{
// The following number types have the range [-1..1]
ADDR_NO_NUMBER, // This component doesn't exist and has no default value
ADDR_EPSILON, // Force component value to integer 0x00000001
ADDR_ZERO, // Force component value to integer 0x00000000
ADDR_ONE, // Force component value to floating point 1.0
// Above values don't have any bits per component (keep ADDR_ONE the last of these)
ADDR_UNORM, // Unsigned normalized (repeating fraction) full precision
ADDR_SNORM, // Signed normalized (repeating fraction) full precision
ADDR_GAMMA, // Gamma-corrected, full precision
ADDR_UNORM_R5XXRB, // Unsigned normalized (repeating fraction) for r5xx RB
ADDR_SNORM_R5XXRB, // Signed normalized (repeating fraction) for r5xx RB
ADDR_GAMMA_R5XXRB, // Gamma-corrected for r5xx RB (note: unnormalized value)
ADDR_UNORM_R5XXBC, // Unsigned normalized (repeating fraction) for r5xx BC
ADDR_SNORM_R5XXBC, // Signed normalized (repeating fraction) for r5xx BC
ADDR_GAMMA_R5XXBC, // Gamma-corrected for r5xx BC (note: unnormalized value)
ADDR_UNORM_R6XX, // Unsigned normalized (repeating fraction) for R6xx
ADDR_UNORM_R6XXDB, // Unorms for 24-bit depth: one value differs from ADDR_UNORM_R6XX
ADDR_SNORM_R6XX, // Signed normalized (repeating fraction) for R6xx
ADDR_GAMMA8_R6XX, // Gamma-corrected for r6xx
ADDR_GAMMA8_R7XX_TP, // Gamma-corrected for r7xx TP 12bit unorm 8.4.
ADDR_U4FLOATC, // Unsigned float: 4-bit exponent, bias=15, no NaN, clamp [0..1]
ADDR_GAMMA_4SEG, // Gamma-corrected, four segment approximation
ADDR_U0FIXED, // Unsigned 0.N-bit fixed point
// The following number types have large ranges (LEAVE ADDR_USCALED first or fix Finish routine)
ADDR_USCALED, // Unsigned integer converted to/from floating point
ADDR_SSCALED, // Signed integer converted to/from floating point
ADDR_USCALED_R5XXRB, // Unsigned integer to/from floating point for r5xx RB
ADDR_SSCALED_R5XXRB, // Signed integer to/from floating point for r5xx RB
ADDR_UINT_BITS, // Keep in unsigned integer form, clamped to specified range
ADDR_SINT_BITS, // Keep in signed integer form, clamped to specified range
ADDR_UINTBITS, // @@ remove Keep in unsigned integer form, use modulus to reduce bits
ADDR_SINTBITS, // @@ remove Keep in signed integer form, use modulus to reduce bits
// The following number types and ADDR_U4FLOATC have exponents
// (LEAVE ADDR_S8FLOAT first or fix Finish routine)
ADDR_S8FLOAT, // Signed floating point with 8-bit exponent, bias=127
ADDR_S8FLOAT32, // 32-bit IEEE float, passes through NaN values
ADDR_S5FLOAT, // Signed floating point with 5-bit exponent, bias=15
ADDR_S5FLOATM, // Signed floating point with 5-bit exponent, bias=15, no NaN/Inf
ADDR_U5FLOAT, // Signed floating point with 5-bit exponent, bias=15
ADDR_U3FLOATM, // Unsigned floating point with 3-bit exponent, bias=3
ADDR_S5FIXED, // Signed 5.N-bit fixed point, with rounding
ADDR_END_NUMBER // Used for range comparisons
};
// Copy from legacy lib's AddrElement
enum ElemMode
{
// These formats allow both packing an unpacking
ADDR_ROUND_BY_HALF, // add 1/2 and truncate when packing this element
ADDR_ROUND_TRUNCATE, // truncate toward 0 for sign/mag, else toward neg
ADDR_ROUND_DITHER, // Pack by dithering -- requires (x,y) position
// These formats only allow unpacking, no packing
ADDR_UNCOMPRESSED, // Elements are not compressed: one data element per pixel/texel
ADDR_EXPANDED, // Elements are split up and stored in multiple data elements
ADDR_PACKED_STD, // Elements are compressed into ExpandX by ExpandY data elements
ADDR_PACKED_REV, // Like ADDR_PACKED, but X order of pixels is reverved
ADDR_PACKED_GBGR, // Elements are compressed 4:2:2 in G1B_G0R order (high to low)
ADDR_PACKED_BGRG, // Elements are compressed 4:2:2 in BG1_RG0 order (high to low)
ADDR_PACKED_BC1, // Each data element is uncompressed to a 4x4 pixel/texel array
ADDR_PACKED_BC2, // Each data element is uncompressed to a 4x4 pixel/texel array
ADDR_PACKED_BC3, // Each data element is uncompressed to a 4x4 pixel/texel array
ADDR_PACKED_BC4, // Each data element is uncompressed to a 4x4 pixel/texel array
ADDR_PACKED_BC5, // Each data element is uncompressed to a 4x4 pixel/texel array
ADDR_PACKED_ETC2_64BPP, // ETC2 formats that use 64bpp to represent each 4x4 block
ADDR_PACKED_ETC2_128BPP, // ETC2 formats that use 128bpp to represent each 4x4 block
ADDR_PACKED_ASTC, // Various ASTC formats, all are 128bpp with varying block sizes
// These formats provide various kinds of compression
ADDR_ZPLANE_R5XX, // Compressed Zplane using r5xx architecture format
ADDR_ZPLANE_R6XX, // Compressed Zplane using r6xx architecture format
//@@ Fill in the compression modes
ADDR_END_ELEMENT // Used for range comparisons
};
enum DepthPlanarType
{
ADDR_DEPTH_PLANAR_NONE = 0, // No plane z/stencl
ADDR_DEPTH_PLANAR_R600 = 1, // R600 z and stencil planes are store within a tile
ADDR_DEPTH_PLANAR_R800 = 2, // R800 has separate z and stencil planes
};
/**
****************************************************************************************************
* PixelFormatInfo
*
* @brief
* Per component info
*
****************************************************************************************************
*/
struct PixelFormatInfo
{
UINT_32 compBit[4];
NumberType numType[4];
UINT_32 compStart[4];
ElemMode elemMode;
UINT_32 comps; ///< Number of components
};
/**
****************************************************************************************************
* @brief This class contains asic indepentent element related attributes and operations
****************************************************************************************************
*/
class ElemLib : public Object
{
protected:
ElemLib(Lib* pAddrLib);
public:
/// Makes this class virtual
virtual ~ElemLib();
static ElemLib* Create(
const Lib* pAddrLib);
/// The implementation is only for R6xx/R7xx, so make it virtual in case we need for R8xx
BOOL_32 PixGetExportNorm(
AddrColorFormat colorFmt,
AddrSurfaceNumber numberFmt, AddrSurfaceSwap swap) const;
/// Below method are asic independent, so make them just static.
/// Remove static if we need different operation in hwl.
VOID Flt32ToDepthPixel(
AddrDepthFormat format, const ADDR_FLT_32 comps[2], UINT_8 *pPixel) const;
VOID Flt32ToColorPixel(
AddrColorFormat format, AddrSurfaceNumber surfNum, AddrSurfaceSwap surfSwap,
const ADDR_FLT_32 comps[4], UINT_8 *pPixel) const;
static VOID Flt32sToInt32s(
ADDR_FLT_32 value, UINT_32 bits, NumberType numberType, UINT_32* pResult);
static VOID Int32sToPixel(
UINT_32 numComps, UINT_32* pComps, UINT_32* pCompBits, UINT_32* pCompStart,
ComponentFlags properties, UINT_32 resultBits, UINT_8* pPixel);
VOID PixGetColorCompInfo(
AddrColorFormat format, AddrSurfaceNumber number, AddrSurfaceSwap swap,
PixelFormatInfo* pInfo) const;
VOID PixGetDepthCompInfo(
AddrDepthFormat format, PixelFormatInfo* pInfo) const;
UINT_32 GetBitsPerPixel(
AddrFormat format, ElemMode* pElemMode = NULL,
UINT_32* pExpandX = NULL, UINT_32* pExpandY = NULL, UINT_32* pBitsUnused = NULL);
static VOID SetClearComps(
ADDR_FLT_32 comps[4], BOOL_32 clearColor, BOOL_32 float32);
VOID AdjustSurfaceInfo(
ElemMode elemMode, UINT_32 expandX, UINT_32 expandY,
UINT_32* pBpp, UINT_32* pBasePitch, UINT_32* pWidth, UINT_32* pHeight);
VOID RestoreSurfaceInfo(
ElemMode elemMode, UINT_32 expandX, UINT_32 expandY,
UINT_32* pBpp, UINT_32* pWidth, UINT_32* pHeight);
/// Checks if depth and stencil are planar inside a tile
BOOL_32 IsDepthStencilTilePlanar()
{
return (m_depthPlanarType == ADDR_DEPTH_PLANAR_R600) ? TRUE : FALSE;
}
/// Sets m_configFlags, copied from AddrLib
VOID SetConfigFlags(ConfigFlags flags)
{
m_configFlags = flags;
}
static BOOL_32 IsCompressed(AddrFormat format);
static BOOL_32 IsBlockCompressed(AddrFormat format);
static BOOL_32 IsExpand3x(AddrFormat format);
static BOOL_32 IsMacroPixelPacked(AddrFormat format);
protected:
static VOID GetCompBits(
UINT_32 c0, UINT_32 c1, UINT_32 c2, UINT_32 c3,
PixelFormatInfo* pInfo,
ElemMode elemMode = ADDR_ROUND_BY_HALF);
static VOID GetCompType(
AddrColorFormat format, AddrSurfaceNumber numType,
PixelFormatInfo* pInfo);
static VOID GetCompSwap(
AddrSurfaceSwap swap, PixelFormatInfo* pInfo);
static VOID SwapComps(
UINT_32 c0, UINT_32 c1, PixelFormatInfo* pInfo);
private:
UINT_32 m_fp16ExportNorm; ///< If allow FP16 to be reported as EXPORT_NORM
DepthPlanarType m_depthPlanarType;
ConfigFlags m_configFlags; ///< Copy of AddrLib's configFlags
Addr::Lib* const m_pAddrLib; ///< Pointer to parent addrlib instance
};
} //Addr
#endif
src/amd/addrlib/src/core/addrlib.cpp
+852
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@@ -0,0 +1,852 @@
/*
************************************************************************************************************************
*
* Copyright (C) 2007-2026 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
****************************************************************************************************
* @file addrlib.cpp
* @brief Contains the implementation for the Addr::Lib class.
****************************************************************************************************
*/
#include "addrinterface.h"
#include "addrlib.h"
#include "addrcommon.h"
#if defined(__APPLE__)
UINT_32 div64_32(UINT_64 n, UINT_32 base)
{
UINT_64 rem = n;
UINT_64 b = base;
UINT_64 res, d = 1;
UINT_32 high = rem >> 32;
res = 0;
if (high >= base)
{
high /= base;
res = (UINT_64) high << 32;
rem -= (UINT_64) (high * base) << 32;
}
while (((INT_64)b > 0) && (b < rem))
{
b = b + b;
d = d + d;
}
do
{
if (rem >= b)
{
rem -= b;
res += d;
}
b >>= 1;
d >>= 1;
} while (d);
n = res;
return rem;
}
extern "C"
UINT_32 __umoddi3(UINT_64 n, UINT_32 base)
{
return div64_32(n, base);
}
#endif // __APPLE__
namespace Addr
{
////////////////////////////////////////////////////////////////////////////////////////////////////
// Constructor/Destructor
////////////////////////////////////////////////////////////////////////////////////////////////////
/**
****************************************************************************************************
* Lib::Lib
*
* @brief
* Constructor for the AddrLib class
*
****************************************************************************************************
*/
Lib::Lib() :
m_chipFamily(ADDR_CHIP_FAMILY_IVLD),
m_chipRevision(0),
m_version(ADDRLIB_VERSION),
m_pipes(0),
m_banks(0),
m_pipeInterleaveBytes(0),
m_rowSize(0),
m_minPitchAlignPixels(1),
m_maxSamples(8),
m_maxBaseAlign(0),
m_maxMetaBaseAlign(0),
m_pElemLib(NULL)
{
m_configFlags.value = 0;
}
/**
****************************************************************************************************
* Lib::Lib
*
* @brief
* Constructor for the AddrLib class with hClient as parameter
*
****************************************************************************************************
*/
Lib::Lib(const Client* pClient) :
Object(pClient),
m_chipFamily(ADDR_CHIP_FAMILY_IVLD),
m_chipRevision(0),
m_version(ADDRLIB_VERSION),
m_pipes(0),
m_banks(0),
m_pipeInterleaveBytes(0),
m_rowSize(0),
m_minPitchAlignPixels(1),
m_maxSamples(8),
m_maxBaseAlign(0),
m_maxMetaBaseAlign(0),
m_pElemLib(NULL)
{
m_configFlags.value = 0;
}
/**
****************************************************************************************************
* Lib::~AddrLib
*
* @brief
* Destructor for the AddrLib class
*
****************************************************************************************************
*/
Lib::~Lib()
{
if (m_pElemLib)
{
delete m_pElemLib;
m_pElemLib = NULL;
}
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// Initialization/Helper
////////////////////////////////////////////////////////////////////////////////////////////////////
/**
****************************************************************************************************
* Lib::Create
*
* @brief
* Creates and initializes AddrLib object.
*
* @return
* ADDR_E_RETURNCODE
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::Create(
const ADDR_CREATE_INPUT* pCreateIn, ///< [in] pointer to ADDR_CREATE_INPUT
ADDR_CREATE_OUTPUT* pCreateOut) ///< [out] pointer to ADDR_CREATE_OUTPUT
{
Lib* pLib = NULL;
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (pCreateIn->createFlags.fillSizeFields == TRUE)
{
if ((pCreateIn->size != sizeof(ADDR_CREATE_INPUT)) ||
(pCreateOut->size != sizeof(ADDR_CREATE_OUTPUT)))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}
}
#if DEBUG
ApplyDebugPrinters(pCreateIn->callbacks.debugPrint, pCreateIn->hClient);
#endif
if ((returnCode == ADDR_OK) &&
(pCreateIn->callbacks.allocSysMem != NULL) &&
(pCreateIn->callbacks.freeSysMem != NULL))
{
Client client = {
pCreateIn->hClient,
pCreateIn->callbacks
};
switch (pCreateIn->chipEngine)
{
case CIASICIDGFXENGINE_SOUTHERNISLAND:
switch (pCreateIn->chipFamily)
{
case FAMILY_SI:
pLib = SiHwlInit(&client);
break;
case FAMILY_CI:
case FAMILY_KV: // CI based fusion
case FAMILY_VI:
case FAMILY_CZ: // VI based fusion
pLib = CiHwlInit(&client);
break;
default:
ADDR_ASSERT_ALWAYS();
break;
}
break;
case CIASICIDGFXENGINE_ARCTICISLAND:
switch (pCreateIn->chipFamily)
{
case FAMILY_AI:
case FAMILY_RV:
pLib = Gfx9HwlInit(&client);
break;
case FAMILY_NV:
case FAMILY_VGH:
case FAMILY_RMB:
case FAMILY_RPL:
case FAMILY_MDN:
pLib = Gfx10HwlInit(&client);
break;
case FAMILY_NV3:
case FAMILY_STX:
case FAMILY_PHX:
case FAMILY_GFX1170:
pLib = Gfx11HwlInit(&client);
break;
case FAMILY_NV4:
pLib = Gfx12HwlInit(&client);
break;
default:
ADDR_ASSERT_ALWAYS();
break;
}
break;
default:
ADDR_ASSERT_ALWAYS();
break;
}
}
if(pLib == NULL)
{
returnCode = ADDR_OUTOFMEMORY;
}
if (pLib != NULL)
{
BOOL_32 initValid;
// Pass createFlags to configFlags first since these flags may be overwritten
pLib->m_configFlags.noCubeMipSlicesPad = pCreateIn->createFlags.noCubeMipSlicesPad;
pLib->m_configFlags.fillSizeFields = pCreateIn->createFlags.fillSizeFields;
pLib->m_configFlags.useTileIndex = pCreateIn->createFlags.useTileIndex;
pLib->m_configFlags.useCombinedSwizzle = pCreateIn->createFlags.useCombinedSwizzle;
pLib->m_configFlags.checkLast2DLevel = pCreateIn->createFlags.checkLast2DLevel;
pLib->m_configFlags.useHtileSliceAlign = pCreateIn->createFlags.useHtileSliceAlign;
pLib->m_configFlags.allowLargeThickTile = pCreateIn->createFlags.allowLargeThickTile;
pLib->m_configFlags.forceDccAndTcCompat = pCreateIn->createFlags.forceDccAndTcCompat;
pLib->m_configFlags.nonPower2MemConfig = pCreateIn->createFlags.nonPower2MemConfig;
pLib->m_configFlags.enableAltTiling = pCreateIn->createFlags.enableAltTiling;
pLib->m_configFlags.disableLinearOpt = FALSE;
pLib->SetChipFamily(pCreateIn->chipFamily, pCreateIn->chipRevision);
pLib->SetMinPitchAlignPixels(pCreateIn->minPitchAlignPixels);
// Global parameters initialized and remaining configFlags bits are set as well
initValid = pLib->HwlInitGlobalParams(pCreateIn);
if (initValid)
{
pLib->m_pElemLib = ElemLib::Create(pLib);
}
else
{
pLib->m_pElemLib = NULL; // Don't go on allocating element lib
returnCode = ADDR_INVALIDGBREGVALUES;
}
if (pLib->m_pElemLib == NULL)
{
delete pLib;
pLib = NULL;
returnCode = ADDR_OUTOFMEMORY;
ADDR_ASSERT_ALWAYS();
}
else
{
pLib->m_pElemLib->SetConfigFlags(pLib->m_configFlags);
}
}
pCreateOut->hLib = pLib;
if ((pLib != NULL) &&
(returnCode == ADDR_OK))
{
pCreateOut->numEquations =
pLib->HwlGetEquationTableInfo(&pCreateOut->pEquationTable);
pLib->SetMaxAlignments();
}
return returnCode;
}
/**
****************************************************************************************************
* Lib::GetFormatProperties
*
* @brief
* Returns the properties of the format as specifed in the input.
* @return
* ADDR_E_RETURNCODE
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::GetFormatProperties(
const ADDR_FORMAT_PROPERTIES_IN& in,
ADDR_FORMAT_PROPERTIES_OUT* pOut
) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (GetFillSizeFieldsFlags() == TRUE)
{
if ((in.size != sizeof(ADDR_FORMAT_PROPERTIES_IN)) ||
(pOut->size != sizeof(ADDR_FORMAT_PROPERTIES_OUT)))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}
}
if (returnCode == ADDR_OK)
{
pOut->bpp = GetElemLib()->GetBitsPerPixel(in.format,
nullptr, // elemMode, unused
&pOut->expand.width,
&pOut->expand.height,
nullptr); // unused bits
}
return returnCode;
}
/**
****************************************************************************************************
* Lib::SetChipFamily
*
* @brief
* Convert familyID defined in atiid.h to ChipFamily and set m_chipFamily/m_chipRevision
* @return
* N/A
****************************************************************************************************
*/
VOID Lib::SetChipFamily(
UINT_32 uChipFamily, ///< [in] chip family defined in atiid.h
UINT_32 uChipRevision) ///< [in] chip revision defined in "asic_family"_id.h
{
ChipFamily family = HwlConvertChipFamily(uChipFamily, uChipRevision);
ADDR_ASSERT(family != ADDR_CHIP_FAMILY_IVLD);
m_chipFamily = family;
m_chipRevision = uChipRevision;
}
/**
****************************************************************************************************
* Lib::SetMinPitchAlignPixels
*
* @brief
* Set m_minPitchAlignPixels with input param
*
* @return
* N/A
****************************************************************************************************
*/
VOID Lib::SetMinPitchAlignPixels(
UINT_32 minPitchAlignPixels) ///< [in] minmum pitch alignment in pixels
{
m_minPitchAlignPixels = (minPitchAlignPixels == 0) ? 1 : minPitchAlignPixels;
}
/**
****************************************************************************************************
* Lib::SetMaxAlignments
*
* @brief
* Set max alignments
*
* @return
* N/A
****************************************************************************************************
*/
VOID Lib::SetMaxAlignments()
{
m_maxBaseAlign = HwlComputeMaxBaseAlignments();
m_maxMetaBaseAlign = HwlComputeMaxMetaBaseAlignments();
}
/**
****************************************************************************************************
* Lib::GetLib
*
* @brief
* Get AddrLib pointer
*
* @return
* An AddrLib class pointer
****************************************************************************************************
*/
Lib* Lib::GetLib(
ADDR_HANDLE hLib) ///< [in] handle of ADDR_HANDLE
{
Lib* pLib = static_cast<Addr::Lib*>(hLib);
#if DEBUG
if (pLib != NULL)
{
pLib->SetDebugPrinters();
}
#endif
return pLib;
}
/**
****************************************************************************************************
* Lib::GetMaxAlignments
*
* @brief
* Gets maximum alignments for data surface (include FMask)
*
* @return
* ADDR_E_RETURNCODE
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::GetMaxAlignments(
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut ///< [out] output structure
) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (GetFillSizeFieldsFlags() == TRUE)
{
if (pOut->size != sizeof(ADDR_GET_MAX_ALIGNMENTS_OUTPUT))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}
}
if (returnCode == ADDR_OK)
{
if (m_maxBaseAlign != 0)
{
pOut->baseAlign = m_maxBaseAlign;
}
else
{
returnCode = ADDR_NOTIMPLEMENTED;
}
}
return returnCode;
}
/**
****************************************************************************************************
* Lib::GetMaxMetaAlignments
*
* @brief
* Gets maximum alignments for metadata (CMask, DCC and HTile)
*
* @return
* ADDR_E_RETURNCODE
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::GetMaxMetaAlignments(
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut ///< [out] output structure
) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (GetFillSizeFieldsFlags() == TRUE)
{
if (pOut->size != sizeof(ADDR_GET_MAX_ALIGNMENTS_OUTPUT))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}
}
if (returnCode == ADDR_OK)
{
if (m_maxMetaBaseAlign != 0)
{
pOut->baseAlign = m_maxMetaBaseAlign;
}
else
{
returnCode = ADDR_NOTIMPLEMENTED;
}
}
return returnCode;
}
/**
****************************************************************************************************
* Lib::Bits2Number
*
* @brief
* Cat a array of binary bit to a number
*
* @return
* The number combined with the array of bits
****************************************************************************************************
*/
UINT_32 Lib::Bits2Number(
UINT_32 bitNum, ///< [in] how many bits
...) ///< [in] varaible bits value starting from MSB
{
UINT_32 number = 0;
UINT_32 i;
va_list bits_ptr;
va_start(bits_ptr, bitNum);
for(i = 0; i < bitNum; i++)
{
number |= va_arg(bits_ptr, UINT_32);
number <<= 1;
}
number >>= 1;
va_end(bits_ptr);
return number;
}
////////////////////////////////////////////////////////////////////////////////////////////////////
// Element lib
////////////////////////////////////////////////////////////////////////////////////////////////////
/**
****************************************************************************************************
* Lib::Flt32ToColorPixel
*
* @brief
* Convert a FLT_32 value to a depth/stencil pixel value
* @return
* ADDR_E_RETURNCODE
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::Flt32ToDepthPixel(
const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (GetFillSizeFieldsFlags() == TRUE)
{
if ((pIn->size != sizeof(ELEM_FLT32TODEPTHPIXEL_INPUT)) ||
(pOut->size != sizeof(ELEM_FLT32TODEPTHPIXEL_OUTPUT)))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}
}
if (returnCode == ADDR_OK)
{
GetElemLib()->Flt32ToDepthPixel(pIn->format, pIn->comps, pOut->pPixel);
UINT_32 depthBase = 0;
UINT_32 stencilBase = 0;
UINT_32 depthBits = 0;
UINT_32 stencilBits = 0;
switch (pIn->format)
{
case ADDR_DEPTH_16:
depthBits = 16;
break;
case ADDR_DEPTH_X8_24:
case ADDR_DEPTH_8_24:
case ADDR_DEPTH_X8_24_FLOAT:
case ADDR_DEPTH_8_24_FLOAT:
depthBase = 8;
depthBits = 24;
stencilBits = 8;
break;
case ADDR_DEPTH_32_FLOAT:
depthBits = 32;
break;
case ADDR_DEPTH_X24_8_32_FLOAT:
depthBase = 8;
depthBits = 32;
stencilBits = 8;
break;
default:
break;
}
// Overwrite base since R800 has no "tileBase"
if (GetElemLib()->IsDepthStencilTilePlanar() == FALSE)
{
depthBase = 0;
stencilBase = 0;
}
depthBase *= 64;
stencilBase *= 64;
pOut->stencilBase = stencilBase;
pOut->depthBase = depthBase;
pOut->depthBits = depthBits;
pOut->stencilBits = stencilBits;
}
return returnCode;
}
/**
****************************************************************************************************
* Lib::Flt32ToColorPixel
*
* @brief
* Convert a FLT_32 value to a red/green/blue/alpha pixel value
* @return
* ADDR_E_RETURNCODE
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::Flt32ToColorPixel(
const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (GetFillSizeFieldsFlags() == TRUE)
{
if ((pIn->size != sizeof(ELEM_FLT32TOCOLORPIXEL_INPUT)) ||
(pOut->size != sizeof(ELEM_FLT32TOCOLORPIXEL_OUTPUT)))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}
}
if (returnCode == ADDR_OK)
{
GetElemLib()->Flt32ToColorPixel(pIn->format,
pIn->surfNum,
pIn->surfSwap,
pIn->comps,
pOut->pPixel);
}
return returnCode;
}
/**
****************************************************************************************************
* Lib::GetExportNorm
*
* @brief
* Check one format can be EXPORT_NUM
* @return
* TRUE if EXPORT_NORM can be used
****************************************************************************************************
*/
BOOL_32 Lib::GetExportNorm(
const ELEM_GETEXPORTNORM_INPUT* pIn) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
BOOL_32 enabled = FALSE;
if (GetFillSizeFieldsFlags() == TRUE)
{
if (pIn->size != sizeof(ELEM_GETEXPORTNORM_INPUT))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}
}
if (returnCode == ADDR_OK)
{
enabled = GetElemLib()->PixGetExportNorm(pIn->format, pIn->num, pIn->swap);
}
return enabled;
}
/**
****************************************************************************************************
* Lib::GetBpe
*
* @brief
* Get bits-per-element for specified format
* @return
* bits-per-element of specified format
****************************************************************************************************
*/
UINT_32 Lib::GetBpe(AddrFormat format) const
{
return GetElemLib()->GetBitsPerPixel(format);
}
/**
****************************************************************************************************
* Lib::GetSwizzleModePreferenceRatio
*
* @brief
* Get ratio driving swizzle mode selection heuristic. Ratio is returned as fraction nominator
* and denominator
* @return
* void
****************************************************************************************************
*/
void Lib::GetSwizzleModePreferenceRatio(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
UINT_32* pOutRatioLo,
UINT_32* pOutRatioHi
) const
{
const BOOL_32 computeMinSize = (pIn->flags.minimizeAlign == 1) || (pIn->memoryBudget >= 1.0);
if (computeMinSize)
{
*pOutRatioLo = 1;
*pOutRatioHi = 1;
}
else if (pIn->flags.opt4space)
{
*pOutRatioLo = 3;
*pOutRatioHi = 2;
}
else if (pIn->flags.computeMaxSize)
{
*pOutRatioLo = 1024;
*pOutRatioHi = 1;
}
else
{
*pOutRatioLo = 2;
*pOutRatioHi = 1;
}
}
/**
************************************************************************************************************************
* Lib::ComputeOffsetFromSwizzlePattern
*
* @brief
* Compute offset from swizzle pattern
*
* @return
* Offset
************************************************************************************************************************
*/
UINT_32 Lib::ComputeOffsetFromSwizzlePattern(
const UINT_64* pPattern, ///< Swizzle pattern
UINT_32 numBits, ///< Number of bits in pattern
UINT_32 x, ///< x coord in pixel
UINT_32 y, ///< y coord in pixel
UINT_32 z, ///< z coord in slice
UINT_32 s ///< sample id
)
{
UINT_32 offset = 0;
const ADDR_BIT_SETTING* pSwizzlePattern = reinterpret_cast<const ADDR_BIT_SETTING*>(pPattern);
for (UINT_32 i = 0; i < numBits; i++)
{
UINT_32 v = 0;
if (pSwizzlePattern[i].x != 0)
{
UINT_16 mask = pSwizzlePattern[i].x;
UINT_32 xBits = x;
while (mask != 0)
{
if (mask & 1)
{
v ^= xBits & 1;
}
xBits >>= 1;
mask >>= 1;
}
}
if (pSwizzlePattern[i].y != 0)
{
UINT_16 mask = pSwizzlePattern[i].y;
UINT_32 yBits = y;
while (mask != 0)
{
if (mask & 1)
{
v ^= yBits & 1;
}
yBits >>= 1;
mask >>= 1;
}
}
if (pSwizzlePattern[i].z != 0)
{
UINT_16 mask = pSwizzlePattern[i].z;
UINT_32 zBits = z;
while (mask != 0)
{
if (mask & 1)
{
v ^= zBits & 1;
}
zBits >>= 1;
mask >>= 1;
}
}
if (pSwizzlePattern[i].s != 0)
{
UINT_16 mask = pSwizzlePattern[i].s;
UINT_32 sBits = s;
while (mask != 0)
{
if (mask & 1)
{
v ^= sBits & 1;
}
sBits >>= 1;
mask >>= 1;
}
}
offset |= (v << i);
}
return offset;
}
} // Addr
src/amd/addrlib/src/core/addrlib.h
+492
View File
@@ -0,0 +1,492 @@
/*
************************************************************************************************************************
*
* Copyright (C) 2007-2026 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
****************************************************************************************************
* @file addrlib.h
* @brief Contains the Addr::Lib base class definition.
****************************************************************************************************
*/
#ifndef __ADDR_LIB_H__
#define __ADDR_LIB_H__
#include "addrinterface.h"
#include "addrtypes.h"
#include "addrobject.h"
#include "addrelemlib.h"
#include "amdgpu_asic_addr.h"
#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
#endif
#ifndef CIASICIDGFXENGINE_ARCTICISLAND
#define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
#endif
namespace Addr
{
/**
****************************************************************************************************
* @brief Neutral enums that define pipeinterleave
****************************************************************************************************
*/
enum PipeInterleave
{
ADDR_PIPEINTERLEAVE_256B = 256,
ADDR_PIPEINTERLEAVE_512B = 512,
ADDR_PIPEINTERLEAVE_1KB = 1024,
ADDR_PIPEINTERLEAVE_2KB = 2048,
};
/**
****************************************************************************************************
* @brief Neutral enums that define DRAM row size
****************************************************************************************************
*/
enum RowSize
{
ADDR_ROWSIZE_1KB = 1024,
ADDR_ROWSIZE_2KB = 2048,
ADDR_ROWSIZE_4KB = 4096,
ADDR_ROWSIZE_8KB = 8192,
};
/**
****************************************************************************************************
* @brief Neutral enums that define bank interleave
****************************************************************************************************
*/
enum BankInterleave
{
ADDR_BANKINTERLEAVE_1 = 1,
ADDR_BANKINTERLEAVE_2 = 2,
ADDR_BANKINTERLEAVE_4 = 4,
ADDR_BANKINTERLEAVE_8 = 8,
};
/**
****************************************************************************************************
* @brief Neutral enums that define shader engine tile size
****************************************************************************************************
*/
enum ShaderEngineTileSize
{
ADDR_SE_TILESIZE_16 = 16,
ADDR_SE_TILESIZE_32 = 32,
};
/**
****************************************************************************************************
* @brief Neutral enums that define bank swap size
****************************************************************************************************
*/
enum BankSwapSize
{
ADDR_BANKSWAP_128B = 128,
ADDR_BANKSWAP_256B = 256,
ADDR_BANKSWAP_512B = 512,
ADDR_BANKSWAP_1KB = 1024,
};
/**
****************************************************************************************************
* @brief Enums that define max compressed fragments config
****************************************************************************************************
*/
enum NumMaxCompressedFragmentsConfig
{
ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000,
ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001,
ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002,
ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003,
};
/**
****************************************************************************************************
* @brief Enums that define num pipes config
****************************************************************************************************
*/
enum NumPipesConfig
{
ADDR_CONFIG_1_PIPE = 0x00000000,
ADDR_CONFIG_2_PIPE = 0x00000001,
ADDR_CONFIG_4_PIPE = 0x00000002,
ADDR_CONFIG_8_PIPE = 0x00000003,
ADDR_CONFIG_16_PIPE = 0x00000004,
ADDR_CONFIG_32_PIPE = 0x00000005,
ADDR_CONFIG_64_PIPE = 0x00000006,
};
/**
****************************************************************************************************
* @brief Enums that define num banks config
****************************************************************************************************
*/
enum NumBanksConfig
{
ADDR_CONFIG_1_BANK = 0x00000000,
ADDR_CONFIG_2_BANK = 0x00000001,
ADDR_CONFIG_4_BANK = 0x00000002,
ADDR_CONFIG_8_BANK = 0x00000003,
ADDR_CONFIG_16_BANK = 0x00000004,
};
/**
****************************************************************************************************
* @brief Enums that define num rb per shader engine config
****************************************************************************************************
*/
enum NumRbPerShaderEngineConfig
{
ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000,
ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001,
ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002,
};
/**
****************************************************************************************************
* @brief Enums that define num shader engines config
****************************************************************************************************
*/
enum NumShaderEnginesConfig
{
ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000,
ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001,
ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002,
ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003,
};
/**
****************************************************************************************************
* @brief Enums that define pipe interleave size config
****************************************************************************************************
*/
enum PipeInterleaveSizeConfig
{
ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,
ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,
ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002,
ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003,
};
/**
****************************************************************************************************
* @brief Enums that define row size config
****************************************************************************************************
*/
enum RowSizeConfig
{
ADDR_CONFIG_1KB_ROW = 0x00000000,
ADDR_CONFIG_2KB_ROW = 0x00000001,
ADDR_CONFIG_4KB_ROW = 0x00000002,
};
/**
****************************************************************************************************
* @brief Enums that define bank interleave size config
****************************************************************************************************
*/
enum BankInterleaveSizeConfig
{
ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000,
ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001,
ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002,
ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003,
};
/**
****************************************************************************************************
* @brief Enums that define engine tile size config
****************************************************************************************************
*/
enum ShaderEngineTileSizeConfig
{
ADDR_CONFIG_SE_TILE_16 = 0x00000000,
ADDR_CONFIG_SE_TILE_32 = 0x00000001,
};
/**
************************************************************************************************************************
* @brief Bit setting for swizzle pattern
************************************************************************************************************************
*/
union ADDR_BIT_SETTING
{
struct
{
UINT_16 x;
UINT_16 y;
UINT_16 z;
UINT_16 s;
};
UINT_64 value;
};
/**
************************************************************************************************************************
* InitBit
*
* @brief
* Initialize bit setting value via a return value
************************************************************************************************************************
*/
#define InitBit(c, index) (1ull << ((c << 4) + index))
const UINT_64 X0 = InitBit(0, 0);
const UINT_64 X1 = InitBit(0, 1);
const UINT_64 X2 = InitBit(0, 2);
const UINT_64 X3 = InitBit(0, 3);
const UINT_64 X4 = InitBit(0, 4);
const UINT_64 X5 = InitBit(0, 5);
const UINT_64 X6 = InitBit(0, 6);
const UINT_64 X7 = InitBit(0, 7);
const UINT_64 X8 = InitBit(0, 8);
const UINT_64 X9 = InitBit(0, 9);
const UINT_64 X10 = InitBit(0, 10);
const UINT_64 X11 = InitBit(0, 11);
const UINT_64 Y0 = InitBit(1, 0);
const UINT_64 Y1 = InitBit(1, 1);
const UINT_64 Y2 = InitBit(1, 2);
const UINT_64 Y3 = InitBit(1, 3);
const UINT_64 Y4 = InitBit(1, 4);
const UINT_64 Y5 = InitBit(1, 5);
const UINT_64 Y6 = InitBit(1, 6);
const UINT_64 Y7 = InitBit(1, 7);
const UINT_64 Y8 = InitBit(1, 8);
const UINT_64 Y9 = InitBit(1, 9);
const UINT_64 Y10 = InitBit(1, 10);
const UINT_64 Y11 = InitBit(1, 11);
const UINT_64 Z0 = InitBit(2, 0);
const UINT_64 Z1 = InitBit(2, 1);
const UINT_64 Z2 = InitBit(2, 2);
const UINT_64 Z3 = InitBit(2, 3);
const UINT_64 Z4 = InitBit(2, 4);
const UINT_64 Z5 = InitBit(2, 5);
const UINT_64 Z6 = InitBit(2, 6);
const UINT_64 Z7 = InitBit(2, 7);
const UINT_64 Z8 = InitBit(2, 8);
const UINT_64 S0 = InitBit(3, 0);
const UINT_64 S1 = InitBit(3, 1);
const UINT_64 S2 = InitBit(3, 2);
/**
****************************************************************************************************
* @brief This class contains asic independent address lib functionalities
****************************************************************************************************
*/
class Lib : public Object
{
public:
virtual ~Lib();
static ADDR_E_RETURNCODE Create(
const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut);
/// Pair of Create
VOID Destroy()
{
delete this;
}
ADDR_E_RETURNCODE GetFormatProperties(
const ADDR_FORMAT_PROPERTIES_IN& in,
ADDR_FORMAT_PROPERTIES_OUT* pOut) const;
static Lib* GetLib(ADDR_HANDLE hLib);
/// Returns which version of addrlib functions should be used.
virtual UINT_32 GetInterfaceVersion() const = 0;
/// Returns AddrLib version (from compiled binary instead include file)
UINT_32 GetVersion()
{
return m_version;
}
/// Returns asic chip family name defined by AddrLib
ChipFamily GetChipFamily() const
{
return m_chipFamily;
}
ADDR_E_RETURNCODE Flt32ToDepthPixel(
const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const;
ADDR_E_RETURNCODE Flt32ToColorPixel(
const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const;
BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const;
ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
UINT_32 GetBpe(AddrFormat format) const;
void GetSwizzleModePreferenceRatio(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
UINT_32* pOutRatioLo,
UINT_32* pOutRatioHi) const;
static UINT_32 ComputeOffsetFromSwizzlePattern(
const UINT_64* pPattern,
UINT_32 numBits,
UINT_32 x,
UINT_32 y,
UINT_32 z,
UINT_32 s);
protected:
Lib(); // Constructor is protected
Lib(const Client* pClient);
/// Pure virtual function to get max base alignments
virtual UINT_32 HwlComputeMaxBaseAlignments() const = 0;
/// Gets maximum alignements for metadata
virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const
{
ADDR_NOT_IMPLEMENTED();
return 0;
}
VOID ValidBaseAlignments(UINT_32 alignment) const
{
#if DEBUG
ADDR_ASSERT(alignment <= m_maxBaseAlign);
#endif
}
VOID ValidMetaBaseAlignments(UINT_32 metaAlignment) const
{
#if DEBUG
ADDR_ASSERT(metaAlignment <= m_maxMetaBaseAlign);
#endif
}
static BOOL_32 IsTex1d(AddrResourceType resourceType)
{
return (resourceType == ADDR_RSRC_TEX_1D);
}
static BOOL_32 IsTex2d(AddrResourceType resourceType)
{
return (resourceType == ADDR_RSRC_TEX_2D);
}
static BOOL_32 IsTex3d(AddrResourceType resourceType)
{
return (resourceType == ADDR_RSRC_TEX_3D);
}
//
// Initialization
//
/// Pure Virtual function for Hwl computing internal global parameters from h/w registers
virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) = 0;
/// Pure Virtual function for Hwl converting chip family
virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0;
/// Get equation table pointer and number of equations
virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
{
*ppEquationTable = NULL;
return 0;
}
//
// Misc helper
//
static UINT_32 Bits2Number(UINT_32 bitNum, ...);
static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags)
{
return (numFrags != 0) ? numFrags : Max(1u, numSamples);
}
/// Returns pointer of ElemLib
ElemLib* GetElemLib() const
{
return m_pElemLib;
}
/// Returns fillSizeFields flag
UINT_32 GetFillSizeFieldsFlags() const
{
return m_configFlags.fillSizeFields;
}
private:
// Disallow the copy constructor
Lib(const Lib& a);
// Disallow the assignment operator
Lib& operator=(const Lib& a);
VOID SetChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels);
VOID SetMaxAlignments();
protected:
ChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h
UINT_32 m_chipRevision; ///< Revision id from xxx_id.h
UINT_32 m_version; ///< Current version
//
// Global parameters
//
ConfigFlags m_configFlags; ///< Global configuration flags. Note this is setup by
/// AddrLib instead of Client except forceLinearAligned
UINT_32 m_pipes; ///< Number of pipes
UINT_32 m_banks; ///< Number of banks
/// For r800 this is MC_ARB_RAMCFG.NOOFBANK
/// Keep it here to do default parameter calculation
UINT_32 m_pipeInterleaveBytes;
///< Specifies the size of contiguous address space
/// within each tiling pipe when making linear
/// accesses. (Formerly Group Size)
UINT_32 m_rowSize; ///< DRAM row size, in bytes
UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels
UINT_32 m_maxSamples; ///< Max numSamples
UINT_32 m_maxBaseAlign; ///< Max base alignment for data surface
UINT_32 m_maxMetaBaseAlign; ///< Max base alignment for metadata
private:
ElemLib* m_pElemLib; ///< Element Lib pointer
};
Lib* SiHwlInit (const Client* pClient);
Lib* CiHwlInit (const Client* pClient);
Lib* Gfx9HwlInit (const Client* pClient);
Lib* Gfx10HwlInit(const Client* pClient);
Lib* Gfx11HwlInit(const Client* pClient);
Lib* Gfx12HwlInit(const Client* pClient);
} // Addr
#endif
src/amd/addrlib/src/core/addrlib1.cpp
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src/amd/addrlib/src/core/addrlib1.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
****************************************************************************************************
* @file addrlib1.h
* @brief Contains the Addr::V1::Lib class definition.
****************************************************************************************************
*/
#ifndef __ADDR_LIB1_H__
#define __ADDR_LIB1_H__
#include "addrlib.h"
namespace Addr
{
namespace V1
{
/**
****************************************************************************************************
* @brief Neutral enums that define bank swap size
****************************************************************************************************
*/
enum SampleSplitSize
{
ADDR_SAMPLESPLIT_1KB = 1024,
ADDR_SAMPLESPLIT_2KB = 2048,
ADDR_SAMPLESPLIT_4KB = 4096,
ADDR_SAMPLESPLIT_8KB = 8192,
};
/**
****************************************************************************************************
* @brief Flags for AddrTileMode
****************************************************************************************************
*/
struct TileModeFlags
{
UINT_32 thickness : 4;
UINT_32 isLinear : 1;
UINT_32 isMicro : 1;
UINT_32 isMacro : 1;
UINT_32 isMacro3d : 1;
UINT_32 isPrt : 1;
UINT_32 isPrtNoRotation : 1;
UINT_32 isBankSwapped : 1;
};
static const UINT_32 Block64K = 0x10000;
static const UINT_32 PrtTileSize = Block64K;
/**
****************************************************************************************************
* @brief This class contains asic independent address lib functionalities
****************************************************************************************************
*/
class Lib : public Addr::Lib
{
public:
virtual ~Lib();
static Lib* GetLib(
ADDR_HANDLE hLib);
virtual UINT_32 GetInterfaceVersion() const override
{
return 1;
}
/// Returns tileIndex support
BOOL_32 UseTileIndex(INT_32 index) const
{
return m_configFlags.useTileIndex && (index != TileIndexInvalid);
}
/// Returns combined swizzle support
BOOL_32 UseCombinedSwizzle() const
{
return m_configFlags.useCombinedSwizzle;
}
//
// Interface stubs
//
ADDR_E_RETURNCODE ComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord(
const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr(
const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSliceTileSwizzle(
const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ExtractBankPipeSwizzle(
const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const;
ADDR_E_RETURNCODE CombineBankPipeSwizzle(
const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn,
ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeBaseSwizzle(
const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord(
const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr(
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ConvertTileInfoToHW(
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ConvertTileIndex(
const ADDR_CONVERT_TILEINDEX_INPUT* pIn,
ADDR_CONVERT_TILEINDEX_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetMacroModeIndex(
const ADDR_GET_MACROMODEINDEX_INPUT* pIn,
ADDR_GET_MACROMODEINDEX_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ConvertTileIndex1(
const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,
ADDR_CONVERT_TILEINDEX_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetTileIndex(
const ADDR_GET_TILEINDEX_INPUT* pIn,
ADDR_GET_TILEINDEX_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeHtileInfo(
const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeCmaskInfo(
const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeDccInfo(
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeHtileAddrFromCoord(
const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord(
const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeHtileCoordFromAddr(
const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr(
const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputePrtInfo(
const ADDR_PRT_INFO_INPUT* pIn,
ADDR_PRT_INFO_OUTPUT* pOut) const;
protected:
Lib(); // Constructor is protected
Lib(const Client* pClient);
/// Pure Virtual function for Hwl computing surface info
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl computing surface address from coord
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoord(
const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl computing surface coord from address
virtual ADDR_E_RETURNCODE HwlComputeSurfaceCoordFromAddr(
const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl computing surface tile swizzle
virtual ADDR_E_RETURNCODE HwlComputeSliceTileSwizzle(
const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl extracting bank/pipe swizzle from base256b
virtual ADDR_E_RETURNCODE HwlExtractBankPipeSwizzle(
const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl combining bank/pipe swizzle
virtual ADDR_E_RETURNCODE HwlCombineBankPipeSwizzle(
UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO* pTileInfo,
UINT_64 baseAddr, UINT_32* pTileSwizzle) const = 0;
/// Pure Virtual function for Hwl computing base swizzle
virtual ADDR_E_RETURNCODE HwlComputeBaseSwizzle(
const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl computing HTILE base align
virtual UINT_32 HwlComputeHtileBaseAlign(
BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const = 0;
/// Pure Virtual function for Hwl computing HTILE bpp
virtual UINT_32 HwlComputeHtileBpp(
BOOL_32 isWidth8, BOOL_32 isHeight8) const = 0;
/// Pure Virtual function for Hwl computing HTILE bytes
virtual UINT_64 HwlComputeHtileBytes(
UINT_32 pitch, UINT_32 height, UINT_32 bpp,
BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const = 0;
/// Pure Virtual function for Hwl computing FMASK info
virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut) = 0;
/// Pure Virtual function for Hwl FMASK address from coord
virtual ADDR_E_RETURNCODE HwlComputeFmaskAddrFromCoord(
const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl FMASK coord from address
virtual ADDR_E_RETURNCODE HwlComputeFmaskCoordFromAddr(
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl convert tile info from real value to HW value
virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW(
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl compute mipmap info
virtual BOOL_32 HwlComputeMipLevel(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const = 0;
/// Pure Virtual function for Hwl compute max cmask blockMax value
virtual BOOL_32 HwlGetMaxCmaskBlockMax() const = 0;
/// Pure Virtual function for Hwl compute fmask bits
virtual UINT_32 HwlComputeFmaskBits(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
UINT_32* pNumSamples) const = 0;
/// Virtual function to get index (not pure then no need to implement this in all hwls
virtual ADDR_E_RETURNCODE HwlGetTileIndex(
const ADDR_GET_TILEINDEX_INPUT* pIn,
ADDR_GET_TILEINDEX_OUTPUT* pOut) const
{
return ADDR_NOTSUPPORTED;
}
/// Virtual function for Hwl to compute Dcc info
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const
{
return ADDR_NOTSUPPORTED;
}
/// Virtual function to get cmask address for tc compatible cmask
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const
{
return ADDR_NOTSUPPORTED;
}
/// Virtual function to get htile address for tc compatible htile
virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const
{
return ADDR_NOTSUPPORTED;
}
// Compute attributes
// HTILE
UINT_32 ComputeHtileInfo(
ADDR_HTILE_FLAGS flags,
UINT_32 pitchIn, UINT_32 heightIn, UINT_32 numSlices,
BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
ADDR_TILEINFO* pTileInfo,
UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pHtileBytes,
UINT_32* pMacroWidth = NULL, UINT_32* pMacroHeight = NULL,
UINT_64* pSliceSize = NULL, UINT_32* pBaseAlign = NULL) const;
// CMASK
ADDR_E_RETURNCODE ComputeCmaskInfo(
ADDR_CMASK_FLAGS flags,
UINT_32 pitchIn, UINT_32 heightIn, UINT_32 numSlices, BOOL_32 isLinear,
ADDR_TILEINFO* pTileInfo, UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pCmaskBytes,
UINT_32* pMacroWidth, UINT_32* pMacroHeight, UINT_64* pSliceSize = NULL,
UINT_32* pBaseAlign = NULL, UINT_32* pBlockMax = NULL) const;
virtual VOID HwlComputeTileDataWidthAndHeightLinear(
UINT_32* pMacroWidth, UINT_32* pMacroHeight,
UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
// CMASK & HTILE addressing
virtual UINT_64 HwlComputeXmaskAddrFromCoord(
UINT_32 pitch, UINT_32 height, UINT_32 x, UINT_32 y, UINT_32 slice,
UINT_32 numSlices, UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8,
BOOL_32 isHeight8, ADDR_TILEINFO* pTileInfo,
UINT_32* bitPosition) const;
virtual VOID HwlComputeXmaskCoordFromAddr(
UINT_64 addr, UINT_32 bitPosition, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
// Surface mipmap
VOID ComputeMipLevel(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
/// Pure Virtual function for Hwl to get macro tiled alignment info
virtual BOOL_32 HwlGetAlignmentInfoMacroTiled(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32* pPitchAlign, UINT_32* pHeightAlign, UINT_32* pSizeAlign) const = 0;
virtual VOID HwlOverrideTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const
{
// not supported in hwl layer
}
virtual VOID HwlOptimizeTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const
{
// not supported in hwl layer
}
virtual VOID HwlSelectTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const
{
// not supported in hwl layer
}
AddrTileMode DegradeLargeThickTile(AddrTileMode tileMode, UINT_32 bpp) const;
VOID PadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32* pPitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
UINT_32* pSlices, UINT_32 sliceAlign) const;
virtual VOID HwlPadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32* pPitchAlign, UINT_32 height, UINT_32 heightAlign) const
{
}
//
// Addressing shared for linear/1D tiling
//
UINT_64 ComputeSurfaceAddrFromCoordLinear(
UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
UINT_32* pBitPosition) const;
VOID ComputeSurfaceCoordFromAddrLinear(
UINT_64 addr, UINT_32 bitPosition, UINT_32 bpp,
UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample) const;
VOID ComputeSurfaceCoordFromAddrMicroTiled(
UINT_64 addr, UINT_32 bitPosition,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample,
AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const;
ADDR_E_RETURNCODE ComputeMicroTileEquation(
UINT_32 bpp, AddrTileMode tileMode,
AddrTileType microTileType, ADDR_EQUATION* pEquation) const;
UINT_32 ComputePixelIndexWithinMicroTile(
UINT_32 x, UINT_32 y, UINT_32 z,
UINT_32 bpp, AddrTileMode tileMode, AddrTileType microTileType) const;
/// Pure Virtual function for Hwl computing coord from offset inside micro tile
virtual VOID HwlComputePixelCoordFromOffset(
UINT_32 offset, UINT_32 bpp, UINT_32 numSamples,
AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample,
AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const = 0;
//
// Addressing shared by all
//
virtual UINT_32 HwlGetPipes(
const ADDR_TILEINFO* pTileInfo) const;
UINT_32 ComputePipeFromAddr(
UINT_64 addr, UINT_32 numPipes) const;
virtual ADDR_E_RETURNCODE ComputePipeEquation(
UINT_32 log2BytesPP, UINT_32 threshX, UINT_32 threshY, ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const
{
return ADDR_NOTSUPPORTED;
}
/// Pure Virtual function for Hwl computing pipe from coord
virtual UINT_32 ComputePipeFromCoord(
UINT_32 x, UINT_32 y, UINT_32 slice, AddrTileMode tileMode,
UINT_32 pipeSwizzle, BOOL_32 flags, ADDR_TILEINFO* pTileInfo) const = 0;
/// Pure Virtual function for Hwl computing coord Y for 8 pipe cmask/htile
virtual UINT_32 HwlComputeXmaskCoordYFrom8Pipe(
UINT_32 pipe, UINT_32 x) const = 0;
//
// Misc helper
//
static const TileModeFlags ModeFlags[ADDR_TM_COUNT];
static UINT_32 Thickness(
AddrTileMode tileMode);
// Checking tile mode
static BOOL_32 IsMacroTiled(AddrTileMode tileMode);
static BOOL_32 IsMacro3dTiled(AddrTileMode tileMode);
static BOOL_32 IsLinear(AddrTileMode tileMode);
static BOOL_32 IsMicroTiled(AddrTileMode tileMode);
static BOOL_32 IsPrtTileMode(AddrTileMode tileMode);
static BOOL_32 IsPrtNoRotationTileMode(AddrTileMode tileMode);
/// Return TRUE if tile info is needed
BOOL_32 UseTileInfo() const
{
return !m_configFlags.ignoreTileInfo;
}
/// Adjusts pitch alignment for flipping surface
VOID AdjustPitchAlignment(
ADDR_SURFACE_FLAGS flags, UINT_32* pPitchAlign) const;
/// Overwrite tile config according to tile index
virtual ADDR_E_RETURNCODE HwlSetupTileCfg(
UINT_32 bpp, INT_32 index, INT_32 macroModeIndex,
ADDR_TILEINFO* pInfo, AddrTileMode* mode = NULL, AddrTileType* type = NULL) const;
/// Overwrite macro tile config according to tile index
virtual INT_32 HwlComputeMacroModeIndex(
INT_32 index, ADDR_SURFACE_FLAGS flags, UINT_32 bpp, UINT_32 numSamples,
ADDR_TILEINFO* pTileInfo, AddrTileMode *pTileMode = NULL, AddrTileType *pTileType = NULL
) const
{
return TileIndexNoMacroIndex;
}
/// Pre-handler of 3x pitch (96 bit) adjustment
virtual UINT_32 HwlPreHandleBaseLvl3xPitch(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
/// Post-handler of 3x pitch adjustment
virtual UINT_32 HwlPostHandleBaseLvl3xPitch(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
/// Check miplevel after surface adjustment
ADDR_E_RETURNCODE PostComputeMipLevel(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
/// Quad buffer stereo support, has its implementation in ind. layer
VOID ComputeQbStereoInfo(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
/// Pure virutual function to compute stereo bank swizzle for right eye
virtual UINT_32 HwlComputeQbStereoRightSwizzle(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
VOID OptimizeTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
/// Overwrite tile setting to PRT
virtual VOID HwlSetPrtTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const
{
}
static BOOL_32 DegradeTo1D(
UINT_32 width, UINT_32 height,
UINT_32 macroTilePitchAlign, UINT_32 macroTileHeightAlign);
private:
// Disallow the copy constructor
Lib(const Lib& a);
// Disallow the assignment operator
Lib& operator=(const Lib& a);
UINT_32 ComputeCmaskBaseAlign(
ADDR_CMASK_FLAGS flags, ADDR_TILEINFO* pTileInfo) const;
UINT_64 ComputeCmaskBytes(
UINT_32 pitch, UINT_32 height, UINT_32 numSlices) const;
//
// CMASK/HTILE shared methods
//
VOID ComputeTileDataWidthAndHeight(
UINT_32 bpp, UINT_32 cacheBits, ADDR_TILEINFO* pTileInfo,
UINT_32* pMacroWidth, UINT_32* pMacroHeight) const;
UINT_32 ComputeXmaskCoordYFromPipe(
UINT_32 pipe, UINT_32 x) const;
};
} // V1
} // Addr
#endif
src/amd/addrlib/src/core/addrlib2.cpp
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src/amd/addrlib/src/core/addrlib2.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
************************************************************************************************************************
* @file addrlib2.h
* @brief Contains the Addr::V2::Lib class definition.
************************************************************************************************************************
*/
#ifndef __ADDR2_LIB2_H__
#define __ADDR2_LIB2_H__
#include "addrlib.h"
namespace Addr
{
namespace V2
{
/**
************************************************************************************************************************
* @brief Flags for SwizzleModeTable
************************************************************************************************************************
*/
union SwizzleModeFlags
{
struct
{
// Swizzle mode
UINT_32 isLinear : 1; // Linear
// Block size
UINT_32 is256b : 1; // Block size is 256B
UINT_32 is4kb : 1; // Block size is 4KB
UINT_32 is64kb : 1; // Block size is 64KB
UINT_32 isVar : 1; // Block size is variable
UINT_32 isZ : 1; // Z order swizzle mode
UINT_32 isStd : 1; // Standard swizzle mode
UINT_32 isDisp : 1; // Display swizzle mode
UINT_32 isRot : 1; // Rotate swizzle mode
// XOR mode
UINT_32 isXor : 1; // XOR after swizzle if set
UINT_32 isT : 1; // T mode
// GFX10
UINT_32 isRtOpt : 1; // mode opt for render target
UINT_32 reserved : 20; // Reserved bits
};
UINT_32 u32All;
};
struct Dim2d
{
UINT_32 w;
UINT_32 h;
};
struct Dim3d
{
UINT_32 w;
UINT_32 h;
UINT_32 d;
};
enum AddrSwSet
{
AddrSwSetZ = 1 << ADDR_SW_Z,
AddrSwSetS = 1 << ADDR_SW_S,
AddrSwSetD = 1 << ADDR_SW_D,
AddrSwSetR = 1 << ADDR_SW_R,
AddrSwSetAll = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR,
};
const UINT_32 Size256 = 256u;
const UINT_32 Size4K = 4096u;
const UINT_32 Size64K = 65536u;
const UINT_32 Log2Size256 = 8u;
const UINT_32 Log2Size4K = 12u;
const UINT_32 Log2Size64K = 16u;
/**
************************************************************************************************************************
* @brief Swizzle pattern information
************************************************************************************************************************
*/
// Accessed by index representing the logbase2 of (8bpp/16bpp/32bpp/64bpp/128bpp)
// contains the indices which map to 2D arrays SW_PATTERN_NIBBLE[0-9] which contain sections of an index equation. They are dependant on pipe# and bpe #
struct ADDR_SW_PATINFO
{
UINT_8 maxItemCount;
UINT_8 nibble01Idx;
UINT_16 nibble2Idx;
UINT_16 nibble3Idx;
UINT_8 nibble4Idx;
};
/**
************************************************************************************************************************
* @brief This class contains asic independent address lib functionalities
************************************************************************************************************************
*/
class Lib : public Addr::Lib
{
public:
virtual ~Lib();
static Lib* GetLib(
ADDR_HANDLE hLib);
virtual UINT_32 GetInterfaceVersion() const override
{
return 2;
}
//
// Interface stubs
//
// For data surface
ADDR_E_RETURNCODE ComputeSurfaceInfo(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr(
const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
ADDR_E_RETURNCODE CopyMemToSurface(
const ADDR2_COPY_MEMSURFACE_INPUT* pIn,
const ADDR2_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const;
ADDR_E_RETURNCODE CopySurfaceToMem(
const ADDR2_COPY_MEMSURFACE_INPUT* pIn,
const ADDR2_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const;
// For HTile
ADDR_E_RETURNCODE ComputeHtileInfo(
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeHtileAddrFromCoord(
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeHtileCoordFromAddr(
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
// For CMask
ADDR_E_RETURNCODE ComputeCmaskInfo(
const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord(
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr(
const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const;
// For FMask
ADDR_E_RETURNCODE ComputeFmaskInfo(
const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord(
const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr(
const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
// For DCC key
ADDR_E_RETURNCODE ComputeDccInfo(
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
// Misc
ADDR_E_RETURNCODE ComputePipeBankXor(
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeSlicePipeBankXor(
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeSubResourceOffsetForSwizzlePattern(
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeNonBlockCompressedView(
const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn,
ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut);
ADDR_E_RETURNCODE Addr2GetPreferredSurfaceSetting(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetPossibleSwizzleModes(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const;
virtual BOOL_32 IsValidDisplaySwizzleMode(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTIMPLEMENTED;
}
ADDR_E_RETURNCODE GetAllowedBlockSet(
ADDR2_SWMODE_SET allowedSwModeSet,
AddrResourceType rsrcType,
ADDR2_BLOCK_SET* pAllowedBlockSet) const;
ADDR_E_RETURNCODE GetAllowedSwSet(
ADDR2_SWMODE_SET allowedSwModeSet,
ADDR2_SWTYPE_SET* pAllowedSwSet) const;
protected:
Lib(); // Constructor is protected
Lib(const Client* pClient);
static const UINT_32 MaxNumOfBpp = 5;
static const UINT_32 MaxNumOfBppCMask = 4;
static const UINT_32 MaxNumOfAA = 4;
static const Dim2d Block256_2d[MaxNumOfBpp];
static const Dim3d Block1K_3d[MaxNumOfBpp];
static const UINT_32 PrtAlignment = 64 * 1024;
static const UINT_32 MaxMacroBits = 20;
static const UINT_32 MaxMipLevels = 16;
BOOL_32 IsValidSwMode(AddrSwizzleMode swizzleMode) const
{
return (m_swizzleModeTable[swizzleMode].u32All != 0);
}
// Checking block size
BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].is256b;
}
BOOL_32 IsBlock4kb(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].is4kb;
}
BOOL_32 IsBlock64kb(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].is64kb;
}
BOOL_32 IsBlockVariable(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isVar;
}
// Checking swizzle mode
BOOL_32 IsLinear(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isLinear;
}
BOOL_32 IsRtOptSwizzle(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isRtOpt;
}
BOOL_32 IsZOrderSwizzle(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isZ;
}
BOOL_32 IsStandardSwizzle(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isStd;
}
BOOL_32 IsDisplaySwizzle(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isDisp;
}
BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isRot;
}
BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
{
return HwlIsStandardSwizzle(resourceType, swizzleMode);
}
BOOL_32 IsDisplaySwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
{
return HwlIsDisplaySwizzle(resourceType, swizzleMode);
}
BOOL_32 IsXor(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isXor;
}
BOOL_32 IsPrt(AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isT;
}
BOOL_32 IsNonPrtXor(AddrSwizzleMode swizzleMode) const
{
return (IsXor(swizzleMode) && (IsPrt(swizzleMode) == FALSE));
}
// Checking resource type
static BOOL_32 IsTex1d(AddrResourceType resourceType)
{
return (resourceType == ADDR_RSRC_TEX_1D);
}
static BOOL_32 IsTex2d(AddrResourceType resourceType)
{
return (resourceType == ADDR_RSRC_TEX_2D);
}
static BOOL_32 IsTex3d(AddrResourceType resourceType)
{
return (resourceType == ADDR_RSRC_TEX_3D);
}
BOOL_32 IsThick(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
{
return HwlIsThick(resourceType, swizzleMode);
}
BOOL_32 IsThin(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
{
return HwlIsThin(resourceType, swizzleMode);
}
UINT_32 GetBlockSizeLog2(AddrSwizzleMode swizzleMode) const
{
UINT_32 blockSizeLog2 = 0;
if (IsBlock256b(swizzleMode) || IsLinear(swizzleMode))
{
blockSizeLog2 = 8;
}
else if (IsBlock4kb(swizzleMode))
{
blockSizeLog2 = 12;
}
else if (IsBlock64kb(swizzleMode))
{
blockSizeLog2 = 16;
}
else if (IsBlockVariable(swizzleMode) && (m_blockVarSizeLog2 != 0))
{
blockSizeLog2 = m_blockVarSizeLog2;
}
else
{
ADDR_ASSERT_ALWAYS();
}
return blockSizeLog2;
}
UINT_32 GetBlockSize(AddrSwizzleMode swizzleMode) const
{
return (1 << GetBlockSizeLog2(swizzleMode));
}
static UINT_32 GetFmaskBpp(UINT_32 sample, UINT_32 frag)
{
sample = (sample == 0) ? 1 : sample;
frag = (frag == 0) ? sample : frag;
UINT_32 fmaskBpp = Log2(frag);
if (sample > frag)
{
fmaskBpp++;
}
if (fmaskBpp == 3)
{
fmaskBpp = 4;
}
fmaskBpp = Max(8u, fmaskBpp * sample);
return fmaskBpp;
}
virtual BOOL_32 HwlIsStandardSwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
ADDR_NOT_IMPLEMENTED();
return FALSE;
}
virtual BOOL_32 HwlIsDisplaySwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
ADDR_NOT_IMPLEMENTED();
return FALSE;
}
virtual BOOL_32 HwlIsThin(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
ADDR_NOT_IMPLEMENTED();
return FALSE;
}
virtual BOOL_32 HwlIsThick(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
ADDR_NOT_IMPLEMENTED();
return FALSE;
}
virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo(
const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn)
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual VOID HwlComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut)
{
ADDR_NOT_IMPLEMENTED();
}
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut)
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut)
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut)
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation(
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
UINT_32 elementBytesLog2,
ADDR_EQUATION* pEquation) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeThinEquation(
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
UINT_32 elementBytesLog2,
ADDR_EQUATION* pEquation) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeThickEquation(
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
UINT_32 elementBytesLog2,
ADDR_EQUATION* pEquation) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual UINT_32 HwlGetEquationIndex(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_INVALID_EQUATION_INDEX;
}
UINT_32 GetEquationIndex(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
{
return HwlGetEquationIndex(pIn, pOut);
}
virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView(
const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn,
ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlGetPossibleSwizzleModes(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlGetAllowedBlockSet(
ADDR2_SWMODE_SET allowedSwModeSet,
AddrResourceType rsrcType,
ADDR2_BLOCK_SET* pAllowedBlockSet) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTIMPLEMENTED;
}
virtual ADDR_E_RETURNCODE HwlGetAllowedSwSet(
ADDR2_SWMODE_SET allowedSwModeSet,
ADDR2_SWTYPE_SET* pAllowedSwSet) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTIMPLEMENTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTIMPLEMENTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTIMPLEMENTED;
}
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTIMPLEMENTED;
}
virtual ADDR_E_RETURNCODE HwlCopyMemToSurface(
const ADDR2_COPY_MEMSURFACE_INPUT* pIn,
const ADDR2_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlCopySurfaceToMem(
const ADDR2_COPY_MEMSURFACE_INPUT* pIn,
const ADDR2_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
ADDR_E_RETURNCODE ComputeBlock256Equation(
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
UINT_32 elementBytesLog2,
ADDR_EQUATION* pEquation) const;
ADDR_E_RETURNCODE ComputeThinEquation(
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
UINT_32 elementBytesLog2,
ADDR_EQUATION* pEquation) const;
ADDR_E_RETURNCODE ComputeThickEquation(
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
UINT_32 elementBytesLog2,
ADDR_EQUATION* pEquation) const;
ADDR_E_RETURNCODE ComputeSurfaceInfoSanityCheck(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
ADDR_E_RETURNCODE ComputeSurfaceInfoLinear(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceInfoTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE CopyLinearSurface(
const ADDR2_COPY_MEMSURFACE_INPUT* pIn,
const ADDR2_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount,
bool surfaceIsDst) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordLinear(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrLinear(
const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrTiled(
const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
UINT_32 ComputeSurface2DMicroBlockOffset(
const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const;
UINT_32 ComputeSurface3DMicroBlockOffset(
const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const;
// Misc
ADDR_E_RETURNCODE ComputeBlockDimensionForSurf(
UINT_32* pWidth,
UINT_32* pHeight,
UINT_32* pDepth,
UINT_32 bpp,
UINT_32 numSamples,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const;
ADDR_E_RETURNCODE ComputeBlockDimension(
UINT_32* pWidth,
UINT_32* pHeight,
UINT_32* pDepth,
UINT_32 bpp,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const;
virtual VOID ComputeThinBlockDimension(
UINT_32* pWidth,
UINT_32* pHeight,
UINT_32* pDepth,
UINT_32 bpp,
UINT_32 numSamples,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const;
VOID ComputeThickBlockDimension(
UINT_32* pWidth,
UINT_32* pHeight,
UINT_32* pDepth,
UINT_32 bpp,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const;
static UINT_64 ComputePadSize(
const Dim3d* pBlkDim,
UINT_32 width,
UINT_32 height,
UINT_32 numSlices,
Dim3d* pPadDim)
{
pPadDim->w = PowTwoAlign(width ,pBlkDim->w);
pPadDim->h = PowTwoAlign(height ,pBlkDim->h);
pPadDim->d = PowTwoAlign(numSlices, pBlkDim->d);
return static_cast<UINT_64>(pPadDim->w) * pPadDim->h * pPadDim->d;
}
static ADDR_E_RETURNCODE ExtractPipeBankXor(
UINT_32 pipeBankXor,
UINT_32 bankBits,
UINT_32 pipeBits,
UINT_32* pBankX,
UINT_32* pPipeX);
static BOOL_32 Valid3DMipSliceIdConstraint(
UINT_32 numSlices,
UINT_32 mipId,
UINT_32 slice)
{
return (Max((numSlices >> mipId), 1u) > slice);
}
Dim3d GetMipTailDim(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 blockWidth,
UINT_32 blockHeight,
UINT_32 blockDepth) const;
static BOOL_32 IsLocalHeap(AddrResrouceLocation resourceType)
{
return ((resourceType == ADDR_RSRC_LOC_LOCAL) ||
(resourceType == ADDR_RSRC_LOC_INVIS));
}
static BOOL_32 IsInvisibleHeap(AddrResrouceLocation resourceType)
{
return (resourceType == ADDR_RSRC_LOC_INVIS);
}
static BOOL_32 IsNonlocalHeap(AddrResrouceLocation resourceType)
{
return ((resourceType == ADDR_RSRC_LOC_USWC) ||
(resourceType == ADDR_RSRC_LOC_CACHED));
}
UINT_32 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const
{
UINT_32 numPipeLog2 = pipeAligned ? Min(m_pipesLog2 + m_seLog2, 5u) : 0;
if (IsXor(swizzleMode))
{
UINT_32 maxPipeLog2 = GetBlockSizeLog2(swizzleMode) - m_pipeInterleaveLog2;
numPipeLog2 = Min(numPipeLog2, maxPipeLog2);
}
return numPipeLog2;
}
UINT_32 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const
{
return (1 << GetPipeLog2ForMetaAddressing(pipeAligned, swizzleMode));
}
VOID VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
{
#if DEBUG
if (pIn->numMipLevels > 1)
{
UINT_32 actualMipLevels = 1;
switch (pIn->resourceType)
{
case ADDR_RSRC_TEX_3D:
// Fall through to share 2D case
actualMipLevels = Max(actualMipLevels, Log2(pIn->numSlices) + 1);
case ADDR_RSRC_TEX_2D:
// Fall through to share 1D case
actualMipLevels = Max(actualMipLevels, Log2(pIn->height) + 1);
case ADDR_RSRC_TEX_1D:
// Base 1D case
actualMipLevels = Max(actualMipLevels, Log2(pIn->width) + 1);
break;
default:
ADDR_ASSERT_ALWAYS();
break;
}
// Client pass wrong number of MipLevels to addrlib and result will be bad.
// Not sure if we should fail this calling instead of putting an assertion here.
ADDR_ASSERT(actualMipLevels >= pIn->numMipLevels);
}
#endif
}
ADDR_E_RETURNCODE ApplyCustomerPipeBankXor(
AddrSwizzleMode swizzleMode,
UINT_32 pipeBankXor,
UINT_32 bankBits,
UINT_32 pipeBits,
UINT_32* pBlockOffset) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (IsXor(swizzleMode))
{
// Apply driver set bankPipeXor
UINT_32 bankX = 0;
UINT_32 pipeX = 0;
returnCode = ExtractPipeBankXor(pipeBankXor, bankBits, pipeBits, &bankX, &pipeX);
*pBlockOffset ^= (pipeX << m_pipeInterleaveLog2);
*pBlockOffset ^= (bankX << (m_pipeInterleaveLog2 + pipeBits));
}
return returnCode;
}
UINT_32 GetPipeXorBits(UINT_32 macroBlockBits) const;
ADDR_E_RETURNCODE ApplyCustomizedPitchHeight(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32 elementBytes,
UINT_32 pitchAlignInElement,
UINT_32* pPitch,
UINT_32* pHeight) const;
VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
VOID FilterInvalidEqSwizzleMode(
ADDR2_SWMODE_SET& allowedSwModeSet,
AddrResourceType resourceType,
UINT_32 elemLog2,
UINT_32 maxComponents) const;
#if DEBUG
VOID ValidateStereoInfo(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
const ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
#endif
UINT_32 m_se; ///< Number of shader engine
UINT_32 m_rbPerSe; ///< Number of render backend per shader engine
UINT_32 m_maxCompFrag; ///< Number of max compressed fragment
UINT_32 m_banksLog2; ///< Number of bank Log2
UINT_32 m_pipesLog2; ///< Number of pipe per shader engine Log2
UINT_32 m_seLog2; ///< Number of shader engine Log2
UINT_32 m_rbPerSeLog2; ///< Number of render backend per shader engine Log2
UINT_32 m_maxCompFragLog2; ///< Number of max compressed fragment Log2
UINT_32 m_pipeInterleaveLog2; ///< Log2 of pipe interleave bytes
UINT_32 m_blockVarSizeLog2; ///< Log2 of block var size
SwizzleModeFlags m_swizzleModeTable[ADDR_SW_MAX_TYPE]; ///< Swizzle mode table
// Max number of swizzle mode supported for equation
static const UINT_32 MaxSwModeType = 32;
// Max number of resource type (2D/3D) supported for equation
static const UINT_32 MaxRsrcType = 2;
// Almost all swizzle mode + resource type support equation
static const UINT_32 EquationTableSize = MaxElementBytesLog2 * MaxSwModeType * MaxRsrcType;
// Equation table
ADDR_EQUATION m_equationTable[EquationTableSize];
// Number of equation entries in the table
UINT_32 m_numEquations;
// Equation lookup table according to bpp and tile index
UINT_32 m_equationLookupTable[MaxRsrcType][MaxSwModeType][MaxElementBytesLog2];
private:
// Disallow the copy constructor
Lib(const Lib& a);
// Disallow the assignment operator
Lib& operator=(const Lib& a);
};
} // V2
} // Addr
#endif
src/amd/addrlib/src/core/addrlib3.cpp
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src/amd/addrlib/src/core/addrlib3.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
************************************************************************************************************************
* @file addrlib3.h
* @brief Contains the Addr::V3::Lib class definition.
************************************************************************************************************************
*/
#ifndef __ADDR3_LIB3_H__
#define __ADDR3_LIB3_H__
#include "addrlib.h"
namespace Addr
{
namespace V3
{
constexpr UINT_32 Size256 = 256u;
constexpr UINT_32 Size4K = 4 * 1024;
constexpr UINT_32 Size64K = 64 * 1024;
constexpr UINT_32 Size256K = 256 * 1024;
constexpr UINT_32 Addr3MaxMipLevels = 16; // Max Mip Levels across all addr3 chips
struct ADDR3_COORD
{
INT_32 x;
INT_32 y;
INT_32 z;
};
// The HW address library utilizes an "addr_params" structure that is GPU-specific; therefore, we use a "void" pointer
// here to allow the HWL's to interpret this pointer with the appropriate structure.
// To reduce the frequency of conversion between the "ADDR3_COMPUTE_SURFACE_INFO_INPUT" structure and the "addr_params"
// structure, we create this super-structure to tie the two structures together.
struct ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT
{
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pSurfInfo;
};
/**
************************************************************************************************************************
* @brief Flags for SwizzleModeTable
************************************************************************************************************************
*/
union SwizzleModeFlags
{
struct
{
// Swizzle mode
UINT_32 isLinear : 1; // Linear
UINT_32 is2d : 1; // 2d mode
UINT_32 is3d : 1; // 3d mode
// Block size
UINT_32 is256b : 1; // Block size is 256B
UINT_32 is4kb : 1; // Block size is 4KB
UINT_32 is64kb : 1; // Block size is 64KB
UINT_32 is256kb : 1; // Block size is 256KB
UINT_32 reserved : 25; // Reserved bits
};
UINT_32 u32All;
};
const UINT_32 Log2Size256 = 8u;
const UINT_32 Log2Size256K = 18u;
/**
************************************************************************************************************************
* @brief Swizzle pattern information
************************************************************************************************************************
*/
// Accessed by index representing the logbase2 of (8bpp/16bpp/32bpp/64bpp/128bpp)
// contains the indices which map to 2D arrays SW_PATTERN_NIBBLE[1-4] which contain sections of an index equation.
struct ADDR_SW_PATINFO
{
UINT_8 nibble1Idx;
UINT_8 nibble2Idx;
UINT_8 nibble3Idx;
UINT_8 nibble4Idx;
};
/**
************************************************************************************************************************
* @brief This class contains asic independent address lib functionalities
************************************************************************************************************************
*/
class Lib : public Addr::Lib
{
public:
virtual ~Lib();
static Lib* GetLib(
ADDR_HANDLE hLib);
UINT_32 GetInterfaceVersion() const override { return 3; }
//
// Interface stubs
//
// For data surface
ADDR_E_RETURNCODE ComputeSurfaceInfo(
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetPossibleSwizzleModes(
const ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT* pIn,
ADDR3_GET_POSSIBLE_SWIZZLE_MODE_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord(
const ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE CopyMemToSurface(
const ADDR3_COPY_MEMSURFACE_INPUT* pIn,
const ADDR3_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const;
ADDR_E_RETURNCODE CopySurfaceToMem(
const ADDR3_COPY_MEMSURFACE_INPUT* pIn,
const ADDR3_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const;
// Misc
ADDR_E_RETURNCODE ComputePipeBankXor(
const ADDR3_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeNonBlockCompressedView(
const ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn,
ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeSubResourceOffsetForSwizzlePattern(
const ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeSlicePipeBankXor(
const ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut);
protected:
Lib(); // Constructor is protected
Lib(const Client* pClient);
SwizzleModeFlags m_swizzleModeTable[ADDR3_MAX_TYPE]; ///< Swizzle mode table
// Number of unique MSAA sample rates (1/2/4/8)
static const UINT_32 MaxNumMsaaRates = 4;
//# These fields exist in the GB_ADDR_CONFIG register; however, the HW does not care about them.
//# The HW acts as if the log2(pipes)==5 and log2(pi) == 8, always.
static const UINT_32 NumPipesLog2 = 5;
static const UINT_32 PipeInterleaveLog2 = 8;
// Number of equation entries in the table
UINT_32 m_numEquations;
// Swizzle equation lookup table according to swizzle mode, MSAA sample rate and bpp. This does not include linear.
UINT_32 m_equationLookupTable[ADDR3_MAX_TYPE - 1][MaxNumMsaaRates][MaxElementBytesLog2];
// Block dimension lookup table according to swizzle mode, MSAA sample rate and bpp. This includes linear.
ADDR_EXTENT3D m_blockDimensionTable[ADDR3_MAX_TYPE][MaxNumMsaaRates][MaxElementBytesLog2];
virtual ADDR_E_RETURNCODE HwlComputeStereoInfo(
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32* pAlignY,
UINT_32* pRightXor) const = 0;
void SetEquationTableEntry(
Addr3SwizzleMode swMode,
UINT_32 msaaLog2,
UINT_32 elementBytesLog2,
UINT_32 value)
{
// m_equationLookupTable doesn't include linear, so we must exclude linear when calling this function.
ADDR_ASSERT(swMode != ADDR3_LINEAR);
m_equationLookupTable[swMode - 1][msaaLog2][elementBytesLog2] = value;
}
const UINT_32 GetEquationTableEntry(
Addr3SwizzleMode swMode,
UINT_32 msaaLog2,
UINT_32 elementBytesLog2) const
{
UINT_32 res = ADDR_INVALID_EQUATION_INDEX;
// m_equationLookupTable doesn't include linear
if (swMode != ADDR3_LINEAR)
{
res = m_equationLookupTable[swMode - 1][msaaLog2][elementBytesLog2];
}
return res;
}
static UINT_32 ComputeOffsetFromEquation(
const ADDR_EQUATION* pEq,
UINT_32 x,
UINT_32 y,
UINT_32 z,
UINT_32 s);
const ADDR_EXTENT3D GetBlockDimensionTableEntry(
Addr3SwizzleMode swMode,
UINT_32 msaaLog2,
UINT_32 elementBytesLog2) const
{
return m_blockDimensionTable[swMode][msaaLog2][elementBytesLog2];
}
static BOOL_32 Valid3DMipSliceIdConstraint(
UINT_32 numSlices,
UINT_32 mipId,
UINT_32 slice)
{
return (Max((numSlices >> mipId), 1u) > slice);
}
UINT_32 GetBlockSize(
Addr3SwizzleMode swizzleMode,
BOOL_32 forPitch = FALSE) const;
UINT_32 GetBlockSizeLog2(
Addr3SwizzleMode swizzleMode,
BOOL_32 forPitch = FALSE) const;
BOOL_32 IsValidSwMode(Addr3SwizzleMode swizzleMode) const
{
return (m_swizzleModeTable[swizzleMode].u32All != 0);
}
UINT_32 IsLinear(Addr3SwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isLinear;
}
// Checking block size
BOOL_32 IsBlock256b(Addr3SwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].is256b;
}
// Checking block size
BOOL_32 IsBlock4kb(Addr3SwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].is4kb;
}
// Checking block size
BOOL_32 IsBlock64kb(Addr3SwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].is64kb;
}
// Checking block size
BOOL_32 IsBlock256kb(Addr3SwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].is256kb;
}
BOOL_32 Is2dSwizzle(Addr3SwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].is2d;
}
BOOL_32 Is3dSwizzle(Addr3SwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].is3d;
}
// miptail is applied to only larger block size (4kb, 64kb, 256kb), so there is no miptail in linear and
// 256b_2d addressing since they are both 256b block.
BOOL_32 SupportsMipTail(Addr3SwizzleMode swizzleMode) const
{
return GetBlockSize(swizzleMode) > 256u;
}
// The max alignment is tied to the swizzle mode and since the largest swizzle mode is 256kb, so the maximal
// alignment is also 256kb.
UINT_32 HwlComputeMaxBaseAlignments() const override { return Size256K; }
virtual ADDR_E_RETURNCODE HwlGetPossibleSwizzleModes(
const ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT* pIn,
ADDR3_GET_POSSIBLE_SWIZZLE_MODE_OUTPUT* pOut) const = 0;
UINT_32 HwlComputeMaxMetaBaseAlignments() const override { return 0; }
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlCopyMemToSurface(
const ADDR3_COPY_MEMSURFACE_INPUT* pIn,
const ADDR3_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlCopySurfaceToMem(
const ADDR3_COPY_MEMSURFACE_INPUT* pIn,
const ADDR3_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
const ADDR3_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
VOID ComputeBlockDimensionForSurf(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn,
ADDR_EXTENT3D* pExtent) const;
ADDR_EXTENT3D GetMipTailDim(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn,
const ADDR_EXTENT3D& blockDims) const;
ADDR_E_RETURNCODE CopyLinearSurface(
const ADDR3_COPY_MEMSURFACE_INPUT* pIn,
const ADDR3_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount,
bool surfaceIsDst) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordLinear(
const ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordLinear(
const ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pSurfInfoIn,
ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const = 0;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordTiled(
const ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
const ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTIMPLEMENTED;
}
virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView(
const ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn,
ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual VOID HwlComputeSubResourceOffsetForSwizzlePattern(
const ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
}
virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
const ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_NOTSUPPORTED;
}
virtual UINT_32 HwlGetEquationIndex(
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn) const
{
ADDR_NOT_IMPLEMENTED();
return ADDR_INVALID_EQUATION_INDEX;
}
void SetEquationIndex(
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
{
UINT_32 equationIdx = HwlGetEquationIndex(pIn);
if (pOut->pMipInfo != NULL)
{
for (UINT_32 i = 0; i < pIn->numMipLevels; i++)
{
pOut->pMipInfo[i].equationIndex = equationIdx;
}
}
}
ADDR_E_RETURNCODE ApplyCustomizedPitchHeight(
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
BOOL_32 UseCustomHeight(const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
BOOL_32 UseCustomPitch(const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
BOOL_32 CanTrimLinearPadding(const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
virtual VOID HwlCalcBlockSize(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn,
ADDR_EXTENT3D* pExtent) const = 0;
virtual ADDR_EXTENT3D HwlGetMipInTailMaxSize(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn,
const ADDR_EXTENT3D& blockDims) const = 0;
virtual BOOL_32 HwlValidateNonSwModeParams(const ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT* pIn) const = 0;
ADDR_E_RETURNCODE ComputeSurfaceInfoSanityCheck(const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
private:
// Disallow the copy constructor
Lib(const Lib& a);
// Disallow the assignment operator
Lib& operator=(const Lib& a);
void Init();
VOID ComputeQbStereoInfo(ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
};
} // V3
} // Addr
#endif
src/amd/addrlib/src/core/addrobject.cpp
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
****************************************************************************************************
* @file addrobject.cpp
* @brief Contains the Object base class implementation.
****************************************************************************************************
*/
#include "addrinterface.h"
#include "addrobject.h"
#if DEBUG
#include <stdio.h>
#endif
namespace Addr
{
#if DEBUG && ADDR_ALLOW_TLS
thread_local ADDR_CLIENT_HANDLE g_clientHandle = nullptr;
thread_local ADDR_DEBUGPRINT g_pfnDebugPrint = nullptr;
#endif
/**
****************************************************************************************************
* Object::Object
*
* @brief
* Constructor for the Object class.
****************************************************************************************************
*/
Object::Object()
{
m_client.handle = NULL;
m_client.callbacks.allocSysMem = NULL;
m_client.callbacks.freeSysMem = NULL;
m_client.callbacks.debugPrint = NULL;
}
/**
****************************************************************************************************
* Object::Object
*
* @brief
* Constructor for the Object class.
****************************************************************************************************
*/
Object::Object(const Client* pClient)
{
m_client = *pClient;
}
/**
****************************************************************************************************
* Object::~Object
*
* @brief
* Destructor for the Object class.
****************************************************************************************************
*/
Object::~Object()
{
}
/**
****************************************************************************************************
* Object::ClientAlloc
*
* @brief
* Calls instanced allocSysMem inside Client
****************************************************************************************************
*/
VOID* Object::ClientAlloc(
size_t objSize, ///< [in] Size to allocate
const Client* pClient) ///< [in] Client pointer
{
VOID* pObjMem = NULL;
if (pClient->callbacks.allocSysMem != NULL)
{
ADDR_ALLOCSYSMEM_INPUT allocInput = {0};
allocInput.size = sizeof(ADDR_ALLOCSYSMEM_INPUT);
allocInput.flags.value = 0;
allocInput.sizeInBytes = static_cast<UINT_32>(objSize);
allocInput.hClient = pClient->handle;
pObjMem = pClient->callbacks.allocSysMem(&allocInput);
}
return pObjMem;
}
/**
****************************************************************************************************
* Object::Alloc
*
* @brief
* A wrapper of ClientAlloc
****************************************************************************************************
*/
VOID* Object::Alloc(
size_t objSize ///< [in] Size to allocate
) const
{
return ClientAlloc(objSize, &m_client);;
}
/**
****************************************************************************************************
* Object::ClientFree
*
* @brief
* Calls freeSysMem inside Client
****************************************************************************************************
*/
VOID Object::ClientFree(
VOID* pObjMem, ///< [in] User virtual address to free.
const Client* pClient) ///< [in] Client pointer
{
if (pClient->callbacks.freeSysMem != NULL)
{
if (pObjMem != NULL)
{
ADDR_FREESYSMEM_INPUT freeInput = {0};
freeInput.size = sizeof(ADDR_FREESYSMEM_INPUT);
freeInput.hClient = pClient->handle;
freeInput.pVirtAddr = pObjMem;
pClient->callbacks.freeSysMem(&freeInput);
}
}
}
/**
****************************************************************************************************
* Object::Free
*
* @brief
* A wrapper of ClientFree
****************************************************************************************************
*/
VOID Object::Free(
VOID* pObjMem ///< [in] User virtual address to free.
) const
{
ClientFree(pObjMem, &m_client);
}
/**
****************************************************************************************************
* Object::operator new
*
* @brief
* Placement new operator. (with pre-allocated memory pointer)
*
* @return
* Returns pre-allocated memory pointer.
****************************************************************************************************
*/
VOID* Object::operator new(
size_t objSize, ///< [in] Size to allocate
VOID* pMem ///< [in] Pre-allocated pointer
) noexcept
{
return pMem;
}
/**
****************************************************************************************************
* Object::operator delete
*
* @brief
* Frees Object object memory.
****************************************************************************************************
*/
VOID Object::operator delete(
VOID* pObjMem) ///< [in] User virtual address to free.
{
Object* pObj = static_cast<Object*>(pObjMem);
ClientFree(pObjMem, &pObj->m_client);
}
#if DEBUG
/**
****************************************************************************************************
* ApplyDebugPrinters
*
* @brief
* Sets the debug printers via TLS
*
* @return
* N/A
****************************************************************************************************
*/
VOID ApplyDebugPrinters(
ADDR_DEBUGPRINT pfnDebugPrint,
ADDR_CLIENT_HANDLE pClientHandle)
{
#if ADDR_ALLOW_TLS
g_clientHandle = pClientHandle;
g_pfnDebugPrint = pfnDebugPrint;
#endif
}
/**
****************************************************************************************************
* DebugPrint
*
* @brief
* Print debug message
*
* @return
* N/A
****************************************************************************************************
*/
VOID DebugPrint(
const CHAR* pDebugString, ///< [in] Debug string
...
)
{
va_list ap;
va_start(ap, pDebugString);
#if ADDR_ALLOW_TLS
if (g_pfnDebugPrint != NULL)
{
ADDR_DEBUGPRINT_INPUT debugPrintInput = {0};
debugPrintInput.size = sizeof(ADDR_DEBUGPRINT_INPUT);
debugPrintInput.pDebugString = const_cast<CHAR*>(pDebugString);
debugPrintInput.hClient = g_clientHandle;
va_copy(debugPrintInput.ap, ap);
g_pfnDebugPrint(&debugPrintInput);
va_end(debugPrintInput.ap);
}
else
#endif
{
#if ADDR_ALLOW_STDIO
fprintf(stderr, "Warning: Addrlib assert function called without corresponding 'ApplyDebugPrinters'\n");
vfprintf(stderr, pDebugString, ap);
#endif
}
va_end(ap);
}
#endif
} // Addr
src/amd/addrlib/src/core/addrobject.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
****************************************************************************************************
* @file addrobject.h
* @brief Contains the Object base class definition.
****************************************************************************************************
*/
#ifndef __ADDR_OBJECT_H__
#define __ADDR_OBJECT_H__
#include "addrtypes.h"
#include "addrcommon.h"
namespace Addr
{
/**
****************************************************************************************************
* @brief This structure contains client specific data
****************************************************************************************************
*/
struct Client
{
ADDR_CLIENT_HANDLE handle;
ADDR_CALLBACKS callbacks;
};
/**
****************************************************************************************************
* @brief This class is the base class for all ADDR class objects.
****************************************************************************************************
*/
class Object
{
public:
Object();
Object(const Client* pClient);
virtual ~Object();
VOID* operator new(size_t size, VOID* pMem) noexcept;
VOID operator delete(VOID* pObj);
/// Microsoft compiler requires a matching delete implementation, which seems to be called when
/// bad_alloc is thrown. But currently C++ exception isn't allowed so a dummy implementation is
/// added to eliminate the warning.
VOID operator delete(VOID* pObj, VOID* pMem) { ADDR_ASSERT_ALWAYS(); }
VOID* Alloc(size_t size) const;
VOID Free(VOID* pObj) const;
#if DEBUG
// This function should be called on every addrlib entrypoint (usually implicit by GetLib())
VOID SetDebugPrinters() const { ApplyDebugPrinters(m_client.callbacks.debugPrint, m_client.handle); }
#endif
const Client* GetClient() const {return &m_client;}
protected:
Client m_client;
static VOID* ClientAlloc(size_t size, const Client* pClient);
static VOID ClientFree(VOID* pObj, const Client* pClient);
private:
// disallow the copy constructor
Object(const Object& a);
// disallow the assignment operator
Object& operator=(const Object& a);
};
} // Addr
#endif
src/amd/addrlib/src/core/addrswizzler.cpp
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src/amd/addrlib/src/core/addrswizzler.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2024-2026 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
****************************************************************************************************
* @file addrswizzler.cpp
* @brief Contains code for efficient CPU swizzling.
****************************************************************************************************
*/
#ifndef __ADDR_SWIZZLER_H__
#define __ADDR_SWIZZLER_H__
#include "addrlib.h"
#include "addrcommon.h"
namespace Addr
{
// Forward decl
class LutAddresser;
typedef void (*UnalignedCopyMemImgFunc)(
void* pImgBlockSliceStart, // Block corresponding to beginning of slice
void* pBuf, // Pointer to data starting from the copy origin.
size_t bufStrideY, // Stride of each row in pBuf
size_t bufStrideZ, // Stride of each slice in pBuf
UINT_32 imageBlocksY, // Width of the image slice, in blocks.
UINT_32 imageBlocksZ, // Depth pitch of the image slice, in blocks.
ADDR_COORD3D origin, // Absolute origin, in elements
ADDR_EXTENT3D extent, // Size to copy, in elements
UINT_32 pipeBankXor, // Final value to XOR into the address
BOOL_32 isInMipTail, // True if this is in the mip tail.
const LutAddresser& addresser);
// This class calculates and holds up to four lookup tables (x/y/z/s) which can be used to cheaply calculate the
// position of a pixel within a block at the cost of some precomputation and memory usage.
//
// This works for all equations and does something like this:
// offset = blockAddr ^ XLut[x & xMask] ^ YLut[Y & ymask]...
class LutAddresser
{
public:
constexpr static UINT_32 MaxLutSize = 2100; // Sized to fit the largest non-VAR LUT size
LutAddresser();
void Init(const ADDR_BIT_SETTING* pEq, UINT_32 eqSize, ADDR_EXTENT3D blockSize, UINT_8 blkBits);
// Does a full calculation to get the offset within a block. Takes an *absolute* coordinate,
// not the coordinate within the block.
UINT_32 GetBlockOffset(
UINT_32 x,
UINT_32 y,
UINT_32 z,
UINT_32 s = 0,
UINT_32 pipeBankXor = 0)
{
return GetAddressX(x) ^ GetAddressY(y) ^ GetAddressZ(z) ^ GetAddressS(s) ^ pipeBankXor;
}
// Get the block size
UINT_32 GetBlockBits() const { return m_blockBits; }
UINT_32 GetBlockX() const { return m_blockSize.width; }
UINT_32 GetBlockY() const { return m_blockSize.height; }
UINT_32 GetBlockZ() const { return m_blockSize.depth; }
UINT_32 GetBlockXBits() const { return Log2(m_blockSize.width); }
UINT_32 GetBlockYBits() const { return Log2(m_blockSize.height); }
UINT_32 GetBlockZBits() const { return Log2(m_blockSize.depth); }
// Get the microblock size
UINT_32 GetMicroBlockX() const { return m_microBlockSize.width; }
UINT_32 GetMicroBlockY() const { return m_microBlockSize.height; }
UINT_32 GetMicroBlockZ() const { return m_microBlockSize.depth; }
// Get other image props
UINT_32 GetBpeLog2() const { return m_bpeLog2; }
// "Fast single channel" functions to get the part that each channel contributes to be XORd together.
UINT_32 GetAddressX(UINT_32 x) const { return m_pXLut[x & m_xLutMask];}
UINT_32 GetAddressY(UINT_32 y) const { return m_pYLut[y & m_yLutMask];}
UINT_32 GetAddressZ(UINT_32 z) const { return m_pZLut[z & m_zLutMask];}
UINT_32 GetAddressS(UINT_32 s) const { return m_pSLut[s & m_sLutMask];}
// Get a function that can copy a single 2D slice of an image with this swizzle.
UnalignedCopyMemImgFunc GetCopyMemImgFunc(ADDR_COPY_FLAGS flags) const;
UnalignedCopyMemImgFunc GetCopyImgMemFunc(ADDR_COPY_FLAGS flags) const;
void DoCopyMemImgPostFlushes(ADDR_COPY_FLAGS flags) const;
void DoCopyImgMemPreFlushes(ADDR_COPY_FLAGS flags) const;
private:
// Calculate general properties of the swizzle equations
void InitSwizzleProps();
// Fills a LUT for each channel.
void InitLuts();
// Evaluate coordinate without LUTs
UINT_32 EvalEquation(UINT_32 x, UINT_32 y, UINT_32 z, UINT_32 s);
// Pointers within m_lutData corresponding to where each LUT starts
// m_lutData[0] always has a value of 0 and thus can be considered an empty 1-entry LUT for "don't care" channels
UINT_32* m_pXLut;
UINT_32* m_pYLut;
UINT_32* m_pZLut;
UINT_32* m_pSLut;
// Size of each LUT, minus 1 to form a mask. A mask of 0 is valid for an empty LUT.
UINT_32 m_xLutMask;
UINT_32 m_yLutMask;
UINT_32 m_zLutMask;
UINT_32 m_sLutMask;
// Number of bits in the block (aka Log2(blkSize))
UINT_32 m_blockBits;
// The block size
ADDR_EXTENT3D m_blockSize;
// The microblock size
ADDR_EXTENT3D m_microBlockSize;
// Number of 'x' bits at the bottom of the equation. Must be a pow2 and at least 1.
// This will be used as a simple optimization to batch together operations on adjacent x pixels.
UINT_32 m_maxExpandX;
// BPE for this equation.
UINT_32 m_bpeLog2;
// The full equation
ADDR_BIT_SETTING m_bit[ADDR_MAX_EQUATION_BIT];
// Backing store for the LUT tables.
UINT_32 m_lutData[MaxLutSize];
};
}
#endif // __ADDR_SWIZZLER_H__
src/amd/addrlib/src/core/addrswizzlersimd.h
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src/amd/addrlib/src/core/coord.cpp
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
// Coordinate class implementation
#include "addrcommon.h"
#include "coord.h"
namespace Addr
{
namespace V2
{
Coordinate::Coordinate()
{
dim = DIM_X;
ord = 0;
}
Coordinate::Coordinate(enum Dim dim, INT_32 n)
{
set(dim, n);
}
VOID Coordinate::set(enum Dim d, INT_32 n)
{
dim = d;
ord = static_cast<INT_8>(n);
}
UINT_32 Coordinate::ison(const UINT_32 *coords) const
{
UINT_32 bit = static_cast<UINT_32>(1ull << static_cast<UINT_32>(ord));
return (coords[dim] & bit) ? 1 : 0;
}
enum Dim Coordinate::getdim()
{
return dim;
}
INT_8 Coordinate::getord()
{
return ord;
}
BOOL_32 Coordinate::operator==(const Coordinate& b)
{
return (dim == b.dim) && (ord == b.ord);
}
BOOL_32 Coordinate::operator<(const Coordinate& b)
{
BOOL_32 ret;
if (dim == b.dim)
{
ret = ord < b.ord;
}
else
{
if (dim == DIM_S || b.dim == DIM_M)
{
ret = TRUE;
}
else if (b.dim == DIM_S || dim == DIM_M)
{
ret = FALSE;
}
else if (ord == b.ord)
{
ret = dim < b.dim;
}
else
{
ret = ord < b.ord;
}
}
return ret;
}
BOOL_32 Coordinate::operator>(const Coordinate& b)
{
BOOL_32 lt = *this < b;
BOOL_32 eq = *this == b;
return !lt && !eq;
}
BOOL_32 Coordinate::operator<=(const Coordinate& b)
{
return (*this < b) || (*this == b);
}
BOOL_32 Coordinate::operator>=(const Coordinate& b)
{
return !(*this < b);
}
BOOL_32 Coordinate::operator!=(const Coordinate& b)
{
return !(*this == b);
}
Coordinate& Coordinate::operator++(INT_32)
{
ord++;
return *this;
}
// CoordTerm
CoordTerm::CoordTerm()
{
num_coords = 0;
}
VOID CoordTerm::Clear()
{
num_coords = 0;
}
VOID CoordTerm::add(Coordinate& co)
{
// This function adds a coordinate INT_32o the list
// It will prevent the same coordinate from appearing,
// and will keep the list ordered from smallest to largest
UINT_32 i;
for (i = 0; i < num_coords; i++)
{
if (m_coord[i] == co)
{
break;
}
if (m_coord[i] > co)
{
for (UINT_32 j = num_coords; j > i; j--)
{
m_coord[j] = m_coord[j - 1];
}
m_coord[i] = co;
num_coords++;
break;
}
}
if (i == num_coords)
{
m_coord[num_coords] = co;
num_coords++;
}
}
VOID CoordTerm::add(CoordTerm& cl)
{
for (UINT_32 i = 0; i < cl.num_coords; i++)
{
add(cl.m_coord[i]);
}
}
BOOL_32 CoordTerm::remove(Coordinate& co)
{
BOOL_32 remove = FALSE;
for (UINT_32 i = 0; i < num_coords; i++)
{
if (m_coord[i] == co)
{
remove = TRUE;
num_coords--;
}
if (remove)
{
m_coord[i] = m_coord[i + 1];
}
}
return remove;
}
BOOL_32 CoordTerm::Exists(Coordinate& co)
{
BOOL_32 exists = FALSE;
for (UINT_32 i = 0; i < num_coords; i++)
{
if (m_coord[i] == co)
{
exists = TRUE;
break;
}
}
return exists;
}
VOID CoordTerm::copyto(CoordTerm& cl)
{
cl.num_coords = num_coords;
for (UINT_32 i = 0; i < num_coords; i++)
{
cl.m_coord[i] = m_coord[i];
}
}
UINT_32 CoordTerm::getsize()
{
return num_coords;
}
UINT_32 CoordTerm::getxor(const UINT_32 *coords) const
{
UINT_32 out = 0;
for (UINT_32 i = 0; i < num_coords; i++)
{
out = out ^ m_coord[i].ison(coords);
}
return out;
}
VOID CoordTerm::getsmallest(Coordinate& co)
{
co = m_coord[0];
}
UINT_32 CoordTerm::Filter(INT_8 f, Coordinate& co, UINT_32 start, enum Dim axis)
{
for (UINT_32 i = start; i < num_coords;)
{
if (((f == '<' && m_coord[i] < co) ||
(f == '>' && m_coord[i] > co) ||
(f == '=' && m_coord[i] == co)) &&
(axis == NUM_DIMS || axis == m_coord[i].getdim()))
{
for (UINT_32 j = i; j < num_coords - 1; j++)
{
m_coord[j] = m_coord[j + 1];
}
num_coords--;
}
else
{
i++;
}
}
return num_coords;
}
Coordinate& CoordTerm::operator[](UINT_32 i)
{
return m_coord[i];
}
BOOL_32 CoordTerm::operator==(const CoordTerm& b)
{
BOOL_32 ret = TRUE;
if (num_coords != b.num_coords)
{
ret = FALSE;
}
else
{
for (UINT_32 i = 0; i < num_coords; i++)
{
// Note: the lists will always be in order, so we can compare the two lists at time
if (m_coord[i] != b.m_coord[i])
{
ret = FALSE;
break;
}
}
}
return ret;
}
BOOL_32 CoordTerm::operator!=(const CoordTerm& b)
{
return !(*this == b);
}
BOOL_32 CoordTerm::exceedRange(const UINT_32 *ranges)
{
BOOL_32 exceed = FALSE;
for (UINT_32 i = 0; (i < num_coords) && (exceed == FALSE); i++)
{
exceed = ((1u << m_coord[i].getord()) <= ranges[m_coord[i].getdim()]);
}
return exceed;
}
// coordeq
CoordEq::CoordEq()
{
m_numBits = 0;
}
VOID CoordEq::remove(Coordinate& co)
{
for (UINT_32 i = 0; i < m_numBits; i++)
{
m_eq[i].remove(co);
}
}
BOOL_32 CoordEq::Exists(Coordinate& co)
{
BOOL_32 exists = FALSE;
for (UINT_32 i = 0; i < m_numBits; i++)
{
if (m_eq[i].Exists(co))
{
exists = TRUE;
}
}
return exists;
}
VOID CoordEq::resize(UINT_32 n)
{
if (n > m_numBits)
{
for (UINT_32 i = m_numBits; i < n; i++)
{
m_eq[i].Clear();
}
}
m_numBits = n;
}
UINT_32 CoordEq::getsize()
{
return m_numBits;
}
UINT_64 CoordEq::solve(const UINT_32 *coords) const
{
UINT_64 out = 0;
for (UINT_32 i = 0; i < m_numBits; i++)
{
out |= static_cast<UINT_64>(m_eq[i].getxor(coords)) << i;
}
return out;
}
VOID CoordEq::solveAddr(
UINT_64 addr, UINT_32 sliceInM,
UINT_32 *coords) const
{
UINT_32 BitsValid[NUM_DIMS] = {0};
CoordEq temp = *this;
memset(coords, 0, NUM_DIMS * sizeof(coords[0]));
UINT_32 bitsLeft = 0;
for (UINT_32 i = 0; i < temp.m_numBits; i++)
{
UINT_32 termSize = temp.m_eq[i].getsize();
if (termSize == 1)
{
INT_8 bit = (addr >> i) & 1;
enum Dim dim = temp.m_eq[i][0].getdim();
INT_8 ord = temp.m_eq[i][0].getord();
ADDR_ASSERT((ord < 32) || (bit == 0));
BitsValid[dim] |= 1u << ord;
coords[dim] |= bit << ord;
temp.m_eq[i].Clear();
}
else if (termSize > 1)
{
bitsLeft++;
}
}
if (bitsLeft > 0)
{
if (sliceInM != 0)
{
coords[DIM_Z] = coords[DIM_M] / sliceInM;
BitsValid[DIM_Z] = 0xffffffff;
}
do
{
bitsLeft = 0;
for (UINT_32 i = 0; i < temp.m_numBits; i++)
{
UINT_32 termSize = temp.m_eq[i].getsize();
if (termSize == 1)
{
INT_8 bit = (addr >> i) & 1;
enum Dim dim = temp.m_eq[i][0].getdim();
INT_8 ord = temp.m_eq[i][0].getord();
ADDR_ASSERT((ord < 32) || (bit == 0));
ADDR_ASSERT(dim < DIM_S);
BitsValid[dim] |= 1u << ord;
coords[dim] |= bit << ord;
temp.m_eq[i].Clear();
}
else if (termSize > 1)
{
CoordTerm tmpTerm = temp.m_eq[i];
for (UINT_32 j = 0; j < termSize; j++)
{
enum Dim dim = temp.m_eq[i][j].getdim();
INT_8 ord = temp.m_eq[i][j].getord();
ADDR_ASSERT(dim < DIM_S);
if (BitsValid[dim] & (1u << ord))
{
UINT_32 v = (((coords[dim] >> ord) & 1) << i);
addr ^= static_cast<UINT_64>(v);
tmpTerm.remove(temp.m_eq[i][j]);
}
}
temp.m_eq[i] = tmpTerm;
bitsLeft++;
}
}
} while (bitsLeft > 0);
}
}
VOID CoordEq::copy(CoordEq& o, UINT_32 start, UINT_32 num)
{
o.m_numBits = (num == 0xFFFFFFFF) ? m_numBits : num;
for (UINT_32 i = 0; i < o.m_numBits; i++)
{
m_eq[start + i].copyto(o.m_eq[i]);
}
}
VOID CoordEq::reverse(UINT_32 start, UINT_32 num)
{
UINT_32 n = (num == 0xFFFFFFFF) ? m_numBits : num;
for (UINT_32 i = 0; i < n / 2; i++)
{
CoordTerm temp;
m_eq[start + i].copyto(temp);
m_eq[start + n - 1 - i].copyto(m_eq[start + i]);
temp.copyto(m_eq[start + n - 1 - i]);
}
}
VOID CoordEq::xorin(CoordEq& x, UINT_32 start)
{
UINT_32 n = ((m_numBits - start) < x.m_numBits) ? (m_numBits - start) : x.m_numBits;
for (UINT_32 i = 0; i < n; i++)
{
m_eq[start + i].add(x.m_eq[i]);
}
}
UINT_32 CoordEq::Filter(INT_8 f, Coordinate& co, UINT_32 start, enum Dim axis)
{
for (UINT_32 i = start; i < m_numBits;)
{
UINT_32 m = m_eq[i].Filter(f, co, 0, axis);
if (m == 0)
{
for (UINT_32 j = i; j < m_numBits - 1; j++)
{
m_eq[j] = m_eq[j + 1];
}
m_numBits--;
}
else
{
i++;
}
}
return m_numBits;
}
VOID CoordEq::shift(INT_32 amount, INT_32 start)
{
if (amount != 0)
{
INT_32 numBits = static_cast<INT_32>(m_numBits);
amount = -amount;
INT_32 inc = (amount < 0) ? -1 : 1;
INT_32 i = (amount < 0) ? numBits - 1 : start;
INT_32 end = (amount < 0) ? start - 1 : numBits;
for (; (inc > 0) ? i < end : i > end; i += inc)
{
if ((i + amount < start) || (i + amount >= numBits))
{
m_eq[i].Clear();
}
else
{
m_eq[i + amount].copyto(m_eq[i]);
}
}
}
}
CoordTerm& CoordEq::operator[](UINT_32 i)
{
return m_eq[i];
}
VOID CoordEq::mort2d(Coordinate& c0, Coordinate& c1, UINT_32 start, UINT_32 end)
{
if (end == 0)
{
ADDR_ASSERT(m_numBits > 0);
end = m_numBits - 1;
}
for (UINT_32 i = start; i <= end; i++)
{
UINT_32 select = (i - start) % 2;
Coordinate& c = (select == 0) ? c0 : c1;
m_eq[i].add(c);
c++;
}
}
VOID CoordEq::mort3d(Coordinate& c0, Coordinate& c1, Coordinate& c2, UINT_32 start, UINT_32 end)
{
if (end == 0)
{
ADDR_ASSERT(m_numBits > 0);
end = m_numBits - 1;
}
for (UINT_32 i = start; i <= end; i++)
{
UINT_32 select = (i - start) % 3;
Coordinate& c = (select == 0) ? c0 : ((select == 1) ? c1 : c2);
m_eq[i].add(c);
c++;
}
}
BOOL_32 CoordEq::operator==(const CoordEq& b)
{
BOOL_32 ret = TRUE;
if (m_numBits != b.m_numBits)
{
ret = FALSE;
}
else
{
for (UINT_32 i = 0; i < m_numBits; i++)
{
if (m_eq[i] != b.m_eq[i])
{
ret = FALSE;
break;
}
}
}
return ret;
}
BOOL_32 CoordEq::operator!=(const CoordEq& b)
{
return !(*this == b);
}
} // V2
} // Addr
src/amd/addrlib/src/core/coord.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
// Class used to define a coordinate bit
#ifndef __COORD_H
#define __COORD_H
namespace Addr
{
namespace V2
{
#if defined(__cplusplus)
#if defined(_MSC_VER)
#if _MSC_VER >= 1900
#define ADDR_CPP11_COMPILER TRUE
#endif
#else
#if __cplusplus >= 201103L
#define ADDR_CPP11_COMPILER TRUE
#endif
#endif
#endif
#if defined(ADDR_CPP11_COMPILER)
enum Dim : INT_8
#else
enum Dim
#endif
{
DIM_X,
DIM_Y,
DIM_Z,
DIM_S,
DIM_M,
NUM_DIMS
};
class Coordinate
{
public:
Coordinate();
Coordinate(enum Dim dim, INT_32 n);
VOID set(enum Dim dim, INT_32 n);
UINT_32 ison(const UINT_32 *coords) const;
enum Dim getdim();
INT_8 getord();
BOOL_32 operator==(const Coordinate& b);
BOOL_32 operator<(const Coordinate& b);
BOOL_32 operator>(const Coordinate& b);
BOOL_32 operator<=(const Coordinate& b);
BOOL_32 operator>=(const Coordinate& b);
BOOL_32 operator!=(const Coordinate& b);
Coordinate& operator++(INT_32);
private:
enum Dim dim;
INT_8 ord;
};
class CoordTerm
{
public:
CoordTerm();
VOID Clear();
VOID add(Coordinate& co);
VOID add(CoordTerm& cl);
BOOL_32 remove(Coordinate& co);
BOOL_32 Exists(Coordinate& co);
VOID copyto(CoordTerm& cl);
UINT_32 getsize();
UINT_32 getxor(const UINT_32 *coords) const;
VOID getsmallest(Coordinate& co);
UINT_32 Filter(INT_8 f, Coordinate& co, UINT_32 start = 0, enum Dim axis = NUM_DIMS);
Coordinate& operator[](UINT_32 i);
BOOL_32 operator==(const CoordTerm& b);
BOOL_32 operator!=(const CoordTerm& b);
BOOL_32 exceedRange(const UINT_32 *ranges);
private:
static const UINT_32 MaxCoords = 8;
UINT_32 num_coords;
Coordinate m_coord[MaxCoords];
};
class CoordEq
{
public:
CoordEq();
VOID remove(Coordinate& co);
BOOL_32 Exists(Coordinate& co);
VOID resize(UINT_32 n);
UINT_32 getsize();
virtual UINT_64 solve(const UINT_32 *coords) const;
virtual VOID solveAddr(UINT_64 addr, UINT_32 sliceInM,
UINT_32 *coords) const;
VOID copy(CoordEq& o, UINT_32 start = 0, UINT_32 num = 0xFFFFFFFF);
VOID reverse(UINT_32 start = 0, UINT_32 num = 0xFFFFFFFF);
VOID xorin(CoordEq& x, UINT_32 start = 0);
UINT_32 Filter(INT_8 f, Coordinate& co, UINT_32 start = 0, enum Dim axis = NUM_DIMS);
VOID shift(INT_32 amount, INT_32 start = 0);
virtual CoordTerm& operator[](UINT_32 i);
VOID mort2d(Coordinate& c0, Coordinate& c1, UINT_32 start = 0, UINT_32 end = 0);
VOID mort3d(Coordinate& c0, Coordinate& c1, Coordinate& c2, UINT_32 start = 0, UINT_32 end = 0);
BOOL_32 operator==(const CoordEq& b);
BOOL_32 operator!=(const CoordEq& b);
private:
static const UINT_32 MaxEqBits = 64;
UINT_32 m_numBits;
CoordTerm m_eq[MaxEqBits];
};
} // V2
} // Addr
#endif
src/amd/addrlib/src/gfx10/gfx10SwizzlePattern.h
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src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
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src/amd/addrlib/src/gfx10/gfx10addrlib.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
************************************************************************************************************************
* @file gfx10addrlib.h
* @brief Contains the Gfx10Lib class definition.
************************************************************************************************************************
*/
#ifndef __GFX10_ADDR_LIB_H__
#define __GFX10_ADDR_LIB_H__
#include "addrlib2.h"
#include "coord.h"
#include "gfx10SwizzlePattern.h"
namespace Addr
{
namespace V2
{
/**
************************************************************************************************************************
* @brief GFX10 specific settings structure.
************************************************************************************************************************
*/
struct Gfx10ChipSettings
{
struct
{
UINT_32 reserved1 : 32;
// Misc configuration bits
UINT_32 isDcn20 : 1; // If using DCN2.0
UINT_32 supportRbPlus : 1;
UINT_32 dsMipmapHtileFix : 1;
UINT_32 dccUnsup3DSwDis : 1;
UINT_32 reserved2 : 28;
};
};
/**
************************************************************************************************************************
* @brief GFX10 data surface type.
************************************************************************************************************************
*/
enum Gfx10DataType
{
Gfx10DataColor,
Gfx10DataDepthStencil,
Gfx10DataFmask
};
const UINT_32 Gfx10LinearSwModeMask = (1u << ADDR_SW_LINEAR);
const UINT_32 Gfx10Blk256BSwModeMask = (1u << ADDR_SW_256B_S) |
(1u << ADDR_SW_256B_D);
const UINT_32 Gfx10Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_4KB_D_X);
const UINT_32 Gfx10Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx10BlkVarSwModeMask = (1u << ADDR_SW_VAR_Z_X) |
(1u << ADDR_SW_VAR_R_X);
const UINT_32 Gfx10ZSwModeMask = (1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_VAR_Z_X);
const UINT_32 Gfx10StandardSwModeMask = (1u << ADDR_SW_256B_S) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_64KB_S_X);
const UINT_32 Gfx10DisplaySwModeMask = (1u << ADDR_SW_256B_D) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_D_X);
const UINT_32 Gfx10RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) |
(1u << ADDR_SW_VAR_R_X);
const UINT_32 Gfx10XSwModeMask = (1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X) |
Gfx10BlkVarSwModeMask;
const UINT_32 Gfx10TSwModeMask = (1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_D_T);
const UINT_32 Gfx10XorSwModeMask = Gfx10XSwModeMask |
Gfx10TSwModeMask;
const UINT_32 Gfx10Rsrc1dSwModeMask = Gfx10LinearSwModeMask |
Gfx10RenderSwModeMask |
Gfx10ZSwModeMask;
const UINT_32 Gfx10Rsrc2dSwModeMask = Gfx10LinearSwModeMask |
Gfx10Blk256BSwModeMask |
Gfx10Blk4KBSwModeMask |
Gfx10Blk64KBSwModeMask |
Gfx10BlkVarSwModeMask;
const UINT_32 Gfx10Rsrc3dSwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X) |
Gfx10BlkVarSwModeMask;
const UINT_32 Gfx10Rsrc2dPrtSwModeMask = (Gfx10Blk4KBSwModeMask | Gfx10Blk64KBSwModeMask) & ~Gfx10XSwModeMask;
const UINT_32 Gfx10Rsrc3dPrtSwModeMask = Gfx10Rsrc2dPrtSwModeMask & ~Gfx10DisplaySwModeMask;
const UINT_32 Gfx10Rsrc3dThin64KBSwModeMask = (1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx10Rsrc3dThinSwModeMask = Gfx10Rsrc3dThin64KBSwModeMask |
Gfx10BlkVarSwModeMask;
const UINT_32 Gfx10Rsrc3dViewAs2dSwModeMask = Gfx10Rsrc3dThinSwModeMask | Gfx10LinearSwModeMask;
const UINT_32 Gfx10Rsrc3dThickSwModeMask = Gfx10Rsrc3dSwModeMask & ~(Gfx10Rsrc3dThinSwModeMask | Gfx10LinearSwModeMask);
const UINT_32 Gfx10Rsrc3dThick4KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk4KBSwModeMask;
const UINT_32 Gfx10Rsrc3dThick64KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk64KBSwModeMask;
const UINT_32 Gfx10MsaaSwModeMask = (Gfx10ZSwModeMask |
Gfx10RenderSwModeMask);
const UINT_32 Dcn20NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Dcn20Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_D_X) |
Dcn20NonBpp64SwModeMask;
const UINT_32 Dcn21NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Dcn21Bpp64SwModeMask = (1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_64KB_D_X) |
Dcn21NonBpp64SwModeMask;
/**
************************************************************************************************************************
* @brief This class is the GFX10 specific address library
* function set.
************************************************************************************************************************
*/
class Gfx10Lib : public Lib
{
public:
/// Creates Gfx10Lib object
static Addr::Lib* CreateObj(const Client* pClient)
{
VOID* pMem = Object::ClientAlloc(sizeof(Gfx10Lib), pClient);
return (pMem != NULL) ? new (pMem) Gfx10Lib(pClient) : NULL;
}
protected:
Gfx10Lib(const Client* pClient);
virtual ~Gfx10Lib();
BOOL_32 HwlIsStandardSwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const override final
{
return m_swizzleModeTable[swizzleMode].isStd;
}
BOOL_32 HwlIsDisplaySwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const override final
{
return m_swizzleModeTable[swizzleMode].isDisp;
}
BOOL_32 HwlIsThin(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const override final
{
return ((IsTex1d(resourceType) == TRUE) ||
(IsTex2d(resourceType) == TRUE) ||
((IsTex3d(resourceType) == TRUE) &&
(m_swizzleModeTable[swizzleMode].isStd == FALSE) &&
(m_swizzleModeTable[swizzleMode].isDisp == FALSE)));
}
BOOL_32 HwlIsThick(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const override final
{
return ((IsTex3d(resourceType) == TRUE) &&
(m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp));
}
ADDR_E_RETURNCODE HwlComputeHtileInfo(
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeCmaskInfo(
const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) override final;
ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) override final;
ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) override final;
ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn) override final;
VOID HwlComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) override final;
UINT_32 HwlGetEquationIndex(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const override final;
UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const override final
{
*ppEquationTable = m_equationTable;
return m_numEquations;
}
ADDR_E_RETURNCODE HwlComputePipeBankXor(
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView(
const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn,
ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlGetPossibleSwizzleModes(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const override final;
ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlCopyMemToSurface(
const ADDR2_COPY_MEMSURFACE_INPUT* pIn,
const ADDR2_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const override final;
ADDR_E_RETURNCODE HwlCopySurfaceToMem(
const ADDR2_COPY_MEMSURFACE_INPUT* pIn,
const ADDR2_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const override final;
UINT_32 HwlComputeMaxBaseAlignments() const override final;
UINT_32 HwlComputeMaxMetaBaseAlignments() const override final;
BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) override final;
ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) override final;
private:
// Initialize equation table
VOID InitEquationTable();
ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
UINT_32 ComputeOffsetFromEquation(
const ADDR_EQUATION* pEq,
UINT_32 x,
UINT_32 y,
UINT_32 z) const;
ADDR_E_RETURNCODE ComputeStereoInfo(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32* pAlignY,
UINT_32* pRightXor) const;
static void GetMipSize(
UINT_32 mip0Width,
UINT_32 mip0Height,
UINT_32 mip0Depth,
UINT_32 mipId,
UINT_32* pMipWidth,
UINT_32* pMipHeight,
UINT_32* pMipDepth = NULL)
{
*pMipWidth = ShiftCeil(Max(mip0Width, 1u), mipId);
*pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId);
if (pMipDepth != NULL)
{
*pMipDepth = ShiftCeil(Max(mip0Depth, 1u), mipId);
}
}
const ADDR_SW_PATINFO* GetSwizzlePatternInfo(
AddrSwizzleMode swizzleMode,
AddrResourceType resourceType,
UINT_32 log2Elem,
UINT_32 numFrag) const;
/**
* Will use the indices, "nibbles", to build an index equation inside pSwizzle
*
* @param pPatInfo Pointer to a patInfo. Contains indices mapping to the 2D nibble arrays which will be used to build an index equation.
* @param pSwizzle Array to write the index equation to.
*/
VOID GetSwizzlePatternFromPatternInfo(
const ADDR_SW_PATINFO* pPatInfo,
ADDR_BIT_SETTING (&pSwizzle)[ADDR_MAX_EQUATION_BIT]) const
{
memcpy(pSwizzle,
GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx],
sizeof(GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx]));
memcpy(&pSwizzle[8],
GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx],
sizeof(GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx]));
memcpy(&pSwizzle[12],
GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx],
sizeof(GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx]));
memcpy(&pSwizzle[16],
GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx],
sizeof(GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx]));
}
VOID ConvertSwizzlePatternToEquation(
UINT_32 elemLog2,
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
const ADDR_SW_PATINFO* pPatInfo,
ADDR_EQUATION* pEquation) const;
static INT_32 GetMetaElementSizeLog2(Gfx10DataType dataType);
static INT_32 GetMetaCacheSizeLog2(Gfx10DataType dataType);
void GetBlk256SizeLog2(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2,
Dim3d* pBlock) const;
void GetCompressedBlockSizeLog2(
Gfx10DataType dataType,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2,
Dim3d* pBlock) const;
INT_32 GetMetaOverlapLog2(
Gfx10DataType dataType,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2) const;
INT_32 Get3DMetaOverlapLog2(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2) const;
UINT_32 GetMetaBlkSize(
Gfx10DataType dataType,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2,
BOOL_32 pipeAlign,
Dim3d* pBlock) const;
INT_32 GetPipeRotateAmount(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const;
INT_32 GetEffectiveNumPipes() const
{
return ((m_settings.supportRbPlus == FALSE) ||
((m_numSaLog2 + 1) >= m_pipesLog2)) ? m_pipesLog2 : m_numSaLog2 + 1;
}
BOOL_32 IsRbAligned(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
const BOOL_32 isRtopt = IsRtOptSwizzle(swizzleMode);
const BOOL_32 isZ = IsZOrderSwizzle(swizzleMode);
const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode);
return (IsTex2d(resourceType) && (isRtopt || isZ)) ||
(IsTex3d(resourceType) && isDisplay);
}
UINT_32 GetValidDisplaySwizzleModes(UINT_32 bpp) const;
BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const override final;
UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const;
static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType)
{
ADDR2_BLOCK_SET allowedBlockSet = {};
allowedBlockSet.micro = (allowedSwModeSet.value & Gfx10Blk256BSwModeMask) ? TRUE : FALSE;
allowedBlockSet.linear = (allowedSwModeSet.value & Gfx10LinearSwModeMask) ? TRUE : FALSE;
allowedBlockSet.var = (allowedSwModeSet.value & Gfx10BlkVarSwModeMask) ? TRUE : FALSE;
if (rsrcType == ADDR_RSRC_TEX_3D)
{
allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE;
allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE;
allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE;
}
else
{
allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx10Blk4KBSwModeMask) ? TRUE : FALSE;
allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Blk64KBSwModeMask) ? TRUE : FALSE;
}
return allowedBlockSet;
}
static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)
{
ADDR2_SWTYPE_SET allowedSwSet = {};
allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx10ZSwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx10StandardSwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx10DisplaySwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx10RenderSwModeMask) ? TRUE : FALSE;
return allowedSwSet;
}
BOOL_32 IsInMipTail(
Dim3d mipTailDim,
UINT_32 maxNumMipsInTail,
UINT_32 mipWidth,
UINT_32 mipHeight,
UINT_32 numMipsToTheEnd) const
{
BOOL_32 inTail = ((mipWidth <= mipTailDim.w) &&
(mipHeight <= mipTailDim.h) &&
(numMipsToTheEnd <= maxNumMipsInTail));
return inTail;
}
UINT_32 GetBankXorBits(UINT_32 blockBits) const
{
return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ?
Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0;
}
BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
static const UINT_32 ColumnBits = 2;
static const UINT_32 BankBits = 4;
static const UINT_32 UnalignedDccType = 3;
static const Dim3d Block256_3d[MaxNumOfBpp];
static const Dim3d Block64K_Log2_3d[MaxNumOfBpp];
static const Dim3d Block4K_Log2_3d[MaxNumOfBpp];
static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE];
// Number of packers log2
UINT_32 m_numPkrLog2;
// Number of shader array log2
UINT_32 m_numSaLog2;
Gfx10ChipSettings m_settings;
UINT_32 m_colorBaseIndex;
UINT_32 m_xmaskBaseIndex;
UINT_32 m_htileBaseIndex;
UINT_32 m_dccBaseIndex;
};
} // V2
} // Addr
#endif
src/amd/addrlib/src/gfx11/gfx11SwizzlePattern.h
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src/amd/addrlib/src/gfx11/gfx11addrlib.cpp
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src/amd/addrlib/src/gfx11/gfx11addrlib.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2026 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
************************************************************************************************************************
* @file gfx11addrlib.h
* @brief Contains the Gfx11Lib class definition.
************************************************************************************************************************
*/
#ifndef __GFX11_ADDR_LIB_H__
#define __GFX11_ADDR_LIB_H__
#include "addrlib2.h"
#include "coord.h"
#include "gfx11SwizzlePattern.h"
namespace Addr
{
namespace V2
{
/**
************************************************************************************************************************
* @brief GFX11 specific settings structure.
************************************************************************************************************************
*/
struct Gfx11ChipSettings
{
struct
{
UINT_32 isStrix : 1;
UINT_32 isPhoenix : 1;
UINT_32 isGfx1170 : 1;
UINT_32 reserved1 : 29;
// Misc configuration bits
UINT_32 reserved2 : 32;
};
};
/**
************************************************************************************************************************
* @brief GFX11 data surface type.
************************************************************************************************************************
*/
enum Gfx11DataType
{
Gfx11DataColor,
Gfx11DataDepthStencil,
};
const UINT_32 Gfx11LinearSwModeMask = (1u << ADDR_SW_LINEAR);
const UINT_32 Gfx11Blk256BSwModeMask = (1u << ADDR_SW_256B_D);
const UINT_32 Gfx11Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_4KB_D_X);
const UINT_32 Gfx11Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx11Blk256KBSwModeMask = (1u << ADDR_SW_256KB_Z_X) |
(1u << ADDR_SW_256KB_S_X) |
(1u << ADDR_SW_256KB_D_X) |
(1u << ADDR_SW_256KB_R_X);
const UINT_32 Gfx11ZSwModeMask = (1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_256KB_Z_X);
const UINT_32 Gfx11StandardSwModeMask = (1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_256KB_S_X);
const UINT_32 Gfx11DisplaySwModeMask = (1u << ADDR_SW_256B_D) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_256KB_D_X);
const UINT_32 Gfx11RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) |
(1u << ADDR_SW_256KB_R_X);
const UINT_32 Gfx11XSwModeMask = (1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X) |
Gfx11Blk256KBSwModeMask;
const UINT_32 Gfx11TSwModeMask = (1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_D_T);
const UINT_32 Gfx11XorSwModeMask = Gfx11XSwModeMask |
Gfx11TSwModeMask;
const UINT_32 Gfx11Rsrc1dSwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_64KB_R_X) |
(1u << ADDR_SW_64KB_Z_X) ;
const UINT_32 Gfx11Rsrc2dSwModeMask = Gfx11LinearSwModeMask |
Gfx11DisplaySwModeMask |
Gfx11ZSwModeMask |
Gfx11RenderSwModeMask;
const UINT_32 Gfx11Rsrc3dSwModeMask = Gfx11LinearSwModeMask |
Gfx11StandardSwModeMask |
Gfx11ZSwModeMask |
Gfx11RenderSwModeMask |
(1u << ADDR_SW_64KB_D_X);
const UINT_32 Gfx11Rsrc2dPrtSwModeMask =
(Gfx11Blk4KBSwModeMask | Gfx11Blk64KBSwModeMask) & ~Gfx11XSwModeMask & Gfx11Rsrc2dSwModeMask;
const UINT_32 Gfx11Rsrc3dPrtSwModeMask =
(Gfx11Blk4KBSwModeMask | Gfx11Blk64KBSwModeMask) & ~Gfx11XSwModeMask & Gfx11Rsrc3dSwModeMask;
const UINT_32 Gfx11Rsrc3dThin64KBSwModeMask = (1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx11Rsrc3dThin256KBSwModeMask = (1u << ADDR_SW_256KB_Z_X) |
(1u << ADDR_SW_256KB_R_X);
const UINT_32 Gfx11Rsrc3dThinSwModeMask = Gfx11Rsrc3dThin64KBSwModeMask | Gfx11Rsrc3dThin256KBSwModeMask;
const UINT_32 Gfx11Rsrc3dViewAs2dSwModeMask = Gfx11Rsrc3dThinSwModeMask | Gfx11LinearSwModeMask;
const UINT_32 Gfx11Rsrc3dThickSwModeMask = Gfx11Rsrc3dSwModeMask & ~(Gfx11Rsrc3dThinSwModeMask | Gfx11LinearSwModeMask);
const UINT_32 Gfx11Rsrc3dThick4KBSwModeMask = Gfx11Rsrc3dThickSwModeMask & Gfx11Blk4KBSwModeMask;
const UINT_32 Gfx11Rsrc3dThick64KBSwModeMask = Gfx11Rsrc3dThickSwModeMask & Gfx11Blk64KBSwModeMask;
const UINT_32 Gfx11Rsrc3dThick256KBSwModeMask = Gfx11Rsrc3dThickSwModeMask & Gfx11Blk256KBSwModeMask;
const UINT_32 Gfx11MsaaSwModeMask = Gfx11ZSwModeMask |
Gfx11RenderSwModeMask;
const UINT_32 Dcn32SwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X) |
(1u << ADDR_SW_256KB_D_X) |
(1u << ADDR_SW_256KB_R_X);
const UINT_32 Size256K = 262144u;
const UINT_32 Log2Size256K = 18u;
/**
************************************************************************************************************************
* @brief This class is the GFX11 specific address library
* function set.
************************************************************************************************************************
*/
class Gfx11Lib : public Lib
{
public:
/// Creates Gfx11Lib object
static Addr::Lib* CreateObj(const Client* pClient)
{
VOID* pMem = Object::ClientAlloc(sizeof(Gfx11Lib), pClient);
return (pMem != NULL) ? new (pMem) Gfx11Lib(pClient) : NULL;
}
protected:
Gfx11Lib(const Client* pClient);
virtual ~Gfx11Lib();
BOOL_32 HwlIsStandardSwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const override final
{
return m_swizzleModeTable[swizzleMode].isStd;
}
BOOL_32 HwlIsDisplaySwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const override final
{
return m_swizzleModeTable[swizzleMode].isDisp;
}
BOOL_32 HwlIsThin(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const override final
{
return ((IsTex1d(resourceType) == TRUE) ||
(IsTex2d(resourceType) == TRUE) ||
((IsTex3d(resourceType) == TRUE) &&
(m_swizzleModeTable[swizzleMode].isStd == FALSE) &&
(m_swizzleModeTable[swizzleMode].isDisp == FALSE)));
}
BOOL_32 HwlIsThick(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const override final
{
return ((IsTex3d(resourceType) == TRUE) &&
(m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp));
}
ADDR_E_RETURNCODE HwlComputeHtileInfo(
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) override final;
ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) override final;
ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn) override final;
VOID HwlComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) override final;
UINT_32 HwlGetEquationIndex(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const override final;
UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const override final
{
*ppEquationTable = m_equationTable;
return m_numEquations;
}
ADDR_E_RETURNCODE HwlComputePipeBankXor(
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView(
const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn,
ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlGetPossibleSwizzleModes(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlGetAllowedBlockSet(
ADDR2_SWMODE_SET allowedSwModeSet,
AddrResourceType rsrcType,
ADDR2_BLOCK_SET* pAllowedBlockSet) const override final;
ADDR_E_RETURNCODE HwlGetAllowedSwSet(
ADDR2_SWMODE_SET allowedSwModeSet,
ADDR2_SWTYPE_SET* pAllowedSwSet) const override final;
ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const override final;
ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const override final;
ADDR_E_RETURNCODE HwlCopyMemToSurface(
const ADDR2_COPY_MEMSURFACE_INPUT* pIn,
const ADDR2_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const override final;
ADDR_E_RETURNCODE HwlCopySurfaceToMem(
const ADDR2_COPY_MEMSURFACE_INPUT* pIn,
const ADDR2_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const override final;
UINT_32 HwlComputeMaxBaseAlignments() const override final;
UINT_32 HwlComputeMaxMetaBaseAlignments() const override final;
BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) override final;
ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) override final;
private:
// Initialize equation table
VOID InitEquationTable();
ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
UINT_32 ComputeOffsetFromEquation(
const ADDR_EQUATION* pEq,
UINT_32 x,
UINT_32 y,
UINT_32 z) const;
ADDR_E_RETURNCODE ComputeStereoInfo(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32* pAlignY,
UINT_32* pRightXor) const;
static void GetMipSize(
UINT_32 mip0Width,
UINT_32 mip0Height,
UINT_32 mip0Depth,
UINT_32 mipId,
UINT_32* pMipWidth,
UINT_32* pMipHeight,
UINT_32* pMipDepth = NULL)
{
*pMipWidth = ShiftCeil(Max(mip0Width, 1u), mipId);
*pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId);
if (pMipDepth != NULL)
{
*pMipDepth = ShiftCeil(Max(mip0Depth, 1u), mipId);
}
}
const ADDR_SW_PATINFO* GetSwizzlePatternInfo(
AddrSwizzleMode swizzleMode,
AddrResourceType resourceType,
UINT_32 log2Elem,
UINT_32 numFrag) const;
VOID GetSwizzlePatternFromPatternInfo(
const ADDR_SW_PATINFO* pPatInfo,
ADDR_BIT_SETTING (&pSwizzle)[ADDR_MAX_EQUATION_BIT]) const
{
memcpy(pSwizzle,
GFX11_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx],
sizeof(GFX11_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx]));
memcpy(&pSwizzle[8],
GFX11_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx],
sizeof(GFX11_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx]));
memcpy(&pSwizzle[12],
GFX11_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx],
sizeof(GFX11_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx]));
memcpy(&pSwizzle[16],
GFX11_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx],
sizeof(GFX11_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx]));
}
VOID ConvertSwizzlePatternToEquation(
UINT_32 elemLog2,
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
const ADDR_SW_PATINFO* pPatInfo,
ADDR_EQUATION* pEquation) const;
static INT_32 GetMetaElementSizeLog2(Gfx11DataType dataType);
static INT_32 GetMetaCacheSizeLog2(Gfx11DataType dataType);
void GetBlk256SizeLog2(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2,
Dim3d* pBlock) const;
void GetCompressedBlockSizeLog2(
Gfx11DataType dataType,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2,
Dim3d* pBlock) const;
INT_32 GetMetaOverlapLog2(
Gfx11DataType dataType,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2) const;
INT_32 Get3DMetaOverlapLog2(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2) const;
UINT_32 GetMetaBlkSize(
Gfx11DataType dataType,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2,
BOOL_32 pipeAlign,
Dim3d* pBlock) const;
INT_32 GetPipeRotateAmount(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const;
INT_32 GetEffectiveNumPipes() const
{
return ((m_numSaLog2 + 1) >= m_pipesLog2) ? m_pipesLog2 : m_numSaLog2 + 1;
}
BOOL_32 IsRbAligned(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
const BOOL_32 isRtopt = IsRtOptSwizzle(swizzleMode);
const BOOL_32 isZ = IsZOrderSwizzle(swizzleMode);
const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode);
return (IsTex2d(resourceType) && (isRtopt || isZ)) ||
(IsTex3d(resourceType) && isDisplay);
}
UINT_32 GetValidDisplaySwizzleModes(UINT_32 bpp) const;
BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const override final;
UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const;
BOOL_32 IsInMipTail(
Dim3d mipTailDim,
UINT_32 maxNumMipsInTail,
UINT_32 mipWidth,
UINT_32 mipHeight,
UINT_32 numMipsToTheEnd) const
{
BOOL_32 inTail = ((mipWidth <= mipTailDim.w) &&
(mipHeight <= mipTailDim.h) &&
(numMipsToTheEnd <= maxNumMipsInTail));
return inTail;
}
UINT_32 GetBankXorBits(UINT_32 blockBits) const
{
return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ?
Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0;
}
BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
BOOL_32 IsBlock256kb(AddrSwizzleMode swizzleMode) const { return IsBlockVariable(swizzleMode); }
// TODO: figure out if there is any Column bits on GFX11...
static const UINT_32 ColumnBits = 2;
static const UINT_32 BankBits = 4;
static const UINT_32 UnalignedDccType = 3;
static const Dim3d Block256_3d[MaxNumOfBpp];
static const Dim3d Block256K_Log2_3d[MaxNumOfBpp];
static const Dim3d Block64K_Log2_3d[MaxNumOfBpp];
static const Dim3d Block4K_Log2_3d[MaxNumOfBpp];
static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE];
// Number of packers log2
UINT_32 m_numPkrLog2;
// Number of shader array log2
UINT_32 m_numSaLog2;
Gfx11ChipSettings m_settings;
UINT_32 m_colorBaseIndex;
UINT_32 m_htileBaseIndex;
UINT_32 m_dccBaseIndex;
};
} // V2
} // Addr
#endif
src/amd/addrlib/src/gfx12/gfx12SwizzlePattern.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
************************************************************************************************************************
* @file gfx12SwizzlePattern.h
* @brief swizzle pattern for gfx12.
************************************************************************************************************************
*/
#ifndef __GFX12_SWIZZLE_PATTERN_H__
#define __GFX12_SWIZZLE_PATTERN_H__
namespace Addr
{
namespace V3
{
const ADDR_SW_PATINFO GFX12_SW_256B_2D_1xAA_PATINFO[] =
{
{ 0, 0, 0, 0, } , // 1 BPE @ SW_256B_2D_1xAA
{ 1, 0, 0, 0, } , // 2 BPE @ SW_256B_2D_1xAA
{ 2, 0, 0, 0, } , // 4 BPE @ SW_256B_2D_1xAA
{ 3, 0, 0, 0, } , // 8 BPE @ SW_256B_2D_1xAA
{ 4, 0, 0, 0, } , // 16 BPE @ SW_256B_2D_1xAA
};
const ADDR_SW_PATINFO GFX12_SW_256B_2D_2xAA_PATINFO[] =
{
{ 5, 0, 0, 0, } , // 1 BPE @ SW_256B_2D_2xAA
{ 6, 0, 0, 0, } , // 2 BPE @ SW_256B_2D_2xAA
{ 7, 0, 0, 0, } , // 4 BPE @ SW_256B_2D_2xAA
{ 8, 0, 0, 0, } , // 8 BPE @ SW_256B_2D_2xAA
{ 9, 0, 0, 0, } , // 16 BPE @ SW_256B_2D_2xAA
};
const ADDR_SW_PATINFO GFX12_SW_256B_2D_4xAA_PATINFO[] =
{
{ 10, 0, 0, 0, } , // 1 BPE @ SW_256B_2D_4xAA
{ 11, 0, 0, 0, } , // 2 BPE @ SW_256B_2D_4xAA
{ 12, 0, 0, 0, } , // 4 BPE @ SW_256B_2D_4xAA
{ 13, 0, 0, 0, } , // 8 BPE @ SW_256B_2D_4xAA
{ 14, 0, 0, 0, } , // 16 BPE @ SW_256B_2D_4xAA
};
const ADDR_SW_PATINFO GFX12_SW_256B_2D_8xAA_PATINFO[] =
{
{ 15, 0, 0, 0, } , // 1 BPE @ SW_256B_2D_8xAA
{ 16, 0, 0, 0, } , // 2 BPE @ SW_256B_2D_8xAA
{ 17, 0, 0, 0, } , // 4 BPE @ SW_256B_2D_8xAA
{ 18, 0, 0, 0, } , // 8 BPE @ SW_256B_2D_8xAA
{ 19, 0, 0, 0, } , // 16 BPE @ SW_256B_2D_8xAA
};
const ADDR_SW_PATINFO GFX12_SW_4KB_2D_1xAA_PATINFO[] =
{
{ 0, 1, 0, 0, } , // 1 BPE @ SW_4KB_2D_1xAA
{ 1, 2, 0, 0, } , // 2 BPE @ SW_4KB_2D_1xAA
{ 2, 3, 0, 0, } , // 4 BPE @ SW_4KB_2D_1xAA
{ 3, 4, 0, 0, } , // 8 BPE @ SW_4KB_2D_1xAA
{ 4, 5, 0, 0, } , // 16 BPE @ SW_4KB_2D_1xAA
};
const ADDR_SW_PATINFO GFX12_SW_4KB_2D_2xAA_PATINFO[] =
{
{ 5, 2, 0, 0, } , // 1 BPE @ SW_4KB_2D_2xAA
{ 6, 3, 0, 0, } , // 2 BPE @ SW_4KB_2D_2xAA
{ 7, 4, 0, 0, } , // 4 BPE @ SW_4KB_2D_2xAA
{ 8, 5, 0, 0, } , // 8 BPE @ SW_4KB_2D_2xAA
{ 9, 6, 0, 0, } , // 16 BPE @ SW_4KB_2D_2xAA
};
const ADDR_SW_PATINFO GFX12_SW_4KB_2D_4xAA_PATINFO[] =
{
{ 10, 3, 0, 0, } , // 1 BPE @ SW_4KB_2D_4xAA
{ 11, 4, 0, 0, } , // 2 BPE @ SW_4KB_2D_4xAA
{ 12, 5, 0, 0, } , // 4 BPE @ SW_4KB_2D_4xAA
{ 13, 6, 0, 0, } , // 8 BPE @ SW_4KB_2D_4xAA
{ 14, 7, 0, 0, } , // 16 BPE @ SW_4KB_2D_4xAA
};
const ADDR_SW_PATINFO GFX12_SW_4KB_2D_8xAA_PATINFO[] =
{
{ 15, 4, 0, 0, } , // 1 BPE @ SW_4KB_2D_8xAA
{ 16, 5, 0, 0, } , // 2 BPE @ SW_4KB_2D_8xAA
{ 17, 6, 0, 0, } , // 4 BPE @ SW_4KB_2D_8xAA
{ 18, 7, 0, 0, } , // 8 BPE @ SW_4KB_2D_8xAA
{ 19, 8, 0, 0, } , // 16 BPE @ SW_4KB_2D_8xAA
};
const ADDR_SW_PATINFO GFX12_SW_64KB_2D_1xAA_PATINFO[] =
{
{ 0, 1, 1, 0, } , // 1 BPE @ SW_64KB_2D_1xAA
{ 1, 2, 2, 0, } , // 2 BPE @ SW_64KB_2D_1xAA
{ 2, 3, 3, 0, } , // 4 BPE @ SW_64KB_2D_1xAA
{ 3, 4, 4, 0, } , // 8 BPE @ SW_64KB_2D_1xAA
{ 4, 5, 5, 0, } , // 16 BPE @ SW_64KB_2D_1xAA
};
const ADDR_SW_PATINFO GFX12_SW_64KB_2D_2xAA_PATINFO[] =
{
{ 5, 2, 2, 0, } , // 1 BPE @ SW_64KB_2D_2xAA
{ 6, 3, 3, 0, } , // 2 BPE @ SW_64KB_2D_2xAA
{ 7, 4, 4, 0, } , // 4 BPE @ SW_64KB_2D_2xAA
{ 8, 5, 5, 0, } , // 8 BPE @ SW_64KB_2D_2xAA
{ 9, 6, 6, 0, } , // 16 BPE @ SW_64KB_2D_2xAA
};
const ADDR_SW_PATINFO GFX12_SW_64KB_2D_4xAA_PATINFO[] =
{
{ 10, 3, 3, 0, } , // 1 BPE @ SW_64KB_2D_4xAA
{ 11, 4, 4, 0, } , // 2 BPE @ SW_64KB_2D_4xAA
{ 12, 5, 5, 0, } , // 4 BPE @ SW_64KB_2D_4xAA
{ 13, 6, 6, 0, } , // 8 BPE @ SW_64KB_2D_4xAA
{ 14, 7, 7, 0, } , // 16 BPE @ SW_64KB_2D_4xAA
};
const ADDR_SW_PATINFO GFX12_SW_64KB_2D_8xAA_PATINFO[] =
{
{ 15, 4, 4, 0, } , // 1 BPE @ SW_64KB_2D_8xAA
{ 16, 5, 5, 0, } , // 2 BPE @ SW_64KB_2D_8xAA
{ 17, 6, 6, 0, } , // 4 BPE @ SW_64KB_2D_8xAA
{ 18, 7, 7, 0, } , // 8 BPE @ SW_64KB_2D_8xAA
{ 19, 8, 8, 0, } , // 16 BPE @ SW_64KB_2D_8xAA
};
const ADDR_SW_PATINFO GFX12_SW_256KB_2D_1xAA_PATINFO[] =
{
{ 0, 1, 1, 1, } , // 1 BPE @ SW_256KB_2D_1xAA
{ 1, 2, 2, 2, } , // 2 BPE @ SW_256KB_2D_1xAA
{ 2, 3, 3, 3, } , // 4 BPE @ SW_256KB_2D_1xAA
{ 3, 4, 4, 4, } , // 8 BPE @ SW_256KB_2D_1xAA
{ 4, 5, 5, 5, } , // 16 BPE @ SW_256KB_2D_1xAA
};
const ADDR_SW_PATINFO GFX12_SW_256KB_2D_2xAA_PATINFO[] =
{
{ 5, 2, 2, 2, } , // 1 BPE @ SW_256KB_2D_2xAA
{ 6, 3, 3, 3, } , // 2 BPE @ SW_256KB_2D_2xAA
{ 7, 4, 4, 4, } , // 4 BPE @ SW_256KB_2D_2xAA
{ 8, 5, 5, 5, } , // 8 BPE @ SW_256KB_2D_2xAA
{ 9, 6, 6, 6, } , // 16 BPE @ SW_256KB_2D_2xAA
};
const ADDR_SW_PATINFO GFX12_SW_256KB_2D_4xAA_PATINFO[] =
{
{ 10, 3, 3, 3, } , // 1 BPE @ SW_256KB_2D_4xAA
{ 11, 4, 4, 4, } , // 2 BPE @ SW_256KB_2D_4xAA
{ 12, 5, 5, 5, } , // 4 BPE @ SW_256KB_2D_4xAA
{ 13, 6, 6, 6, } , // 8 BPE @ SW_256KB_2D_4xAA
{ 14, 7, 7, 7, } , // 16 BPE @ SW_256KB_2D_4xAA
};
const ADDR_SW_PATINFO GFX12_SW_256KB_2D_8xAA_PATINFO[] =
{
{ 15, 4, 4, 4, } , // 1 BPE @ SW_256KB_2D_8xAA
{ 16, 5, 5, 5, } , // 2 BPE @ SW_256KB_2D_8xAA
{ 17, 6, 6, 6, } , // 4 BPE @ SW_256KB_2D_8xAA
{ 18, 7, 7, 7, } , // 8 BPE @ SW_256KB_2D_8xAA
{ 19, 8, 8, 8, } , // 16 BPE @ SW_256KB_2D_8xAA
};
const ADDR_SW_PATINFO GFX12_SW_4KB_3D_PATINFO[] =
{
{ 20, 9, 0, 0, } , // 1 BPE @ SW_4KB_3D
{ 21, 10, 0, 0, } , // 2 BPE @ SW_4KB_3D
{ 22, 11, 0, 0, } , // 4 BPE @ SW_4KB_3D
{ 23, 12, 0, 0, } , // 8 BPE @ SW_4KB_3D
{ 24, 13, 0, 0, } , // 16 BPE @ SW_4KB_3D
};
const ADDR_SW_PATINFO GFX12_SW_64KB_3D_PATINFO[] =
{
{ 20, 9, 9, 0, } , // 1 BPE @ SW_64KB_3D
{ 21, 10, 10, 0, } , // 2 BPE @ SW_64KB_3D
{ 22, 11, 11, 0, } , // 4 BPE @ SW_64KB_3D
{ 23, 12, 12, 0, } , // 8 BPE @ SW_64KB_3D
{ 24, 13, 13, 0, } , // 16 BPE @ SW_64KB_3D
};
const ADDR_SW_PATINFO GFX12_SW_256KB_3D_PATINFO[] =
{
{ 20, 9, 9, 9, } , // 1 BPE @ SW_256KB_3D
{ 21, 10, 10, 9, } , // 2 BPE @ SW_256KB_3D
{ 22, 11, 11, 10, } , // 4 BPE @ SW_256KB_3D
{ 23, 12, 12, 11, } , // 8 BPE @ SW_256KB_3D
{ 24, 13, 13, 11, } , // 16 BPE @ SW_256KB_3D
};
const UINT_64 GFX12_SW_PATTERN_NIBBLE1[][8] =
{
{X0, X1, Y0, X2, Y1, Y2, X3, Y3, }, // 0
{0, X0, Y0, X1, Y1, X2, Y2, X3, }, // 1
{0, 0, X0, Y0, X1, Y1, X2, Y2, }, // 2
{0, 0, 0, X0, Y0, X1, X2, Y1, }, // 3
{0, 0, 0, 0, X0, Y0, X1, Y1, }, // 4
{S0, X0, Y0, X1, Y1, X2, Y2, X3, }, // 5
{0, S0, X0, Y0, X1, Y1, X2, Y2, }, // 6
{0, 0, S0, X0, Y0, X1, Y1, X2, }, // 7
{0, 0, 0, S0, X0, Y0, X1, Y1, }, // 8
{0, 0, 0, 0, S0, X0, Y0, X1, }, // 9
{S0, S1, X0, Y0, X1, Y1, X2, Y2, }, // 10
{0, S0, S1, X0, Y0, X1, Y1, X2, }, // 11
{0, 0, S0, S1, X0, Y0, X1, Y1, }, // 12
{0, 0, 0, S0, S1, X0, Y0, X1, }, // 13
{0, 0, 0, 0, S0, S1, X0, Y0, }, // 14
{S0, S1, S2, X0, Y0, X1, Y1, X2, }, // 15
{0, S0, S1, S2, X0, Y0, X1, Y1, }, // 16
{0, 0, S0, S1, S2, X0, Y0, X1, }, // 17
{0, 0, 0, S0, S1, S2, X0, Y0, }, // 18
{0, 0, 0, 0, S0, S1, S2, X0, }, // 19
{X0, X1, Z0, Y0, Y1, Z1, X2, Z2, }, // 20
{0, X0, Z0, Y0, X1, Z1, Y1, Z2, }, // 21
{0, 0, X0, Y0, X1, Z0, Y1, Z1, }, // 22
{0, 0, 0, X0, Y0, Z0, X1, Z1, }, // 23
{0, 0, 0, 0, X0, Z0, Y0, Z1, }, // 24
};
const UINT_64 GFX12_SW_PATTERN_NIBBLE2[][4] =
{
{0, 0, 0, 0, }, // 0
{Y4, X4, Y5, X5, }, // 1
{Y3, X4, Y4, X5, }, // 2
{Y3, X3, Y4, X4, }, // 3
{Y2, X3, Y3, X4, }, // 4
{Y2, X2, Y3, X3, }, // 5
{Y1, X2, Y2, X3, }, // 6
{Y1, X1, Y2, X2, }, // 7
{Y0, X1, Y1, X2, }, // 8
{Y2, X3, Z3, Y3, }, // 9
{Y2, X2, Z3, Y3, }, // 10
{Y2, X2, Z2, Y3, }, // 11
{Y1, X2, Z2, Y2, }, // 12
{Y1, X1, Z2, Y2, }, // 13
};
const UINT_64 GFX12_SW_PATTERN_NIBBLE3[][4] =
{
{0, 0, 0, 0, }, // 0
{Y6, X6, Y7, X7, }, // 1
{Y5, X6, Y6, X7, }, // 2
{Y5, X5, Y6, X6, }, // 3
{Y4, X5, Y5, X6, }, // 4
{Y4, X4, Y5, X5, }, // 5
{Y3, X4, Y4, X5, }, // 6
{Y3, X3, Y4, X4, }, // 7
{Y2, X3, Y3, X4, }, // 8
{X4, Z4, Y4, X5, }, // 9
{X3, Z4, Y4, X4, }, // 10
{X3, Z3, Y4, X4, }, // 11
{X3, Z3, Y3, X4, }, // 12
{X2, Z3, Y3, X3, }, // 13
};
const UINT_64 GFX12_SW_PATTERN_NIBBLE4[][2] =
{
{0, 0, }, // 0
{Y8, X8, }, // 1
{Y7, X8, }, // 2
{Y7, X7, }, // 3
{Y6, X7, }, // 4
{Y6, X6, }, // 5
{Y5, X6, }, // 6
{Y5, X5, }, // 7
{Y4, X5, }, // 8
{Z5, Y5, }, // 9
{Z4, Y5, }, // 10
{Z4, Y4, }, // 11
};
} // V3
} // Addr
#endif
src/amd/addrlib/src/gfx12/gfx12addrlib.cpp
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/*
************************************************************************************************************************
*
* Copyright (C) 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
************************************************************************************************************************
* @file gfx12addrlib.h
* @brief Contains the Gfx12Lib class definition.
************************************************************************************************************************
*/
#ifndef __GFX12_ADDR_LIB_H__
#define __GFX12_ADDR_LIB_H__
#include "addrlib3.h"
#include "coord.h"
#include "gfx12SwizzlePattern.h"
namespace Addr
{
namespace V3
{
/**
************************************************************************************************************************
* @brief This class is the GFX12 specific address library
* function set.
************************************************************************************************************************
*/
class Gfx12Lib : public Lib
{
public:
/// Creates Gfx12Lib object
static Addr::Lib* CreateObj(const Client* pClient)
{
VOID* pMem = Object::ClientAlloc(sizeof(Gfx12Lib), pClient);
return (pMem != NULL) ? new (pMem) Gfx12Lib(pClient) : NULL;
}
protected:
Gfx12Lib(const Client* pClient);
virtual ~Gfx12Lib();
// Meta surfaces such as Hi-S/Z are essentially images on GFX12, so just return the max
// image alignment.
virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const override { return 256 * 1024; }
UINT_32 GetMaxNumMipsInTail(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn) const;
BOOL_32 IsInMipTail(
const ADDR_EXTENT3D& mipTailDim, ///< The output of GetMipTailDim() function which is dimensions of the
/// largest mip level in the tail (again, only 4kb/64kb/256kb block).
const ADDR_EXTENT3D& mipDims, ///< The dimensions of the mip level being queried now.
INT_32 maxNumMipsInTail, ///< The output of GetMaxNumMipsInTail() function which is the maximal
/// number of the mip levels that could fit in the tail of larger
/// block.
INT_32 numMipsToTheEnd ///< This is (numMipLevels - mipIdx) and it may be negative when called
/// in SanityCheckSurfSize() since mipIdx has to be in [0, 16].
) const
{
BOOL_32 inTail = ((mipDims.width <= mipTailDim.width) &&
(mipDims.height <= mipTailDim.height) &&
(numMipsToTheEnd <= maxNumMipsInTail));
return inTail;
}
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordLinear(
const ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pSurfInfoIn,
ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const override;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
const ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR3_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const override;
virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView(
const ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn,
ADDR3_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const override;
virtual VOID HwlComputeSubResourceOffsetForSwizzlePattern(
const ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR3_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const override;
virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
const ADDR3_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR3_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const override;
virtual UINT_32 HwlGetEquationIndex(
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn) const override;
virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const override
{
*ppEquationTable = m_equationTable;
return m_numEquations;
}
BOOL_32 HwlValidateNonSwModeParams(const ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT* pIn) const override;
virtual ADDR_E_RETURNCODE HwlGetPossibleSwizzleModes(
const ADDR3_GET_POSSIBLE_SWIZZLE_MODE_INPUT* pIn,
ADDR3_GET_POSSIBLE_SWIZZLE_MODE_OUTPUT* pOut) const override;
virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) override;
protected:
virtual VOID HwlCalcBlockSize(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn,
ADDR_EXTENT3D* pExtent) const override final;
ADDR_EXTENT3D HwlGetMicroBlockSize(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn) const;
virtual ADDR_EXTENT3D HwlGetMipInTailMaxSize(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn,
const ADDR_EXTENT3D& blockDims) const override final;
private:
static const SwizzleModeFlags SwizzleModeTable[ADDR3_MAX_TYPE];
// Number of unique swizzle patterns (one entry per swizzle mode + MSAA + bpp configuration)
static const UINT_32 NumSwizzlePatterns = 19 * MaxElementBytesLog2;
// Equation table
ADDR_EQUATION m_equationTable[NumSwizzlePatterns];
/**
************************************************************************************************************************
* @brief Bitmasks for swizzle mode determination on GFX12
************************************************************************************************************************
*/
static const UINT_32 Blk256KBSwModeMask = (1u << ADDR3_256KB_2D) |
(1u << ADDR3_256KB_3D);
static const UINT_32 Blk64KBSwModeMask = (1u << ADDR3_64KB_2D) |
(1u << ADDR3_64KB_3D);
static const UINT_32 Blk4KBSwModeMask = (1u << ADDR3_4KB_2D) |
(1u << ADDR3_4KB_3D);
static const UINT_32 Blk256BSwModeMask = (1u << ADDR3_256B_2D);
static const UINT_32 MaxImageDim = 32768; // Max image size is 32k
static const UINT_32 MaxMipLevels = 16;
virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) override;
virtual ADDR_E_RETURNCODE HwlComputeStereoInfo(
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32* pAlignY,
UINT_32* pRightXor) const override;
void SanityCheckSurfSize(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn,
const ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlCopyMemToSurface(
const ADDR3_COPY_MEMSURFACE_INPUT* pIn,
const ADDR3_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const override;
virtual ADDR_E_RETURNCODE HwlCopySurfaceToMem(
const ADDR3_COPY_MEMSURFACE_INPUT* pIn,
const ADDR3_COPY_MEMSURFACE_REGION* pRegions,
UINT_32 regionCount) const override;
// Initialize equation table
VOID InitEquationTable();
// Initialize block dimension table
VOID InitBlockDimensionTable();
VOID GetSwizzlePatternFromPatternInfo(
const ADDR_SW_PATINFO* pPatInfo,
ADDR_BIT_SETTING (&pSwizzle)[Log2Size256K]) const
{
memcpy(pSwizzle,
GFX12_SW_PATTERN_NIBBLE1[pPatInfo->nibble1Idx],
sizeof(GFX12_SW_PATTERN_NIBBLE1[pPatInfo->nibble1Idx]));
memcpy(&pSwizzle[8],
GFX12_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx],
sizeof(GFX12_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx]));
memcpy(&pSwizzle[12],
GFX12_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx],
sizeof(GFX12_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx]));
memcpy(&pSwizzle[16],
GFX12_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx],
sizeof(GFX12_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx]));
}
VOID ConvertSwizzlePatternToEquation(
UINT_32 elemLog2,
Addr3SwizzleMode swMode,
const ADDR_SW_PATINFO* pPatInfo,
ADDR_EQUATION* pEquation) const;
ADDR_EXTENT3D GetBaseMipExtents(
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
INT_32 CalcMipInTail(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn,
const ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
UINT_32 mipLevel) const;
UINT_32 CalcMipOffset(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn,
UINT_32 mipInTail) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR3_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const override;
static ADDR_EXTENT3D GetMipExtent(
const ADDR_EXTENT3D& mip0,
UINT_32 mipId)
{
return {
ShiftCeil(Max(mip0.width, 1u), mipId),
ShiftCeil(Max(mip0.height, 1u), mipId),
ShiftCeil(Max(mip0.depth, 1u), mipId)
};
}
const ADDR_SW_PATINFO* GetSwizzlePatternInfo(
Addr3SwizzleMode swizzleMode,
UINT_32 log2Elem,
UINT_32 numFrag) const;
VOID GetMipOffset(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn,
ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
VOID GetMipOrigin(
const ADDR3_COMPUTE_SURFACE_INFO_PARAMS_INPUT* pIn,
const ADDR_EXTENT3D& mipExtentFirstInTail,
ADDR3_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
};
} // V3
} // Addr
#endif
src/amd/addrlib/src/gfx9/gfx9addrlib.cpp
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
************************************************************************************************************************
* @file gfx9addrlib.h
* @brief Contgfx9ns the Gfx9Lib class definition.
************************************************************************************************************************
*/
#ifndef __GFX9_ADDR_LIB_H__
#define __GFX9_ADDR_LIB_H__
#include "addrlib2.h"
#include "coord.h"
namespace Addr
{
namespace V2
{
/**
************************************************************************************************************************
* @brief GFX9 specific settings structure.
************************************************************************************************************************
*/
struct Gfx9ChipSettings
{
struct
{
// Asic/Generation name
UINT_32 isArcticIsland : 1;
UINT_32 isVega10 : 1;
UINT_32 isRaven : 1;
UINT_32 isVega12 : 1;
UINT_32 isVega20 : 1;
UINT_32 reserved0 : 27;
// Display engine IP version name
UINT_32 isDce12 : 1;
UINT_32 isDcn1 : 1;
UINT_32 isDcn2 : 1;
UINT_32 reserved1 : 29;
// Misc configuration bits
UINT_32 metaBaseAlignFix : 1;
UINT_32 depthPipeXorDisable : 1;
UINT_32 htileAlignFix : 1;
UINT_32 applyAliasFix : 1;
UINT_32 htileCacheRbConflict: 1;
UINT_32 reserved2 : 27;
};
};
/**
************************************************************************************************************************
* @brief GFX9 data surface type.
************************************************************************************************************************
*/
enum Gfx9DataType
{
Gfx9DataColor,
Gfx9DataDepthStencil,
Gfx9DataFmask
};
const UINT_32 Gfx9LinearSwModeMask = (1u << ADDR_SW_LINEAR);
const UINT_32 Gfx9Blk256BSwModeMask = (1u << ADDR_SW_256B_S) |
(1u << ADDR_SW_256B_D) |
(1u << ADDR_SW_256B_R);
const UINT_32 Gfx9Blk4KBSwModeMask = (1u << ADDR_SW_4KB_Z) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_4KB_R) |
(1u << ADDR_SW_4KB_Z_X) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_4KB_R_X);
const UINT_32 Gfx9Blk64KBSwModeMask = (1u << ADDR_SW_64KB_Z) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_R) |
(1u << ADDR_SW_64KB_Z_T) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_64KB_R_T) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx9ZSwModeMask = (1u << ADDR_SW_4KB_Z) |
(1u << ADDR_SW_64KB_Z) |
(1u << ADDR_SW_64KB_Z_T) |
(1u << ADDR_SW_4KB_Z_X) |
(1u << ADDR_SW_64KB_Z_X);
const UINT_32 Gfx9StandardSwModeMask = (1u << ADDR_SW_256B_S) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_64KB_S_X);
const UINT_32 Gfx9DisplaySwModeMask = (1u << ADDR_SW_256B_D) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_D_X);
const UINT_32 Gfx9RotateSwModeMask = (1u << ADDR_SW_256B_R) |
(1u << ADDR_SW_4KB_R) |
(1u << ADDR_SW_64KB_R) |
(1u << ADDR_SW_64KB_R_T) |
(1u << ADDR_SW_4KB_R_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx9XSwModeMask = (1u << ADDR_SW_4KB_Z_X) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_4KB_R_X) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx9TSwModeMask = (1u << ADDR_SW_64KB_Z_T) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_64KB_R_T);
const UINT_32 Gfx9XorSwModeMask = Gfx9XSwModeMask |
Gfx9TSwModeMask;
const UINT_32 Gfx9AllSwModeMask = Gfx9LinearSwModeMask |
Gfx9ZSwModeMask |
Gfx9StandardSwModeMask |
Gfx9DisplaySwModeMask |
Gfx9RotateSwModeMask;
const UINT_32 Gfx9Rsrc1dSwModeMask = Gfx9LinearSwModeMask;
const UINT_32 Gfx9Rsrc2dSwModeMask = Gfx9AllSwModeMask;
const UINT_32 Gfx9Rsrc3dSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9RotateSwModeMask;
const UINT_32 Gfx9Rsrc2dPrtSwModeMask = (Gfx9Blk4KBSwModeMask | Gfx9Blk64KBSwModeMask) & ~Gfx9XSwModeMask;
const UINT_32 Gfx9Rsrc3dPrtSwModeMask = Gfx9Rsrc2dPrtSwModeMask & ~Gfx9RotateSwModeMask & ~Gfx9DisplaySwModeMask;
const UINT_32 Gfx9Rsrc3dThinSwModeMask = Gfx9DisplaySwModeMask & ~Gfx9Blk256BSwModeMask;
const UINT_32 Gfx9Rsrc3dThin4KBSwModeMask = Gfx9Rsrc3dThinSwModeMask & Gfx9Blk4KBSwModeMask;
const UINT_32 Gfx9Rsrc3dThin64KBSwModeMask = Gfx9Rsrc3dThinSwModeMask & Gfx9Blk64KBSwModeMask;
const UINT_32 Gfx9Rsrc3dThickSwModeMask = Gfx9Rsrc3dSwModeMask & ~(Gfx9Rsrc3dThinSwModeMask | Gfx9LinearSwModeMask);
const UINT_32 Gfx9Rsrc3dThick4KBSwModeMask = Gfx9Rsrc3dThickSwModeMask & Gfx9Blk4KBSwModeMask;
const UINT_32 Gfx9Rsrc3dThick64KBSwModeMask = Gfx9Rsrc3dThickSwModeMask & Gfx9Blk64KBSwModeMask;
const UINT_32 Gfx9MsaaSwModeMask = Gfx9AllSwModeMask & ~Gfx9Blk256BSwModeMask & ~Gfx9LinearSwModeMask;
const UINT_32 Dce12NonBpp32SwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_4KB_R) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_R) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_4KB_R_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Dce12Bpp32SwModeMask = (1u << ADDR_SW_256B_D) |
(1u << ADDR_SW_256B_R) |
Dce12NonBpp32SwModeMask;
const UINT_32 Dcn1NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_64KB_S_X);
const UINT_32 Dcn1Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_D_X) |
Dcn1NonBpp64SwModeMask;
const UINT_32 Dcn2NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_S_X);
const UINT_32 Dcn2Bpp64SwModeMask = (1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_64KB_D_X) |
Dcn2NonBpp64SwModeMask;
/**
************************************************************************************************************************
* @brief GFX9 meta equation parameters
************************************************************************************************************************
*/
struct MetaEqParams
{
UINT_32 maxMip;
UINT_32 elementBytesLog2;
UINT_32 numSamplesLog2;
ADDR2_META_FLAGS metaFlag;
Gfx9DataType dataSurfaceType;
AddrSwizzleMode swizzleMode;
AddrResourceType resourceType;
UINT_32 metaBlkWidthLog2;
UINT_32 metaBlkHeightLog2;
UINT_32 metaBlkDepthLog2;
UINT_32 compBlkWidthLog2;
UINT_32 compBlkHeightLog2;
UINT_32 compBlkDepthLog2;
};
/**
************************************************************************************************************************
* @brief This class is the GFX9 specific address library
* function set.
************************************************************************************************************************
*/
class Gfx9Lib : public Lib
{
public:
/// Creates Gfx9Lib object
static Addr::Lib* CreateObj(const Client* pClient)
{
VOID* pMem = Object::ClientAlloc(sizeof(Gfx9Lib), pClient);
return (pMem != NULL) ? new (pMem) Gfx9Lib(pClient) : NULL;
}
protected:
Gfx9Lib(const Client* pClient);
virtual ~Gfx9Lib();
virtual BOOL_32 HwlIsStandardSwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isStd ||
(IsTex3d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp);
}
virtual BOOL_32 HwlIsDisplaySwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return IsTex2d(resourceType) && m_swizzleModeTable[swizzleMode].isDisp;
}
virtual BOOL_32 HwlIsThin(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return ((IsTex2d(resourceType) == TRUE) ||
((IsTex3d(resourceType) == TRUE) &&
(m_swizzleModeTable[swizzleMode].isZ == FALSE) &&
(m_swizzleModeTable[swizzleMode].isStd == FALSE)));
}
virtual BOOL_32 HwlIsThick(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return (IsTex3d(resourceType) &&
(m_swizzleModeTable[swizzleMode].isZ || m_swizzleModeTable[swizzleMode].isStd));
}
virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo(
const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn);
virtual VOID HwlComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
virtual UINT_32 HwlGetEquationIndex(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation(
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
UINT_32 elementBytesLog2,
ADDR_EQUATION* pEquation) const;
virtual ADDR_E_RETURNCODE HwlComputeThinEquation(
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
UINT_32 elementBytesLog2,
ADDR_EQUATION* pEquation) const;
virtual ADDR_E_RETURNCODE HwlComputeThickEquation(
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
UINT_32 elementBytesLog2,
ADDR_EQUATION* pEquation) const;
// Get equation table pointer and number of equations
virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
{
*ppEquationTable = m_equationTable;
return m_numEquations;
}
virtual BOOL_32 IsEquationSupported(
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
UINT_32 elementBytesLog2) const;
virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual UINT_32 HwlComputeMaxBaseAlignments() const;
virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const;
virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn);
virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
virtual VOID ComputeThinBlockDimension(
UINT_32* pWidth,
UINT_32* pHeight,
UINT_32* pDepth,
UINT_32 bpp,
UINT_32 numSamples,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const;
private:
VOID GetRbEquation(CoordEq* pRbEq, UINT_32 rbPerSeLog2, UINT_32 seLog2) const;
VOID GetDataEquation(CoordEq* pDataEq, Gfx9DataType dataSurfaceType,
AddrSwizzleMode swizzleMode, AddrResourceType resourceType,
UINT_32 elementBytesLog2, UINT_32 numSamplesLog2) const;
VOID GetPipeEquation(CoordEq* pPipeEq, CoordEq* pDataEq,
UINT_32 pipeInterleaveLog2, UINT_32 numPipesLog2,
UINT_32 numSamplesLog2, Gfx9DataType dataSurfaceType,
AddrSwizzleMode swizzleMode, AddrResourceType resourceType) const;
VOID GenMetaEquation(CoordEq* pMetaEq, UINT_32 maxMip,
UINT_32 elementBytesLog2, UINT_32 numSamplesLog2,
ADDR2_META_FLAGS metaFlag, Gfx9DataType dataSurfaceType,
AddrSwizzleMode swizzleMode, AddrResourceType resourceType,
UINT_32 metaBlkWidthLog2, UINT_32 metaBlkHeightLog2,
UINT_32 metaBlkDepthLog2, UINT_32 compBlkWidthLog2,
UINT_32 compBlkHeightLog2, UINT_32 compBlkDepthLog2) const;
const CoordEq* GetMetaEquation(const MetaEqParams& metaEqParams);
VOID GetMetaMipInfo(UINT_32 numMipLevels, Dim3d* pMetaBlkDim,
BOOL_32 dataThick, ADDR2_META_MIP_INFO* pInfo,
UINT_32 mip0Width, UINT_32 mip0Height, UINT_32 mip0Depth,
UINT_32* pNumMetaBlkX, UINT_32* pNumMetaBlkY, UINT_32* pNumMetaBlkZ) const;
BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
ADDR_E_RETURNCODE ComputeSurfaceLinearPadding(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32* pMipmap0PaddedWidth,
UINT_32* pSlice0PaddedHeight,
ADDR2_MIP_INFO* pMipInfo = NULL) const;
static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType)
{
ADDR2_BLOCK_SET allowedBlockSet = {};
allowedBlockSet.micro = (allowedSwModeSet.value & Gfx9Blk256BSwModeMask) ? TRUE : FALSE;
allowedBlockSet.linear = (allowedSwModeSet.value & Gfx9LinearSwModeMask) ? TRUE : FALSE;
if (rsrcType == ADDR_RSRC_TEX_3D)
{
allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx9Rsrc3dThin4KBSwModeMask) ? TRUE : FALSE;
allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx9Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE;
allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx9Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE;
allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx9Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE;
}
else
{
allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx9Blk4KBSwModeMask) ? TRUE : FALSE;
allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx9Blk64KBSwModeMask) ? TRUE : FALSE;
}
return allowedBlockSet;
}
static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)
{
ADDR2_SWTYPE_SET allowedSwSet = {};
allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx9ZSwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx9StandardSwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx9DisplaySwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx9RotateSwModeMask) ? TRUE : FALSE;
return allowedSwSet;
}
BOOL_32 IsInMipTail(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
Dim3d mipTailDim,
UINT_32 width,
UINT_32 height,
UINT_32 depth) const
{
BOOL_32 inTail = ((width <= mipTailDim.w) &&
(height <= mipTailDim.h) &&
(IsThin(resourceType, swizzleMode) || (depth <= mipTailDim.d)));
return inTail;
}
BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
UINT_32 GetBankXorBits(UINT_32 macroBlockBits) const
{
UINT_32 pipeBits = GetPipeXorBits(macroBlockBits);
// Bank xor bits
UINT_32 bankBits = Min(macroBlockBits - pipeBits - m_pipeInterleaveLog2, m_banksLog2);
return bankBits;
}
UINT_32 ComputeSurfaceBaseAlignTiled(AddrSwizzleMode swizzleMode) const
{
UINT_32 baseAlign;
if (IsXor(swizzleMode))
{
baseAlign = GetBlockSize(swizzleMode);
}
else
{
baseAlign = 256;
}
return baseAlign;
}
// Initialize equation table
VOID InitEquationTable();
ADDR_E_RETURNCODE ComputeStereoInfo(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
UINT_32* pHeightAlign) const;
UINT_32 GetMipChainInfo(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 bpp,
UINT_32 mip0Width,
UINT_32 mip0Height,
UINT_32 mip0Depth,
UINT_32 blockWidth,
UINT_32 blockHeight,
UINT_32 blockDepth,
UINT_32 numMipLevel,
ADDR2_MIP_INFO* pMipInfo) const;
VOID GetMetaMiptailInfo(
ADDR2_META_MIP_INFO* pInfo,
Dim3d mipCoord,
UINT_32 numMipInTail,
Dim3d* pMetaBlkDim) const;
Dim3d GetMipStartPos(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 width,
UINT_32 height,
UINT_32 depth,
UINT_32 blockWidth,
UINT_32 blockHeight,
UINT_32 blockDepth,
UINT_32 mipId,
UINT_32 log2ElementBytes,
UINT_32* pMipTailBytesOffset) const;
AddrMajorMode GetMajorMode(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 mip0WidthInBlk,
UINT_32 mip0HeightInBlk,
UINT_32 mip0DepthInBlk) const
{
BOOL_32 yMajor = (mip0WidthInBlk < mip0HeightInBlk);
BOOL_32 xMajor = (yMajor == FALSE);
if (IsThick(resourceType, swizzleMode))
{
yMajor = yMajor && (mip0HeightInBlk >= mip0DepthInBlk);
xMajor = xMajor && (mip0WidthInBlk >= mip0DepthInBlk);
}
AddrMajorMode majorMode;
if (xMajor)
{
majorMode = ADDR_MAJOR_X;
}
else if (yMajor)
{
majorMode = ADDR_MAJOR_Y;
}
else
{
majorMode = ADDR_MAJOR_Z;
}
return majorMode;
}
Dim3d GetDccCompressBlk(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 bpp) const
{
UINT_32 index = Log2(bpp >> 3);
Dim3d compressBlkDim;
if (IsThin(resourceType, swizzleMode))
{
compressBlkDim.w = Block256_2d[index].w;
compressBlkDim.h = Block256_2d[index].h;
compressBlkDim.d = 1;
}
else if (IsStandardSwizzle(resourceType, swizzleMode))
{
compressBlkDim = Block256_3dS[index];
}
else
{
compressBlkDim = Block256_3dZ[index];
}
return compressBlkDim;
}
static const UINT_32 MaxSeLog2 = 3;
static const UINT_32 MaxRbPerSeLog2 = 2;
static const Dim3d Block256_3dS[MaxNumOfBpp];
static const Dim3d Block256_3dZ[MaxNumOfBpp];
static const UINT_32 MipTailOffset256B[];
static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE];
static const UINT_32 MaxCachedMetaEq = 2;
Gfx9ChipSettings m_settings;
CoordEq m_cachedMetaEq[MaxCachedMetaEq];
MetaEqParams m_cachedMetaEqKey[MaxCachedMetaEq];
UINT_32 m_metaEqOverrideIndex;
};
} // V2
} // Addr
#endif
src/amd/addrlib/src/r800/ciaddrlib.cpp
+2337
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src/amd/addrlib/src/r800/ciaddrlib.h
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
****************************************************************************************************
* @file ciaddrlib.h
* @brief Contains the CiLib class definition.
****************************************************************************************************
*/
#ifndef __CI_ADDR_LIB_H__
#define __CI_ADDR_LIB_H__
#include "addrlib1.h"
#include "siaddrlib.h"
namespace Addr
{
namespace V1
{
/**
****************************************************************************************************
* @brief This class is the CI specific address library
* function set.
****************************************************************************************************
*/
class CiLib : public SiLib
{
public:
/// Creates CiLib object
static Addr::Lib* CreateObj(const Client* pClient)
{
VOID* pMem = Object::ClientAlloc(sizeof(CiLib), pClient);
return (pMem != NULL) ? new (pMem) CiLib(pClient) : NULL;
}
private:
CiLib(const Client* pClient);
virtual ~CiLib();
protected:
// Hwl interface - defined in AddrLib1
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
virtual ChipFamily HwlConvertChipFamily(
UINT_32 uChipFamily, UINT_32 uChipRevision);
virtual BOOL_32 HwlInitGlobalParams(
const ADDR_CREATE_INPUT* pCreateIn);
virtual ADDR_E_RETURNCODE HwlSetupTileCfg(
UINT_32 bpp, INT_32 index, INT_32 macroModeIndex, ADDR_TILEINFO* pInfo,
AddrTileMode* pMode = 0, AddrTileType* pType = 0) const;
virtual VOID HwlComputeTileDataWidthAndHeightLinear(
UINT_32* pMacroWidth, UINT_32* pMacroHeight,
UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
virtual INT_32 HwlComputeMacroModeIndex(
INT_32 tileIndex, ADDR_SURFACE_FLAGS flags, UINT_32 bpp, UINT_32 numSamples,
ADDR_TILEINFO* pTileInfo, AddrTileMode* pTileMode = NULL, AddrTileType* pTileType = NULL
) const;
// Sub-hwl interface - defined in EgBasedLib
virtual VOID HwlSetupTileInfo(
AddrTileMode tileMode, ADDR_SURFACE_FLAGS flags,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
AddrTileType inTileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual INT_32 HwlPostCheckTileIndex(
const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
INT curIndex = TileIndexInvalid) const;
virtual VOID HwlFmaskPreThunkSurfInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const;
virtual VOID HwlFmaskPostThunkSurfInfo(
const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const;
virtual AddrTileMode HwlDegradeThickTileMode(
AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const;
virtual VOID HwlOverrideTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual VOID HwlOptimizeTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual VOID HwlSelectTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
/// Overwrite tile setting to PRT
virtual VOID HwlSetPrtTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual UINT_32 HwlComputeMaxBaseAlignments() const;
virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const;
virtual VOID HwlPadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32 *PitchAlign, UINT_32 height, UINT_32 heightAlign) const;
virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
private:
VOID ReadGbTileMode(
UINT_32 regValue, TileConfig* pCfg) const;
VOID ReadGbMacroTileCfg(
UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
private:
BOOL_32 InitTileSettingTable(
const UINT_32 *pSetting, UINT_32 noOfEntries);
BOOL_32 InitMacroTileCfgTable(
const UINT_32 *pSetting, UINT_32 noOfEntries);
UINT_64 HwlComputeMetadataNibbleAddress(
UINT_64 uncompressedDataByteAddress,
UINT_64 dataBaseByteAddress,
UINT_64 metadataBaseByteAddress,
UINT_32 metadataBitSize,
UINT_32 elementBitSize,
UINT_32 blockByteSize,
UINT_32 pipeInterleaveBytes,
UINT_32 numOfPipes,
UINT_32 numOfBanks,
UINT_32 numOfSamplesPerSplit) const;
BOOL_32 DepthStencilTileCfgMatch(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
BOOL_32 CheckTcCompatibility(const ADDR_TILEINFO* pTileInfo, UINT_32 bpp, AddrTileMode tileMode,
AddrTileType tileType, const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
BOOL_32 SupportDccAndTcCompatibility() const
{
return ((m_settings.isVolcanicIslands == TRUE) || (m_configFlags.forceDccAndTcCompat == TRUE));
}
BOOL_32 AltTilingEnabled() const
{
return (m_configFlags.enableAltTiling == TRUE);
}
static const UINT_32 MacroTileTableSize = 16;
static const UINT_32 PrtMacroModeOffset = MacroTileTableSize / 2;
static const INT_32 MinDepth2DThinIndex = 0;
static const INT_32 MaxDepth2DThinIndex = 4;
static const INT_32 Depth1DThinIndex = 5;
ADDR_TILEINFO m_macroTileTable[MacroTileTableSize];
UINT_32 m_noOfMacroEntries;
BOOL_32 m_allowNonDispThickModes;
};
} // V1
} // Addr
#endif
src/amd/addrlib/src/r800/egbaddrlib.cpp
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
****************************************************************************************************
* @file egbaddrlib.h
* @brief Contains the EgBasedLib class definition.
****************************************************************************************************
*/
#ifndef __EG_BASED_ADDR_LIB_H__
#define __EG_BASED_ADDR_LIB_H__
#include "addrlib1.h"
namespace Addr
{
namespace V1
{
/// Structures for functions
struct CoordFromBankPipe
{
UINT_32 xBits : 3;
UINT_32 yBits : 4;
UINT_32 xBit3 : 1;
UINT_32 xBit4 : 1;
UINT_32 xBit5 : 1;
UINT_32 yBit3 : 1;
UINT_32 yBit4 : 1;
UINT_32 yBit5 : 1;
UINT_32 yBit6 : 1;
};
/**
****************************************************************************************************
* @brief This class is the Evergreen based address library
* @note Abstract class
****************************************************************************************************
*/
class EgBasedLib : public Lib
{
protected:
EgBasedLib(const Client* pClient);
virtual ~EgBasedLib();
public:
/// Surface info functions
// NOTE: DispatchComputeSurfaceInfo using TileInfo takes both an input and an output.
// On input:
// One or more fields may be 0 to be calculated/defaulted - pre-SI h/w.
// H/W using tile mode index only accepts none or all 0's - SI and newer h/w.
// It then returns the actual tiling configuration used.
// Other methods' TileInfo must be valid on entry
BOOL_32 DispatchComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE DispatchComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
protected:
// Hwl interface
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoord(
const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceCoordFromAddr(
const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSliceTileSwizzle(
const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlExtractBankPipeSwizzle(
const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlCombineBankPipeSwizzle(
UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO* pTileInfo,
UINT_64 baseAddr, UINT_32* pTileSwizzle) const;
virtual ADDR_E_RETURNCODE HwlComputeBaseSwizzle(
const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW(
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const;
virtual UINT_32 HwlComputeHtileBpp(
BOOL_32 isWidth8, BOOL_32 isHeight8) const;
virtual UINT_32 HwlComputeHtileBaseAlign(
BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const;
virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
virtual ADDR_E_RETURNCODE HwlComputeFmaskAddrFromCoord(
const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeFmaskCoordFromAddr(
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
virtual BOOL_32 HwlGetAlignmentInfoMacroTiled(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32* pPitchAlign, UINT_32* pHeightAlign, UINT_32* pSizeAlign) const;
virtual UINT_32 HwlComputeQbStereoRightSwizzle(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pInfo) const;
virtual VOID HwlComputePixelCoordFromOffset(
UINT_32 offset, UINT_32 bpp, UINT_32 numSamples,
AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample,
AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const;
/// Return Cmask block max
virtual BOOL_32 HwlGetMaxCmaskBlockMax() const
{
return 0x3FFF; // 14 bits, 0n16383
}
// Sub-hwl interface
/// Pure virtual function to setup tile info (indices) if client requests to do so
virtual VOID HwlSetupTileInfo(
AddrTileMode tileMode, ADDR_SURFACE_FLAGS flags,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
AddrTileType inTileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
/// Pure virtual function to get pitch alignment for linear modes
virtual UINT_32 HwlGetPitchAlignmentLinear(UINT_32 bpp, ADDR_SURFACE_FLAGS flags) const = 0;
/// Pure virtual function to get size adjustment for linear modes
virtual UINT_64 HwlGetSizeAdjustmentLinear(
AddrTileMode tileMode,
UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
UINT_32 *pPitch, UINT_32 *pHeight, UINT_32 *pHeightAlign) const = 0;
virtual UINT_32 HwlGetPitchAlignmentMicroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples) const;
virtual UINT_64 HwlGetSizeAdjustmentMicroTiled(
UINT_32 thickness, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
UINT_32 baseAlign, UINT_32 pitchAlign,
UINT_32 *pPitch, UINT_32 *pHeight) const;
/// Pure virtual function to do extra sanity check
virtual BOOL_32 HwlSanityCheckMacroTiled(
ADDR_TILEINFO* pTileInfo) const = 0;
/// Pure virtual function to check current level to be the last macro tiled one
virtual VOID HwlCheckLastMacroTiledLvl(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
/// Adjusts bank before bank is modified by rotation
virtual UINT_32 HwlPreAdjustBank(
UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const = 0;
virtual VOID HwlComputeSurfaceCoord2DFromBankPipe(
AddrTileMode tileMode, UINT_32* pX, UINT_32* pY, UINT_32 slice,
UINT_32 bank, UINT_32 pipe,
UINT_32 bankSwizzle, UINT_32 pipeSwizzle, UINT_32 tileSlices,
BOOL_32 ignoreSE,
ADDR_TILEINFO* pTileInfo) const = 0;
virtual BOOL_32 HwlTileInfoEqual(
const ADDR_TILEINFO* pLeft, const ADDR_TILEINFO* pRight) const;
virtual AddrTileMode HwlDegradeThickTileMode(
AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const;
virtual INT_32 HwlPostCheckTileIndex(
const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
INT curIndex = TileIndexInvalid) const
{
return TileIndexInvalid;
}
virtual VOID HwlFmaskPreThunkSurfInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const
{
}
virtual VOID HwlFmaskPostThunkSurfInfo(
const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const
{
}
virtual UINT_32 HwlStereoCheckRightOffsetPadding(ADDR_TILEINFO* pTileInfo) const;
virtual BOOL_32 HwlReduceBankWidthHeight(
UINT_32 tileSize, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
UINT_32 bankHeightAlign, UINT_32 pipes,
ADDR_TILEINFO* pTileInfo) const;
// Protected non-virtual functions
/// Mip level functions
AddrTileMode ComputeSurfaceMipLevelTileMode(
AddrTileMode baseTileMode, UINT_32 bpp,
UINT_32 pitch, UINT_32 height, UINT_32 numSlices, UINT_32 numSamples,
UINT_32 pitchAlign, UINT_32 heightAlign,
ADDR_TILEINFO* pTileInfo) const;
/// Swizzle functions
VOID ExtractBankPipeSwizzle(
UINT_32 base256b, ADDR_TILEINFO* pTileInfo,
UINT_32* pBankSwizzle, UINT_32* pPipeSwizzle) const;
UINT_32 GetBankPipeSwizzle(
UINT_32 bankSwizzle, UINT_32 pipeSwizzle,
UINT_64 baseAddr, ADDR_TILEINFO* pTileInfo) const;
UINT_32 ComputeSliceTileSwizzle(
AddrTileMode tileMode, UINT_32 baseSwizzle, UINT_32 slice, UINT_64 baseAddr,
ADDR_TILEINFO* pTileInfo) const;
/// Addressing functions
virtual ADDR_E_RETURNCODE ComputeBankEquation(
UINT_32 log2BytesPP, UINT_32 threshX, UINT_32 threshY,
ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const
{
return ADDR_NOTSUPPORTED;
}
UINT_32 ComputeBankFromCoord(
UINT_32 x, UINT_32 y, UINT_32 slice,
AddrTileMode tileMode, UINT_32 bankSwizzle, UINT_32 tileSpitSlice,
ADDR_TILEINFO* pTileInfo) const;
UINT_32 ComputeBankFromAddr(
UINT_64 addr, UINT_32 numBanks, UINT_32 numPipes) const;
UINT_32 ComputePipeRotation(
AddrTileMode tileMode, UINT_32 numPipes) const;
UINT_32 ComputeBankRotation(
AddrTileMode tileMode, UINT_32 numBanks,
UINT_32 numPipes) const;
VOID ComputeSurfaceCoord2DFromBankPipe(
AddrTileMode tileMode, UINT_32 x, UINT_32 y, UINT_32 slice,
UINT_32 bank, UINT_32 pipe,
UINT_32 bankSwizzle, UINT_32 pipeSwizzle, UINT_32 tileSlices,
ADDR_TILEINFO* pTileInfo,
CoordFromBankPipe *pOutput) const;
/// Htile/Cmask functions
UINT_64 ComputeHtileBytes(
UINT_32 pitch, UINT_32 height, UINT_32 bpp,
BOOL_32 isLinear, UINT_32 numSlices, UINT_64* sliceBytes, UINT_32 baseAlign) const;
ADDR_E_RETURNCODE ComputeMacroTileEquation(
UINT_32 log2BytesPP, AddrTileMode tileMode, AddrTileType microTileType,
ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const;
// Static functions
static BOOL_32 IsTileInfoAllZero(const ADDR_TILEINFO* pTileInfo);
static UINT_32 ComputeFmaskNumPlanesFromNumSamples(UINT_32 numSamples);
static UINT_32 ComputeFmaskResolvedBppFromNumSamples(UINT_32 numSamples);
virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
{
}
private:
BOOL_32 ComputeSurfaceInfoLinear(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
UINT_32 padDims) const;
BOOL_32 ComputeSurfaceInfoMicroTiled(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
UINT_32 padDims,
AddrTileMode expTileMode) const;
BOOL_32 ComputeSurfaceInfoMacroTiled(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
UINT_32 padDims,
AddrTileMode expTileMode) const;
BOOL_32 ComputeSurfaceAlignmentsLinear(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
BOOL_32 ComputeSurfaceAlignmentsMicroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples,
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
BOOL_32 ComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
/// Surface addressing functions
UINT_64 DispatchComputeSurfaceAddrFromCoord(
const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
VOID DispatchComputeSurfaceCoordFromAddr(
const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
UINT_64 ComputeSurfaceAddrFromCoordMicroTiled(
UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode,
AddrTileType microTileType, BOOL_32 isDepthSampleOrder,
UINT_32* pBitPosition) const;
UINT_64 ComputeSurfaceAddrFromCoordMacroTiled(
UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode,
AddrTileType microTileType, BOOL_32 ignoreSE, BOOL_32 isDepthSampleOrder,
UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
ADDR_TILEINFO* pTileInfo,
UINT_32* pBitPosition) const;
VOID ComputeSurfaceCoordFromAddrMacroTiled(
UINT_64 addr, UINT_32 bitPosition,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
AddrTileType microTileType, BOOL_32 ignoreSE, BOOL_32 isDepthSampleOrder,
UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
ADDR_TILEINFO* pTileInfo,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample) const;
/// Fmask functions
UINT_64 DispatchComputeFmaskAddrFromCoord(
const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
VOID DispatchComputeFmaskCoordFromAddr(
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
// FMASK related methods - private
UINT_64 ComputeFmaskAddrFromCoordMicroTiled(
UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample, UINT_32 plane,
UINT_32 pitch, UINT_32 height, UINT_32 numSamples, AddrTileMode tileMode,
BOOL_32 resolved, UINT_32* pBitPosition) const;
VOID ComputeFmaskCoordFromAddrMicroTiled(
UINT_64 addr, UINT_32 bitPosition,
UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode, BOOL_32 resolved,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample, UINT_32* pPlane) const;
VOID ComputeFmaskCoordFromAddrMacroTiled(
UINT_64 addr, UINT_32 bitPosition,
UINT_32 pitch, UINT_32 height, UINT_32 numSamples, AddrTileMode tileMode,
UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
BOOL_32 ignoreSE,
ADDR_TILEINFO* pTileInfo,
BOOL_32 resolved,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample, UINT_32* pPlane) const;
UINT_64 ComputeFmaskAddrFromCoordMacroTiled(
UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample, UINT_32 plane,
UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode, UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
BOOL_32 ignoreSE,
ADDR_TILEINFO* pTileInfo,
BOOL_32 resolved,
UINT_32* pBitPosition) const;
/// Sanity check functions
BOOL_32 SanityCheckMacroTiled(
ADDR_TILEINFO* pTileInfo) const;
protected:
UINT_32 m_ranks; ///< Number of ranks - MC_ARB_RAMCFG.NOOFRANK
UINT_32 m_logicalBanks; ///< Logical banks = m_banks * m_ranks if m_banks != 16
UINT_32 m_bankInterleave; ///< Bank interleave, as a multiple of pipe interleave size
};
} // V1
} // Addr
#endif
src/amd/addrlib/src/r800/siaddrlib.cpp
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/*
************************************************************************************************************************
*
* Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
/**
****************************************************************************************************
* @file siaddrlib.h
* @brief Contains the R800Lib class definition.
****************************************************************************************************
*/
#ifndef __SI_ADDR_LIB_H__
#define __SI_ADDR_LIB_H__
#include "addrlib1.h"
#include "egbaddrlib.h"
namespace Addr
{
namespace V1
{
/**
****************************************************************************************************
* @brief Describes the information in tile mode table
****************************************************************************************************
*/
struct TileConfig
{
AddrTileMode mode;
AddrTileType type;
ADDR_TILEINFO info;
};
/**
****************************************************************************************************
* @brief SI specific settings structure.
****************************************************************************************************
*/
struct SiChipSettings
{
UINT_32 isSouthernIsland : 1;
UINT_32 isTahiti : 1;
UINT_32 isPitCairn : 1;
UINT_32 isCapeVerde : 1;
// Oland/Hainan are of GFXIP 6.0, similar with SI
UINT_32 isOland : 1;
UINT_32 isHainan : 1;
// CI
UINT_32 isSeaIsland : 1;
UINT_32 isBonaire : 1;
UINT_32 isKaveri : 1;
UINT_32 isSpectre : 1;
UINT_32 isSpooky : 1;
UINT_32 isKalindi : 1;
UINT_32 isHawaii : 1;
// VI
UINT_32 isVolcanicIslands : 1;
UINT_32 isIceland : 1;
UINT_32 isTonga : 1;
UINT_32 isFiji : 1;
UINT_32 isPolaris10 : 1;
UINT_32 isPolaris11 : 1;
UINT_32 isPolaris12 : 1;
UINT_32 isVegaM : 1;
UINT_32 isCarrizo : 1;
UINT_32 : 1;
};
/**
****************************************************************************************************
* @brief This class is the SI specific address library
* function set.
****************************************************************************************************
*/
class SiLib : public EgBasedLib
{
public:
/// Creates SiLib object
static Addr::Lib* CreateObj(const Client* pClient)
{
VOID* pMem = Object::ClientAlloc(sizeof(SiLib), pClient);
return (pMem != NULL) ? new (pMem) SiLib(pClient) : NULL;
}
protected:
SiLib(const Client* pClient);
virtual ~SiLib();
// Hwl interface - defined in AddrLib1
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW(
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const;
virtual UINT_64 HwlComputeXmaskAddrFromCoord(
UINT_32 pitch, UINT_32 height, UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 numSlices,
UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
ADDR_TILEINFO* pTileInfo, UINT_32* pBitPosition) const;
virtual VOID HwlComputeXmaskCoordFromAddr(
UINT_64 addr, UINT_32 bitPosition, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
virtual ADDR_E_RETURNCODE HwlGetTileIndex(
const ADDR_GET_TILEINDEX_INPUT* pIn,
ADDR_GET_TILEINDEX_OUTPUT* pOut) const;
virtual BOOL_32 HwlComputeMipLevel(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
virtual ChipFamily HwlConvertChipFamily(
UINT_32 uChipFamily, UINT_32 uChipRevision);
virtual BOOL_32 HwlInitGlobalParams(
const ADDR_CREATE_INPUT* pCreateIn);
virtual ADDR_E_RETURNCODE HwlSetupTileCfg(
UINT_32 bpp, INT_32 index, INT_32 macroModeIndex,
ADDR_TILEINFO* pInfo, AddrTileMode* pMode = 0, AddrTileType* pType = 0) const;
virtual VOID HwlComputeTileDataWidthAndHeightLinear(
UINT_32* pMacroWidth, UINT_32* pMacroHeight,
UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
virtual UINT_64 HwlComputeHtileBytes(
UINT_32 pitch, UINT_32 height, UINT_32 bpp,
BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const;
virtual ADDR_E_RETURNCODE ComputeBankEquation(
UINT_32 log2BytesPP, UINT_32 threshX, UINT_32 threshY,
ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const;
virtual ADDR_E_RETURNCODE ComputePipeEquation(
UINT_32 log2BytesPP, UINT_32 threshX, UINT_32 threshY,
ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const;
virtual UINT_32 ComputePipeFromCoord(
UINT_32 x, UINT_32 y, UINT_32 slice,
AddrTileMode tileMode, UINT_32 pipeSwizzle, BOOL_32 ignoreSE,
ADDR_TILEINFO* pTileInfo) const;
virtual UINT_32 HwlGetPipes(const ADDR_TILEINFO* pTileInfo) const;
/// Pre-handler of 3x pitch (96 bit) adjustment
virtual UINT_32 HwlPreHandleBaseLvl3xPitch(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
/// Post-handler of 3x pitch adjustment
virtual UINT_32 HwlPostHandleBaseLvl3xPitch(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
/// Dummy function to finalize the inheritance
virtual UINT_32 HwlComputeXmaskCoordYFrom8Pipe(
UINT_32 pipe, UINT_32 x) const;
// Sub-hwl interface - defined in EgBasedLib
virtual VOID HwlSetupTileInfo(
AddrTileMode tileMode, ADDR_SURFACE_FLAGS flags,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
AddrTileType inTileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual UINT_32 HwlGetPitchAlignmentMicroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples) const;
virtual UINT_64 HwlGetSizeAdjustmentMicroTiled(
UINT_32 thickness, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
UINT_32 baseAlign, UINT_32 pitchAlign,
UINT_32 *pPitch, UINT_32 *pHeight) const;
virtual VOID HwlCheckLastMacroTiledLvl(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual BOOL_32 HwlTileInfoEqual(
const ADDR_TILEINFO* pLeft, const ADDR_TILEINFO* pRight) const;
virtual AddrTileMode HwlDegradeThickTileMode(
AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const;
virtual VOID HwlOverrideTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual VOID HwlOptimizeTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual VOID HwlSelectTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
/// Overwrite tile setting to PRT
virtual VOID HwlSetPrtTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const;
virtual BOOL_32 HwlSanityCheckMacroTiled(
ADDR_TILEINFO* pTileInfo) const
{
return TRUE;
}
virtual UINT_32 HwlGetPitchAlignmentLinear(UINT_32 bpp, ADDR_SURFACE_FLAGS flags) const;
virtual UINT_64 HwlGetSizeAdjustmentLinear(
AddrTileMode tileMode,
UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
UINT_32 *pPitch, UINT_32 *pHeight, UINT_32 *pHeightAlign) const;
virtual VOID HwlComputeSurfaceCoord2DFromBankPipe(
AddrTileMode tileMode, UINT_32* pX, UINT_32* pY, UINT_32 slice,
UINT_32 bank, UINT_32 pipe,
UINT_32 bankSwizzle, UINT_32 pipeSwizzle, UINT_32 tileSlices,
BOOL_32 ignoreSE,
ADDR_TILEINFO* pTileInfo) const;
virtual UINT_32 HwlPreAdjustBank(
UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const;
virtual INT_32 HwlPostCheckTileIndex(
const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
INT curIndex = TileIndexInvalid) const;
virtual VOID HwlFmaskPreThunkSurfInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const;
virtual VOID HwlFmaskPostThunkSurfInfo(
const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const;
virtual UINT_32 HwlComputeFmaskBits(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
UINT_32* pNumSamples) const;
virtual BOOL_32 HwlReduceBankWidthHeight(
UINT_32 tileSize, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
UINT_32 bankHeightAlign, UINT_32 pipes,
ADDR_TILEINFO* pTileInfo) const
{
return TRUE;
}
virtual UINT_32 HwlComputeMaxBaseAlignments() const;
virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const;
virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
// Get equation table pointer and number of equations
virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
{
*ppEquationTable = m_equationTable;
return m_numEquations;
}
// Check if it is supported for given bpp and tile config to generate an equation
BOOL_32 IsEquationSupported(
UINT_32 bpp, TileConfig tileConfig, INT_32 tileIndex, UINT_32 elementBytesLog2) const;
// Protected non-virtual functions
VOID ComputeTileCoordFromPipeAndElemIdx(
UINT_32 elemIdx, UINT_32 pipe, AddrPipeCfg pipeCfg, UINT_32 pitchInMacroTile,
UINT_32 x, UINT_32 y, UINT_32* pX, UINT_32* pY) const;
UINT_32 TileCoordToMaskElementIndex(
UINT_32 tx, UINT_32 ty, AddrPipeCfg pipeConfig,
UINT_32 *macroShift, UINT_32 *elemIdxBits) const;
BOOL_32 DecodeGbRegs(
const ADDR_REGISTER_VALUE* pRegValue);
const TileConfig* GetTileSetting(
UINT_32 index) const;
// Initialize equation table
VOID InitEquationTable();
UINT_32 GetPipePerSurf(AddrPipeCfg pipeConfig) const;
static const UINT_32 TileTableSize = 32;
TileConfig m_tileTable[TileTableSize];
UINT_32 m_noOfEntries;
// Max number of bpp (8bpp/16bpp/32bpp/64bpp/128bpp)
static const UINT_32 MaxNumElementBytes = 5;
static const BOOL_32 m_EquationSupport[TileTableSize][MaxNumElementBytes];
// Prt tile mode index mask
static const UINT_32 SiPrtTileIndexMask = ((1 << 3) | (1 << 5) | (1 << 6) | (1 << 7) |
(1 << 21) | (1 << 22) | (1 << 23) | (1 << 24) |
(1 << 25) | (1 << 30));
// More than half slots in tile mode table can't support equation
static const UINT_32 EquationTableSize = (MaxNumElementBytes * TileTableSize) / 2;
// Equation table
ADDR_EQUATION m_equationTable[EquationTableSize];
UINT_32 m_numMacroBits[EquationTableSize];
UINT_32 m_blockWidth[EquationTableSize];
UINT_32 m_blockHeight[EquationTableSize];
UINT_32 m_blockSlices[EquationTableSize];
// Number of equation entries in the table
UINT_32 m_numEquations;
// Equation lookup table according to bpp and tile index
UINT_32 m_equationLookupTable[MaxNumElementBytes][TileTableSize];
UINT_32 m_uncompressDepthEqIndex;
SiChipSettings m_settings;
private:
VOID ReadGbTileMode(UINT_32 regValue, TileConfig* pCfg) const;
BOOL_32 InitTileSettingTable(const UINT_32 *pSetting, UINT_32 noOfEntries);
};
} // V1
} // Addr
#endif
src/amd/ci/.gitattributes
+1
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@@ -0,0 +1 @@
vkd3d-*.txt eol=crlf
src/amd/ci/amd-raven-fails.txt
+4
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@@ -0,0 +1,4 @@
# skqp failure:
# SRGBReadWritePixels FAILED (7 errors)
# ../../tests/SRGBReadWritePixelsTest.cpp:214 Could not create sRGB surface context. [OpenGL]
SRGBReadWritePixels,Fail
src/amd/ci/angle-radv-stoney-fails.txt
+953
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@@ -0,0 +1,953 @@
# Failing since ANGLE exposed geometry shaders in their commit a4c7abcbc1eb
# ("Advertise GL_OES_geometry_shader and GL_EXT_tessellation_shader"):
#
# "Rendered data at (28, 21) equal (0.0980392, 0.2, 0.298039, 0.4) exceeds allowed epsilon when compared to reference data equal (0.5, 0.6, 0.7, 0.8).
# Data comparison failed at esextcGeometryShaderRendering.cpp:5751"
#
# Also fails, reports no validation failures on my RX Vega.
KHR-GLES31.core.geometry_shader.rendering.rendering.triangles_with_adjacency_input_line_strip_output_triangle_strip_adjacency_drawcall,Fail
KHR-GLES31.core.geometry_shader.rendering.rendering.triangles_with_adjacency_input_triangle_strip_output_triangle_strip_adjacency_drawcall,Fail
# Failure in later miplevels, occasionally flaky
dEQP-GLES3.functional.texture.specification.teximage2d_depth.depth_component24,Fail
dEQP-GLES3.functional.texture.specification.teximage2d_depth.depth24_stencil8,Fail
dEQP-GLES3.functional.texture.specification.teximage2d_depth.depth32f_stencil8,Fail
dEQP-GLES3.functional.texture.specification.teximage3d_depth.depth_component24_2d_array,Fail
dEQP-GLES3.functional.texture.specification.teximage3d_depth.depth24_stencil8_2d_array,Fail
dEQP-GLES3.functional.texture.specification.teximage3d_depth.depth32f_stencil8_2d_array,Fail
dEQP-GLES3.functional.texture.specification.texstorage2d.format.depth_component24_2d,Fail
dEQP-GLES3.functional.texture.specification.texstorage2d.format.depth_component24_cube,Fail
dEQP-GLES3.functional.texture.specification.texstorage2d.format.depth24_stencil8_2d,Fail
dEQP-GLES3.functional.texture.specification.texstorage2d.format.depth24_stencil8_cube,Fail
dEQP-GLES3.functional.texture.specification.texstorage2d.format.depth32f_stencil8_2d,Fail
dEQP-GLES3.functional.texture.specification.texstorage2d.format.depth32f_stencil8_cube,Fail
dEQP-GLES3.functional.texture.specification.texstorage3d.format.depth_component24_2d_array,Fail
dEQP-GLES3.functional.texture.specification.texstorage3d.format.depth24_stencil8_2d_array,Fail
dEQP-GLES3.functional.texture.specification.texstorage3d.format.depth32f_stencil8_2d_array,Fail
dEQP-GLES3.functional.texture.specification.texsubimage2d_depth.depth_component24,Fail
dEQP-GLES3.functional.texture.specification.texsubimage2d_depth.depth24_stencil8,Fail
dEQP-GLES3.functional.texture.specification.texsubimage2d_depth.depth32f_stencil8,Fail
dEQP-GLES3.functional.texture.specification.texsubimage3d_depth.depth_component24_2d_array,Fail
dEQP-GLES3.functional.texture.specification.texsubimage3d_depth.depth24_stencil8_2d_array,Fail
dEQP-GLES3.functional.texture.specification.texsubimage3d_depth.depth32f_stencil8_2d_array,Fail
dEQP-GLES31.functional.texture.specification.texstorage3d.format.depth_component24_cube_array,Fail
dEQP-GLES31.functional.texture.specification.texsubimage3d_depth.depth24_stencil8_cube_array,Fail
dEQP-GLES31.functional.texture.specification.texsubimage3d_depth.depth32f_stencil8_cube_array,Fail
dEQP-GLES31.functional.texture.specification.texstorage3d.format.depth24_stencil8_cube_array,Fail
dEQP-GLES31.functional.texture.specification.texstorage3d.format.depth32f_stencil8_cube_array,Fail
# ASTC failures
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.rgba_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.rgba_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.rgba_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.rgba_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.rgba_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.rgba_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.rgba_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.rgba_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.rgba_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_rgba_astc_5x4_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_rgba_astc_5x4_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_rgba_astc_5x4_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_rgba_astc_5x4_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_rgba_astc_5x4_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_rgba_astc_5x4_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_rgba_astc_5x4_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_rgba_astc_5x4_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_rgba_astc_5x4_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.rgba_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.rgba_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.rgba_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.rgba_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.rgba_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.rgba_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.rgba_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.rgba_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.rgba_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_rgba_astc_5x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_rgba_astc_5x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_rgba_astc_5x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_rgba_astc_5x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_rgba_astc_5x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_rgba_astc_5x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_rgba_astc_5x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_rgba_astc_5x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_rgba_astc_5x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x5_rgba.srgb8_alpha8_astc_5x5_khr_srgb8_alpha8_astc_5x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.rgba_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.rgba_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.rgba_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.rgba_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.rgba_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.rgba_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.rgba_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.rgba_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.rgba_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_rgba_astc_6x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_rgba_astc_6x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_rgba_astc_6x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_rgba_astc_6x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_rgba_astc_6x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_rgba_astc_6x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_rgba_astc_6x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_rgba_astc_6x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_rgba_astc_6x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x5_rgba.srgb8_alpha8_astc_6x5_khr_srgb8_alpha8_astc_6x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.rgba_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.rgba_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.rgba_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.rgba_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.rgba_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.rgba_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.rgba_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.rgba_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.rgba_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_rgba_astc_6x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_rgba_astc_6x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_rgba_astc_6x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_rgba_astc_6x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_rgba_astc_6x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_rgba_astc_6x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_rgba_astc_6x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_rgba_astc_6x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_rgba_astc_6x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_6x6_rgba.srgb8_alpha8_astc_6x6_khr_srgb8_alpha8_astc_6x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.rgba_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.rgba_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.rgba_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.rgba_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.rgba_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.rgba_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.rgba_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.rgba_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.rgba_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_rgba_astc_8x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_rgba_astc_8x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_rgba_astc_8x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_rgba_astc_8x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_rgba_astc_8x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_rgba_astc_8x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_rgba_astc_8x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_rgba_astc_8x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_rgba_astc_8x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x5_rgba.srgb8_alpha8_astc_8x5_khr_srgb8_alpha8_astc_8x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.rgba_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.rgba_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.rgba_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.rgba_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.rgba_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.rgba_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.rgba_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.rgba_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.rgba_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_rgba_astc_8x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_rgba_astc_8x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_rgba_astc_8x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_rgba_astc_8x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_rgba_astc_8x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_rgba_astc_8x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_rgba_astc_8x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_rgba_astc_8x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_rgba_astc_8x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x6_rgba.srgb8_alpha8_astc_8x6_khr_srgb8_alpha8_astc_8x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.rgba_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.rgba_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.rgba_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.rgba_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.rgba_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.rgba_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.rgba_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.rgba_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.rgba_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_rgba_astc_8x8_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_rgba_astc_8x8_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_rgba_astc_8x8_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_rgba_astc_8x8_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_rgba_astc_8x8_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_rgba_astc_8x8_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_rgba_astc_8x8_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_rgba_astc_8x8_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_rgba_astc_8x8_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_8x8_rgba.srgb8_alpha8_astc_8x8_khr_srgb8_alpha8_astc_8x8_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x4_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_5x5_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x5_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_6x6_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x5_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x6_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_astc_8x8_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x4_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_5x5_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x6_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x5_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x6_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_8x8_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x4_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_5x5_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x5_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_6x6_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x5_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x6_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.renderbuffer_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.renderbuffer_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.renderbuffer_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.texture3d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.texture3d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_srgb8_alpha8_astc_8x8_khr.texture3d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32f.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32f.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32f.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32f.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32f.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32f.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32f.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32f.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32i.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32i.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32i.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32i.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32i.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32i.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32i.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32i.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32i.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32i.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32ui.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32ui.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32ui.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32ui.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32ui.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32ui.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32ui.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32ui.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32ui.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x4_khr_rgba32ui.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32f.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32i.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_5x5_khr_rgba32ui.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32f.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32f.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32f.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32f.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32f.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32f.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32f.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32f.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32f.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32f.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32i.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32f.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32f.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32f.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32f.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32f.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32f.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32i.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32i.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32i.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32i.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32i.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32i.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32i.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32ui.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32ui.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32ui.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32ui.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32ui.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32ui.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x6_khr_rgba32ui.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32f.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32i.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x4_khr_rgba32ui.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32f.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32i.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_5x5_khr_rgba32ui.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32f.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32i.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x5_khr_rgba32ui.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32f.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32ui.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32f.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32i.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x5_khr_rgba32ui.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32f.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32i.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x6_khr_rgba32ui.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32i.texture2d_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.cubemap_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.cubemap_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.cubemap_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.cubemap_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.cubemap_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.texture2d_array_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.texture2d_array_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.texture2d_array_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.texture2d_array_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.texture2d_array_to_texture3d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.texture2d_to_cubemap,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.texture2d_to_renderbuffer,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.texture2d_to_texture2d,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.texture2d_to_texture2d_array,Fail
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32ui.texture2d_to_texture3d,Fail
# Note that the set of test failures in this group changes based on the tests
# run before them in the caselist! We set them to what CI currently produces
# for the default fractional test run, and mark the rest as flakes.
multisample-dEQP-GLES31.functional.blend_equation_advanced.basic.multiply,Fail
multisample-dEQP-GLES31.functional.blend_equation_advanced.basic.overlay,Fail
multisample-dEQP-GLES31.functional.blend_equation_advanced.basic.screen,Fail
# New failure with ANGLE 2025-02-12
KHR-GLES3.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit,Crash
# New failures with ES CTS 3.2.12.0
KHR-GLES3.framebuffer_blit.multisampled_to_singlesampled_blit_depth_config_test,Crash
src/amd/ci/angle-radv-stoney-flakes.txt
+26
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@@ -0,0 +1,26 @@
# Vertex attrib array state reset failed: glGetError() returned GL_CONTEXT_LOST at gluStateReset.cpp:93
# Naming a few specific flakes seen here, but also including a general regex match.
dEQP-GLES3.functional.fbo.blit.default_framebuffer.rg32f_nearest_scale_blit_from_default
dEQP-GLES3.functional.fbo.blit.default_framebuffer.rgb565
dEQP-GLES3.functional.fbo.blit.default_framebuffer.rgba4_linear_out_of_bounds_blit_from_default
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_stencil_only
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_stencil_only
dEQP-GLES3.functional.fbo.*blit.*
dEQP-GLES3.functional.fbo.msaa.4_samples.*
# "ERROR: Verification against low precision requirements failed, failing test case."
dEQP-GLES3.functional.texture.shadow.2d.*depth24_stencil8
# Mostly fails, occasional pass
dEQP-GLES3.*functional.texture.specification.*depth.*
dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_stencil
dEQP-GLES31.functional.blend_equation_advanced.basic.multiply
KHR-GLES3.framebuffer_blit.multisampled_to_singlesampled_blit_depth_config_test
# MSAA dEQP-GLES31.functional.blend_equation_advanced exhibits different
# failures based on the caselist test order. This regex covers the different
# results for the full test run.
multisample-dEQP-GLES31.functional.blend_equation_advanced.*
src/amd/ci/deqp-amd-raven-skqp.toml
+3
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@@ -0,0 +1,3 @@
[[skqp]]
skqp = "/skqp/skqp"
skqp_assets = "/skqp/assets"
src/amd/ci/deqp-radeonsi-mendocino.toml
+69
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@@ -0,0 +1,69 @@
[[deqp]]
deqp = "/deqp-gles/modules/gles31/deqp-gles31"
caselists = [
"/deqp-gles/mustpass/gles31-main.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
[[deqp]]
deqp = "/deqp-gles/modules/gles3/deqp-gles3"
caselists = [
"/deqp-gles/mustpass/gles3-main.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
[[deqp]]
deqp = "/deqp-gles/modules/gles2/deqp-gles2"
caselists = [
"/deqp-gles/mustpass/gles2-main.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
[[deqp]]
deqp = "/deqp-gles/external/openglcts/modules/glcts"
caselists = [
# The GLES* tests don't include the tests for the previous versions.
"/deqp-gles/mustpass/gles2-khr-main.txt",
"/deqp-gles/mustpass/gles3-khr-main.txt",
"/deqp-gles/mustpass/gles31-khr-main.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
[[deqp]]
deqp = "/deqp-gl/external/openglcts/modules/glcts"
caselists = [
# The GL* tests include the tests for the previous versions.
"/deqp-gl/mustpass/gl46-main.txt",
"/deqp-gl/mustpass/gl46-khr-single.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
renderer_check = "mendocino"
[[piglit]]
piglit_folder = "/piglit"
profile = "gpu"
process_isolation = true
[piglit.env]
PIGLIT_NO_WINDOW = "1"
PIGLIT_PLATFORM = "gbm"
WAFFLE_PLATFORM = "gbm"
src/amd/ci/deqp-radeonsi-raven-cdna.toml
+9
View File
@@ -0,0 +1,9 @@
[[piglit]]
piglit_folder = "/piglit"
profile = "gpu"
process_isolation = true
[piglit.env]
PIGLIT_NO_WINDOW = "1"
PIGLIT_PLATFORM = "gbm"
WAFFLE_PLATFORM = "gbm"
AMD_IMAGE_OPCODES = "0"
src/amd/ci/deqp-radeonsi-raven.toml
+21
View File
@@ -0,0 +1,21 @@
[[piglit]]
piglit_folder = "/piglit"
profile = "quick_gl"
process_isolation = true
[piglit.env]
PIGLIT_PLATFORM = "mixed_glx_egl"
[[piglit]]
piglit_folder = "/piglit"
profile = "quick_shader"
fraction = 3
process_isolation = true
[piglit.env]
PIGLIT_PLATFORM = "mixed_glx_egl"
[[piglit]]
piglit_folder = "/piglit"
profile = "cl"
process_isolation = true
[piglit.env]
RUSTICL_ENABLE = "radeonsi"
src/amd/ci/deqp-radeonsi-stoney.toml
+22
View File
@@ -0,0 +1,22 @@
[[deqp]]
deqp = "/deqp-gles/external/openglcts/modules/glcts"
caselists = [
"/deqp-gles/mustpass/gles2-main.txt",
"/deqp-gles/mustpass/gles3-main.txt",
"/deqp-gles/mustpass/gles31-main.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
version_check = "GL ES 3.2.*git"
renderer_check = "stoney"
[[piglit]]
piglit_folder = "/piglit"
profile = "gpu"
process_isolation = true
timeout = 180.0
[piglit.env]
PIGLIT_NO_WINDOW = "1"
src/amd/ci/deqp-radeonsi-vangogh.toml
+69
View File
@@ -0,0 +1,69 @@
[[deqp]]
deqp = "/deqp-gles/modules/gles31/deqp-gles31"
caselists = [
"/deqp-gles/mustpass/gles31-main.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
[[deqp]]
deqp = "/deqp-gles/modules/gles3/deqp-gles3"
caselists = [
"/deqp-gles/mustpass/gles3-main.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
[[deqp]]
deqp = "/deqp-gles/modules/gles2/deqp-gles2"
caselists = [
"/deqp-gles/mustpass/gles2-main.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
[[deqp]]
deqp = "/deqp-gles/external/openglcts/modules/glcts"
caselists = [
# The GLES* tests don't include the tests for the previous versions.
"/deqp-gles/mustpass/gles2-khr-main.txt",
"/deqp-gles/mustpass/gles3-khr-main.txt",
"/deqp-gles/mustpass/gles31-khr-main.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
[[deqp]]
deqp = "/deqp-gl/external/openglcts/modules/glcts"
caselists = [
# The GL* tests include the tests for the previous versions.
"/deqp-gl/mustpass/gl46-main.txt",
"/deqp-gl/mustpass/gl46-khr-single.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
renderer_check = "vangogh"
[[piglit]]
piglit_folder = "/piglit"
profile = "gpu"
process_isolation = true
[piglit.env]
PIGLIT_NO_WINDOW = "1"
PIGLIT_PLATFORM = "gbm"
WAFFLE_PLATFORM = "gbm"
src/amd/ci/deqp-radv-fluster.toml
+8
View File
@@ -0,0 +1,8 @@
[[fluster]]
bin = "/fluster/fluster.py"
decoders = [
# "GStreamer-AV1-Vulkan-Gst1.0", # uncomment when updating to gstreamer >= 1.28
# "GStreamer-VP9-Vulkan-Gst1.0", # uncomment when updating to gstreamer >= 1.28
"GStreamer-H.264-Vulkan-Gst1.0",
"GStreamer-H.265-Vulkan-Gst1.0",
]
src/amd/ci/deqp-radv-nightly.toml
+6
View File
@@ -0,0 +1,6 @@
[[deqp]]
deqp = "/deqp-vk-main/external/vulkancts/modules/vulkan/deqp-vk"
caselists = ["/deqp-vk-main/mustpass/vk-main.txt"]
timeout = 120
tests_per_group = 5000
renderer_check = "RADV"
src/amd/ci/deqp-radv-stoney-angle-full.toml
+68
View File
@@ -0,0 +1,68 @@
# Basic test set
[[deqp]]
deqp = "/deqp-gles/modules/gles2/deqp-gles2"
caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
version_check = "GL ES 3.2"
renderer_check = "ANGLE.*RADV"
[[deqp]]
deqp = "/deqp-gles/modules/gles3/deqp-gles3"
caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
[[deqp]]
deqp = "/deqp-gles/modules/gles31/deqp-gles31"
caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
# Note that KHR-GL3* test sets include all tests from the previous
# version, so we only need to run one test list (unlike dEQP-GLES,
# where the test sets are separate).
[[deqp]]
deqp = "/deqp-gles/external/openglcts/modules/glcts"
caselists = [
"/deqp-gles/mustpass/gles2-khr-main.txt",
"/deqp-gles/mustpass/gles3-khr-main.txt",
"/deqp-gles/mustpass/gles31-khr-main.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
# 565-no-depth-no-stencil: Not supported with angle on X11?
# multisample
[[deqp]]
deqp = "/deqp-gles/modules/gles3/deqp-gles3"
caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms4",
]
prefix = "multisample-"
[[deqp]]
deqp = "/deqp-gles/modules/gles31/deqp-gles31"
caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms4",
]
prefix = "multisample-"
src/amd/ci/deqp-radv-stoney-angle.toml
+71
View File
@@ -0,0 +1,71 @@
# Basic test set
[[deqp]]
deqp = "/deqp-gles/modules/gles2/deqp-gles2"
caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
fraction = 4
version_check = "GL ES 3.2"
renderer_check = "ANGLE.*RADV"
[[deqp]]
deqp = "/deqp-gles/modules/gles3/deqp-gles3"
caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
fraction = 12
[[deqp]]
deqp = "/deqp-gles/modules/gles31/deqp-gles31"
caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
fraction = 12
# Note that KHR-GL3* test sets include all tests from the previous
# version, so we only need to run one test list (unlike dEQP-GLES,
# where the test sets are separate).
[[deqp]]
deqp = "/deqp-gles/external/openglcts/modules/glcts"
caselists = [
"/deqp-gles/mustpass/gles2-khr-main.txt",
"/deqp-gles/mustpass/gles3-khr-main.txt",
"/deqp-gles/mustpass/gles31-khr-main.txt",
]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms0",
]
# 565-no-depth-no-stencil: Not supported with angle on X11?
# multisample
[[deqp]]
deqp = "/deqp-gles/modules/gles3/deqp-gles3"
caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms4",
]
prefix = "multisample-"
[[deqp]]
deqp = "/deqp-gles/modules/gles31/deqp-gles31"
caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
deqp_args = [
"--deqp-surface-width=256", "--deqp-surface-height=256",
"--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
"--deqp-gl-config-name=rgba8888d24s8ms4",
]
prefix = "multisample-"
src/amd/ci/deqp-radv.toml
+7
View File
@@ -0,0 +1,7 @@
# Basic test set
[[deqp]]
deqp = "/deqp-vk-main/external/vulkancts/modules/vulkan/deqp-vk"
caselists = ["/deqp-vk-main/mustpass/vk-main.txt"]
skips = ["./install/radv-slow-skips.txt"]
tests_per_group = 5000
renderer_check = "RADV"
src/amd/ci/deqp-vaapi.toml
+10
View File
@@ -0,0 +1,10 @@
[[gtest]]
bin = "/va/bin/test_va_api"
[[fluster]]
bin = "/fluster/fluster.py"
decoders = [
"GStreamer-VP9-VAAPI-Gst1.0",
"GStreamer-H.264-VAAPI-Gst1.0",
"GStreamer-H.265-VAAPI-Gst1.0",
]
src/amd/ci/external/radv-bonaire-fails.txt
Vendored
View File
Whitespace-only changes.
src/amd/ci/external/radv-bonaire-skips.txt
Vendored
View File
Whitespace-only changes.
src/amd/ci/external/radv-fiji-fails.txt
Vendored
+18
View File
@@ -0,0 +1,18 @@
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint.stencil_max,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint.stencil_min,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint.stencil_zero,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint_separate_layouts.stencil_max,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint_separate_layouts.stencil_min,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint_separate_layouts.stencil_zero,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint.stencil_max,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint.stencil_min,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint.stencil_zero,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint_separate_layouts.stencil_max,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint_separate_layouts.stencil_min,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_4.d32_sfloat_s8_uint_separate_layouts.stencil_zero,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint.stencil_max,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint.stencil_min,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint.stencil_zero,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint_separate_layouts.stencil_max,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint_separate_layouts.stencil_min,Fail
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_8.d32_sfloat_s8_uint_separate_layouts.stencil_zero,Fail
src/amd/ci/external/radv-kabini-fails.txt
Vendored
+14
View File
@@ -0,0 +1,14 @@
dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.layer_copy_before_resolving.2_bit,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.layer_copy_before_resolving.4_bit,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.layer_copy_before_resolving.8_bit,Fail
dEQP-VK.api.copy_and_blit.core.resolve_image.layer_copy_before_resolving.2_bit,Fail
dEQP-VK.api.copy_and_blit.core.resolve_image.layer_copy_before_resolving.4_bit,Fail
dEQP-VK.api.copy_and_blit.core.resolve_image.layer_copy_before_resolving.8_bit,Fail
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.layer_copy_before_resolving.2_bit,Fail
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.layer_copy_before_resolving.4_bit,Fail
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.layer_copy_before_resolving.8_bit,Fail
dEQP-VK.pipeline.monolithic.timestamp.calibrated.calibration_test,Fail
dEQP-VK.image.sample_texture.128_bit_compressed_format_two_samplers,Fail
dEQP-VK.image.sample_texture.128_bit_compressed_format_two_samplers_cubemap,Fail
dEQP-VK.image.sample_texture.64_bit_compressed_format_two_samplers,Fail
dEQP-VK.image.sample_texture.64_bit_compressed_format_two_samplers_cubemap,Fail
src/amd/ci/external/radv-kabini-flakes.txt
Vendored
+2
View File
@@ -0,0 +1,2 @@
dEQP-VK.reconvergence.subgroup_uniform_control_flow_elect.compute.nesting4.2.35
dEQP-VK.reconvergence.workgroup_uniform_control_flow_elect.compute.nesting4.2.35
src/amd/ci/external/radv-kabini-skips.txt
Vendored
+2
View File
@@ -0,0 +1,2 @@
# Timeouts
dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail
src/amd/ci/external/radv-navi14-fails.txt
Vendored
View File
Whitespace-only changes.
src/amd/ci/external/radv-navi22-fails.txt
Vendored
View File
Whitespace-only changes.
src/amd/ci/external/radv-navi22-flakes.txt
Vendored
View File
Whitespace-only changes.
src/amd/ci/external/radv-pitcairn-fails.txt
Vendored
View File
Whitespace-only changes.
src/amd/ci/gitlab-ci-inc.yml
+507
View File
@@ -0,0 +1,507 @@
.radeonsi-collabora-rules:
stage: amd
rules:
- !reference [.test, rules]
- !reference [.collabora-farm-rules, rules]
- !reference [.gl-rules, rules]
- changes: &amd_common_file_list
- src/amd/*
- src/amd/addrlib/**/*
- src/amd/ci/gitlab-ci.yml
- src/amd/ci/gitlab-ci-inc.yml
- src/amd/ci/deqp-$DEQP_SUITE.toml
- src/amd/ci/$GPU_VERSION-fails.txt
- src/amd/ci/$GPU_VERSION-flakes.txt
- src/amd/ci/$GPU_VERSION-skips.txt
- src/amd/ci/$GPU_VERSION-slow-skips.txt
- src/amd/ci/$VK_DRIVER-skips.txt
- src/amd/ci/$GALLIUM_DRIVER-skips.txt
- src/amd/ci/$DRIVER_NAME-skips.txt
- src/amd/ci/$PIGLIT_TRACES_FILE
- src/amd/ci/$REPLAY_CONFIG
- src/amd/ci/$GPU_VERSION-vkd3d-fails.txt
- src/amd/ci/$GPU_VERSION-vkd3d-flakes.txt
- src/amd/ci/$GPU_VERSION-vkd3d-skips.txt
- src/amd/common/**/*
- src/amd/common/nir/**/*
- src/amd/compiler/**/*
- src/amd/llvm/**/*
- src/amd/registers/**/*
when: on_success
- changes: &radeonsi_file_list
- src/gallium/drivers/radeonsi/**/*
- src/gallium/include/winsys/**/*
- src/gallium/winsys/amdgpu/**/*
- src/amd/vpelib/**/*
when: on_success
.radeonsi-collabora-manual-rules:
stage: amd-nightly
extends: .no-auto-retry
rules:
- !reference [.test, rules]
- !reference [.collabora-farm-manual-rules, rules]
- !reference [.gl-manual-rules, rules]
- changes:
*amd_common_file_list
when: manual
- changes:
*radeonsi_file_list
when: manual
.radv-rules:
stage: amd
rules:
- !reference [.test, rules]
- !reference [.vulkan-rules, rules]
- changes:
*amd_common_file_list
when: on_success
- changes: &radv_file_list
- src/amd/compiler/**/*
- src/amd/vulkan/**/*
- src/vulkan/**/*
when: on_success
.radv-manual-rules:
stage: amd-nightly
rules:
- !reference [.test, rules]
- !reference [.vulkan-manual-rules, rules]
- changes:
*amd_common_file_list
when: manual
- changes:
*radv_file_list
when: manual
.radv-collabora-rules:
stage: amd
rules:
- !reference [.test, rules]
- !reference [.collabora-farm-rules, rules]
- !reference [.radv-rules, rules]
.radv-collabora-restricted-rules:
stage: amd
rules:
- !reference [.test, rules]
- !reference [.restricted-rules, rules]
- !reference [.radv-collabora-rules, rules]
.radv-collabora-manual-rules:
stage: amd-nightly
extends: .no-auto-retry
rules:
- !reference [.test, rules]
- !reference [.collabora-farm-manual-rules, rules]
- !reference [.radv-manual-rules, rules]
.radv-valve-rules:
stage: amd
rules:
- !reference [.test, rules]
- !reference [.valve-farm-rules, rules]
- !reference [.radv-rules, rules]
.radv-valve-manual-rules:
stage: amd-nightly
extends: .no-auto-retry
rules:
- !reference [.test, rules]
- !reference [.valve-farm-manual-rules, rules]
- !reference [.radv-manual-rules, rules]
.radeonsi+radv-rules:
stage: amd
rules:
- !reference [.test, rules]
- !reference [.radeonsi-collabora-rules, rules]
- !reference [.radv-rules, rules]
.radeonsi-vaapi-rules:
stage: amd
rules:
- !reference [.test, rules]
- !reference [.radeonsi-collabora-rules, rules]
- changes: &radeon_vcn_file_list
- src/gallium/frontends/va/**/*
- src/gallium/targets/va/**/*
when: on_success
.radeonsi-vaapi-manual-rules:
stage: amd-nightly
rules:
- !reference [.test, rules]
- !reference [.collabora-farm-manual-rules, rules]
- !reference [.gl-manual-rules, rules]
- changes:
*radeon_vcn_file_list
when: manual
.radeonsi-valve-rules:
stage: amd
rules:
- !reference [.test, rules]
- !reference [.valve-farm-rules, rules]
- !reference [.radeonsi-collabora-rules, rules]
.radeonsi-valve-manual-rules:
stage: amd-nightly
extends: .no-auto-retry
rules:
- !reference [.test, rules]
- !reference [.valve-farm-manual-rules, rules]
- !reference [.gl-manual-rules, rules]
- changes:
*amd_common_file_list
when: manual
- changes:
*radeonsi_file_list
when: manual
# Status: https://lava.collabora.dev/scheduler/device_type/acer-R721T-grunt
.lava-acer-R721T-grunt:x86_64:
variables:
BOOT_METHOD: depthcharge
DEVICE_TYPE: acer-R721T-grunt
DTB: ""
FARM: collabora
FDO_CI_CONCURRENT: 3
HWCI_FREQ_MAX: "true"
HWCI_KERNEL_MODULES: amdgpu
KERNEL_IMAGE_TYPE: ""
RUNNER_TAG: mesa-ci-x86-64-lava-acer-R721T-grunt
VK_DRIVER: radeon
# Status: https://lava.collabora.dev/scheduler/device_type/hp-14-db0003na-grunt
.lava-hp-14-db0003na-grunt:x86_64:
variables:
BOOT_METHOD: depthcharge
DEVICE_TYPE: hp-14-db0003na-grunt
DTB: ""
FARM: collabora
FDO_CI_CONCURRENT: 3
HWCI_FREQ_MAX: "true"
HWCI_KERNEL_MODULES: amdgpu
KERNEL_IMAGE_TYPE: ""
RUNNER_TAG: mesa-ci-x86-64-lava-hp-14-db0003na-grunt
VK_DRIVER: radeon
# Status: https://lava.collabora.dev/scheduler/device_type/asus-CM1400CXA-dalboz
.lava-asus-CM1400CXA-dalboz:x86_64:
variables:
BOOT_METHOD: depthcharge
DEVICE_TYPE: asus-CM1400CXA-dalboz
DTB: ""
FARM: collabora
# FDO_CI_CONCURRENT: ?
HWCI_FREQ_MAX: "true"
HWCI_KERNEL_MODULES: amdgpu
KERNEL_IMAGE_TYPE: ""
RUNNER_TAG: mesa-ci-x86-64-lava-asus-CM1400CXA-dalboz
# Force fixed 6.6 kernel, amdgpu doesn't revcover from GPU resets on 6.13
# https://gitlab.freedesktop.org/drm/amd/-/issues/3861
# https://gitlab.freedesktop.org/mesa/mesa/-/issues/12676
KERNEL_TAG: "v6.6.21-mesa-1978"
# Status: https://lava.collabora.dev/scheduler/device_type/lenovo-TPad-C13-Yoga-zork
.lava-lenovo-TPad-C13-Yoga-zork:x86_64:
variables:
BOOT_METHOD: depthcharge
DEVICE_TYPE: lenovo-TPad-C13-Yoga-zork
DTB: ""
FARM: collabora
# FDO_CI_CONCURRENT: ?
HWCI_FREQ_MAX: "true"
HWCI_KERNEL_MODULES: amdgpu
KERNEL_IMAGE_TYPE: ""
RUNNER_TAG: mesa-ci-x86-64-lava-lenovo-TPad-C13-Yoga-zork
# Force fixed 6.6 kernel, amdgpu doesn't revcover from GPU resets on 6.13
# https://gitlab.freedesktop.org/drm/amd/-/issues/3861
# https://gitlab.freedesktop.org/mesa/mesa/-/issues/12676
KERNEL_TAG: "v6.6.21-mesa-1978"
# Status: https://lava.collabora.dev/scheduler/device_type/hp-x360-14a-cb0001xx-zork
.lava-hp-x360-14a-cb0001xx-zork:x86_64:
variables:
BOOT_METHOD: depthcharge
DEVICE_TYPE: hp-x360-14a-cb0001xx-zork
DTB: ""
FARM: collabora
FDO_CI_CONCURRENT: 4
HWCI_FREQ_MAX: "true"
HWCI_KERNEL_MODULES: amdgpu
KERNEL_IMAGE_TYPE: ""
RUNNER_TAG: mesa-ci-x86-64-lava-hp-x360-14a-cb0001xx-zork
# Force fixed 6.6 kernel, amdgpu doesn't revcover from GPU resets on 6.13
# https://gitlab.freedesktop.org/drm/amd/-/issues/3861
# https://gitlab.freedesktop.org/mesa/mesa/-/issues/12676
KERNEL_TAG: "v6.6.21-mesa-1978"
# Status: https://lava.collabora.dev/scheduler/device_type/dell-latitude-3445-7520c-skyrim
.lava-dell-latitude-3445-7520c-skyrim:x86_64:
variables:
BOOT_METHOD: depthcharge
DEVICE_TYPE: dell-latitude-3445-7520c-skyrim
DTB: ""
FARM: collabora
FDO_CI_CONCURRENT: 8
HWCI_FREQ_MAX: "true"
HWCI_KERNEL_MODULES: amdgpu
KERNEL_IMAGE_TYPE: ""
RUNNER_TAG: mesa-ci-x86-64-lava-dell-latitude-3445-7520c-skyrim
VK_DRIVER: radeon
LAVA_FIRMWARE: amdgpu
# Status: https://lava.collabora.dev/scheduler/device_type/acer-cp514-3wh-r0qs-guybrush
.lava-acer-cp514-3wh-r0qs-guybrush:x86_64:
variables:
BOOT_METHOD: depthcharge
DEVICE_TYPE: acer-cp514-3wh-r0qs-guybrush
DTB: ""
FARM: collabora
FDO_CI_CONCURRENT: 4
HWCI_FREQ_MAX: "true"
HWCI_KERNEL_MODULES: amdgpu
KERNEL_IMAGE_TYPE: ""
RUNNER_TAG: mesa-ci-x86-64-lava-acer-cp514-3wh-r0qs-guybrush
VK_DRIVER: radeon
LAVA_FIRMWARE: amdgpu
# Force fixed 6.6 kernel
KERNEL_TAG: "v6.6.21-mesa-1978"
############### LAVA
# job prefixes: radeonsi (OpenGL), radv (Vulkan), amd (radeonsi+radv)
.stoney-test:x86_64:
variables:
FLAKES_CHANNEL: "#amd-ci"
LAVA_FIRMWARE: amdgpu-lava
.radeonsi-stoney-test:x86_64:
extends:
- .stoney-test:x86_64
- .lava-acer-R721T-grunt:x86_64
- .radeonsi-collabora-rules
variables:
GPU_VERSION: radeonsi-stoney
DRIVER_NAME: radeonsi
PIGLIT_PLATFORM: mixed_glx_egl
.radv-stoney-test:x86_64:
extends:
- .stoney-test:x86_64
- .lava-hp-14-db0003na-grunt:x86_64
- .radv-collabora-rules
variables:
DRIVER_NAME: radv
GPU_VERSION: radv-stoney
.radeonsi-raven-test:x86_64:
extends:
- .radeonsi-collabora-rules
variables:
GPU_VERSION: radeonsi-raven
DRIVER_NAME: radeonsi
LAVA_FIRMWARE: amdgpu-lava
.radv-raven-test:x86_64:
extends:
- .radv-collabora-rules
variables:
DRIVER_NAME: radv
GPU_VERSION: radv-raven
VK_DRIVER: radeon
LAVA_FIRMWARE: amdgpu-lava
.amd-raven-test:x86_64:
extends:
- .radeonsi+radv-rules
variables:
DRIVER_NAME: radeonsi
GPU_VERSION: amd-raven
VK_DRIVER: radeon
LAVA_FIRMWARE: amdgpu-lava
.radv-cezanne-test:x86_64:
extends:
- .lava-acer-cp514-3wh-r0qs-guybrush:x86_64
variables:
DRIVER_NAME: radv
GPU_VERSION: radv-cezanne
############### CI-tron
.ci-tron-test-amdgpu:
variables:
CI_TRON_PATTERN__JOB_WARN__REGEX: 'ring .* timeout'
CI_TRON_KERNEL__URL: "https://fs.mupuf.org/radv/linux-6.17.3_w_buddy_fixes/linux-x86_64"
CI_TRON_INITRAMFS__DEPMOD__URL: "https://fs.mupuf.org/radv/linux-6.17.3_w_buddy_fixes/linux-x86_64.depmod.cpio.xz"
CI_TRON_INITRAMFS__GPU__URL: "https://fs.mupuf.org/radv/linux-6.17.3_w_buddy_fixes/linux-x86_64.gpu_amdgpu.cpio"
CI_TRON_INITRAMFS__GPU__FORMAT__0__ARCHIVE__KEEP__0__PATH: "(lib/(modules|firmware/amdgpu)/.*)"
CI_TRON_KERNEL_CMDLINE__LOAD_MODULES: 'modules_load=amdgpu'
tags:
- farm:$RUNNER_FARM_LOCATION
- $CI_TRON_DUT_SETUP_TAGS
- amdgpu:$INTEGRATED_OR_DISCRETE
- ci-tron:priority:$CI_TRON_JOB_PRIORITY
.ci-tron-test-radv:
extends: .ci-tron-test-amdgpu
variables:
VK_DRIVER: radeon
DRIVER_NAME: radv
# The SPIRV -> NIR code generator generates so many harmless
# warnings on the shaders in VK-CTS that jobs fail due to the log
# size getting too big. Since it's not feasible right now
# to fix these shaders in the CTS, instead, ignore warnings from
# the code generator.
ACO_DEBUG: validateir,validatera
MESA_VK_IGNORE_CONFORMANCE_WARNING: 1
radv_cooperative_matrix2_nv: 'true'
# Enable ETC2 emulation on non-native platforms (RENOIR,RDNA+, GFX6-8 dGPUs)
vk_require_etc2: 'true'
CI_TRON__B2C_SWAP_SIZE: '16g'
.ci-tron-test-radv-vk:
extends:
- .ci-tron-x86_64-test-vk
- .radv-valve-rules
- .ci-tron-test-radv
variables:
DEQP_SUITE: radv
.ci-tron-test-radv-vk-nightly:
extends:
- .ci-tron-x86_64-test-vk
- .radv-valve-rules
- .ci-tron-test-radv
variables:
DEQP_SUITE: radv-nightly
.tahiti-test-valve:
variables:
FDO_CI_CONCURRENT: 24
RUNNER_FARM_LOCATION: mupuf
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:TAHITI
INTEGRATED_OR_DISCRETE: discrete
CI_TRON_KERNEL_CMDLINE__AMDGPU_FORCE_SI_SUPPORT: amdgpu.si_support=1
GPU_VERSION: radv-tahiti
.hawaii-test-valve:
variables:
FDO_CI_CONCURRENT: 24
RUNNER_FARM_LOCATION: mupuf
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:HAWAII
INTEGRATED_OR_DISCRETE: discrete
CI_TRON_KERNEL_CMDLINE__AMDGPU_FORCE_CIK_SUPPORT: amdgpu.cik_support=1
GPU_VERSION: radv-hawaii
.kabini-test-valve:
variables:
RUNNER_FARM_LOCATION: mupuf
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:KABINI
INTEGRATED_OR_DISCRETE: integrated
GPU_VERSION: radv-kabini
.polaris10-test-valve:
variables:
FDO_CI_CONCURRENT: 16
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:POLARIS10
INTEGRATED_OR_DISCRETE: discrete
# (2022-01) tsc=unstable was added in response to this message in kmsg,
# TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'.
CI_TRON_KERNEL_CMDLINE__TSC_WORKAROUND: 'tsc=unstable'
GPU_VERSION: radv-polaris10
.polaris10-test-valve-mupuf:
extends: .polaris10-test-valve
variables:
RUNNER_FARM_LOCATION: mupuf
.polaris10-test-valve-kws:
extends: .polaris10-test-valve
variables:
RUNNER_FARM_LOCATION: keywords
.vega10-test-valve:
variables:
RUNNER_FARM_LOCATION: keywords
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:VEGA10
INTEGRATED_OR_DISCRETE: discrete
GPU_VERSION: radv-vega10
FDO_CI_CONCURRENT: 16
.renoir-test-valve:
variables:
RUNNER_FARM_LOCATION: mupuf
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:RENOIR
INTEGRATED_OR_DISCRETE: integrated
GPU_VERSION: radv-renoir
FDO_CI_CONCURRENT: 16
.navi10-test-valve:
variables:
# (2022-01) noapic is set because the serial adapter on this
# machine is using non-MSI IRQs and is generating a lot of
# IRQs. This tends to confuse the interrupt controller and breaks
# MSI IRQs leading to GPU hangs on amdgpu.
CI_TRON_KERNEL_CMDLINE__APIC_WORKAROUND: 'noapic'
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:NAVI10
INTEGRATED_OR_DISCRETE: discrete
GPU_VERSION: radv-navi10
.navi10-test-valve-mupuf:
extends:
- .navi10-test-valve
variables:
RUNNER_FARM_LOCATION: mupuf
FDO_CI_CONCURRENT: 24
.navi10-test-valve-kws:
extends:
- .navi10-test-valve
variables:
RUNNER_FARM_LOCATION: keywords
FDO_CI_CONCURRENT: 16
.navi21-test-valve:
variables:
RUNNER_FARM_LOCATION: keywords
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:NAVI21
INTEGRATED_OR_DISCRETE: discrete
GPU_VERSION: radv-navi21
FDO_CI_CONCURRENT: 32
.vangogh-test-valve:
variables:
RUNNER_FARM_LOCATION: mupuf
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:VANGOGH
INTEGRATED_OR_DISCRETE: integrated
GPU_VERSION: radv-vangogh
FDO_CI_CONCURRENT: 8
.raphael-test-valve:
variables:
RUNNER_FARM_LOCATION: keywords
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:RAPHAEL
INTEGRATED_OR_DISCRETE: integrated
GPU_VERSION: radv-raphael
FDO_CI_CONCURRENT: 32
.navi31-test-valve:
variables:
RUNNER_FARM_LOCATION: keywords
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:NAVI31
INTEGRATED_OR_DISCRETE: discrete
GPU_VERSION: radv-navi31
FDO_CI_CONCURRENT: 32
.gfx1201-test-valve:
variables:
RUNNER_FARM_LOCATION: keywords
CI_TRON_DUT_SETUP_TAGS: amdgpu:codename:NAVI48
INTEGRATED_OR_DISCRETE: discrete
GPU_VERSION: radv-gfx1201
FDO_CI_CONCURRENT: 32
src/amd/ci/gitlab-ci.yml
+549
View File
@@ -0,0 +1,549 @@
include:
- local: 'src/amd/ci/gitlab-ci-inc.yml'
# Run five jobs in parallel each running 1/55th of the test suite
radv-stoney-vkcts:
extends:
- .lava-x86_64-test-vk
- .radv-stoney-test:x86_64
parallel: 5
variables:
DEQP_SUITE: radv
DEQP_FRACTION: 18
radv-stoney-angle:
extends:
- .lava-x86_64-test-gl
- .radv-stoney-test:x86_64
- .test-angle
variables:
DEQP_SUITE: radv-stoney-angle
GPU_VERSION: angle-radv-stoney
DEQP_FRACTION: 3
vk_require_astc: 'true'
radv-stoney-angle-full:
extends:
- radv-stoney-angle
- .radv-collabora-manual-rules
parallel: 2
variables:
DEQP_SUITE: radv-stoney-angle-full
DEQP_FRACTION: 1
radeonsi-stoney-glcts-piglit:
extends:
- .lava-x86_64-test-gl
- .radeonsi-stoney-test:x86_64
- .test-piglit
parallel: 11
variables:
DEQP_SUITE: radeonsi-stoney
HWCI_START_WESTON: 1
radeonsi-stoney-traces:
extends:
- .lava-x86_64-piglit-traces
- .radeonsi-stoney-test:x86_64
variables:
EGL_PLATFORM: surfaceless
PIGLIT_TRACES_FILE: traces-amd.yml
PIGLIT_REPLAY_EXTRA_ARGS: --keep-image
radv-raven-vkcts:
extends:
- .lava-x86_64-test-vk
- .radv-raven-test:x86_64
- .lava-asus-CM1400CXA-dalboz:x86_64
parallel: 9
variables:
DEQP_SUITE: radv
DEQP_FRACTION: 6
amd-raven-skqp:
extends:
- .lava-x86_64-test-gl
- .amd-raven-test:x86_64
- .lava-hp-x360-14a-cb0001xx-zork:x86_64
variables:
HWCI_START_WESTON: 1
DEQP_SUITE: amd-raven-skqp
parallel: 2
# Disabled as it was using an older version of Wine, with most of the traces
# being disabled due to being flaky.
.radv-raven-traces:
extends:
- .lava-x86_64-piglit-traces
- .radv-raven-test:x86_64
- .lava-asus-CM1400CXA-dalboz:x86_64
variables:
HWCI_START_XORG: 1
PIGLIT_PLATFORM: mixed_glx_egl # TODO, take wine/VK in account
PIGLIT_REPLAY_DEVICE_NAME: "vk-${GPU_VERSION}"
PIGLIT_TRACES_FILE: traces-amd.yml
radv-raven-traces-restricted:
extends:
- .lava-x86_64-test-vk
- .traces-test
- .test-wine
- .radv-raven-test:x86_64
- .lava-lenovo-TPad-C13-Yoga-zork:x86_64
- .radv-collabora-restricted-rules
variables:
HWCI_START_WESTON: 1
ANGLE_TRACE_FILES_TAG: "2025-03-28"
REPLAY_CONFIG: traces-amd-restricted.toml
FDO_CI_CONCURRENT: 5 # Run the 10 traces in 2 sets of 5 to avoid OOMs
allow_failure: true
radeonsi-raven-piglit:
extends:
- .lava-x86_64-test-gl
- .radeonsi-raven-test:x86_64
- .test-piglit
- .lava-lenovo-TPad-C13-Yoga-zork:x86_64
parallel: 2
rules:
- !reference [.radeonsi-collabora-rules, rules]
- !reference [.rusticl-rules, rules]
variables:
DEQP_SUITE: radeonsi-raven
HWCI_START_WESTON: 1
# lower image opcodes to emulate CDNA compute devices
radeonsi-raven-cdna-lower-image-piglit:
extends:
- .lava-x86_64-test-gl
- .radeonsi-raven-test:x86_64
- .test-piglit
- .lava-lenovo-TPad-C13-Yoga-zork:x86_64
variables:
DEQP_SUITE: radeonsi-raven-cdna
GPU_VERSION: radeonsi-raven-cdna
radeonsi-raven-va:
extends:
- .lava-x86_64-test-video
- .radeonsi-raven-test:x86_64
- .radeonsi-vaapi-rules
- .test-fluster
- .lava-hp-x360-14a-cb0001xx-zork:x86_64
variables:
DEQP_SUITE: vaapi
GPU_VERSION: radeonsi-raven-va
# While the tests don't need Xorg, it's an easy way to keep DRM open so we don't
# spend all our time in drm_lastclose()'s modesetting.
HWCI_START_WESTON: 1
radeonsi-mendocino-glcts-piglit:
extends:
- .lava-x86_64-test-gl
- .lava-dell-latitude-3445-7520c-skyrim:x86_64
- .test-piglit
- .radeonsi-collabora-rules
parallel: 8
variables:
DEQP_SUITE: radeonsi-mendocino
GPU_VERSION: radeonsi-mendocino
HWCI_START_WESTON: 1
radv-cezanne-vkcts-asan:
extends:
- .lava-x86_64-test-asan-vk
- .radv-cezanne-test:x86_64
- .radv-collabora-rules
parallel: 10
variables:
DEQP_SUITE: radv
DEQP_FRACTION: 5
FDO_CI_CONCURRENT: 3 # We get OOMkills if we go wider
############### VKCTS tests ###############
# VKCTS never finishes on gfx7 due to all the GPU resets and hangs.
# Hence, disable it for now.
.radv-kabini-vkcts-full:
extends:
- .ci-tron-test-radv-vk-nightly
- .kabini-test-valve
- .radv-valve-manual-rules # Make sure this job is *always* run manually
timeout: 12h
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 710
radv-tahiti-vkcts-full:
extends:
- .ci-tron-test-radv-vk-nightly
- .tahiti-test-valve
- .radv-valve-manual-rules # Make sure this job is *always* run manually
timeout: 1h
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 50
RADV_EXPERIMENTAL: heap
radv-hawaii-vkcts-full:
extends:
- .ci-tron-test-radv-vk-nightly
- .hawaii-test-valve
- .radv-valve-manual-rules
timeout: 1h
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 50
RADV_EXPERIMENTAL: heap
radv-polaris10-vkcts-full:
extends:
- .ci-tron-test-radv-vk-nightly
- .polaris10-test-valve-kws
- .radv-valve-manual-rules
timeout: 1h 35m
variables:
CI_TRON_TIMEOUT__BOOT_CYCLE__RETRIES: 4
CI_TRON_TIMEOUT__BOOT_CYCLE__MINUTES: 70
CI_TRON_TIMEOUT__OVERALL__MINUTES: 90
RADV_EXPERIMENTAL: video_decode,video_encode,heap
radv_enable_float16_gfx8: true
radv-vega10-vkcts-full:
extends:
- .ci-tron-test-radv-vk-nightly
- .vega10-test-valve
- .radv-valve-manual-rules
timeout: 1h 15m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 70
RADV_EXPERIMENTAL: transfer_queue,video_decode,video_encode,heap
radv-renoir-vkcts-full:
extends:
- .ci-tron-test-radv-vk-nightly
- .renoir-test-valve
- .radv-valve-manual-rules
timeout: 2h 15m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 130
RADV_EXPERIMENTAL: transfer_queue,heap
radv-navi10-vkcts-full:
parallel: 2
extends:
- .ci-tron-test-radv-vk-nightly
- .navi10-test-valve-kws
- .radv-valve-manual-rules
variables:
RADV_EXPERIMENTAL: transfer_queue,hic,heap
radv-navi21-vkcts:
timeout: 35m
parallel: 3
extends:
- .ci-tron-test-radv-vk
- .navi21-test-valve
- .radv-valve-rules
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 30
RADV_EXPERIMENTAL: transfer_queue,heap
radv-navi21-vkcts-full:
timeout: 60m
extends:
- .ci-tron-test-radv-vk-nightly
- .navi21-test-valve
- .radv-valve-manual-rules
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 55
RADV_EXPERIMENTAL: transfer_queue,heap
radv-vangogh-vkcts-full:
parallel: 2
extends:
- .ci-tron-test-radv-vk-nightly
- .vangogh-test-valve
- .radv-valve-manual-rules
timeout: 90m
variables:
RADV_EXPERIMENTAL: transfer_queue,heap
CI_TRON_TIMEOUT__OVERALL__MINUTES: 89
radeonsi-vangogh-glcts:
extends:
- .ci-tron-x86_64-test-gl
- .ci-tron-test-amdgpu
- .test-piglit
- .vangogh-test-valve
- .radeonsi-valve-rules
timeout: 20m
variables:
GPU_VERSION: radeonsi-vangogh
DEQP_SUITE: radeonsi-vangogh
DEQP_FRACTION: 6
CI_TRON_TIMEOUT__OVERALL__MINUTES: 19
radeonsi-vangogh-glcts-full:
extends:
- radeonsi-vangogh-glcts
- .radeonsi-valve-manual-rules
timeout: 90m
variables:
DEQP_FRACTION: 1
CI_TRON_TIMEOUT__OVERALL__MINUTES: 89
radv-raphael-vkcts-full:
extends:
- .ci-tron-test-radv-vk-nightly
- .raphael-test-valve
- .radv-valve-manual-rules
timeout: 45m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 40
RADV_EXPERIMENTAL: transfer_queue,heap
radv-navi31-vkcts:
timeout: 25m
parallel: 2
extends:
- .ci-tron-test-radv-vk
- .navi31-test-valve
- .radv-valve-rules
variables:
RADV_DEBUG: nomeshshader # Disable mesh shaders until task shaders stop hanging
RADV_EXPERIMENTAL: transfer_queue,heap
CI_TRON_TIMEOUT__OVERALL__MINUTES: 20
radv-navi31-vkcts-full:
timeout: 30m
extends:
- .ci-tron-test-radv-vk-nightly
- .navi31-test-valve
- .radv-valve-manual-rules
variables:
RADV_EXPERIMENTAL: transfer_queue,heap
CI_TRON_TIMEOUT__OVERALL__MINUTES: 25
radv-gfx1201-vkcts:
timeout: 25m
parallel: 3
extends:
- .ci-tron-test-radv-vk
- .gfx1201-test-valve
- .radv-valve-rules
variables:
# TODO: Verify that task shaders don't hang.
RADV_DEBUG: nomeshshader
RADV_EXPERIMENTAL: transfer_queue,heap
CI_TRON_TIMEOUT__OVERALL__MINUTES: 20
radv-gfx1201-vkcts-full:
timeout: 45m
extends:
- .ci-tron-test-radv-vk-nightly
- .gfx1201-test-valve
- .radv-valve-manual-rules
variables:
RADV_EXPERIMENTAL: transfer_queue,heap
CI_TRON_TIMEOUT__OVERALL__MINUTES: 40
radv-gfx1201-fluster:
extends:
- .ci-tron-x86_64-test-video
- .ci-tron-test-radv
- .gfx1201-test-valve
- .radv-valve-manual-rules
- .test-fluster
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8 # normal runtime: 50-60sec, but let's leave room for more tests
DEQP_SUITE: radv-fluster
############### Fossilize
radv-fossils:
extends:
- .radv-valve-rules
- .test-vk
- .ci-tron-test-radv
- .fossilize-test
rules:
- when: never # disabled due to broken job (no git in container)
script:
- export LD_PRELOAD=$PWD/install/lib/libamdgpu_noop_drm_shim.so
# Pitcairn (GFX6)
- AMDGPU_GPU_ID="PITCAIRN"
./install/fossilize-runner.sh
# Bonaire (GFX7)
- AMDGPU_GPU_ID="BONAIRE"
./install/fossilize-runner.sh
# Polaris10 (GFX8)
- AMDGPU_GPU_ID="POLARIS10"
./install/fossilize-runner.sh
# Vega10 (GFX9)
- AMDGPU_GPU_ID="VEGA10"
./install/fossilize-runner.sh
# Navi10 (GFX10)
- AMDGPU_GPU_ID="NAVI10"
./install/fossilize-runner.sh
# Navi21 (GFX10_3)
- AMDGPU_GPU_ID="NAVI21"
./install/fossilize-runner.sh
# RDNA3 (GFX11)
- AMDGPU_GPU_ID="NAVI31"
./install/fossilize-runner.sh
# RDNA3.5 (STRIX1)
- AMDGPU_GPU_ID="STRIX1"
./install/fossilize-runner.sh
############### vkd3d-proton
radv-raven-vkd3d:
extends:
- .lava-x86_64-test-vk
- .test-vkd3d-proton
- .radv-raven-test:x86_64
- .lava-hp-x360-14a-cb0001xx-zork:x86_64
variables:
GPU_VERSION: radv-raven
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
radv-tahiti-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .tahiti-test-valve
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
radv-hawaii-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .hawaii-test-valve
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
radv-polaris10-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .polaris10-test-valve-kws
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
radv-vega10-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .vega10-test-valve
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
radv-renoir-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .renoir-test-valve
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
radv-navi10-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .navi10-test-valve-mupuf
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
radv-navi21-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .navi21-test-valve
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
radv-vangogh-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .vangogh-test-valve
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
radv-raphael-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .raphael-test-valve
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
radv-navi31-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .navi31-test-valve
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
radv-gfx1201-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .gfx1201-test-valve
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
# Random tests fail/crash when trying to run them in parallel
FDO_CI_CONCURRENT: 1
.radv-kabini-vkd3d:
extends:
- .ci-tron-test-radv-vk
- .test-vkd3d-proton
- .kabini-test-valve
- .radv-valve-manual-rules
timeout: 10m
variables:
CI_TRON_TIMEOUT__OVERALL__MINUTES: 8
src/amd/ci/radeonsi-mendocino-fails.txt
+413
View File
@@ -0,0 +1,413 @@
KHR-GL46.shader_image_load_store.basic-allTargets-atomic,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgb10_a2,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgb10_a2ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgb565,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgb9_e5,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba16_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgb10_a2,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgb10_a2ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgb565,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgb9_e5,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba16_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_depth_component16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r16i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r16ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r32f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r32ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r8i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg16i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg16ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg32f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg32ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg8i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgb10_a2,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba16i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba16ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba32f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba8i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_depth_component16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r16i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r16ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r32f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r32ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r8i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg16i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg16ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg32f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg32ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg8i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgb10_a2,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba16i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba16ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba32f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba8i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba8ui,Fail
glx@glx_arb_sync_control@waitformsc,Fail
glx@glx-make-current,Fail
glx@glx-multi-window-single-context,Fail
glx@glx-swap-pixmap-bad,Fail
spec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,Fail
spec@arb_shading_language_packing@execution@built-in-functions@fs-packhalf2x16,Fail
spec@arb_shading_language_packing@execution@built-in-functions@vs-packhalf2x16,Fail
spec@arb_tessellation_shader@arb_tessellation_shader-tes-gs-max-output -small -scan 1 50,Fail
spec@arb_texture_multisample@sample-position@4,Fail
spec@egl 1.4@eglterminate then unbind context,Fail
spec@egl_khr_surfaceless_context@viewport,Fail
spec@egl_mesa_configless_context@basic,Fail
spec@ext_external_objects@vk-ping-pong-single-sem,Crash
[email protected]@execution@built-in-functions@fs-packhalf2x16,Fail
[email protected]@execution@built-in-functions@vs-packhalf2x16,Fail
spec@khr_texture_compression_astc@miptree-gles srgb-fp,Fail
spec@khr_texture_compression_astc@miptree-gles srgb-fp@sRGB decode full precision,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp@sRGB decode full precision,Fail
spec@!opengl 1.0@rasterpos,Fail
spec@!opengl 1.0@rasterpos@glsl_vs_gs_linked,Fail
spec@!opengl 1.0@rasterpos@glsl_vs_tes_linked,Fail
spec@!opengl 1.1@line-smooth-stipple,Fail
src/amd/ci/radeonsi-mendocino-flakes.txt
+60
View File
@@ -0,0 +1,60 @@
dEQP-GLES31.functional.geometry_shading.basic.output_max
KHR-GL46.copy_image.functional_src_target_texture_2d_array_src_format_r11f_g11f_b10f_dst_target_texture_2d_array_dst_format_rgb9_e5
KHR-GL46.copy_image.functional_src_target_texture_2d_array_src_format_r11f_g11f_b10f_dst_target_texture_rectangle_dst_format_rgb10_a2
KHR-GL46.copy_image.functional_src_target_texture_2d_array_src_format_rgb10_a2ui_dst_target_texture_rectangle_dst_format_rgb9_e5
KHR-GL46.copy_image.functional_src_target_texture_3d_src_format_r11f_g11f_b10f_dst_target_texture_rectangle_dst_format_rgb10_a2
KHR-GL46.copy_image.functional_src_target_texture_3d_src_format_rgb10_a2ui_dst_target_texture_rectangle_dst_format_rgb9_e5
KHR-GL46.copy_image.functional_src_target_texture_rectangle_src_format_rgb32f_dst_target_texture_2d_array_dst_format_rgb32f
KHR-GL46.copy_image.functional_src_target_texture_rectangle_src_format_rgb9_e5_dst_target_texture_2d_array_dst_format_r11f_g11f_b10f
KHR-GL46.direct_state_access.framebuffers_texture_layer_attachment
KHR-GL46.explicit_uniform_location.uniform-loc-mix-with-implicit-max
KHR-GL46.gpu_shader_fp64.builtin.fract_dvec2
KHR-GL46.packed_pixels.varied_rectangle.compressed_srgb_alpha_format_bgr
KHR-GL46.packed_pixels.varied_rectangle.rg8_format_bgr
KHR-GL46.packed_pixels.varied_rectangle.rgba8_format_bgra
KHR-GL46.pipeline_statistics_query_tests_ARB.functional_primitives_vertices_submitted_and_clipping_input_output_primitives
KHR-GL46.pixelstoragemodes.teximage2d.r8i.16_16
KHR-GL46.pixelstoragemodes.teximage2d.rgba8.16_1
KHR-GL46.program_interface_query.subroutines-geometry
KHR-GL46.shader_image_size.advanced-ms-tcs-int
KHR-GL46.shader_storage_buffer_object.advanced-write-tessellation
KHR-GL46.shaders.loops.do_while_uniform_iterations.basic_highp_float_vertex
KHR-GL46.shaders.loops.while_dynamic_iterations.basic_lowp_int_vertex
KHR-GL46.shaders.struct.local.parameter_nested_vertex
KHR-GL46.texture_size_promotion.functional
KHR-GL46.texture_swizzle.smoke_access_idx_3_channel_idx_1
KHR-GLES31.core.explicit_uniform_location.uniform-loc-mix-with-implicit-max
KHR-Single-GL46.arrays_of_arrays_gl.AtomicDeclaration
KHR-Single-GL46.enhanced_layouts.varying_array_locations
KHR-Single-GL46.enhanced_layouts.varying_structure_locations
# The entire test group (400+ tests in every test group under that) is flaky, nothing could be salvaged
KHR-Single-GL46.subgroups.*
glx@glx-multithread-texture
glx@glx-visuals-depth
glx@glx-visuals-stencil
spec@!opengl [email protected]
# Flaky on innocent MRs starting 2025-07-31
spec@arb_shader_image_load_store@coherency
spec@arb_shader_image_load_store@coherency@Tessellation evaluation-Fragment shader/'volatile' qualifier coherency test/256x256
spec@arb_shader_image_load_store@coherency@Tessellation evaluation-Fragment shader/'coherent' qualifier coherency test/256x256
spec@arb_tessellation_shader@arb_tessellation_shader-tes-gs-max-output -small -scan 1 50
spec@arb_texture_multisample@arb_texture_multisample-dsa-texelfetch
spec@arb_texture_multisample@sample-position@6
spec@arb_texture_multisample@sample-position@8
spec@arb_timer_query@query gl_timestamp
spec@arb_timer_query@timestamp-get
spec@egl_chromium_sync_control@conformance
spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test
spec@ext_clear_texture@ext_clear_texture-clear-max-level
spec@ext_external_objects@vk-ping-pong-multi-sem
spec@ext_external_objects@vk-ping-pong-single-sem
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-refcount-multithread
[email protected]@execution@built-in-functions@fs-op-bitand-abs-neg-ivec3-ivec3
[email protected]@execution@built-in-functions@vs-op-assign-rshift-ivec4-uint
[email protected]@execution@inout@vs-out-fs-in-s1-float-dvec2-location-0
src/amd/ci/radeonsi-mendocino-skips.txt
+12
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@@ -0,0 +1,12 @@
# Times out
dEQP-GLES31.functional.geometry_shading.basic.output_256
KHR-GLES31.core.tessellation_shader.vertex.vertex_ordering
KHR-GL46.tessellation_shader.vertex.vertex_ordering
KHR-Single-GL46.arrays_of_arrays_gl.AtomicUsage
# The mesh shader tests trigger GPU resets on amdgpu, making the system
# unstable, so they have to be be skipped for now.
KHR-Single-GL46.meshShader.*
# These tests can time out, even when run single-threaded
KHR-Single-GL46.subgroups.arithmetic.framebuffer.*
src/amd/ci/radeonsi-raven-cdna-fails.txt
+3
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@@ -0,0 +1,3 @@
spec@arb_spirv_extensions@arb_spirv_extensions-post_depth_coverage-basic,Crash
spec@arb_spirv_extensions@arb_spirv_extensions-post_depth_coverage-multisampling,Crash
spec@arb_spirv_extensions@arb_spirv_extensions-post_depth_coverage-sample-shading,Crash
src/amd/ci/radeonsi-raven-cdna-skips.txt
+246
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@@ -0,0 +1,246 @@
# TODO: see if these copy/image load and compute tests should work
spec@arb_compute_shader@render-and-compute
spec@arb_compute_shader@compute-and-render-bug-109630
spec@arb_compute_shader@execution@border-color
spec@nv_compute_shader_derivatives
spec@nv_copy_image
spec@arb_copy_image@arb_copy_image-srgb-copy
spec@arb_copy_image@arb_copy_image-targets
spec@arb_copy_image@arb_copy_image-api_errors
spec@arb_copy_image@arb_copy_image-format-swizzle
spec@arb_copy_image@arb_copy_image-formats
spec@arb_copy_image@arb_copy_image-levels-copy
spec@arb_copy_image@arb_copy_image-simple
spec@arb_copy_image@arb_copy_image-texview
spec@arb_shader_image_load_store@atomicity
spec@arb_shader_image_load_store@bitcast
spec@arb_shader_image_load_store@coherency
spec@arb_shader_image_load_store@dead-fragments
spec@arb_shader_image_load_store@early-z
spec@arb_shader_image_load_store@host-mem-barrier
spec@arb_shader_image_load_store@indexing
spec@arb_shader_image_load_store@invalid
spec@arb_shader_image_load_store@layer
spec@arb_shader_image_load_store@level
spec@arb_shader_image_load_store@max-images
spec@arb_shader_image_load_store@max-size
spec@arb_shader_image_load_store@qualifiers
spec@arb_shader_image_load_store@restrict
spec@arb_shader_image_load_store@semantics
spec@arb_shader_image_load_store@shader-mem-barrier
spec@arb_shader_image_load_store@state
spec@arb_shader_image_load_store@unused
spec@arb_shader_image_load_store@execution
spec@arb_shader_image_load_store@execution
spec@ext_shader_image_load_store@image_functions
shaders@
glx@
wgl@
spec@oes
spec@!opengl
spec@glsl
spec@arb_shader_texture_image_samples
spec@amd_depth_clamp_separate
spec@amd_framebuffer_multisample_advanced
spec@arb_timer_query
spec@arb_transform_feedback_instanced
spec@ext_base_instance
spec@ext_clear_texture@
spec@ext_direct_state_access
spec@ext_draw_instanced
spec@amd_performance_monitor
spec@arb_arrays_of_arrays
spec@arb_point_sprite
spec@arb_tessellation_shader
spec@arb_texture_multisample
spec@arb_texture_gather
spec@arb_stencil_texturing
spec@arb_sync
spec@arb_es2_compatibility
spec@arb_get_program_binary
spec@ext_depth_bounds_test
spec@arb_depth_clamp
spec@arb_draw_elements_base_vertex
spec@arb_draw_instanced
spec@arb_draw_indirect
spec@arb_multi_draw_indirect
spec@arb_fragment_program
spec@nv_fragment_program_option
spec@ati_fragment_shader
spec@arb_framebuffer_object
spec@arb_framebuffer_srgb
spec@arb_gpu_shader5
spec@arb_gpu_shader_fp64
spec@arb_shader_subroutine
spec@arb_occlusion_query
spec@arb_point_parameters
spec@arb_separate_shader_objects
spec@arb_sampler_objects
spec@arb_sample_shading
spec@arb_debug_output
spec@khr_debug
spec@arb_occlusion_query2
spec@ext_external_objects
spec@ext_texture_format_bgra8888
spec@arb_pixel_buffer_object
spec@arb_provoking_vertex
spec@arb_robustness
spec@arb_shader_texture_lod
spec@arb_shader_objects
spec@arb_shading_language_420pack
spec@arb_shading_language_include
spec@arb_enhanced_layouts
spec@arb_explicit_attrib_location
spec@arb_program_interface_query
spec@arb_framebuffer_no_attachments
spec@arb_explicit_uniform_location
spec@arb_texture_buffer_object
spec@arb_texture_buffer_range
spec@arb_texture_rectangle
spec@arb_texture_storage
spec@arb_texture_storage_multisample
spec@arb_texture_view
spec@3dfx_texture_compression_fxt1
spec@arb_clip_control
spec@arb_color_buffer_float
spec@arb_depth_texture
spec@arb_depth_buffer_float
spec@arb_get_texture_sub_image
spec@ext_texture_env_combine
spec@arb_texture_env_crossbar
spec@arb_texture_compression
spec@ext_vertex_array_bgra
spec@apple_vertex_array_object
spec@arb_vertex_array_bgra
spec@arb_vertex_array_object
spec@arb_vertex_buffer_object
spec@arb_vertex_program
spec@arb_viewport_array
spec@nv_vertex_program2_option
spec@ext_framebuffer_blit
spec@ext_framebuffer_multisample_blit_scaled
spec@ext_framebuffer_multisample
spec@ext_framebuffer_object
spec@ext_gpu_shader
spec@ext_image_dma_buf_import
spec@ext_packed_depth_stencil
spec@oes_required_internalformat
spec@ext_occlusion_query_boolean
spec@ext_disjoint_timer_query@simple
spec@ext_texture_norm16@render
spec@ext_render_snorm@render
spec@ext_frag_depth@fragdepth_gles2
spec@ext_texture_array
spec@arb_texture_cube_map
spec@arb_texture_cube_map_array
spec@ext_texture_swizzle
spec@ext_texture_compression
spec@ext_packed_float
spec@arb_texture_float
spec@ext_texture_integer
spec@arb_texture_rg@
spec@arb_texture_rgb10_a2ui
spec@ext_texture_shared_exponent
spec@ext_texture_snorm
spec@ext_texture_srgb
spec@ext_timer_query
spec@ext_transform_feedback
spec@arb_uniform_buffer_object
spec@ati_draw_buffers
spec@ati_envmap_bumpmap
spec@arb_instanced_arrays
spec@arb_internalformat_query
spec@arb_map_buffer_range
spec@arb_multisample@beginend
spec@arb_multisample@pushpop
spec@arb_seamless_cube_map
spec@amd_pinned_memory
spec@amd_seamless_cubemap_per_texture
spec@amd_vertex_shader
spec@ext_fog_coord
spec@nv_half_float
spec@nv_texture_barrier
spec@nv_texture_env_combine4
spec@nv_conditional_render
spec@nv_fill_rectangle@invalid-draw-mode
spec@nv_fog_distance
spec@oes_matrix_get@all queries
spec@oes_fixed_point@attribute-arrays
spec@arb_clear_buffer_object
spec@arb_clear_texture
spec@nv_alpha_to_coverage_dither_control
spec@nv_copy_depth_to_color
spec@arb_cull_distance
spec@arb_half_float_vertex
spec@oes_vertex
spec@arb_vertex_type
spec@arb_draw_buffers
spec@arb_blend_func_extended
spec@arb_base_instance
spec@arb_buffer_storage
spec@apple_object_purgeable
spec@mesa_pack_invert
spec@oes_read_format
spec@nv_primitive_restart
spec@ext_provoking_vertex@provoking-vertex
spec@ext_texture_lod_bias@lodbias
spec@sgis_generate_mipmap
spec@arb_map_buffer_alignment
spec@arb_geometry_shader4
spec@arb_shader_storage_buffer_object
spec@arb_sparse_buffer
spec@arb_sparse_buffer@minmax
spec@ext_polygon_offset_clamp
spec@arb_pipeline_statistics_query
hiz
fast_color_clear
spec@ext_unpack_subimage@basic
spec@oes_draw_texture@oes_draw_texture
spec@oes_compressed_etc1_rgb8_texture@basic
spec@oes_compressed_etc1_rgb8_texture@miptree
spec@khr_parallel_shader_compile@basic
spec@khr_parallel_shader_compile@basic_gles2
spec@khr_texture_compression_astc
spec@nv_read_depth@read_depth_gles3
spec@oes_compressed_paletted_texture@basic api
spec@oes_compressed_paletted_texture@invalid formats
spec@egl
spec@arb_es3_compatibility
spec@arb_shader_atomic_counters
spec@arb_direct_state_access
spec@arb_post_depth_coverage
spec@arb_fragment_shader_interlock@arb_fragment_shader_interlock-image-load-store
spec@arb_shader_image_size@builtin
spec@arb_shader_texture_image_samples@builtin-image
spec@arb_texture_stencil8
spec@arb_vertex_attrib_64bit
spec@arb_query_buffer_object@qbo
spec@arb_query_buffer_object@coherency
spec@ext_framebuffer_blit@blit-early
spec@oes_draw_elements_base_vertex
spec@oes_geometry_shader@built-in constants
spec@ext_shader_samples_identical
spec@arb_shader_draw_parameters
spec@arb_indirect_parameters
object namespace pollution
spec@arb_texture_barrier
spec@arb_invalidate_subdata@buffer
spec@ext_window_rectangles
spec@arb_compute_variable_group_size
spec@intel_conservative_rasterization
spec@intel_blackhole_render
spec@intel_performance_query
spec@arb_bindless_texture
spec@arb_sample_locations@test
spec@nv_image_formats@nv_image_formats-gles3
spec@ext_color_buffer_float@ext_color_buffer_float-draw_gles3
spec@amd_compressed_atc_texture
spec@oes_egl_image_external_essl3
spec@nv_viewport_swizzle
spec@amd_texture_texture4
spec@arb_gl_spirv
spec@arb_shading_language_packing
spec@arb_texture_query_levels
spec@arb_texture_query_lod
spec@ati_texture_compression_3dc
src/amd/ci/radeonsi-raven-fails.txt
+76
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@@ -0,0 +1,76 @@
glx@glx-make-current,Fail
glx@glx-multi-window-single-context,Fail
glx@glx-swap-event_async,Fail
glx@glx-swap-pixmap-bad,Fail
spec@!opengl 1.0@rasterpos,Fail
spec@!opengl 1.0@rasterpos@glsl_vs_gs_linked,Fail
spec@!opengl 1.0@rasterpos@glsl_vs_tes_linked,Fail
spec@!opengl [email protected] cull-back pv-last,Fail
spec@!opengl [email protected] cull-front pv-last,Fail
spec@!opengl [email protected] line cull-back pv-last,Fail
spec@!opengl [email protected] line cull-front pv-last,Fail
spec@!opengl [email protected] pv-last,Fail
spec@arb_shading_language_packing@execution@built-in-functions@fs-packhalf2x16,Fail
spec@arb_shading_language_packing@execution@built-in-functions@vs-packhalf2x16,Fail
spec@egl 1.4@eglterminate then unbind context,Fail
spec@egl_chromium_sync_control@conformance,Fail
spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test,Fail
spec@egl_khr_surfaceless_context@viewport,Fail
spec@egl_mesa_configless_context@basic,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y210,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y212,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y216,Fail
[email protected]@execution@geometry@primitive-types gl_triangle_strip_adjacency,Fail
[email protected]@execution@geometry@tri-strip-ordering-with-prim-restart gl_triangle_strip_adjacency ffs,Fail
[email protected]@execution@geometry@tri-strip-ordering-with-prim-restart gl_triangle_strip_adjacency other,Fail
[email protected]@execution@built-in-functions@fs-packhalf2x16,Fail
[email protected]@execution@built-in-functions@vs-packhalf2x16,Fail
spec@khr_texture_compression_astc@miptree-gles srgb-fp,Fail
spec@khr_texture_compression_astc@miptree-gles srgb-fp@sRGB decode full precision,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp@sRGB decode full precision,Fail
spec@!opengl 1.1@line-smooth-stipple,Fail
# since transition XORG -> WESTON
glx@glx_arb_sync_control@waitformsc,Fail
# Since switching to test-gl container based rootfs
spec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,Fail
# rusticl
api@clbuildprogram,Fail
api@clcompileprogram,Fail
api@clgetcommandqueueinfo,Fail
api@clgetdeviceinfo,Fail
api@clgetextensionfunctionaddressforplatform,Fail
api@clgetkernelarginfo,Fail
api@clsetkernelarg,Fail
api@clsetkernelarg@Input checks,Fail
api@cllinkprogram,Fail
program@build@vector-data-types,Fail
program@execute@[email protected],Fail
program@execute@[email protected]@nextafter float1,Fail
program@execute@[email protected]@nextafter float16,Fail
program@execute@[email protected]@nextafter float2,Fail
program@execute@[email protected]@nextafter float4,Fail
program@execute@[email protected]@nextafter float8,Fail
program@execute@[email protected],Fail
program@execute@[email protected]@sign float1,Fail
program@execute@[email protected]@sign float16,Fail
program@execute@[email protected]@sign float2,Fail
program@execute@[email protected]@sign float4,Fail
program@execute@[email protected]@sign float8,Fail
program@execute@global-offset,Fail
program@execute@global-offset@3d- input dependent,Fail
program@execute@vector-conversion,Fail
api@clgetmemobjectinfo,Fail
# piglit bug, pigligt checks the global limits, but radeonsi advertises
# only half the threads if the work group size is variable...
program@run kernel with max work item sizes,Fail
# uprev Piglit in Mesa
spec@ext_external_objects@vk-semaphores,Crash
spec@ext_external_objects@vk-semaphores-2,Crash
src/amd/ci/radeonsi-raven-flakes.txt
+48
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@@ -0,0 +1,48 @@
spec@arb_timer_query@timestamp-get
spec@arb_shader_draw_parameters@drawid-single-draw-display-list
# The following two case are xfails, but sometimes pass.
spec@egl_chromium_sync_control@conformance
spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test
# ci-collate: Issue found in https://gitlab.freedesktop.org/mesa/mesa/-/jobs/49445712
glx@glx-multithread-texture
# uprev Piglit in Mesa
glx@glx-buffer-age vblank_mode=0
glx@glx-swap-singlebuffer
glx@glx_arb_sync_control@swapbuffersmsc-return swap_interval 1
glx@glx-visuals-depth
spec@!opengl [email protected]
spec@!opengl 1.1@ppgtt_memory_alignment
spec@egl 1.4@eglcreatepbuffersurface with egl_samples set
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-refcount-multithread
# With linux kernel 6.13-rc4 uprev
spec@!opengl [email protected]
spec@arb_gpu_shader5@texturegatheroffset@fs-rgb-2-int-2drect-const
spec@arb_shader_image_load_store@coherency
spec@arb_shader_image_load_store@coherency@Tessellation control-Tessellation evaluation shader/'coherent' qualifier coherency test/256x256
spec@arb_shader_image_load_store@shader-mem-barrier
spec@arb_shader_image_load_store@shader-mem-barrier@Geometry shader/'coherent' qualifier memory barrier test/modulus=64
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec2-index-wr
spec@arb_texture_gather@texturegather@fs-rg-green-int-2darray
spec@arm_shader_framebuffer_fetch_depth_stencil@arm_shader_framebuffer_fetch_depth_stencil gl_depth_component32f 16
spec@ext_framebuffer_multisample@accuracy 32 depth_draw small depthstencil
spec@ext_gpu_shader4@tex-miplevel-selection gpu4textureprojgrad 2dshadow
glx@glx-visuals-stencil
glx@glx_arb_sync_control@swapbuffersmsc-return swap_interval 0
spec@!opengl [email protected]
spec@!opengl 2.0@vertex-program-two-side back front2
spec@!opengl 2.0@vertex-program-two-side enabled front front2 back2
spec@amd_shader_trinary_minmax@execution@built-in-functions@tcs-max3-int-int-int
spec@arb_shader_atomic_counters@semantics
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec2-index-wr-before-tcs
spec@arb_texture_view@rendering-r32ui
spec@egl_nok_texture_from_pixmap@basic
spec@ext_disjoint_timer_query@simple
spec@ext_framebuffer_blit@fbo-blit-check-limits
spec@ext_framebuffer_blit@fbo-sys-blit
[email protected]@execution@texelfetch@gs-texelfetch-sampler1darray
[email protected]@execution@texelfetch@gs-texelfetch-usampler1d
src/amd/ci/radeonsi-raven-fluster-flakes.txt
+5
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@@ -0,0 +1,5 @@
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-16-r1-L1
GStreamer-H.264-VAAPI-Gst1.0@SVCHCTS-1-r1-L1
GStreamer-H.265-VAAPI-Gst1.0@CCP_8bit_RExt_QCOM_1
GStreamer-H.265-VAAPI-Gst1.0@HYBRID_A_QUALCOMM_1
GStreamer-H.265-VAAPI-Gst1.0@SREXT_B_FUJITSU_1
src/amd/ci/radeonsi-raven-skips.txt
+38
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@@ -0,0 +1,38 @@
# From https://github.com/marekolsak/marek-build/blob/master/run-piglit.sh#L36
spec@!opengl [email protected]
spec@!opengl 1.1@max-texture-size
spec@!opengl 1.1@max-texture-size-level
spec@!opengl 1.2@tex3d-maxsize
spec@arb_texture_buffer_object@max-size
spec@ext_framebuffer_object@fbo-maxsize
# times out
spec@arb_compute_shader@local-id-explosion
spec@arb_uniform_buffer_object@maxuniformblocksize@vs
spec@arb_uniform_buffer_object@maxuniformblocksize@vsexceed
spec@arb_uniform_buffer_object@maxuniformblocksize@fs
spec@arb_uniform_buffer_object@maxuniformblocksize@fsexceed
spec@arb_shader_storage_buffer_object@max-ssbo-size@fs
spec@arb_shader_storage_buffer_object@max-ssbo-size@vsexceed
spec@arb_shader_storage_buffer_object@max-ssbo-size@vs
spec@arb_shader_storage_buffer_object@max-ssbo-size@fsexceed
spec@arb_shader_image_load_store@max-size
spec@arb_texture_buffer_object@texture-buffer-size-clamp
spec@arb_texture_buffer_object@texture-buffer-size-clamp@rgba8ui_texture_buffer_size_via_sampler
spec@arb_texture_buffer_object@texture-buffer-size-clamp@rgba8ui_texture_buffer_size_via_image
spec@ext_transform_feedback@max-varyings
spec@ext_external_objects@semaphore-api-errors
spec@ext_external_objects@vk-image-display-overwrite
spec@ext_external_objects@memory-object-api-errors
spec@ext_external_objects@vk-image-overwrite
spec@ext_external_objects@vk-image-display
spec@ext_external_objects@vk-vert-buf-update-errors
spec@ext_external_objects@vk-buf-exchange
spec@ext_external_objects@vk-depth-display
spec@ext_external_objects@vk-pix-buf-update-errors
spec@ext_external_objects_fd@semaphore-api-errors
spec@ext_external_objects_fd@memory-object-api-errors
spec@ext_external_objects@vk-vert-buf-reuse
[email protected]@execution@texelfetch fs sampler2d 1x281-501x281
src/amd/ci/radeonsi-raven-slow-skips.txt
+6
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@@ -0,0 +1,6 @@
# Skip tests, mainly because some tests exceed the 1 minute mark
# Note that this not affect full jobs.
glx@glx-buffer-age vblank_mode=0
glx@glx_arb_sync_control@swapbuffersmsc-return swap_interval 1
spec@egl 1.4@eglcreatepbuffersurface with egl_samples set
src/amd/ci/radeonsi-raven-va-fails.txt
+461
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@@ -0,0 +1,461 @@
GStreamer-H.264-VAAPI-Gst1.0@BA3_SVA_C,Crash
GStreamer-H.264-VAAPI-Gst1.0@CVFC1_Sony_C,Fail
GStreamer-H.264-VAAPI-Gst1.0@FM1_BT_B,Crash
GStreamer-H.264-VAAPI-Gst1.0@FM1_FT_E,Fail
GStreamer-H.264-VAAPI-Gst1.0@FM2_SVA_C,Crash
GStreamer-H.264-VAAPI-Gst1.0@FREH10-1,Crash
GStreamer-H.264-VAAPI-Gst1.0@FREH10-2,Crash
GStreamer-H.264-VAAPI-Gst1.0@FREXT1_TANDBERG_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@FREXT2_TANDBERG_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@FREXT3_TANDBERG_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@HPCAMOLQ_BRCM_B,Fail
GStreamer-H.264-VAAPI-Gst1.0@HPCVMOLQ_BRCM_B,Fail
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR10_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR11_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR12_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR13_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR14_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR15_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR1_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR2_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR3_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR4_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR6_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR7_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR8_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FR9_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FREXT16_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FREXT17_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FREXT18_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@Hi422FREXT19_SONY_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@MR6_BT_B,Crash
GStreamer-H.264-VAAPI-Gst1.0@MR7_BT_B,Crash
GStreamer-H.264-VAAPI-Gst1.0@MR8_BT_B,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCDS-4,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCDS-5,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCDS-6,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCDS1,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCDS2,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCDS3,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCICT-1,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCICT-2,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCNV-2,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCNV-3,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCNV1,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCNV4,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCRP_1,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCRP_2,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCRP_3,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCRP_4,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCRP_5,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCRP_6,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCSPS-1,Crash
GStreamer-H.264-VAAPI-Gst1.0@MVCSPS-2,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPCV444I1_2008,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPCV444I2_2008,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPCV444I3_2008,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPCV444I4_Mitsubishi_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPCV444I5_Mitsubishi_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPCV444I6_Mitsubishi_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPCV444I7_SejongUniv_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH10I1_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH10I2_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH10I3_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH10I4_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH10I5_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH10I6_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH10I7_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH422I1_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH422I2_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH422I3_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH422I4_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH422I5_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH422I6_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH422I7_Panasonic_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444I1_2008,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444I2_2008,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444I3_2008,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444I4_Mitsubishi_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444I5_Mitsubishi_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444I6_Mitsubishi_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444I7_SejongUniv_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444P10_SejongUniv_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444P1_2008,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444P2_2008,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444P3_2008,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444P4_2008,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444P5_2008,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444P6_Mitsubishi_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444P7_Mitsubishi_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444P8_Mitsubishi_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@PPH444P9_Mitsubishi_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@SP1_BT_A,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBC-1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBCT-1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBCTS-1-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBCTS-1-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBCTS-2-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBCTS-2-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBCTS-3-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBCTS-3-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-2-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-2-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-3-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-3-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-4-r1-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-4-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-4-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-5-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-5-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-5-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBM-5-L3,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMST-1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBMST-1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMST-1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMST-2-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBMST-2-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMST-2-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMST-3-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMST-3-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMST-3-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-10-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-10-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-11-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-11-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-12-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-12-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-13-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-13-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-13-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-2-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-3-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-3-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-4-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-4-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-5-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-5-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-6-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-6-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-7-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-7-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-8-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-8-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-9-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBMT-9-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBS-1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBS-2-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBS-2-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBS-3-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBS-4-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBS-5-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBS-6-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBS-6-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBS-7-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBS-8-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-10-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-10-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-11-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-11-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-12-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-12-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-13-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-13-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-14-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-14-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-14-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-15-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-15-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-15-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-16-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-16-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-16-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-17-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-17-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-17-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-18-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-18-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-18-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-19-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-2-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-2-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-20-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-3-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-3-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-4-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-4-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-5-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-5-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-6-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-6-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-7-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-7-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-8-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-8-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-9-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCBST-9-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBSTC-1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCBSTC-1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHCTS-1-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHCTS-1-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHCTS-1-r1-L3,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHCTS-1-r1-L4,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHCTS-1-r1-L5,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHCTS-1-r1-L6,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHCTS-1-r1-L7,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHICS-1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHICS-1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHICS-1-L3,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHIS-1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHIS-1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHIS-2-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHIS-2-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHIS-3-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHIS-3-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHM-1-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHM-1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHM-1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHM-1-L3,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHM-2-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHM-2-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHM-3-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHM-3-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHM-4-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHM-4-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHM-4-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHMTS-1-r1-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHMTS-1-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHMTS-1-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHMTS-1-r1-L3,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHMTS-1-r1-L4,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHMTS-1-r1-L5,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHMTS-2-r1-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHMTS-2-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHMTS-2-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHS-1-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHS-2-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHST-1-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCHST-1-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHST-1-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHST-2-r1-L0,Fail
GStreamer-H.264-VAAPI-Gst1.0@SVCHST-2-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHST-2-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHST-3-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHST-4-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHSTC-1-r1-L0,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHSTC-1-r1-L1,Crash
GStreamer-H.264-VAAPI-Gst1.0@SVCHSTC-1-r1-L2,Crash
GStreamer-H.264-VAAPI-Gst1.0@sp2_bt_b,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_C_A_HHI_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_C_B_HHI_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_C_C_Sharp_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_D1_A_HHI_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_D1_B_HHI_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_D1_C_RWTH_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_D1_D_RWTH_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_D1_E_MediaTek_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_D1_F_MediaTek_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_D1_G_Hisilicon_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_D1_H_Hisilicon_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_D2_A_Samsung_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_D2_B_LGE_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_DT_A_MediaTek_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_DT_B_NTT_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_DT_C_Hisilicon_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_DT_D_NTT_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_TD_A_Qualcomm_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_TD_B_MediaTek_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_TD_C_MediaTek_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_TD_D_HHI_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_TD_E_HHI_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_T_A_Qualcomm_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_T_B_MediaTek_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_T_C_Sharp_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_T_D_Sharp_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@3DHC_T_E_HHI_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@ADAPTRES_A_ERICSSON_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@ADJUST_IPRED_ANGLE_A_RExt_Mitsubishi_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@ALPHA_A_BBC_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@Bipred_8by8_A_Qualcomm_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@Bitdepth_A_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@Bitdepth_B_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CCP_10bit_RExt_QCOM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CCP_12bit_RExt_QCOM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CCP_8bit_RExt_QCOM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CGS_A_TECHNICOLOR_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CGS_B_TECHNICOLOR_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CGS_C_TECHNICOLOR_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CGS_D_TECHNICOLOR_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CGS_E_TECHNICOLOR_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CGS_F_TECHNICOLOR_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CGS_G_TECHNICOLOR_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CGS_H_TECHNICOLOR_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CGS_I_TECHNICOLOR_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@CONFCROP_A_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@CONFCROP_B_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@CONFCROP_C_VIDYO_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@CONFWIN_A_Sony_1,Fail
GStreamer-H.265-VAAPI-Gst1.0@DEPTH_A_NOKIA_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@DISFLAG_A_QUALCOMM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@DPB_A_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@DPB_B_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@DPB_Loop_Filters_A_MediaTek_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@Delta_QP_Chroma_QP_Offsets_A_Qualcomm_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_10BIT_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_12BIT_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_16BIT_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_8BIT_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@EXTPREC_MAIN_444_16_INTRA_10BIT_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@EXTPREC_MAIN_444_16_INTRA_12BIT_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@EXTPREC_MAIN_444_16_INTRA_16BIT_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@EXTPREC_MAIN_444_16_INTRA_8BIT_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@ExplicitRdpcm_A_BBC_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@ExplicitRdpcm_B_BBC_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@GENERAL_10b_422_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@GENERAL_10b_444_RExt_Sony_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@GENERAL_12b_400_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@GENERAL_12b_420_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@GENERAL_12b_422_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@GENERAL_12b_444_RExt_Sony_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@GENERAL_16b_400_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@GENERAL_16b_444_RExt_Sony_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@GENERAL_16b_444_highThroughput_RExt_Sony_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@GENERAL_8b_400_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@GENERAL_8b_444_RExt_Sony_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@HT_A_SCC_Apple_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@HT_B_SCC_Apple_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@HT_C_SCC_Apple_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@HYBRID_A_QUALCOMM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@IBF_Disabled_A_MediaTek_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@IBF_Disabled_B_MediaTek_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@INACTIVE_A_QCOM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@INBLD_A_NOKIA_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@IPCM_A_RExt_NEC_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@IPCM_B_RExt_NEC,Crash
GStreamer-H.265-VAAPI-Gst1.0@IPRED_B_Nokia_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@LAYERID63_A_HHI_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@LAYERID_A_NOKIA_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@MAXTID_A_ETRI_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@MAXTID_B_ETRI_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@MAXTID_C_ETRI_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVD_A_IDCC_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVD_A_NOKIA_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVHEVCS_A_Qualcomm_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVHEVCS_B_Sharp_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVHEVCS_C_Sony_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVHEVCS_D_NTT_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVHEVCS_E_Qualcomm_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVHEVCS_F_Qualcomm_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVHEVCS_G_NTT_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVHEVCS_H_LGE_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVHEVCS_I_Nokia_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVRESIDC_A_MS_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVRESIDC_B_MS_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@MVRESIDC_C_MS_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@Main_422_10_A_RExt_Sony_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@Main_422_10_B_RExt_Sony_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@NONVUI_A_QUALCOMM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@NONVUI_B_QUALCOMM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@NONVUI_C_QUALCOMM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@OLS_A_NOKIA_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@OLS_B_NOKIA_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@OLS_C_NOKIA_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@PERSIST_RPARAM_A_RExt_Sony_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@PICSIZE_A_Bossen_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@PICSIZE_B_Bossen_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@PICSIZE_C_Bossen_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@PICSIZE_D_Bossen_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@POC_A_Ericsson_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@POC_B_Ericsson_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@PPI_A_InterDigital_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@PPI_B_InterDigital_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@PPSSLIST_A_Sony_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@PSEXT_A_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@QMATRIX_A_RExt_Sony_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@REFLAYER_A_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@REFLAYER_B_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@REFLAYER_C_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@REFLAYER_D_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@REFREGOFF_A_SHARP_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@REPFMT_A_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@REPFMT_B_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@REPFMT_C_VIDYO_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@RESCHANGE_A_VIDYO_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@RESPHASE_A_SAMSUNG_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@SAO_A_RExt_MediaTek_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SCREFOFF_A_QCOM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SIM_A_IDCC_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SIM_B_IDCC_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SLLEV_A_VIDYO_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SNR_A_IDCC_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SNR_B_IDCC_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SNR_C_IDCC_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SPLITFLAG_A_HHI_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SPSREPFMT_A_Sony_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@SPSSLIST_A_Sony_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@SRATIOS_A_SAMSUNG_3,Crash
GStreamer-H.265-VAAPI-Gst1.0@SRATIOS_B_SAMSUNG_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@SREXT_A_FUJITSU_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SREXT_B_FUJITSU_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SREXT_C_FUJITSU_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SREXT_D_FUJITSU_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SREXT_E_FUJITSU_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@SREXT_F_FUJITSU_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@Slice_ACT_QP_Offsets_A_Qualcomm_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@TSCTX_10bit_I_RExt_SHARP_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@TSCTX_10bit_RExt_SHARP_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@TSCTX_12bit_I_RExt_SHARP_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@TSCTX_12bit_RExt_SHARP_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@TSCTX_8bit_I_RExt_SHARP_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@TSCTX_8bit_RExt_SHARP_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@TSUNEQBD_A_MAIN10_Technicolor_2,Fail
GStreamer-H.265-VAAPI-Gst1.0@VUI_A_QUALCOMM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@VUI_B_QUALCOMM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@VUI_C_QUALCOMM_1,Crash
GStreamer-H.265-VAAPI-Gst1.0@WAVETILES_RExt_Sony_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@WPP_AND_TILE_10Bit422Test_HIGH_TP_444_10BIT_RExt_Apple_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@WPP_AND_TILE_AND_CABAC_BYPASS_ALIGN_0_HIGH_TP_444_14BIT_RExt_Apple_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@WPP_AND_TILE_AND_CABAC_BYPASS_ALIGN_1_HIGH_TP_444_14BIT_RExt_Apple_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@WPP_AND_TILE_AND_CABAC_EXT_PREC_1_HIGH_TP_444_14BIT_RExt_Apple_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@WPP_AND_TILE_HIGH_TP_444_8BIT_RExt_Apple_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@WPP_HIGH_TP_444_8BIT_RExt_Apple_2,Crash
GStreamer-H.265-VAAPI-Gst1.0@Zero_and_One_Palette_Size_A_Canon_2,Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
GStreamer-VP9-VAAPI-Gst1.0@vp90-2-22-svc_1280x720_3.ivf,Fail
[email protected],Crash
[email protected],Crash
[email protected],Fail
[email protected],Crash
[email protected],Crash
[email protected],Crash
[email protected],Crash
src/amd/ci/radeonsi-raven-va-skips.txt
+5
View File
@@ -0,0 +1,5 @@
# Makes the GPU hang
GStreamer-H.265-VAAPI-Gst1.0@SLPPLP_A_VIDYO_2
GStreamer-H.265-VAAPI-Gst1.0@TSCL_A_VIDYO_5
GStreamer-H.265-VAAPI-Gst1.0@TSCL_B_VIDYO_4
GStreamer-H.265-VAAPI-Gst1.0@VPSID_A_VIDYO_2
src/amd/ci/radeonsi-stoney-fails.txt
+152
View File
@@ -0,0 +1,152 @@
glx@glx-multi-window-single-context,Fail
glx@glx-swap-pixmap-bad,Fail
spec@!opengl 1.0@rasterpos,Fail
spec@!opengl 1.0@rasterpos@glsl_vs_gs_linked,Fail
spec@!opengl 1.0@rasterpos@glsl_vs_tes_linked,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_R3_G3_B2- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGB10- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGB10_A2- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGB12- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGB16- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGB4- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGB5- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGB5_A1- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGB8- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGBA12- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGBA16- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGBA2- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGBA4- swizzled- border color only,Fail
spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGBA8- swizzled- border color only,Fail
spec@!opengl [email protected] cull-back pv-first,Fail
spec@!opengl [email protected] cull-front pv-first,Fail
spec@!opengl [email protected] line cull-back pv-first,Fail
spec@!opengl [email protected] line cull-front pv-first,Fail
spec@!opengl [email protected] pv-first,Fail
spec@arb_es2_compatibility@texwrap formats bordercolor-swizzled,Fail
spec@arb_es2_compatibility@texwrap formats bordercolor-swizzled@GL_RGB565- swizzled- border color only,Fail
spec@arb_shading_language_packing@execution@built-in-functions@fs-packhalf2x16,Fail
spec@arb_shading_language_packing@execution@built-in-functions@vs-packhalf2x16,Fail
spec@arb_texture_compression@texwrap formats bordercolor-swizzled,Fail
spec@arb_texture_compression@texwrap formats bordercolor-swizzled@GL_COMPRESSED_RGB- swizzled- border color only,Fail
spec@arb_texture_compression@texwrap formats bordercolor-swizzled@GL_COMPRESSED_RGBA- swizzled- border color only,Fail
spec@arb_texture_compression_bptc@texwrap formats bordercolor-swizzled,Fail
spec@arb_texture_compression_bptc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_RGBA_BPTC_UNORM- swizzled- border color only,Fail
spec@arb_texture_compression_bptc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_RGB_BPTC_SIGNED_FLOAT- swizzled- border color only,Fail
spec@arb_texture_compression_bptc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_RGB_BPTC_UNSIGNED_FLOAT- swizzled- border color only,Fail
spec@arb_texture_compression_bptc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_SRGB_ALPHA_BPTC_UNORM- swizzled- border color only,Fail
spec@arb_texture_float@texwrap formats bordercolor-swizzled,Fail
spec@arb_texture_float@texwrap formats bordercolor-swizzled@GL_RGB16F- swizzled- border color only,Fail
spec@arb_texture_float@texwrap formats bordercolor-swizzled@GL_RGB32F- swizzled- border color only,Fail
spec@arb_texture_float@texwrap formats bordercolor-swizzled@GL_RGBA16F- swizzled- border color only,Fail
spec@arb_texture_float@texwrap formats bordercolor-swizzled@GL_RGBA32F- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats bordercolor-swizzled,Fail
spec@arb_texture_rg@texwrap formats bordercolor-swizzled@GL_R16- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats bordercolor-swizzled@GL_R8- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats bordercolor-swizzled@GL_RG16- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats bordercolor-swizzled@GL_RG8- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-float bordercolor-swizzled,Fail
spec@arb_texture_rg@texwrap formats-float bordercolor-swizzled@GL_R16F- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-float bordercolor-swizzled@GL_R32F- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-float bordercolor-swizzled@GL_RG16F- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-float bordercolor-swizzled@GL_RG32F- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_R16I- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_R16UI- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_R32I- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_R32UI- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_R8I- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_R8UI- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_RG16I- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_RG16UI- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_RG32I- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_RG32UI- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_RG8I- swizzled- border color only,Fail
spec@arb_texture_rg@texwrap formats-int bordercolor-swizzled@GL_RG8UI- swizzled- border color only,Fail
spec@arb_texture_rgb10_a2ui@texwrap formats bordercolor-swizzled,Fail
spec@arb_texture_rgb10_a2ui@texwrap formats bordercolor-swizzled@GL_RGB10_A2UI- swizzled- border color only,Fail
spec@egl 1.4@eglterminate then unbind context,Fail
spec@egl_chromium_sync_control@conformance,Fail
spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test,Fail
spec@egl_khr_surfaceless_context@viewport,Fail
spec@egl_mesa_configless_context@basic,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y210,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y212,Fail
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y216,Fail
spec@ext_packed_float@texwrap formats bordercolor-swizzled,Fail
spec@ext_packed_float@texwrap formats bordercolor-swizzled@GL_R11F_G11F_B10F- swizzled- border color only,Fail
spec@ext_texture_compression_rgtc@texwrap formats bordercolor-swizzled,Fail
spec@ext_texture_compression_rgtc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_RED_RGTC1- swizzled- border color only,Fail
spec@ext_texture_compression_rgtc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_RG_RGTC2- swizzled- border color only,Fail
spec@ext_texture_compression_rgtc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_SIGNED_RED_RGTC1- swizzled- border color only,Fail
spec@ext_texture_compression_rgtc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_SIGNED_RG_RGTC2- swizzled- border color only,Fail
spec@ext_texture_compression_s3tc@texwrap formats bordercolor-swizzled,Fail
spec@ext_texture_compression_s3tc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_RGBA_S3TC_DXT1_EXT- swizzled- border color only,Fail
spec@ext_texture_compression_s3tc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_RGBA_S3TC_DXT3_EXT- swizzled- border color only,Fail
spec@ext_texture_compression_s3tc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_RGBA_S3TC_DXT5_EXT- swizzled- border color only,Fail
spec@ext_texture_compression_s3tc@texwrap formats bordercolor-swizzled@GL_COMPRESSED_RGB_S3TC_DXT1_EXT- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGB16I- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGB16UI- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGB32I- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGB32UI- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGB8I- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGB8UI- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGBA16I- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGBA16UI- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGBA32I- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGBA32UI- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGBA8I- swizzled- border color only,Fail
spec@ext_texture_integer@texwrap formats bordercolor-swizzled@GL_RGBA8UI- swizzled- border color only,Fail
spec@ext_texture_shared_exponent@texwrap formats bordercolor-swizzled,Fail
spec@ext_texture_shared_exponent@texwrap formats bordercolor-swizzled@GL_RGB9_E5- swizzled- border color only,Fail
spec@ext_texture_snorm@texwrap formats bordercolor-swizzled,Fail
spec@ext_texture_snorm@texwrap formats bordercolor-swizzled@GL_R16_SNORM- swizzled- border color only,Fail
spec@ext_texture_snorm@texwrap formats bordercolor-swizzled@GL_R8_SNORM- swizzled- border color only,Fail
spec@ext_texture_snorm@texwrap formats bordercolor-swizzled@GL_RG16_SNORM- swizzled- border color only,Fail
spec@ext_texture_snorm@texwrap formats bordercolor-swizzled@GL_RG8_SNORM- swizzled- border color only,Fail
spec@ext_texture_snorm@texwrap formats bordercolor-swizzled@GL_RGB16_SNORM- swizzled- border color only,Fail
spec@ext_texture_snorm@texwrap formats bordercolor-swizzled@GL_RGB8_SNORM- swizzled- border color only,Fail
spec@ext_texture_snorm@texwrap formats bordercolor-swizzled@GL_RGBA16_SNORM- swizzled- border color only,Fail
spec@ext_texture_snorm@texwrap formats bordercolor-swizzled@GL_RGBA8_SNORM- swizzled- border color only,Fail
spec@ext_texture_srgb@texwrap formats bordercolor-swizzled,Fail
spec@ext_texture_srgb@texwrap formats bordercolor-swizzled@GL_SRGB8- swizzled- border color only,Fail
spec@ext_texture_srgb@texwrap formats bordercolor-swizzled@GL_SRGB8_ALPHA8- swizzled- border color only,Fail
spec@ext_texture_srgb@texwrap formats-s3tc bordercolor-swizzled,Fail
spec@ext_texture_srgb@texwrap formats-s3tc bordercolor-swizzled@GL_COMPRESSED_SRGB- swizzled- border color only,Fail
spec@ext_texture_srgb@texwrap formats-s3tc bordercolor-swizzled@GL_COMPRESSED_SRGB_ALPHA- swizzled- border color only,Fail
spec@ext_texture_srgb@texwrap formats-s3tc bordercolor-swizzled@GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT- swizzled- border color only,Fail
spec@ext_texture_srgb@texwrap formats-s3tc bordercolor-swizzled@GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT- swizzled- border color only,Fail
spec@ext_texture_srgb@texwrap formats-s3tc bordercolor-swizzled@GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT- swizzled- border color only,Fail
spec@ext_texture_srgb@texwrap formats-s3tc bordercolor-swizzled@GL_COMPRESSED_SRGB_S3TC_DXT1_EXT- swizzled- border color only,Fail
[email protected]@execution@geometry@tri-strip-ordering-with-prim-restart gl_triangle_strip_adjacency ffs,Fail
[email protected]@execution@geometry@tri-strip-ordering-with-prim-restart gl_triangle_strip_adjacency other,Fail
[email protected]@execution@built-in-functions@fs-packhalf2x16,Fail
[email protected]@execution@built-in-functions@vs-packhalf2x16,Fail
spec@khr_texture_compression_astc@miptree-gl srgb-fp,Fail
spec@khr_texture_compression_astc@miptree-gl srgb-fp@sRGB decode full precision,Fail
spec@khr_texture_compression_astc@miptree-gles srgb-fp,Fail
spec@khr_texture_compression_astc@miptree-gles srgb-fp@sRGB decode full precision,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gl srgb-fp,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gl srgb-fp@sRGB decode full precision,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp@sRGB decode full precision,Fail
spec@!opengl 1.1@line-smooth-stipple,Fail
# since transition XORG -> WESTON
glx@glx_arb_sync_control@waitformsc,Fail
# remove these after updating piglit:
spec@arb_fragment_layer_viewport@layer-gs-writes-out-of-range,Fail
# glcts update
KHR-GLES3.clip_distance.coverage,Fail
KHR-GLES3.cull_distance.functional,Fail
# uprev Piglit in Mesa
spec@ext_external_objects@vk-ping-pong-multi-sem,Fail
spec@ext_external_objects@vk-ping-pong-single-sem,Crash
# Since switching to test-gl container based rootfs
spec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,Fail
src/amd/ci/radeonsi-stoney-flakes.txt
+138
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@@ -0,0 +1,138 @@
spec@arb_shader_image_load_store@host-mem-barrier
spec@arb_shader_image_load_store@host-mem-barrier@Vertex array/RaW/one bit barrier test/64x64
# 2022-11-23 The following two case are xfails, but sometimes pass.
spec@egl_chromium_sync_control@conformance
spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test
# Flaky with a Fail result since the piglit fix made it stop crashing.
glx@glx-make-current
# uprev Piglit in Mesa
dEQP-GLES3.functional.occlusion_query.scissor_depth_write_stencil_write_stencil_clear
glx@glx-multithread-texture
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-refcount-multithread
dEQP-GLES2.functional.fbo.render.resize.rbo_bgra_stencil_index8
dEQP-GLES3.functional.fbo.render.recreate_color.tex2d_rg8ui_depth_stencil_rbo_depth24_stencil8
dEQP-GLES2.functional.texture.mipmap.2d.generate.rgba8888_non_square_fastest
dEQP-GLES3.functional.texture.filtering.3d.formats.r11f_g11f_b10f_nearest_mipmap_nearest
dEQP-GLES3.functional.texture.units.4_units.only_3d.4
dEQP-GLES3.functional.texture.vertex.3d.wrap.repeat_clamp_mirror
dEQP-GLES3.functional.shaders.derivate.dfdx.texture.msaa4.vec3_highp
dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_12x12_rgba.srgb8_alpha8_astc_12x12_khr_srgb8_alpha8_astc_12x12_khr.texture2d_to_cubemap
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_srgb8_alpha8_etc2_eac.texture2d_array_to_cubemap
dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_8x8_khr_rgba32f.texture3d_to_texture2d
dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.rg32i_r11_eac.cubemap_to_texture2d
dEQP-GLES31.functional.copy_image.non_compressed.viewclass_64_bits.rg32f_rgba16ui.texture3d_to_renderbuffer
dEQP-GLES31.functional.copy_image.non_compressed.viewclass_96_bits.rgb32f_rgb32i.texture3d_to_texture2d
dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_sample.at_sample_id.multisample_rbo_2
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.tessellation_control.sampler2darrayshadow
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.dynamically_uniform.fragment.samplercubeshadow
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.uniform.fragment.sampler2dshadow
glx@glx-visuals-stencil
shaders@glsl-kwin-blur-2
spec@!opengl [email protected]
spec@!opengl [email protected]
spec@!opengl 1.1@draw-copypixels-sync
spec@!opengl 1.1@draw-pixels
spec@!opengl 1.2@texture-packed-formats
spec@!opengl 3.2@layered-rendering@clear-color-all-types 3d mipmapped
spec@amd_shader_trinary_minmax@execution@built-in-functions@fs-mid3-vec4-vec4-vec4
spec@arb_clear_buffer_object@arb_clear_buffer_object-formats
spec@arb_clear_texture@arb_clear_texture-depth
spec@arb_copy_image@arb_copy_image-formats --samples=2
spec@arb_draw_indirect@arb_draw_indirect-transform-feedback
spec@arb_framebuffer_srgb@blit renderbuffer linear single_sampled enabled render
spec@arb_framebuffer_srgb@blit renderbuffer linear_to_srgb upsample disabled render
spec@arb_framebuffer_srgb@blit renderbuffer srgb scaled disabled clear
spec@arb_framebuffer_srgb@blit texture linear upsample enabled clear
spec@arb_framebuffer_srgb@blit texture linear_to_srgb scaled enabled render
spec@arb_framebuffer_srgb@blit texture linear_to_srgb single_sampled disabled render
spec@arb_framebuffer_srgb@blit texture srgb single_sampled enabled render
spec@arb_framebuffer_srgb@blit texture srgb_to_linear single_sampled enabled render
spec@arb_gpu_shader5@execution@fs-underflow-fma-compare-zero
spec@arb_gpu_shader5@texturegatheroffset@vs-rg-1-int-2darray-const
spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-int-2drect-const
spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-unorm-2d
spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-1-float-2d
spec@arb_gpu_shader_int64@execution@built-in-functions@fs-op-sub-uint64_t-uint64_t
spec@arb_sample_shading@arb_sample_shading-builtin-gl-sample-mask-mrt-alpha-to-coverage
spec@arb_sample_shading@samplemask 6 all
spec@arb_shader_texture_lod@execution@tex-miplevel-selection \*gradarb 3d
spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-assign-bitxor-uint-uint
spec@arb_texture_float@multisample-formats 2 gl_arb_texture_float
spec@arb_texture_gather@texturegatheroffset@vs-r-none-int-2d
spec@arb_texture_gather@texturegatheroffset@vs-r-none-uint-2d
spec@arb_texture_gather@texturegatheroffset@vs-r-one-float-2d
spec@arb_texture_gather@texturegatheroffset@vs-r-red-uint-2darray
spec@arb_texture_gather@texturegatheroffset@vs-rgba-alpha-int-2d
spec@arb_texture_gather@texturegatheroffset@vs-rgba-alpha-uint-2d
spec@arb_texture_gather@texturegatheroffset@vs-rgba-none-float-2darray
spec@arb_texture_gather@texturegatheroffset@vs-rgba-one-unorm-2d
spec@arb_texture_multisample@arb_texture_multisample-sample-mask-execution
spec@arb_texture_rg@multisample-formats 2 gl_arb_texture_rg-int
spec@arb_texture_rg@multisample-formats 6 gl_arb_texture_rg-float
spec@arb_texture_rg@multisample-formats 8 gl_arb_texture_rg
spec@arb_texture_view@cubemap-view
spec@arb_texture_view@rendering-r32ui
spec@arb_timer_query@timestamp-get
spec@arb_transform_feedback2@change objects while paused
spec@arb_vertex_buffer_object@vbo-subdata-many drawarrays
spec@arb_vertex_buffer_object@vbo-subdata-many drawelements
spec@arb_vertex_buffer_object@vbo-subdata-many drawrangeelements
spec@ext_external_objects@vk-ping-pong-multi-sem
spec@ext_external_objects@vk-ping-pong-single-sem
spec@ext_external_objects@vk-semaphores
spec@ext_framebuffer_blit@fbo-blit-check-limits
spec@ext_framebuffer_multisample@accuracy 16 stencil_resolve
spec@ext_framebuffer_multisample@accuracy 2 depth_resolve small depthstencil
spec@ext_framebuffer_multisample@accuracy 4 depth_draw small depthstencil
spec@ext_framebuffer_multisample@accuracy 4 depth_resolve small depthstencil
spec@ext_framebuffer_multisample@accuracy 4 srgb small depthstencil
spec@ext_framebuffer_multisample@accuracy all_samples depth_draw depthstencil
spec@ext_framebuffer_multisample@accuracy all_samples depth_draw small depthstencil
spec@ext_framebuffer_multisample@accuracy all_samples depth_resolve small depthstencil
spec@ext_framebuffer_multisample@accuracy all_samples stencil_draw small depthstencil
spec@ext_framebuffer_multisample@accuracy all_samples stencil_resolve small depthstencil
spec@ext_framebuffer_multisample@draw-buffers-alpha-to-coverage 8
spec@ext_framebuffer_multisample@interpolation 2 non-centroid-deriv-disabled
spec@ext_framebuffer_multisample@interpolation 6 non-centroid-deriv-disabled
spec@ext_framebuffer_multisample@multisample-blit 8 depth
spec@ext_framebuffer_object@fbo-drawbuffers-blend-add
spec@ext_framebuffer_object@fbo-generatemipmap-nonsquare
spec@ext_framebuffer_object@getteximage-formats init-by-rendering
spec@ext_texture_snorm@multisample-formats 4 gl_ext_texture_snorm
spec@ext_texture_srgb@multisample-formats 4 gl_ext_texture_srgb
spec@ext_transform_feedback@immediate-reuse
[email protected]@execution@built-in-functions@vs-transpose-mat2x4
[email protected]@execution@tex-miplevel-selection gl2:texture\(\) 1d
[email protected]@execution@variable-indexing@vs-varying-mat2-row-rd
[email protected]@execution@fs-execution-ordering
[email protected]@execution@tex-miplevel-selection texture\(\) 1darrayshadow
[email protected]@execution@tex-miplevel-selection texture\(\) 2d
[email protected]@execution@tex-miplevel-selection texture\(\) 2darrayshadow
[email protected]@execution@tex-miplevel-selection texturegrad 2darrayshadow
[email protected]@execution@tex-miplevel-selection texturegradoffset 2d
[email protected]@execution@tex-miplevel-selection texturegradoffset 3d
[email protected]@execution@tex-miplevel-selection texturelodoffset 1d
[email protected]@execution@tex-miplevel-selection texturelodoffset 3d
[email protected]@execution@tex-miplevel-selection textureoffset 1darray
[email protected]@execution@tex-miplevel-selection textureoffset 2d
[email protected]@execution@tex-miplevel-selection textureoffset 3d
[email protected]@execution@tex-miplevel-selection textureoffset\(bias\) 1d
[email protected]@execution@tex-miplevel-selection textureproj\(bias\) 1d_projvec4
[email protected]@execution@tex-miplevel-selection textureprojgradoffset 1d
[email protected]@execution@tex-miplevel-selection textureprojlodoffset 2d_projvec4
[email protected]@execution@texelfetch fs sampler3d 98x1x9-98x129x9
[email protected]@execution@texturesize@fs-texturesize-sampler2darrayshadow
[email protected]@execution@built-in-functions@gs-mix-dvec2-dvec2-bvec2
[email protected]@execution@built-in-functions@cs-op-bitxor-uvec3-uint
spec@nv_copy_image@nv_copy_image-formats --samples=2
spec@nv_copy_image@nv_copy_image-formats --samples=4
spec@nv_copy_image@nv_copy_image-formats --samples=8
spec@nv_copy_image@nv_copy_image-simple --tex-to-tex
src/amd/ci/radeonsi-stoney-skips.txt
+54
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@@ -0,0 +1,54 @@
# From https://github.com/marekolsak/marek-build/blob/master/run-piglit.sh#L36
spec@!opengl [email protected]
spec@!opengl 1.1@max-texture-size
spec@!opengl 1.1@max-texture-size-level
spec@!opengl 1.2@tex3d-maxsize
spec@arb_texture_buffer_object@max-size
spec@ext_framebuffer_object@fbo-maxsize
# times out
spec@arb_compute_shader@local-id-explosion
# most of these just allocate way too much memory
spec@arb_shader_image_load_store@max-size
spec@arb_shader_storage_buffer_object@max-ssbo-size@fs
spec@arb_shader_storage_buffer_object@max-ssbo-size@fsexceed
spec@arb_shader_storage_buffer_object@max-ssbo-size@vs
spec@arb_shader_storage_buffer_object@max-ssbo-size@vsexceed
spec@arb_texture_buffer_object@texture-buffer-size-clamp
spec@arb_texture_buffer_object@texture-buffer-size-clamp@rgba8ui_texture_buffer_size_via_sampler
spec@arb_texture_buffer_object@texture-buffer-size-clamp@rgba8ui_texture_buffer_size_via_image
spec@arb_uniform_buffer_object@maxuniformblocksize@fs
spec@arb_uniform_buffer_object@maxuniformblocksize@fsexceed
spec@arb_uniform_buffer_object@maxuniformblocksize@vs
spec@arb_uniform_buffer_object@maxuniformblocksize@vsexceed
spec@ext_transform_feedback@max-varyings
# these are timeout-prone
spec@ext_external_objects@memory-object-api-errors
spec@ext_external_objects@semaphore-api-errors
spec@ext_external_objects@vk-buf-exchange
spec@ext_external_objects@vk-depth-display
spec@ext_external_objects@vk-image-display
spec@ext_external_objects@vk-image-display-overwrite
spec@ext_external_objects@vk-image-overwrite
spec@ext_external_objects@vk-pix-buf-update-errors
spec@ext_external_objects@vk-vert-buf-reuse
spec@ext_external_objects@vk-vert-buf-update-errors
spec@ext_external_objects_fd@memory-object-api-errors
spec@ext_external_objects_fd@semaphore-api-errors
[email protected]@execution@texelfetch fs sampler2d 1x281-501x281
# most GLX tests are pretty broken
glx@glx-swap-event_async
glx@glx-swap-event_interval
glx@glx-copy-sub-buffer
glx@glx-copy-sub-buffer samples=6
glx@glx-swap-event_event
glx@glx-buffer-age
glx@glx-buffer-age vblank_mode=0
glx@glx-multithread-buffer
# Debian 12 (bookworm) uprev
dEQP-VK.binding_model.descriptor_buffer.multiple.graphics_frag_buffers32_sets1
src/amd/ci/radeonsi-vangogh-fails.txt
+412
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@@ -0,0 +1,412 @@
spec@!opengl 1.0@rasterpos,Fail
spec@!opengl 1.0@rasterpos@glsl_vs_gs_linked,Fail
spec@!opengl 1.0@rasterpos@glsl_vs_tes_linked,Fail
spec@!opengl 1.1@line-smooth-stipple,Fail
spec@arb_fragment_layer_viewport@layer-gs-writes-out-of-range,Fail
spec@arb_program_interface_query@arb_program_interface_query-getprogramresourceindex,Fail
spec@arb_program_interface_query@arb_program_interface_query-getprogramresourceindex@'vs_input2[1][0]' on GL_PROGRAM_INPUT,Fail
spec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,Fail
spec@arb_shading_language_packing@execution@built-in-functions@fs-packhalf2x16,Fail
spec@arb_shading_language_packing@execution@built-in-functions@vs-packhalf2x16,Fail
spec@arb_tessellation_shader@arb_tessellation_shader-tes-gs-max-output -small -scan 1 50,Fail
spec@egl 1.4@eglterminate then unbind context,Fail
spec@egl_khr_surfaceless_context@viewport,Fail
spec@ext_external_objects@vk-image-display,Crash
spec@ext_external_objects@vk-semaphores,Crash
spec@ext_external_objects@vk-semaphores-2,Crash
[email protected]@execution@built-in-functions@fs-packhalf2x16,Fail
[email protected]@execution@built-in-functions@vs-packhalf2x16,Fail
spec@khr_texture_compression_astc@miptree-gles srgb-fp,Fail
spec@khr_texture_compression_astc@miptree-gles srgb-fp@sRGB decode full precision,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp,Fail
spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp@sRGB decode full precision,Fail
# glcts update
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r8i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgb10_a2,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r8i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg32f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r32ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgb565,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r16ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r32ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r32f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgb10_a2,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg16i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba32ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg8i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r8i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg32ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgb10_a2ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r32f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r32ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg32f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgb10_a2,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r16i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_depth_component16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg32ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgb565,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg16ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgb10_a2,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r16i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_depth_component16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg16f,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rg16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg32i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg8_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rgba16ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgb9_e5,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg16,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_r32ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg8,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg16ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgb10_a2ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r16ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_buffer_rgba16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_rg8i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rgba16_snorm,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r16f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgb9_e5,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_array_r8_snorm,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_rg32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg8i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg16,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r16f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_array_r16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rgba8,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_rg16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_r32i,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_r32f,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rg8i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_rgba32f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_r16i,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r16ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_rectangle_rg16,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r8,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_r11f_g11f_b10f,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r8ui,Fail
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor_texture_1d_array_rg16i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r16_snorm,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_rg32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_3d_rg8ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_cube_map_r32i,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_multisample_r32ui,Fail
KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase_texture_1d_array_r32ui,Fail
KHR-GL46.sparse_texture2_tests.UncommittedRegionsAccess_texture_2d_array_rg16f,Fail
src/amd/ci/radeonsi-vangogh-flakes.txt
+38
View File
@@ -0,0 +1,38 @@
dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_ops.decr_decr_wrap_incr_wrap
dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.r32f_r32f.cubemap_to_texture2d_array
dEQP-GLES31.functional.geometry_shading.basic.output_256
dEQP-GLES31.functional.geometry_shading.basic.output_max
KHR-GLES31.core.explicit_uniform_location.uniform-loc-mix-with-implicit-max-array
KHR-GLES31.core.shader_image_load_store.basic-allFormats-store-fs
KHR-GLES31.core.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_MaxPatchVertices_Position_PointSize
KHR-GLES31.core.tessellation_shader.vertex.vertex_ordering
KHR-GL46.pipeline_statistics_query_tests_ARB.functional_primitives_vertices_submitted_and_clipping_input_output_primitives
KHR-GL46.shader_image_load_store.basic-allTargets-atomic
KHR-GL46.tessellation_shader.vertex.vertex_ordering
KHR-GL46.texture_swizzle.functional
KHR-Single-GL46.arrays_of_arrays_gl.ConstructorsAndUnsizedDeclConstructors1
KHR-Single-GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive
spec@arb_compute_shader@local-id-explosion
spec@arb_tessellation_shader@arb_tessellation_shader-tes-gs-max-output -small -scan 1 50
spec@arb_texture_multisample@arb_texture_multisample-dsa-texelfetch
spec@arb_texture_multisample@arb_texture_multisample-dsa-texelfetch@Texture type: GL_RGB9_E5
spec@arb_timer_query@timestamp-get
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-refcount-multithread
spec@!opengl es [email protected]
KHR-GL46.pipeline_statistics_query_tests_ARB.functional_primitives_vertices_submitted_and_clipping_input_output_primitives
dEQP-GLES3.functional.occlusion_query.conservative_depth_write
dEQP-GLES3.functional.occlusion_query.conservative_depth_write_depth_clear_stencil_write_stencil_clear
dEQP-GLES3.functional.occlusion_query.conservative_scissor
dEQP-GLES3.functional.occlusion_query.scissor_stencil_clear
spec@!opengl es [email protected]
spec@arb_timer_query@timestamp-get
dEQP-GLES3.functional.occlusion_query.scissor_depth_write_stencil_write
dEQP-GLES3.functional.occlusion_query.conservative_scissor_depth_clear_stencil_clear
KHR-Single-GL46.arrays_of_arrays_gl.AtomicDeclaration
src/amd/ci/radeonsi-vangogh-skips.txt
+10
View File
@@ -0,0 +1,10 @@
# GLX doesn't work in CI
glx@
# these tests take longer than 60sec
KHR-GLES31.core.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_MaxPatchVertices_Position_PointSize
KHR-GL46.copy_image.functional
KHR-GL46.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_MaxPatchVertices_Position_PointSize
KHR-GL46.texture_swizzle.smoke
KHR-Single-GL46.arrays_of_arrays_gl.AtomicUsage
KHR-Single-GL46.arrays_of_arrays_gl.AtomicDeclaration
src/amd/ci/radv-cezanne-fails.txt
+22
View File
@@ -0,0 +1,22 @@
# RADV bug
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm.general.32x32x1_cq_regions,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.general.32x32x1_cq_regions,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.general.32x32x2_cq_regions_img2img,Fail
# VKCTS test bug (invalid behavior)
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.general.32x32x2_cq_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.general.32x32x2_cq_regions_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.transfer_dst_optimal.32x32x2_cq_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.transfer_dst_optimal.32x32x2_cq_regions_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat.general.32x32x2_cq_regions_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat_s8_uint.transfer_dst_optimal.32x32x2_cq_regions_img2img_msaa,Fail
# CTS is missing -frounding-math: https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/6580
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.scalar.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.scalar.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec2.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec2.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec3.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec3.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec4.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec4.rte.denorm_flush.float_controls,Fail
src/amd/ci/radv-cezanne-flakes.txt
View File
Whitespace-only changes.
src/amd/ci/radv-cezanne-skips.txt
+4
View File
@@ -0,0 +1,4 @@
# Initialization leaks, causing the ASan of this job to mark everything failed.
# Needs to get fixed.
dEQP-VK.wsi.*
dEQP-VK.image.swapchain_mutable.*
src/amd/ci/radv-fails.txt
+22
View File
@@ -0,0 +1,22 @@
dEQP-VK.info.device_extension_dependencies,Fail
# VKCTS bug: https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/6446
dEQP-VK.binding_model.descriptor_heap.basic.fragment.input_attachment,Fail
# CTS is missing -frounding-math: https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/6580
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.scalar.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.scalar.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.scalar.rte.denorm_none.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.scalar.rte.denorm_none.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec2.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec2.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec2.rte.denorm_none.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec2.rte.denorm_none.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec3.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec3.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec3.rte.denorm_none.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec3.rte.denorm_none.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec4.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec4.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec4.rte.denorm_none.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec4.rte.denorm_none.float_controls,Fail
src/amd/ci/radv-gfx1201-fails.txt
+499
View File
@@ -0,0 +1,499 @@
dEQP-VK.wsi.direct.colorspace.basic,Fail
dEQP-VK.wsi.direct.colorspace.hdr,Fail
dEQP-VK.wsi.direct_drm.colorspace.basic,Fail
dEQP-VK.wsi.direct_drm.colorspace.hdr,Fail
# Fluster
GStreamer-H.264-Vulkan-Gst1.0@CABREF3_Sand_D,Fail
GStreamer-H.264-Vulkan-Gst1.0@CAFI1_SVA_C,Fail
GStreamer-H.264-Vulkan-Gst1.0@CAPA1_TOSHIBA_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@CAPAMA3_Sand_F,Fail
GStreamer-H.264-Vulkan-Gst1.0@CVFC1_Sony_C,Fail
GStreamer-H.264-Vulkan-Gst1.0@CVFI1_Sony_D,Fail
GStreamer-H.264-Vulkan-Gst1.0@CVFI2_SVA_C,Fail
GStreamer-H.264-Vulkan-Gst1.0@CVFI2_Sony_H,Fail
GStreamer-H.264-Vulkan-Gst1.0@CVMP_MOT_FLD_L30_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@CVMP_MOT_FRM_L31_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@CVNLFI1_Sony_C,Fail
GStreamer-H.264-Vulkan-Gst1.0@CVNLFI2_Sony_H,Fail
GStreamer-H.264-Vulkan-Gst1.0@CVPA1_TOSHIBA_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@FM1_BT_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@FM1_FT_E,Fail
GStreamer-H.264-Vulkan-Gst1.0@FM2_SVA_C,Crash
GStreamer-H.264-Vulkan-Gst1.0@FREH10-1,Crash
GStreamer-H.264-Vulkan-Gst1.0@FREH10-2,Crash
GStreamer-H.264-Vulkan-Gst1.0@FREXT1_TANDBERG_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@FREXT2_TANDBERG_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@FREXT3_TANDBERG_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@FRExt1_Panasonic_D,Fail
GStreamer-H.264-Vulkan-Gst1.0@FRExt2_Panasonic_C,Fail
GStreamer-H.264-Vulkan-Gst1.0@FRExt3_Panasonic_E,Fail
GStreamer-H.264-Vulkan-Gst1.0@FRExt4_Panasonic_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@FRExt_MMCO4_Sony_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@HCHP3_HHI_A,Fail
GStreamer-H.264-Vulkan-Gst1.0@HPCAFLNL_BRCM_C,Fail
GStreamer-H.264-Vulkan-Gst1.0@HPCAFL_BRCM_C,Fail
GStreamer-H.264-Vulkan-Gst1.0@HPCAMAPALQ_BRCM_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@HPCAMOLQ_BRCM_B,Crash
GStreamer-H.264-Vulkan-Gst1.0@HPCAQ2LQ_BRCM_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@HPCVFLNL_BRCM_A,Fail
GStreamer-H.264-Vulkan-Gst1.0@HPCVFL_BRCM_A,Fail
GStreamer-H.264-Vulkan-Gst1.0@HPCVMOLQ_BRCM_B,Crash
GStreamer-H.264-Vulkan-Gst1.0@HVLCFI0_Sony_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR10_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR11_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR12_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR13_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR14_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR15_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR1_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR2_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR3_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR4_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR6_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR7_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR8_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FR9_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FREXT16_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FREXT17_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FREXT18_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@Hi422FREXT19_SONY_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@MR4_TANDBERG_C,Fail
GStreamer-H.264-Vulkan-Gst1.0@MR5_TANDBERG_C,Fail
GStreamer-H.264-Vulkan-Gst1.0@MR6_BT_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@MR7_BT_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@MR8_BT_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@MR9_BT_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@MVCDS-4,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCDS-5,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCDS-6,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCDS1,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCDS2,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCDS3,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCICT-1,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCICT-2,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCNV-2,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCNV-3,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCNV1,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCNV4,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCRP_1,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCRP_2,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCRP_3,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCRP_4,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCRP_5,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCRP_6,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCSPS-1,Crash
GStreamer-H.264-Vulkan-Gst1.0@MVCSPS-2,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPCV444I1_2008,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPCV444I2_2008,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPCV444I3_2008,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPCV444I4_Mitsubishi_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPCV444I5_Mitsubishi_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPCV444I6_Mitsubishi_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPCV444I7_SejongUniv_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH10I1_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH10I2_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH10I3_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH10I4_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH10I5_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH10I6_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH10I7_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH422I1_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH422I2_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH422I3_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH422I4_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH422I5_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH422I6_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH422I7_Panasonic_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444I1_2008,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444I2_2008,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444I3_2008,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444I4_Mitsubishi_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444I5_Mitsubishi_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444I6_Mitsubishi_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444I7_SejongUniv_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444P10_SejongUniv_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444P1_2008,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444P2_2008,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444P3_2008,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444P4_2008,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444P5_2008,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444P6_Mitsubishi_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444P7_Mitsubishi_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444P8_Mitsubishi_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@PPH444P9_Mitsubishi_A,Crash
GStreamer-H.264-Vulkan-Gst1.0@SP1_BT_A,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBC-1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBCT-1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-1-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-1-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-2-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-2-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-3-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-3-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-2-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-2-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-3-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-3-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-4-r1-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-4-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-4-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-5-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-5-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-5-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBM-5-L3,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-2-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-2-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-2-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-3-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-3-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-3-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-10-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-10-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-11-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-11-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-12-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-12-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-13-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-13-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-13-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-2-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-3-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-3-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-4-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-4-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-5-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-5-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-6-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-6-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-7-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-7-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-8-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-8-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-9-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-9-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBS-1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBS-2-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBS-2-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBS-3-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBS-4-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBS-5-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBS-6-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBS-6-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBS-7-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBS-8-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-10-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-10-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-11-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-11-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-12-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-12-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-13-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-13-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-14-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-14-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-14-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-15-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-15-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-15-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-16-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-16-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-16-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-17-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-17-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-17-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-18-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-18-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-18-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-19-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-2-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-2-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-20-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-3-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-3-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-4-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-4-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-5-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-5-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-6-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-6-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-7-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-7-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-8-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-8-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-9-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCBST-9-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBSTC-1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCBSTC-1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L3,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L4,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L5,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L6,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L7,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHICS-1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHICS-1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHICS-1-L3,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-2-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-2-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-3-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-3-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHM-1-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHM-1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHM-1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHM-1-L3,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHM-2-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHM-2-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHM-3-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHM-3-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHM-4-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHM-4-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHM-4-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L3,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L4,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L5,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-2-r1-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-2-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-2-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHS-1-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHS-2-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHST-1-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCHST-1-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHST-1-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHST-2-r1-L0,Fail
GStreamer-H.264-Vulkan-Gst1.0@SVCHST-2-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHST-2-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHST-3-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHST-4-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHSTC-1-r1-L0,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHSTC-1-r1-L1,Crash
GStreamer-H.264-Vulkan-Gst1.0@SVCHSTC-1-r1-L2,Crash
GStreamer-H.264-Vulkan-Gst1.0@Sharp_MP_Field_1_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@Sharp_MP_Field_2_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@Sharp_MP_Field_3_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@Sharp_MP_PAFF_1r2,Fail
GStreamer-H.264-Vulkan-Gst1.0@Sharp_MP_PAFF_2r,Fail
GStreamer-H.264-Vulkan-Gst1.0@brcm_freh10,Fail
GStreamer-H.264-Vulkan-Gst1.0@brcm_freh11,Fail
GStreamer-H.264-Vulkan-Gst1.0@brcm_freh4,Fail
GStreamer-H.264-Vulkan-Gst1.0@brcm_freh6,Fail
GStreamer-H.264-Vulkan-Gst1.0@cabac_mot_fld0_full,Fail
GStreamer-H.264-Vulkan-Gst1.0@cabac_mot_picaff0_full,Fail
GStreamer-H.264-Vulkan-Gst1.0@cavlc_mot_fld0_full_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@cavlc_mot_picaff0_full_B,Fail
GStreamer-H.264-Vulkan-Gst1.0@freh1_b,Fail
GStreamer-H.264-Vulkan-Gst1.0@freh2_b,Fail
GStreamer-H.264-Vulkan-Gst1.0@freh7_b,Fail
GStreamer-H.264-Vulkan-Gst1.0@sp2_bt_b,Fail
GStreamer-H.265-Vulkan-Gst1.0@3DHC_C_A_HHI_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_C_B_HHI_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_C_C_Sharp_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_A_HHI_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_B_HHI_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_C_RWTH_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_D_RWTH_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_E_MediaTek_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_F_MediaTek_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_G_Hisilicon_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_H_Hisilicon_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_D2_A_Samsung_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_D2_B_LGE_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_DT_A_MediaTek_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_DT_B_NTT_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_DT_C_Hisilicon_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_DT_D_NTT_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_TD_A_Qualcomm_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_TD_B_MediaTek_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_TD_C_MediaTek_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_TD_D_HHI_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_TD_E_HHI_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_T_A_Qualcomm_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_T_B_MediaTek_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_T_C_Sharp_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_T_D_Sharp_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@3DHC_T_E_HHI_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@ADAPTRES_A_ERICSSON_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@ADJUST_IPRED_ANGLE_A_RExt_Mitsubishi_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@ALPHA_A_BBC_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@Bipred_8by8_A_Qualcomm_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@Bitdepth_A_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@Bitdepth_B_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CCP_10bit_RExt_QCOM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CCP_12bit_RExt_QCOM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CCP_8bit_RExt_QCOM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CGS_A_TECHNICOLOR_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CGS_B_TECHNICOLOR_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CGS_C_TECHNICOLOR_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CGS_D_TECHNICOLOR_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CGS_E_TECHNICOLOR_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CGS_F_TECHNICOLOR_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CGS_G_TECHNICOLOR_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CGS_H_TECHNICOLOR_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CGS_I_TECHNICOLOR_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@CONFCROP_A_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@CONFCROP_B_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@CONFCROP_C_VIDYO_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@CONFWIN_A_Sony_1,Fail
GStreamer-H.265-Vulkan-Gst1.0@DBLK_A_MAIN10_VIXS_4,Crash
GStreamer-H.265-Vulkan-Gst1.0@DEPTH_A_NOKIA_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@DISFLAG_A_QUALCOMM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@DPB_A_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@DPB_B_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@DPB_Loop_Filters_A_MediaTek_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@Delta_QP_Chroma_QP_Offsets_A_Qualcomm_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_10BIT_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_12BIT_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_16BIT_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_8BIT_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_MAIN_444_16_INTRA_10BIT_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_MAIN_444_16_INTRA_12BIT_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_MAIN_444_16_INTRA_16BIT_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_MAIN_444_16_INTRA_8BIT_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@ExplicitRdpcm_A_BBC_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@ExplicitRdpcm_B_BBC_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_10b_420_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_10b_422_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_10b_444_RExt_Sony_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_12b_400_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_12b_420_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_12b_422_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_12b_444_RExt_Sony_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_16b_400_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_16b_444_RExt_Sony_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_16b_444_highThroughput_RExt_Sony_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_8b_400_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_8b_420_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@GENERAL_8b_444_RExt_Sony_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@HT_A_SCC_Apple_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@HT_B_SCC_Apple_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@HT_C_SCC_Apple_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@HYBRID_A_QUALCOMM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@IBF_Disabled_A_MediaTek_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@IBF_Disabled_B_MediaTek_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@INACTIVE_A_QCOM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@INBLD_A_NOKIA_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@INITQP_B_Main10_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@IPCM_A_RExt_NEC_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@IPCM_B_RExt_NEC,Crash
GStreamer-H.265-Vulkan-Gst1.0@IPRED_B_Nokia_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@LAYERID63_A_HHI_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@LAYERID_A_NOKIA_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@MAXTID_A_ETRI_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@MAXTID_B_ETRI_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@MAXTID_C_ETRI_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVD_A_IDCC_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVD_A_NOKIA_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_A_Qualcomm_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_B_Sharp_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_C_Sony_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_D_NTT_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_E_Qualcomm_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_F_Qualcomm_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_G_NTT_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_H_LGE_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_I_Nokia_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVRESIDC_A_MS_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVRESIDC_B_MS_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@MVRESIDC_C_MS_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@Main_422_10_A_RExt_Sony_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@Main_422_10_B_RExt_Sony_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@NONVUI_A_QUALCOMM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@NONVUI_B_QUALCOMM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@NONVUI_C_QUALCOMM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@OLS_A_NOKIA_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@OLS_B_NOKIA_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@OLS_C_NOKIA_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@PERSIST_RPARAM_A_RExt_Sony_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@PICSIZE_A_Bossen_1,Fail
GStreamer-H.265-Vulkan-Gst1.0@PICSIZE_B_Bossen_1,Fail
GStreamer-H.265-Vulkan-Gst1.0@POC_A_Ericsson_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@POC_B_Ericsson_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@PPI_A_InterDigital_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@PPI_B_InterDigital_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@PPSSLIST_A_Sony_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@PSEXT_A_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@QMATRIX_A_RExt_Sony_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@REFLAYER_A_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@REFLAYER_B_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@REFLAYER_C_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@REFLAYER_D_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@REFREGOFF_A_SHARP_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@REPFMT_A_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@REPFMT_B_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@REPFMT_C_VIDYO_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@RESCHANGE_A_VIDYO_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@RESPHASE_A_SAMSUNG_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@SAO_A_RExt_MediaTek_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SCREFOFF_A_QCOM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SIM_A_IDCC_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SIM_B_IDCC_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SLIST_A_Sony_5,Fail
GStreamer-H.265-Vulkan-Gst1.0@SLIST_B_Sony_9,Crash
GStreamer-H.265-Vulkan-Gst1.0@SLIST_C_Sony_4,Fail
GStreamer-H.265-Vulkan-Gst1.0@SLIST_D_Sony_9,Crash
GStreamer-H.265-Vulkan-Gst1.0@SLLEV_A_VIDYO_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SNR_A_IDCC_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SNR_B_IDCC_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SNR_C_IDCC_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SPLITFLAG_A_HHI_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SPSREPFMT_A_Sony_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@SPSSLIST_A_Sony_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@SRATIOS_A_SAMSUNG_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@SRATIOS_B_SAMSUNG_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@SREXT_A_FUJITSU_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SREXT_B_FUJITSU_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SREXT_C_FUJITSU_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SREXT_D_FUJITSU_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SREXT_E_FUJITSU_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@SREXT_F_FUJITSU_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@Slice_ACT_QP_Offsets_A_Qualcomm_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@TSCTX_10bit_I_RExt_SHARP_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@TSCTX_10bit_RExt_SHARP_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@TSCTX_12bit_I_RExt_SHARP_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@TSCTX_12bit_RExt_SHARP_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@TSCTX_8bit_I_RExt_SHARP_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@TSCTX_8bit_RExt_SHARP_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@TSUNEQBD_A_MAIN10_Technicolor_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@VPSSPSPPS_A_MainConcept_1,Fail
GStreamer-H.265-Vulkan-Gst1.0@VUI_A_QUALCOMM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@VUI_B_QUALCOMM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@VUI_C_QUALCOMM_1,Crash
GStreamer-H.265-Vulkan-Gst1.0@WAVETILES_RExt_Sony_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_AND_TILE_10Bit422Test_HIGH_TP_444_10BIT_RExt_Apple_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_AND_TILE_AND_CABAC_BYPASS_ALIGN_0_HIGH_TP_444_14BIT_RExt_Apple_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_AND_TILE_AND_CABAC_BYPASS_ALIGN_1_HIGH_TP_444_14BIT_RExt_Apple_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_AND_TILE_AND_CABAC_EXT_PREC_1_HIGH_TP_444_14BIT_RExt_Apple_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_AND_TILE_HIGH_TP_444_8BIT_RExt_Apple_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_A_ericsson_MAIN10_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_B_ericsson_MAIN10_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_C_ericsson_MAIN10_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_D_ericsson_MAIN10_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_E_ericsson_MAIN10_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_F_ericsson_MAIN10_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WPP_HIGH_TP_444_8BIT_RExt_Apple_2,Crash
GStreamer-H.265-Vulkan-Gst1.0@WP_A_MAIN10_Toshiba_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@WP_MAIN10_B_Toshiba_3,Crash
GStreamer-H.265-Vulkan-Gst1.0@Zero_and_One_Palette_Size_A_Canon_2,Crash
# CTS is missing -frounding-math: https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/6580
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.scalar.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.scalar.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec2.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec2.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec3.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec3.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec4.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec4.rte.denorm_flush.float_controls,Fail
src/amd/ci/radv-gfx1201-flakes.txt
+22
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@@ -0,0 +1,22 @@
dEQP-VK.api.buffer_marker.compute.default_mem.bottom_of_pipe.memory_dep.buffer_copy
dEQP-VK.pipeline.fast_linked_library.depth.format.d16_unorm_s8_uint.compare_ops.line_list_equal_less_or_equal_less_less_or_equal
dEQP-VK.pipeline.fast_linked_library.depth.format.d32_sfloat.compare_ops.triangle_list_equal_less_or_equal_less_less_or_equal
dEQP-VK.pipeline.fast_linked_library.depth.format.d32_sfloat_s8_uint.compare_ops.triangle_list_equal_less_or_equal_less_less_or_equal
dEQP-VK.pipeline.fast_linked_library.depth.nocolor.format.d16_unorm_s8_uint.compare_ops.triangle_list_greater_less_or_equal_never_greater_or_equal
dEQP-VK.pipeline.monolithic.depth.format.d16_unorm_s8_uint.compare_ops.triangle_list_greater_less_or_equal_never_greater_or_equal
dEQP-VK.pipeline.monolithic.depth.nocolor.format.d16_unorm_s8_uint.compare_ops.line_list_equal_less_or_equal_less_less_or_equal
dEQP-VK.pipeline.monolithic.depth.nocolor.format.d16_unorm_s8_uint.compare_ops.triangle_list_equal_less_or_equal_less_less_or_equal
dEQP-VK.pipeline.monolithic.depth.nocolor.format.d16_unorm_s8_uint_separate_layouts.compare_ops.triangle_list_greater_or_equal_less_less_or_equal_equal
dEQP-VK.pipeline.monolithic.depth.nocolor.format.d16_unorm_s8_uint_separate_layouts.compare_ops.triangle_list_greater_or_equal_less_or_equal_always_less
dEQP-VK.pipeline.monolithic.depth.nocolor.format.d32_sfloat_s8_uint.compare_ops.line_list_greater_or_equal_not_equal_greater_or_equal_greater
dEQP-VK.pipeline.monolithic.depth.nocolor.format.d32_sfloat_s8_uint_separate_layouts.compare_ops.triangle_list_equal_less_or_equal_less_less_or_equal
dEQP-VK.pipeline.pipeline_library.depth.format.d16_unorm.compare_ops.line_list_greater_not_equal_greater_less
dEQP-VK.pipeline.pipeline_library.depth.format.d32_sfloat.compare_ops.triangle_list_greater_or_equal_less_less_or_equal_equal
dEQP-VK.pipeline.pipeline_library.depth.format.d32_sfloat_s8_uint_separate_layouts.compare_ops.line_list_greater_or_equal_not_equal_greater_or_equal_greater
dEQP-VK.pipeline.shader_object_unlinked_spirv.depth.nocolor.format.d16_unorm_s8_uint.compare_ops.triangle_list_greater_or_equal_not_equal_greater_or_equal_greater
dEQP-VK.sparse_resources.image_sparse_residency.3d.rgba16_snorm.1024_128_8
dEQP-VK.wsi.direct.present_timing.basic.retired_swapchain
dEQP-VK.wsi.direct.present_timing.time_domain.calibration.present_stage_local
dEQP-VK.wsi.direct_drm.maintenance1.scaling.fifo.one_to_one.center_max.swapchain_smaller_same_aspect
dEQP-VK.wsi.direct_drm.present_timing.basic.retired_swapchain
dEQP-VK.wsi.direct_drm.present_timing.time_domain.calibration.present_stage_local
src/amd/ci/radv-hawaii-fails.txt
+41
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@@ -0,0 +1,41 @@
# RADV bug
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm.transfer_dst_optimal.32x32x1_cq_regions,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm.transfer_dst_optimal.32x32x2_cq_regions,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm.transfer_dst_optimal.32x32x2_cq_regions_img2img,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.transfer_dst_optimal.32x32x1_cq_regions,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.transfer_dst_optimal.32x32x2_cq_regions,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.transfer_dst_optimal.32x32x2_cq_regions_img2img,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat.transfer_dst_optimal.32x32x1_cq_regions,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat.transfer_dst_optimal.32x32x2_cq_regions,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat.transfer_dst_optimal.32x32x2_cq_regions_img2img,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat_s8_uint.transfer_dst_optimal.32x32x1_cq_regions,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat_s8_uint.transfer_dst_optimal.32x32x2_cq_regions,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat_s8_uint.transfer_dst_optimal.32x32x2_cq_regions_img2img,Fail
# VKCTS test bug (invalid behavior)
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm.general.32x32x2_cq_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm.general.32x32x2_cq_regions_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm.transfer_dst_optimal.32x32x2_cq_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm.transfer_dst_optimal.32x32x2_cq_regions_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.general.32x32x2_cq_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.general.32x32x2_cq_regions_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.transfer_dst_optimal.32x32x2_cq_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d16_unorm_s8_uint.transfer_dst_optimal.32x32x2_cq_regions_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat.general.32x32x2_cq_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat.general.32x32x2_cq_regions_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat.transfer_dst_optimal.32x32x2_cq_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat.transfer_dst_optimal.32x32x2_cq_regions_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat_s8_uint.general.32x32x2_cq_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat_s8_uint.general.32x32x2_cq_regions_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat_s8_uint.transfer_dst_optimal.32x32x2_cq_img2img_msaa,Fail
dEQP-VK.api.copy_and_blit.core.use_after_copy.d32_sfloat_s8_uint.transfer_dst_optimal.32x32x2_cq_regions_img2img_msaa,Fail
# CTS is missing -frounding-math: https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/6580
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.scalar.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.scalar.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec2.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec2.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec3.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec3.rte.denorm_flush.float_controls,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec4.rte.denorm_flush.directed,Fail
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp64.vec4.rte.denorm_flush.float_controls,Fail
src/amd/ci/radv-hawaii-flakes.txt
+7
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@@ -0,0 +1,7 @@
dEQP-VK.api.buffer_marker.compute.default_mem.bottom_of_pipe.memory_dep.buffer_copy
dEQP-VK.api.buffer_marker.compute.default_mem.bottom_of_pipe.memory_dep.buffer_copy_offset_24
dEQP-VK.api.buffer_marker.compute.external_host_mem.bottom_of_pipe.memory_dep.buffer_copy
dEQP-VK.api.buffer_marker.compute.external_host_mem.bottom_of_pipe.memory_dep.buffer_copy_offset_24
dEQP-VK.api.buffer_marker.compute.external_host_mem.bottom_of_pipe.memory_dep.dispatch
dEQP-VK.api.buffer_marker.compute.external_host_mem.bottom_of_pipe.memory_dep.dispatch_offset_24
dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.64bits_cmdcopyquerypoolresults_primary_cq
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