init

src/freedreno/.clang-format

@@ -0,0 +1,7 @@
+
+BasedOnStyle: InheritParentConfig
+DisableFormat: false
+
+AlignConsecutiveBitFields: Consecutive
+ColumnLimit: 80
+BreakStringLiterals: false

src/freedreno/.dir-locals.el

@@ -0,0 +1,11 @@
+((prog-mode
+  (indent-tabs-mode . nil)
+  (tab-width . 3)
+  (c-basic-offset . 3)
+  (c-file-style . "k&r")
+  (fill-column . 78)
+  (c-file-offsets
+   (arglist-cont-nonempty . ++)
+   )
+  )
+ )

src/freedreno/.editorconfig

@@ -0,0 +1,5 @@
+[*.{c,h}]
+indent_style = space
+indent_size = 3
+tab_width = 3
+max_line_length = 78

src/freedreno/ci/deqp-freedreno-a200.toml

@@ -0,0 +1,23 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 2.0.*git"
+renderer_check = "FD200"
+extensions_check = "/install/freedreno-a200-gles2-extensions.txt"
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]

src/freedreno/ci/deqp-freedreno-a306-piglit-quick-gl.toml

@@ -0,0 +1,8 @@
+[[piglit]]
+piglit_folder = "/piglit"
+profile = "quick_gl"
+process_isolation = true
+  [piglit.env]
+  PIGLIT_PLATFORM = "mixed_glx_egl"
+
+

src/freedreno/ci/deqp-freedreno-a306-piglit-quick-shader.toml

@@ -0,0 +1,8 @@
+[[piglit]]
+piglit_folder = "/piglit"
+profile = "quick_shader"
+process_isolation = true
+  [piglit.env]
+  PIGLIT_PLATFORM = "mixed_glx_egl"
+
+

src/freedreno/ci/deqp-freedreno-a306-piglit.toml

@@ -0,0 +1,6 @@
+[[piglit]]
+piglit_folder = "/piglit"
+profile = "gpu"
+process_isolation = true
+  [piglit.env]
+  PIGLIT_NO_WINDOW = "1"

src/freedreno/ci/deqp-freedreno-a306.toml

@@ -0,0 +1,47 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.0.*git"
+renderer_check = "FD307"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+# Not doing GLES3 because of a lot of GPU hangs.
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# Check that the non-constbuf UBO case works.
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+include = ["functional.*ubo"]
+prefix = "nouboopt-"
+[deqp.env]
+IR3_SHADER_DEBUG = "nouboopt"

src/freedreno/ci/deqp-freedreno-a530-piglit.toml

@@ -0,0 +1,6 @@
+[[piglit]]
+piglit_folder = "/piglit"
+profile = "gpu"
+process_isolation = true
+  [piglit.env]
+  PIGLIT_NO_WINDOW = "1"

src/freedreno/ci/deqp-freedreno-a530.toml

@@ -0,0 +1,54 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.1.*git"
+renderer_check = "FD530"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 2
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 2
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[piglit]]
+piglit_folder = "/piglit"
+# We use "gpu" to skip running glslparser tests, with the assumption that
+# they're covered by the llvmpipe run.
+profile = "quick_shader"
+process_isolation = true
+  [piglit.env]
+  PIGLIT_PLATFORM = "gbm"
+  WAFFLE_PLATFORM = "gbm"

src/freedreno/ci/deqp-freedreno-a618-gles-asan.toml

@@ -0,0 +1,13 @@
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+fraction = 1
+renderer_check = "FD618"
+deqp_args = [
+    "--deqp-surface-width=256",
+    "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+    "--deqp-visibility=hidden",
+]
+prefix = "asan-"

src/freedreno/ci/deqp-freedreno-a618-piglit-full.toml

@@ -0,0 +1,7 @@
+[[piglit]]
+piglit_folder = "/piglit"
+profile = "gpu"
+process_isolation = true
+timeout = 180.0
+  [piglit.env]
+  PIGLIT_NO_WINDOW = "1"

src/freedreno/ci/deqp-freedreno-a618-piglit.toml

@@ -0,0 +1,14 @@
+[[piglit]]
+piglit_folder = "/piglit"
+profile = "gpu"
+process_isolation = true
+fraction = 6
+  [piglit.env]
+  PIGLIT_NO_WINDOW = "1"
+
+[[piglit]]
+piglit_folder = "/piglit"
+profile = "cl"
+process_isolation = true
+  [piglit.env]
+  RUSTICL_ENABLE = "msm"

src/freedreno/ci/deqp-freedreno-a618-skqp.toml

@@ -0,0 +1,3 @@
+[[skqp]]
+skqp = "/skqp/skqp"
+skqp_assets = "/skqp/assets"

src/freedreno/ci/deqp-freedreno-a618-vk-asan.toml

@@ -0,0 +1,22 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+fraction = 100
+renderer_check = "Turnip Adreno .* 618"
+prefix = "asan-"
+timeout = 180
+tests_per_group = 3500
+
+# Force the spiller on one test so we see its memory usage.
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+include = ["dEQP-VK.graphicsfuzz.barrier-in-loop-with-break"]
+prefix = "spill-"
+tests_per_group = 1
+[deqp.env]
+# Increase the hangcheck timer for our spilling tests which bump up against
+# the .5s default.
+FREEDRENO_HANGCHECK_MS = "2000"
+IR3_SHADER_DEBUG = "spillall"

src/freedreno/ci/deqp-freedreno-a618-vk.toml

@@ -0,0 +1,51 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "Turnip Adreno .* 618"
+fraction = 1
+tests_per_group = 10000
+[deqp.env]
+# Enable additional tests that test fp32 denorm preserve.
+tu_enable_softfloat32 = "true"
+
+# force-gmem testing
+# Autotuner forces sysmem on most CTS tests
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+prefix = "gmem-"
+fraction = 15
+tests_per_group = 5000
+[deqp.env]
+TU_DEBUG = "gmem,forcebin"
+
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+include = ["dEQP-VK.graphicsfuzz.*", "dEQP-VK.subgroups.ballot*"]
+prefix = "spill-"
+tests_per_group = 2000
+[deqp.env]
+IR3_SHADER_DEBUG = "spillall"
+
+# non-binning gmem-forced testing.  Takes about 2-5 seconds.
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+prefix = "nobin-"
+include = ["dEQP-VK.transform_feedback.*"]
+tests_per_group = 5000
+[deqp.env]
+TU_DEBUG = "gmem,nobin"
+
+# force-sysmem testing
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+include = ["dEQP-VK.renderpass.*"]
+prefix = "bypass-"
+fraction = 15
+tests_per_group = 5000
+[deqp.env]
+TU_DEBUG = "sysmem"

src/freedreno/ci/deqp-freedreno-a618.toml

@@ -0,0 +1,179 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2.*git"
+renderer_check = "FD618"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gl/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gl/mustpass/gl46-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+
+# force-gmem testing
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 5
+prefix = "gmem-"
+[deqp.env]
+FD_MESA_DEBUG = "gmem"
+
+
+# force-bypass testing
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 5
+prefix = "bypass-"
+[deqp.env]
+FD_MESA_DEBUG = "sysmem"
+
+
+# noubo testing
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+include = ["functional.*ubo"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "noubo-"
+[deqp.env]
+IR3_SHADER_DEBUG = "nouboopt"
+
+
+# 565-nozs
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+# spilling testing
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+include = ["functional.shaders"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "spill-"
+[deqp.env]
+IR3_SHADER_DEBUG = "spillall"
+
+# x11
+[[deqp]]
+deqp = "/deqp-gles/modules/egl/deqp-egl-x11"
+caselists = ["/deqp-gles/mustpass/egl-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "x11-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/egl/deqp-egl-wayland"
+caselists = ["/deqp-gles/mustpass/egl-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "wayland-"

src/freedreno/ci/deqp-freedreno-a660-vk-full.toml

@@ -0,0 +1,45 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+timeout = 300
+renderer_check = "Turnip Adreno .* 660"
+tests_per_group = 10000
+[deqp.env]
+# Enable additional tests that test fp32 denorm preserve.
+tu_enable_softfloat32 = "true"
+
+# force-gmem testing
+# Autotuner forces sysmem on most CTS tests
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+timeout = 300
+prefix = "gmem-"
+fraction = 10
+tests_per_group = 10000
+[deqp.env]
+TU_DEBUG = "gmem,forcebin"
+
+# non-binning gmem-forced testing.  Takes about 2-5 seconds.
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+timeout = 300
+prefix = "nobin-"
+fraction = 10
+include = ["dEQP-VK.transform_feedback.*"]
+tests_per_group = 5000
+[deqp.env]
+TU_DEBUG = "gmem,nobin"
+
+# force-sysmem testing
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+timeout = 300
+include = ["dEQP-VK.renderpass.*"]
+prefix = "bypass-"
+tests_per_group = 5000
+[deqp.env]
+TU_DEBUG = "sysmem"

src/freedreno/ci/deqp-freedreno-a660-vk.toml

@@ -0,0 +1,43 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "Turnip Adreno .* 660"
+fraction = 6
+tests_per_group = 10000
+[deqp.env]
+# Enable additional tests that test fp32 denorm preserve.
+tu_enable_softfloat32 = "true"
+
+# force-gmem testing
+# Autotuner forces sysmem on most CTS tests
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+prefix = "gmem-"
+fraction = 20
+tests_per_group = 10000
+[deqp.env]
+TU_DEBUG = "gmem,forcebin"
+
+# spillall and stale regs testing disabled due to crashing a ton.
+#[[deqp]]
+#deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+#caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+#include = ["dEQP-VK.graphicsfuzz.*", "dEQP-VK.subgroups.ballot*"]
+#prefix = "spill-"
+#tests_per_group = 2000
+#[deqp.env]
+#IR3_SHADER_DEBUG = "spillall"
+
+# testing for stale regs usage
+#[[deqp]]
+#deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+#caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+#prefix = "stale-regs-"
+#fraction = 200
+#tests_per_group = 5000
+#[deqp.env]
+#TU_DEBUG = "gmem,forcebin"
+#TU_DEBUG_STALE_REGS_RANGE = "0x0c00,0xbe01"
+#TU_DEBUG_STALE_REGS_FLAGS = "cmdbuf,renderpass"

src/freedreno/ci/deqp-freedreno-a660.toml

@@ -0,0 +1,165 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2.*git"
+renderer_check = "FD660"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gl/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gl/mustpass/gl46-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+
+# force-gmem testing
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 5
+prefix = "gmem-"
+[deqp.env]
+FD_MESA_DEBUG = "gmem"
+
+
+# force-bypass testing
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 5
+prefix = "bypass-"
+[deqp.env]
+FD_MESA_DEBUG = "sysmem"
+
+
+# noubo testing
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+include = ["functional.*ubo"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "noubo-"
+[deqp.env]
+IR3_SHADER_DEBUG = "nouboopt"
+
+
+# 565-nozs
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+# spilling testing
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+include = ["functional.shaders"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "spill-"
+[deqp.env]
+IR3_SHADER_DEBUG = "spillall"
+
+[[piglit]]
+piglit_folder = "/piglit"
+profile = "cl"
+process_isolation = true
+  [piglit.env]
+  RUSTICL_ENABLE = "msm"

src/freedreno/ci/deqp-freedreno-a750-vk.toml

@@ -0,0 +1,95 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "Turnip Adreno .* 750"
+tests_per_group = 10000
+[deqp.env]
+# Enable additional tests that test fp32 denorm preserve.
+tu_enable_softfloat32 = "true"
+
+# force-gmem testing
+# Autotuner forces sysmem on most CTS tests
+# Also force-enable concurrent binning.
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+prefix = "gmem-"
+fraction = 20
+tests_per_group = 10000
+[deqp.env]
+TU_DEBUG = "gmem,forcebin,forcecb"
+
+# force-gmem with unaligned gmem store testing
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+include = ["dEQP-VK.renderpass2.*"]
+prefix = "gmem-unaligned-"
+fraction = 10
+tests_per_group = 10000
+[deqp.env]
+TU_DEBUG = "gmem,unaligned_store"
+
+# force-gmem with concurrent binning allowed to test concurrent binning
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+include = ["dEQP-VK.renderpass2.*"]
+prefix = "gmem-cb-"
+fraction = 20
+tests_per_group = 10000
+[deqp.env]
+TU_DEBUG = "gmem"
+tu_allow_concurrent_binning = "true"
+
+# force-sysmem testing
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+include = ["dEQP-VK.renderpass.*"]
+prefix = "bypass-"
+fraction = 10
+tests_per_group = 10000
+[deqp.env]
+TU_DEBUG = "sysmem"
+
+# force-spilling testing
+# NOTE: Disabled due to crashing the board so hard it goes into Sahara mode
+# [[deqp]]
+# deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+# caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+# include = ["dEQP-VK.graphicsfuzz.*"]
+# prefix = "spill-"
+# fraction = 10
+# tests_per_group = 1000
+# [deqp.env]
+# IR3_SHADER_DEBUG = "spillall"
+
+# dynamic rendering testing using emulated renderpass
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+include = ["dEQP-VK.renderpass2.*"]
+prefix = "dynamic-"
+tests_per_group = 10000
+[deqp.env]
+TU_DEBUG = "dynamic"
+
+# testing for stale regs usage
+# NOTE: Disabled due to constant gpu hangs
+# [[deqp]]
+# deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+# caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+# prefix = "stale-regs-"
+# fraction = 100
+# tests_per_group = 1000
+# [deqp.env]
+# TU_DEBUG = "gmem,forcebin"
+# TU_DEBUG_STALE_REGS_RANGE = "0x0c00,0xbe01"
+# TU_DEBUG_STALE_REGS_FLAGS = "cmdbuf,renderpass"
+# FREEDRENO_HANGCHECK_MS = "2000"
+
+[[vkd3d]]
+vkd3d_folder = "/vkd3d-proton-tests/"
+prefix="vkd3d-" # The test names are pretty ambiguous, otherwise.

src/freedreno/ci/deqp-freedreno-a750.toml

@@ -0,0 +1,63 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2.*git"
+renderer_check = "FD750"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gl/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gl/mustpass/gl46-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[piglit]]
+piglit_folder = "/piglit"
+profile = "cl"
+process_isolation = true
+  [piglit.env]
+  RUSTICL_ENABLE = "msm"

src/freedreno/ci/deqp-tu-android.toml

@@ -0,0 +1,52 @@
+# Run one GLES 2 test to check the version and renderer
+[[deqp]]
+deqp = "/data/deqp/deqp-gles2"
+caselists = ["/data/deqp/gles2-main.txt"]
+include = [ "dEQP-GLES2.info.renderer" ]
+deqp_args = [
+    "--deqp-surface-width=256",
+    "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+    "--deqp-visibility=hidden"
+]
+version_check = "GL ES 3.2.*ANGLE 2.1.1 git"
+renderer_check = "ANGLE.*Adreno"
+
+# AHB test set
+[[deqp]]
+deqp = "/data/deqp/deqp-vk"
+caselists = ["/data/deqp/vk-main.txt"]
+include = ["dEQP-VK.api.external.memory.android_hardware_buffer.*"]
+renderer_check = "Adreno"
+prefix = "ahb-"
+
+# Vulkan WSI test set
+[[deqp]]
+deqp = "/data/deqp/deqp-vk"
+caselists = ["/data/deqp/vk-main.txt"]
+include = ["dEQP-VK.wsi.android.*"]
+prefix = "awsi-"
+
+# Basic fractioned VKCTS test set
+[[deqp]]
+deqp = "/data/deqp/deqp-vk"
+caselists = [ "/data/deqp/vk-main.txt" ]
+tests_per_group = 10000
+skips = ["/data/deqp/android-skips.txt"]
+timeout = 120
+fraction = 600
+prefix = "android-"
+
+# EGL test set
+[[deqp]]
+deqp = "/data/deqp/deqp-egl-android"
+caselists = ["/data/deqp/egl-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256",
+    "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+    "--deqp-visibility=hidden"
+]
+prefix = "android-"

src/freedreno/ci/deqp-tu-angle.toml

@@ -0,0 +1,72 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2"
+renderer_check = "ANGLE.*Adreno"
+prefix = "angle-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "angle-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "angle-"
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "angle-"
+
+# 565-no-depth-no-stencil: Not supported with angle on X11?
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "angle-multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "angle-multisample-"

src/freedreno/ci/freedreno-a200-flakes.txt

@@ -0,0 +1,6 @@
+# It was Timeout'ing when run in with concurency set to 2, let's call it a
+# flake for now
+dEQP-GLES2.functional.texture.mipmap.cube.basic.linear_linear
+
+# likely in 6ea4fe98..c69f7904
+dEQP-GLES2.functional.color_clear.single_rgba

src/freedreno/ci/freedreno-a200-gles2-extensions.txt

@@ -0,0 +1,75 @@
+GL_AMD_compressed_ATC_texture
+GL_ANGLE_pack_reverse_row_order
+GL_ANGLE_texture_compression_dxt3
+GL_ANGLE_texture_compression_dxt5
+GL_APPLE_sync
+GL_APPLE_texture_max_level
+GL_EXT_blend_minmax
+GL_EXT_color_buffer_half_float
+GL_EXT_compressed_ETC1_RGB8_sub_texture
+GL_EXT_debug_label
+GL_EXT_discard_framebuffer
+GL_EXT_draw_buffers
+GL_EXT_draw_elements_base_vertex
+GL_EXT_frag_depth
+GL_EXT_map_buffer_range
+GL_EXT_memory_object
+GL_EXT_memory_object_fd
+GL_EXT_multi_draw_arrays
+GL_EXT_read_format_bgra
+GL_EXT_robustness
+GL_EXT_semaphore
+GL_EXT_semaphore_fd
+GL_EXT_separate_shader_objects
+GL_EXT_shadow_samplers
+GL_EXT_texture_border_clamp
+GL_EXT_texture_compression_dxt1
+GL_EXT_texture_compression_s3tc
+GL_EXT_texture_filter_anisotropic
+GL_EXT_texture_format_BGRA8888
+GL_EXT_texture_mirror_clamp_to_edge
+GL_EXT_texture_rg
+GL_EXT_texture_storage
+GL_EXT_texture_type_2_10_10_10_REV
+GL_EXT_unpack_subimage
+GL_KHR_context_flush_control
+GL_KHR_debug
+GL_KHR_no_error
+GL_KHR_parallel_shader_compile
+GL_KHR_robust_buffer_access_behavior
+GL_KHR_robustness
+GL_MESA_bgra
+GL_MESA_sampler_objects
+GL_MESA_texture_const_bandwidth
+GL_NV_draw_buffers
+GL_NV_fbo_color_attachments
+GL_NV_pack_subimage
+GL_NV_pixel_buffer_object
+GL_NV_read_buffer
+GL_NV_read_depth
+GL_NV_read_depth_stencil
+GL_NV_read_stencil
+GL_NV_texture_barrier
+GL_OES_EGL_image
+GL_OES_EGL_image_external
+GL_OES_EGL_sync
+GL_OES_compressed_ETC1_RGB8_texture
+GL_OES_depth24
+GL_OES_depth_texture
+GL_OES_draw_elements_base_vertex
+GL_OES_element_index_uint
+GL_OES_fbo_render_mipmap
+GL_OES_get_program_binary
+GL_OES_mapbuffer
+GL_OES_packed_depth_stencil
+GL_OES_required_internalformat
+GL_OES_rgb8_rgba8
+GL_OES_stencil8
+GL_OES_surfaceless_context
+GL_OES_texture_3D
+GL_OES_texture_border_clamp
+GL_OES_texture_float
+GL_OES_texture_half_float
+GL_OES_texture_npot
+GL_OES_vertex_array_object
+GL_OES_vertex_half_float

src/freedreno/ci/freedreno-a306-flakes.txt

@@ -0,0 +1,59 @@
+# Note: flakes lists for CI are just a list of lines that, when
+# non-zero-length and not starting with '#', will regex match to
+# delete lines from the test list.  Be careful.
+dEQP-GLES3.functional.shaders.texture_functions.texture.*gradoffset.*
+dEQP-GLES3.functional.texture.units.4_units.only_3d.*
+dEQP-GLES3.functional.vertex_arrays.single_attribute.*
+
+# These started UnexpectedPass'ing in an unrelated MR, let's call
+# them flakes for now
+dEQP-GLES3.functional.occlusion_query.*
+
+glx@glx-swap-event_interval
+glx@glx-swap-event_async
+glx@glx_arb_sync_control@swapbuffersmsc-divisor-zero
+glx@glx_arb_sync_control@waitformsc
+glx@glx_ext_no_config_context@no fbconfig
+
+spec@arb_map_buffer_alignment@arb_map_buffer_alignment-map-invalidate-range
+spec@arb_vertex_buffer_object@vbo-subdata-many drawelements
+spec@egl_chromium_sync_control@conformance
+spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test
+
+dEQP-GLES3.functional.occlusion_query.all_occluders
+dEQP-GLES3.functional.occlusion_query.conservative_depth_clear_stencil_write
+dEQP-GLES3.functional.occlusion_query.conservative_depth_clear_stencil_write_stencil_clear
+dEQP-GLES3.functional.occlusion_query.conservative_depth_write
+dEQP-GLES3.functional.occlusion_query.conservative_depth_write_depth_clear
+dEQP-GLES3.functional.occlusion_query.conservative_depth_write_depth_clear_stencil_write
+dEQP-GLES3.functional.occlusion_query.conservative_depth_write_stencil_clear
+dEQP-GLES3.functional.occlusion_query.conservative_depth_write_stencil_write
+dEQP-GLES3.functional.occlusion_query.conservative_depth_write_stencil_write_stencil_clear
+dEQP-GLES3.functional.occlusion_query.conservative_scissor_depth_clear_stencil_write
+dEQP-GLES3.functional.occlusion_query.conservative_scissor_depth_write
+dEQP-GLES3.functional.occlusion_query.conservative_scissor_depth_write_depth_clear
+dEQP-GLES3.functional.occlusion_query.conservative_scissor_depth_write_depth_clear_stencil_clear
+dEQP-GLES3.functional.occlusion_query.conservative_scissor_depth_write_stencil_write
+dEQP-GLES3.functional.occlusion_query.conservative_scissor_depth_write_stencil_write_stencil_clear
+dEQP-GLES3.functional.occlusion_query.conservative_stencil_write
+dEQP-GLES3.functional.occlusion_query.conservative_stencil_write_stencil_clear
+dEQP-GLES3.functional.occlusion_query.depth_clear
+dEQP-GLES3.functional.occlusion_query.depth_write_depth_clear_stencil_write_stencil_clear
+dEQP-GLES3.functional.occlusion_query.depth_write_stencil_clear
+dEQP-GLES3.functional.occlusion_query.depth_write_stencil_write_stencil_clear
+dEQP-GLES3.functional.occlusion_query.scissor
+dEQP-GLES3.functional.occlusion_query.scissor_depth_clear_stencil_clear
+dEQP-GLES3.functional.occlusion_query.scissor_depth_clear_stencil_write_stencil_clear
+dEQP-GLES3.functional.occlusion_query.scissor_depth_write_depth_clear_stencil_clear
+dEQP-GLES3.functional.occlusion_query.scissor_depth_write_stencil_write_stencil_clear
+dEQP-GLES3.functional.occlusion_query.scissor_stencil_write
+dEQP-GLES3.functional.occlusion_query.stencil_clear
+dEQP-GLES3.functional.occlusion_query.stencil_write
+dEQP-GLES3.functional.occlusion_query.stencil_write_stencil_clear
+dEQP-GLES3.functional.vertex_arrays.single_attribute.normalize.int2_10_10_10.components4_quads256
+
+# uprev Piglit in Mesa
+spec@!opengl 2.0@tex3d-npot
+spec@arb_vertex_buffer_object@vbo-subdata-many drawarrays
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_nv21
+

src/freedreno/ci/freedreno-a306-skips.txt

@@ -0,0 +1,79 @@
+# Note: skips lists for CI are just a list of lines that, when
+# non-zero-length and not starting with '#', will regex match to
+# delete lines from the test list.  Be careful.
+
+# no Vulkan support
+spec@ext_external_objects@vk.*
+
+# no msaa support
+.*msaa.*
+.*multisample.*
+
+# Skip over a bunch of extensions since we don't have extension fast skipping yet.
+[email protected]
+spec@glsl-4.*
+spec@arb_gpu_shader5
+spec@arb_gpu_shader_fp64
+spec@arb_gpu_shader_int64
+spec@arb_tessellation_shader
+
+# Timeouts sometimes
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-refcount-multithread
+
+# 1.5 minutes
+spec@!opengl 1.2@tex3d-maxsize
+
+# ~1 minute
+glx@glx-multithread-texture
+spec@!opengl 1.1@draw-sync
+spec@arb_uniform_buffer_object@execution@shared-struct-array-array-array-struct
+spec@arb_uniform_buffer_object@execution@std140-struct-array-array-array-struct
+[email protected]@execution@texelfetch fs sampler2d 1x281-501x281
+[email protected]@execution@texelfetch fs sampler2darray 98x1x9-98x129x9
+[email protected]@execution@texelfetch fs sampler2darray 1x129x9-98x129x9
+
+# If we let these tests run in parallel with other piglit tests, we end up
+# intermittent GL_OUT_OF_MEMORY errors in innocent tests.
+arb_texture_buffer_object@max-size
+fbo-maxsize
+max-texture-size
+copypixels-draw-sync
+
+# This OOMs on its own
+spec@!opengl [email protected]
+
+# Hangchecks
+tex-miplevel-selection
+spec@arb_direct_state_access@transformfeedback-bufferrange
+spec@arb_direct_state_access@transformfeedback-bufferbase
+spec@arb_uniform_buffer_object@rendering-array
+spec@arb_uniform_buffer_object@rendering-array-offset
+spec@arb_point_sprite@arb_point_sprite-interactions
+shaders@glsl-uniform-interstage-limits --subdivide 5 --statechanges
+gles-3.0-transform-feedback-uniform-buffer-object
+
+spec@!opengl [email protected] 100000 varray gl_lines
+spec@!opengl [email protected] 100000 vbo gl_lines
+glsl-1.40-tf-no-position
+spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index8-clear
+spec@arb_framebuffer_srgb@arb_framebuffer_srgb-srgb_conformance
+spec@arb_framebuffer_srgb@blit renderbuffer linear
+spec@arb_framebuffer_srgb@blit texture srgb
+spec@!opengl 1.1@dlist-fdo3129-01
+
+# Unsupported legacy gl features
+.*edgeflag.*
+.*stipple.*
+# uses edgeflags:
+shaders@point-vertex-id.*
+# uses stipple:
+spec@!opengl [email protected]
+
+# Times out
+glx@glx-visuals-depth
+glx@glx-visuals-stencil
+shaders@glsl-uniform-interstage-limits@subdivide 5- statechanges
+spec@arb_point_parameters@arb_point_parameters-point-attenuation
+[email protected]@execution@texelfetch fs sampler2d 281x1-281x281
+spec@ext_texture_lod_bias@lodbias
+

src/freedreno/ci/freedreno-a420-fails.txt

@@ -0,0 +1,378 @@
+# Points/lines pop in and out instead of being clipped ES-style
+dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_center,Fail
+dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_corner,Fail
+dEQP-GLES2.functional.clipping.point.wide_point_clip,Fail
+dEQP-GLES2.functional.clipping.point.wide_point_clip_viewport_center,Fail
+dEQP-GLES2.functional.clipping.point.wide_point_clip_viewport_corner,Fail
+dEQP-GLES3.functional.clipping.line.wide_line_clip_viewport_center,Fail
+dEQP-GLES3.functional.clipping.line.wide_line_clip_viewport_corner,Fail
+dEQP-GLES3.functional.clipping.point.wide_point_clip,Fail
+dEQP-GLES3.functional.clipping.point.wide_point_clip_viewport_center,Fail
+dEQP-GLES3.functional.clipping.point.wide_point_clip_viewport_corner,Fail
+
+# Problems blitting stencil?
+dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_basic,Fail
+dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_scale,Fail
+dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_stencil_only,Fail
+dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_basic,Fail
+dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_scale,Fail
+dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_stencil_only,Fail
+KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8,Fail
+
+# Something to do with the nearest rounding being incorrectly done?
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_dst_x,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_dst_y,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_src_dst_x,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_src_dst_y,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_src_x,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_src_y,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_dst_x,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_dst_y,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_src_dst_x,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_src_dst_y,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_src_x,Fail
+dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_src_y,Fail
+
+# Needs investigation
+dEQP-GLES3.functional.fbo.invalidate.default.bind_depth,Fail
+dEQP-GLES3.functional.fbo.invalidate.default.bind_stencil,Fail
+dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_color,Fail
+dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_depth,Fail
+dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_color,Fail
+dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_depth,Fail
+
+# Needs investigation
+dEQP-GLES3.functional.negative_api.buffer.read_pixels_fbo_format_mismatch,Fail
+
+# MSAA not implemented
+dEQP-GLES3.functional.state_query.integers.max_samples_getfloat,Fail
+dEQP-GLES3.functional.state_query.integers.max_samples_getinteger64,Fail
+KHR-GLES3.framebuffer_completeness.all_rbos_expect_same_numsamples,Fail
+KHR-GLES3.framebuffer_completeness.rbo_and_texture_expect_zero_numsamples,Fail
+KHR-GLES31.core.framebuffer_completeness.all_rbos_expect_same_numsamples,Fail
+KHR-GLES31.core.framebuffer_completeness.expect_equal_numsamples,Fail
+KHR-GLES31.core.framebuffer_completeness.rbo_and_texture_expect_zero_numsamples,Fail
+KHR-GLES31.core.framebuffer_no_attachments.api,Fail
+dEQP-GLES31.functional.debug.error_filters.case_29,Fail
+dEQP-GLES31.functional.debug.negative_coverage.callbacks.buffer.read_pixels_fbo_format_mismatch,Fail
+dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.read_pixels_fbo_format_mismatch,Fail
+dEQP-GLES31.functional.debug.negative_coverage.log.buffer.read_pixels_fbo_format_mismatch,Fail
+dEQP-GLES31.functional.fbo.no_attachments.interaction.17x512ms4_default_16x16ms2,Fail
+dEQP-GLES31.functional.fbo.no_attachments.interaction.1x1ms0_default_2048x2048ms4,Fail
+dEQP-GLES31.functional.fbo.no_attachments.interaction.2048x2048ms4_default_1x1ms0,Fail
+dEQP-GLES31.functional.fbo.no_attachments.interaction.256x256ms0_default_512x512ms2,Fail
+dEQP-GLES31.functional.fbo.no_attachments.interaction.256x256ms2_default_128x512ms0,Fail
+dEQP-GLES31.functional.fbo.no_attachments.random.1,Fail
+dEQP-GLES31.functional.fbo.no_attachments.random.11,Fail
+dEQP-GLES31.functional.fbo.no_attachments.random.14,Fail
+dEQP-GLES31.functional.fbo.no_attachments.random.15,Fail
+dEQP-GLES31.functional.fbo.no_attachments.random.4,Fail
+dEQP-GLES31.functional.fbo.no_attachments.random.9,Fail
+dEQP-GLES31.functional.state_query.integer.max_framebuffer_samples_getfloat,Fail
+dEQP-GLES31.functional.state_query.integer.max_framebuffer_samples_getinteger,Fail
+dEQP-GLES31.functional.state_query.integer.max_framebuffer_samples_getinteger64,Fail
+
+# Needs investigation. Maybe shader size and/or constbuf size?
+KHR-GLES3.shaders.uniform_block.random.nested_structs_arrays.9,Fail
+dEQP-GLES31.functional.ubo.random.all_per_block_buffers.13,Fail
+dEQP-GLES31.functional.ubo.random.all_per_block_buffers.20,Fail
+
+# XFB doesn't take indirect draw vertex counts
+KHR-GLES31.core.draw_indirect.advanced-twoPass-transformFeedback-arrays,Fail
+KHR-GLES31.core.draw_indirect.advanced-twoPass-transformFeedback-elements,Fail
+
+# Needs investigation
+KHR-GLES31.core.compute_shader.resource-image,Fail
+KHR-GLES31.core.shader_image_load_store.advanced-allMips-cs,Fail
+KHR-GLES31.core.shader_image_load_store.advanced-allMips-fs,Fail
+
+# Needs investigation -- we don't 100% match blob for imageBuffer
+KHR-GLES31.core.texture_buffer.texture_buffer_atomic_functions,Fail
+
+# Instanced draws don't seem to work properly with XFB
+KHR-GLES31.core.vertex_attrib_binding.basic-input-case11,Fail
+KHR-GLES31.core.vertex_attrib_binding.basic-input-case9,Fail
+KHR-GLES31.core.vertex_attrib_binding.basic-inputI-case2,Fail
+
+# Clamping is done at the wrong time? But why is depth OK?
+KHR-GLES31.core.gpu_shader5.texture_gather_offset_color_clamp_to_border,Fail
+KHR-GLES31.core.gpu_shader5.texture_gather_offset_color_clamp_to_edge,Fail
+
+# Got wrong error code: GL_INVALID_OPERATION, expected: GL_INVALID_VALUE after step 0 at glcCompressedFormatTests.cpp:1463
+KHR-GLES31.core.compressed_format.api.invalid_teximage_with_compressed_format,Fail
+
+# Some sort of integer blending problem? Only sub-32-bit integer RB formats have issues
+dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.1,Fail
+dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.12,Fail
+dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.14,Fail
+dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.17,Fail
+dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.18,Fail
+dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.2,Fail
+dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.5,Fail
+dEQP-GLES31.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.9,Fail
+dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.11,Fail
+
+# ASTC precision issues? Test being too picky?
+spec@khr_texture_compression_astc@array-gl,Fail
+spec@khr_texture_compression_astc@array-gl@12x12 Block Dim,Fail
+spec@khr_texture_compression_astc@array-gl@5x5 Block Dim,Fail
+spec@khr_texture_compression_astc@array-gles,Fail
+spec@khr_texture_compression_astc@array-gles@12x12 Block Dim,Fail
+spec@khr_texture_compression_astc@array-gles@5x5 Block Dim,Fail
+spec@khr_texture_compression_astc@miptree-gl hdr,Fail
+spec@khr_texture_compression_astc@miptree-gl hdr@HDR Profile,Fail
+spec@khr_texture_compression_astc@miptree-gl ldr,Fail
+spec@khr_texture_compression_astc@miptree-gl ldr@LDR Profile,Fail
+spec@khr_texture_compression_astc@miptree-gl srgb,Fail
+spec@khr_texture_compression_astc@miptree-gl srgb-fp,Fail
+spec@khr_texture_compression_astc@miptree-gl srgb-fp@sRGB decode full precision,Fail
+spec@khr_texture_compression_astc@miptree-gl srgb-sd,Fail
+spec@khr_texture_compression_astc@miptree-gl srgb-sd@sRGB skip decode,Fail
+spec@khr_texture_compression_astc@miptree-gl srgb@sRGB decode,Fail
+spec@khr_texture_compression_astc@miptree-gles hdr,Fail
+spec@khr_texture_compression_astc@miptree-gles hdr@HDR Profile,Fail
+spec@khr_texture_compression_astc@miptree-gles ldr,Fail
+spec@khr_texture_compression_astc@miptree-gles ldr@LDR Profile,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb-fp,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb-fp@sRGB decode full precision,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb-sd,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb-sd@sRGB skip decode,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb@sRGB decode,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl hdr,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl hdr@HDR Profile,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl ldr,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl ldr@LDR Profile,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl srgb,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl srgb-fp,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl srgb-fp@sRGB decode full precision,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl srgb@sRGB decode,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles hdr,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles hdr@HDR Profile,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles ldr,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles ldr@LDR Profile,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp@sRGB decode full precision,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb@sRGB decode,Fail
+
+# The clipped polygon is off-by-one pixel from the directly drawn one
+spec@!opengl [email protected],Fail
+
+# Something with ONE_MINUS_CONSTANT_COLOR
+spec@ext_framebuffer_object@fbo-blending-snorm,Fail
+
+# Failure to operate on stencil separately from depth
+spec@!opengl 1.1@depthstencil-default_fb-blit,Fail
+spec@!opengl 1.1@depthstencil-default_fb-copypixels,Fail
+spec@arb_depth_buffer_float@fbo-clear-formats stencil,Fail
+spec@arb_depth_buffer_float@fbo-clear-formats stencil@GL_DEPTH32F_STENCIL8,Fail
+spec@arb_depth_buffer_float@fbo-depthstencil-gl_depth32f_stencil8-blit,Fail
+spec@arb_depth_buffer_float@fbo-depthstencil-gl_depth32f_stencil8-copypixels,Fail
+spec@arb_depth_buffer_float@fbo-stencil-gl_depth32f_stencil8-blit,Fail
+spec@arb_depth_buffer_float@fbo-stencil-gl_depth32f_stencil8-copypixels,Fail
+spec@arb_framebuffer_object@arb_framebuffer_object-depth-stencil-blit depth_stencil gl_depth24_stencil8,Fail
+spec@arb_framebuffer_object@arb_framebuffer_object-depth-stencil-blit depth_stencil gl_depth32f_stencil8,Fail
+spec@arb_framebuffer_object@arb_framebuffer_object-depth-stencil-blit stencil gl_depth24_stencil8,Fail
+spec@arb_framebuffer_object@arb_framebuffer_object-depth-stencil-blit stencil gl_depth32f_stencil8,Fail
+spec@arb_framebuffer_object@arb_framebuffer_object-depth-stencil-blit stencil gl_stencil_index1,Fail
+spec@arb_framebuffer_object@arb_framebuffer_object-depth-stencil-blit stencil gl_stencil_index16,Fail
+spec@arb_framebuffer_object@arb_framebuffer_object-depth-stencil-blit stencil gl_stencil_index4,Fail
+spec@arb_framebuffer_object@arb_framebuffer_object-depth-stencil-blit stencil gl_stencil_index8,Fail
+spec@arb_framebuffer_object@framebuffer-blit-levels draw stencil,Fail
+spec@arb_framebuffer_object@framebuffer-blit-levels read stencil,Fail
+spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index1-blit,Fail
+spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index1-copypixels,Fail
+spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index16-blit,Fail
+spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index16-copypixels,Fail
+spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index4-blit,Fail
+spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index4-copypixels,Fail
+spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index8-blit,Fail
+spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index8-copypixels,Fail
+spec@ext_packed_depth_stencil@fbo-clear-formats stencil,Fail
+spec@ext_packed_depth_stencil@fbo-clear-formats stencil@GL_DEPTH24_STENCIL8,Fail
+spec@ext_packed_depth_stencil@fbo-clear-formats stencil@GL_DEPTH_STENCIL,Fail
+spec@ext_packed_depth_stencil@fbo-depthstencil-gl_depth24_stencil8-blit,Fail
+spec@ext_packed_depth_stencil@fbo-depthstencil-gl_depth24_stencil8-copypixels,Fail
+spec@ext_packed_depth_stencil@fbo-stencil-gl_depth24_stencil8-blit,Fail
+spec@ext_packed_depth_stencil@fbo-stencil-gl_depth24_stencil8-copypixels,Fail
+
+# XFB failure due to (possibly) vtxcnt wrong
+spec@!opengl es [email protected],Fail
+spec@arb_transform_feedback2@change objects while paused,Fail
+spec@arb_transform_feedback2@change objects while paused (gles3),Fail
+spec@arb_transform_feedback3@gl_nextbuffer-gl_nextbuffer,Crash
+spec@arb_transform_feedback_instanced@draw-auto instanced,Fail
+spec@ext_transform_feedback2@draw-auto,Fail
+spec@ext_transform_feedback@change-size base-shrink,Fail
+spec@ext_transform_feedback@change-size offset-shrink,Fail
+spec@ext_transform_feedback@change-size range-grow,Fail
+spec@ext_transform_feedback@change-size range-shrink,Fail
+spec@ext_transform_feedback@generatemipmap prims_generated,Fail
+spec@ext_transform_feedback@interleaved-attribs,Fail
+spec@ext_transform_feedback@intervening-read output,Fail
+spec@ext_transform_feedback@max-varyings,Fail
+spec@ext_transform_feedback@max-varyings@max-varying-arrays-of-arrays,Fail
+spec@ext_transform_feedback@max-varyings@max-varying-single-dimension-array,Fail
+spec@ext_transform_feedback@overflow-edge-cases,Fail
+spec@ext_transform_feedback@position-readback-bufferbase,Fail
+spec@ext_transform_feedback@position-readback-bufferbase-discard,Fail
+spec@ext_transform_feedback@position-readback-bufferoffset,Fail
+spec@ext_transform_feedback@position-readback-bufferoffset-discard,Fail
+spec@ext_transform_feedback@position-readback-bufferrange,Fail
+spec@ext_transform_feedback@position-readback-bufferrange-discard,Fail
+spec@ext_transform_feedback@position-render-bufferbase,Fail
+spec@ext_transform_feedback@position-render-bufferbase-discard,Fail
+spec@ext_transform_feedback@position-render-bufferoffset,Fail
+spec@ext_transform_feedback@position-render-bufferoffset-discard,Fail
+spec@ext_transform_feedback@separate-attribs,Fail
+spec@ext_transform_feedback@tessellation line_loop flat_first,Fail
+spec@ext_transform_feedback@tessellation line_loop flat_last,Fail
+spec@ext_transform_feedback@tessellation line_loop monochrome,Fail
+spec@ext_transform_feedback@tessellation line_loop smooth,Fail
+spec@ext_transform_feedback@tessellation line_strip flat_first,Fail
+spec@ext_transform_feedback@tessellation line_strip flat_last,Fail
+spec@ext_transform_feedback@tessellation line_strip monochrome,Fail
+spec@ext_transform_feedback@tessellation line_strip smooth,Fail
+spec@ext_transform_feedback@tessellation polygon flat_first,Fail
+spec@ext_transform_feedback@tessellation polygon flat_last,Fail
+spec@ext_transform_feedback@tessellation polygon monochrome,Fail
+spec@ext_transform_feedback@tessellation polygon smooth,Fail
+spec@ext_transform_feedback@tessellation polygon wireframe,Fail
+spec@ext_transform_feedback@tessellation quad_strip flat_first,Fail
+spec@ext_transform_feedback@tessellation quad_strip flat_last,Fail
+spec@ext_transform_feedback@tessellation quad_strip monochrome,Fail
+spec@ext_transform_feedback@tessellation quad_strip smooth,Fail
+spec@ext_transform_feedback@tessellation quad_strip wireframe,Fail
+spec@ext_transform_feedback@tessellation quads flat_first,Fail
+spec@ext_transform_feedback@tessellation quads flat_last,Fail
+spec@ext_transform_feedback@tessellation quads monochrome,Fail
+spec@ext_transform_feedback@tessellation quads smooth,Fail
+spec@ext_transform_feedback@tessellation quads wireframe,Fail
+spec@ext_transform_feedback@tessellation triangle_fan flat_first,Fail
+spec@ext_transform_feedback@tessellation triangle_fan flat_last,Fail
+spec@ext_transform_feedback@tessellation triangle_fan monochrome,Fail
+spec@ext_transform_feedback@tessellation triangle_fan smooth,Fail
+spec@ext_transform_feedback@tessellation triangle_fan wireframe,Fail
+spec@ext_transform_feedback@tessellation triangle_strip flat_first,Fail
+spec@ext_transform_feedback@tessellation triangle_strip flat_last,Fail
+spec@ext_transform_feedback@tessellation triangle_strip monochrome,Fail
+spec@ext_transform_feedback@tessellation triangle_strip smooth,Fail
+spec@ext_transform_feedback@tessellation triangle_strip wireframe,Fail
+
+# 3D layout issues
+[email protected]@execution@texelfetch fs sampler3d 1x129x9-98x129x9,Fail
+[email protected]@execution@texelfetch fs sampler3d 98x129x1-98x129x9,Fail
+[email protected]@execution@texelfetch fs sampler3d 98x1x9-98x129x9,Fail
+
+# No MSAA
+spec@!opengl 3.0@minmax,Fail
+spec@!opengl 3.1@minmax,Fail
+spec@!opengl es 3.0@minmax,Fail
+spec@arb_stencil_texturing@glblitframebuffer corrupts state@gl_texture_2d_multisample,Fail
+spec@arb_stencil_texturing@glblitframebuffer corrupts state@gl_texture_2d_multisample_array,Fail
+spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-atomic,Fail
+spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-atomic@MS4,Fail
+
+# Need to specify more formats as renderable (L/I/LA formats are all renderable on e.g. nouveau)
+spec@ext_packed_float@query-rgba-signed-components,Fail
+
+# Uncategorized piglit failures
+glx@glx-make-current,Fail
+glx@glx-multi-window-single-context,Fail
+glx@glx-query-drawable-glx_fbconfig_id-window,Fail
+glx@glx-swap-pixmap-bad,Fail
+glx@glx-visuals-depth -pixmap,Crash
+glx@glx-visuals-stencil -pixmap,Crash
+glx@glx_arb_create_context_no_error@no error,Fail
+glx@glx_ext_import_context@free context,Fail
+glx@glx_ext_import_context@get context id,Fail
+glx@glx_ext_import_context@get current display,Fail
+glx@glx_ext_import_context@import context- multi process,Fail
+glx@glx_ext_import_context@import context- single process,Fail
+glx@glx_ext_import_context@imported context has same context id,Fail
+glx@glx_ext_import_context@make current- multi process,Fail
+glx@glx_ext_import_context@make current- single process,Fail
+glx@glx_ext_import_context@query context info,Fail
+shaders@glsl-bug-110796,Fail
+shaders@glsl-predication-on-large-array,Fail
+shaders@point-vertex-id divisor,Crash
+shaders@point-vertex-id gl_instanceid,Crash
+shaders@point-vertex-id gl_instanceid divisor,Crash
+shaders@point-vertex-id gl_vertexid,Crash
+shaders@point-vertex-id gl_vertexid divisor,Crash
+shaders@point-vertex-id gl_vertexid gl_instanceid,Crash
+shaders@point-vertex-id gl_vertexid gl_instanceid divisor,Crash
+spec@!opengl [email protected],Fail
+spec@!opengl [email protected],Fail
+spec@!opengl 1.0@rasterpos,Crash
+spec@!opengl 1.1@polygon-mode,Fail
+spec@!opengl 1.1@polygon-mode-facing,Fail
+spec@!opengl 1.1@polygon-mode-offset,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 0: Expected white pixel on bottom edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 0: Expected white pixel on left edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 0: Expected white pixel on right edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 0: Expected white pixel on top edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 1: Expected blue pixel in center,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 2: Expected blue pixel in center,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 3: Expected white pixel on bottom edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 3: Expected white pixel on left edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 3: Expected white pixel on right edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 3: Expected white pixel on top edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 4: Expected white pixel on bottom edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 4: Expected white pixel on left edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 4: Expected white pixel on right edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 4: Expected white pixel on top edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 5: Expected blue pixel in center,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 6: Expected blue pixel in center,Fail
+spec@!opengl 1.4@copy-pixels,Fail
+spec@!opengl 2.0@occlusion-query-discard,Crash
+spec@!opengl [email protected],Fail
+spec@!opengl 3.1@primitive-restart-xfb flush,Fail
+spec@!opengl 3.1@primitive-restart-xfb generated,Fail
+spec@!opengl 3.1@primitive-restart-xfb written,Fail
+spec@arb_direct_state_access@gettextureimage-formats,Crash
+spec@arb_draw_indirect@arb_draw_indirect-transform-feedback,Fail
+spec@arb_draw_indirect@gl_vertexid used with gldrawarraysindirect,Fail
+spec@arb_draw_indirect@gl_vertexid used with gldrawelementsindirect,Fail
+spec@arb_framebuffer_no_attachments@arb_framebuffer_no_attachments-query,Crash
+spec@arb_occlusion_query@occlusion_query_meta_no_fragments,Crash
+spec@arb_point_sprite@arb_point_sprite-interactions 1.0,Fail
+spec@arb_texture_rectangle@1-1-linear-texture,Fail
+spec@egl 1.4@eglterminate then unbind context,Fail
+spec@egl_chromium_sync_control@conformance,Fail
+spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test,Fail
+spec@egl_ext_device_base@conformance,Fail
+spec@egl_ext_device_base@conformance@configless_tests,Fail
+spec@egl_ext_device_base@conformance@pbuffer_tests,Fail
+spec@egl_ext_device_base@conformance@surfaceless_tests,Fail
+spec@egl_ext_protected_content@conformance,Fail
+spec@egl_khr_gl_image@egl_khr_gl_renderbuffer_image-clear-shared-image gl_depth_component24,Fail
+spec@egl_khr_gl_image@egl_khr_gl_renderbuffer_image-clear-shared-image gl_rgba,Fail
+spec@egl_khr_surfaceless_context@viewport,Fail
+spec@egl_mesa_configless_context@basic,Fail
+spec@ext_framebuffer_blit@fbo-blit-check-limits,Fail
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-export,Fail
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_p010,Fail
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_p012,Fail
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_p016,Fail
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_uyvy,Fail
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y210,Fail
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y212,Fail
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y216,Fail
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y412,Fail
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_y416,Fail
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_yuyv,Fail
+spec@ext_occlusion_query_boolean@any-samples,Crash
+spec@ext_texture_integer@fbo-integer,Fail
+[email protected]@execution@temp-array-indexing@glsl-fs-giant-temp-array,Fail
+[email protected]@execution@temp-array-indexing@glsl-vs-giant-temp-array,Fail
+[email protected]@execution@fs-large-local-array-vec2,Fail
+[email protected]@execution@fs-large-local-array-vec3,Fail
+[email protected]@execution@fs-large-local-array-vec4,Fail
+[email protected]@execution@varying-struct-centroid_gles3,Fail
+spec@intel_performance_query@intel_performance_query-issue_2235,Fail
+spec@oes_egl_image_external_essl3@oes_egl_image_external_essl3,Fail
+spec@oes_egl_image_external_essl3@oes_egl_image_external_essl3@oes_egl_image_external_essl3_imageStore,Fail

src/freedreno/ci/freedreno-a420-flakes.txt

@@ -0,0 +1,6 @@
+dEQP-GLES3.functional.shaders.texture_functions.texture(proj)?gradoffset.*sampler2d(array)?shadow.*_vertex
+dEQP-GLES3.functional.shaders.texture_functions.texture(proj)?gradoffset.*sampler3d.*_vertex
+
+glx@glx-swap-event_interval
+glx@glx-swap-event_async
+glx@glx_arb_sync_control@swapbuffersmsc-divisor-zero

src/freedreno/ci/freedreno-a420-skips.txt

@@ -0,0 +1,47 @@
+# These are tremendously slow (pushing toward a minute), and aren't
+# reliable to be run in parallel with other tests due to CPU-side timing.
+dEQP-GLES[0-9]*.functional.flush_finish.*
+
+# Times out
+dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.36
+
+# Takes more than a few minutes, time is spent in batch_draw_tracking().
+KHR-GLES31.core.shader_image_load_store.basic-allFormats-store-fs
+
+# no msaa support
+.*msaa.*
+.*multisample.*
+
+# Skip over a bunch of extensions since we don't have extension fast skipping yet.
+[email protected]
+spec@glsl-4.*
+spec@arb_gpu_shader5
+spec@arb_gpu_shader_fp64
+spec@arb_gpu_shader_int64
+spec@arb_tessellation_shader
+
+# 1.5 minutes
+spec@!opengl 1.2@tex3d-maxsize
+
+# ~1 minute
+glx@glx-multithread-texture
+spec@!opengl 1.1@draw-sync
+[email protected]@execution@texelfetch fs sampler2d 1x281-501x281
+[email protected]@execution@texelfetch fs sampler2darray 98x1x9-98x129x9
+[email protected]@execution@texelfetch fs sampler2darray 1x129x9-98x129x9
+
+# If we let these tests run in parallel with other piglit tests, we end up
+# intermittent GL_OUT_OF_MEMORY errors in innocent tests.
+arb_texture_buffer_object@max-size
+fbo-maxsize
+max-texture-size
+tex3d-maxsize
+copypixels-draw-sync
+
+# Unsupported legacy gl features
+.*edgeflag.*
+.*stipple.*
+# uses edgeflags:
+shaders@point-vertex-id.*
+# uses stipple:
+spec@!opengl [email protected]

src/freedreno/ci/freedreno-a530-flakes.txt

@@ -0,0 +1,178 @@
+# Note: flakes lists for CI are just a list of lines that, when
+# non-zero-length and not starting with '#', will regex match to
+# delete lines from the test list.  Be careful.
+
+# unstable results (probably related to the iommu faults).
+dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_msaa_stencil
+dEQP-GLES3.functional.texture.filtering.3d.*
+dEQP-GLES3.functional.texture.vertex.3d.filtering.*
+dEQP-GLES31.functional.ubo.2_level_struct_array.single_buffer.packed_instance_array_fragment
+
+# unstable results once we enabled SMP -- some state not being reset reliably?
+dEQP-GLES3.functional.transform_feedback.*
+
+dEQP-GLES3.functional.fragment_ops.interaction.basic_shader.70
+
+# First appeared 2021-06-11 on an unrelated MR.
+dEQP-GLES31.functional.image_load_store.3d.load_store.*_single_layer
+
+# Separate shader and atomics flakiness increased since bfeb0983d3b3 ("ci/freedreno: Disable flaky a530 for now.")
+dEQP-GLES31.functional.separate_shader.*
+
+KHR-GLES31.core.compute_shader.resource-image
+
+# Occasionally passes
+KHR-GLES31.core.arrays_of_arrays.InteractionFunctionCalls1
+KHR-GLES31.core.arrays_of_arrays.InteractionFunctionCalls2
+
+# Occasionally passes
+KHR-GLES31.core.layout_binding.buffer_layout_binding_atomicAdd_ComputeShader
+KHR-GLES31.core.layout_binding.buffer_layout_binding_atomicAdd_FragmentShader
+
+KHR-GLES31.core.framebuffer_no_attachments.render
+
+# " Counter value is 1024 should be 896."
+# 1. Create atomic counter buffers and init them with start values.
+# 2. Increment (decrement) buffer values in the shader.
+# 3. Map buffers with MapBufferRange command. Increment (decrement) buffer values manually.
+# 4. Unmap buffers with UnmapBuffer command.
+# 5. Again increment (decrement) buffer values in the shader.
+# Verify that this scenario works as expected and final values in the buffer objects are correct.
+KHR-GLES31.core.shader_atomic_counters.advanced-usage-draw-update-draw
+
+KHR-GLES31.core.shader_image_load_store.basic-allTargets-atomicCS
+KHR-GLES31.core.shader_image_load_store.basic-glsl-misc-cs
+KHR-GLES31.core.shader_storage_buffer_object.advanced-switchBuffers-cs
+KHR-GLES31.core.shader_storage_buffer_object.advanced-switchPrograms-cs
+KHR-GLES31.core.shader_storage_buffer_object.basic-syntax-cs
+
+# Flaky since around Feb 26, first appearing on a seemingly-unrelated CI change
+# (ci-fd-fastboot-nfs)
+dEQP-GLES31.functional.synchronization.inter_call.without_memory_barrier.*
+
+glx@glx-swap-event_interval
+glx@glx_arb_sync_control@swapbuffersmsc-divisor-zero
+glx@glx_arb_sync_control@waitformsc
+glx@glx-multithread-texture
+glx@glx-swap-event_async
+shaders@glsl-uniform-interstage-limits@subdivide 5
+spec@!opengl [email protected]
+spec@!opengl_1.1@texsubimage
+spec@!opengl 1.1@user-clip
+spec@arb_depth_texture@fbo-depth-gl_depth_component24-copypixels
+spec@arb_framebuffer_object@fbo-drawbuffers-none glblendfunci
+spec@arb_pixel_buffer_object@texsubimage pbo
+spec@arb_vertex_type_2_10_10_10_rev@attribs
+spec@ext_packed_depth_stencil@fbo-depthstencil-gl_depth24_stencil8-drawpixels-24_8
+spec@arb_texture_cube_map_array@texsubimage cube_map_array
+
+# Flakes since around when the go-fast branch landed
+spec@arb_copy_buffer@copy_buffer_coherency
+.*tex-miplevel-selection.*
+.*glsl-1.30@execution@texelfetch.*
+
+# Flakes since introduction of piglit testing, possibly increased in frequency
+# around Apr 16 or more likely Apr 23
+spec@arb_texture_gather@texturegather.*
+
+# Flakes since around Apr 30th on a clearly innocent MR.
+.*texwrap.formats.*bordercolor
+
+# First flake on Apr 29th on a clearly innocent MR
+spec@arb_direct_state_access@dsa-textures
+spec@arb_depth_buffer_float@depthstencil-render-miplevels_292_ds=z32f_s8
+
+# First flaked on May 3 on a clearly innocent MR.
+spec@arb_draw_instanced@arb_draw_instanced-drawarrays
+
+# Intermittent crashes.  First flaked on May 11th in the piglit 3351e8952
+# uprev, so presumably it regressed some time earlier and then showed up in the
+# piglit reshuffle.
+spec@arb_copy_buffer@intra-buffer-copy
+spec@arb_copy_buffer@dlist
+
+# Intermittent failure, mostly passes but sometimes fails. Was noticed on May 26th.
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_yvu420
+
+# Crashes, possibly after the final piglit report caught by new piglit runner.
+spec@ext_transform_feedback@api-errors.*
+
+spec@!opengl [email protected]
+
+# appeared with a piglit uprev, probably from reshuffling.
+spec@!opengl 1.1@depthstencil-default_fb-copypixels
+spec@arb_direct_state_access@gettextureimage-formats
+spec@ext_polygon_offset_clamp@ext_polygon_offset_clamp-draw_gles2
+spec@ext_polygon_offset_clamp@ext_polygon_offset_clamp-draw_gles2@negative clamp
+
+dEQP-GLES31.functional.texture.multisample.samples_1.use_texture_depth_2d
+
+# 1/10 run flake
+dEQP-GLES31.functional.atomic_counter.layout.default_offset_set.inc_dec.8_counters_5_calls_1_thread
+dEQP-GLES31.functional.compute.indirect_dispatch.gen_in_compute.multi_dispatch_reuse_command
+
+KHR-GLES31.core.explicit_uniform_location.uniform-loc-types-samplers
+KHR-GLES31.core.internalformat.copy_tex_image.alpha
+KHR-GLES31.core.internalformat.texture2d.red_integer_int_r32i
+KHR-GLES31.core.internalformat.texture2d.rgb_integer_byte_rgb8i
+KHR-GLES31.core.internalformat.texture2d.rgb_integer_int_rgb32i
+
+[email protected]@execution@built-in-functions@fs-all-bvec4
+[email protected]@execution@built-in-functions@fs-op-assign-add-ivec4-int
+[email protected]@execution@built-in-functions@fs-max-vec2-vec2
+[email protected]@execution@built-in-functions@vs-acos-vec3
+[email protected]@execution@built-in-functions@vs-dot-vec2-vec2
+[email protected]@execution@built-in-functions@vs-dot-vec3-vec3
+[email protected]@execution@built-in-functions@vs-op-add-mat4-mat4
+[email protected]@execution@built-in-functions@vs-mod-float-float
+[email protected]@execution@copy-propagation@glsl-copy-propagation-self-1
+[email protected]@execution@copy-propagation@glsl-vs-double-negative-copy-propagation
+[email protected]@execution@variable-indexing@fs-varying-mat2-rd
+[email protected]@execution@vs-mat2-array-assignment
+[email protected]@execution@vs-nested-return-sibling-loop2
+[email protected]@execution@built-in-functions@fs-matrixcompmult-mat4x2-mat4x2
+[email protected]@execution@built-in-functions@vs-op-ne-mat2x4-mat2x4-using-if
+[email protected]@execution@built-in-functions@vs-op-neg-mat3x4
+[email protected]@execution@clipping@vs-clip-vertex-different-from-position
+[email protected]@execution@const-builtin@glsl-const-builtin-distance
+[email protected]@execution@const-builtin@glsl-const-builtin-derivatives
+[email protected]@execution@fs-vec4-const-array-indirect-access-128-elements
+[email protected]@execution@vs-outerproduct-const-mat3x4
+[email protected]@execution@uniform-initializer@fs-int-set-by-other-stage
+[email protected]@execution@built-in-functions@fs-abs-ivec2
+[email protected]@execution@built-in-functions@fs-cosh-vec4
+[email protected]@execution@built-in-functions@fs-op-bitand-not-abs-int-ivec3
+[email protected]@execution@built-in-functions@fs-op-bitor-not-abs-int-ivec2
+[email protected]@execution@built-in-functions@fs-op-bitxor-neg-ivec3-int
+[email protected]@execution@built-in-functions@fs-op-bitxor-ivec3-ivec3
+[email protected]@execution@built-in-functions@fs-op-bitxor-uint-uvec3
+[email protected]@execution@built-in-functions@vs-lessthanequal-uvec4-uvec4
+[email protected]@execution@built-in-functions@vs-op-assign-lshift-uvec2-ivec2
+[email protected]@execution@built-in-functions@vs-op-bitand-abs-neg-ivec3-ivec3
+[email protected]@execution@built-in-functions@vs-op-bitor-abs-neg-ivec2-int
+[email protected]@execution@built-in-functions@vs-op-bitxor-neg-abs-ivec4-ivec4
+[email protected]@execution@built-in-functions@vs-op-ne-uvec2-uvec2-using-if
+[email protected]@execution@interpolation@interpolation-smooth-other-flat-distance
+[email protected]@execution@built-in-functions@const-packhalf2x16
+[email protected]@execution@varying-struct-copy-return-vs
+spec@arb_texture_query_levels@execution@fs-miptree
+spec@amd_shader_trinary_minmax@execution@built-in-functions@fs-max3-vec2-vec2-vec2
+spec@arb_uniform_buffer_object@execution@shared-row_major-array-mat2x2-and-column_major-array-mat2x2
+spec@mesa_shader_integer_functions@execution@built-in-functions@fs-umulextended-only-msb-nonuniform
+# ci-collate: Issue found in https://gitlab.freedesktop.org/mesa/mesa/-/jobs/49445812
+KHR-GLES31.core.compute_shader.simple-compute-shared_context
+
+# uprev Piglit in Mesa
+KHR-GLES31.core.compute_shader.simple-compute-shared_context-persistent-buffer
+spec@arb_point_parameters@arb_point_parameters-point-attenuation
+
+# With linux kernel 6.13-rc4 uprev
+dEQP-GLES2.functional.shaders.operator.unary_operator.pre_decrement_effect.highp_float_fragment
+KHR-GLES31.core.arrays_of_arrays.SizedDeclarationsPrimitive
+
+# New flakes with ES CTS 3.2.12.0
+KHR-GLES31.core.compute_shader.simple-compute-shared_context-persistent-buffer
+
+# New flakes while the device was offline
+dEQP-GLES31.functional.atomic_counter.dec.8_counters_5_calls_10_threads
+dEQP-GLES31.functional.shaders.builtin_functions.precision.*

src/freedreno/ci/freedreno-a530-skips.txt

@@ -0,0 +1,120 @@
+# Note: skips lists for CI are just a list of lines that, when
+# non-zero-length and not starting with '#', will regex match to
+# delete lines from the test list.  Be careful.
+
+# no Vulkan support
+spec@ext_external_objects@vk.*
+
+# Intermittent timeouts in CI (~1/month)
+dEQP-GLES3.functional.shaders.builtin_functions.precision.cosh.mediump_fragment.vec3
+dEQP-GLES3.functional.shaders.builtin_functions.precision.faceforward.lowp_fragment.vec4
+dEQP-GLES3.functional.shaders.builtin_functions.precision.sinh.mediump_vertex.vec3
+dEQP-GLES3.functional.shaders.builtin_functions.precision.tanh.highp_fragment.vec3
+dEQP-GLES31.functional.shaders.builtin_functions.precision.distance.lowp_compute.vec4
+dEQP-GLES31.functional.shaders.builtin_functions.precision.pow.highp_compute.vec3
+dEQP-GLES31.functional.shaders.builtin_functions.precision.sqrt.highp_compute.vec3
+dEQP-GLES31.functional.shaders.builtin_functions.precision.tanh.lowp_compute.vec3
+
+# Takes more than a few minutes, time is spent in batch_draw_tracking().
+KHR-GLES31.core.shader_image_load_store.basic-allFormats-store-fs
+
+# Intermittent timeouts
+spec@ext_texture_lod_bias@lodbias
+spec@!opengl [email protected]
+
+# Skip over a bunch of extensions since we don't have extension fast skipping yet.
+[email protected]
+spec@glsl-4.*
+spec@arb_gpu_shader5
+spec@arb_gpu_shader_fp64
+spec@arb_gpu_shader_int64
+spec@arb_tessellation_shader
+
+# Skip flaky piglit MSAA, which is well covered by our xfails in dEQP
+arb_texture_multisample
+ext_framebuffer_multisample
+
+# 1.5 minutes
+spec@!opengl 1.2@tex3d-maxsize
+
+# ~1 minute
+glx@glx-multithread-texture
+spec@!opengl 1.1@draw-sync
+spec@arb_uniform_buffer_object@execution@shared-struct-array-array-array-struct
+spec@arb_uniform_buffer_object@execution@std140-struct-array-array-array-struct
+spec@arb_uniform_buffer_object@execution@std140-array-struct-array-struct
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-refcount-multithread
+
+# This one seems to be triggering faults and causing random other fails
+# depending on what else was running at the time:
+spec@arb_texture_cube_map_array@texsubimage cube_map_array
+spec@arb_pixel_buffer_object@texsubimage cube_map_array pbo
+
+# Causes faults that need the HUPCF fix to actually work to avoid killing the
+# run.
+[email protected]@execution@texelfetch fs sampler3d 98x1x9-98x129x9
+
+# If we let these tests run in parallel with other piglit tests, we end up
+# intermittent GL_OUT_OF_MEMORY errors in innocent tests.
+arb_texture_buffer_object@max-size
+fbo-maxsize
+max-texture-size
+copypixels-draw-sync
+
+# multiple succ/fail
+KHR-GLES31.core.pixelstoragemodes.teximage2d.*
+KHR-GLES31.core.pixelstoragemodes.teximage3d.*
+
+# Hangchecks (copied from a307-skips, first hang matches)
+tex-miplevel-selection
+spec@arb_direct_state_access@transformfeedback-bufferrange
+spec@arb_direct_state_access@transformfeedback-bufferbase
+spec@arb_uniform_buffer_object@rendering-array
+spec@arb_uniform_buffer_object@rendering-array-offset
+spec@arb_point_sprite@arb_point_sprite-interactions
+gles-3.0-transform-feedback-uniform-buffer-object
+
+# additional hangs
+shaders@glsl-uniform-interstage-limits
+spec@arb_color_buffer_float.*
+spec@arb_texture_gather@texturegather.*
+# offending task: copypixels-sync (/piglit/bin/copypixels-sync -auto -fbo)
+spec@!opengl 1.1@copypixels-sync
+# offending task: teximage-colors (/piglit/bin/teximage-colors GL_SRGB8_ALPHA8 -auto -fbo)
+spec@!opengl 1.1@teximage-colors.*
+# offending task: texsubimage (/piglit/bin/texsubimage array pbo -auto -fbo)
+.*texsubimage.*
+# offending task: texelFetch (/piglit/bin/texelFetch fs sampler1DArray 1x71-501x71 -auto -fbo
+spec@ext_gpu_shader4@execution@texelfetch.*
+
+# offending task: texwrap (/piglit/bin/texwrap GL_EXT_texture_integer bordercolor swizzled -auto -fbo)
+#                 texwrap (/piglit/bin/texwrap GL_ARB_texture_float -auto -fbo)
+.*texwrap.*
+
+# offending task: shader_runner (/piglit/bin/shader_runner generated_tests/spec/arb_uniform_buffer_object/execution/shared-array-struct-array-struct.shader_test -auto -fbo)
+shared-array-struct-array-struct
+
+# msm_mdp 901000.display-controller: [drm:a5xx_irq] *ERROR* gpu fault ring 2 fence 8a28 status C5C801C3 rb 004a/004a ib1 0000000002081000/0000 ib2 0000000002091000/0000
+arb_uniform_buffer_object/execution/std140-array-struct-array-struct
+
+# offending task: fbo-clear-forma (/piglit/bin/fbo-clear-formats GL_ARB_depth_buffer_float -auto -fbo
+spec@arb_depth_buffer_float@fbo-clear-formats.*
+# offending task: attribs (/piglit/bin/attribs GL_ARB_vertex_type_2_10_10_10_rev -auto -fbo)
+spec@arb_vertex_type_2_10_10_10_rev@attribs.*
+# offending task: texelFetch (/piglit/bin/texelFetch fs sampler1D 1-513 -auto -fbo)
+[email protected]@execution@texelfetch.*
+
+# offending task: glx-visuals-ste (/piglit/bin/glx-visuals-stencil -auto)
+glx@glx-visuals-stencil.*
+
+# Faults in a way that makes other tests flaky
+# msm_mdp 901000.display-controller: [drm:a5xx_irq] *ERROR* gpu fault ring 2 fence bc846 status 800001C1 rb 004a/004a ib1 000000000634F000/0000 ib2 000000000AA27000/0000
+KHR-GLES31.core.texture_buffer.texture_buffer_atomic_functions
+
+# Unsupported legacy gl features
+.*edgeflag.*
+.*stipple.*
+# uses edgeflags:
+shaders@point-vertex-id.*
+# uses stipple:
+spec@!opengl [email protected]

src/freedreno/ci/freedreno-a618-android-cts-include.txt

@@ -0,0 +1,3 @@
+arm64-v8a CtsGraphicsTestCases
+arm64-v8a CtsNativeHardwareTestCases
+arm64-v8a CtsSkQPTestCases

src/freedreno/ci/freedreno-a618-android-cts-skips.txt

@@ -0,0 +1,6 @@
+# CTS bug? Fails on all drivers with "This device must support the ABP 2021", but not clear what's missing
+arm64-v8a CtsGraphicsTestCases android.graphics.cts.VulkanFeaturesTest#testAndroidBaselineProfile2021Support
+
+# Failed due to non-gfx issues
+arm64-v8a CtsGraphicsTestCases android.graphics.fonts.SystemFontsTest#testFontsFallbackUnreadable[0]
+arm64-v8a CtsGraphicsTestCases android.graphics.fonts.SystemFontsTest#testAvailableFonts_ReadOnlyFile[0]

src/freedreno/ci/freedreno-a618-fails.txt

@@ -0,0 +1,517 @@
+KHR-GL46.shader_image_load_store.basic-allFormats-store,Fail
+KHR-GL46.shading_language_420pack.binding_images,Fail
+
+#
+# new fails with gl45:
+#
+
+spec@!opengl 1.1@getteximage-depth,Fail
+spec@!opengl 1.1@getteximage-depth@GL_TEXTURE_1D-GL_DEPTH_COMPONENT16,Fail
+spec@!opengl 1.1@getteximage-depth@GL_TEXTURE_1D-GL_DEPTH_COMPONENT32,Fail
+spec@!opengl 1.1@getteximage-depth@GL_TEXTURE_1D_ARRAY-GL_DEPTH_COMPONENT16,Fail
+spec@!opengl 1.1@getteximage-depth@GL_TEXTURE_1D_ARRAY-GL_DEPTH_COMPONENT32,Fail
+
+spec@arb_depth_buffer_float@fbo-generatemipmap-formats,Fail
+spec@arb_depth_buffer_float@fbo-generatemipmap-formats@GL_DEPTH_COMPONENT32F,Fail
+spec@arb_depth_buffer_float@fbo-generatemipmap-formats@GL_DEPTH_COMPONENT32F NPOT,Fail
+
+spec@arb_point_sprite@arb_point_sprite-interactions 1.0,Fail
+spec@arb_program_interface_query@arb_program_interface_query-getprogramresourceindex,Fail
+spec@arb_program_interface_query@arb_program_interface_query-getprogramresourceindex@'vs_input2' on GL_PROGRAM_INPUT,Fail
+spec@arb_sample_shading@samplemask [email protected] mask_in_one,Fail
+spec@arb_sample_shading@samplemask [email protected] mask_in_one,Fail
+spec@arb_sample_shading@samplemask 2 [email protected] mask_in_one,Fail
+spec@arb_sample_shading@samplemask 2 [email protected] mask_in_one,Fail
+spec@arb_sample_shading@samplemask 2 all,Fail
+spec@arb_sample_shading@samplemask 2 all@noms mask_in_one,Fail
+spec@arb_sample_shading@samplemask 2 all@sample mask_in_one,Fail
+spec@arb_sample_shading@samplemask 2,Fail
+spec@arb_sample_shading@samplemask 2@noms mask_in_one,Fail
+spec@arb_sample_shading@samplemask 2@sample mask_in_one,Fail
+spec@arb_sample_shading@samplemask [email protected] mask_in_one,Fail
+spec@arb_sample_shading@samplemask [email protected] mask_in_one,Fail
+spec@arb_sample_shading@samplemask [email protected] mask_in_one,Fail
+spec@arb_sample_shading@samplemask 4 [email protected] mask_in_one,Fail
+spec@arb_sample_shading@samplemask 4 [email protected] mask_in_one,Fail
+spec@arb_sample_shading@samplemask 4 [email protected] mask_in_one,Fail
+spec@arb_sample_shading@samplemask 4 all,Fail
+spec@arb_sample_shading@samplemask 4 all@noms mask_in_one,Fail
+spec@arb_sample_shading@samplemask 4 all@sample mask_in_one,Fail
+spec@arb_sample_shading@samplemask 4,Fail
+spec@arb_sample_shading@samplemask 4@noms mask_in_one,Fail
+spec@arb_sample_shading@samplemask 4@sample mask_in_one,Fail
+
+# Same results w/ zink-on-tu as with freedreno:
+spec@arb_post_depth_coverage@arb_post_depth_coverage-multisampling,Fail
+spec@arb_sample_shading@samplemask 2 all@noms partition,Fail
+spec@arb_sample_shading@samplemask 2@noms partition,Fail
+spec@arb_sample_shading@samplemask 4 all@noms partition,Fail
+spec@arb_sample_shading@samplemask 4@noms partition,Fail
+
+# These 3 fails started to happen after piglit uprev with commit
+# 0ef03f824d1833a853d1a20b4be121089bb9246c
+spec@arb_shader_image_load_store@qualifiers,Fail
+spec@arb_shader_image_load_store@qualifiers@r8/permissive layout qualifiers/permissive access qualifiers/permissive binding test,Fail
+spec@arb_shader_image_load_store@qualifiers@r8/permissive layout qualifiers/strict access qualifiers/permissive binding test,Fail
+spec@arb_shader_image_load_store@qualifiers@r8/strict layout qualifiers/permissive access qualifiers/permissive binding test,Fail
+spec@arb_shader_image_load_store@qualifiers@r8/strict layout qualifiers/strict access qualifiers/permissive binding test,Fail
+
+spec@arb_texture_rectangle@1-1-linear-texture,Fail
+
+spec@arb_vertex_type_2_10_10_10_rev@attrib-p-type-size-match,Fail
+
+# fails on gen1 (a618/a630) with both fd and zink, but passes on gen4..
+# maybe gen1 sqe doesn't handle the count==0 case?
+spec@arb_indirect_parameters@tf-count-arrays,Fail
+spec@arb_indirect_parameters@tf-count-elements,Fail
+
+spec@egl 1.4@eglterminate then unbind context,Fail
+spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test,Fail
+spec@egl_chromium_sync_control@conformance,Fail
+spec@egl_khr_surfaceless_context@viewport,Fail
+spec@egl_mesa_configless_context@basic,Fail
+
+# D32S8 skips (GL_FRAMEBUFFER_INCOMPLETE_ATTACHMENT), others fail.
+# The test is importing a z buffer from tu, and rendering a blue fullscreen quad
+# in gl that zfails to leave the green clear color in the middle.
+#
+# TU sysmem mode gets green on the bottom half-ish with some noise at the boundary.
+# TU gmem mode gets fullscreen green.
+spec@ext_external_objects@vk-depth-display,Fail
+spec@ext_external_objects@vk-depth-display@D16,Fail
+spec@ext_external_objects@vk-depth-display@D24S8,Fail
+spec@ext_external_objects@vk-depth-display@D32S8,Fail
+spec@ext_external_objects@vk-stencil-display,Fail
+spec@ext_external_objects@vk-stencil-display@D32S8,Fail
+spec@ext_external_objects@vk-stencil-display@D24S8,Fail
+
+spec@ext_framebuffer_multisample@alpha-to-coverage-dual-src-blend 2,Fail
+spec@ext_framebuffer_multisample@alpha-to-coverage-dual-src-blend 4,Fail
+spec@ext_framebuffer_multisample@alpha-to-coverage-no-draw-buffer-zero 2,Fail
+spec@ext_framebuffer_multisample@alpha-to-coverage-no-draw-buffer-zero 4,Fail
+spec@ext_framebuffer_multisample@draw-buffers-alpha-to-coverage 2,Fail
+spec@ext_framebuffer_multisample@draw-buffers-alpha-to-coverage 4,Fail
+spec@ext_framebuffer_multisample@enable-flag,Fail
+spec@ext_framebuffer_multisample@interpolation 2 centroid-deriv-disabled,Fail
+spec@ext_framebuffer_multisample@interpolation 2 centroid-disabled,Fail
+spec@ext_framebuffer_multisample@interpolation 2 non-centroid-deriv-disabled,Fail
+spec@ext_framebuffer_multisample@interpolation 2 non-centroid-disabled,Fail
+spec@ext_framebuffer_multisample@interpolation 4 centroid-deriv-disabled,Fail
+spec@ext_framebuffer_multisample@interpolation 4 centroid-disabled,Fail
+spec@ext_framebuffer_multisample@interpolation 4 non-centroid-deriv-disabled,Fail
+spec@ext_framebuffer_multisample@interpolation 4 non-centroid-disabled,Fail
+spec@ext_framebuffer_multisample@sample-alpha-to-coverage 2 color,Fail
+spec@ext_framebuffer_multisample@sample-alpha-to-coverage 2 depth,Fail
+spec@ext_framebuffer_multisample@sample-alpha-to-coverage 4 color,Fail
+spec@ext_framebuffer_multisample@sample-alpha-to-coverage 4 depth,Fail
+spec@ext_framebuffer_object@fbo-alphatest-nocolor,Fail
+spec@ext_framebuffer_object@fbo-alphatest-nocolor-ff,Fail
+
+spec@ext_transform_feedback@tessellation triangle_fan flat_first,Fail
+spec@ext_transform_feedback@tessellation triangle_strip flat_first,Fail
+[email protected]@execution@texelfetch fs sampler3d 1x129x9-98x129x9,Fail
+[email protected]@execution@texelfetch fs sampler3d 98x1x9-98x129x9,Fail
+
+[email protected]@execution@primitive-id-no-gs-quads,Fail
+[email protected]@execution@primitive-id-no-gs-quad-strip,Fail
+
+# "ir3_shader.h:923:ir3_link_add: Assertion `i < ARRAY_SIZE(l->var)' failed"
+[email protected]@execution@variable-indexing@gs-output-array-vec4-index-wr,Crash
+
+spec@khr_texture_compression_astc@array-gl@12x12 Block Dim,Fail
+spec@khr_texture_compression_astc@array-gl@5x5 Block Dim,Fail
+spec@khr_texture_compression_astc@array-gles@12x12 Block Dim,Fail
+spec@khr_texture_compression_astc@array-gles@5x5 Block Dim,Fail
+spec@khr_texture_compression_astc@array-gles,Fail
+spec@khr_texture_compression_astc@array-gl,Fail
+spec@khr_texture_compression_astc@miptree-gles hdr,Fail
+spec@khr_texture_compression_astc@miptree-gles hdr@HDR Profile,Fail
+spec@khr_texture_compression_astc@miptree-gles ldr,Fail
+spec@khr_texture_compression_astc@miptree-gles ldr@LDR Profile,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb-sd,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb-sd@sRGB skip decode,Fail
+spec@khr_texture_compression_astc@miptree-gl hdr,Fail
+spec@khr_texture_compression_astc@miptree-gl hdr@HDR Profile,Fail
+spec@khr_texture_compression_astc@miptree-gl ldr,Fail
+spec@khr_texture_compression_astc@miptree-gl ldr@LDR Profile,Fail
+spec@khr_texture_compression_astc@miptree-gl srgb-fp,Fail
+spec@khr_texture_compression_astc@miptree-gl srgb-fp@sRGB decode full precision,Fail
+spec@khr_texture_compression_astc@miptree-gl srgb-sd,Fail
+spec@khr_texture_compression_astc@miptree-gl srgb-sd@sRGB skip decode,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles hdr,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles hdr@HDR Profile,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl hdr,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl hdr@HDR Profile,Fail
+
+spec@oes_egl_image_external_essl3@oes_egl_image_external_essl3@oes_egl_image_external_essl3_imageStore,Fail
+spec@oes_egl_image_external_essl3@oes_egl_image_external_essl3,Fail
+
+# "Failure with Polygon Stipple set to fail mode."
+spec@!opengl [email protected],Fail
+
+spec@!opengl 1.0@rasterpos,Fail
+spec@!opengl 1.0@rasterpos@glsl_vs_gs_linked,Fail
+spec@!opengl 1.0@rasterpos@glsl_vs_tes_linked,Fail
+
+spec@!opengl 1.1@polygon-mode-facing,Fail
+spec@!opengl 1.1@polygon-mode,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 0: Expected white pixel on bottom edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 0: Expected white pixel on left edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 0: Expected white pixel on right edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 0: Expected white pixel on top edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 1: Expected blue pixel in center,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 2: Expected blue pixel in center,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 2: Expected white pixel on right edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 2: Expected white pixel on top edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 5: Expected blue pixel in center,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 6: Expected blue pixel in center,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 6: Expected white pixel on right edge,Fail
+spec@!opengl 1.1@polygon-mode-offset@config 6: Expected white pixel on top edge,Fail
+spec@!opengl 1.1@polygon-mode-offset,Fail
+spec@!opengl [email protected],Fail
+
+
+spec@!opengl 2.1@pbo,Fail
+spec@!opengl 2.1@pbo@test_polygon_stip,Fail
+spec@!opengl [email protected] cull-back pv-first,Fail
+spec@!opengl [email protected] cull-front pv-first,Fail
+spec@!opengl [email protected] line cull-back pv-first,Fail
+spec@!opengl [email protected] line cull-front pv-first,Fail
+spec@!opengl [email protected] pv-first,Fail
+
+spec@!opengl 1.0@depth-clear-precision-check,Fail
+spec@!opengl 1.0@depth-clear-precision-check@depth24,Fail
+spec@!opengl 1.0@depth-clear-precision-check@depth24_stencil8,Fail
+spec@!opengl 1.0@depth-clear-precision-check@depth32,Fail
+
+spec@arb_gpu_shader5@arb_gpu_shader5-interpolateatsample-dynamically-nonuniform,Fail
+spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams,Fail
+spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams-without-invocations,Fail
+spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams-without-invocations spirv,Fail
+spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams@arb_gpu_shader5-xfb-streams,Fail
+spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams@arb_gpu_shader5-xfb-streams-blocks,Fail
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-inverse-dmat4,Fail
+spec@arb_gpu_shader_fp64@[email protected],Fail
+[email protected]@execution@built-in-functions@fs-op-div-double-dmat4,Fail
+
+[email protected]@execution@built-in-functions@fs-op-div-dmat4-dmat4,Fail
+
+# uprev Piglit in Mesa
+glx@glx-swap-pixmap-bad,Fail
+spec@!opengl 1.0@rasterpos@glsl_vs_ssbo,Fail
+spec@arb_occlusion_query@occlusion_query_order,Fail
+spec@arb_gpu_shader_fp64@execution@fs-indirect-temp-double-src,Crash
+[email protected]@execution@fs-uint-to-float-of-extract-int16,Fail
+[email protected]@execution@fs-uint-to-float-of-extract-int8,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb-fp,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb-fp@sRGB decode full precision,Fail
+spec@arb_base_instance@arb_base_instance-baseinstance-doesnt-affect-gl-instance-id,Fail
+spec@arb_base_instance@arb_base_instance-drawarrays,Fail
+spec@ext_base_instance@arb_base_instance-baseinstance-doesnt-affect-gl-instance-id_gles3,Fail
+spec@ext_base_instance@arb_base_instance-drawarrays_gles3,Fail
+
+# New failures appeared after Piglit uprev to 28d1349844eacda869f0f82f551bcd4ac0c4edfe
+spec@arb_gl_spirv@execution@vs-instance-id,Fail
+
+# glcts update
+KHR-GL46.texture_view.view_classes,Fail
+KHR-GLES3.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit,Fail
+KHR-GL46.texture_lod_bias.texture_lod_bias_all,Fail
+
+# New failures with GL CTS 4.6.6.0 & ES CTS 3.2.12.0
+KHR-GLES3.framebuffer_blit.multisampled_to_singlesampled_blit_depth_config_test,Fail
+
+# GL tests above, Vulkan tests below
+
+# New fails in 1.4.3.3
+dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_508,Fail
+dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_508,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_508,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_multiview_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_multiview_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_multiview_counter_offset_508,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_counter_offset_508,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_508,Fail
+android-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_244,Fail
+asan-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_244,Fail
+gmem-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_16,Fail
+gmem-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_multiview_counter_offset_16,Fail
+gmem-dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_508,Fail
+gmem-dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_16,Fail
+nobin-dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_16,Fail
+nobin-dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_244,Fail
+nobin-dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_508,Fail
+nobin-dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_244,Fail
+nobin-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_16,Fail
+nobin-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_multiview_counter_offset_16,Fail
+nobin-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_multiview_counter_offset_244,Fail
+nobin-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_multiview_counter_offset_508,Fail
+nobin-dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_counter_offset_16,Fail
+nobin-dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_counter_offset_244,Fail
+nobin-dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_counter_offset_508,Fail
+nobin-dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_16,Fail
+nobin-dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_244,Fail
+
+# New failures with VKCTS 1.4.4.0
+dEQP-VK.tessellation.misc_draw.tess_factor_barrier_bug,Crash
+gmem-dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_16,Fail
+gmem-dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_508,Fail
+gmem-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_244,Fail
+gmem-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_508,Fail
+gmem-dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_508,Fail
+nobin-dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_16,Fail
+nobin-dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_508,Fail
+nobin-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_244,Fail
+nobin-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_508,Fail
+nobin-dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_508,Fail
+
+# OpenCL tests below
+#
+## rusticl-core issues:
+#
+#Unexpected CL error: CL_BUILD_PROGRAM_FAILURE -11
+#Expected CL error: CL_INVALID_BUILD_OPTIONS -43
+api@clbuildprogram,Fail
+
+#Unexpected CL error: CL_COMPILE_PROGRAM_FAILURE -15
+#Expected CL error: CL_INVALID_COMPILER_OPTIONS -66
+api@clcompileprogram,Fail
+
+#Unexpected CL error: CL_SUCCESS 0
+#Expected CL error: CL_KERNEL_ARG_INFO_NOT_AVAILABLE -19
+api@clgetkernelarginfo,Fail
+
+#Unexpected CL error: CL_SUCCESS 0
+#Expected CL error: CL_INVALID_LINKER_OPTIONS -67
+#Failed (error code: CL_SUCCESS): Trigger CL_INVALID_LINKER_OPTIONS if the linker options specified by options are invalid.
+#Unexpected CL error: CL_LINK_PROGRAM_FAILURE -17
+#Expected CL error: CL_INVALID_OPERATION -59
+#Failed (error code: CL_LINK_PROGRAM_FAILURE): Trigger CL_INVALID_OPERATION if the rules for devices containing compiled binaries or libraries as described in input_programs argument above are not followed.
+#Unexpected CL error: CL_SUCCESS 0
+#Expected CL error: CL_LINK_PROGRAM_FAILURE -17
+api@cllinkprogram,Fail
+
+# can be resolved by RUSTICL_FEATURES=fp16,fp64
+program@build@vector-data-types,Fail
+
+# https://gitlab.freedesktop.org/mesa/mesa/-/issues/8408
+program@execute@global-offset,Fail
+program@execute@global-offset@3d- input dependent,Fail
+
+#
+## freedreno issues:
+#
+#Error at data[0]
+custom@r600 create release buffer bug,Fail
+
+#
+## works on OnePlus 6:
+#
+#Failed: return NULL if platform is not a valid platform
+api@clgetextensionfunctionaddressforplatform,Fail
+
+#
+## Not our problem:
+#
+# CL_DEVICE_MAX_READ_IMAGE_ARGS: failed, expected at least 128, got 16
+api@clgetdeviceinfo,Fail
+
+# CL_QUEUE_SIZE Unexpected CL error: CL_INVALID_COMMAND_QUEUE -36
+api@clgetcommandqueueinfo,Fail
+
+# broken piglit test (doesn't account for FTZ)
+program@execute@[email protected],Fail
+program@execute@[email protected]@nextafter float1,Fail
+program@execute@[email protected]@nextafter float16,Fail
+program@execute@[email protected]@nextafter float2,Fail
+program@execute@[email protected]@nextafter float4,Fail
+program@execute@[email protected]@nextafter float8,Fail
+
+# (file=input,line=0,column=0,index=0): Unresolved external reference to "_Z21convert_char4_sat_rteDv4_i".
+program@execute@vector-conversion,Fail
+
+# Piglit doesn't check subbuffer alignment requirements
+api@clgetmemobjectinfo,Fail
+
+# Piglit checks the pre 3.1 behavior
+api@clsetkernelarg,Fail
+api@clsetkernelarg@Input checks,Fail
+
+# piles of new fails since updating skqp; to be re-evaluated with new upstream
+gl_all_bitmap_configs,Fail
+gl_androidblendmodes,Fail
+gl_annotated_text,Fail
+gl_arithmode,Fail
+gl_bitmapcopy,Fail
+gl_blob_rsxform,Fail
+gl_blurSmallRadii,Fail
+gl_coloremoji_blendmodes,Fail
+gl_colorwheelnative,Fail
+gl_combinemaskfilter,Fail
+gl_dashtextcaps,Fail
+gl_degenerate_gradients,Fail
+gl_draw-atlas-colors,Fail
+gl_encode,Fail
+gl_gammagradienttext,Fail
+gl_gammatext,Fail
+gl_gpusamplerstress,Fail
+gl_gradtext,Fail
+gl_highcontrastfilter,Fail
+gl_image-surface,Fail
+gl_imageblur2,Fail
+gl_imageblur_large,Fail
+gl_imageblurtiled,Fail
+gl_lcdblendmodes,Fail
+gl_lcdtextsize,Fail
+gl_scaled_tilemode_bitmap,Fail
+gl_scaled_tilemode_gradient,Fail
+gl_scaled_tilemodes,Fail
+gl_simpleaaclip_aaclip,Fail
+gl_skbug_5321,Fail
+gl_srcmode,Fail
+gl_surfaceprops,Fail
+gl_textblob_intercepts,Fail
+gl_textblobblockreordering,Fail
+gl_textblobcolortrans,Fail
+gl_textfilter_color,Fail
+gl_textfilter_image,Fail
+gl_tilemode_bitmap,Fail
+gl_typefacestyles,Fail
+gl_wacky_yuv_formats,Fail
+gl_wacky_yuv_formats_cs,Fail
+gl_xfermodes2,Fail
+gl_xfermodes3,Fail
+# GLES failures started when EXT_mdi was properly exposed
+gles_all_bitmap_configs,Fail
+gles_androidblendmodes,Fail
+gles_annotated_text,Fail
+gles_arithmode,Fail
+gles_bitmapcopy,Fail
+gles_blob_rsxform,Fail
+gles_blurSmallRadii,Fail
+gles_coloremoji_blendmodes,Fail
+gles_colorwheelnative,Fail
+gles_combinemaskfilter,Fail
+gles_dashtextcaps,Fail
+gles_degenerate_gradients,Fail
+gles_draw-atlas-colors,Fail
+gles_encode,Fail
+gles_gammagradienttext,Fail
+gles_gammatext,Fail
+gles_gpusamplerstress,Fail
+gles_gradtext,Fail
+gles_highcontrastfilter,Fail
+gles_image-surface,Fail
+gles_imageblur2,Fail
+gles_imageblur_large,Fail
+gles_imageblurtiled,Fail
+gles_lcdblendmodes,Fail
+gles_lcdtextsize,Fail
+gles_scaled_tilemode_bitmap,Fail
+gles_scaled_tilemode_gradient,Fail
+gles_scaled_tilemodes,Fail
+gles_simpleaaclip_aaclip,Fail
+gles_skbug_5321,Fail
+gles_srcmode,Fail
+gles_surfaceprops,Fail
+gles_textblob_intercepts,Fail
+gles_textblobblockreordering,Fail
+gles_textblobcolortrans,Fail
+gles_textfilter_color,Fail
+gles_textfilter_image,Fail
+gles_tilemode_bitmap,Fail
+gles_typefacestyles,Fail
+gles_wacky_yuv_formats,Fail
+gles_wacky_yuv_formats_cs,Fail
+gles_xfermodes2,Fail
+gles_xfermodes3,Fail
+vk_all_bitmap_configs,Fail
+vk_androidblendmodes,Fail
+vk_annotated_text,Fail
+vk_arithmode,Fail
+vk_bitmapcopy,Fail
+vk_blob_rsxform,Fail
+vk_blurSmallRadii,Fail
+vk_coloremoji_blendmodes,Fail
+vk_colorwheelnative,Fail
+vk_combinemaskfilter,Fail
+vk_dashtextcaps,Fail
+vk_degenerate_gradients,Fail
+vk_draw-atlas-colors,Fail
+vk_encode,Fail
+vk_gammagradienttext,Fail
+vk_gammatext,Fail
+vk_gpusamplerstress,Fail
+vk_gradtext,Fail
+vk_highcontrastfilter,Fail
+vk_image-surface,Fail
+vk_imageblur2,Fail
+vk_imageblur_large,Fail
+vk_imageblurtiled,Fail
+vk_lcdblendmodes,Fail
+vk_lcdtextsize,Fail
+vk_scaled_tilemode_bitmap,Fail
+vk_scaled_tilemode_gradient,Fail
+vk_scaled_tilemodes,Fail
+vk_simpleaaclip_aaclip,Fail
+vk_skbug_5321,Fail
+vk_srcmode,Fail
+vk_surfaceprops,Fail
+vk_textblob_intercepts,Fail
+vk_textblobblockreordering,Fail
+vk_textblobcolortrans,Fail
+vk_textfilter_color,Fail
+vk_textfilter_image,Fail
+vk_tilemode_bitmap,Fail
+vk_typefacestyles,Fail
+vk_wacky_yuv_formats,Fail
+vk_wacky_yuv_formats_cs,Fail
+vk_xfermodes2,Fail
+vk_xfermodes3,Fail
+
+# Initial ANGLE failures
+angle-dEQP-GLES2.functional.shaders.algorithm.rgb_to_hsl_vertex,Fail
+
+# Early-fragment multisample autotune regressions
+dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_alpha_to_coverage_samples_2_maintenance5,Fail
+dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_alpha_to_coverage_samples_4_maintenance5,Fail
+dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_samples_2,Fail
+dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_samples_2_maintenance5,Fail
+dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_samples_4,Fail
+dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_samples_4_maintenance5,Fail
+
+# Autotune regression
+angle-dEQP-GLES3.functional.fbo.msaa.2_samples.rg8,Fail
+angle-dEQP-GLES3.functional.fbo.msaa.4_samples.rg8,Fail
+
+# VKCTS 1.4.4.2 -> 1.4.5.3 uprev.
+# [  118.945672] *** gpu fault: ttbr0=00000001d0f38000 iova=00000000040ff000 dir=READ type=TRANSLATION source=TP|VFD (0,0,0,1)
+# Not entirely reliable -- which ones crash vs pass may flip around, so clear the flakes entry when it's fixed.
+dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.custom_resolve.fast_lib.fdm_subsampled_pre_resolve_info_frag_out_only_resolve_info_frag_shader_no_formats,Crash
+dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.custom_resolve.fast_lib.fdm_subsampled_resolve_info_frag_shader_no_formats,Crash
+dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.custom_resolve.fast_lib.fdm_subsampled,Crash
+dEQP-VK.renderpasses.renderpass1.custom_resolve.fast_lib.fdm_subsampled,Crash
+dEQP-VK.renderpasses.renderpass1.custom_resolve.monolithic.fdm_subsampled,Crash
+
+# VKCTS 1.4.4.2 -> 1.4.5.3 uprev
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_10,Fail
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_16,Fail
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_17,Fail
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_20,Fail
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_24,Fail
+gmem-dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_24,Fail
+
+# uprev Piglit in Mesa
+spec@!opengl 1.1@large-tex,Fail
+spec@!opengl 1.1@large-tex@test_image_load_store,Fail
+

src/freedreno/ci/freedreno-a618-flakes.txt

@@ -0,0 +1,388 @@
+# Note: flakes lists for CI are just a list of lines that, when
+# non-zero-length and not starting with '#', will regex match to
+# delete lines from the test list.  Be careful.
+
+# dEQP-EGL started flaking around 2021-04-19 on an innocent CI-related branch.
+dEQP-EGL.functional.color_clears.multi_context.gles2.rgb888_pbuffer
+dEQP-EGL.functional.color_clears.multi_context.gles2.rgb888_window
+dEQP-EGL.functional.color_clears.multi_context.gles2.rgba8888_pbuffer
+dEQP-EGL.functional.color_clears.multi_context.gles2.rgba8888_window
+dEQP-EGL.functional.color_clears.multi_context.gles3.rgb888_pbuffer
+dEQP-EGL.functional.color_clears.multi_context.gles3.rgb888_window
+dEQP-EGL.functional.color_clears.multi_context.gles3.rgba8888_pbuffer
+dEQP-EGL.functional.color_clears.multi_context.gles3.rgba8888_window
+dEQP-EGL.functional.color_clears.multi_thread.gles2.rgba8888_pbuffer
+dEQP-EGL.functional.color_clears.multi_thread.gles2.rgba8888_window
+dEQP-EGL.functional.color_clears.multi_thread.gles3.rgb888_pbuffer
+dEQP-EGL.functional.color_clears.multi_thread.gles3.rgb888_window
+dEQP-EGL.functional.color_clears.multi_thread.gles3.rgba8888_pbuffer
+dEQP-EGL.functional.color_clears.multi_thread.gles3.rgba8888_window
+dEQP-EGL.functional.color_clears.single_context.gles2.rgb888_pbuffer
+dEQP-EGL.functional.color_clears.single_context.gles2.rgb888_window
+dEQP-EGL.functional.color_clears.single_context.gles2.rgba8888_pbuffer
+dEQP-EGL.functional.color_clears.single_context.gles2.rgba8888_window
+dEQP-EGL.functional.color_clears.single_context.gles3.rgb888_pbuffer
+dEQP-EGL.functional.color_clears.single_context.gles3.rgb888_window
+dEQP-EGL.functional.color_clears.single_context.gles3.rgba8888_pbuffer
+dEQP-EGL.functional.color_clears.single_context.gles3.rgba8888_window
+dEQP-EGL.functional.render.multi_context.gles2_gles3.rgb888_pbuffer
+dEQP-EGL.functional.render.multi_context.gles2_gles3.rgb888_window
+dEQP-EGL.functional.render.multi_context.gles2_gles3.rgba8888_pbuffer
+dEQP-EGL.functional.render.multi_context.gles2_gles3.rgba8888_window
+dEQP-EGL.functional.render.multi_context.gles2.rgb888_pbuffer
+dEQP-EGL.functional.render.multi_context.gles2.rgb888_window
+dEQP-EGL.functional.render.multi_context.gles2.rgba8888_pbuffer
+dEQP-EGL.functional.render.multi_context.gles2.rgba8888_window
+dEQP-EGL.functional.render.multi_context.gles3.rgb888_pbuffer
+dEQP-EGL.functional.render.multi_context.gles3.rgb888_window
+dEQP-EGL.functional.render.multi_context.gles3.rgba8888_pbuffer
+dEQP-EGL.functional.render.multi_context.gles3.rgba8888_window
+dEQP-EGL.functional.render.multi_thread.gles2_gles3.rgb888_pbuffer
+dEQP-EGL.functional.render.multi_thread.gles2_gles3.rgb888_window
+dEQP-EGL.functional.render.multi_thread.gles2_gles3.rgba8888_pbuffer
+dEQP-EGL.functional.render.multi_thread.gles2_gles3.rgba8888_window
+dEQP-EGL.functional.render.multi_thread.gles2.rgb888_pbuffer
+dEQP-EGL.functional.render.multi_thread.gles2.rgb888_window
+dEQP-EGL.functional.render.multi_thread.gles2.rgba8888_pbuffer
+dEQP-EGL.functional.render.multi_thread.gles2.rgba8888_window
+dEQP-EGL.functional.render.multi_thread.gles3.rgb888_pbuffer
+dEQP-EGL.functional.render.multi_thread.gles3.rgb888_window
+dEQP-EGL.functional.render.multi_thread.gles3.rgba8888_pbuffer
+dEQP-EGL.functional.render.multi_thread.gles3.rgba8888_window
+dEQP-EGL.functional.render.single_context.gles2.rgb888_pbuffer
+dEQP-EGL.functional.render.single_context.gles2.rgb888_window
+dEQP-EGL.functional.render.single_context.gles2.rgba8888_pbuffer
+dEQP-EGL.functional.render.single_context.gles2.rgba8888_window
+dEQP-EGL.functional.render.single_context.gles3.rgb888_pbuffer
+dEQP-EGL.functional.render.single_context.gles3.rgb888_window
+dEQP-EGL.functional.render.single_context.gles3.rgba8888_pbuffer
+dEQP-EGL.functional.render.single_context.gles3.rgba8888_window
+dEQP-EGL.functional.sharing.gles2.buffer.render
+dEQP-EGL.functional.sharing.gles2.multithread.random_egl_server_sync.textures.copyteximage2d.13
+dEQP-EGL.functional.sharing.gles2.multithread.random_egl_sync.textures.copyteximage2d.0
+dEQP-EGL.functional.sharing.gles2.multithread.random.textures.copyteximage2d.16
+dEQP-EGL.functional.sharing.gles2.multithread.simple.buffers.bufferdata
+
+# Started at least by Jan 2020, current as of May 2021
+dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_array
+
+# Started appearing with the new deqp runner.  possibly different test order?
+dEQP-GLES3.functional.fbo.blit.conversion.rg8i_to_r16i
+dEQP-GLES3.functional.fbo.blit.conversion.rg8_to_r16f
+
+# First noticed Jun 1 2020 on an innocent branch.
+KHR-.*.packed_depth_stencil.verify_copy_tex_image.depth32f_stencil8
+
+# Flaky with introduction of testing
+KHR-.*.core.arrays_of_arrays.InteractionFunctionCalls2
+KHR-.*.core.geometry_shader.layered_framebuffer.depth_support
+
+# [  359.031093] *** gpu fault: ttbr0=00000001040d6000 iova=0000001012c0a880 dir=WRITE type=TRANSLATION source=UCHE (0,0,0,1)
+KHR-.*.core.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_calls
+
+# Typically fails, but occasionally passes.
+KHR-GL46.shader_image_load_store.basic-allTargets-loadStoreVS
+KHR-GL46.shader_image_load_store.basic-allTargets-store
+
+# edfff331b3241d1c18d5c589fcdf75728089c886 mostly fixed this, but apparently it still flakes.
+dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_basic
+dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_scale
+dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_stencil_only
+
+# looks like a cache flushing issue, and it does sometimes pass.
+bypass-dEQP-GLES31.functional.blend_equation_advanced.msaa.*
+bypass-dEQP-GLES31.functional.blend_equation_advanced.srgb.difference
+bypass-dEQP-GLES31.functional.blend_equation_advanced.srgb.hsl_color
+bypass-dEQP-GLES31.functional.blend_equation_advanced.srgb.multiply
+
+# Flakes, all seen since merge of:
+# https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258
+# Failures seen so far in different flakes:
+#
+#  "Array 1 length is 0 should be 4"
+#  "Array 2 length is 0 should be 2"
+#  "Array 4 length is 0 should be 22"
+#  "Array 5 length is 0 should be 122"
+#
+# test does a single point draw in a FS taking the length of the first 7 SSBOs and writing them to
+# ints in SSBO 7, then glMemoryBarrier(GL_BUFFER_UPDATE_BARRIER_BIT), then mapping it.
+KHR-.*.core.shader_storage_buffer_object.advanced-unsizedArrayLength-fs-std140-struct
+KHR-.*.core.shader_storage_buffer_object.advanced-unsizedArrayLength-fs-std140-matR
+KHR-.*.core.shader_storage_buffer_object.advanced-unsizedArrayLength-fs-std430-matC-pad
+KHR-.*.core.shader_storage_buffer_object.advanced-unsizedArrayLength-fs-std430-vec
+KHR-.*.shader_storage_buffer_object.advanced-unsizedArrayLength-fs-std140-matR
+
+glx@glx_arb_sync_control@swapbuffersmsc-divisor-zero
+glx@glx_arb_sync_control@waitformsc
+glx@glx-swap-event_interval
+glx@glx-visuals-depth
+glx@glx-visuals-stencil
+
+# Occasionally flakes preceded by a GPU fault;
+#  [  375.034086] adreno 5000000.gpu: [drm:a6xx_irq] *ERROR* gpu fault ring 0 fence aefe8 status 00E51005 rb 0602/06d2 ib1 000000010023D000/0000 ib2 0000000100246170/0000
+glx@glx-tfp
+
+# Flaky since around 2021-03-20.  First appeared on the autotune branch.
+spec@arb_draw_indirect@arb_draw_indirect-transform-feedback
+
+# Flaky since around 2021-03-22.  First appeared on an innocent mingw branch.
+spec@arb_depth_texture@fbo-clear-formats
+
+# Flaky since around 2021-05-21, the day after a piglit uprev reshuffled us.
+# *** gpu fault: ttbr0=000000001c941000 iova=000000010066a000 dir=READ type=TRANSLATION source=TP|VFD (0,0,0,1)
+spec@arb_map_buffer_range@map_invalidate_buffer_bit offset=0
+
+# Always been flaky, but didn't show up until the testscase was fixed to not spuriously skip.
+spec@arb_shader_image_load_store@indexing
+spec@arb_shader_image_load_store@indexing@Fragment shader/dynamically uniform indexing test
+
+# Occasionally passes instead of failing
+spec@egl_chromium_sync_control@conformance
+spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test
+
+# Flaky since around 2021-04-21.  First appeared on
+# https://gitlab.freedesktop.org/robclark/mesa/-/jobs/9101752 (fd/go-fast)
+spec@ext_packed_depth_stencil@fbo-clear-formats stencil
+
+# Flaky since around 2021-06-21.
+spec@arb_texture_gather@texturegatheroffset@vs-rgb-blue-uint-2darray
+spec@arb_texture_gather@texturegather@fs-rgba-green-uint-cubearray
+spec@arb_texture_gather@texturegather@vs-rgb-none-float-cubearray
+
+# First appeared in https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11511
+[email protected]@execution@tex-miplevel-selection texture\(bias\) cubearray
+
+# First appeared on 2021-05-14 on tc-merge-index-unrefs, but not obviously related.
+spec@!opengl 1.0@rasterpos@glsl_vs_tex1D
+
+# Has only flaked where it fails twice in a run, never as a Flake status.
+spec@!opengl 1.0@rasterpos@glsl_vs_ubo
+
+# First appeared 2021-06-14
+spec@egl 1.4@eglcreatepbuffersurface and then glclear
+
+# Flakes collected from June/July 2022 reports, that seem to have been around forever.
+spec@!opengl [email protected]
+spec@!opengl 1.1@masked-clear
+spec@!opengl 1.1@texsubimage
+spec@!opengl 3.0@gl30basic
+spec@arb_texture_multisample@texelfetch fs sampler2dms 4 1x71-501x71
+spec@egl_nok_texture_from_pixmap@basic
+spec@ext_framebuffer_blit@fbo-sys-blit
+spec@ext_framebuffer_blit@fbo-sys-sub-blit
+[email protected]@execution@texelfetch fs sampler2d 1x71-501x71
+
+# Started around 2022-06-26, first time was on an unlikely MR.
+KHR-.*.shader_image_size.basic-nonMS-fs-float
+KHR-.*.shader_image_size.basic-nonMS-fs-int
+KHR-.*.shader_image_size.basic-nonMS-fs-uint
+KHR-.*.shader_image_size.advanced-nonMS-fs-float
+KHR-.*.shader_image_size.advanced-nonMS-fs-int
+KHR-.*.shader_image_size.advanced-nonMS-fs-uint
+
+# An old classic I thought I fixed at one point, but it still haunts us (particularly sensitive to specific frequencies iirc)
+spec@arb_depth_buffer_float@fbo-depthstencil-gl_depth32f_stencil8-blit
+spec@arb_depth_buffer_float@fbo-depthstencil-gl_depth32f_stencil8-copypixels
+
+# Flakes from aug-oct 2022.
+spec@ext_timer_query@time-elapsed
+spec@ext_texture_lod_bias@lodbias
+
+# recent flakes, first occurence 03-02-2023
+KHR-GL46.buffer_storage.map_persistent_dispatch
+# recent flakes, first occurence 09-02-2023
+KHR-GL46.buffer_storage.map_persistent_flush
+
+# very rare flake (once two weeks), first occurence 21-02-2023
+KHR-GL46.sample_variables.mask.rgba8ui.samples_0.mask_2
+KHR-GL46.sample_variables.mask.rgba8i.samples_4.mask_3
+KHR-GL46.sample_variables.mask.rgba32f.samples_0.mask_2
+KHR-GL46.sample_variables.mask.rgba32f.samples_4.mask_3
+
+# these flake basically everywhere
+glx@glx-make-current
+glx@glx-multi-window-single-context
+
+# flakes that turned up some time in early 2023
+spec@!opengl 1.1@line-smooth-stipple
+spec@!opengl [email protected] cull-back pv-last
+spec@!opengl [email protected] cull-front pv-last
+spec@!opengl [email protected] line cull-back pv-last
+spec@!opengl [email protected] line cull-front pv-last
+spec@!opengl [email protected] pv-last
+
+# discovered by nightly run
+spec@arb_timer_query@timestamp-get
+
+# uprev Piglit in Mesa
+KHR-GLES3.copy_tex_image_conversions.required.cubemap_posx_texture2d
+KHR-GLES31.core.shader_bitfield_operation.findMSB.ivec3_1
+KHR-GLES31.core.shader_multisample_interpolation.render.interpolate_at_offset.rgba8i.samples_1
+KHR-GLES31.core.shader_multisample_interpolation.render.interpolate_at_offset_check.rgba8i.samples_1
+KHR-GLES31.core.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_calls
+glx@glx-visuals-depth -pixmap
+glx@glx-visuals-stencil -pixmap
+glx@glx_arb_create_context_no_error@no error
+spec@arb_gpu_shader_fp64@execution@arb_gpu_shader_fp64-fs-getuniformdv
+spec@arb_gpu_shader_fp64@execution@arb_gpu_shader_fp64-gs-getuniformdv
+spec@arb_gpu_shader_fp64@execution@arb_gpu_shader_fp64-vs-getuniformdv
+spec@arb_program_interface_query@arb_program_interface_query-getprogramresourceindex@'vs_input2[1][0]' on GL_PROGRAM_INPUT
+spec@ext_external_objects@vk-ping-pong-multi-sem
+spec@ext_external_objects@vk-ping-pong-single-sem
+spec@ext_packed_float@query-rgba-signed-components
+
+
+# a618 and a660 seem to have some general instability in tesselation and GS.
+# Some tess tests also use the GS (tesselation.invariance), but others
+# don't (spirv_assembly).  They don't appear to be correlated to any GPU
+# faults or resets in the logs.
+dEQP-VK.binding_model.shader_access.*geometry.*
+dEQP-VK.binding_model.shader_access.*tess_ctrl.*
+dEQP-VK.binding_model.shader_access.*tess_eval.*
+dEQP-VK.clipping.user_defined.clip_cull_distance.*geom.*
+dEQP-VK.clipping.user_defined.clip_cull_distance.*tess.*
+dEQP-VK.clipping.user_defined.clip_distance.*geom.*
+dEQP-VK.clipping.user_defined.clip_distance.*tess.*
+dEQP-VK.draw.dynamic_rendering.*multi_draw.*geom.*
+dEQP-VK.draw.dynamic_rendering.*multi_draw.*tess.*
+dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_vk_primitive_topology_triangle_strip_attrib_divisor_2
+dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.shader_layer.tessellation_shader_4
+dEQP-VK.dynamic_rendering.primary_cmd_buff.random.seed46_geometry
+dEQP-VK.dynamic_rendering.primary_cmd_buff.random.seed88_geometry
+dEQP-VK..*.suballocation.multisample_resolve.layers_[36].*
+dEQP-VK.fragment_operations.scissor.multi_viewport.*
+dEQP-VK.glsl.builtin.function.integer.bitfieldinsert.uvec3_mediump_geometry
+dEQP-VK.glsl.builtin.function.integer.bitfieldreverse.uint_mediump_geometry
+dEQP-VK.glsl.builtin.function.integer.umulextended.uvec4_highp_tess_eval
+dEQP-VK.pipeline.*.interface_matching.vector_length.*tesc.*
+dEQP-VK.pipeline.pipeline_library.extended_dynamic_state.after_pipelines.rasterization_stream_none_to_one
+dEQP-VK.pipeline.pipeline_library.extended_dynamic_state.before_draw.2_scissors_switch
+dEQP-VK.spirv_assembly.instruction.graphics.*geom.*
+dEQP-VK.spirv_assembly.instruction.graphics.*tess.*
+dEQP-VK.spirv_assembly.type.*geom.*
+dEQP-VK.spirv_assembly.type.*tess.*
+dEQP-VK.synchronization.*_geometry.*
+dEQP-VK.synchronization.*_tess_ctrl.*
+dEQP-VK.synchronization.*_tess_control.*
+dEQP-VK.synchronization.*_tess_eval.*
+dEQP-VK.tessellation.invariance.*
+dEQP-VK.tessellation.tesscoord.*
+
+# Updated by ci-collate
+spec@arb_gpu_shader_fp64@execution@arb_gpu_shader_fp64-wrong-type-setter
+spec@ext_external_objects@vk-image-display-overwrite
+
+# SKQP test which seems to flake out
+SRGBReadWritePixels
+
+# glcts update
+KHR-GL46.packed_pixels.varied_rectangle.rgba32i
+gmem-dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32f_rgba_astc_6x6_khr.cubemap_to_texture3d
+gmem-dEQP-GLES31.functional.image_load_store.cube.format_reinterpret.rgba16ui_rgba16i
+gmem-dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32i_srgb8_alpha8_astc_6x5_khr.cubemap_to_cubemap
+KHR-GL46.texture_view.view_classes
+gmem-dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_12x10_khr_rgba32ui.texture3d_to_texture3d
+gmem-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.srgb8_alpha8_rgb10_a2.texture3d_to_texture3d0
+gmem-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.rgb10_a2_rgba8i.texture2d_to_texture2d_array
+gmem-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_8_bits.r8_snorm_r8ui.texture3d_to_texture2d_array
+gmem-dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_6x5_khr_rgba32ui.texture2d_array_to_texture3d
+gmem-dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_8x8_khr_rgba32ui.texture3d_to_texture2d
+gmem-dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_10x8_khr_rgba32i.cubemap_to_texture2d
+KHR-GL46.pixelstoragemodes.teximage3d.rgb5a1.1_1_1
+gmem-dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_4x4_khr_rgba32f.texture2d_array_to_texture2d
+KHR-GL46.pixelstoragemodes.teximage3d.rgba32i.16_1_1
+KHR-GL46.pixelstoragemodes.teximage3d.rgba32i.16_16_4
+gmem-dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.srgb8_alpha8_astc_6x6_khr_rgba32i.texture3d_to_texture3d
+gmem-dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_array_to_texture2d
+gmem-dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_5x4_rgba.srgb8_alpha8_astc_5x4_khr_srgb8_alpha8_astc_5x4_khr.texture2d_to_texture3d
+KHR-GL46.gpu_shader_fp64.builtin.outerproduct_dmat3
+KHR-GL46.shader_multisample_interpolation.render.interpolate_at_sample.rgba8ui.samples_1
+gmem-dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_12x12_rgba.rgba_astc_12x12_khr_rgba_astc_12x12_khr.texture2d_array_to_texture2d_array
+KHR-GL46.texture_cube_map_array.generate_mip_map_filterable_internalformat_immutable
+KHR-GL46.texture_repeat_mode.rgb565_11x131_2_mirrored_repeat
+gmem-dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_4x4_rgba.srgb8_alpha8_astc_4x4_khr_rgba_astc_4x4_khr.texture2d_array_to_texture2d_array
+gmem-dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba_astc_4x4_khr_rgba32f.cubemap_to_cubemap
+KHR-GL46.texture_repeat_mode.depth_component16_11x131_2_repeat
+KHR-GL46.blend_equation_advanced.blend_specific.GL_LIGHTEN_KHR
+KHR-GL46.texture_repeat_mode.r32ui_11x131_2_repeat
+gmem-dEQP-GLES31.functional.copy_image.compressed.viewclass_astc_12x12_rgba.srgb8_alpha8_astc_12x12_khr_rgba_astc_12x12_khr.texture3d_to_texture2d_array
+KHR-GL46.shaders45.shader_integer_mix.mix-bvec4
+KHR-GL46.texture_border_clamp.Texture2DArrayCompressedLinear
+KHR-GL46.shader_bitfield_operation.bitfieldExtract.ivec3_3
+KHR-GL46.texture_repeat_mode.rgb565_49x23_1_clamp_to_edge
+KHR-GL46.gpu_shader_fp64.builtin.smoothstep_against_scalar_dvec4
+KHR-GL46.tessellation_shader.tessellation_shader_point_mode.points_verification
+
+KHR-GL46.blend_equation_advanced.test_coherency.multiplySequence
+KHR-GL46.compute_shader.copy-image
+KHR-GL46.gpu_shader_fp64.builtin.distance_dvec4
+KHR-GL46.gpu_shader_fp64.builtin.inverse_dmat4
+KHR-GL46.gpu_shader_fp64.builtin.mod_double
+KHR-GL46.gpu_shader_fp64.fp64.varyings
+KHR-GL46.pixelstoragemodes.compressedteximage3d.rgba_astc_8x5.16_15_8
+KHR-GL46.pixelstoragemodes.compressedteximage3d.rgba_astc_8x5.32_30_1
+KHR-GL46.pixelstoragemodes.compressedteximage3d.rgba_astc_8x5.32_5_4
+KHR-GL46.pixelstoragemodes.compressedteximage3d.rgba_astc_8x5.8_15_4
+KHR-GL46.pixelstoragemodes.teximage3d.rgba32i.16_16_0
+KHR-GL46.pixelstoragemodes.teximage3d.rgba32ui.16_16_4
+KHR-GL46.sample_variables.mask.rgba8i.samples_0.mask_0
+KHR-GL46.shaders.uniform_block.instance_array_basic_type.std140.bool
+KHR-GL46.texture_swizzle.functional_format_idx_11_target_idx_1
+KHR-GL46.texture_swizzle.functional_format_idx_4_target_idx_4
+KHR-GL46.texture_swizzle.functional_format_idx_7_target_idx_4
+KHR-GL46.texture_swizzle.smoke_access_idx_11_channel_idx_1
+KHR-GL46.texture_swizzle.smoke_access_idx_2_channel_idx_3
+KHR-GL46.texture_swizzle.smoke_access_idx_7_channel_idx_1
+
+# With linux kernel 6.13-rc4 uprev
+gmem-dEQP-GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.rgba32ui_rgba_astc_5x4_khr.texture2d_array_to_texture3d
+KHR-GL46.shader_storage_buffer_object.advanced-switchBuffers
+
+# Initial ANGLE flakes
+angle-dEQP-GLES2.functional.texture.specification.teximage2d_align.cube_rgba4444_51_4
+angle-dEQP-GLES3.functional.fbo.blit.conversion.r16f_to_r8
+angle-dEQP-GLES3.functional.fbo.blit.conversion.r16f_to_rg16f
+angle-dEQP-GLES3.functional.fbo.blit.conversion.r16f_to_rg32f
+angle-dEQP-GLES3.functional.fbo.blit.conversion.r16f_to_rgba16f
+angle-dEQP-GLES3.functional.fbo.blit.conversion.r16f_to_rgba32f
+angle-dEQP-GLES3.functional.fbo.blit.conversion.r16i_to_r8i
+angle-dEQP-GLES3.functional.fbo.blit.conversion.r16i_to_rg16i
+angle-dEQP-GLES3.functional.fbo.blit.conversion.r16ui_to_r8ui
+angle-dEQP-GLES3.functional.fbo.blit.conversion.r16ui_to_r16ui
+angle-dEQP-GLES3.functional.fbo.blit.conversion.r16ui_to_r32ui
+angle-dEQP-GLES3.functional.fbo.blit.conversion.rgb565_to_rg8
+angle-dEQP-GLES3.functional.fbo.blit.conversion.rgb565_to_srgb8_alpha8
+angle-dEQP-GLES3.functional.texture.format.sized.cube.r16ui_npot
+angle-dEQP-GLES3.functional.texture.specification.basic_teximage3d.rgb565_2d_array
+angle-dEQP-GLES3.functional.texture.specification.basic_teximage3d.rgba4_2d_array
+angle-dEQP-GLES3.functional.texture.specification.texstorage2d.format.r16f_2d
+angle-dEQP-GLES3.functional.texture.specification.texstorage2d.format.rgba4_cube
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.r16f_r16ui.cubemap_to_texture3d
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.r16f_rg8.cubemap_to_cubemap
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.r16i_rg8.cubemap_to_texture3d
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.r16f_rg8_snorm.cubemap_to_cubemap
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.r16f_rg8_snorm.cubemap_to_texture2d_array
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.r16i_rg8i.cubemap_to_renderbuffer
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.r16f_rg8ui.cubemap_to_cubemap
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.r16i_r16f.texture3d_to_cubemap
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.r16ui_rg8_snorm.cubemap_to_cubemap
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.r16ui_rg8ui.cubemap_to_texture2d_array
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.rg8_r16f.texture2d_to_cubemap
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.rg8_snorm_r16f.texture2d_to_cubemap
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.rg8_snorm_r16ui.texture2d_to_cubemap
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.rg8i_r16ui.texture2d_to_cubemap
+angle-dEQP-GLES31.functional.copy_image.non_compressed.viewclass_16_bits.rg8ui_r16i.texture2d_to_cubemap
+angle-dEQP-GLES31.functional.state_query.program.tesselation_shader_state_get_programiv
+
+# Autotune regression
+angle-dEQP-GLES3.functional.fbo.msaa.4_samples.rgb5_a1
+
+# Android flakes
+android-dEQP-VK.binding_model.shader_access.primary_cmd_buf.bind.with_template.sampler_mutable.no_access.single_descriptor.2d_array_base_mip
+android-dEQP-VK.pipeline.fast_linked_library.stencil.nocolor.format.d24_unorm_s8_uint.states.fail_wrap.pass_decc.dfail_decc.comp_never.any
+android-dEQP-VK.pipeline.fast_linked_library.stencil.nocolor.format.s8_uint.states.fail_repl.pass_decw.dfail_inv.comp_never.any
+android-dEQP-VK.pipeline.pipeline_library.stencil.nocolor.format.d32_sfloat_s8_uint_separate_layouts.states.fail_incc.pass_decw.dfail_keep.comp_never.any
+android-dEQP-VK.renderpasses.renderpass1.dedicated_allocation.formats.r16g16_uint.input.clear.dont_care.self_dep_draw_use_input_aspect_ms
+
+# See this entry in the VKCTS 1.4.4.2 -> 1.4.5.3 uprev fails list.
+dEQP-VK.*.custom_resolve.*.fdm_subsampled

src/freedreno/ci/freedreno-a618-skips.txt

@@ -0,0 +1,21 @@
+# Note: skips lists for CI are just a list of lines that, when
+# non-zero-length and not starting with '#', will regex match to
+# delete lines from the test list.  Be careful.
+
+# Still running after 3 hours, time is spent in batch_draw_tracking().
+KHR-GLES31.core.shader_image_load_store.basic-allFormats-store-fs
+
+# 60s timeout
+KHR-GLES31.core.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_MaxPatchVertices_Position_PointSize
+KHR-GL46.copy_image.functional
+
+# Exclude WSI related tests for a618-vk-asan
+# The ones that weren't being skipped were causing leaks
+asan-dEQP-VK.image.swapchain_mutable.*
+asan-dEQP-VK.wsi.*
+
+# Skip single-threaded gmem testing that doesn't give useful extra coverage.
+gmem-dEQP-VK.wsi.direct_drm.*
+
+# Mainly for testing platform features. Skip as take too long. Passes reliably though.
+awsi-dEQP-VK.wsi.android.incremental_present.*

src/freedreno/ci/freedreno-a618-slow-skips.txt

@@ -0,0 +1,77 @@
+# Note: skips lists for CI are just a list of lines that, when
+# non-zero-length and not starting with '#', will regex match to
+# delete lines from the test list.  Be careful.
+
+# Timeouts, passes otherwise
+KHR-GL46.texture_swizzle.smoke
+KHR-GL46.gpu_shader_fp64.builtin.inverse_dmat4
+KHR-GL46.gpu_shader_fp64.fp64.varyings
+
+# Slow tests that may hit 60s timeout pre-merge, but pass otherwise
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.struct_mixed_types.uniform_buffer_block_vert
+dEQP-VK.api.buffer_memory_requirements.create_sparse_binding_sparse_residency.ext_mem_flags_excluded.method1.size_req_storage_usage_bits
+dEQP-VK.api.buffer_memory_requirements.create_sparse_binding_sparse_residency.ext_mem_flags_excluded.method2.size_req_storage_usage_bits
+dEQP-VK.api.buffer_memory_requirements.create_sparse_binding_sparse_residency_sparse_aliased.ext_mem_flags_excluded.method1.size_req_storage_usage_bits
+dEQP-VK.api.buffer_memory_requirements.create_sparse_binding_sparse_residency_sparse_aliased.ext_mem_flags_excluded.method2.size_req_storage_usage_bits
+
+# Slow tests that may hit 60s timeout pre-merge, but pass otherwise
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-div-dmat3-dmat3
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-div-dmat4x2-dmat4x2
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-div-double-dmat3
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-mult-dmat4x3-dmat3x4
+spec@arb_gpu_shader_fp64@execution@fs-isnan-dvec
+spec@arb_gpu_shader_fp64@execution@gs-isnan-dvec
+spec@arb_gpu_shader_fp64@execution@vs-isnan-dvec
+spec@arb_gpu_shader_fp64@execution@vs-increment-dvec
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-inverse-dmat3
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-add-dmat4-double
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-mult-dmat3-dmat3
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-div-dmat4-dmat4
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-div-dmat3x4-dmat3x4
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-mult-dmat3x4-dmat4x3
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-div-double-dmat4
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-mod-dvec4-dvec4
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-div-dmat2x4-dmat2x4
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-div-double-dmat2x4
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-mult-dmat3-dmat4x3
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-mult-dmat3x4-dmat3
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-sub-dmat4-double
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-smoothstep-dvec4-dvec4-dvec4
+[email protected]@execution@built-in-functions@fs-floatbitstoint-neg_abs
+[email protected]@execution@built-in-functions@fs-inverse-dmat4
+[email protected]@execution@built-in-functions@fs-op-div-double-dmat3x4
+[email protected]@execution@built-in-functions@fs-op-div-dmat3x4-dmat3x4
+[email protected]@execution@built-in-functions@fs-op-mult-dmat3x4-dmat4x3
+[email protected]@execution@built-in-functions@fs-op-add-dmat4-dmat4
+[email protected]@execution@built-in-functions@fs-op-add-double-dmat4
+[email protected]@execution@built-in-functions@fs-op-div-dmat3x2-dmat3x2
+[email protected]@execution@built-in-functions@fs-op-div-dmat4x2-dmat4x2
+[email protected]@execution@built-in-functions@fs-op-mult-dmat3x4-dmat3
+[email protected]@execution@built-in-functions@fs-op-mult-dmat4-dmat3x4
+[email protected]@execution@built-in-functions@fs-smoothstep-dvec4-dvec4-dvec4
+[email protected]@execution@built-in-functions@fs-op-div-dmat4-double
+[email protected]@execution@built-in-functions@fs-op-mult-dmat4x2-dmat4
+[email protected]@execution@built-in-functions@fs-op-mult-dmat4x3-dmat4
+[email protected]@execution@built-in-functions@fs-inversesqrt-dvec4
+[email protected]@execution@built-in-functions@fs-refract-dvec4-dvec4-double
+[email protected]@execution@conversion@frag-conversion-implicit-mat3x4-dmat3x4-zero-sign
+[email protected]@execution@conversion@frag-conversion-implicit-mat3x4-dmat3x4-zero-sign
+[email protected]@execution@conversion@frag-conversion-implicit-mat4-dmat4-zero-sign
+
+# Slow tests that may hit 60s timeout pre-merge, but pass otherwise.  94% CPU
+# used in ir3 create_variant, but no single pass there dominating its time.
+# Just use the scalar/vec2 cases, which are fast enough for CI.
+dEQP-VK.subgroups.clustered.compute.subgroupclustered(min|max|mul|and|or|xor|add)_[iu]64vec[34].*
+dEQP-VK.subgroups.clustered.compute.subgroupclustered(min|max|mul|and|or|xor|add)_[iu]vec[34].*
+dEQP-VK.subgroups.clustered.compute.subgroupclustered(min|max|mul|and|or|xor|add)_bvec[34].*
+
+# Speed up pre-merge testing by removing redundant coverage in force-gmem mode
+gmem-dEQP-VK.api.*
+gmem-dEQP-VK.renderpass\..*
+gmem-dEQP-VK.synchronization\..*
+gmem-dEQP-VK.wsi.*
+
+# Slow single-threaded tests (~45s each).
+# Running both adds ~90s, which is too much for pre-merge.
+dEQP-VK.memory.mapping.suballocation.full.variable.implicit_unmap
+dEQP-VK.memory.mapping.suballocation.full.variable.implicit_unmap_map2

src/freedreno/ci/freedreno-a660-fails.txt

@@ -0,0 +1,136 @@
+KHR-GL46.shader_subroutine.control_flow_and_returned_subroutine_values_used_as_subroutine_input,Fail
+
+#glcts update
+KHR-GLES3.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit,Fail
+KHR-GL46.texture_lod_bias.texture_lod_bias_all,Fail
+
+# New failures with ES CTS 3.2.12.0
+KHR-GLES3.framebuffer_blit.multisampled_to_singlesampled_blit_depth_config_test,Fail
+KHR-GLES31.core.texture_stencil8.multisample,Fail
+KHR-GL46.texture_stencil8.multisample,Fail
+
+# GL tests above, Vulkan tests below
+
+# New fails in 1.4.3.3
+dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_508,Fail
+dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_508,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_508,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_multiview_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_multiview_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_multiview_counter_offset_508,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_counter_offset_508,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_16,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_244,Fail
+dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_508,Fail
+gmem-dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_16,Fail
+gmem-dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_244,Fail
+nobin-dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_16,Fail
+nobin-dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_244,Fail
+
+# New failures with VKCTS 1.4.4.0
+dEQP-VK.tessellation.misc_draw.tess_factor_barrier_bug,Crash
+gmem-dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_16,Fail
+gmem-dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_508,Fail
+gmem-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_244,Fail
+gmem-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_508,Fail
+gmem-dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_508,Fail
+nobin-dEQP-VK.transform_feedback.simple.draw_indirect_counter_offset_16,Fail
+nobin-dEQP-VK.transform_feedback.simple.draw_indirect_multiview_counter_offset_508,Fail
+nobin-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_244,Fail
+nobin-dEQP-VK.transform_feedback.simple_fast_gpl.draw_indirect_counter_offset_508,Fail
+nobin-dEQP-VK.transform_feedback.simple_optimized_gpl.draw_indirect_multiview_counter_offset_508,Fail
+
+
+# Bad assumptions in piglit about layout of multiplanar formats,
+# it should use separate buffers per plane:
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_yvu420,Fail
+
+# OpenCL tests below
+#
+## rusticl-core issues:
+#
+#Unexpected CL error: CL_BUILD_PROGRAM_FAILURE -11
+#Expected CL error: CL_INVALID_BUILD_OPTIONS -43
+api@clbuildprogram,Fail
+
+#Unexpected CL error: CL_COMPILE_PROGRAM_FAILURE -15
+#Expected CL error: CL_INVALID_COMPILER_OPTIONS -66
+api@clcompileprogram,Fail
+
+#Unexpected CL error: CL_SUCCESS 0
+#Expected CL error: CL_KERNEL_ARG_INFO_NOT_AVAILABLE -19
+api@clgetkernelarginfo,Fail
+
+# Piglit checks the pre 3.1 behavior
+api@clsetkernelarg,Fail
+api@clsetkernelarg@Input checks,Fail
+
+#Unexpected CL error: CL_SUCCESS 0
+#Expected CL error: CL_INVALID_LINKER_OPTIONS -67
+#Failed (error code: CL_SUCCESS): Trigger CL_INVALID_LINKER_OPTIONS if the linker options specified by options are invalid.
+#Unexpected CL error: CL_LINK_PROGRAM_FAILURE -17
+#Expected CL error: CL_INVALID_OPERATION -59
+#Failed (error code: CL_LINK_PROGRAM_FAILURE): Trigger CL_INVALID_OPERATION if the rules for devices containing compiled binaries or libraries as described in input_programs argument above are not followed.
+#Unexpected CL error: CL_SUCCESS 0
+#Expected CL error: CL_LINK_PROGRAM_FAILURE -17
+api@cllinkprogram,Fail
+
+# can be resolved by RUSTICL_FEATURES=fp16,fp64
+program@build@vector-data-types,Fail
+
+# https://gitlab.freedesktop.org/mesa/mesa/-/issues/8408
+program@execute@global-offset,Fail
+program@execute@global-offset@3d- input dependent,Fail
+
+#
+## freedreno issues:
+#
+#Error at data[0]
+custom@r600 create release buffer bug,Fail
+
+#
+## works on OnePlus 6:
+#
+#Failed: return NULL if platform is not a valid platform
+api@clgetextensionfunctionaddressforplatform,Fail
+
+#
+## Not our problem:
+#
+# CL_DEVICE_MAX_READ_IMAGE_ARGS: failed, expected at least 128, got 16 
+api@clgetdeviceinfo,Fail
+
+# CL_QUEUE_SIZE Unexpected CL error: CL_INVALID_COMMAND_QUEUE -36
+api@clgetcommandqueueinfo,Fail
+
+# Piglit doesn't check subbuffer alignment requirements
+api@clgetmemobjectinfo,Fail
+
+# broken piglit test (doesn't account for FTZ)
+program@execute@[email protected],Fail
+program@execute@[email protected]@nextafter float1,Fail
+program@execute@[email protected]@nextafter float16,Fail
+program@execute@[email protected]@nextafter float2,Fail
+program@execute@[email protected]@nextafter float4,Fail
+program@execute@[email protected]@nextafter float8,Fail
+
+# (file=input,line=0,column=0,index=0): Unresolved external reference to "_Z21convert_char4_sat_rteDv4_i".
+program@execute@vector-conversion,Fail
+
+# Initial ANGLE failures
+angle-dEQP-GLES2.functional.shaders.algorithm.rgb_to_hsl_vertex,Fail
+
+# VKCTS 1.4.4.2 -> 1.4.5.3 uprev
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_10,Fail
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_16,Fail
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_17,Fail
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_20,Fail
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_24,Fail

src/freedreno/ci/freedreno-a660-flakes.txt

@@ -0,0 +1,58 @@
+KHR-GL46.buffer_storage.map_persistent_dispatch
+KHR-GL46.buffer_storage.map_persistent_flush
+KHR-GL46.shader_subroutine.control_flow_and_returned_subroutine_values_used_as_subroutine_input
+
+# a618 and a660 seem to have some general instability in tesselation and GS.
+# Some tess tests also use the GS (tesselation.invariance), but others
+# don't (spirv_assembly).  They don't appear to be correlated to any GPU
+# faults or resets in the logs.
+dEQP-VK.binding_model.shader_access.*geometry.*
+dEQP-VK.binding_model.shader_access.*tess_ctrl.*
+dEQP-VK.binding_model.shader_access.*tess_eval.*
+dEQP-VK.clipping.user_defined.clip_cull_distance.*geom.*
+dEQP-VK.clipping.user_defined.clip_cull_distance.*tess.*
+dEQP-VK.clipping.user_defined.clip_distance.*geom.*
+dEQP-VK.clipping.user_defined.clip_distance.*tess.*
+dEQP-VK.draw.dynamic_rendering.*multi_draw.*geom.*
+dEQP-VK.draw.dynamic_rendering.*multi_draw.*tess.*
+dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_vk_primitive_topology_triangle_strip_attrib_divisor_2
+dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.shader_layer.tessellation_shader_4
+dEQP-VK.dynamic_rendering.primary_cmd_buff.random.seed46_geometry
+dEQP-VK.dynamic_rendering.primary_cmd_buff.random.seed88_geometry
+dEQP-VK..*.suballocation.multisample_resolve.layers_[36].*
+dEQP-VK.fragment_operations.scissor.multi_viewport.*
+dEQP-VK.glsl.builtin.function.integer.bitfieldinsert.uvec3_mediump_geometry
+dEQP-VK.glsl.builtin.function.integer.bitfieldreverse.uint_mediump_geometry
+dEQP-VK.glsl.builtin.function.integer.umulextended.uvec4_highp_tess_eval
+dEQP-VK.pipeline.*.interface_matching.vector_length.*tesc.*
+dEQP-VK.pipeline.pipeline_library.extended_dynamic_state.after_pipelines.rasterization_stream_none_to_one
+dEQP-VK.pipeline.pipeline_library.extended_dynamic_state.before_draw.2_scissors_switch
+dEQP-VK.spirv_assembly.instruction.graphics.*geom.*
+dEQP-VK.spirv_assembly.instruction.graphics.*tess.*
+dEQP-VK.spirv_assembly.type.*geom.*
+dEQP-VK.spirv_assembly.type.*tess.*
+dEQP-VK.synchronization.*_geometry.*
+dEQP-VK.synchronization.*_tess_ctrl.*
+dEQP-VK.synchronization.*_tess_control.*
+dEQP-VK.synchronization.*_tess_eval.*
+dEQP-VK.tessellation.invariance.*
+
+# Updated by ci-collate
+dEQP-VK.reconvergence.workgroup_uniform_control_flow_ballot.compute.nesting4.7.38
+dEQP-VK.query_pool.statistics_query.host_query_reset.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth
+
+KHR-GL46.shader_image_load_store.basic-allTargets-loadStoreVS
+dEQP-GLES31.functional.image_load_store.3d.load_store.rgba8_snorm_single_layer
+dEQP-GLES31.functional.image_load_store.3d.load_store.r32f_single_layer
+
+# glcts update
+KHR-GL46.texture_view.view_classes
+
+# Appeared after decreasing the fraction
+
+# Random flakes, unkown when they started appearing
+dEQP-VK.subgroups.shuffle.graphics.subgroupshufflexor_int64_t_constant
+dEQP-VK.subgroups.shuffle.framebuffer.subgroupshuffle_bool_tess_control
+
+# New flake with GL CTS 4.6.6.0
+KHR-GL46.gpu_shader_fp64.builtin.smoothstep_dvec4

src/freedreno/ci/freedreno-a660-skips.txt

@@ -0,0 +1,11 @@
+# 60s timeout
+KHR-GL46.copy_image.functional
+KHR-GL46.gpu_shader_fp64.fp64.varyings
+KHR-GL46.texture_swizzle.smoke
+
+# 60s timeout (flake)
+KHR-GL46.gpu_shader_fp64.builtin.inverse_dmat4
+
+# VKCTS 1.4.4.2 -> 1.4.5.3 uprev seems to have bumped this back over
+# the timeout for a few drivers.
+gmem-dEQP-VK.memory.mapping.suballocation.full.variable.implicit_unmap

src/freedreno/ci/freedreno-a660-slow-skips.txt

@@ -0,0 +1,20 @@
+# Note: skips lists for CI are just a list of lines that, when
+# non-zero-length and not starting with '#', will regex match to
+# delete lines from the test list.  Be careful.
+
+# Slow tests that may hit 60s timeout pre-merge, but pass otherwise
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.struct_mixed_types.uniform_buffer_block_vert
+dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_vert
+dEQP-VK.subgroups.arithmetic.compute.subgroupmul_i64vec4_requiredsubgroupsize
+dEQP-VK.subgroups.clustered.compute.subgroupclusteredmin_uint64_t_requiredsubgroupsize
+
+# Slow tests that may hit 60s timeout pre-merge, but pass otherwise.  94% CPU
+# used in ir3 create_variant, but no single pass there dominating its time.
+# Just use the scalar cases, which are fast enough for CI.
+dEQP-VK.subgroups.clustered.compute.subgroupclustered(min|max|mul|and|or|xor|add)_[iu]64vec[234].*
+
+# Speed up pre-merge testing by removing redundant coverage in force-gmem mode
+gmem-dEQP-VK.api.*
+gmem-dEQP-VK.renderpass\..*
+gmem-dEQP-VK.synchronization\..*
+gmem-dEQP-VK.wsi.*

src/freedreno/ci/freedreno-a6xx-skips.txt

@@ -0,0 +1,103 @@
+# Note: skips lists for CI are just a list of lines that, when
+# non-zero-length and not starting with '#', will regex match to
+# delete lines from the test list.  Be careful.
+#
+# This file lists tests to skip for _all_ a6xx devices
+
+# 60s timeout
+KHR-GLES31.core.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_MaxPatchVertices_Position_PointSize
+KHR-GL46.copy_image.functional
+
+# Slow tests
+spec@arb_compute_shader@local-id-explosion
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-inverse-dmat4
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-div-dmat4x3-dmat4x3
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-div-double-dmat3x4
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-div-double-dmat4x3
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-mult-dmat2x4-dmat4x2
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-mult-dmat4-dmat3x4
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-mult-dmat4x3-dmat4
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-smoothstep-double-double-dvec4
+spec@arb_gpu_shader_fp64@execution@vs-decrement-dvec
+spec@egl 1.4@eglquerysurface egl_bad_attribute
+spec@egl_chromium_sync_control@conformance
+spec@egl_khr_gl_colorspace@linear
+[email protected]@execution@built-in-functions@fs-op-div-dmat2x3-dmat2x3
+[email protected]@execution@built-in-functions@fs-op-div-dmat2x4-dmat2x4
+[email protected]@execution@built-in-functions@fs-op-div-dmat4x3-dmat4x3
+[email protected]@execution@built-in-functions@fs-op-div-dmat4-dmat4
+[email protected]@execution@built-in-functions@fs-op-div-double-dmat2x4
+[email protected]@execution@built-in-functions@fs-op-div-double-dmat4
+[email protected]@execution@built-in-functions@fs-op-mult-dmat2x4-dmat3x2
+[email protected]@execution@built-in-functions@fs-op-mult-dmat4-dmat4
+[email protected]@execution@conversion@frag-conversion-implicit-mat4-dmat4-zero-sign
+[email protected]@execution@conversion@frag-conversion-implicit-mat4x3-dmat4x3-zero-sign
+
+# Timeout
+spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-op-mult-dmat4-dmat4
+
+# These take most of a minute to run
+spec@!opengl 3.0@clearbuffer-depth-cs-probe
+spec@ext_texture_array@fbo-depth-array depth-clear
+spec@ext_texture_array@fbo-depth-array depth-draw
+spec@ext_texture_array@fbo-depth-array fs-writes-depth
+spec@ext_texture_array@fbo-depth-array fs-writes-stencil
+spec@ext_texture_array@fbo-depth-array stencil-clear
+spec@ext_texture_array@fbo-depth-array stencil-draw
+spec@ext_transform_feedback@max-varyings
+spec@!opengl [email protected]
+
+# TC Timeouts
+spec@arb_sync@clientwaitsync-timeout
+spec@arb_texture_buffer_object@bufferstorage
+spec@arb_uniform_buffer_object@bufferstorage
+spec@arb_buffer_storage@bufferstorage-persistent read
+spec@arb_buffer_storage@bufferstorage-persistent read client-storage
+spec@arb_buffer_storage@bufferstorage-persistent read coherent
+spec@arb_buffer_storage@bufferstorage-persistent read coherent client-storage
+spec@arb_buffer_storage@bufferstorage-persistent_gles3 read
+spec@arb_buffer_storage@bufferstorage-persistent_gles3 read client-storage
+spec@arb_buffer_storage@bufferstorage-persistent_gles3 read coherent
+spec@arb_buffer_storage@bufferstorage-persistent_gles3 read coherent client-storage
+
+# Only run the FS versions of build-in-functions, the VS and GS variants
+# don't add additional useful coverage.  And in some cases (GS+fp64) the
+# compile times are somewhat long.
+.*built-in-functions@[vg]s.*
+.*conversion@vert.*
+.*@conversion@geom.*
+
+# Don't bother trying, it just causes more OoM havoc than it is
+# worth:
+spec@!opengl 1.1@max-texture-size
+
+# These are redundant with arb_copy_image, so skip them to cut down
+# on CI runtime:
+spec@nv_copy_image@nv_copy_image.*
+
+# Legacy gl features unsupported by hw.  We _could_ emulate it with a GS
+# at the cost of extra per-draw overhead for all users.
+#
+# If we find any non-piglit users of these features, then maybe a driconf
+# way to force fall-over to zink for that app could make sense.  Until
+# then, just pretend that this stuff doesn't exist:
+.*edgeflag.*
+.*stipple.*
+# uses edgeflags:
+shaders@point-vertex-id.*
+# uses stipple:
+spec@!opengl [email protected]
+
+# Some reconvergence tests are very slow:
+(gmem-|stale-regs-)?dEQP-VK.reconvergence.(sub|work)group_uniform_control_flow_(ballot|elect).compute.nesting4.(0.40|7.10)
+
+# Piglit assumes fp16 denorms are supported, which the driver doesn't.
+program@execute@amdgcn-f16-inline-immediates
+program@execute@amdgcn-f16-inline-immediates@add integer 64
+
+# Vulkan Video isn't supported, since video isn't part of the gpu
+dEQP-VK.video.*
+
+# Generates too many immediates due to loop unrolling
+KHR-GLES31.core.geometry_shader.limits.max_output_components
+KHR-GL46.geometry_shader.limits.max_output_components

src/freedreno/ci/freedreno-a750-fails.txt

@@ -0,0 +1,101 @@
+KHR-GL46.shader_image_size.basic-nonMS-tes-int,Fail
+KHR-GL46.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_tessLevel,Fail
+KHR-GL46.tessellation_shader.tessellation_shader_tessellation.TES,Fail
+KHR-GL46.texture_lod_bias.texture_lod_bias_all,Fail
+KHR-GL46.texture_stencil8.multisample,Fail
+KHR-GL46.vertex_attrib_binding.advanced-iterations,Fail
+
+KHR-GLES3.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit,Fail
+KHR-GLES3.framebuffer_blit.multisampled_to_singlesampled_blit_depth_config_test,Fail
+KHR-GLES31.core.texture_stencil8.multisample,Fail
+KHR-GLES31.core.vertex_attrib_binding.advanced-iterations,Fail
+
+# New failures with GL CTS 4.6.7.0 & ES CTS 3.2.13.0
+dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.rgba8_rgba8ui.renderbuffer_to_renderbuffer,Fail
+dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.srgb8_alpha8_rgba8ui.renderbuffer_to_renderbuffer,Fail
+
+# New failures when updating kernel from msm-next at 6.16 to 6.19.5
+# https://gitlab.freedesktop.org/drm/msm/-/issues/93
+dEQP-VK.pipeline.monolithic.timestamp.calibrated.calibration_test,Fail
+dEQP-VK.pipeline.monolithic.timestamp.calibrated.dev_domain_test,Fail
+
+
+# Bad assumptions in piglit about layout of multiplanar formats,
+# it should use separate buffers per plane:
+spec@ext_image_dma_buf_import@ext_image_dma_buf_import-sample_yvu420,Fail
+
+
+# OpenCL tests below
+#
+## rusticl-core issues:
+#
+#Unexpected CL error: CL_BUILD_PROGRAM_FAILURE -11
+#Expected CL error: CL_INVALID_BUILD_OPTIONS -43
+api@clbuildprogram,Fail
+
+#Unexpected CL error: CL_COMPILE_PROGRAM_FAILURE -15
+#Expected CL error: CL_INVALID_COMPILER_OPTIONS -66
+api@clcompileprogram,Fail
+
+#Unexpected CL error: CL_SUCCESS 0
+#Expected CL error: CL_KERNEL_ARG_INFO_NOT_AVAILABLE -19
+api@clgetkernelarginfo,Fail
+
+#Unexpected CL error: CL_SUCCESS 0
+#Expected CL error: CL_INVALID_LINKER_OPTIONS -67
+#Failed (error code: CL_SUCCESS): Trigger CL_INVALID_LINKER_OPTIONS if the linker options specified by options are invalid.
+#Unexpected CL error: CL_LINK_PROGRAM_FAILURE -17
+#Expected CL error: CL_INVALID_OPERATION -59
+#Failed (error code: CL_LINK_PROGRAM_FAILURE): Trigger CL_INVALID_OPERATION if the rules for devices containing compiled binaries or libraries as described in input_programs argument above are not followed.
+#Unexpected CL error: CL_SUCCESS 0
+#Expected CL error: CL_LINK_PROGRAM_FAILURE -17
+api@cllinkprogram,Fail
+
+# can be resolved by RUSTICL_FEATURES=fp16,fp64
+program@build@vector-data-types,Fail
+
+# https://gitlab.freedesktop.org/mesa/mesa/-/issues/8408
+program@execute@global-offset,Fail
+program@execute@global-offset@3d- input dependent,Fail
+
+# Regressed between https://gitlab.freedesktop.org/mesa/mesa/-/jobs/70146138 and https://gitlab.freedesktop.org/mesa/mesa/-/jobs/70217173
+program@execute@vector-conversion,Fail
+
+#
+## freedreno issues:
+#
+#Error at data[0]
+custom@r600 create release buffer bug,Fail
+
+#
+## works on OnePlus 6:
+#
+#Failed: return NULL if platform is not a valid platform
+api@clgetextensionfunctionaddressforplatform,Fail
+
+#
+## Not our problem:
+#
+# CL_DEVICE_MAX_READ_IMAGE_ARGS: failed, expected at least 128, got 16 
+api@clgetdeviceinfo,Fail
+
+# CL_QUEUE_SIZE Unexpected CL error: CL_INVALID_COMMAND_QUEUE -36
+api@clgetcommandqueueinfo,Fail
+
+# broken piglit test (doesn't account for FTZ)
+program@execute@[email protected],Fail
+program@execute@[email protected]@nextafter float1,Fail
+program@execute@[email protected]@nextafter float16,Fail
+program@execute@[email protected]@nextafter float2,Fail
+program@execute@[email protected]@nextafter float4,Fail
+program@execute@[email protected]@nextafter float8,Fail
+
+# Initial ANGLE failures
+angle-dEQP-GLES2.functional.shaders.algorithm.rgb_to_hsl_vertex,Fail
+
+KHR-GL46.shader_atomic_counters.basic-usage-tes,Fail
+
+# test_sampler_feedback_implicit_lod_aniso:3429:Test 19: Test failed: Mip 1, expected 0, got 1.
+# Enabled by EXT_shader_image_atomic_int64:
+# https://github.com/HansKristian-Work/vkd3d-proton/blob/master/docs/sampler_feedback.md
+vkd3d-test_sampler_feedback_implicit_lod_aniso,Fail

src/freedreno/ci/freedreno-a750-flakes.txt

@@ -0,0 +1,102 @@
+dEQP-VK.api.buffer_memory_requirements.create_sparse_binding_sparse_residency.ext_mem_flags_excluded.method1.size_req_storage_usage_bits
+dEQP-VK.api.image_clearing.core.clear_color_image.2d.optimal.single_layer.r16g16_unorm_1x33_multiple_subresourcerange
+dEQP-VK.binding_model.shader_access.primary_cmd_buf.bind.with_push.storage_image.vertex.multiple_contiguous_descriptors.2d_array
+dEQP-VK.binding_model.shader_access.primary_cmd_buf.bind.with_push_template.combined_image_sampler_mutable.vertex_fragment.multiple_arbitrary_descriptors.2d_base_slice
+dEQP-VK.binding_model.shader_access.secondary_cmd_buf.bind.sampler_mutable.vertex.multiple_descriptor_sets.multiple_discontiguous_descriptors.1d_base_slice
+dEQP-VK.fragment_shading_rate.renderpass2.fast_linked_library.sampleshadingenable.dynamic.attachment.shaderrate.keep.keep.1x1.samples1.gs
+dEQP-VK.glsl.builtin.precision_fp16_storage32b.distance.compute.vec4
+dEQP-VK.glsl.texture_gather.offset.min_required_offset.2d.rgba8i.size_pot.mirrored_repeat_clamp_to_edge
+dEQP-VK.image.host_image_copy.identical_memory_layout.linear.d32_sfloat
+dEQP-VK.image.host_image_copy.optimal.image_to_image_memcpy.depth_attachment_stencil_read_only_optimal.depth_attachment_stencil_read_only_optimal.32x32x1_1.0.r16_unorm
+dEQP-VK.memory.allocation.basic.size_8KiB.forward.count_4000
+dEQP-VK.pipeline.fast_linked_library.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_inv.dfail_decc.comp_always
+dEQP-VK.pipeline.monolithic.sampler.view_type.1d_array.format.r16g16b16a16_sfloat.mag_reduce.comp_one_r_r_r.max
+dEQP-VK.pipeline.monolithic.stencil.format.d32_sfloat_s8_uint.states.fail_decc.pass_decc.dfail_repl.comp_always.any
+dEQP-VK.pipeline.monolithic.stencil.format.s8_uint.states.fail_keep.pass_decw.dfail_zero.comp_always.any
+dEQP-VK.pipeline.pipeline_library.blend.dual_source.format.r8g8b8a8_snorm.output_variable.states.color_ca_1ms1a_sub_alpha_1msa_1mdc_sub-color_1mda_sas_add_alpha_o_ca_add-color_sa_1mdc_sub_alpha_o_1mca_rsub-color_s1c_1msa_rsub_alpha_1msa_1mca_add
+dEQP-VK.pipeline.pipeline_library.color_write_enable.no_channels.two_draws_static.disable_second
+dEQP-VK.pipeline.pipeline_library.stencil.format.d24_unorm_s8_uint.states.fail_decw.pass_incc.dfail_wrap.comp_not_equal
+dEQP-VK.pipeline.pipeline_library.stencil.nocolor.format.d24_unorm_s8_uint.states.fail_wrap.pass_decw.dfail_inv.comp_greater_or_equal
+dEQP-VK.query_pool.statistics_query.reset_after_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency
+dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_clear_color
+dEQP-VK.spirv_assembly.instruction.compute.opinboundsaccesschain.uint.array_2
+dEQP-VK.synchronization.cross_instance.suballocated.write_ssbo_tess_control_read_ubo_compute.buffer_16384_binary_semaphore_fd
+dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_compute
+dEQP-VK.synchronization.op.single_queue.fence.write_image_fragment_read_blit_image.image_128x128_r16g16b16a16_uint
+dEQP-VK.synchronization2.cross_instance.dedicated.write_image_tess_control_read_blit_image.image_128x128_r16_uint_binary_semaphore_fd
+dEQP-VK.synchronization2.op.single_queue.timeline_semaphore.write_image_fragment_read_image_compute.image_128_r32_uint
+dEQP-VK.texture.shadow.cube_array.nearest_mipmap_nearest.not_equal_d32_sfloat
+dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after
+dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries
+dEQP-VK.transform_feedback.primitives_generated_query.get.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries
+dynamic-dEQP-VK.renderpass2.suballocation.attachment_sparse_filling.input_attachment_1
+
+KHR-GL46.es_31_compatibility.shader_storage_buffer_object.advanced-usage-sync-cs
+KHR-GL46.shader_bitfield_operation.bitCount.uvec3_0
+KHR-GL46.shader_bitfield_operation.findMSB.ivec4_1
+KHR-GL46.shader_bitfield_operation.unpackUnorm4x8.3
+KHR-GL46.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters
+KHR-GL46.shader_draw_parameters_tests.MultiDrawElementIndirectCountParameters
+KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawElementsIndirectParameters
+KHR-GL46.shader_group_vote.all_invocations
+KHR-GL46.shader_group_vote.all_invocations_equal
+KHR-GL46.shader_group_vote.invocations_with_variables
+KHR-GL46.shader_image_load_store.basic-allTargets-loadStoreTES
+KHR-GL46.shader_image_load_store.multiple-uniforms
+KHR-GL46.shader_image_size.advanced-nonMS-tes-float
+KHR-GL46.shader_image_size.advanced-nonMS-tes-int
+KHR-GL46.shader_image_size.advanced-nonMS-tes-uint
+KHR-GL46.shader_image_size.basic-nonMS-tes-float
+KHR-GL46.shader_image_size.basic-nonMS-tes-uint
+KHR-GL46.shader_storage_buffer_object.advanced-usage-sync-cs
+KHR-GL46.shader_storage_buffer_object.advanced-write-tessellation
+KHR-GL46.tessellation_shader.single.max_patch_vertices
+KHR-GL46.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn
+KHR-GL46.texture_cube_map_array.color_depth_attachments
+KHR-GL46.transform_feedback.draw_xfb_feedbackk_test
+KHR-GLES31.core.shader_bitfield_operation.bitfieldInsert.ivec3_0
+KHR-GLES31.core.shader_storage_buffer_object.advanced-usage-sync-cs
+KHR-GLES31.core.texture_cube_map_array.color_depth_attachments
+custom@buffer flags
+custom@buffer flags@in-0x0-out-0x20
+custom@buffer flags@in-0x0-out-0x30
+custom@buffer flags@in-0x0-out-0x8
+custom@buffer flags@in-0x10-out-0x0
+custom@buffer flags@in-0x10-out-0x10
+custom@buffer flags@in-0x10-out-0x20
+custom@buffer flags@in-0x10-out-0x30
+custom@buffer flags@in-0x10-out-0x8
+custom@buffer flags@in-0x20-out-0x0
+custom@buffer flags@in-0x20-out-0x10
+custom@buffer flags@in-0x20-out-0x20
+custom@buffer flags@in-0x20-out-0x8
+custom@buffer flags@in-0x30-out-0x0
+custom@buffer flags@in-0x30-out-0x10
+custom@buffer flags@in-0x30-out-0x20
+custom@buffer flags@in-0x30-out-0x8
+custom@buffer flags@in-0x8-out-0x0
+custom@buffer flags@in-0x8-out-0x10
+custom@buffer flags@in-0x8-out-0x20
+custom@buffer flags@in-0x8-out-0x30
+custom@buffer flags@in-0x8-out-0x8
+dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.srgb8_alpha8_rgba8ui.renderbuffer_to_renderbuffer
+dEQP-GLES31.functional.image_load_store.2d_array.store.rgba8_single_layer
+dEQP-GLES31.functional.image_load_store.buffer.format_reinterpret.r32f_rgba8i
+dEQP-GLES31.functional.ssbo.layout.random.nested_structs.8
+dEQP-GLES31.functional.ssbo.layout.random.vector_types.15
+dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_ivec2
+dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.column_major_highp_mat2x3
+dEQP-GLES31.functional.ssbo.layout.single_basic_type.std140.row_major_mediump_mat4x2
+dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.highp_uvec2
+dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.mediump_mat3
+
+# test_object_interface:1615:pipeline state: Test failed: Test object has 1 references left.
+vkd3d-test_object_interface
+# "test_pipeline_library:369: Test failed: Refcount 2 != 1."
+vkd3d-test_pipeline_library
+# Aborted with malloc corruption
+vkd3d-test_read_subresource_rt
+
+vkd3d-test_fence_signal_availability_plain
+vkd3d-test_planar_video_formats
+vkd3d-test_render_pass_suspend_resume_opts_enabled

src/freedreno/ci/freedreno-a750-skips.txt

@@ -0,0 +1,12 @@
+# Speed up pre-merge testing by removing redundant coverage in force-gmem mode
+gmem-dEQP-VK.api.*
+gmem-dEQP-VK.renderpass\..*
+gmem-dEQP-VK.synchronization\..*
+gmem-dEQP-VK.wsi.*
+
+# Blocks until timeout (then reports Crash):
+# msm_dpu ae01000.display-controller: [drm:hangcheck_handler] *ERROR* 67.5.20.1: hangcheck detected gpu lockup rb 2!
+# msm_dpu ae01000.display-controller: [drm:hangcheck_handler] *ERROR* 67.5.20.1:     completed fence: 4294967112
+# msm_dpu ae01000.display-controller: [drm:hangcheck_handler] *ERROR* 67.5.20.1:     submitted fence: 4294967115
+# *** gpu fault: ttbr0=00000008b80fc000 iova=0000000100691300 dir=READ type=TRANSLATION source=UCHE (3736059565,3736059565,3736059565,3736059565)
+vkd3d-test_fence_pending_signal_cpu_rewind_plain

src/freedreno/ci/freedreno-a750-slow-skips.txt

@@ -0,0 +1,8 @@
+# Note: skips lists for CI are just a list of lines that, when
+# non-zero-length and not starting with '#', will regex match to
+# delete lines from the test list.  Be careful.
+
+# Slow tests that aren't very useful coverage, but pass otherwise.  94% CPU
+# used in ir3 create_variant, but no single pass there dominating its time.
+# Just use the scalar/vec2 cases, which are fast enough for CI.
+dEQP-VK.subgroups.clustered.*.subgroupclustered(min|max|mul|and|or|xor|add)_[iu]64vec[34].*

src/freedreno/ci/gitlab-ci-inc.yml

@@ -0,0 +1,335 @@
+# Rules for changes that impact either freedreno or turnip.
+.freedreno-common-rules:
+  rules:
+    - !reference [.test, rules]
+    - !reference [.no_scheduled_pipelines-rules, rules]
+    - changes: &freedreno_core_file_list
+        - src/freedreno/ci/gitlab-ci.yml
+        - src/freedreno/ci/gitlab-ci-inc.yml
+        - src/freedreno/ci/deqp-$DEQP_SUITE.toml
+        - src/freedreno/ci/$GPU_VERSION-fails.txt
+        - src/freedreno/ci/$GPU_VERSION-flakes.txt
+        - src/freedreno/ci/$GPU_VERSION-skips.txt
+        - src/freedreno/ci/$GPU_VERSION-slow-skips.txt
+        - src/freedreno/ci/$PIGLIT_TRACES_FILE
+        - src/freedreno/ci/$REPLAY_CONFIG
+        - src/freedreno/ci/$GPU_VERSION-vkd3d-fails.txt
+        - src/freedreno/ci/$GPU_VERSION-vkd3d-flakes.txt
+        - src/freedreno/ci/$GPU_VERSION-vkd3d-skips.txt
+        - src/freedreno/common/**/*
+        - src/freedreno/drm/**/*
+        - src/freedreno/fdl/**/*
+        - src/freedreno/ir3/**/*
+        - src/freedreno/isa/**/*
+        - src/freedreno/registers/**/*
+      when: on_success
+
+.freedreno-common-manual-rules:
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.core-manual-rules, rules]
+    - changes:
+        *freedreno_core_file_list
+      when: manual
+
+.freedreno-rules:
+  rules:
+    - !reference [.freedreno-common-rules, rules]
+    - !reference [.gl-rules, rules]
+    - changes: &freedreno_file_list
+        - src/freedreno/ir2/**/*
+        - src/gallium/drivers/freedreno/**/*
+        - src/gallium/winsys/freedreno/**/*
+      when: on_success
+
+.freedreno-manual-rules:
+  rules:
+    - !reference [.freedreno-common-manual-rules, rules]
+    - !reference [.gl-manual-rules, rules]
+    - changes: *freedreno_file_list
+      when: manual
+
+.turnip-rules:
+  rules:
+    - !reference [.freedreno-common-rules, rules]
+    - !reference [.vulkan-rules, rules]
+    - changes: &turnip_file_list
+        - src/freedreno/vulkan/**/*
+      when: on_success
+
+.turnip-manual-rules:
+  rules:
+    - !reference [.freedreno-common-manual-rules, rules]
+    - !reference [.vulkan-manual-rules, rules]
+    - changes: *turnip_file_list
+      when: manual
+
+
+.collabora-freedreno-rules:
+  stage: freedreno
+  rules:
+    - !reference [.test, rules]
+    - !reference [.collabora-farm-rules, rules]
+    - !reference [.freedreno-rules, rules]
+
+.collabora-freedreno-manual-rules:
+  stage: freedreno-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.collabora-farm-manual-rules, rules]
+    - !reference [.freedreno-manual-rules, rules]
+
+
+.collabora-turnip-rules:
+  stage: freedreno
+  rules:
+    - !reference [.test, rules]
+    - !reference [.collabora-farm-rules, rules]
+    - !reference [.turnip-rules, rules]
+
+.collabora-turnip-restricted-rules:
+  stage: freedreno
+  rules:
+    - !reference [.test, rules]
+    - !reference [.restricted-rules, rules]
+    - !reference [.collabora-turnip-rules, rules]
+
+.collabora-turnip-manual-rules:
+  stage: freedreno-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.collabora-farm-manual-rules, rules]
+    - !reference [.turnip-manual-rules, rules]
+
+# For piglit and skqp test jobs that run both GL and VK tests.
+.collabora-freedreno-turnip-rules:
+  stage: freedreno
+  rules:
+    - !reference [.test, rules]
+    - !reference [.collabora-freedreno-rules, rules]
+    - !reference [.collabora-turnip-rules, rules]
+
+.collabora-freedreno-turnip-manual-rules:
+  stage: freedreno-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.collabora-freedreno-manual-rules, rules]
+    - !reference [.collabora-turnip-manual-rules, rules]
+
+.valve-freedreno-manual-rules:
+  stage: freedreno-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.valve-farm-manual-rules, rules]
+    - !reference [.freedreno-manual-rules, rules]
+
+.valve-turnip-rules:
+  stage: freedreno
+  rules:
+    - !reference [.test, rules]
+    - !reference [.valve-farm-rules, rules]
+    - !reference [.turnip-rules, rules]
+
+.valve-turnip-restricted-rules:
+  stage: freedreno
+  rules:
+    - !reference [.test, rules]
+    - !reference [.restricted-rules, rules]
+    - !reference [.valve-turnip-rules, rules]
+
+.valve-turnip-manual-rules:
+  stage: freedreno-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.valve-farm-manual-rules, rules]
+    - !reference [.turnip-manual-rules, rules]
+
+.lumag-freedreno-rules:
+  stage: freedreno
+  rules:
+    - !reference [.test, rules]
+    - !reference [.lumag-farm-rules, rules]
+    - !reference [.freedreno-rules, rules]
+
+.lumag-freedreno-manual-rules:
+  stage: freedreno-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.lumag-farm-manual-rules, rules]
+    - !reference [.freedreno-manual-rules, rules]
+
+.collabora-freedreno-rules-restricted:
+  stage: freedreno
+  rules:
+    - !reference [.test, rules]
+    - !reference [.restricted-rules, rules]
+    - !reference [.collabora-freedreno-rules, rules]
+
+.collabora-freedreno-rules-performance:
+  stage: performance
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.performance-rules, rules]
+    - !reference [.collabora-freedreno-manual-rules, rules]
+  allow_failure: true # see comment in .performance-rules, which we don't inherit this line from.
+  variables:
+    JOB_PRIORITY: 40
+    # Ensure that we are using the release build artifact
+    S3_ARTIFACT_NAME: mesa-arm64-default-release
+  needs:
+    - job: alpine/x86_64_lava-trigger
+      optional: true
+    - job: debian-arm64-release
+      artifacts: false # we pull the artifacts from S3
+  dependencies: null
+
+# Status: https://lava.collabora.dev/scheduler/device_type/dragonboard-410c
+.lava-dragonboard-410c:arm64:
+  variables:
+    BOOT_METHOD: fastboot
+    DEVICE_TYPE: dragonboard-410c
+    DTB: apq8016-sbc-usb-host
+    FDO_CI_CONCURRENT: 8
+    FARM: collabora
+    GPU_VERSION: freedreno-a306
+    KERNEL_IMAGE_NAME: "Image.gz"
+    KERNEL_IMAGE_TYPE: ""
+    RUNNER_TAG: mesa-ci-x86-64-lava-dragonboard-410c
+    LAVA_FIRMWARE: qcom-lava
+
+# Status: https://lava.collabora.dev/scheduler/device_type/dragonboard-820c
+.lava-dragonboard-820c:arm64:
+  variables:
+    BOOT_METHOD: fastboot
+    DEVICE_TYPE: dragonboard-820c
+    DTB: apq8096-db820c
+    FDO_CI_CONCURRENT: 8
+    FARM: collabora
+    GPU_VERSION: freedreno-a530
+    KERNEL_IMAGE_NAME: "Image.gz"
+    KERNEL_IMAGE_TYPE: ""
+    RUNNER_TAG: mesa-ci-x86-64-lava-dragonboard-820c
+    LAVA_FIRMWARE: qcom-lava
+
+# Status: https://lava.collabora.dev/scheduler/device_type/sc7180-trogdor-kingoftown
+.lava-sc7180-trogdor-kingoftown:arm64:
+  variables:
+    BOOT_METHOD: depthcharge
+    DEVICE_TYPE: sc7180-trogdor-kingoftown
+    DTB: sc7180-trogdor-kingoftown
+    FDO_CI_CONCURRENT: 8
+    # Increase the hangcheck timer for our spilling tests which bump up against
+    # the .5s default.
+    FREEDRENO_HANGCHECK_MS: 2000
+    FARM: collabora
+    GPU_VERSION: freedreno-a618
+    KERNEL_IMAGE_TYPE: ""
+    RUNNER_TAG: mesa-ci-x86-64-lava-sc7180-trogdor-kingoftown
+    DRIVER_NAME: freedreno-a6xx
+    VK_DRIVER: freedreno
+    LAVA_FIRMWARE: qcom-lava
+
+# Status: https://lava.collabora.dev/scheduler/device_type/sc7180-trogdor-wormdingler-rev1-boe
+.lava-sc7180-trogdor-wormdingler-rev1-boe:arm64:
+  variables:
+    BOOT_METHOD: depthcharge
+    DEVICE_TYPE: sc7180-trogdor-wormdingler-rev1-boe
+    DTB: sc7180-trogdor-wormdingler-rev1-boe
+    FDO_CI_CONCURRENT: 8
+    # Increase the hangcheck timer for our spilling tests which bump up against
+    # the .5s default.
+    FREEDRENO_HANGCHECK_MS: 2000
+    FARM: collabora
+    GPU_VERSION: freedreno-a618
+    KERNEL_IMAGE_TYPE: ""
+    RUNNER_TAG: mesa-ci-x86-64-lava-sc7180-trogdor-wormdingler-rev1-boe
+    DRIVER_NAME: freedreno-a6xx
+    VK_DRIVER: freedreno
+    LAVA_FIRMWARE: qcom-lava
+
+# Status: https://lava.collabora.dev/scheduler/device_type/sm8350-hdk
+.lava-sm8350-hdk:arm64:
+  variables:
+    BOOT_METHOD: fastboot
+    DEVICE_TYPE: sm8350-hdk
+    DTB: sm8350-hdk
+    FDO_CI_CONCURRENT: 9
+    # Increase the hangcheck timer for our spilling tests which bump up against
+    # the .5s default.
+    FREEDRENO_HANGCHECK_MS: 2000
+    FARM: collabora
+    GPU_VERSION: freedreno-a660
+    KERNEL_IMAGE_NAME: "Image.gz"
+    KERNEL_IMAGE_TYPE: ""
+    RUNNER_TAG: mesa-ci-x86-64-lava-sm8350-hdk
+    # The device has A/B boot slots - select slot A
+    LAVA_FASTBOOT_CMD: "set_active a"
+    DRIVER_NAME: freedreno-a6xx
+    VK_DRIVER: freedreno
+    LAVA_FIRMWARE: qcom-lava
+
+
+# CI-tron
+
+.a200:
+  variables:
+    FDO_CI_CONCURRENT: 2
+    CI_TRON_DUT_SETUP_TAGS: dt_gpu:codename:a200
+    CI_TRON_INITRAMFS_CATEGORY__50_PLATFORM__0__URL: 'https://${S3_BASE_PATH}/${FIRMWARE_REPO}/qcom-${FIRMWARE_TAG}.tar'
+    CI_TRON_INITRAMFS_CATEGORY__50_PLATFORM__0__FORMAT__0__ARCHIVE__EXTENSION: 'cpio'
+    CI_TRON_INITRAMFS_CATEGORY__50_PLATFORM__0__FORMAT__0__ARCHIVE__KEEP__0__PATH: '(./lib/firmware/qcom/yamato.*)'
+    # as good as anything else, works for now
+    CI_TRON_DTB__0__URL: '$KERNEL_IMAGE_BASE/armhf/imx53-qsrb.dtb'
+    CI_TRON__B2C_SWAP_SIZE: '4g'
+    CI_TRON_TIMEOUT__FIRST_CONSOLE_ACTIVITY__MINUTES: 0.5
+    CI_TRON_TIMEOUT__FIRST_CONSOLE_ACTIVITY__RETRIES: 3
+    CI_TRON_WATCHDOG__FIRMWARE_TO_LINUX__MINUTES: 1.0
+    CI_TRON_WATCHDOG__FIRMWARE_TO_LINUX__RETRIES: 5
+    CI_TRON_WATCHDOG__FIRMWARE_TO_LINUX__START_REGEX: 'Model: Freescale i.MX53 Quick Start Board'  # A line repeated during firmware boot
+    CI_TRON_WATCHDOG__FIRMWARE_TO_LINUX__STOP_REGEX: 'CPU identified as i.MX53'                    # A line repeated during Linux boot
+    GPU_VERSION: freedreno-a200
+    RUNNER_FARM_LOCATION: lumag
+
+
+.a750:
+  variables:
+    FDO_CI_CONCURRENT: 8
+    CI_TRON_DUT_SETUP_TAGS: dt_gpu:codename:a750
+    CI_TRON_KERNEL__URL: '$KERNEL_IMAGE_BASE/arm64/Image.gz'
+    CI_TRON_INITRAMFS_CATEGORY__50_PLATFORM__0__URL: "https://${S3_BASE_PATH}/${FIRMWARE_REPO}/qcom-${FIRMWARE_TAG}.tar"
+    CI_TRON_INITRAMFS_CATEGORY__50_PLATFORM__0__FORMAT__0__ARCHIVE__EXTENSION: cpio
+    CI_TRON_INITRAMFS_CATEGORY__50_PLATFORM__0__FORMAT__0__ARCHIVE__KEEP__0__PATH: './lib/firmware/qcom/(sm8650/)?.*gen70900.*'
+    CI_TRON_DTB__0__URL: '$KERNEL_IMAGE_BASE/arm64/sm8650-hdk.dtb'
+    CI_TRON__B2C_SWAP_SIZE: '16g'
+    CI_TRON_TIMEOUT__FIRST_CONSOLE_ACTIVITY__MINUTES: 0.5
+    CI_TRON_TIMEOUT__FIRST_CONSOLE_ACTIVITY__RETRIES: 3
+    CI_TRON_WATCHDOG__FIRMWARE_TO_LINUX__MINUTES: 0.3
+    CI_TRON_WATCHDOG__FIRMWARE_TO_LINUX__RETRIES: 5
+    CI_TRON_WATCHDOG__FIRMWARE_TO_LINUX__START_REGEX: 'VB: RWDeviceState: Succeed using devinfo!'  # A line repeated during firmware boot
+    CI_TRON_WATCHDOG__FIRMWARE_TO_LINUX__STOP_REGEX: 'CPU features: detected:'                     # A line repeated during Linux boot
+    GPU_VERSION: freedreno-a750
+    DRIVER_NAME: freedreno-a6xx
+    VK_DRIVER: freedreno
+
+
+# 6 devices (2025-09-28)
+.a750-kws:
+  extends:
+    - .a750
+  variables:
+    RUNNER_FARM_LOCATION: keywords
+
+# 1 device (2025-09-15)
+.a750-mupuf:
+  extends:
+    - .a750
+  variables:
+    RUNNER_FARM_LOCATION: mupuf

src/freedreno/ci/gitlab-ci.yml

@@ -0,0 +1,378 @@
+include:
+  - local: 'src/freedreno/ci/gitlab-ci-inc.yml'
+
+a200-gl:
+  extends:
+    - .ci-tron-arm32-test-gl
+    - .a200
+    - .lumag-freedreno-manual-rules
+  timeout: 180m
+  parallel: 3
+  variables:
+    CI_TRON_TIMEOUT__OVERALL__MINUTES: 180
+    DEQP_SUITE: freedreno-a200
+
+a306-gl:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-dragonboard-410c:arm64
+    - .collabora-freedreno-rules
+  variables:
+    DEQP_SUITE: freedreno-a306
+    FDO_CI_CONCURRENT: 6
+  parallel: 5
+
+a306-piglit:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-dragonboard-410c:arm64
+    - .test-piglit
+    - .collabora-freedreno-manual-rules
+  timeout: 40m
+  variables:
+    DEQP_SUITE: freedreno-a306-piglit
+    HWCI_START_WESTON: 1
+    TEST_PHASE_TIMEOUT_MINUTES: 35
+
+# Something happened and now this hangchecks and doesn't recover.  Unkown when
+# it started.
+.a306-piglit-gl:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-dragonboard-410c:arm64
+    - .test-piglit
+    - .collabora-freedreno-manual-rules
+  variables:
+    BM_KERNEL_EXTRA_ARGS: "msm.num_hw_submissions=1"
+    DEQP_SUITE: freedreno-a306-piglit-quick-gl
+    FDO_CI_CONCURRENT: 3
+    HWCI_START_WESTON: 1
+
+a306-piglit-shader:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-dragonboard-410c:arm64
+    - .test-piglit
+    - .collabora-freedreno-manual-rules
+  variables:
+    DEQP_SUITE: freedreno-a306-piglit-quick-shader
+    FDO_CI_CONCURRENT: 6
+    HWCI_START_WESTON: 1
+
+a306-traces:
+  extends:
+    - .lava-arm64-piglit-traces
+    - .lava-dragonboard-410c:arm64
+    - .collabora-freedreno-rules
+  variables:
+    HWCI_START_WESTON: 1
+    PIGLIT_REPLAY_DEVICE_NAME: "${GPU_VERSION}"
+    PIGLIT_TRACES_FILE: traces-freedreno.yml
+
+a530-gl:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-dragonboard-820c:arm64
+    - .test-piglit
+    - .collabora-freedreno-rules
+  variables:
+    DEQP_SUITE: freedreno-a530
+    FDO_CI_CONCURRENT: 3  # if 4, sometimes "deqp-gles31, not enough memory for the allocation" appears
+  parallel: 6
+
+a530-traces:
+  extends:
+    - .lava-arm64-piglit-traces
+    - .lava-dragonboard-820c:arm64
+    - .collabora-freedreno-rules
+  variables:
+    HWCI_START_WESTON: 1
+    PIGLIT_REPLAY_DEVICE_NAME: "${GPU_VERSION}"
+    PIGLIT_TRACES_FILE: traces-freedreno.yml
+
+a530-piglit:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-dragonboard-820c:arm64
+    - .test-piglit
+    - .collabora-freedreno-manual-rules
+  parallel: 2
+  variables:
+    DEQP_SUITE: freedreno-a530-piglit
+    HWCI_START_WESTON: 1
+
+a618-angle:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-sc7180-trogdor-kingoftown:arm64
+    - .collabora-turnip-manual-rules
+    - .test-angle
+  variables:
+    DEQP_SUITE: tu-angle
+    DRIVER_NAME: null  # Don't use freedreno skips
+
+a618-vk:
+  extends:
+    - .lava-arm64-test-vk
+    - .lava-sc7180-trogdor-wormdingler-rev1-boe:arm64
+    - .collabora-turnip-rules
+  parallel: 11
+  variables:
+    DEQP_SUITE: freedreno-a618-vk
+    FLAKES_CHANNEL: "#freedreno-ci"
+
+a618-vk-asan:
+  extends:
+    - .lava-arm64-test-asan-vk
+    - .lava-sc7180-trogdor-kingoftown:arm64
+    - .collabora-turnip-rules
+  timeout: 2h
+  variables:
+    DEQP_SUITE: freedreno-a618-vk-asan
+    FLAKES_CHANNEL: "#freedreno-ci"
+    FDO_CI_CONCURRENT: 2 # We get OOMkills if we go too wide with asan enabled
+
+a618-gles-asan:
+  extends:
+    - .lava-arm64-test-asan-gl
+    - .lava-sc7180-trogdor-kingoftown:arm64
+    - .collabora-freedreno-manual-rules
+  variables:
+    DEQP_SUITE: freedreno-a618-gles-asan
+    FLAKES_CHANNEL: "#freedreno-ci"
+    FDO_CI_CONCURRENT: 2 # We get OOMkills if we go too wide with asan enabled
+
+# Run dEQP EGL window system tests with the window systems available.
+# wayland and xwayland run headless.
+a618-gl:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-sc7180-trogdor-kingoftown:arm64
+    - .collabora-freedreno-rules
+  variables:
+    DEQP_SUITE: freedreno-a618
+    FLAKES_CHANNEL: "#freedreno-ci"
+    HWCI_START_WESTON: 1
+    DEQP_FRACTION: 4
+
+a618-gl-full:
+  extends:
+    - a618-gl
+    - .collabora-freedreno-manual-rules
+  timeout: 65m
+  variables:
+    FDO_CI_CONCURRENT: 6  # More causes issues and slows the job down
+    DEQP_FRACTION: 1
+
+a618-skqp:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-sc7180-trogdor-kingoftown:arm64
+    - .collabora-freedreno-rules
+    # SKQP tests both the GL and VK drivers.
+    - .collabora-freedreno-turnip-rules
+  variables:
+    FLAKES_CHANNEL: "#freedreno-ci"
+    HWCI_START_XORG: 1
+    DEQP_SUITE: freedreno-a618-skqp
+
+a618-piglit:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-sc7180-trogdor-kingoftown:arm64
+    - .test-piglit
+    # Note that piglit has GL+VK integration testing.
+    - .collabora-freedreno-turnip-rules
+  rules:
+    - !reference [.collabora-freedreno-turnip-rules, rules]
+    - !reference [.rusticl-rules, rules]
+  variables:
+    DEQP_SUITE: freedreno-a618-piglit
+    FDO_CI_CONCURRENT: 6  # More causes issues and isn't much faster anyway
+    FLAKES_CHANNEL: "#freedreno-ci"
+    HWCI_START_WESTON: 1
+
+a618-piglit-full:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-sc7180-trogdor-kingoftown:arm64
+    - .test-piglit
+    # Note that piglit has GL+VK integration testing.
+    - .collabora-freedreno-turnip-manual-rules
+  timeout: 60m
+  variables:
+    DEQP_SUITE: freedreno-a618-piglit-full
+    FLAKES_CHANNEL: "#freedreno-ci"
+    HWCI_START_WESTON: 1
+
+a618-traces:
+  extends:
+    - .lava-arm64-piglit-traces
+    - .lava-sc7180-trogdor-kingoftown:arm64
+    - .collabora-freedreno-rules
+  variables:
+    HWCI_START_WESTON: 1
+    # So we aren't capped by VSync by the X server
+    EGL_PLATFORM: surfaceless
+    FDO_CI_CONCURRENT: 5  # 6 is too much leading to OOM
+    FLAKES_CHANNEL: "#freedreno-ci"
+    PIGLIT_REPLAY_DEVICE_NAME: "${GPU_VERSION}"
+    # This lets us run several more traces which don't use any features we're
+    # missing.
+    MESA_GLSL_VERSION_OVERRIDE: "460"
+    MESA_GL_VERSION_OVERRIDE: "4.6"
+    PIGLIT_TRACES_FILE: traces-freedreno.yml
+
+a618-traces-performance:
+  extends:
+    - a618-traces
+    - .collabora-freedreno-rules-performance
+    - .piglit-performance-base
+  rules:
+    - !reference [.piglit-performance-base, rules]
+    - !reference [.collabora-freedreno-rules-performance, rules]
+  variables:
+    # Always use the same device
+    # a618 tag starts with cbg-1 (not cbg-0) for some reason
+    LAVA_TAGS: "cbg-1"
+
+a618-android:
+  extends:
+    - .lava-arm64-test-android
+    - .lava-sc7180-trogdor-kingoftown:arm64
+    - .collabora-freedreno-turnip-rules
+    - .test-angle
+  variables:
+    CUTTLEFISH_GPU_MODE: drm_nctx_guest_angle
+    DEQP_SUITE: tu-android
+    FDO_CI_CONCURRENT: 6  # We get OOMkills if we go too wide since VKCTS 1.4.4.0
+
+a618-android-cts:
+  extends:
+    - .lava-arm64-test-android
+    - .lava-sc7180-trogdor-kingoftown:arm64
+    - .collabora-turnip-manual-rules
+    - .test-android-cts
+    - .test-angle
+  timeout: 2h
+  variables:
+    CUTTLEFISH_GPU_MODE: drm_nctx_guest_angle
+    DEVICE_HANGING_TIMEOUT_SEC: 5400  # Android CTS might not print anything for minutes
+
+a660-angle:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-sm8350-hdk:arm64
+    - .collabora-turnip-manual-rules
+    - .test-angle
+  variables:
+    DEQP_SUITE: tu-angle
+    DRIVER_NAME: null  # Don't use freedreno skips
+
+a660-gl-cl:
+  extends:
+    - .lava-arm64-test-gl
+    - .lava-sm8350-hdk:arm64
+    - .test-piglit
+    - .collabora-freedreno-rules
+  rules:
+    - !reference [.collabora-freedreno-rules, rules]
+    - !reference [.rusticl-rules, rules]
+  parallel: 2
+  variables:
+    DEQP_SUITE: freedreno-a660
+    HWCI_START_WESTON: 1
+
+a660-vk:
+  extends:
+    - .lava-arm64-test-vk
+    - .collabora-turnip-rules
+    - .lava-sm8350-hdk:arm64
+  parallel: 3
+  variables:
+    DEQP_SUITE: freedreno-a660-vk
+    FLAKES_CHANNEL: "#freedreno-ci"
+
+a660-vk-full:
+  extends:
+    - a660-vk
+    - .collabora-turnip-manual-rules
+  parallel: 3
+  timeout: 2h
+  variables:
+    DEQP_SUITE: freedreno-a660-vk-full
+    DEQP_FRACTION: 1
+
+a660-vk-traces-restricted:
+  extends:
+    - .lava-arm64-test-vk
+    - .collabora-turnip-restricted-rules
+    - .lava-sm8350-hdk:arm64
+    - .traces-test
+    - .test-wine
+  variables:
+    REPLAY_CONFIG: traces-freedreno-restricted.toml
+    ANGLE_TRACE_FILES_TAG: "2025-03-28"
+    HWCI_START_WESTON: 1
+  allow_failure: true
+
+a750-angle:
+  extends:
+    - .ci-tron-arm64-test-gl
+    - .a750-mupuf
+    - .valve-turnip-manual-rules
+    - .test-angle
+  timeout: 25m  # base runtime 10min total, 7min of testing
+  variables:
+    CI_TRON_TIMEOUT__OVERALL__MINUTES: 20
+    DEQP_SUITE: tu-angle
+    DRIVER_NAME: null  # Don't use freedreno skips
+
+a750-gl-cl:
+  extends:
+    - .ci-tron-arm64-test-gl
+    - .test-piglit
+    - .a750-mupuf
+    - .valve-freedreno-manual-rules
+  rules:
+    - !reference [.valve-freedreno-manual-rules, rules]
+    - !reference [.rusticl-manual-rules, rules]
+  timeout: 30m  # base runtime 11min total, 8min of testing
+  variables:
+    CI_TRON_TIMEOUT__OVERALL__MINUTES: 25
+    HWCI_START_WESTON: 1
+    DEQP_SUITE: freedreno-a750
+
+a750-vk:
+  extends:
+    - .test-vkd3d-proton # must come before other extends, since we don't want its HWCI_TEST_SCRIPT
+    - .ci-tron-arm64-test-vk
+    - .a750-kws
+    - .valve-turnip-rules
+  parallel: 4
+  timeout: 18m  # base runtime is 12.5, 11min of testing
+  variables:
+    CI_TRON_TIMEOUT__OVERALL__MINUTES: 16
+    DEQP_SUITE: freedreno-a750-vk
+    DEQP_FRACTION: 2
+
+# A750 VK traces are disabled because they time out -- we have a lot of:
+# [  465.720843] adreno 3d00000.gpu: CP | protected mode error | WRITE | addr=0x0000930A | status=0x0060930A
+# [  465.982685] adreno 3d00000.gpu: [drm:a6xx_irq] *ERROR* gpu fault ring 0 fence ffffff25 status 00800005 rb 0072/009e ib1 0000000101655000/0043 ib2 0000000100404900/0000
+# [  465.998171] msm_dpu ae01000.display-controller: [drm:recover_worker] *ERROR* 67.5.20.1: hangcheck recover!
+# [  466.008147] msm_dpu ae01000.display-controller: [drm:recover_worker] *ERROR* 67.5.20.1: offending task: weston (weston --config=/install/common/weston.ini --socket=wayland-0 --log /builds/anholt/mesa/results/weston.log --logger-scopes=log,xwm-wm-x11 --renderer=gl)
+# and maybe that's the problem -- let's try this (and rebalance core VK coverage) once we figure it out.
+.a750-vk-restricted-traces:
+  extends:
+    - .ci-tron-arm64-test-vk
+    - .a750-kws
+    - .valve-turnip-restricted-rules
+    - .traces-test
+    - .test-wine
+  timeout: 20m
+  variables:
+    MESA_LOADER_DRIVER_OVERRIDE: "zink"
+    CI_TRON_TIMEOUT__OVERALL__MINUTES: 16
+    REPLAY_CONFIG: traces-freedreno-restricted.toml
+    HWCI_START_WESTON: 1
+  allow_failure: true

src/freedreno/ci/restricted-traces-freedreno.yml

@@ -0,0 +1,87 @@
+%YAML 1.2
+---
+traces-db:
+  download-url: "https://s3.freedesktop.org/mesa-tracie-private/"
+
+traces:
+  stellaris/Stellaris-trim--f722-v20201203-v2.trace:
+    freedreno-a618:
+      label: [skip, slow, crash]
+      text: triggers Hangcheck on testing runner (not on OnePlus 6T thou)
+      checksum: 9d3e44e66842611728c7db0cfb29862c
+  SirYouAreBeingHunted/sir-f750-v2.trace:
+    freedreno-a618:
+      label: [slow]
+      checksum: 8369e3a59f2a61d0212dafc86c7d0dcf
+  SpecOps/specops-s0-1088-f1300-v2.trace:
+    freedreno-a618:
+      label: [slow, skip, flakes]
+      checksum: 8ab8fa893171d6b21cf8af2d6d4e1f17
+  AmnesiaTDD/Amnesia-f700-v2.trace:
+    freedreno-a618:
+      checksum: 26f6493537a2228a392b001c6e5a9cfe
+  Antichamber/antichamber-f240-v2.trace:
+    freedreno-a618:
+      checksum: 2df47f6dffc78e01ba94ff6600e54bfa
+  ICEDarkness/ICEDarkness-f230-v2.trace:
+    freedreno-a618:
+      checksum: 06687fb890f32bcd44e922558f47e553
+  LifelessPlanet/LifelessPlanet-f420-v2.trace:
+    freedreno-a618:
+      checksum: 67694d4c5ddd2e353786b7400f26eae9
+  civilization-v/CivilizationV-trim--s705-761-f762-v20201203-v2.trace:
+    freedreno-a618:
+      label: [skip, flakes]
+      checksum: 282b0fdb96624977fa656d93745c1037
+      text: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7491
+  golf-with-your-friends/GolfWithYourFriends-trim--f1070-v20201203-v2.trace:
+    freedreno-a618:
+      checksum: cd01820de77063f0397f26d6cd747d1c
+  TheRavenRemastered/Raven-f10900-v2.trace:
+    freedreno-a618:
+      checksum: c9fdace50bcf6ca9b739d5bb7b4720ac
+  PenumbraOverture/penumbra-ov-s0-2-864-f1500-v2.trace:
+    freedreno-a618:
+      label: [skip, broken]
+      checksum: a3cc3e461c15d0469d258c5c6dcd6cbb
+      text: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12465#note_2745831
+  hollow-knight/HollowKnight-trim--f2020-v20201203-v2.trace:
+    freedreno-a618:
+      checksum: 6020da5ac6e5b7d410984dee52e5d36c
+  Superhot/superhot-f8100-v2.trace:
+    freedreno-a618:
+      checksum: 21a4901a1e4fc1664ddd314c956625ea
+  overcooked2/Overcooked2-trim--f3301-v20201203-v2.trace:
+    freedreno-a618:
+      checksum: 837456fa4fdd382fc120df03e7bee2eb
+  Osmos/Osmos-f2660-v2.trace:
+    freedreno-a618:
+      checksum: cea8067f4538fd73e3505f58f0b7044e
+  ksp/KSP-trim--f4800-v20201203-v2.trace:
+    freedreno-a618:
+      checksum: 37007359e6b16f0d07ebd48e3ff49f2d
+  Witcher2/witcher2-s0-1970-f2038-v2.trace:
+    freedreno-a618:
+      label: [skip, broken]
+  ShadowWarrior/ShadowWarrior-f3952-v2.trace:
+    freedreno-a618:
+      label: [skip, flakes]
+  Cradle/cradle-f3000-v2.trace:
+    freedreno-a618:
+      label: [unsupported]
+  OilRush/OilRush-f14000-v2.trace:
+    freedreno-a618:
+      label: [skip, slow]
+  TombRaider2013/TombRaider-f1430-v2.trace:
+    freedreno-a618:
+      label: [unsupported]
+  MetroLLRedux/metro-ll-redux-kf480-v2.trace:
+    freedreno-a618:
+      label: [skip, slow]
+  alien-isolation/AlienIsolation.bin.1-trim--k-f2000-v20201203-v2.trace:
+    freedreno-a618:
+      label: [fail]
+  slime-rancher/SlimeRancher-trim--f970-v20201203-v2.trace:
+    freedreno-a618:
+      label: [skip]
+      text: Cannot download for some reason.

src/freedreno/ci/traces-freedreno.yml

@@ -0,0 +1,574 @@
+%YAML 1.2
+---
+traces-db:
+  download-url: https://s3.freedesktop.org/mesa-tracie-public/
+
+text: |-
+  NOTE for faster runtime, try to sort tests so the longer running traces
+  appear first (and therefore are started first).
+
+  Current approx durations for the longer traces (17 Jun 2021):
+
+    half-life-2:          37.83s
+    portal:               16.29s
+    counterstrike-source: 14.24s
+    xonotic:              13.46s
+    stk:                  11.15s
+    0ad:                  10.93s
+    counterstrike:         9.87s
+    neverball:             8.53s
+
+traces:
+  valve/half-life-2-v2.trace:
+    freedreno-a306:
+      checksum: 8f5929c82e7d990e8c3d2bea14688224
+      label: [skip, slow]
+    freedreno-a530:
+      checksum: 5def334bb574b024198ddddb1a069529
+    freedreno-a618:
+      checksum: a1710b1977081218f518cf988c86c6e6
+    zink-a618:
+      checksum: 45bdbb33bf87ed114bd548248be13408
+      label: [skip, broken]
+      text: |
+        MESA: warning: zink: PERF WARNING! > 100 copy boxes detected for 0xaaaaeeea5240
+        MESA: error: ZINK: vkQueueSubmit failed (VK_ERROR_DEVICE_LOST)
+        hl2_linux: ../src/gallium/drivers/zink/zink_batch.c:640: zink_end_batch: Assertion `!ctx->batch_states' failed.
+
+  valve/portal-2-v2.trace:
+    freedreno-a306:
+      checksum: a3a9e158ccf7fa5ba978e045505a060e
+      label: [skip, slow]
+    freedreno-a530:
+      checksum: 102a09ce76092436173fd09a6a2bd941
+    freedreno-a618:
+      checksum: e0e18dcc50ab2e23cead650d64469178
+    zink-a618:
+      checksum: b7e0cdb0db74ea9a31fb7a75ae0d76fc
+
+  valve/counterstrike-source-v2.trace:
+    freedreno-a306:
+      checksum: 4b707f385256b380c936186db8c251cb
+      label: [skip, broken, slow]
+      text: Broken minimap rendering since around !14643
+    freedreno-a530:
+      checksum: bbe74b2171d62fc6738086740e1aa0d8
+    freedreno-a618:
+      checksum: e7b57988348b2ce98b964d71b18c1771
+    zink-a618:
+      label: [skip, slow]
+      checksum: ade41e6fe932552914c678155149babb
+
+  xonotic/xonotic-keybench-high-v2.trace:
+    freedreno-a306:
+      checksum: 0efd30250af93d0b5f03eeabd079e8ee
+      label: [skip, slow]
+    freedreno-a530:
+      checksum: 0efd30250af93d0b5f03eeabd079e8ee
+      label: [skip, slow]
+    freedreno-a618:
+      checksum: 0efd30250af93d0b5f03eeabd079e8ee
+    zink-a618:
+      checksum: 947da2890506f363d3aef0d1a981eec6
+
+  godot/godot-tps-gles3-high.trace:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+    freedreno-a618:
+      checksum: b5fdea0f949c4c02c86b5785e0556dfe
+    zink-a618:
+      label: [skip, flakes]
+      checksum: 96f7f231042f892c7d11c91defd7ecc1
+      text: May time out
+
+  godot/godot-thrive.trace:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+    freedreno-a618:
+      label: [skip]
+    zink-a618:
+      label: [crash, skip]
+      checksum: 491a16f1f9bf8bc467fadbc8439c1a2a
+      text: causes GPU hangs on turnip+zink too, see https://gitlab.freedesktop.org/mesa/mesa/-/issues/7732
+
+  supertuxkart/supertuxkart-mansion-egl-gles-v2.trace:
+    freedreno-a306:
+      checksum: 1ae49af7017ae2a08fbb1caf377ada91
+      label: [skip, slow]
+    freedreno-a530:
+      checksum: 1ae49af7017ae2a08fbb1caf377ada91
+      label: [skip, slow]
+    freedreno-a618:
+      checksum: 47016a34553e5a28e2e1e0b92d11c92f
+    zink-a618:
+      label: [crash, skip]
+      checksum: 5cd30bb46cbabc0d77cc4aacbcd7c0c2
+      text: >
+        Got intermittent crash with the following log message:
+          MESA: warning: zink: PERF WARNING! > 100 copy boxes detected for 0xaaaaeb0949c0
+          MESA: warning: zink: PERF WARNING! > 100 copy boxes detected for 0xaaaaeb0949c0
+          apitrace: warning: caught signal 11
+          74882: error: caught an unhandled exception
+        Source:
+        https://gallo.pages.freedesktop.org/-/mesa/-/jobs/38460939/artifacts/results/summary/results/trace@zink-a618@[email protected]
+
+  0ad/0ad-v2.trace:
+    freedreno-a306:
+      checksum: ea2b03e0768e8400c0badd46e4d26087
+      label: [hang, slow]
+      text: triggers hangcheck on db410c
+    freedreno-a530:
+      checksum: b007061e6e93020ddf2aff6a0f32ed72
+      label: [skip, slow]
+      text: 2 minute runtime on db820c
+    freedreno-a618:
+      checksum: e0b4cb968d2653a568f0ea5eeee4d39a
+    zink-a618:
+      label: [skip, timeout]
+
+  valve/counterstrike-v2.trace:
+    freedreno-a306:
+      checksum: b4af9243e34f3de0153b6855dc9c66b6
+      label: [skip]
+      text: |-
+        With the addition of userspace fences we start feeding the GPU fast
+        enough to hit bad behavior on kernel side with ringbuffer-full
+        situations.  Kernel side fix is WIP, disable for now.
+    freedreno-a530:
+      label: [skip, flakes]
+    freedreno-a618:
+      checksum: 1b9a79f0088a3ddb5723f217d37cee74
+    zink-a618:
+      checksum: e4e5415f7a81a6bd14b7ff8f67083cbf
+
+  neverball/neverball-v2.trace:
+    freedreno-a306:
+      checksum: 57fd57aef14d37043a7b56a16dbf50b6
+      label: [skip, slow]
+    freedreno-a530:
+      checksum: 2a53e6086588f4675ae3dcda9f26603b
+      label: [skip, slow]
+    freedreno-a618:
+      checksum: 730692659fbb9eefa44d6b1a2df2fa8e
+    zink-a618:
+      checksum: 552e62fabd05ebfbb6d7bdd574b4e1c7
+
+  behdad-glyphy/glyphy-v2.trace:
+    freedreno-a306:
+      checksum: 2d4a6b609ba58cfb0df1e78ef30c7ab5
+    freedreno-a530:
+      checksum: 3a37faf7ec62d48dada63f157f30d876
+    freedreno-a618:
+      label: [no-perf]
+      checksum: d25edb433abfcde517b626b3071906ff
+    zink-a618:
+      label: [no-perf]
+      checksum: a8a714fd7017fb07be6c3e904595eb0f
+
+  glxgears/glxgears-2-v2.trace:
+    freedreno-a306:
+      checksum: 3df913932335f17918c55aa70cfba817
+      label: [broken]
+      text: inner rings are flat shaded when they should be smooth
+    freedreno-a530:
+      checksum: 4e980c27c1715a355d3226295b3885e9
+      label: [broken]
+      text: bad shading on the inner ring of red
+    freedreno-a618:
+      checksum: 3ff0833c1456ad05fa9dab751decd838
+    zink-a618:
+      checksum: 3ff0833c1456ad05fa9dab751decd838
+
+  gputest/furmark-v2.trace:
+    freedreno-a306:
+      checksum: 751e0e784ba2f003cfc456fe8699f1fa
+      label: [hang]
+    freedreno-a530:
+      checksum: 1a4fbb06c7453efe0c71455f6be475c1
+    freedreno-a618:
+      checksum: 709d72f86faa9b768495888b49cad086
+    zink-a618:
+      checksum: f4e4216bfcf202d680b1cb6a20ef2dd5
+
+# gimark requires an environment var to work around a bug, disable for now
+#  gputest/gimark-v2.trace:
+#    freedreno-a306:
+#      label: [unsupported]
+#      text: requires GL 3.3
+#    freedreno-a530:
+#      label: [unsupported]
+#      text: requires GL 3.3
+#    freedreno-a618:
+#      checksum: e58167bd8eeb8952facbc00ff0449135
+#    zink-a618:
+#      checksum: e58167bd8eeb8952facbc00ff0449135
+
+  gputest/pixmark-julia-fp32-v2.trace:
+    freedreno-a306:
+      checksum: 650e670be449771ff192faff3af56e74
+    freedreno-a530:
+      checksum: 591ed55990423caad0a7e5da6bc3b441
+    freedreno-a618:
+      label: [no-perf]
+      checksum: 95bbb55cc2d59dc9523120f49a2adf5d
+    zink-a618:
+      checksum: 95bbb55cc2d59dc9523120f49a2adf5d
+
+  gputest/pixmark-julia-fp64-v2.trace:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+      text: requires GL 4
+    freedreno-a618:
+      label: [skip, slow]
+      checksum: 2ab33ccad9887ef6d09e8448217b359b
+      text: |
+        May take longer than 5 min:
+        https://gallo.pages.freedesktop.org/-/mesa/-/jobs/38411151/artifacts/results/summary/results/trace@freedreno-a618@[email protected]
+    zink-a618:
+      label: [skip, flakes]
+      checksum: 2a99e051c8a0126f2283e6b9bbb2fb40
+      text: 'Unsupported SPIR-V capability: SpvCapabilityInt64 (11)'
+
+  gputest/pixmark-volplosion-v2.trace:
+    freedreno-a306:
+      label: [hang]
+    freedreno-a530:
+      checksum: 57bb50e4a016bf870ee192057de3c19e
+      text: Looks fine, but totally different shape from the rendering on i965.
+    freedreno-a618:
+      checksum: dbd6130eeae3eb6d5df73f3069beae28
+    zink-a618:
+      checksum: dbd6130eeae3eb6d5df73f3069beae28
+
+  gputest/plot3d-v2.trace:
+    freedreno-a306:
+      checksum: 4e9d4eae83618e47b655de9fd8536e84
+    freedreno-a530:
+      checksum: 512da39a517434eaaf9d8daaf7b736ea
+    freedreno-a618:
+      checksum: 361926f700dac2db7e95a983f1d63e62
+    zink-a618:
+      checksum: 361926f700dac2db7e95a983f1d63e62
+
+  gputest/tessmark-v2.trace:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+      text: Requires GL4 for tess.
+    freedreno-a618:
+      checksum: 92312303aa8279214f0a300a625efa87
+    zink-a618:
+      checksum: 1fd6650d5f929fdac04430d0e22e0269
+
+  gputest/triangle-v2.trace:
+    freedreno-a306:
+      checksum: aa9f373a7aef4bf03942c0b4c71ff900
+    freedreno-a530:
+      checksum: a7142cfb819f5f45863ccca75a5e26a5
+    freedreno-a618:
+      checksum: 2cbd1de2e9ed281b3cd19c957858c81a
+    zink-a618:
+      checksum: 2cbd1de2e9ed281b3cd19c957858c81a
+
+  humus/AmbientAperture-v2.trace:
+    freedreno-a306:
+      checksum: 8d4c52f0af9c09710d358f24c73fae3c
+    freedreno-a530:
+      checksum: aab5c853e383e1cda56663d65f6925ad
+    freedreno-a618:
+      checksum: 83fd7bce0fc1e1f30bd143b7d30ca890
+    zink-a618:
+      checksum: 5263f9d22462a6f48f5ca9e91d146f06
+
+  humus/CelShading-v2.trace:
+    freedreno-a306:
+      checksum: daedd0c29d197ee1b6a4a7dea72ec87b
+      label: [broken]
+      text: Z or stencil failures or something on the cel shading outlines on a306
+    freedreno-a530:
+      checksum: c424072f305db125ffd9e3f5bebcb512
+    freedreno-a618:
+      checksum: b0ac8fb4b2b2268cfb87944730125886
+    zink-a618:
+      checksum: bd713b79eaa2a7ebbf4ebebab3577e40
+
+  humus/DynamicBranching3-v2.trace:
+    freedreno-a306:
+      checksum: 765fa742b87e411763921c6f988b2573
+    freedreno-a530:
+      checksum: f4aa0730942c471759d6f9b929b9122a
+    freedreno-a618:
+      checksum: 238f06550db39c36e5b880d3b3d7440f
+    zink-a618:
+      checksum: 238f06550db39c36e5b880d3b3d7440f
+
+  humus/HDR-v2.trace:
+    freedreno-a306:
+      checksum: 80b164e85e96a413568d18ce308caae3
+    freedreno-a530:
+      checksum: 22e849b9c7a91869729f4d2b73681d75
+    freedreno-a618:
+      checksum: 40387a4e89ef71c472a94413b175ff59
+    zink-a618:
+      checksum: d570eaea17c3f9bf1ad24c4af3836524
+
+  humus/Portals-v2.trace:
+    freedreno-a306:
+      label: [crash]
+      text: |-
+        ../src/freedreno/drm/freedreno_ringbuffer.h:288:
+          OUT_RELOC: Assertion `offset < fd_bo_size(bo)' failed.
+    freedreno-a530:
+      checksum: c5c7ade65a476d8e46eab878134d8a76
+    freedreno-a618:
+      label: [skip, broken, flakes]
+    zink-a618:
+      checksum: d3751c0d756fb331275c74297d69f96c
+
+  humus/RaytracedShadows-v2.trace:
+    freedreno-a306:
+      checksum: b3a848fbd6d9bc9c35a7604994867c38
+    freedreno-a530:
+      checksum: 0fb847eb10e74da0483a17e782f2a22a
+    freedreno-a618:
+      checksum: 5f1a655e62eab99d53dab88b634afed3
+    zink-a618:
+      checksum: 5f1a655e62eab99d53dab88b634afed3
+
+  humus/VolumetricFogging2-v2.trace:
+    freedreno-a306:
+      checksum: aec880cec7ba460f3144b789bc517891
+      label: [hang]
+    freedreno-a530:
+      checksum: fa6ec09d80a2c42e3ed49f87b608e0c4
+    freedreno-a618:
+      checksum: e5d2b54f49ba1c24279d5ff84e0f002b
+    zink-a618:
+      checksum: e5d2b54f49ba1c24279d5ff84e0f002b
+
+  paraview/pv-manyspheres-v2.trace:
+    freedreno-a306:
+      label: [skip]
+    freedreno-a530:
+      label: [skip]
+    freedreno-a618:
+      checksum: 5567434cd44c5deda19e7a9619e1c8fd
+    zink-a618:
+      checksum: 5567434cd44c5deda19e7a9619e1c8fd
+
+  paraview/pv-waveletcontour-v2.trace:
+    freedreno-a306:
+      label: [skip]
+    freedreno-a530:
+      label: [skip]
+    freedreno-a618:
+      checksum: 5ce2fde8189c8ef6665994fa9bed4cfc
+    zink-a618:
+      label: [no-perf]
+      checksum: 5ce2fde8189c8ef6665994fa9bed4cfc
+
+  paraview/pv-waveletvolume-v2.trace:
+    freedreno-a306:
+      label: [skip]
+    freedreno-a530:
+      label: [skip]
+    freedreno-a618:
+      checksum: dd05d3e98eb93c0e520c1359de18e9fb
+    zink-a618:
+      label: [no-perf]
+      checksum: dd05d3e98eb93c0e520c1359de18e9fb
+
+  pathfinder/canvas_moire-v2.trace:
+    freedreno-a306:
+      label: [skip]
+    freedreno-a530:
+      label: [skip]
+    freedreno-a618:
+      checksum: 0e32ca8fc815a7250f38a07faeafb21b
+    zink-a618:
+      label: [no-perf]
+      checksum: 0e32ca8fc815a7250f38a07faeafb21b
+
+  pathfinder/canvas_text-v2.trace:
+    freedreno-a306:
+      text: more suitable is canvas_text_v2-v2
+      label: [skip]
+    freedreno-a530:
+      label: [skip]
+    freedreno-a618:
+      label: [skip]
+    zink-a618:
+      label: [skip]
+
+  pathfinder/canvas_text_v2-v2.trace:
+    freedreno-a306:
+      label: [skip]
+    freedreno-a530:
+      label: [skip]
+    freedreno-a618:
+      checksum: c163253b33a93577600e2f1c0571737c
+    zink-a618:
+      checksum: c163253b33a93577600e2f1c0571737c
+
+  pathfinder/demo-v2.trace:
+    freedreno-a306:
+      label: [skip]
+    freedreno-a530:
+      label: [skip]
+    freedreno-a618:
+      checksum: f6661ed4de9e0a444c6338ebd0cd3768
+    zink-a618:
+      checksum: f6661ed4de9e0a444c6338ebd0cd3768
+
+  ror/ror-default.trace:
+    freedreno-a306:
+      label: [skip]
+    freedreno-a530:
+      label: [crash]
+    freedreno-a618:
+      label: [skip, broken]
+    zink-a618:
+      checksum: 8533a3fd4dca0c68df6721f7eab75960
+
+  nheko/nheko-colors.trace:
+    freedreno-a306:
+      label: [skip, slow]
+    freedreno-a530:
+      label: [skip, slow]
+    freedreno-a618:
+      label: [skip, broken, no-perf]
+    zink-a618:
+      label: [skip, flakes, no-perf]
+      checksum: fd1b9033e68c394a5564d8c4819a3012
+      text: >
+        Zink assertion error:
+          MESA: warning: zink: PERF WARNING! > 100 copy boxes detected for 0xffff5c924780
+          .nheko-wrapped: ../src/util/slab.c:228: slab_alloc: Assertion `(elt)->magic == (0x7ee01234)' failed.
+          apitrace: warning: caught signal 6
+          28177: error: caught an unhandled exception
+
+  blender/blender-demo-cube_diorama.trace:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+      text: needs GL 4.5
+    freedreno-a618:
+      label: [crash, no-perf]
+    zink-a618:
+      label: [crash, no-perf]
+      text: 'blender: ../src/gallium/drivers/zink/zink_context.c:3512: zink_wait_on_batch: Assertion batch_id failed.'
+
+  blender/blender-demo-ellie_pose.trace:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+      text: needs GL 4.5
+    freedreno-a618:
+      label: [skip, flakes]
+    zink-a618:
+      label: [skip, flakes]
+      text: Inconsistent rendering, but looks good.
+
+  unvanquished/unvanquished-lowest.trace:
+    freedreno-a306:
+      label: [skip]
+    freedreno-a530:
+      label: [skip]
+    freedreno-a618:
+      label: [skip, flakes]
+      text: text is prone to occasional misrendering, particularly in the lower left
+      checksum: ae37867b1a9a94d2be9ff6c7e2009813
+    zink-a618:
+      checksum: ae37867b1a9a94d2be9ff6c7e2009813
+
+  unvanquished/unvanquished-ultra.trace:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+    freedreno-a618:
+      checksum: b575c6f7e33472b56714a32449b332c4
+    zink-a618:
+      checksum: b487c2784d458dff4a12f65e5cc46ac1
+
+  warzone2100/warzone2100-default.trace:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+      text: GLSL 1.50 is needed.
+    freedreno-a618:
+      checksum: 85c2d8129d761db4d9332790f694431a
+    zink-a618:
+      checksum: 8d450896439fe8b1b333e3ff61179f1b
+
+  pioneer/pioneer.trace:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+    freedreno-a618:
+      label: [crash]
+    zink-a618:
+      label: [crash]
+
+  jvgs/jvgs-d27fb67-v2.trace:
+    freedreno-a306:
+      checksum: d44fdd0c4f5afe5ce7697b7c67dff6a0
+    freedreno-a530:
+      checksum: 8fade25941ec15172f0d2ee50ff9c5c5
+    freedreno-a618:
+      checksum: da3cf87ea3f62d67771a63f24a7eccff
+    zink-a618:
+      checksum: 502c7cb7bcb47e9ccc9ce18897ac7ae5
+
+
+  supertuxkart/supertuxkart-antediluvian-abyss.rdc:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+    freedreno-a618:
+      label: [crash]
+    zink-a618:
+      label: [fail]
+      text: OpenGL ES 3.x replay context - required for replay
+
+  supertuxkart/supertuxkart-menu.rdc:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+    freedreno-a618:
+      label: [crash]
+    zink-a618:
+      label: [fail]
+
+  supertuxkart/supertuxkart-ravenbridge-mansion.rdc:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+    freedreno-a618:
+      label: [crash]
+    zink-a618:
+      label: [fail]
+
+  godot/Material Testers.x86_64_2020.04.08_13.38_frame799.rdc:
+    freedreno-a306:
+      label: [unsupported]
+    freedreno-a530:
+      label: [unsupported]
+    freedreno-a618:
+      label: [crash]
+    zink-a618:
+      label: [unsupported]

src/freedreno/common/README.rst

@@ -0,0 +1,5 @@
+Overview
+========
+
+Common functionality shared between freedreno drivers (that are not
+registers, layout or the compiler), e.g UUID generation.

src/freedreno/common/disasm.h

@@ -0,0 +1,72 @@
+/*
+ * Copyright © 2012 Rob Clark <[email protected]>
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef DISASM_H_
+#define DISASM_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+
+#include "compiler/shader_enums.h"
+
+/* bitmask of debug flags */
+enum debug_t {
+   PRINT_RAW = 0x1, /* dump raw hexdump */
+   PRINT_VERBOSE = 0x2,
+   PRINT_STATS = 0x4,
+   EXPAND_REPEAT = 0x8,
+};
+
+/* bitmask of sampler/memobj descriptor usage per bindless/bindfull
+ * bases.  If the sampler/texture is not immediate (such as .s2en)
+ * then the corresponding bitmask is set to ~0 (ie. all used).  For
+ * simplicity, #tN immediate > 64 marks all used (~0)
+ */
+struct descriptor_stats {
+   uint64_t img;             /* img/img_bindless descriptor usage */
+   uint64_t tex;             /* non img/img_bindless cat5/cat6 descriptor usage */
+   uint64_t samp;            /* cat5 sampler usage */
+   uint64_t ubo;             /* ubo descriptor usage */
+};
+
+/* Keep in sync with domain "ir3_shader_stats" in xml */
+struct shader_stats {
+   /* desc[0] is bindfull, desc[N+1] is .baseN: */
+   struct descriptor_stats desc[9];
+   uint32_t has_img;
+   uint32_t has_tex;
+   uint32_t has_samp;
+   uint32_t has_ubo;
+   /* instructions counts rpnN, and instlen does not */
+   int instructions, instlen;
+   int nops;
+   int ss, sy;
+   int constlen;
+   int halfreg;
+   int fullreg;
+   uint16_t sstall;
+   uint16_t mov_count;
+   uint16_t cov_count;
+   uint16_t last_baryf;
+   uint16_t instrs_per_cat[8];
+};
+
+int disasm_a2xx(const uint32_t *dwords, int sizedwords, int level,
+                mesa_shader_stage type);
+int disasm_a3xx(const uint32_t *dwords, int sizedwords, int level, FILE *out,
+                unsigned gpu_id);
+int disasm_a3xx_stat(const uint32_t *dwords, int sizedwords, int level,
+                     FILE *out, unsigned gpu_id, struct shader_stats *stats);
+int try_disasm_a3xx(const uint32_t *dwords, int sizedwords, int level,
+                    FILE *out, unsigned gpu_id);
+int try_disasm_a3xx_stat(const uint32_t *dwords, int sizedwords, int level,
+                         FILE *out, unsigned gpu_id,
+                         struct shader_stats *stats);
+
+void disasm_a2xx_set_debug(enum debug_t debug);
+void disasm_a3xx_set_debug(enum debug_t debug);
+
+#endif /* DISASM_H_ */

src/freedreno/common/fd2_hw.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2026 Valve Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef FD2_HW_H
+#define FD2_HW_H
+
+#include "fd_hw_common.h"
+#include "a2xx.xml.h"
+
+#endif /* FD2_HW_H */

src/freedreno/common/fd3_hw.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2026 Valve Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef FD3_HW_H
+#define FD3_HW_H
+
+#include "fd_hw_common.h"
+#include "a3xx.xml.h"
+
+#endif /* FD3_HW_H */

src/freedreno/common/fd4_hw.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2026 Valve Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef FD4_HW_H
+#define FD4_HW_H
+
+#include "fd_hw_common.h"
+#include "a4xx.xml.h"
+
+#endif /* FD4_HW_H */

src/freedreno/common/fd5_hw.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2026 Valve Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef FD5_HW_H
+#define FD5_HW_H
+
+#include "fd_hw_common.h"
+#include "a5xx.xml.h"
+
+#endif /* FD5_HW_H */

src/freedreno/common/fd6_gmem_cache.h

@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its susidiaries.
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef FD6_GMEM_CACHE_H
+#define FD6_GMEM_CACHE_H
+
+#include <stdint.h>
+
+#include "common/freedreno_dev_info.h"
+
+/* Offset within GMEM of various "non-GMEM" things that GMEM is used to
+ * cache.  These offsets differ for gmem vs sysmem rendering (in sysmem
+ * mode, the entire GMEM can be used)
+ */
+struct fd6_gmem_config {
+   /* Color/depth CCU cache: */
+   uint32_t color_ccu_offset;
+   uint32_t depth_ccu_offset;
+
+   /* Vertex attrib cache (a750+): */
+   uint32_t vpc_attr_buf_size;
+   uint32_t vpc_attr_buf_offset;
+
+   /* Vertex position cache (a8xx+): */
+   uint32_t vpc_pos_buf_size;
+   uint32_t vpc_pos_buf_offset;
+   uint32_t vpc_bv_pos_buf_size;
+   uint32_t vpc_bv_pos_buf_offset;
+
+   /* see enum a6xx_ccu_cache_size */
+   uint32_t depth_cache_fraction;
+   uint32_t color_cache_fraction;
+   uint32_t depth_cache_size;
+   uint32_t color_cache_size;
+};
+
+static inline unsigned
+__calc_gmem_cache_offsets(const struct fd_dev_info *info, unsigned offset,
+                          struct fd6_gmem_config *config)
+{
+   unsigned num_ccu = info->num_ccu;
+
+   config->vpc_bv_pos_buf_offset = offset - (num_ccu * config->vpc_bv_pos_buf_size);
+   offset = config->vpc_bv_pos_buf_offset;
+
+   config->vpc_attr_buf_offset = offset - (num_ccu * config->vpc_attr_buf_size);
+   offset = config->vpc_attr_buf_offset;
+
+   config->vpc_pos_buf_offset = offset - (num_ccu * config->vpc_pos_buf_size);
+   offset = config->vpc_pos_buf_offset;
+
+   config->color_ccu_offset = offset - (num_ccu * config->color_cache_size);
+   offset = config->color_ccu_offset;
+
+   config->depth_ccu_offset = offset - (num_ccu * config->depth_cache_size);
+   offset = config->depth_ccu_offset;
+
+   return offset;
+}
+
+static inline unsigned
+fd6_calc_gmem_cache_offsets(const struct fd_dev_info *info, unsigned gmemsize_bytes,
+                            struct fd6_gmem_config *gmem, struct fd6_gmem_config *sysmem)
+{
+   uint32_t depth_cache_size =
+      info->num_ccu * info->props.sysmem_per_ccu_depth_cache_size;
+   uint32_t color_cache_size =
+      (info->num_ccu * info->props.sysmem_per_ccu_color_cache_size);
+   uint32_t color_cache_size_gmem =
+      color_cache_size /
+      (1 << info->props.gmem_ccu_color_cache_fraction);
+
+   sysmem->depth_ccu_offset = 0;
+   sysmem->color_ccu_offset = sysmem->depth_ccu_offset + depth_cache_size;
+
+   /* TODO we could unify gen7/gen8 setup.. gen7 is a subset.. */
+   if (info->chip == 8) {
+      gmem->depth_cache_fraction = info->props.gmem_ccu_depth_cache_fraction;
+      gmem->depth_cache_size     = info->props.gmem_per_ccu_depth_cache_size;
+      gmem->color_cache_fraction = info->props.gmem_ccu_color_cache_fraction;
+      gmem->color_cache_size     = info->props.gmem_per_ccu_color_cache_size;
+      gmem->vpc_attr_buf_size    = info->props.gmem_vpc_attr_buf_size;
+      gmem->vpc_pos_buf_size     = info->props.gmem_vpc_pos_buf_size;
+      gmem->vpc_bv_pos_buf_size  = info->props.gmem_vpc_bv_pos_buf_size;
+
+      sysmem->depth_cache_fraction = info->props.sysmem_ccu_depth_cache_fraction;
+      sysmem->depth_cache_size     = info->props.sysmem_per_ccu_depth_cache_size;
+      sysmem->color_cache_fraction = info->props.sysmem_ccu_color_cache_fraction;
+      sysmem->color_cache_size     = info->props.sysmem_per_ccu_color_cache_size;
+      sysmem->vpc_attr_buf_size    = info->props.sysmem_vpc_attr_buf_size;
+      sysmem->vpc_pos_buf_size     = info->props.sysmem_vpc_pos_buf_size;
+      sysmem->vpc_bv_pos_buf_size  = info->props.sysmem_vpc_bv_pos_buf_size;
+
+      __calc_gmem_cache_offsets(info, gmemsize_bytes, sysmem);
+      return __calc_gmem_cache_offsets(info, gmemsize_bytes, gmem);
+   } else if (info->props.has_gmem_vpc_attr_buf) {
+      sysmem->vpc_attr_buf_size = info->props.sysmem_vpc_attr_buf_size;
+      sysmem->vpc_attr_buf_offset = sysmem->color_ccu_offset + color_cache_size;
+
+      gmem->vpc_attr_buf_size = info->props.gmem_vpc_attr_buf_size;
+      gmem->vpc_attr_buf_offset = gmemsize_bytes -
+         (gmem->vpc_attr_buf_size * info->num_ccu);
+
+      gmem->color_ccu_offset = gmem->vpc_attr_buf_offset - color_cache_size_gmem;
+
+      return gmem->vpc_attr_buf_offset;
+   } else {
+      gmem->depth_ccu_offset = 0;
+      gmem->color_ccu_offset = gmemsize_bytes - color_cache_size_gmem;
+
+      return gmemsize_bytes;
+   }
+}
+
+#endif /* FD6_GMEM_CACHE_H */

src/freedreno/common/fd6_hw.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its susidiaries.
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef FD6_HW_H
+#define FD6_HW_H
+
+#include "fd_hw_common.h"
+
+#include "a6xx_enums.xml.h"
+#include "a7xx_enums.xml.h"
+#include "a8xx_enums.xml.h"
+#include "a6xx_perfcntrs.xml.h"
+#include "a7xx_perfcntrs.xml.h"
+#include "a8xx_perfcntrs.xml.h"
+#include "a6xx_descriptors.xml.h"
+#include "a8xx_descriptors.xml.h"
+#include "a6xx.xml.h"
+
+#endif /* FD6_HW_H */

src/freedreno/common/fd6_pack.h

@@ -0,0 +1,572 @@
+/*
+ * Copyright © 2019 Google, Inc.
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef FD6_PACK_H
+#define FD6_PACK_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "fd6_hw.h"
+
+struct fd_reg_pair {
+   uint32_t reg;
+   uint64_t value;
+   struct fd_bo *bo;
+   bool is_address;
+   uint32_t bo_offset;
+   uint32_t bo_shift;
+   uint32_t bo_low;
+};
+
+#define __bo_type struct fd_bo *
+
+#include "a6xx-pack.xml.h"
+#include "adreno-pm4-pack.xml.h"
+
+#ifdef NDEBUG
+#  define __assert_eq(a, b) do { (void)(a); (void)(b); } while (0)
+#else
+#  define __assert_eq(a, b)                                                    \
+   do {                                                                        \
+      if ((a) != (b)) {                                                        \
+         fprintf(stderr, "assert failed: " #a " (0x%x) != " #b " (0x%x)\n", a, \
+                 b);                                                           \
+         assert((a) == (b));                                                   \
+      }                                                                        \
+   } while (0)
+#endif
+
+#if !FD_BO_NO_HARDPIN
+#  error 'Hardpin unsupported'
+#endif
+
+static inline uint64_t
+__reg_iova(const struct fd_reg_pair *reg)
+{
+   uint64_t iova = __reloc_iova((struct fd_bo *)reg->bo,
+                                reg->bo_offset, 0,
+                                -reg->bo_shift);
+   return iova << reg->bo_low;
+}
+
+/* Special helper for building UBO descriptors inline with pkt7 */
+#define A6XX_UBO_DESC(_i, _bo, _bo_offset, _size_vec4s) {       \
+      .reg = 3 + (2 * _i),                                      \
+      .value = (uint64_t)A6XX_UBO_1_SIZE(_size_vec4s) << 32,    \
+      .bo = _bo, .bo_offset = _bo_offset,                       \
+   }, {}
+
+/**
+ * Helper for various builders that use fd_ringbuffer.  Not for direct use.
+ */
+class fd_ringbuffer_builder {
+protected:
+   fd_ringbuffer_builder(struct fd_ringbuffer *ring) {
+      ring_ = ring;
+   }
+
+   uint64_t reg_iova(struct fd_reg_pair reg_lo) {
+      if (reg_lo.bo) {
+         fd_ringbuffer_assert_attached(ring_, reg_lo.bo);
+         return __reg_iova(&reg_lo) | reg_lo.value;
+      } else {
+         return reg_lo.value;
+      }
+   }
+
+   struct fd_ringbuffer *ring_;
+
+public:
+   void attach_bo(struct fd_bo *bo) {
+      fd_ringbuffer_attach_bo(ring_, bo);
+   }
+
+   friend class fd_cs;
+   friend class fd_pkt;
+   friend class fd_pkt4;
+   friend class fd_pkt7;
+   template <chip CHIP, typename Enable> friend class fd_ncrb;
+};
+
+class fd_pkt;
+
+/**
+ * A general command stream builder, which can mix CRB's for register writes
+ * (via fd_crb) and other pkt7 packets.
+ */
+class fd_cs : public fd_ringbuffer_builder {
+public:
+   fd_cs(struct fd_ringbuffer *ring) : fd_ringbuffer_builder(ring) {
+   }
+
+   /* Constructor for streaming state tied to the submit: */
+   fd_cs(struct fd_submit *submit, unsigned ndwords) :
+      fd_ringbuffer_builder(fd_submit_new_ringbuffer(submit, ndwords, FD_RINGBUFFER_STREAMING))
+   {}
+
+   /* Constructor for long lived state objects: */
+   fd_cs(struct fd_pipe *pipe, unsigned ndwords) :
+      fd_ringbuffer_builder(fd_ringbuffer_new_object(pipe, ndwords))
+   {}
+
+   /* If this assert fails, the currently built packet has not gone out of
+    * scope and hasn't been finalized.  This is not allowed when passing
+    * thing underling ring buffer back to legacy cmdstream builders, or
+    * when starting a new pm4 packet.
+    *
+    * In cases where you need to delineate scope, the with_xyz() macros
+    * can be used, for example:
+    *
+    *   with_crb (cs, 7) {
+    *      set_window_offset<CHIP>(crb, x1, y1);
+    *
+    *      set_bin_size<CHIP>(crb, gmem, {
+    *            .render_mode = RENDERING_PASS,
+    *            .force_lrz_write_dis = !screen->info->props.has_lrz_feedback,
+    *            .buffers_location = BUFFERS_IN_GMEM,
+    *            .lrz_feedback_zmode_mask = screen->info->props.has_lrz_feedback
+    *                                          ? LRZ_FEEDBACK_EARLY_Z_LATE_Z
+    *                                          : LRZ_FEEDBACK_NONE,
+    *      });
+    *   }
+    *
+    *   fd_pkt7(cs, CP_SET_MODE, 1)
+    *      .add(0x0);
+    *
+    */
+   void check_flush(void) {
+      assert(!pkt_);
+   }
+
+   /* bridge back to the legacy world: */
+   operator struct fd_ringbuffer *() {
+      check_flush();
+      return ring_;
+   }
+
+   friend class fd_crb;
+   friend class fd_pkt;
+
+private:
+   /* Disallow copy constructor to prevent mistakes with using fd_cs instead
+    * of fd_cs& as function param:
+    */
+   fd_cs(const fd_cs &);
+
+   /* Non-NULL if currently building a pkt, which needs flushing: */
+   fd_pkt *pkt_ = NULL;
+};
+
+/**
+ * A builder for pkt4 packets.
+ *
+ * It would be nice to re-use fd_pkt base class for this, but the extra
+ * conditionals in flush() make the generated code worse.  So this is
+ * more limited, and only intended to be used like:
+ *
+ *    fd_pkt4(cs, 3)
+ *       .add(REG1)
+ *       .add(REG2)
+ *       .add(REG3);
+ *
+ * Where possible (ie. 3d context regs) prefer fd_crb instead.
+ */
+class fd_pkt4 : public fd_ringbuffer_builder {
+public:
+   fd_pkt4(fd_cs &cs, unsigned nregs) : fd_ringbuffer_builder(cs) {
+      init(nregs);
+   }
+
+   ~fd_pkt4() {
+      flush();
+   }
+
+   /* Append a <reg32> to PKT4: */
+   fd_pkt4& add(struct fd_reg_pair reg) {
+      if (reg_)
+         __assert_eq(reg.reg, reg_ + 1);
+      reg_ = reg.reg;
+      append(reg.value);
+      return *this;
+   }
+
+   /* Append a <reg64> to PKT4: */
+   fd_pkt4& add(struct fd_reg_pair reg_lo, struct fd_reg_pair reg_hi) {
+      __assert_eq(reg_hi.reg, 0);
+      if (reg_)
+         __assert_eq(reg_lo.reg, reg_ + 1);
+      reg_ = reg_lo.reg + 1;
+      uint64_t val = reg_iova(reg_lo);
+      append(val);
+      append(val >> 32);
+      return *this;
+   }
+
+protected:
+   fd_pkt4(struct fd_ringbuffer *ring) : fd_ringbuffer_builder(ring) {}
+
+   void reinit(void) {
+      struct fd_ringbuffer *ring = ring_;
+      cur_ = ring->cur + 1;
+      start_ = ring->cur;
+      reg_ = 0;
+   }
+
+   void init(unsigned nregs) {
+      struct fd_ringbuffer *ring = ring_;
+      BEGIN_RING(ring, 1 + nregs);
+      reinit();
+      ndwords_ = nregs;
+   }
+
+   void flush() {
+      uint32_t *cur = cur_;
+
+      /* Catch any use-after-flush: */
+      cur_ = NULL;
+
+      unsigned cnt = cur - ring_->cur - 1;
+
+      assert(cnt > 0);
+
+      /* Check for under-estimate of dwords emitted: */
+      assert(cnt <= ndwords_);
+      (void)ndwords_;
+
+      /* Check for any other direct use of ringbuffer while building the CRB: */
+      assert(ring_->cur == start_);
+      (void)start_;
+
+      *ring_->cur = pm4_pkt4_hdr(reg_ - cnt + 1, cnt);
+      ring_->cur = cur;
+   }
+
+   void append(uint32_t dword) {
+      *(cur_++) = dword;
+   }
+
+   uint32_t reg_ = 0;
+
+private:
+   uint32_t *cur_ = NULL, *start_ = NULL;
+   uint32_t ndwords_ = 0;
+};
+
+/**
+ * Helper base class for any pkt building.
+ */
+class fd_pkt : public fd_ringbuffer_builder {
+protected:
+   /* Initializer to use with fd_cs: */
+   void init(fd_cs &cs, enum adreno_pm4_type3_packets pkt, unsigned ndwords) {
+      cs.check_flush();
+      BEGIN_RING(cs.ring_, ndwords + 1);
+      init(pkt, ndwords);
+      assert(!cs.pkt_);
+      cs_ = &cs;
+#if !defined(__clang__)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpragmas"
+#pragma GCC diagnostic ignored "-Wdangling-pointer="
+#endif
+      /* Safe because destructor calls flush() which clears the potentially
+       * dangling pointer:
+       */
+      cs.pkt_ = this;
+#if !defined(__clang__)
+#pragma GCC diagnostic pop
+#endif
+   }
+
+   ~fd_pkt() {
+      flush();
+   }
+
+   /* Initializer to use directly with ring (for fd_crb stateobjs): */
+   void init(enum adreno_pm4_type3_packets pkt, unsigned ndwords) {
+      cur_ = ring_->cur + 1;
+      start_ = ring_->cur;
+      pkt_ = pkt;
+      ndwords_ = ndwords;
+   }
+
+   void append(uint32_t dword) {
+      *(cur_++) = dword;
+   }
+
+   void append(const uint32_t *dwords, uint32_t sizedwords) {
+      memcpy(cur_, dwords, 4 * sizedwords);
+      cur_ += sizedwords;
+   }
+
+   fd_pkt(struct fd_ringbuffer *ring) : fd_ringbuffer_builder(ring) {};
+
+   enum adreno_pm4_type3_packets pkt_;
+
+public:
+   /* Bridge to the legacy world, ideally we can remove this eventually: */
+   operator struct fd_ringbuffer *() {
+      return ring_;
+   }
+
+   void flush() {
+      bool allow_empty = (pkt_ != CP_CONTEXT_REG_BUNCH);
+      uint32_t *cur = cur_;
+
+      assert(cur);
+
+      if (cs_) {
+         assert(cs_->pkt_ == this);
+         cs_->pkt_ = NULL;
+      }
+
+      /* Catch any use-after-flush: */
+      cur_ = NULL;
+
+      unsigned cnt = cur - ring_->cur - 1;
+
+      /* Check for under-estimate of dwords emitted: */
+      assert(cnt <= ndwords_);
+      (void)ndwords_;
+
+      /* Check for any other direct use of ringbuffer while building the CRB: */
+      assert(ring_->cur == start_);
+      (void)start_;
+
+      if (!allow_empty && !cnt)
+         return;
+
+      *ring_->cur = pm4_pkt7_hdr(pkt_, cnt);
+      ring_->cur = cur;
+   }
+
+private:
+   uint32_t *cur_ = NULL, *start_ = NULL;
+   uint32_t ndwords_ = 0;
+   fd_cs *cs_ = NULL;
+};
+
+/**
+ * A builder for CP_CONTEXT_REG_BUNCH.  This packet can write an
+ * arbitrary sequence of registers (payload consists of pairs of
+ * offset,value).  It should be as fast as a pkt4 packet writing
+ * a consecutive sequence of registers, without the constraint of
+ * the registers being sequential, making it easier to use when
+ * cmdstream emit involves if/else/loops.  And should be less
+ * brittle if registers shift around between generations.  This
+ * builder intentionally encourages use of fd_reg_pair.
+ */
+class fd_crb : public fd_pkt {
+public:
+   /* Constructor for streaming state tied to the submit: */
+   fd_crb(struct fd_submit *submit, unsigned nregs) :
+      fd_pkt(fd_submit_new_ringbuffer(submit, cs_size(nregs), FD_RINGBUFFER_STREAMING))
+   {
+      init(CP_CONTEXT_REG_BUNCH, nregs * 2);
+   }
+
+   /* Constructor for long lived state objects: */
+   fd_crb(struct fd_pipe *pipe, unsigned nregs) :
+      fd_pkt(fd_ringbuffer_new_object(pipe, cs_size(nregs)))
+   {
+      init(CP_CONTEXT_REG_BUNCH, nregs * 2);
+   }
+
+   /* Constructor to use with fd_cs: */
+   fd_crb(fd_cs &cs, unsigned nregs) : fd_pkt(cs.ring_) {
+      init(cs, CP_CONTEXT_REG_BUNCH, nregs * 2);
+   }
+
+   /* Append a <reg32> to CRB: */
+   fd_crb& add(struct fd_reg_pair reg) {
+      append(reg.reg);
+      append(reg.value);
+      return *this;
+   }
+
+   /* Append a <reg64> to CRB: */
+   fd_crb& add(struct fd_reg_pair reg_lo, struct fd_reg_pair reg_hi) {
+      __assert_eq(reg_hi.reg, 0);
+      uint64_t val = reg_iova(reg_lo);
+      append(reg_lo.reg);
+      append(val);
+      append(reg_lo.reg + 1);
+      append(val >> 32);
+      return *this;
+   }
+
+   bool first = true;
+
+protected:
+   fd_crb(struct fd_ringbuffer *ring) : fd_pkt(ring) {}
+
+private:
+   /* Disallow copy constructor to prevent mistakes with using fd_crb instead
+    * of fd_crb& as function param:
+    */
+   fd_crb(const fd_crb &);
+
+   static unsigned cs_size(unsigned nregs) {
+      /* 1 dword hdr plus 2 dword per reg (offset, value pairs) */
+      return 4 * (1 + (nregs * 2));
+   }
+};
+
+#define with_crb(...) \
+   for (fd_crb crb(__VA_ARGS__); crb.first; crb.first = false)
+
+/**
+ * A builder for writing non-context regs, which is implemented differently
+ * depending on generation (A6XX doesn't have CP_NON_CONTEXT_REG_BUNCH)
+ */
+template <chip_range_support>
+class fd_ncrb {
+public:
+   fd_ncrb(fd_cs &cs, unsigned nregs);
+
+   /* Append a <reg32> to NCRB: */
+   fd_ncrb& add(struct fd_reg_pair reg);
+
+   /* Append a <reg64> to NCRB: */
+   fd_ncrb& add(struct fd_reg_pair reg_lo, struct fd_reg_pair reg_hi);
+};
+
+#define with_ncrb(cs, nregs) \
+   for (fd_ncrb<CHIP> ncrb(cs, nregs); ncrb.first; ncrb.first = false)
+
+/**
+ * A6XX does not have CP_NON_CONTEXT_REG_BUNCH, so the builder is implemented
+ * as a sequence of pkt4's
+ */
+template <chip CHIP>
+class fd_ncrb<chip_range(CHIP == A6XX)> : fd_pkt4 {
+public:
+   fd_ncrb(fd_cs &cs, unsigned nregs) : fd_pkt4(cs.ring_) {
+      /* worst case, one pkt4 per reg: */
+      init(nregs * 2);
+   }
+
+   /* Append a <reg32>: */
+   fd_ncrb& add(struct fd_reg_pair reg) {
+      check_restart(reg);
+      fd_pkt4::add(reg);
+      return *this;
+   }
+
+   /* Append a <reg64>: */
+   fd_ncrb& add(struct fd_reg_pair reg_lo, struct fd_reg_pair reg_hi) {
+      check_restart(reg_lo);
+      fd_pkt4::add(reg_lo, reg_hi);
+      return *this;
+   }
+
+   bool first = true;
+
+private:
+   void check_restart(struct fd_reg_pair reg) {
+      if (reg_ && (reg.reg != reg_ + 1)) {
+         /* Start a new pkt4: */
+         flush();
+         reinit();
+      }
+   }
+};
+
+/**
+ * Builder to write non-context regs for A7XX+, which uses CP_NON_CONTEXT_REG_BUNCH
+ */
+template <chip CHIP>
+class fd_ncrb<chip_range(CHIP >= A7XX)> : fd_crb {
+public:
+   fd_ncrb(fd_cs &cs, unsigned nregs) : fd_crb(cs.ring_) {
+      init(cs, CP_NON_CONTEXT_REG_BUNCH, 2 + (nregs * 2));
+      append(1);
+      append(0);
+   }
+
+   /* Append a <reg32>: */
+   fd_ncrb& add(struct fd_reg_pair reg) {
+      fd_crb::add(reg);
+      return *this;
+   }
+
+   /* Append a <reg64>: */
+   fd_ncrb& add(struct fd_reg_pair reg_lo, struct fd_reg_pair reg_hi) {
+      fd_crb::add(reg_lo, reg_hi);
+      return *this;
+   }
+
+   bool first = true;
+};
+
+/**
+ * A builder for an arbitrary PKT7 (for CRB, use fd_crb instead)
+ */
+class fd_pkt7 final : public fd_pkt {
+public:
+   fd_pkt7(fd_cs &cs, enum adreno_pm4_type3_packets pkt, unsigned ndwords) :
+      fd_pkt(cs.ring_)
+   {
+      init(cs, pkt, ndwords);
+   }
+
+   /* Allow appending a "naked" dwords: */
+   fd_pkt7& add(uint32_t val) {
+      append(val);
+      off_++;
+      return *this;
+   }
+
+   /* Append a <reg32> to CRB: */
+   fd_pkt7& add(struct fd_reg_pair reg) {
+      __assert_eq(off_, reg.reg);
+      off_ = reg.reg + 1;
+      append(reg.value);
+      return *this;
+   }
+
+   /* Append a <reg64> to CRB: */
+   fd_pkt7& add(struct fd_reg_pair reg_lo, struct fd_reg_pair reg_hi) {
+      __assert_eq(reg_hi.reg, 0);
+      __assert_eq(off_, reg_lo.reg);
+      off_ = reg_lo.reg + 2;
+      uint64_t val = reg_iova(reg_lo);
+      append(val);
+      append(val >> 32);
+      return *this;
+   }
+
+   fd_pkt7& add(const uint32_t *dwords, uint32_t sizedwords) {
+      append(dwords, sizedwords);
+      return *this;
+   }
+
+   fd_pkt7& add(struct fd_ringbuffer *target, uint32_t cmd_idx, uint32_t *dwords) {
+      uint64_t iova;
+      uint32_t size;
+
+      size = fd_ringbuffer_attach_ring(ring_, target, cmd_idx, &iova);
+      append(iova);
+      append(iova >> 32);
+      off_ += 2;
+
+      if (dwords)
+         *dwords = size / 4;
+
+      return *this;
+   }
+
+private:
+   /* Disallow copy constructor to prevent mistakes with using fd_pkt7 instead
+    * of fd_pkt7& as function param:
+    */
+   fd_pkt7(const fd_pkt7 &);
+
+   /* for debugging: */
+   unsigned off_ = 0;
+};
+
+#endif /* FD6_PACK_H */

src/freedreno/common/fd_hw_common.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2026 Valve Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef FD_HW_COMMON_H
+#define FD_HW_COMMON_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "util/half_float.h"
+#include "util/u_math.h"
+
+#include "adreno_pm4.xml.h"
+#include "adreno_common.xml.h"
+
+#endif /* FD_HW_COMMON_H */

src/freedreno/common/freedreno_common.h

@@ -0,0 +1,191 @@
+/*
+ * Copyright © 2022 Google, Inc.
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef FREEDRENO_COMMON_H_
+#define FREEDRENO_COMMON_H_
+
+#include "util/u_atomic.h"
+#include "util/macros.h"
+
+#ifdef __cplusplus
+
+#include <tuple>
+
+#define __FD_GPU_GENS A6XX, A7XX, A8XX
+
+#define FD_GENX(FUNC_NAME)                                                   \
+   template <chip... CHIPs> constexpr auto FUNC_NAME##instantiate()          \
+   {                                                                         \
+      return std::tuple_cat(std::make_tuple(FUNC_NAME<CHIPs>)...);           \
+   }                                                                         \
+   static constexpr auto FUNC_NAME##tmpl __attribute__((used)) =             \
+      FUNC_NAME##instantiate<__FD_GPU_GENS>();
+
+#define FD_GENX2(FUNC_NAME, EXT_TYPE, EXT)                                   \
+   template <chip... CHIPs> constexpr auto FUNC_NAME##inst##EXT()            \
+   {                                                                         \
+      return std::tuple_cat(std::make_tuple(FUNC_NAME<EXT, CHIPs>)...);      \
+   }                                                                         \
+   static constexpr auto FUNC_NAME##tmpl##EXT __attribute__((used)) =        \
+      FUNC_NAME##inst##EXT<__FD_GPU_GENS>();
+
+#define FD_CALLX(info, thing)                                                \
+   ({                                                                        \
+      decltype(&thing<A6XX>) genX_thing;                                     \
+      switch (info->chip) {                                                  \
+      case 6:                                                                \
+         genX_thing = &thing<A6XX>;                                          \
+         break;                                                              \
+      case 7:                                                                \
+         genX_thing = &thing<A7XX>;                                          \
+         break;                                                              \
+      case 8:                                                                \
+         genX_thing = &thing<A8XX>;                                          \
+         break;                                                              \
+      default:                                                               \
+         UNREACHABLE("Unknown hardware generation");                         \
+      }                                                                      \
+      genX_thing;                                                            \
+   })
+
+/* Helpers to deal with things that support ranges of chipsets: */
+#define chip_range_support chip CHIP, typename Enable = void
+#define chip_range(range) CHIP, typename std::enable_if<(range)>::type
+
+template<typename E>
+struct BitmaskEnum {
+   E value;
+
+   using underlying = typename std::underlying_type_t<E>;
+
+#define FOREACH_TYPE(M, ...) \
+   M(E,          ##__VA_ARGS__) \
+   M(bool,       ##__VA_ARGS__) \
+   M(uint8_t,    ##__VA_ARGS__) \
+   M(int8_t,     ##__VA_ARGS__) \
+   M(uint16_t,   ##__VA_ARGS__) \
+   M(int16_t,    ##__VA_ARGS__) \
+   M(uint32_t,   ##__VA_ARGS__) \
+   M(int32_t,    ##__VA_ARGS__)
+
+#define CONSTRUCTOR(T) BitmaskEnum(T value) :  value(static_cast<E>(value)) {}
+   FOREACH_TYPE(CONSTRUCTOR)
+#undef CONSTRUCTOR
+
+#define CAST(T) inline operator T() const { return static_cast<T>(value); }
+   FOREACH_TYPE(CAST)
+#undef CAST
+
+#define BOP(T, OP)                          \
+   inline E operator OP(T rhs) const {      \
+      return static_cast<E> (               \
+         static_cast<underlying>(value) OP  \
+         static_cast<underlying>(rhs)       \
+      );                                    \
+   }
+   FOREACH_TYPE(BOP, |)
+   FOREACH_TYPE(BOP, &)
+#undef BOP
+
+#define BOP(OP)                                                    \
+   inline BitmaskEnum<E> operator OP(BitmaskEnum<E> rhs) const {   \
+      return static_cast<E> (                                      \
+         static_cast<underlying>(value) OP                         \
+         static_cast<underlying>(rhs.value)                        \
+      );                                                           \
+   }
+   BOP(|)
+   BOP(&)
+#undef BOP
+
+#if defined(__GNUC__) && !defined(__clang)
+/*
+ * Silence:
+ *
+ *   ../src/freedreno/common/freedreno_common.h: In instantiation of 'E& BitmaskEnum<E>::operator|=(BitmaskEnum<E>::underlying) [with E = fd_dirty_3d_state; BitmaskEnum<E>::underlying = unsigned int]':
+ *   ../src/gallium/drivers/freedreno/freedreno_context.h:620:16:   required from here
+ *   ../src/freedreno/common/freedreno_common.h:68:39: error: dereferencing type-punned pointer will break strict-aliasing rules [-Werror=strict-aliasing]
+ *      68 |         reinterpret_cast<underlying&>(value) OP static_cast<underlying>(rhs) ); \
+ *         |                                       ^~~~~
+ *
+ * I cannot reproduce on gcc 12.2.1 or with clang 14.0.5 so I'm going to assume
+ * this is a bug with gcc 10.x
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-aliasing"
+#endif
+
+#define UOP(T, OP)                          \
+   inline E& operator OP(T rhs) {           \
+      return reinterpret_cast<E&>(          \
+        reinterpret_cast<underlying&>(value) OP static_cast<underlying>(rhs) ); \
+   }
+   UOP(underlying, |=)
+   UOP(underlying, &=)
+#undef UOP
+
+#if defined(__GNUC__) && !defined(__clang) && (__GNUC__ < 7)
+#pragma GCC diagnostic pop
+#endif
+
+   inline E operator ~() const {
+      static_assert(sizeof(E) == sizeof(BitmaskEnum<E>));
+      return static_cast<E> (
+            ~static_cast<underlying>(value)
+      );
+   }
+#undef FOREACH_TYPE
+};
+#define BITMASK_ENUM(E) BitmaskEnum<E>
+#else
+#define BITMASK_ENUM(E) enum E
+#endif
+
+#ifdef __cplusplus
+#  define EXTERNC extern "C"
+#  define BEGINC EXTERNC {
+#  define ENDC }
+#else
+#  define EXTERNC
+#  define BEGINC
+#  define ENDC
+#endif
+
+/* for conditionally setting boolean flag(s): */
+#define COND(bool, val) ((bool) ? (val) : 0)
+
+#define BIT(bit) BITFIELD64_BIT(bit)
+
+#define U642VOID(x) ((void *)(unsigned long)(x))
+#define VOID2U64(x) ((uint64_t)(unsigned long)(x))
+
+/**
+ * Helper for allocating sequence #s where zero is a non-valid seqno
+ */
+typedef struct {
+   uint32_t counter;
+} seqno_t;
+
+static inline uint32_t
+seqno_next(seqno_t *seq)
+{
+   uint32_t n;
+   do {
+      n = p_atomic_inc_return(&seq->counter);
+   } while (n == 0);
+   return n;
+}
+
+static inline uint16_t
+seqno_next_u16(seqno_t *seq)
+{
+   uint16_t n;
+   do {
+      n = p_atomic_inc_return(&seq->counter);
+   } while (n == 0);
+   return n;
+}
+
+#endif /* FREEDRENO_COMMON_H_ */

src/freedreno/common/freedreno_dev_info.c

@@ -0,0 +1,112 @@
+/*
+ * Copyright © 2020 Valve Corporation
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#include "freedreno_dev_info.h"
+#include "util/macros.h"
+
+/**
+ * Table entry for a single GPU version
+ */
+struct fd_dev_rec {
+   struct fd_dev_id id;
+   const char *name;
+   const struct fd_dev_info *info;
+};
+
+#include "freedreno_devices.h"
+
+/**
+ * Compare device 'id' against reference id ('ref') from gpu table.
+ */
+static bool
+dev_id_compare(const struct fd_dev_id *ref, const struct fd_dev_id *id)
+{
+   if (ref->gpu_id && id->gpu_id) {
+      return ref->gpu_id == id->gpu_id;
+   } else {
+      if (!id->chip_id)
+         return false;
+
+      /* Match on either:
+       * (a) exact match:
+       */
+      if (ref->chip_id == id->chip_id)
+         return true;
+      /* (b) device table entry has 0xff wildcard patch_id and core/
+       *     major/minor match:
+       */
+      if (((ref->chip_id & 0xff) == 0xff) &&
+            ((ref->chip_id & UINT64_C(0xffffff00)) ==
+             (id->chip_id & UINT64_C(0xffffff00))))
+         return true;
+#define WILDCARD_FUSE_ID UINT64_C(0x0000ffff00000000)
+      /* If the reference id has wildcard fuse-id value (ie. bits 47..32
+       * are all ones, then try matching ignoring the device fuse-id:
+       */
+      if ((ref->chip_id & WILDCARD_FUSE_ID) == WILDCARD_FUSE_ID) {
+         uint64_t chip_id = id->chip_id | WILDCARD_FUSE_ID;
+         /* (c) exact match (ignoring the fuse-id from kernel):
+          */
+         if (ref->chip_id == chip_id)
+            return true;
+         /* (d) device table entry has 0xff wildcard patch_id and core/
+          *     major/minor match (ignoring fuse-id from kernel):
+          */
+         if (((ref->chip_id & 0xff) == 0xff) &&
+               ((ref->chip_id & UINT64_C(0xffffff00)) ==
+                (chip_id & UINT64_C(0xffffff00))))
+            return true;
+      }
+      return false;
+   }
+}
+
+const struct fd_dev_info *
+fd_dev_info_raw(const struct fd_dev_id *id)
+{
+   for (int i = 0; i < ARRAY_SIZE(fd_dev_recs); i++) {
+      if (dev_id_compare(&fd_dev_recs[i].id, id)) {
+         return fd_dev_recs[i].info;
+      }
+   }
+   return NULL;
+}
+
+struct fd_dev_info
+fd_dev_info(const struct fd_dev_id *id)
+{
+   struct fd_dev_info modified = {};
+   const struct fd_dev_info *orig = fd_dev_info_raw(id);
+   if (orig) {
+      modified = *orig;
+      fd_dev_info_apply_dbg_options(&modified);
+   }
+
+   return modified;
+}
+
+const struct fd_dev_info *
+fd_dev_info_raw_by_name(const char *name)
+{
+   for (int i = 0; i < ARRAY_SIZE(fd_dev_recs); i++) {
+      if (!strcmp(fd_dev_recs[i].name, name)) {
+         return fd_dev_recs[i].info;
+      }
+   }
+
+   return NULL;
+}
+
+const char *
+fd_dev_name(const struct fd_dev_id *id)
+{
+   for (int i = 0; i < ARRAY_SIZE(fd_dev_recs); i++) {
+      if (dev_id_compare(&fd_dev_recs[i].id, id)) {
+         return fd_dev_recs[i].name;
+      }
+   }
+   return NULL;
+}

src/freedreno/common/freedreno_dev_info.h

@@ -0,0 +1,557 @@
+/*
+ * Copyright © 2020 Valve Corporation
+ * SPDX-License-Identifier: MIT
+ *
+ */
+
+#ifndef FREEDRENO_DEVICE_INFO_H
+#define FREEDRENO_DEVICE_INFO_H
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Freedreno hardware description and quirks
+ */
+
+struct fd_dev_info {
+   uint8_t chip;
+
+   /* alignment for size of tiles */
+   uint32_t tile_align_w, tile_align_h;
+   /* gmem load/store granularity */
+   uint32_t gmem_align_w, gmem_align_h;
+   /* max tile size */
+   uint32_t tile_max_w, tile_max_h;
+
+   uint32_t num_vsc_pipes;
+
+   /* The size of local memory in bytes */
+   uint32_t cs_shared_mem_size;
+
+   /* On at least a6xx, waves are always launched in pairs. In calculations
+    * about occupancy, we pretend that each wave pair is actually one wave,
+    * which simplifies many of the calculations, but means we have to
+    * multiply threadsize_base by this number.
+    */
+   int wave_granularity;
+
+   /* These are fallback values that should match what drm/msm programs, for
+    * kernels that don't support returning them. Newer devices should not set
+    * them and just use the value from the kernel.
+    */
+   uint32_t highest_bank_bit;
+   uint32_t ubwc_swizzle;
+   uint32_t macrotile_mode;
+
+   /* Information for private memory calculations */
+   uint32_t fibers_per_sp;
+
+   /* The base number of threads per wave. Some stages may be able to double
+    * this.
+    */
+   uint32_t threadsize_base;
+
+   /* The maximum number of simultaneous waves per core. */
+   uint32_t max_waves;
+
+   /* Local Memory (i.e. shared memory in GL/Vulkan) and compute shader
+    * const registers, as well as other things not relevant here, share the
+    * same storage space, called the Local Buffer or LB. This is the size of
+    * the part of the LB used for consts and LM. Consts are duplicated
+    * wavesize_granularity times, and the size of duplicated consts + local
+    * memory must not exceed it. If it is left 0, assume that it is
+    * compute constlen + wavesize_granularity * cs_shared_mem_size, which is
+    * enough to hold both the maximum possible compute consts and local
+    * memory at the same time.
+    */
+   uint32_t compute_lb_size;
+
+   /* number of CCU is always equal to the number of SP */
+   union {
+      uint32_t num_sp_cores;
+      uint32_t num_ccu;
+   };
+
+   uint32_t num_slices;    /* gen8+ */
+
+   struct {
+      uint32_t RB_DBG_ECO_CNTL;
+      uint32_t RB_DBG_ECO_CNTL_blit;
+      uint32_t RB_RBP_CNTL;
+   } magic;
+
+   struct {
+         uint32_t reg;
+         uint32_t value;
+   } magic_raw[64];
+
+   struct {
+      /*
+       * A6XX / gen6
+       */
+      uint32_t reg_size_vec4;
+
+      /* The size (in instrlen units (128 bytes)) of instruction cache where
+       * we preload a shader. Loading more than this could trigger a hang
+       * on gen3 and later.
+       */
+      uint32_t instr_cache_size;
+
+      bool has_hw_multiview;
+
+      bool has_fs_tex_prefetch;
+
+      /* Whether the PC_MULTIVIEW_MASK register exists. */
+      bool supports_multiview_mask;
+
+      /* info for setting RB_CCU_CNTL */
+      bool concurrent_resolve;
+      bool has_z24uint_s8uint;
+
+      /* on a650, vertex shader <-> tess control io uses LDL/STL */
+      bool tess_use_shared;
+
+      /* Does the hw support GL_QCOM_shading_rate? */
+      bool has_legacy_pipeline_shading_rate;
+
+      /* Whether a 16-bit descriptor can be used */
+      bool storage_16bit;
+
+      /* The latest known a630_sqe.fw fails to wait for WFI before
+       * reading the indirect buffer when using CP_DRAW_INDIRECT_MULTI,
+       * so we have to fall back to CP_WAIT_FOR_ME except for a650
+       * which has a fixed firmware.
+       *
+       * TODO: There may be newer a630_sqe.fw released in the future
+       * which fixes this, if so we should detect it and avoid this
+       * workaround.  Once we have uapi to query fw version, we can
+       * replace this with minimum fw version.
+       */
+      bool indirect_draw_wfm_quirk;
+
+      /* On some GPUs, the depth test needs to be enabled when the
+       * depth bounds test is enabled and the depth attachment uses UBWC.
+       */
+      bool depth_bounds_require_depth_test_quirk;
+
+      bool has_tex_filter_cubic;
+
+      /* The blob driver does not support SEPARATE_RECONSTRUCTION_FILTER_BIT
+       * before a6xx_gen3.  It still sets CHROMA_LINEAR bit according to
+       * chromaFilter, but the bit has no effect before a6xx_gen3.
+       */
+      bool has_separate_chroma_filter;
+
+      bool has_sample_locations;
+
+      /* The firmware on newer a6xx drops CP_REG_WRITE support as we
+       * can now use direct register writes for these regs.
+       */
+      bool has_cp_reg_write;
+
+      bool has_8bpp_ubwc;
+
+      bool has_lpac;
+
+      /* True if getfiberid, getlast.w8, brcst.active, and quad_shuffle
+       * instructions are supported which are necessary to support
+       * subgroup quad and arithmetic operations.
+       */
+      bool has_getfiberid;
+
+      /* Whether half register shared->non-shared moves are broken. */
+      bool mov_half_shared_quirk;
+
+      /* Whether movs is supported for subgroupBroadcast. */
+      bool has_movs;
+
+      bool has_dp2acc;
+      bool has_dp4acc;
+
+      /* LRZ fast-clear works on all gens, however blob disables it on
+       * gen1 and gen2. We also elect to disable fast-clear on these gens
+       * because for close to none gains it adds complexity and seem to work
+       * a bit differently from gen3+. Which creates at least one edge case:
+       * if first draw which uses LRZ fast-clear doesn't lock LRZ direction
+       * the fast-clear value is undefined. For details see
+       * https://gitlab.freedesktop.org/mesa/mesa/-/issues/6829
+       */
+      bool enable_lrz_fast_clear;
+      bool has_lrz_dir_tracking;
+      bool lrz_track_quirk;
+      bool has_lrz_feedback;
+
+      /* Some generations have a bit to add the multiview index to the
+       * viewport index, which lets us implement different scaling for
+       * different views.
+       */
+      bool has_per_view_viewport;
+      bool has_gmem_fast_clear;
+
+      /* Per CCU GMEM amount reserved for color cache used by GMEM resolves
+       * which require color cache (non-BLIT event case).
+       * The size is expressed as a fraction of ccu cache used by sysmem
+       * rendering. If a GMEM resolve requires color cache, the driver needs
+       * to make sure it will not overwrite pixel data in GMEM that is still
+       * needed.
+       */
+      /* see enum a6xx_ccu_cache_size */
+      uint32_t gmem_ccu_color_cache_fraction;
+      uint32_t gmem_per_ccu_color_cache_size;
+      uint32_t gmem_ccu_depth_cache_fraction;
+      uint32_t gmem_per_ccu_depth_cache_size;
+      uint32_t sysmem_ccu_color_cache_fraction;
+      uint32_t sysmem_per_ccu_color_cache_size;
+      uint32_t sysmem_ccu_depth_cache_fraction;
+      uint32_t sysmem_per_ccu_depth_cache_size;
+
+      /* Size of various in-gmem caches: */
+      uint32_t sysmem_vpc_attr_buf_size;
+      uint32_t sysmem_vpc_pos_buf_size;
+      uint32_t sysmem_vpc_bv_pos_buf_size;
+      uint32_t gmem_vpc_attr_buf_size;
+      uint32_t gmem_vpc_pos_buf_size;
+      uint32_t gmem_vpc_bv_pos_buf_size;
+
+      /* Corresponds to SP_LB_PARAM_LIMIT::PRIMALLOCTHRESHOLD */
+      uint32_t prim_alloc_threshold;
+
+      uint32_t vs_max_inputs_count;
+
+      bool supports_double_threadsize;
+
+      /* Dual-wave dispatch replaces THREAD128 (supports_double_threadsize)
+       * on newer devices.
+       *
+       * This has some implications for marking join-points (jp), because
+       * while a wave may not diverge, a pair of waves might, for example
+       * subgroup-ops.
+       */
+      bool has_dual_wave_dispatch;
+
+      bool has_sampler_minmax;
+
+      bool has_astc_hdr;
+
+      bool broken_ds_ubwc_quirk;
+
+      /* True if there is a scalar ALU capable of executing a subset of
+       * cat2-cat4 instructions with a shared register destination. This also
+       * implies expanded MOV/COV capability when writing to shared registers,
+       * as MOV/COV is now executed on the scalar ALU except when reading from a
+       * normal register, as well as the ability for ldc to write to a shared
+       * register.
+       */
+      bool has_scalar_alu;
+
+      /* True if cat2 instructions can write predicate registers from the scalar
+       * ALU.
+       */
+      bool has_scalar_predicates;
+
+      /* On all generations that support scalar ALU, there is also a copy of the
+       * scalar ALU and some other HW units in HLSQ that can execute preambles
+       * before work is dispatched to the SPs, called "early preamble". We detect
+       * whether the shader can use early preamble in ir3.
+       */
+      bool has_early_preamble;
+
+      /* Whether isam.v is supported to sample multiple components from SSBOs */
+      bool has_isam_v;
+
+      /* Whether isam/stib/ldib have immediate offsets. */
+      bool has_ssbo_imm_offsets;
+
+      /* Whether writing to UBWC attachment and reading the same image as input
+       * attachment or as a texture reads correct values from the image.
+       * If this is false, we may read stale values from the flag buffer,
+       * thus reading incorrect values from the image.
+       * Happens with VK_EXT_attachment_feedback_loop_layout.
+       */
+      bool has_coherent_ubwc_flag_caches;
+
+      bool has_attachment_shading_rate;
+
+      /* Whether mipmaps below certain threshold can use LINEAR tiling when higher
+       * levels use UBWC,
+       */
+      bool has_ubwc_linear_mipmap_fallback;
+
+      /* Whether threshold for linear mipmaps for compressed textures is in
+       * blocks, if false then threshold is in texels.
+       */
+      bool supports_linear_mipmap_threshold_in_blocks;
+
+      /* Whether 4 nops are needed after the second pred[tf] of a
+       * pred[tf]/pred[ft] pair to work around a hardware issue.
+       */
+      bool predtf_nop_quirk;
+
+      /* Whether 6 nops are needed after prede to work around a hardware
+       * issue.
+       */
+      bool prede_nop_quirk;
+
+      /* Whether the sad instruction (iadd3) is supported. */
+      bool has_sad;
+
+      /* A702 cuts A LOT of things.. */
+      bool is_a702;
+
+      /* maximum number of descriptor sets */
+      uint32_t max_sets;
+
+      float line_width_min;
+      float line_width_max;
+
+      bool has_bin_mask;
+
+      /* On a618 at least, there seems to be an errata where a 3D draw
+       * followed by an A2D blit without any event or wait in between hangs
+       * waiting for the draw to complete. Seen on
+       * dEQP-VK.renderpass2.dedicated_allocation.attachment_allocation.grow.17
+       * with sysmem.
+       */
+      bool blit_wfi_quirk;
+
+      /* True if sel.b supports (neg) that behaves as fneg. */
+      bool has_sel_b_fneg;
+
+      /* Whether CP_REG_TEST::PRED_BIT exists so that there are 32 predicates
+       * that can be written by CP_REG_TEST instead of just 1.
+       */
+      bool has_pred_bit;
+
+      /* True if PC_DGEN_SO_CNTL is present. */
+      bool has_pc_dgen_so_cntl;
+
+      /*
+       * A7XX / gen7
+       */
+
+      /* stsc may need to be done twice for the same range to workaround
+       * _something_, observed in blob's disassembly.
+       */
+      bool stsc_duplication_quirk;
+
+      /* Whether there is CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT */
+      bool has_event_write_sample_count;
+
+      bool has_64b_ssbo_atomics;
+      bool has_64b_image_atomics;
+
+      /* Blob executes a special compute dispatch at the start of each
+       * command buffers. We copy this dispatch as is.
+       */
+      bool cmdbuf_start_a725_quirk;
+
+      bool load_inline_uniforms_via_preamble_ldgk;
+      bool load_shader_consts_via_preamble;
+
+      bool has_gmem_vpc_attr_buf;
+
+      /* Whether UBWC is supported on all UAVs. Prior to this, only readonly
+       * or writeonly UAVs could use UBWC and mixing reads and writes was not
+       * permitted.
+       */
+      bool supports_uav_ubwc;
+
+      /* Whether the UBWC fast-clear values for snorn, unorm, and int formats
+       * are the same. This is the case from a740 onwards. These formats were
+       * already otherwise UBWC-compatible, so this means that they are now
+       * fully compatible.
+       */
+      bool ubwc_unorm_snorm_int_compatible;
+
+      /* Having zero consts in one FS may corrupt consts in follow up FSs,
+       * on such GPUs blob never has zero consts in FS. The mechanism of
+       * corruption is unknown.
+       */
+      bool fs_must_have_non_zero_constlen_quirk;
+
+      /* On a750 there is a hardware bug where certain VPC sizes in a GS with
+       * an input primitive type that is a triangle with adjacency can hang
+       * with a high enough vertex count.
+       */
+      bool gs_vpc_adjacency_quirk;
+
+      /* On a740 TPL1_DBG_ECO_CNTL1.TP_UBWC_FLAG_HINT must be the same between
+       * all drivers in the system, somehow having different values affects
+       * BLIT_OP_SCALE. We cannot automatically match blob's value, so the
+       * best thing we could do is a toggle.
+       */
+      bool enable_tp_ubwc_flag_hint;
+
+      bool storage_8bit;
+
+      /* A750+ added a special flag that allows HW to correctly interpret UBWC, including
+       * UBWC fast-clear when casting image to a different format permitted by Vulkan.
+       * So it's possible to have UBWC enabled for image that has e.g. R32_UINT and
+       * R8G8B8A8_UNORM in the mutable formats list.
+       */
+      bool ubwc_all_formats_compatible;
+
+      bool has_compliant_dp4acc;
+
+      /* Whether a single clear blit could be used for both sysmem and gmem.*/
+      bool has_generic_clear;
+
+      /* Whether r8g8 UBWC fast-clear work correctly. */
+      bool r8g8_faulty_fast_clear_quirk;
+
+      /* a750 has a bug where writing and then reading a UBWC-compressed UAV
+       * requires flushing UCHE. This is reproducible in many CTS tests, for
+       * example dEQP-VK.image.load_store.with_format.2d.*.
+       */
+      bool ubwc_coherency_quirk;
+
+      /* Whether CP_ALWAYS_ON_COUNTER only resets on device loss rather than
+       * on every suspend/resume.
+       */
+      bool has_persistent_counter;
+
+      bool has_primitive_shading_rate;
+
+      /* If true, the hw shading rate value matches vk/gl rather than dx.
+       *
+       *   dx:  (width_log2 << 2) | height_log2
+       *   vk:  (height_log2 << 2) | width_log2
+       */
+      bool shading_rate_matches_vk;
+
+      /* A7XX gen1 and gen2 seem to require declaring SAMPLEMASK input
+       * for fragment shading rate to be read correctly.
+       * This workaround was seen in the prop driver v512.762.12.
+       */
+      bool reading_shading_rate_requires_smask_quirk;
+
+      /* Is lock/unlock sequence needed at end of compute shader? */
+      bool cs_lock_unlock_quirk;
+
+      /* Whether the ray_intersection instruction is present. */
+      bool has_ray_intersection;
+
+      /* Whether features may be fused off by the SW_FUSE. So far, this is
+       * just raytracing.
+       */
+      bool has_sw_fuse;
+
+      /* a750-specific HW bug workaround for ray tracing */
+      bool has_rt_workaround;
+
+      /* Whether alias.rt is supported. */
+      bool has_alias_rt;
+
+      /* Whether CP_SET_BIN_DATA5::ABS_MASK exists */
+      bool has_abs_bin_mask;
+
+      /* On a750 the control register layout is rearranged. */
+      bool new_control_regs;
+
+      /* a740+ support a per-view list of bin scales in GRAS which can be used
+       * to modify the viewport, rather than manually patching it in the
+       * driver.
+       */
+      bool has_hw_bin_scaling;
+
+      /* Whether the (eolm) and (eogm) nop flags are supported. */
+      bool has_eolm_eogm;
+
+      /* integer narrowing convert from GPR to uGPR does not behave as
+       * expected:
+       */
+      bool has_salu_int_narrowing_quirk;
+
+      /* Whether the device supports the image processing opcode */
+      bool has_image_processing;
+
+      /* The amount of valid draw state IDs. */
+      uint32_t max_draw_states;
+
+      /* Whether GRAS_CL_INTERP_CNTL has FACENESS/CENTERRHW and thus
+       * being able to avoid setting ij_linear_sample for FragFace/FragCoord.
+       */
+      bool has_implicit_fragface_fragcoord_ij_linear;
+   } props;
+};
+
+struct fd_dev_id {
+   uint32_t gpu_id;
+   uint64_t chip_id;
+};
+
+/**
+ * Note that gpu-id should be considered deprecated.  For newer a6xx, if
+ * there is no gpu-id, this attempts to generate one from the chip-id.
+ * But that may not work forever, so avoid depending on this for newer
+ * gens
+ */
+static inline uint32_t
+fd_dev_gpu_id(const struct fd_dev_id *id)
+{
+   assert(id->gpu_id || id->chip_id);
+   if (!id->gpu_id) {
+      return ((id->chip_id >> 24) & 0xff) * 100 +
+             ((id->chip_id >> 16) & 0xff) * 10 +
+             ((id->chip_id >>  8) & 0xff);
+
+   }
+   return id->gpu_id;
+}
+
+/* Unmodified dev info as defined in freedreno_devices.py */
+const struct fd_dev_info *fd_dev_info_raw(const struct fd_dev_id *id);
+
+/* Helper to check if GPU is known before going any further */
+static inline uint8_t
+fd_dev_is_supported(const struct fd_dev_id *id) {
+   assert(id);
+   assert(id->gpu_id || id->chip_id);
+   return fd_dev_info_raw(id) != NULL;
+}
+
+/* Final dev info with dbg options and everything else applied.  */
+struct fd_dev_info fd_dev_info(const struct fd_dev_id *id);
+
+const struct fd_dev_info *fd_dev_info_raw_by_name(const char *name);
+
+static uint8_t
+fd_dev_gen(const struct fd_dev_id *id)
+{
+   return fd_dev_info_raw(id)->chip;
+}
+
+static inline bool
+fd_dev_64b(const struct fd_dev_id *id)
+{
+   return fd_dev_gen(id) >= 5;
+}
+
+/* per CCU GMEM amount reserved for depth cache for direct rendering */
+#define A6XX_CCU_DEPTH_SIZE (64 * 1024)
+/* per CCU GMEM amount reserved for color cache used by GMEM resolves
+ * which require color cache (non-BLIT event case).
+ * this is smaller than what is normally used by direct rendering
+ * (RB_CCU_CNTL.GMEM bit enables this smaller size)
+ * if a GMEM resolve requires color cache, the driver needs to make sure
+ * it will not overwrite pixel data in GMEM that is still needed
+ */
+#define A6XX_CCU_GMEM_COLOR_SIZE (16 * 1024)
+
+const char * fd_dev_name(const struct fd_dev_id *id);
+
+void
+fd_dev_info_apply_dbg_options(struct fd_dev_info *info);
+
+#ifdef __cplusplus
+} /* end of extern "C" */
+#endif
+
+#endif /* FREEDRENO_DEVICE_INFO_H */

src/freedreno/common/freedreno_dev_info.py

@@ -0,0 +1,275 @@
+#
+# Copyright © 2021 Google, Inc.
+#
+# SPDX-License-Identifier: MIT
+
+from mako.template import Template
+import sys
+import argparse
+from enum import Enum
+
+def max_bitfield_val(high, low, shift):
+    return ((1 << (high - low)) - 1) << shift
+
+parser = argparse.ArgumentParser()
+parser.add_argument('-p', '--import-path', required=True)
+parser.add_argument('--nvtop', action='store_true')
+args = parser.parse_args()
+sys.path.insert(0, args.import_path)
+
+from a6xx import *
+
+
+class CHIP(Enum):
+    A2XX = 2
+    A3XX = 3
+    A4XX = 4
+    A5XX = 5
+    A6XX = 6
+    A7XX = 7
+    A8XX = 8
+
+class CCUColorCacheFraction(Enum):
+    FULL = 0
+    HALF = 1
+    QUARTER = 2
+    EIGHTH = 3
+    THREE_QUARTER = 3  # a8xx_gen2 and later
+
+
+class State(object):
+    def __init__(self):
+        # List of unique device-info structs, multiple different GPU ids
+        # can map to a single info struct in cases where the differences
+        # are not sw visible, or the only differences are parameters
+        # queried from the kernel (like GMEM size)
+        self.gpu_infos = []
+
+        # Table mapping GPU id to device-info struct
+        self.gpus = {}
+
+    def info_index(self, gpu_info):
+        i = 0
+        for info in self.gpu_infos:
+            if gpu_info == info:
+                return i
+            i += 1
+        raise Error("invalid info")
+
+s = State()
+
+def add_gpus(ids, info):
+    for id in ids:
+        s.gpus[id] = info
+
+class GPUId(object):
+    def __init__(self, gpu_id = None, chip_id = None, name=None):
+        if chip_id is None:
+            assert(gpu_id is not None)
+            val = gpu_id
+            core = int(val / 100)
+            val -= (core * 100)
+            major = int(val / 10)
+            val -= (major * 10)
+            minor = val
+            chip_id = (core << 24) | (major << 16) | (minor << 8) | 0xff
+        self.chip_id = chip_id
+        if gpu_id is None:
+            gpu_id = 0
+        self.gpu_id = gpu_id
+        if name is None:
+            assert(gpu_id != 0)
+            name = "FD%d" % gpu_id
+        self.name = name
+
+class Struct(object):
+    """A helper class that stringifies itself to a 'C' struct initializer
+    """
+    def __str__(self):
+        s = "{"
+        for name, value in vars(self).items():
+            s += "." + name + "=" + str(value) + ","
+        return s + "}"
+
+class GPUInfo(Struct):
+    """Base class for any generation of adreno, consists of GMEM layout
+       related parameters
+
+       Note that tile_max_h is normally only constrained by corresponding
+       bitfield size/shift (ie. VSC_BIN_SIZE, or similar), but tile_max_h
+       tends to have lower limits, in which case a comment will describe
+       the bitfield size/shift
+    """
+    def __init__(self, chip, gmem_align_w, gmem_align_h,
+                 tile_align_w, tile_align_h,
+                 tile_max_w, tile_max_h, num_vsc_pipes,
+                 cs_shared_mem_size, num_sp_cores, wave_granularity, fibers_per_sp,
+                 highest_bank_bit = 0, ubwc_swizzle = 0x7, macrotile_mode = 0,
+                 threadsize_base = 64, max_waves = 16, compute_lb_size = 0):
+        self.chip          = chip.value
+        self.gmem_align_w  = gmem_align_w
+        self.gmem_align_h  = gmem_align_h
+        self.tile_align_w  = tile_align_w
+        self.tile_align_h  = tile_align_h
+        self.tile_max_w    = tile_max_w
+        self.tile_max_h    = tile_max_h
+        self.num_vsc_pipes = num_vsc_pipes
+        self.cs_shared_mem_size = cs_shared_mem_size
+        self.num_sp_cores  = num_sp_cores
+        self.wave_granularity = wave_granularity
+        self.fibers_per_sp = fibers_per_sp
+        self.threadsize_base = threadsize_base
+        self.max_waves     = max_waves
+        self.highest_bank_bit = highest_bank_bit
+        self.ubwc_swizzle = ubwc_swizzle
+        self.macrotile_mode = macrotile_mode
+
+        s.gpu_infos.append(self)
+
+
+class A6xxGPUInfo(GPUInfo):
+    """The a6xx generation has a lot more parameters, and is broken down
+       into distinct sub-generations.  The template parameter avoids
+       duplication of parameters that are unique to the sub-generation.
+    """
+    def __init__(self, chip, template, num_ccu,
+                 tile_align_w, tile_align_h, tile_max_w, tile_max_h, num_vsc_pipes,
+                 cs_shared_mem_size, wave_granularity, fibers_per_sp,
+                 magic_regs, raw_magic_regs = None, highest_bank_bit = 15,
+                 ubwc_swizzle = 0x6, macrotile_mode = 1,
+                 threadsize_base = 64, max_waves = 16, num_slices = 0):
+        if chip == CHIP.A6XX:
+            compute_lb_size = 0
+        else:
+            # on a7xx the compute_lb_size is 40KB for all known parts for now.
+            # We have a parameter for it in case some low-end parts cut it down.
+            compute_lb_size = 40 * 1024
+
+        super().__init__(chip, gmem_align_w = 16, gmem_align_h = 4,
+                         tile_align_w = tile_align_w,
+                         tile_align_h = tile_align_h,
+                         tile_max_w   = tile_max_w,
+                         tile_max_h   = tile_max_h,
+                         num_vsc_pipes = num_vsc_pipes,
+                         cs_shared_mem_size = cs_shared_mem_size,
+                         num_sp_cores = num_ccu, # The # of SP cores seems to always match # of CCU
+                         wave_granularity   = wave_granularity,
+                         fibers_per_sp      = fibers_per_sp,
+                         highest_bank_bit = highest_bank_bit,
+                         ubwc_swizzle = ubwc_swizzle,
+                         macrotile_mode = macrotile_mode,
+                         threadsize_base    = threadsize_base,
+                         max_waves    = max_waves,
+                         compute_lb_size = compute_lb_size)
+
+        self.num_ccu = num_ccu
+        self.num_slices = num_slices
+
+        self.props = Struct()
+
+        self.magic = Struct()
+
+        for name, val in magic_regs.items():
+            setattr(self.magic, name, val)
+
+        if raw_magic_regs:
+            self.magic_raw = [[int(r[0]), r[1]] for r in raw_magic_regs]
+
+        templates = template if isinstance(template, list) else [template]
+        for template in templates:
+            template.apply_props(self)
+
+
+    def __str__(self):
+     return super(A6xxGPUInfo, self).__str__().replace('[', '{').replace("]", "}")
+
+class GPUProps(dict):
+    unique_props = dict()
+    def apply_props(self, gpu_info):
+        for name, val in self.items():
+            setattr(getattr(gpu_info, "props"), name, val)
+            GPUProps.unique_props[(name, "props")] = val
+
+template = """\
+/* Copyright © 2021 Google, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "freedreno_dev_info.h"
+#include "util/u_debug.h"
+#include "util/log.h"
+
+#include <stdlib.h>
+
+/* Map python to C: */
+#define True true
+#define False false
+
+%for info in s.gpu_infos:
+static const struct fd_dev_info __info${s.info_index(info)} = ${str(info)};
+%endfor
+
+static const struct fd_dev_rec fd_dev_recs[] = {
+%for id, info in s.gpus.items():
+   { {${id.gpu_id}, ${hex(id.chip_id)}}, "${id.name}", &__info${s.info_index(info)} },
+%endfor
+};
+
+void
+fd_dev_info_apply_dbg_options(struct fd_dev_info *info)
+{
+    const char *env = debug_get_option("FD_DEV_FEATURES", NULL);
+    if (!env || !*env)
+        return;
+
+    char *features = strdup(env);
+    char *feature, *feature_end;
+    feature = strtok_r(features, ":", &feature_end);
+    while (feature != NULL) {
+        char *name, *name_end;
+        name = strtok_r(feature, "=", &name_end);
+
+        if (!name) {
+            mesa_loge("Invalid feature \\"%s\\" in FD_DEV_FEATURES", feature);
+            exit(1);
+        }
+
+        char *value = strtok_r(NULL, "=", &name_end);
+
+        feature = strtok_r(NULL, ":", &feature_end);
+
+%for (prop, gen), val in unique_props.items():
+  <%
+    if isinstance(val, bool):
+        parse_value = "debug_parse_bool_option"
+    else:
+        parse_value = "debug_parse_num_option"
+  %>
+        if (strcmp(name, "${prop}") == 0) {
+            info->${gen}.${prop} = ${parse_value}(value, info->${gen}.${prop});
+            continue;
+        }
+%endfor
+
+        mesa_loge("Invalid feature \\"%s\\" in FD_DEV_FEATURES", name);
+        exit(1);
+    }
+
+    free(features);
+}
+"""
+
+nvtop_template="""
+static const struct msm_id_struct msm_ids[] = {
+%for id, info in s.gpus.items():
+  { ${hex(id.chip_id)}, "${id.name}" },
+%endfor
+};
+"""
+
+def main():
+    if args.nvtop:
+        print(Template(nvtop_template).render(s=s, unique_props=GPUProps.unique_props))
+    else:
+        print(Template(template).render(s=s, unique_props=GPUProps.unique_props))

src/freedreno/common/freedreno_gpu_event.h

@@ -0,0 +1,131 @@
+/*
+ * Copyright © 2023 Igalia S.L.
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef __FREEDRENO_GPU_EVENT_H__
+#define __FREEDRENO_GPU_EVENT_H__
+
+#include "fd_hw_common.h"
+#include "freedreno_common.h"
+
+/* On terminology:
+ * - CLEAN events write dirty cache lines to memory.
+ * - INVALIDATE events cause subsequent reads to read the cache line from
+ *   memory.
+ *
+ * Prior to a7xx CLEAN was instead called FLUSH. On a7xx FLUSH events do a
+ * clean and invalidate. We stick to the a7xx terminology in fd_gpu_event, and
+ * map FD_*_CLEAN events to the corresponding FLUSH events on a6xx. Note
+ * however that FLUSH_SO_* events, which write streamout counters to memory
+ * and also do a CACHE_CLEAN, haven't changed their names on a7xx.
+ */
+
+enum fd_gpu_event : uint32_t {
+    FD_WRITE_PRIMITIVE_COUNTS = 0,
+    FD_START_PRIMITIVE_CTRS,
+    FD_STOP_PRIMITIVE_CTRS,
+    FD_START_FRAGMENT_CTRS,
+    FD_STOP_FRAGMENT_CTRS,
+    FD_START_COMPUTE_CTRS,
+    FD_STOP_COMPUTE_CTRS,
+    FD_ZPASS_DONE,
+    FD_RB_DONE,
+    FD_FLUSH_SO_0,
+    FD_FLUSH_SO_1,
+    FD_FLUSH_SO_2,
+    FD_FLUSH_SO_3,
+    FD_CACHE_CLEAN,
+    FD_CACHE_INVALIDATE,
+    FD_CCU_INVALIDATE_DEPTH,
+    FD_CCU_INVALIDATE_COLOR,
+    FD_CCU_CLEAN_BLIT_CACHE,
+    FD_CCU_CLEAN_DEPTH,
+    FD_CCU_CLEAN_COLOR,
+    FD_LRZ_CLEAR,
+    FD_LRZ_FLIP,
+    FD_LRZ_FLUSH,
+    FD_LRZ_INVALIDATE,
+    FD_VSC_BINNING_START,
+    FD_VSC_BINNING_END,
+    FD_CCU_RESOLVE,
+    FD_LABEL,
+    FD_DUMMY_EVENT,
+
+    FD_GPU_EVENT_MAX,
+};
+
+struct fd_gpu_event_info {
+    enum vgt_event_type raw_event;
+    bool needs_seqno;
+};
+
+template <chip_range_support>
+constexpr struct fd_gpu_event_info fd_gpu_events[FD_GPU_EVENT_MAX] = {};
+
+template <chip CHIP>
+constexpr inline struct fd_gpu_event_info fd_gpu_events<chip_range(CHIP == A6XX)>[FD_GPU_EVENT_MAX] = {
+    {WRITE_PRIMITIVE_COUNTS, false},  /* FD_WRITE_PRIMITIVE_COUNTS */
+    {START_PRIMITIVE_CTRS, false},    /* FD_START_PRIMITIVE_CTRS */
+    {STOP_PRIMITIVE_CTRS, false},     /* FD_STOP_PRIMITIVE_CTRS */
+    {START_FRAGMENT_CTRS, false},     /* FD_START_FRAGMENT_CTRS */
+    {STOP_FRAGMENT_CTRS, false},      /* FD_STOP_FRAGMENT_CTRS */
+    {START_COMPUTE_CTRS, false},      /* FD_START_COMPUTE_CTRS */
+    {STOP_COMPUTE_CTRS, false},       /* FD_STOP_COMPUTE_CTRS */
+    {ZPASS_DONE, false},              /* FD_ZPASS_DONE */
+    {RB_DONE_TS, true},               /* FD_RB_DONE */
+    {FLUSH_SO_0, false},              /* FD_FLUSH_SO_0 */
+    {FLUSH_SO_1, false},              /* FD_FLUSH_SO_1 */
+    {FLUSH_SO_2, false},              /* FD_FLUSH_SO_2 */
+    {FLUSH_SO_3, false},              /* FD_FLUSH_SO_3 */
+    {CACHE_FLUSH_TS, true},           /* FD_CACHE_CLEAN */
+    {CACHE_INVALIDATE, false},        /* FD_CACHE_INVALIDATE */
+    {PC_CCU_INVALIDATE_DEPTH, false}, /* FD_CCU_INVALIDATE_DEPTH */
+    {PC_CCU_INVALIDATE_COLOR, false}, /* FD_CCU_INVALIDATE_COLOR */
+    {PC_CCU_RESOLVE_TS, true},        /* FD_CCU_CLEAN_BLIT_CACHE */
+    {PC_CCU_FLUSH_DEPTH_TS, true},    /* FD_CCU_CLEAN_DEPTH */
+    {PC_CCU_FLUSH_COLOR_TS, true},    /* FD_CCU_CLEAN_COLOR */
+    {LRZ_CLEAR, false},               /* FD_LRZ_CLEAR */
+    {DEBUG_LABEL, false},             /* FD_LRZ_FLIP */
+    {LRZ_FLUSH_INVALIDATE, false},    /* FD_LRZ_FLUSH */
+    {DEBUG_LABEL, false},             /* FD_LRZ_INVALIDATE */
+    {VSC_BINNING_START, false},       /* FD_VSC_BINNING_START */
+    {VSC_BINNING_END, false},         /* FD_VSC_BINNING_END */
+    {CCU_RESOLVE, false},             /* FD_CCU_RESOLVE */
+    {DEBUG_LABEL, false},             /* FD_LABEL */
+};
+
+template <chip CHIP>
+constexpr inline struct fd_gpu_event_info fd_gpu_events<chip_range(CHIP >= A7XX)>[FD_GPU_EVENT_MAX] = {
+    {WRITE_PRIMITIVE_COUNTS, false},  /* FD_WRITE_PRIMITIVE_COUNTS */
+    {START_PRIMITIVE_CTRS, false},    /* FD_START_PRIMITIVE_CTRS */
+    {STOP_PRIMITIVE_CTRS, false},     /* FD_STOP_PRIMITIVE_CTRS */
+    {START_FRAGMENT_CTRS, false},     /* FD_START_FRAGMENT_CTRS */
+    {STOP_FRAGMENT_CTRS, false},      /* FD_STOP_FRAGMENT_CTRS */
+    {START_COMPUTE_CTRS, false},      /* FD_START_COMPUTE_CTRS */
+    {STOP_COMPUTE_CTRS, false},       /* FD_STOP_COMPUTE_CTRS */
+    {ZPASS_DONE, false},              /* FD_ZPASS_DONE */
+    {RB_DONE_TS, true},               /* FD_RB_DONE */
+    {FLUSH_SO_0, false},              /* FD_FLUSH_SO_0 */
+    {FLUSH_SO_1, false},              /* FD_FLUSH_SO_1 */
+    {FLUSH_SO_2, false},              /* FD_FLUSH_SO_2 */
+    {FLUSH_SO_3, false},              /* FD_FLUSH_SO_3 */
+    {CACHE_CLEAN, false},             /* FD_CACHE_CLEAN */
+    {CACHE_INVALIDATE7, false},       /* FD_CACHE_INVALIDATE */
+    {CCU_INVALIDATE_DEPTH, false},    /* FD_CCU_INVALIDATE_DEPTH */
+    {CCU_INVALIDATE_COLOR, false},    /* FD_CCU_INVALIDATE_COLOR */
+    {CCU_RESOLVE_CLEAN, false},       /* FD_CCU_CLEAN_BLIT_CACHE */
+    {CCU_CLEAN_DEPTH, false},         /* FD_CCU_CLEAN_DEPTH */
+    {CCU_CLEAN_COLOR, false},         /* FD_CCU_CLEAN_COLOR */
+    {LRZ_CLEAR, false},               /* FD_LRZ_CLEAR */
+    {LRZ_FLIP_BUFFER, false},         /* FD_LRZ_FLIP */
+    {LRZ_CACHE_FLUSH, false},         /* FD_LRZ_FLUSH */
+    {LRZ_CACHE_INVALIDATE, false},    /* FD_LRZ_INVALIDATE */
+    {VSC_BINNING_START, false},       /* FD_VSC_BINNING_START */
+    {VSC_BINNING_END, false},         /* FD_VSC_BINNING_END */
+    {CCU_RESOLVE, false},             /* FD_CCU_RESOLVE */
+    {DEBUG_LABEL, false},             /* FD_LABEL */
+    {DUMMY_EVENT, false},             /* FD_DUMMY_EVENT */
+};
+
+#endif

src/freedreno/common/freedreno_guardband.h

@@ -0,0 +1,85 @@
+/*
+ * Copyright © 2020 Valve Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef __FREEDRENO_GUARDBAND_H__
+#define __FREEDRENO_GUARDBAND_H__
+
+#include <assert.h>
+#include <math.h>
+#include <stdbool.h>
+
+/* All 1's but don't overflow the GUARDBAND_CLIP_ADJ bitfields: */
+#define MAX_GB 0x1ff
+
+static inline unsigned
+fd_calc_guardband(float offset, float scale, bool is_a3xx)
+{
+   /* On a3xx, the viewport max is 4k and the docs say the max guardband
+    * width is 8k. That is, GRAS cannot handle triangle coordinates more than
+    * 8k, positive or negative. On a4xx+ the viewport width was bumped to
+    * 16k, and so the guardband width was necessarily also bumped. Note that
+    * the numbers here should correspond to
+    * VkPhysicalDeviceLimits::viewportBoundsRange in Vulkan.
+    */
+   const float gb_min = is_a3xx ? -8192. : -32768.;
+   const float gb_max = is_a3xx ? 8191. : 32767.;
+
+   /* Clipping happens in normalized device coordinates, so we have to
+    * transform gb_min and gb_max to ndc using the inverse of the viewport
+    * transform. Avoid flipping min and max by using the absolute value of
+    * the scale.
+    */
+   const float gb_min_ndc = (gb_min - offset) / fabsf(scale);
+   const float gb_max_ndc = (gb_max - offset) / fabsf(scale);
+
+   /* There's only one GB_ADJ field, so presumably the guardband is
+    * [-GB_ADJ, GB_ADJ] like on Radeon. It's always safe to make the
+    * guardband smaller, so we have to take the min to get the largest range
+    * contained in [gb_min_ndc, gb_max_ndc].
+    */
+   const float gb_adj = fminf(-gb_min_ndc, gb_max_ndc);
+
+   /* The viewport should always be contained in the guardband. */
+   if (gb_adj < 1.0)
+      return MAX_GB;
+
+   /* frexp returns an unspecified value if given an infinite value, which
+    * can happen if scale == 0.
+    */
+   if (isinf(gb_adj))
+      return MAX_GB;
+
+   /* Convert gb_adj to 3.6 floating point, rounding down since it's always
+    * safe to make the guard band smaller (but not the other way around!).
+    *
+    * Note: After converting back to a float, the value the blob returns here
+    * is sometimes a little smaller than the value we return. This seems to
+    * happen around the boundary between two different rounded values. For
+    * example, using the a6xx blob:
+    *
+    * min  | width  | unrounded gb_adj | blob result | mesa result
+    * ------------------------------------------------------------
+    * 0    | 510    |          127.498 |        127. |        127.
+    * 0    | 511    |          127.247 |        126. |        127.
+    * 0    | 512    |          126.996 |        126. |        126.
+    *
+    * The guardband must be 32767 wide, since that's what the blob reports
+    * for viewportBoundsRange, so I'm guessing that they're rounding slightly
+    * more conservatively somehow.
+    */
+   int gb_adj_exp;
+   float gb_adj_mantissa = frexpf(gb_adj, &gb_adj_exp);
+   if (gb_adj_exp <= 0)
+      return MAX_GB;
+
+   /* Round non-representable numbers down to the largest possible number. */
+   if (gb_adj_exp > 8)
+      return MAX_GB;
+
+   return ((gb_adj_exp - 1) << 6) |
+          ((unsigned)truncf(gb_adj_mantissa * (1 << 7)) - (1 << 6));
+}
+
+#endif /* __FREEDRENO_GUARDBAND_H__ */

src/freedreno/common/freedreno_lrz.h

@@ -0,0 +1,191 @@
+/*
+ * Copyright © 2024 Igalia S.L.
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef __FREEDRENO_LRZ_H__
+#define __FREEDRENO_LRZ_H__
+
+#include "fd_hw_common.h"
+#include "freedreno_common.h"
+
+enum fd_lrz_gpu_dir : uint8_t {
+   FD_LRZ_GPU_DIR_DISABLED = 0,
+   FD_LRZ_GPU_DIR_LESS = 1,
+   FD_LRZ_GPU_DIR_GREATER = 2,
+   FD_LRZ_GPU_DIR_NOT_SET = 3,
+};
+
+UNUSED static const char *
+fd_lrz_gpu_dir_to_str(enum fd_lrz_gpu_dir dir)
+{
+   switch (dir) {
+   case FD_LRZ_GPU_DIR_DISABLED:
+      return "DISABLED";
+   case FD_LRZ_GPU_DIR_LESS:
+      return "DIR_LESS";
+   case FD_LRZ_GPU_DIR_GREATER:
+      return "DIR_GREATER";
+   case FD_LRZ_GPU_DIR_NOT_SET:
+      return "DIR_NOT_SET";
+   default:
+      return "INVALID";
+   }
+}
+
+/* Layout of LRZ fast-clear buffer templated on the generation, the
+ * members are as follows:
+ * - fc1: The first FC buffer, always present. This may contain multiple
+ *        sub-buffers with _a/_b suffixes for concurrent binning which
+ *        can be checked using HAS_CB.
+ * - fc2: The second FC buffer, used for bidirectional LRZ and only present
+ *        when HAS_BIDIR set. It has suffixes for CB like fc1.
+ * - metadata: Metadata buffer for LRZ fast-clear. The contents are not
+ *             always known, since they're handled by the hardware.
+ */
+template <chip CHIP>
+struct fd_lrzfc_layout;
+
+template <>
+struct PACKED fd_lrzfc_layout<A6XX> {
+   static const bool HAS_BIDIR = false;
+   static const bool HAS_CB = false;
+   static const size_t FC_SIZE = 512;
+
+   uint8_t fc1[FC_SIZE];
+   union {
+      struct {
+         struct {
+            enum fd_lrz_gpu_dir dir_track;
+            uint8_t _pad_;
+            uint32_t gras_lrz_depth_view;
+         } buffer[1];
+      };
+      uint8_t metadata[6];
+   };
+};
+
+template <>
+struct PACKED fd_lrzfc_layout<A7XX> {
+   static const bool HAS_BIDIR = true;
+   static const bool HAS_CB = true;
+   static const size_t FC_SIZE = 1024;
+
+   union {
+      struct {
+         uint8_t fc1_a[FC_SIZE];
+         uint8_t fc1_b[FC_SIZE];
+      };
+      uint8_t fc1[FC_SIZE * 2];
+   };
+   union {
+      struct {
+         struct {
+            enum fd_lrz_gpu_dir dir_track;
+            uint8_t _padding0[47];
+            uint32_t gras_lrz_depth_view;
+            uint8_t gras_lrz_depth_view_2;
+            uint8_t _padding1[3];
+            float depth_clear_val;
+            uint8_t _padding2[4];
+         } buffer[2];
+         uint32_t bv_cur_buffer; /* flipped by LRZ_FLIP_BUFFER */
+         uint8_t _padding0[60]; /* cacheline padding */
+         uint32_t br_cur_buffer; /* flipped by LRZ_FLIP_BUFFER */
+         uint8_t _padding1[60]; /* cacheline padding */
+      };
+      uint8_t metadata[512];
+   };
+   uint8_t _padding4[1536];
+   union {
+      struct {
+         uint8_t fc2_a[FC_SIZE];
+         uint8_t fc2_b[FC_SIZE];
+      };
+      uint8_t fc2[FC_SIZE * 2];
+   };
+};
+
+static_assert(sizeof(fd_lrzfc_layout<A7XX>) == 0x1800);
+static_assert(offsetof(fd_lrzfc_layout<A7XX>, fc1) == 0x0);
+static_assert(offsetof(fd_lrzfc_layout<A7XX>, fc2) == 0x1000);
+
+template <>
+struct PACKED fd_lrzfc_layout<A8XX> {
+   static const bool HAS_BIDIR = true;
+   static const bool HAS_CB = true;
+   static const size_t FC_SIZE = 2048;
+
+   union {
+      struct {
+         uint8_t fc1_a[FC_SIZE];
+         uint8_t fc1_b[FC_SIZE];
+      };
+      uint8_t fc1[FC_SIZE * 2];
+   };
+   union {
+      struct {
+         uint8_t fc2_a[FC_SIZE];
+         uint8_t fc2_b[FC_SIZE];
+      };
+      uint8_t fc2[FC_SIZE * 2];
+   };
+
+   /* 1k per buf0, buf1, bv flag, br flag.  Within each 1k
+    * is (slice_num * 64) followed by reserved padding.  Ie.
+    * each slice has it's own metadata.
+    *
+    * Within each 1k block, assume the per-slice status is
+    * laid out the same as before.  But this is unclear (and
+    * may differ between devices since the exact layout the
+    * hw uses does not seem to be specified as it was on
+    * earlier gens)
+    */
+   union {
+      struct {
+         struct {
+            enum fd_lrz_gpu_dir dir_track;
+            uint8_t _padding0[47];
+            uint32_t gras_lrz_depth_view;
+            uint8_t gras_lrz_depth_view_2;
+            uint8_t _padding1[3];
+            float depth_clear_val;
+            uint8_t _padding2[4];
+            /* above repeated for slice[1..n-1].. offset of above fields
+             * per slice is 64B*slice_num
+             *
+             * Note, may actually be 128B*slice_num on later gen8
+             */
+            uint8_t _padding3[1024-64];
+         } buffer[2];
+
+         uint32_t bv_cur_buffer; /* flipped by LRZ_FLIP_BUFFER */
+         uint8_t _padding0[60]; /* cacheline padding */
+         /* bv_cur_buffer is repeated for slice[1..n-1], offset
+          * of per-slice value is 64B*slice_num
+          */
+         uint8_t _padding1[1024-64];
+
+         uint32_t br_cur_buffer; /* flipped by LRZ_FLIP_BUFFER */
+         uint8_t _padding2[60]; /* cacheline padding */
+         /* bv_cur_buffer is repeated for slice[1..n-1], offset
+          * of per-slice value is 64B*slice_num
+          */
+         uint8_t _padding3[1024-64];
+      };
+      uint8_t metadata[4096];
+   };
+
+   /* Extended in kaanapali and later with additional metadata
+    * below here.  For simplicity, use the larger size on all
+    * gen8.
+    */
+   struct {
+      uint8_t data[2048];
+   } wrdisbuf[2];
+   struct {
+      uint8_t data[8096];
+   } compmaskidx[2];
+};
+
+#endif

src/freedreno/common/freedreno_pm4.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright © 2012-2018 Rob Clark <[email protected]>
+ * SPDX-License-Identifier: MIT
+ *
+ * Authors:
+ *    Rob Clark <[email protected]>
+ */
+
+#ifndef FREEDRENO_PM4_H_
+#define FREEDRENO_PM4_H_
+
+#include <stdint.h>
+
+#include "adreno_pm4.xml.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CP_NOP_MESG 0x4D455347
+#define CP_NOP_BEGN 0x4245474E
+#define CP_NOP_END  0x454E4400
+
+/*
+ * Helpers for pm4 pkt header building/parsing:
+ */
+
+static inline unsigned
+pm4_odd_parity_bit(unsigned val)
+{
+   /* See: http://graphics.stanford.edu/~seander/bithacks.html#ParityParallel
+    * note that we want odd parity so 0x6996 is inverted.
+    */
+   val ^= val >> 16;
+   val ^= val >> 8;
+   val ^= val >> 4;
+   val &= 0xf;
+   return (~0x6996 >> val) & 1;
+}
+
+static inline uint32_t
+pm4_pkt0_hdr(uint16_t regindx, uint16_t cnt)
+{
+   return CP_TYPE0_PKT | ((cnt - 1) << 16) | (regindx & 0x7fff);
+}
+
+static inline uint32_t
+pm4_pkt3_hdr(uint8_t opcode, uint16_t cnt)
+{
+   return CP_TYPE3_PKT | ((cnt - 1) << 16) | ((opcode & 0xff) << 8);
+}
+
+static inline uint32_t
+pm4_pkt4_hdr(uint16_t regindx, uint16_t cnt)
+{
+   assert(cnt < 0x7f);
+   assert (cnt > 0);
+   assert(regindx);
+   return CP_TYPE4_PKT | cnt | (pm4_odd_parity_bit(cnt) << 7) |
+         ((regindx & 0x3ffff) << 8) |
+         ((pm4_odd_parity_bit(regindx) << 27));
+}
+
+static inline uint32_t
+pm4_pkt7_hdr(uint8_t opcode, uint16_t cnt)
+{
+   return CP_TYPE7_PKT | cnt | (pm4_odd_parity_bit(cnt) << 15) |
+         ((opcode & 0x7f) << 16) |
+         ((pm4_odd_parity_bit(opcode) << 23));
+}
+
+/*
+ * Helpers for packet parsing:
+ */
+
+#define pkt_is_type0(pkt)     (((pkt)&0XC0000000) == CP_TYPE0_PKT)
+#define type0_pkt_size(pkt)   ((((pkt) >> 16) & 0x3FFF) + 1)
+#define type0_pkt_offset(pkt) ((pkt)&0x7FFF)
+
+#define pkt_is_type2(pkt) ((pkt) == CP_TYPE2_PKT)
+
+#define pkt_is_type3(pkt)                                                      \
+   ((((pkt)&0xC0000000) == CP_TYPE3_PKT) && (((pkt)&0x80FE) == 0))
+
+#define cp_type3_opcode(pkt) (((pkt) >> 8) & 0xFF)
+#define type3_pkt_size(pkt)  ((((pkt) >> 16) & 0x3FFF) + 1)
+
+static inline unsigned
+pm4_calc_odd_parity_bit(unsigned val)
+{
+   return (0x9669 >> (0xf & ((val) ^ ((val) >> 4) ^ ((val) >> 8) ^
+                             ((val) >> 12) ^ ((val) >> 16) ^ ((val) >> 20) ^
+                             ((val) >> 24) ^ ((val) >> 28)))) &
+          1;
+}
+
+#define pkt_is_type4(pkt)                                                      \
+   ((((pkt)&0xF0000000) == CP_TYPE4_PKT) &&                                    \
+    ((((pkt) >> 27) & 0x1) ==                                                  \
+     pm4_calc_odd_parity_bit(type4_pkt_offset(pkt))) &&                        \
+    ((((pkt) >> 7) & 0x1) == pm4_calc_odd_parity_bit(type4_pkt_size(pkt))))
+
+#define type4_pkt_offset(pkt) (((pkt) >> 8) & 0x7FFFF)
+#define type4_pkt_size(pkt)   ((pkt)&0x7F)
+
+#define pkt_is_type7(pkt)                                                      \
+   ((((pkt)&0xF0000000) == CP_TYPE7_PKT) && (((pkt)&0x0F000000) == 0) &&       \
+    ((((pkt) >> 23) & 0x1) ==                                                  \
+     pm4_calc_odd_parity_bit(cp_type7_opcode(pkt))) &&                         \
+    ((((pkt) >> 15) & 0x1) == pm4_calc_odd_parity_bit(type7_pkt_size(pkt))))
+
+#define cp_type7_opcode(pkt) (((pkt) >> 16) & 0x7F)
+#define type7_pkt_size(pkt)  ((pkt)&0x3FFF)
+
+#define pkt_field_get(reg_field, pkt)                                          \
+   (((pkt)&CONCAT2(reg_field, __MASK)) >> CONCAT2(reg_field, __SHIFT))
+#define pkt_field_set(reg_field, pkt, new_val)                                 \
+   (((pkt) & ~CONCAT2(reg_field, __MASK)) | reg_field(new_val))
+
+#ifdef __cplusplus
+} /* end of extern "C" */
+#endif
+
+#endif /* FREEDRENO_PM4_H_ */

src/freedreno/common/freedreno_rd_output.c

@@ -0,0 +1,360 @@
+/*
+ * Copyright © 2024 Igalia S.L.
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "freedreno_rd_output.h"
+
+#include <assert.h>
+#include <ctype.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/stat.h>
+#include <unistd.h>
+
+#include "c11/threads.h"
+#include "util/detect_os.h"
+#include "util/log.h"
+#include "util/u_atomic.h"
+#include "util/u_debug.h"
+
+static const struct debug_control fd_rd_dump_options[] = {
+   { "enable", FD_RD_DUMP_ENABLE },
+   { "combine", FD_RD_DUMP_COMBINE },
+   { "full", FD_RD_DUMP_FULL },
+   { "trigger", FD_RD_DUMP_TRIGGER },
+   { NULL, 0 }
+};
+
+struct fd_rd_dump_env fd_rd_dump_env;
+
+struct fd_rd_dump_range {
+   unsigned range_begin;
+   unsigned range_end;
+};
+
+static void
+fd_rd_dump_env_init_once(void)
+{
+   fd_rd_dump_env.flags = parse_debug_string(os_get_option("FD_RD_DUMP"),
+                                             fd_rd_dump_options);
+
+   /* If any of the more-detailed FD_RD_DUMP flags is enabled, the general
+    * FD_RD_DUMP_ENABLE flag should also implicitly be set.
+    */
+   if (fd_rd_dump_env.flags & ~FD_RD_DUMP_ENABLE)
+      fd_rd_dump_env.flags |= FD_RD_DUMP_ENABLE;
+
+   const char *output_path_value = os_get_option("FD_RD_DUMP_PATH");
+   if (!output_path_value) {
+      output_path_value =
+#if DETECT_OS_ANDROID
+         "/data/local/tmp";
+#else
+         "/tmp";
+#endif
+   }
+   snprintf(fd_rd_dump_env.output_path, sizeof(fd_rd_dump_env.output_path),
+      "%s", output_path_value);
+}
+
+void
+fd_rd_dump_env_init(void)
+{
+   static once_flag once = ONCE_FLAG_INIT;
+   call_once(&once, fd_rd_dump_env_init_once);
+}
+
+static void
+fd_rd_output_sanitize_name(char *name)
+{
+   /* The name string is null-terminated after being constructed via asprintf.
+    * Sanitize it by reducing to an underscore anything that's not a hyphen,
+    * underscore, dot or alphanumeric character.
+    */
+   for (char *s = name; *s; ++s) {
+      if (isalnum(*s) || *s == '-' || *s == '_' || *s == '.')
+         continue;
+      *s = '_';
+   }
+}
+
+static void
+fd_rd_parse_dump_range(const char *option_name, struct util_dynarray *range_array)
+{
+   *range_array = UTIL_DYNARRAY_INIT;
+   const char *range_value = os_get_option(option_name);
+   if (!range_value)
+      return;
+
+   const char *p = range_value;
+   while (p && *p) {
+      char *ep = NULL;
+
+      struct fd_rd_dump_range range;
+      range.range_begin = strtol(p, &ep, 0);
+      if (ep == p)
+         break;
+      p = ep;
+
+      range.range_end = range.range_begin;
+      if (*p == '-') {
+         ep = NULL;
+         range.range_end = strtol(++p, &ep, 0);
+         if (ep == p)
+            break;
+         p = ep;
+      }
+
+      util_dynarray_append(range_array, range);
+
+      if (*p == ',')
+         ++p;
+      if (!isdigit(*p) && !!*p)
+         break;
+   }
+
+   if (*p == '\0') {
+      mesa_logi("[fd_rd_output] %s specified %" PRIuPTR " dump ranges:",
+                option_name, util_dynarray_num_elements(range_array, struct fd_rd_dump_range));
+      util_dynarray_foreach(range_array, struct fd_rd_dump_range, range) {
+         mesa_logi("[fd_rd_output]   [%u, %u]", range->range_begin, range->range_end);
+      }
+   } else {
+      mesa_logi("[fd_rd_output] failed to parse dump range '%s' for %s",
+                range_value, option_name);
+
+      util_dynarray_clear(range_array);
+      struct fd_rd_dump_range invalid_range = {
+         .range_begin = UINT_MAX,
+         .range_end = UINT_MAX,
+      };
+      util_dynarray_append(range_array, invalid_range);
+   }
+}
+
+static bool
+fd_rd_output_allowed(struct fd_rd_output *output, uint32_t frame, uint32_t submit)
+{
+   /* Allow output if no ranges were specified. */
+   if (!util_dynarray_num_elements(&output->frame_ranges, struct fd_rd_dump_range) &&
+       !util_dynarray_num_elements(&output->submit_ranges, struct fd_rd_dump_range))
+      return true;
+
+   util_dynarray_foreach(&output->frame_ranges, struct fd_rd_dump_range, range) {
+      if (frame >= range->range_begin && frame <= range->range_end)
+         return true;
+   }
+
+   util_dynarray_foreach(&output->submit_ranges, struct fd_rd_dump_range, range) {
+      if (submit >= range->range_begin && submit <= range->range_end)
+         return true;
+   }
+
+   return false;
+}
+
+void
+fd_rd_output_init(struct fd_rd_output *output, const char* output_name)
+{
+   const char *test_name = os_get_option("FD_RD_DUMP_TESTNAME");
+   ASSERTED int name_len;
+   if (test_name)
+      name_len = asprintf(&output->name, "%s_%s", test_name, output_name);
+   else
+      name_len = asprintf(&output->name, "%s", output_name);
+   assert(name_len != -1);
+   fd_rd_output_sanitize_name(output->name);
+
+   output->combine = false;
+   output->file = NULL;
+   output->trigger_fd = -1;
+   output->trigger_count = 0;
+
+   if (FD_RD_DUMP(COMBINE)) {
+      output->combine = true;
+
+      char file_path[PATH_MAX];
+      snprintf(file_path, sizeof(file_path), "%s/%s_combined.rd.gz",
+               fd_rd_dump_env.output_path, output->name);
+      output->file = gzopen(file_path, "w");
+   }
+
+   if (FD_RD_DUMP(TRIGGER)) {
+      char file_path[PATH_MAX];
+      snprintf(file_path, sizeof(file_path), "%s/%s_trigger",
+               fd_rd_dump_env.output_path, output->name);
+      output->trigger_fd = open(file_path, O_RDWR | O_CREAT | O_TRUNC, 0600);
+   }
+
+   fd_rd_parse_dump_range("FD_RD_DUMP_FRAMES", &output->frame_ranges);
+   fd_rd_parse_dump_range("FD_RD_DUMP_SUBMITS", &output->submit_ranges);
+}
+
+void
+fd_rd_output_fini(struct fd_rd_output *output)
+{
+   free(output->name);
+
+   if (output->file != NULL) {
+      assert(output->combine);
+      gzclose(output->file);
+   }
+
+   if (output->trigger_fd >= 0) {
+      close(output->trigger_fd);
+
+      /* Remove the trigger file. The filename is reconstructed here
+       * instead of having to spend memory to store it in the struct.
+       */
+      char file_path[PATH_MAX];
+      snprintf(file_path, sizeof(file_path), "%s/%s_trigger",
+               fd_rd_dump_env.output_path, output->name);
+      unlink(file_path);
+   }
+
+   util_dynarray_fini(&output->frame_ranges);
+   util_dynarray_fini(&output->submit_ranges);
+}
+
+static void
+fd_rd_output_update_trigger_count(struct fd_rd_output *output)
+{
+   assert(FD_RD_DUMP(TRIGGER));
+
+   /* Retrieve the trigger file size, only attempt to update the trigger
+    * value if anything was actually written to that file.
+    */
+   struct stat stat;
+   if (fstat(output->trigger_fd, &stat) != 0) {
+      mesa_loge("[fd_rd_output] failed to acccess the %s trigger file",
+                output->name);
+      return;
+   }
+
+   if (stat.st_size == 0)
+      return;
+
+   char trigger_data[32];
+   int ret = read(output->trigger_fd, trigger_data, sizeof(trigger_data));
+   if (ret < 0) {
+      mesa_loge("[fd_rd_output] failed to read from the %s trigger file",
+                output->name);
+      return;
+   }
+   int num_read = MIN2(ret, sizeof(trigger_data) - 1);
+
+   /* After reading from it, the trigger file should be reset, which means
+    * moving the file offset to the start of the file as well as truncating
+    * it to zero bytes.
+    */
+   if (lseek(output->trigger_fd, 0, SEEK_SET) < 0) {
+      mesa_loge("[fd_rd_output] failed to reset the %s trigger file position",
+                output->name);
+      return;
+   }
+
+   if (ftruncate(output->trigger_fd, 0) < 0) {
+      mesa_loge("[fd_rd_output] failed to truncate the %s trigger file",
+                output->name);
+      return;
+   }
+
+   /* Try to decode the count value through strtol. -1 translates to UINT_MAX
+    * and keeps generating dumps until disabled. Any positive value will
+    * allow generating dumps for that many submits. Any other value will
+    * disable any further generation of RD dumps.
+    */
+   trigger_data[num_read] = '\0';
+   int32_t value = strtol(trigger_data, NULL, 0);
+
+   if (value == -1) {
+      output->trigger_count = UINT_MAX;
+      mesa_logi("[fd_rd_output] %s trigger enabling RD dumps until disabled",
+                output->name);
+   } else if (value > 0) {
+      output->trigger_count = (uint32_t) value;
+      mesa_logi("[fd_rd_output] %s trigger enabling RD dumps for next %u submissions",
+                output->name, output->trigger_count);
+   } else {
+      output->trigger_count = 0;
+      mesa_logi("[fd_rd_output] %s trigger disabling RD dumps", output->name);
+   }
+}
+
+bool
+fd_rd_output_begin(struct fd_rd_output *output, uint32_t frame, uint32_t submit)
+{
+   assert(output->combine ^ (output->file == NULL));
+
+   if (FD_RD_DUMP(TRIGGER)) {
+      fd_rd_output_update_trigger_count(output);
+
+      if (output->trigger_count == 0)
+         return false;
+      /* UINT_MAX corresponds to generating dumps until disabled. */
+      if (output->trigger_count != UINT_MAX)
+          --output->trigger_count;
+   }
+
+   if (!fd_rd_output_allowed(output, frame, submit))
+      return false;
+
+   if (output->combine)
+      return true;
+
+   char file_path[PATH_MAX];
+   if (frame != UINT_MAX) {
+      snprintf(file_path, sizeof(file_path), "%s/%s_frame%.5d_submit%.5d.rd",
+               fd_rd_dump_env.output_path, output->name, frame, submit);
+   } else {
+      snprintf(file_path, sizeof(file_path), "%s/%s_submit%.5d.rd",
+               fd_rd_dump_env.output_path, output->name, submit);
+   }
+   output->file = gzopen(file_path, "w");
+   return true;
+}
+
+static void
+fd_rd_output_write(struct fd_rd_output *output, const void *buffer, int size)
+{
+   const uint8_t *pos = (uint8_t *) buffer;
+   while (size > 0) {
+      int ret = gzwrite(output->file, pos, size);
+      if (ret < 0) {
+         mesa_loge("[fd_rd_output] failed to write to compressed output: %s",
+                   gzerror(output->file, NULL));
+         return;
+      }
+      pos += ret;
+      size -= ret;
+   }
+}
+
+void
+fd_rd_output_write_section(struct fd_rd_output *output, enum rd_sect_type type,
+                           const void *buffer, int size)
+{
+   fd_rd_output_write(output, &type, 4);
+   fd_rd_output_write(output, &size, 4);
+   fd_rd_output_write(output, buffer, size);
+}
+
+void
+fd_rd_output_end(struct fd_rd_output *output)
+{
+   assert(output->file != NULL);
+
+   /* When combining output, flush the gzip stream on each submit. This should
+    * store all the data before any problem during the submit itself occurs.
+    */
+   if (output->combine) {
+      gzflush(output->file, Z_FINISH);
+      return;
+   }
+
+   gzclose(output->file);
+   output->file = NULL;
+}

src/freedreno/common/freedreno_rd_output.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright © 2024 Igalia S.L.
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef __FREEDRENO_RD_OUTPUT_H__
+#define __FREEDRENO_RD_OUTPUT_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <zlib.h>
+
+#include "redump.h"
+#include "util/u_dynarray.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum fd_rd_dump_flags {
+   FD_RD_DUMP_ENABLE = 1 << 0,
+   FD_RD_DUMP_COMBINE = 1 << 1,
+   FD_RD_DUMP_FULL = 1 << 2,
+   FD_RD_DUMP_TRIGGER = 1 << 3,
+};
+
+struct fd_rd_dump_env {
+   uint32_t flags;
+   char output_path[PATH_MAX];
+};
+
+extern struct fd_rd_dump_env fd_rd_dump_env;
+
+#define FD_RD_DUMP(name) unlikely(fd_rd_dump_env.flags & FD_RD_DUMP_##name)
+
+void
+fd_rd_dump_env_init(void);
+
+struct fd_rd_output {
+   char *name;
+   bool combine;
+   gzFile file;
+
+   int trigger_fd;
+   uint32_t trigger_count;
+
+   struct util_dynarray frame_ranges;
+   struct util_dynarray submit_ranges;
+};
+
+void
+fd_rd_output_init(struct fd_rd_output *output, const char* output_name);
+
+void
+fd_rd_output_fini(struct fd_rd_output *output);
+
+bool
+fd_rd_output_begin(struct fd_rd_output *output, uint32_t frame, uint32_t submit_idx);
+
+void
+fd_rd_output_write_section(struct fd_rd_output *output, enum rd_sect_type type,
+                           const void *buffer, int size);
+
+void
+fd_rd_output_end(struct fd_rd_output *output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FREEDRENO_RD_OUTPUT_H__ */

src/freedreno/common/freedreno_stompable_regs.h

@@ -0,0 +1,91 @@
+/*
+ * Copyright © 2023 Igalia S.L.
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef __FREEDRENO_STOMPABLE_REGS_H__
+#define __FREEDRENO_STOMPABLE_REGS_H__
+
+#include <stdint.h>
+
+#include "util/macros.h"
+
+#include "fd6_hw.h"
+
+/* In order to debug issues with usage of stale reg data we need to have
+ * a list of regs which we allowed to stomp.
+ * The regs we are NOT allowed to stomp are:
+ * - Write protected;
+ * - Written by kernel but are not write protected;
+ * - Some regs that are not written by anyone but do affect the result.
+ *
+ * In addition, some regs are only emmitted during cmdbuf setup
+ * so we have to have additional filter to get a reduced list of regs
+ * stompable before each renderpass/blit.
+ */
+
+/* Stomping some regs is known to cause issues */
+static inline bool
+fd_reg_stomp_allowed(chip CHIP, uint16_t reg)
+{
+   PRAGMA_DIAGNOSTIC_PUSH
+   PRAGMA_DIAGNOSTIC_IGNORED_CLANG(-W#pragma-messages)
+
+   switch (CHIP) {
+   case A6XX: {
+      switch (reg) {
+      /* Faults in
+       * dEQP-VK.renderpass.suballocation.formats.r5g6b5_unorm_pack16.clear.clear
+       * It seems that PC_CCU_FLUSH_COLOR_TS reads REG_A6XX_RB_DEPTH_PLANE_CNTL.
+       */
+      case REG_A6XX_RB_DEPTH_PLANE_CNTL:
+      /* Faults in
+       * dEQP-VK.conditional_rendering.draw.condition_host_memory_expect_noop.draw
+       */
+      case REG_A6XX_SP_VS_CONST_CONFIG ... REG_A6XX_SP_GS_CONST_CONFIG:
+      case REG_A6XX_SP_PS_CONST_CONFIG:
+      /* Faults in
+       * dEQP-VK.memory_model.message_passing.ext.u32.coherent.atomic_atomic.atomicrmw.device.payload_local.image.guard_local.image.comp
+       * while there is even no fragment shaders.
+       */
+      case REG_A6XX_SP_PS_BASE ... REG_A6XX_SP_PS_BASE + 1:
+         return false;
+      }
+      break;
+   }
+   case A7XX: {
+      switch (reg) {
+      case REG_A6XX_RB_DEPTH_PLANE_CNTL:
+      case REG_A7XX_SP_VS_CONST_CONFIG:
+      case REG_A7XX_SP_HS_CONST_CONFIG:
+      case REG_A7XX_SP_DS_CONST_CONFIG:
+      case REG_A7XX_SP_GS_CONST_CONFIG:
+      case REG_A7XX_SP_PS_CONST_CONFIG:
+      case REG_A6XX_SP_VS_BASE ... REG_A6XX_SP_VS_BASE + 1:
+      case REG_A6XX_SP_PS_BASE ... REG_A6XX_SP_PS_BASE + 1:
+      case REG_A7XX_SP_GS_VGS_CNTL:
+      case REG_A7XX_SP_PS_VGS_CNTL:
+      case REG_A7XX_SP_CS_VGS_CNTL:
+         return false;
+      }
+
+      /* The reg stomper doesn't play well with VSC registers because they are
+       * shared between BR and BV and it isn't part of the synchronization
+       * dance to enable BV and binning in BR with concurrent binning disabled
+       * to share the use of them.
+       */
+      if (reg >= REG_A6XX_VSC_BIN_SIZE && reg <= REG_A7XX_VSC_UNKNOWN_0D08)
+         return false;
+
+      break;
+   }
+   default: {
+      UNREACHABLE("Unknown GPU");
+   }
+   PRAGMA_DIAGNOSTIC_POP
+   }
+
+   return true;
+}
+
+#endif /* __FREEDRENO_STOMPABLE_REGS_H__ */

src/freedreno/common/freedreno_ubwc.h

@@ -0,0 +1,115 @@
+/*
+ * Copyright © Google, Inc.
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef __FREEDRENO_UBWC_H__
+#define __FREEDRENO_UBWC_H__
+
+#include "util/format/u_format.h"
+
+#include "freedreno_dev_info.h"
+
+enum fd6_ubwc_compat_type {
+   FD6_UBWC_UNKNOWN_COMPAT,
+   FD6_UBWC_R8G8_UNORM,
+   FD6_UBWC_R8G8_INT,
+   FD6_UBWC_R8G8B8A8_UNORM,
+   FD6_UBWC_R8G8B8A8_INT,
+   FD6_UBWC_B8G8R8A8_UNORM,
+   FD6_UBWC_R16G16_UNORM,
+   FD6_UBWC_R16G16_INT,
+   FD6_UBWC_R16G16B16A16_UNORM,
+   FD6_UBWC_R16G16B16A16_INT,
+   FD6_UBWC_R32_INT,
+   FD6_UBWC_R32G32_INT,
+   FD6_UBWC_R32G32B32A32_INT,
+   FD6_UBWC_R32_FLOAT,
+};
+
+static inline enum fd6_ubwc_compat_type
+fd6_ubwc_compat_mode(const struct fd_dev_info *info, enum pipe_format format)
+{
+   switch (format) {
+   case PIPE_FORMAT_R8G8_UNORM:
+   case PIPE_FORMAT_R8G8_SRGB:
+      return info->props.ubwc_unorm_snorm_int_compatible ?
+         FD6_UBWC_R8G8_INT : FD6_UBWC_R8G8_UNORM;
+
+   case PIPE_FORMAT_R8G8_SNORM:
+      return info->props.ubwc_unorm_snorm_int_compatible ?
+         FD6_UBWC_R8G8_INT : FD6_UBWC_UNKNOWN_COMPAT;
+
+   case PIPE_FORMAT_R8G8_UINT:
+   case PIPE_FORMAT_R8G8_SINT:
+      return FD6_UBWC_R8G8_INT;
+
+   case PIPE_FORMAT_R8G8B8A8_UNORM:
+   case PIPE_FORMAT_R8G8B8A8_SRGB:
+      return info->props.ubwc_unorm_snorm_int_compatible ?
+         FD6_UBWC_R8G8B8A8_INT : FD6_UBWC_R8G8B8A8_UNORM;
+
+   case PIPE_FORMAT_R8G8B8A8_SNORM:
+      return info->props.ubwc_unorm_snorm_int_compatible ?
+         FD6_UBWC_R8G8B8A8_INT : FD6_UBWC_UNKNOWN_COMPAT;
+
+   case PIPE_FORMAT_R8G8B8A8_UINT:
+   case PIPE_FORMAT_R8G8B8A8_SINT:
+      return FD6_UBWC_R8G8B8A8_INT;
+
+   case PIPE_FORMAT_R16G16_UNORM:
+      return info->props.ubwc_unorm_snorm_int_compatible ?
+         FD6_UBWC_R16G16_INT : FD6_UBWC_R16G16_UNORM;
+
+   case PIPE_FORMAT_R16G16_SNORM:
+      return info->props.ubwc_unorm_snorm_int_compatible ?
+         FD6_UBWC_R16G16_INT : FD6_UBWC_UNKNOWN_COMPAT;
+
+   case PIPE_FORMAT_R16G16_UINT:
+   case PIPE_FORMAT_R16G16_SINT:
+      return FD6_UBWC_R16G16_INT;
+
+   case PIPE_FORMAT_R16G16B16A16_UNORM:
+      return info->props.ubwc_unorm_snorm_int_compatible ?
+         FD6_UBWC_R16G16B16A16_INT : FD6_UBWC_R16G16B16A16_UNORM;
+
+   case PIPE_FORMAT_R16G16B16A16_SNORM:
+      return info->props.ubwc_unorm_snorm_int_compatible ?
+         FD6_UBWC_R16G16B16A16_INT : FD6_UBWC_UNKNOWN_COMPAT;
+
+   case PIPE_FORMAT_R16G16B16A16_UINT:
+   case PIPE_FORMAT_R16G16B16A16_SINT:
+      return FD6_UBWC_R16G16B16A16_INT;
+
+   case PIPE_FORMAT_R32_UINT:
+   case PIPE_FORMAT_R32_SINT:
+      return FD6_UBWC_R32_INT;
+
+   case PIPE_FORMAT_R32G32_UINT:
+   case PIPE_FORMAT_R32G32_SINT:
+      return FD6_UBWC_R32G32_INT;
+
+   case PIPE_FORMAT_R32G32B32A32_UINT:
+   case PIPE_FORMAT_R32G32B32A32_SINT:
+      return FD6_UBWC_R32G32B32A32_INT;
+
+   case PIPE_FORMAT_Z32_FLOAT:
+   case PIPE_FORMAT_R32_FLOAT:
+      /* TODO: a630 blob allows these, but not a660.  When is it legal? */
+      return FD6_UBWC_UNKNOWN_COMPAT;
+
+   case PIPE_FORMAT_B8G8R8A8_UNORM:
+   case PIPE_FORMAT_B8G8R8A8_SRGB:
+      /* The blob doesn't list these as compatible, but they surely are.
+       * freedreno's happy to cast between them, and zink would really like
+       * to.
+       */
+      return FD6_UBWC_B8G8R8A8_UNORM;
+
+   default:
+      return FD6_UBWC_UNKNOWN_COMPAT;
+   }
+}
+
+
+#endif

src/freedreno/common/freedreno_uuid.c

@@ -0,0 +1,76 @@
+/*
+ * Copyright © 2020 Igalia S.L.
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "freedreno_dev_info.h"
+#include "freedreno_uuid.h"
+
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "util/mesa-blake3.h"
+#include "git_sha1.h"
+
+/* (Re)define UUID_SIZE to avoid including vulkan.h (or p_defines.h) here. */
+#define UUID_SIZE 16
+
+void
+fd_get_driver_uuid(void *uuid)
+{
+   const char *driver_id = PACKAGE_VERSION MESA_GIT_SHA1;
+
+   /* The driver UUID is used for determining sharability of images and memory
+    * between two Vulkan instances in separate processes, but also to
+    * determining memory objects and sharability between Vulkan and OpenGL
+    * driver. People who want to share memory need to also check the device
+    * UUID.
+    */
+   blake3_hasher blake3_ctx;
+   _mesa_blake3_init(&blake3_ctx);
+
+   _mesa_blake3_update(&blake3_ctx, driver_id, strlen(driver_id));
+
+   uint8_t blake3[BLAKE3_KEY_LEN];
+   _mesa_blake3_final(&blake3_ctx, blake3);
+
+   assert(BLAKE3_KEY_LEN >= UUID_SIZE);
+   memcpy(uuid, blake3, UUID_SIZE);
+}
+
+void
+fd_get_device_uuid(void *uuid, const struct fd_dev_id *id)
+{
+   blake3_hasher blake3_ctx;
+   _mesa_blake3_init(&blake3_ctx);
+
+   /* The device UUID uniquely identifies the given device within the machine.
+    * Since we never have more than one device, this doesn't need to be a real
+    * UUID, so we use BLAKE3("freedreno" + gpu_id).
+    *
+    * @TODO: Using the GPU id could be too restrictive on the off-chance that
+    * someone would like to use this UUID to cache pre-tiled images or something
+    * of the like, and use them across devices. In the future, we could allow
+    * that by:
+    * * Being a bit loose about GPU id and hash only the generation's
+    * 'major' number (e.g, '6' instead of '630').
+    *
+    * * Include HW specific constants that are relevant for layout resolving,
+    * like minimum width to enable UBWC, tile_align_w, etc.
+    *
+    * This would allow cached device memory to be safely used from HW in
+    * (slightly) different revisions of the same generation.
+    */
+
+   static const char *device_name = "freedreno";
+   _mesa_blake3_update(&blake3_ctx, device_name, strlen(device_name));
+
+   _mesa_blake3_update(&blake3_ctx, id, sizeof(*id));
+
+   uint8_t blake3[BLAKE3_KEY_LEN];
+   _mesa_blake3_final(&blake3_ctx, blake3);
+
+   assert(BLAKE3_KEY_LEN >= UUID_SIZE);
+   memcpy(uuid, blake3, UUID_SIZE);
+}

src/freedreno/common/freedreno_uuid.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright © 2020 Igalia S.L.
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef __FREEDRENO_UUID_H__
+#define __FREEDRENO_UUID_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct fd_dev_id;
+
+void fd_get_driver_uuid(void *uuid);
+void fd_get_device_uuid(void *uuid, const struct fd_dev_id *id);
+
+#ifdef __cplusplus
+} /* end of extern "C" */
+#endif
+
+#endif /* __FREEDRENO_UUID_H__ */

src/freedreno/common/freedreno_vrs.h

@@ -0,0 +1,107 @@
+/*
+ * Copyright © 2025 Valve Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef __FREEDRENO_VRS_H__
+#define __FREEDRENO_VRS_H__
+
+#include "util/macros.h"
+
+/* HW values for shading rate. This matches D3D12_SHADING_RATE. The value is
+ * encoded as (width_log2 << 2) | height_log2, but a width or height of 8 is
+ * not supported.  Vulkan and GL shading rate values are specified as
+ * (height_log2 << 2) | width_log2, and are translated to this via lookup
+ * tables in the last pre-rasterization shader (for per-primitive shading
+ * rate) and GRAS (for attachment-based shading rate).
+ */
+
+enum fd_shading_rate {
+   FD_SHADING_RATE_1X1 = 0,
+   FD_SHADING_RATE_1X2 = 1,
+   FD_SHADING_RATE_1X4 = 2,
+   FD_SHADING_RATE_2X1 = 4,
+   FD_SHADING_RATE_2X2 = 5,
+   FD_SHADING_RATE_2X4 = 6,
+   FD_SHADING_RATE_4X1 = 8,
+   FD_SHADING_RATE_4X2 = 9,
+   FD_SHADING_RATE_4X4 = 10,
+   FD_SHADING_RATE_INVALID = 11, /* used in shader LUT */
+};
+
+#define VK_SHADING_RATE(wlog2, hlog2) (((hlog2) << 2) | (wlog2))
+#define VK_SHADING_RATE_INVALID 11
+
+static const uint32_t vk_to_hw_shading_rate_lut[] = {
+   [VK_SHADING_RATE(0, 0)] = FD_SHADING_RATE_1X1,
+   [VK_SHADING_RATE(1, 0)] = FD_SHADING_RATE_2X1,
+   [VK_SHADING_RATE(2, 0)] = FD_SHADING_RATE_4X1,
+   [VK_SHADING_RATE(3, 0)] = FD_SHADING_RATE_INVALID,
+
+   [VK_SHADING_RATE(0, 1)] = FD_SHADING_RATE_1X2,
+   [VK_SHADING_RATE(1, 1)] = FD_SHADING_RATE_2X2,
+   [VK_SHADING_RATE(2, 1)] = FD_SHADING_RATE_4X2,
+   [VK_SHADING_RATE(3, 1)] = FD_SHADING_RATE_INVALID,
+
+   [VK_SHADING_RATE(0, 2)] = FD_SHADING_RATE_1X4,
+   [VK_SHADING_RATE(1, 2)] = FD_SHADING_RATE_2X4,
+   [VK_SHADING_RATE(2, 2)] = FD_SHADING_RATE_4X4,
+   [VK_SHADING_RATE(3, 2)] = FD_SHADING_RATE_INVALID,
+
+   [VK_SHADING_RATE(0, 3)] = FD_SHADING_RATE_INVALID,
+   [VK_SHADING_RATE(1, 3)] = FD_SHADING_RATE_INVALID,
+   [VK_SHADING_RATE(2, 3)] = FD_SHADING_RATE_INVALID,
+   [VK_SHADING_RATE(3, 3)] = FD_SHADING_RATE_INVALID,
+};
+
+/* The value provided to the FS is the HW value which must be translated back
+ * to the VK/GL value via this lookup table.
+ */
+
+static const uint32_t hw_to_vk_shading_rate_lut[] = {
+   [FD_SHADING_RATE_1X1] = VK_SHADING_RATE(0, 0),
+   [FD_SHADING_RATE_1X2] = VK_SHADING_RATE(0, 1),
+   [FD_SHADING_RATE_1X4] = VK_SHADING_RATE(0, 2),
+   [3] = VK_SHADING_RATE_INVALID,
+
+   [FD_SHADING_RATE_2X1] = VK_SHADING_RATE(1, 0),
+   [FD_SHADING_RATE_2X2] = VK_SHADING_RATE(1, 1),
+   [FD_SHADING_RATE_2X4] = VK_SHADING_RATE(1, 2),
+   [7] = VK_SHADING_RATE_INVALID,
+
+   [FD_SHADING_RATE_4X1] = VK_SHADING_RATE(2, 0),
+   [FD_SHADING_RATE_4X2] = VK_SHADING_RATE(2, 1),
+   [FD_SHADING_RATE_4X4] = VK_SHADING_RATE(2, 2),
+   [11] = VK_SHADING_RATE_INVALID,
+
+   [12] = VK_SHADING_RATE_INVALID,
+   [13] = VK_SHADING_RATE_INVALID,
+   [14] = VK_SHADING_RATE_INVALID,
+   [15] = VK_SHADING_RATE_INVALID,
+};
+
+/* The GRAS lookup table is an array of 4-bit values packed into 32-bit
+ * registers. Calculate the value to put in the given register.
+ */
+
+static ALWAYS_INLINE uint32_t
+fd_gras_shading_rate_lut(unsigned index)
+{
+   if (index / 8 >= ARRAY_SIZE(vk_to_hw_shading_rate_lut))
+      return 0;
+
+   uint32_t ret = 0;
+   for (unsigned i = 0; i < 8; i++) {
+      uint32_t rate = vk_to_hw_shading_rate_lut[index * 8 + i];
+      /* For some reason the blob avoids writing INVALID in the GRAS lookup
+       * table, unlike the shader lookup table. Follow it here.
+       */
+      if (rate == FD_SHADING_RATE_INVALID)
+         rate = 0;
+      ret |= rate << (4 * i);
+   }
+
+   return ret;
+}
+
+#endif

src/freedreno/common/meson.build

@@ -0,0 +1,46 @@
+# Copyright © 2020 Igalia S.L
+# SPDX-License-Identifier: MIT
+
+freedreno_devices_h = custom_target(
+  'freedreno_devices.h',
+  input: 'freedreno_devices.py',
+  output: 'freedreno_devices.h',
+  command: [
+    prog_python, '@INPUT@',
+    '-p', join_paths(meson.project_build_root(), 'src/freedreno/registers/adreno/')
+  ],
+  depends: freedreno_py_header_files,
+  depend_files: [files('freedreno_dev_info.py')],
+  capture: true,
+)
+
+libfreedreno_common = static_library(
+  'freedreno_common',
+  [
+    'disasm.h',
+    'fd6_pack.h',
+    'freedreno_dev_info.c',
+    'freedreno_dev_info.h',
+    'freedreno_pm4.h',
+    'freedreno_rd_output.c',
+    'freedreno_rd_output.h',
+    'freedreno_uuid.c',
+    'freedreno_uuid.h',
+    'freedreno_guardband.h',
+    'freedreno_vrs.h',
+    freedreno_devices_h,
+    freedreno_pm4_xml_header_file,
+    sha1_h,
+    'redump.h'
+  ],
+  include_directories : [inc_freedreno, inc_include, inc_src],
+  c_args : [no_override_init_args, soong_compat_c_args],
+  build_by_default : false,
+  dependencies: [idep_mesautil],
+  gnu_symbol_visibility : 'hidden',
+)
+
+idep_libfreedreno_common = declare_dependency(
+  link_with: [libfreedreno_common],
+  include_directories : [inc_freedreno, inc_include, inc_src],
+)

src/freedreno/common/msm_proto.h

@@ -0,0 +1,316 @@
+/*
+ * Copyright 2022 Google LLC
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef MSM_PROTO_H_
+#define MSM_PROTO_H_
+
+/**
+ * General protocol notes:
+ * 1) Request (req) messages are generally sent over DRM_VIRTGPU_EXECBUFFER
+ *    but can also be sent via DRM_VIRTGPU_RESOURCE_CREATE_BLOB (in which
+ *    case they are processed by the host before ctx->get_blob())
+ * 2) Response (rsp) messages are returned via shmem->rsp_mem, at an offset
+ *    specified by the guest in the req message.  Not all req messages have
+ *    a rsp.
+ * 3) Host and guest could have different pointer sizes, ie. 32b guest and
+ *    64b host, or visa versa, so similar to kernel uabi, req and rsp msgs
+ *    should be explicitly padded to avoid 32b vs 64b struct padding issues
+ */
+
+/**
+ * Defines the layout of shmem buffer used for host->guest communication.
+ */
+struct msm_shmem {
+   struct vdrm_shmem base;
+
+   /**
+    * Counter that is incremented on asynchronous errors, like SUBMIT
+    * or GEM_NEW failures.  The guest should treat errors as context-
+    * lost.
+    */
+   uint32_t async_error;
+
+   /**
+    * Counter that is incremented on global fault (see MSM_PARAM_FAULTS)
+    */
+   uint32_t global_faults;
+};
+DEFINE_CAST(vdrm_shmem, msm_shmem)
+
+/*
+ * Possible cmd types for "command stream", ie. payload of EXECBUF ioctl:
+ */
+enum msm_ccmd {
+   MSM_CCMD_NOP = 1,         /* No payload, can be used to sync with host */
+   MSM_CCMD_IOCTL_SIMPLE,
+   MSM_CCMD_GEM_NEW,
+   MSM_CCMD_GEM_SET_IOVA,
+   MSM_CCMD_GEM_CPU_PREP,
+   MSM_CCMD_GEM_SET_NAME,
+   MSM_CCMD_GEM_SUBMIT,
+   MSM_CCMD_GEM_UPLOAD,
+   MSM_CCMD_SUBMITQUEUE_QUERY,
+   MSM_CCMD_WAIT_FENCE,
+   MSM_CCMD_SET_DEBUGINFO,
+   MSM_CCMD_LAST,
+};
+
+#ifdef __cplusplus
+#define MSM_CCMD(_cmd, _len) {                      \
+       .cmd = MSM_CCMD_##_cmd,                      \
+       .len = (_len),                               \
+   }
+#else
+#define MSM_CCMD(_cmd, _len) (struct vdrm_ccmd_req){ \
+       .cmd = MSM_CCMD_##_cmd,                      \
+       .len = (_len),                               \
+   }
+#endif
+
+/*
+ * MSM_CCMD_NOP
+ */
+struct msm_ccmd_nop_req {
+   struct vdrm_ccmd_req hdr;
+};
+
+/*
+ * MSM_CCMD_IOCTL_SIMPLE
+ *
+ * Forward simple/flat IOC_RW or IOC_W ioctls.  Limited ioctls are supported.
+ */
+struct msm_ccmd_ioctl_simple_req {
+   struct vdrm_ccmd_req hdr;
+
+   uint32_t cmd;
+   uint8_t payload[];
+};
+DEFINE_CAST(vdrm_ccmd_req, msm_ccmd_ioctl_simple_req)
+
+struct msm_ccmd_ioctl_simple_rsp {
+   struct vdrm_ccmd_rsp hdr;
+
+   /* ioctl return value, interrupted syscalls are handled on the host without
+    * returning to the guest.
+    */
+   int32_t ret;
+
+   /* The output payload for IOC_RW ioctls, the payload is the same size as
+    * msm_context_cmd_ioctl_simple_req.
+    *
+    * For IOC_W ioctls (userspace writes, kernel reads) this is zero length.
+    */
+   uint8_t payload[];
+};
+
+/*
+ * MSM_CCMD_GEM_NEW
+ *
+ * GEM buffer allocation, maps to DRM_MSM_GEM_NEW plus DRM_MSM_GEM_INFO to
+ * set the BO's iova (to avoid extra guest -> host trip)
+ *
+ * No response.
+ */
+struct msm_ccmd_gem_new_req {
+   struct vdrm_ccmd_req hdr;
+
+   uint64_t iova;
+   uint64_t size;
+   uint32_t flags;
+   uint32_t blob_id;
+};
+DEFINE_CAST(vdrm_ccmd_req, msm_ccmd_gem_new_req)
+
+/*
+ * MSM_CCMD_GEM_SET_IOVA
+ *
+ * Set the buffer iova (for imported BOs).  Also used to release the iova
+ * (by setting it to zero) when a BO is freed.
+ */
+struct msm_ccmd_gem_set_iova_req {
+   struct vdrm_ccmd_req hdr;
+
+   uint64_t iova;
+   uint32_t res_id;
+};
+DEFINE_CAST(vdrm_ccmd_req, msm_ccmd_gem_set_iova_req)
+
+/*
+ * MSM_CCMD_GEM_CPU_PREP
+ *
+ * Maps to DRM_MSM_GEM_CPU_PREP
+ *
+ * Note: Since we don't want to block the single threaded host, this returns
+ * immediately with -EBUSY if the fence is not yet signaled.  The guest
+ * should poll if needed.
+ */
+struct msm_ccmd_gem_cpu_prep_req {
+   struct vdrm_ccmd_req hdr;
+
+   uint32_t res_id;
+   uint32_t op;
+};
+DEFINE_CAST(vdrm_ccmd_req, msm_ccmd_gem_cpu_prep_req)
+
+struct msm_ccmd_gem_cpu_prep_rsp {
+   struct vdrm_ccmd_rsp hdr;
+
+   int32_t ret;
+};
+
+/*
+ * MSM_CCMD_GEM_SET_NAME
+ *
+ * Maps to DRM_MSM_GEM_INFO:MSM_INFO_SET_NAME
+ *
+ * No response.
+ */
+struct msm_ccmd_gem_set_name_req {
+   struct vdrm_ccmd_req hdr;
+
+   uint32_t res_id;
+   /* Note: packet size aligned to 4 bytes, so the string name may
+    * be shorter than the packet header indicates.
+    */
+   uint32_t len;
+   uint8_t  payload[];
+};
+DEFINE_CAST(vdrm_ccmd_req, msm_ccmd_gem_set_name_req)
+
+/*
+ * MSM_CCMD_GEM_SUBMIT
+ *
+ * Maps to DRM_MSM_GEM_SUBMIT
+ *
+ * The actual for-reals cmdstream submission.  Note this intentionally
+ * does not support relocs, since we already require a non-ancient
+ * kernel.
+ *
+ * Note, no in/out fence-fd, that synchronization is handled on guest
+ * kernel side (ugg).. need to come up with a better story for fencing.
+ * We probably need to sort something out for that to handle syncobjs.
+ *
+ * No response.
+ */
+struct msm_ccmd_gem_submit_req {
+   struct vdrm_ccmd_req hdr;
+
+   uint32_t flags;
+   uint32_t queue_id;
+   uint32_t nr_bos;
+   uint32_t nr_cmds;
+
+   /**
+    * The fence "seqno" assigned by the guest userspace.  The host SUBMIT
+    * ioctl uses the MSM_SUBMIT_FENCE_SN_IN flag to let the guest assign
+    * the sequence #, to avoid the guest needing to wait for a response
+    * from the host.
+    */
+   uint32_t fence;
+
+   /**
+    * Payload is first an array of 'struct drm_msm_gem_submit_bo' of
+    * length determined by nr_bos (note that handles are guest resource
+    * ids which are translated to host GEM handles by the host VMM),
+    * followed by an array of 'struct drm_msm_gem_submit_cmd' of length
+    * determined by nr_cmds
+    */
+   int8_t   payload[];
+};
+DEFINE_CAST(vdrm_ccmd_req, msm_ccmd_gem_submit_req)
+
+/*
+ * MSM_CCMD_GEM_UPLOAD
+ *
+ * Upload data to a GEM buffer
+ *
+ * No response.
+ */
+struct msm_ccmd_gem_upload_req {
+   struct vdrm_ccmd_req hdr;
+
+   uint32_t res_id;
+   uint32_t pad;
+   uint32_t off;
+
+   /* Note: packet size aligned to 4 bytes, so the payload may
+    * be shorter than the packet header indicates.
+    */
+   uint32_t len;
+   uint8_t  payload[];
+};
+DEFINE_CAST(vdrm_ccmd_req, msm_ccmd_gem_upload_req)
+
+/*
+ * MSM_CCMD_SUBMITQUEUE_QUERY
+ *
+ * Maps to DRM_MSM_SUBMITQUEUE_QUERY
+ */
+struct msm_ccmd_submitqueue_query_req {
+   struct vdrm_ccmd_req hdr;
+
+   uint32_t queue_id;
+   uint32_t param;
+   uint32_t len;   /* size of payload in rsp */
+};
+DEFINE_CAST(vdrm_ccmd_req, msm_ccmd_submitqueue_query_req)
+
+struct msm_ccmd_submitqueue_query_rsp {
+   struct vdrm_ccmd_rsp hdr;
+
+   int32_t  ret;
+   uint32_t out_len;
+   uint8_t  payload[];
+};
+
+/*
+ * MSM_CCMD_WAIT_FENCE
+ *
+ * Maps to DRM_MSM_WAIT_FENCE
+ *
+ * Note: Since we don't want to block the single threaded host, this returns
+ * immediately with -ETIMEDOUT if the fence is not yet signaled.  The guest
+ * should poll if needed.
+ */
+struct msm_ccmd_wait_fence_req {
+   struct vdrm_ccmd_req hdr;
+
+   uint32_t queue_id;
+   uint32_t fence;
+};
+DEFINE_CAST(vdrm_ccmd_req, msm_ccmd_wait_fence_req)
+
+struct msm_ccmd_wait_fence_rsp {
+   struct vdrm_ccmd_rsp hdr;
+
+   int32_t ret;
+};
+
+/*
+ * MSM_CCMD_SET_DEBUGINFO
+ *
+ * Set per-guest-process debug info (comm and cmdline).  For GPU faults/
+ * crashes, it isn't too useful to see the crosvm (for ex.) comm/cmdline,
+ * since the host process is only a proxy.  This allows the guest to
+ * pass through the guest process comm and commandline for debugging
+ * purposes.
+ *
+ * No response.
+ */
+struct msm_ccmd_set_debuginfo_req {
+   struct vdrm_ccmd_req hdr;
+
+   uint32_t comm_len;
+   uint32_t cmdline_len;
+
+   /**
+    * Payload is first the comm string followed by cmdline string, padded
+    * out to a multiple of 4.
+    */
+   int8_t   payload[];
+};
+DEFINE_CAST(vdrm_ccmd_req, msm_ccmd_set_debuginfo_req)
+
+#endif /* MSM_PROTO_H_ */

src/freedreno/common/redump.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright © 2012 Rob Clark <[email protected]>
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef REDUMP_H_
+#define REDUMP_H_
+
+#include <unistd.h>
+
+enum rd_sect_type {
+   RD_NONE,
+   RD_TEST,           /* ascii text */
+   RD_CMD,            /* ascii text */
+   RD_GPUADDR,        /* u32 gpuaddr, u32 size */
+   RD_CONTEXT,        /* raw dump */
+   RD_CMDSTREAM,      /* raw dump */
+   RD_CMDSTREAM_ADDR, /* gpu addr of cmdstream */
+   RD_PARAM,          /* u32 param_type, u32 param_val, u32 bitlen */
+   RD_FLUSH,          /* empty, clear previous params */
+   RD_PROGRAM,        /* shader program, raw dump */
+   RD_VERT_SHADER,
+   RD_FRAG_SHADER,
+   RD_BUFFER_CONTENTS,
+   RD_GPU_ID,
+   RD_CHIP_ID,
+   RD_SHADER_LOG_BUFFER, /* Specifies buffer which has logs from shaders */
+   RD_CP_LOG_BUFFER, /* Specifies buffer which has logs from CP */
+   RD_WRBUFFER,     /* Specifies buffer which has data that needs to be written out to a file */
+};
+
+/* RD_PARAM types: */
+enum rd_param_type {
+   RD_PARAM_SURFACE_WIDTH,
+   RD_PARAM_SURFACE_HEIGHT,
+   RD_PARAM_SURFACE_PITCH,
+   RD_PARAM_COLOR,
+   RD_PARAM_BLIT_X,
+   RD_PARAM_BLIT_Y,
+   RD_PARAM_BLIT_WIDTH,
+   RD_PARAM_BLIT_HEIGHT,
+   RD_PARAM_BLIT_X2, /* BLIT_X + BLIT_WIDTH */
+   RD_PARAM_BLIT_Y2, /* BLIT_Y + BLIT_WIDTH */
+};
+
+static inline void
+rd_write_section(int fd, enum rd_sect_type type, const void *buf, int sz)
+{
+   write(fd, &type, 4);
+   write(fd, &sz, 4);
+   write(fd, buf, sz);
+}
+
+#endif /* REDUMP_H_ */

src/freedreno/computerator/README.rst

@@ -0,0 +1,55 @@
+Overview
+========
+
+Computerator is a tool to launch compute shaders, written in assembly.
+The main purpose is to have an easy way to experiment with instructions
+without dealing with the entire compiler stack (which makes controlling
+the order of instructions, the registers chosen, etc, difficult).  The
+choice of compute shaders is simply because there is far less state
+setup required.
+
+Headers
+-------
+
+The shader assembly can be prefixed with headers to control state setup:
+
+* ``@localsize X, Y, Z`` - configures local workgroup size
+* ``@buf SZ (cN.c)`` - configures an SSBO of the specified size (in dwords).
+  The order of the ``@buf`` headers determines the index, ie the first
+  ``@buf`` header is ``g[0]``, the second ``g[1]``, and so on.
+  The iova of the buffer is written as a vec2 to ``cN.c``
+* ``@const(cN.c)`` configures a const vec4 starting at specified
+  const register, ie ``@const(c1.x) 1.0, 2.0, 3.0, 4.0`` will populate
+  ``c1.xyzw`` with ``vec4(1.0, 2.0, 3.0, 4.0)``
+* ``@invocationid(rN.c)`` will populate a vec3 starting at the specified
+  register with the local invocation-id
+* ``@wgid(rN.c)`` will populate a vec3 starting at the specified register
+  with the workgroup-id (must be a high-reg, ie. ``r48.x`` and above)
+* ``@numwg(cN.c)`` will populate a vec3 starting at the specified const
+  register
+
+Example
+-------
+
+```
+@localsize 32, 1, 1
+@buf 32  ; g[0]
+@const(c0.x)  0.0, 0.0, 0.0, 0.0
+@const(c1.x)  1.0, 2.0, 3.0, 4.0
+@wgid(r48.x)        ; r48.xyz
+@invocationid(r0.x) ; r0.xyz
+@numwg(c2.x)        ; c2.xyz
+mov.u32u32 r0.y, r0.x
+(rpt5)nop
+stib.untyped.1d.u32.1 g[0] + r0.y, r0.x
+end
+nop
+```
+
+Usage
+-----
+
+```
+cat myshader.asm | ./computerator --disasm --groups=4,4,4
+```
+

src/freedreno/computerator/a4xx.cc

@@ -0,0 +1,352 @@
+/*
+ * Copyright © 2021 Ilia Mirkin
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "ir3/ir3_compiler.h"
+
+#include "util/u_math.h"
+#include "util/u_queue.h"
+
+#include "common/fd4_hw.h"
+#include "ir3_asm.h"
+#include "main.h"
+
+struct a4xx_backend {
+   struct backend base;
+
+   struct ir3_compiler *compiler;
+   struct fd_device *dev;
+};
+define_cast(backend, a4xx_backend);
+
+/*
+ * Backend implementation:
+ */
+
+static struct kernel *
+a4xx_assemble(struct backend *b, FILE *in)
+{
+   struct a4xx_backend *a4xx_backend = to_a4xx_backend(b);
+   struct ir3_kernel *ir3_kernel = ir3_asm_assemble(a4xx_backend->compiler, in);
+   ir3_kernel->backend = b;
+   return &ir3_kernel->base;
+}
+
+static void
+a4xx_disassemble(struct kernel *kernel, struct ir3_disasm_options *options)
+{
+   ir3_asm_disassemble(to_ir3_kernel(kernel), options);
+}
+
+static void
+cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
+{
+   struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
+   struct ir3_shader_variant *v = ir3_kernel->v;
+   const struct ir3_info *i = &v->info;
+   enum a3xx_threadsize thrsz = i->double_threadsize ? FOUR_QUADS : TWO_QUADS;
+
+   OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
+   OUT_RING(ring, 0x00000000);
+   OUT_RING(ring, 0x00000012);
+
+   OUT_WFI(ring);
+
+   OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
+   OUT_RING(ring, 0x0000001e);
+
+   OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
+   OUT_RING(ring, 0x00000038);
+
+   OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
+   OUT_RING(ring, 0x00000000);
+
+   OUT_WFI(ring);
+
+   OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
+   OUT_RING(ring, 0x00000003);
+
+   OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 1);
+   OUT_RING(ring, 0x080005f0);
+
+   OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
+   OUT_RING(ring, 0x00000038);
+
+   OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
+   OUT_RING(ring, 0x00860010);
+   // OUT_RING(ring, 0x00920000);
+
+   OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
+   OUT_RING(ring, 0x000004ff);
+   // OUT_RING(ring, 0x00000260);
+
+   OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG1, 1);
+   OUT_RING(ring, 0x80000000);
+
+   OUT_PKT0(ring, REG_A4XX_SP_CS_CTRL_REG0, 1);
+   OUT_RING(ring,
+            A4XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
+            A4XX_SP_CS_CTRL_REG0_SUPERTHREADMODE |
+            A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
+            A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1));
+
+   OUT_PKT0(ring, REG_A4XX_HLSQ_CS_CONTROL_REG, 1);
+   OUT_RING(ring, A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(0) |
+                     A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(0) |
+                     A4XX_HLSQ_CS_CONTROL_REG_ENABLED |
+                     A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(1) |
+                     COND(v->has_ssbo, A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE) |
+                     A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(v->constlen / 4));
+
+   OUT_PKT0(ring, REG_A4XX_SP_CS_OBJ_START, 1);
+   OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START */
+
+   OUT_PKT0(ring, REG_A4XX_SP_CS_LENGTH_REG, 1);
+   OUT_RING(ring, v->instrlen);
+
+   uint32_t local_invocation_id, work_group_id, num_wg_id;
+   local_invocation_id =
+      ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
+   work_group_id = ir3_kernel->info.wgid;
+   num_wg_id = ir3_kernel->info.numwg;
+
+   OUT_PKT0(ring, REG_A4XX_HLSQ_CL_CONTROL_0, 2);
+   OUT_RING(ring, A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(work_group_id) |
+                     A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(regid(63, 0)) |
+                     A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(local_invocation_id));
+   OUT_RING(ring, A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(regid(63, 0)) |
+                     A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(regid(63, 0)));
+
+   OUT_PKT0(ring, REG_A4XX_HLSQ_CL_KERNEL_CONST, 1);
+   OUT_RING(ring, A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(regid(63, 0)) |
+                     A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID(num_wg_id));
+
+   OUT_PKT0(ring, REG_A4XX_HLSQ_CL_WG_OFFSET, 1);
+   OUT_RING(ring, A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(regid(63, 0)));
+
+   OUT_PKT3(ring, CP_LOAD_STATE4, 2);
+   OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
+                     CP_LOAD_STATE4_0_STATE_SRC(SS4_INDIRECT) |
+                     CP_LOAD_STATE4_0_STATE_BLOCK(SB4_CS_SHADER) |
+                     CP_LOAD_STATE4_0_NUM_UNIT(v->instrlen));
+   OUT_RELOC(ring, v->bo, 0, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
+}
+
+static void
+emit_const(struct fd_ringbuffer *ring, struct kernel *kernel, uint32_t constid, uint32_t sizedwords,
+           const uint32_t *dwords)
+{
+   uint32_t align_sz;
+
+   assert((constid % 4) == 0);
+
+   /* Overwrite appropriate entries with buffer addresses */
+   struct fd_bo **replacements =
+      (struct fd_bo **)calloc(sizedwords, sizeof(struct fd_bo *));
+   for (int i = 0; i < MAX_BUFS; i++) {
+      if (kernel->buf_addr_regs[i] != INVALID_REG) {
+         int idx = kernel->buf_addr_regs[i];
+         assert(idx < sizedwords);
+
+         replacements[idx] = kernel->bufs[i];
+      }
+   }
+
+   align_sz = align(sizedwords, 4);
+
+   OUT_PKT3(ring, CP_LOAD_STATE4, 2 + align_sz);
+   OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(constid / 4) |
+                     CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
+                     CP_LOAD_STATE4_0_STATE_BLOCK(SB4_CS_SHADER) |
+                     CP_LOAD_STATE4_0_NUM_UNIT(DIV_ROUND_UP(sizedwords, 4)));
+   OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
+                     CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
+   for (unsigned i = 0; i < sizedwords; i++) {
+      if (replacements[i])
+         OUT_RELOC(ring, replacements[i], 0, 0, 0);
+      else
+         OUT_RING(ring, dwords[i]);
+   }
+
+   /* Zero-pad to multiple of 4 dwords */
+   for (uint32_t i = sizedwords; i < align_sz; i++) {
+      OUT_RING(ring, 0);
+   }
+
+   free(replacements);
+}
+
+static void
+cs_const_emit(struct fd_ringbuffer *ring, struct kernel *kernel,
+              uint32_t grid[3])
+{
+   struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
+   struct ir3_shader_variant *v = ir3_kernel->v;
+
+   const struct ir3_const_state *const_state = ir3_const_state(v);
+   uint32_t base = const_state->allocs.max_const_offset_vec4;
+   const struct ir3_imm_const_state *imm_state = &v->imm_state;
+   int size = DIV_ROUND_UP(imm_state->count, 4);
+
+   /* truncate size to avoid writing constants that shader
+    * does not use:
+    */
+   size = MIN2(size + base, v->constlen) - base;
+
+   /* convert out of vec4: */
+   base *= 4;
+   size *= 4;
+
+   if (size > 0) {
+      emit_const(ring, kernel, base, size, imm_state->values);
+   }
+}
+
+static void
+cs_ibo_emit(struct fd_ringbuffer *ring, struct fd_submit *submit,
+            struct kernel *kernel)
+{
+   OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (4 * kernel->num_bufs));
+   OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
+         CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
+         CP_LOAD_STATE4_0_STATE_BLOCK(SB4_CS_SSBO) |
+         CP_LOAD_STATE4_0_NUM_UNIT(kernel->num_bufs));
+   OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
+         CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
+   for (unsigned i = 0; i < kernel->num_bufs; i++) {
+      OUT_RELOC(ring, kernel->bufs[i], 0, 0, 0);
+#if 1
+      OUT_RING(ring, 0);
+      OUT_RING(ring, 0);
+      OUT_RING(ring, 0);
+#else
+      OUT_RING(ring, kernel->buf_sizes[i]);
+      OUT_RING(ring, kernel->buf_sizes[i]);
+      OUT_RING(ring, 0x00000004);
+#endif
+   }
+
+   OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * kernel->num_bufs));
+   OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
+         CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
+         CP_LOAD_STATE4_0_STATE_BLOCK(SB4_CS_SSBO) |
+         CP_LOAD_STATE4_0_NUM_UNIT(kernel->num_bufs));
+   OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
+         CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
+   for (unsigned i = 0; i < kernel->num_bufs; i++) {
+      unsigned sz = kernel->buf_sizes[i];
+
+      /* width is in dwords, overflows into height: */
+      sz /= 4;
+
+#if 1
+      OUT_RING(ring, A4XX_SSBO_1_0_WIDTH(sz));
+      OUT_RING(ring, A4XX_SSBO_1_1_HEIGHT(sz >> 16));
+#else
+      OUT_RING(ring, A4XX_SSBO_1_0_WIDTH(sz) |
+            A4XX_SSBO_1_0_FMT(RB4_R32_UINT) |
+            A4XX_SSBO_1_0_CPP(4));
+      OUT_RING(ring, A4XX_SSBO_1_1_HEIGHT(DIV_ROUND_UP(sz, 1 << 16)) |
+            A4XX_SSBO_1_1_DEPTH(1));
+#endif
+   }
+}
+
+static void
+a4xx_emit_grid(struct kernel *kernel, uint32_t grid[3],
+               struct fd_submit *submit)
+{
+   struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
+      submit, 0,
+      (enum fd_ringbuffer_flags)(FD_RINGBUFFER_PRIMARY | FD_RINGBUFFER_GROWABLE));
+
+   cs_program_emit(ring, kernel);
+   cs_const_emit(ring, kernel, grid);
+   cs_ibo_emit(ring, submit, kernel);
+
+   const unsigned *local_size = kernel->local_size;
+   const unsigned *num_groups = grid;
+
+   unsigned work_dim = 0;
+   for (int i = 0; i < 3; i++) {
+      if (!grid[i])
+         break;
+      work_dim++;
+   }
+
+   OUT_PKT0(ring, REG_A4XX_HLSQ_CL_NDRANGE_0, 7);
+   OUT_RING(ring, A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(work_dim) |
+                     A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
+                     A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
+                     A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
+   OUT_RING(ring,
+            A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(local_size[0] * num_groups[0]));
+   OUT_RING(ring, 0); /* HLSQ_CL_NDRANGE_2_GLOBALOFF_X */
+   OUT_RING(ring,
+            A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(local_size[1] * num_groups[1]));
+   OUT_RING(ring, 0); /* HLSQ_CL_NDRANGE_4_GLOBALOFF_Y */
+   OUT_RING(ring,
+            A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(local_size[2] * num_groups[2]));
+   OUT_RING(ring, 0); /* HLSQ_CL_NDRANGE_6_GLOBALOFF_Z */
+
+#if 1
+   OUT_PKT3(ring, CP_EXEC_CS, 4);
+   OUT_RING(ring, 0x00000000);
+   OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(grid[0]));
+   OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(grid[1]));
+   OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(grid[2]));
+#else
+   OUT_PKT0(ring, REG_A4XX_HLSQ_CL_KERNEL_GROUP_X, 3);
+   OUT_RING(ring, grid[0]); /* HLSQ_CL_KERNEL_GROUP_X */
+   OUT_RING(ring, grid[1]); /* HLSQ_CL_KERNEL_GROUP_Y */
+   OUT_RING(ring, grid[2]); /* HLSQ_CL_KERNEL_GROUP_Z */
+
+   OUT_PKT3(ring, CP_RUN_OPENCL, 1);
+   OUT_RING(ring, 0);
+#endif
+
+   OUT_WFI(ring);
+
+   /* TODO: cache_flush */
+}
+
+struct backend *
+a4xx_init(struct fd_device *dev, const struct fd_dev_id *dev_id)
+{
+   struct a4xx_backend *a4xx_backend =
+      (struct a4xx_backend *)calloc(1, sizeof(*a4xx_backend));
+
+   a4xx_backend->base = (struct backend){
+      .assemble = a4xx_assemble,
+      .disassemble = a4xx_disassemble,
+      .emit_grid = a4xx_emit_grid,
+   };
+
+   struct ir3_compiler_options compiler_options = {
+      .disable_cache = true,
+   };
+   a4xx_backend->compiler =
+      ir3_compiler_create(dev, dev_id, fd_dev_info_raw(dev_id), &compiler_options);
+   a4xx_backend->dev = dev;
+
+   return &a4xx_backend->base;
+}

src/freedreno/computerator/a6xx.cc

@@ -0,0 +1,720 @@
+/*
+ * Copyright © 2020 Google, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "ir3/ir3_compiler.h"
+
+#include "util/u_math.h"
+
+#include "fd6_hw.h"
+
+#include "common/freedreno_dev_info.h"
+#include "fdl/freedreno_layout.h"
+
+#include "ir3_asm.h"
+#include "main.h"
+
+#define FD_BO_NO_HARDPIN 1
+#include "common/fd6_pack.h"
+
+struct a6xx_backend {
+   struct backend base;
+
+   struct ir3_compiler *compiler;
+   struct fd_device *dev;
+
+   const struct fd_dev_info *info;
+
+   unsigned seqno;
+   struct fd_bo *control_mem;
+
+   struct fd_bo *query_mem;
+   const struct perfcntr *perfcntrs;
+   unsigned num_perfcntrs;
+};
+define_cast(backend, a6xx_backend);
+
+/*
+ * Data structures shared with GPU:
+ */
+
+/* This struct defines the layout of the fd6_context::control buffer: */
+struct fd6_control {
+   uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
+   uint32_t _pad0;
+   volatile uint32_t vsc_overflow;
+   uint32_t _pad1;
+   /* flag set from cmdstream when VSC overflow detected: */
+   uint32_t vsc_scratch;
+   uint32_t _pad2;
+   uint32_t _pad3;
+   uint32_t _pad4;
+
+   /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
+   struct {
+      uint32_t offset;
+      uint32_t pad[7];
+   } flush_base[4];
+};
+
+#define control_ptr(a6xx_backend, member)                                      \
+   (a6xx_backend)->control_mem, offsetof(struct fd6_control, member)
+
+struct PACKED fd6_query_sample {
+   uint64_t start;
+   uint64_t result;
+   uint64_t stop;
+};
+
+/* offset of a single field of an array of fd6_query_sample: */
+#define query_sample_idx(a6xx_backend, idx, field)                             \
+   (a6xx_backend)->query_mem,                                                  \
+      (idx * sizeof(struct fd6_query_sample)) +                                \
+         offsetof(struct fd6_query_sample, field)
+
+/*
+ * Backend implementation:
+ */
+
+static struct kernel *
+a6xx_assemble(struct backend *b, FILE *in)
+{
+   struct a6xx_backend *a6xx_backend = to_a6xx_backend(b);
+   struct ir3_kernel *ir3_kernel = ir3_asm_assemble(a6xx_backend->compiler, in);
+   ir3_kernel->backend = b;
+   return &ir3_kernel->base;
+}
+
+static void
+a6xx_disassemble(struct kernel *kernel, struct ir3_disasm_options *options)
+{
+   ir3_asm_disassemble(to_ir3_kernel(kernel), options);
+}
+
+template<chip CHIP>
+static void
+cs_restore_emit(fd_cs &cs, struct a6xx_backend *a6xx_backend)
+{
+   fd_ncrb<CHIP> ncrb(cs, 2 + ARRAY_SIZE(a6xx_backend->info->magic_raw));
+
+   ncrb.add(A6XX_SP_PERFCTR_SHADER_MASK(.cs = true));
+
+   /* KMD programs this (and blocks UMD access) on gen8+: */
+   if (CHIP < A8XX)
+      ncrb.add(A6XX_SP_NC_MODE_CNTL_2());
+
+   for (size_t i = 0; i < ARRAY_SIZE(a6xx_backend->info->magic_raw); i++) {
+      auto magic_reg = a6xx_backend->info->magic_raw[i];
+      if (!magic_reg.reg)
+         break;
+
+      ncrb.add({magic_reg.reg, magic_reg.value});
+   }
+}
+
+template<chip CHIP>
+static void
+cs_program_emit_regs(fd_cs &cs, struct kernel *kernel)
+{
+   struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
+   struct a6xx_backend *a6xx_backend = to_a6xx_backend(ir3_kernel->backend);
+   struct ir3_shader_variant *v = ir3_kernel->v;
+   const unsigned *local_size = kernel->local_size;
+   const struct ir3_info *i = &v->info;
+   enum a6xx_threadsize thrsz = i->double_threadsize ? THREAD128 : THREAD64;
+   fd_crb crb(cs, 25);
+
+   crb.add(A6XX_SP_MODE_CNTL(
+      .constant_demotion_enable = true,
+      .isammode = ISAMMODE_GL,
+      .shared_consts_enable = false,
+   ));
+
+   crb.add(SP_UPDATE_CNTL(CHIP,
+      .vs_state = true,
+      .hs_state = true,
+      .ds_state = true,
+      .gs_state = true,
+      .fs_state = true,
+      .cs_state = true,
+      .gfx_uav = true,
+   ));
+
+   unsigned constlen = align(v->constlen, 4);
+   crb.add(SP_CS_CONST_CONFIG(CHIP, .constlen = constlen, .enabled = true, ));
+
+   crb.add(A6XX_SP_CS_CONFIG(
+      .enabled = true,
+      .ntex = v->num_samp,
+      .nsamp = v->num_samp,
+      .nuav = kernel->num_bufs,
+   ));
+   crb.add(A6XX_SP_CS_INSTR_SIZE(v->instrlen));
+
+   crb.add(A6XX_SP_CS_CNTL_0(
+      .halfregfootprint = i->max_half_reg + 1,
+      .fullregfootprint = i->max_reg + 1,
+      .branchstack = ir3_shader_branchstack_hw(v),
+      .threadsize = thrsz,
+      .earlypreamble = v->early_preamble,
+      .mergedregs = v->mergedregs,
+   ));
+
+   if (CHIP >= A7XX) {
+      crb.add(SP_PS_WAVE_CNTL(CHIP, .threadsize = THREAD64));
+
+      crb.add(SP_REG_PROG_ID_0(CHIP, .dword = 0xfcfcfcfc));
+      crb.add(SP_REG_PROG_ID_1(CHIP, .dword = 0xfcfcfcfc));
+      crb.add(SP_REG_PROG_ID_2(CHIP, .dword = 0xfcfcfcfc));
+      crb.add(SP_REG_PROG_ID_3(CHIP, .dword = 0x0000fc00));
+   }
+
+   uint32_t shared_size = MAX2(((int)v->shared_size - 1) / 1024, 1);
+   enum a6xx_const_ram_mode mode =
+      v->constlen > 256 ? CONSTLEN_512 :
+      (v->constlen > 192 ? CONSTLEN_256 :
+      (v->constlen > 128 ? CONSTLEN_192 : CONSTLEN_128));
+   crb.add(A6XX_SP_CS_CNTL_1(.shared_size = shared_size, .constantrammode = mode));
+
+   if (CHIP == A6XX && a6xx_backend->info->props.has_lpac) {
+      crb.add(HLSQ_CS_CTRL_REG1(CHIP, .shared_size = 1, .constantrammode = mode));
+   }
+
+   uint32_t local_invocation_id, work_group_id;
+   local_invocation_id =
+      ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
+   work_group_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_WORKGROUP_ID);
+
+   if (CHIP == A6XX) {
+      crb.add(SP_CS_CONST_CONFIG_0(CHIP,
+         .wgidconstid = work_group_id,
+         .wgsizeconstid = INVALID_REG,
+         .wgoffsetconstid = INVALID_REG,
+         .localidregid = local_invocation_id,
+      ));
+      crb.add(SP_CS_WGE_CNTL(CHIP,
+         .linearlocalidregid = INVALID_REG,
+         .threadsize = thrsz,
+      ));
+   } else {
+      unsigned tile_height = (local_size[1] % 8 == 0)   ? 3
+                             : (local_size[1] % 4 == 0) ? 5
+                             : (local_size[1] % 2 == 0) ? 9
+                                                        : 17;
+
+      crb.add(SP_CS_WGE_CNTL(CHIP,
+         .linearlocalidregid = INVALID_REG,
+         .threadsize = thrsz,
+         .workgrouprastorderzfirsten = true,
+         .wgtilewidth = 4,
+         .wgtileheight = tile_height,
+      ));
+   }
+
+   if (CHIP >= A7XX || a6xx_backend->info->props.has_lpac) {
+      crb.add(A6XX_SP_CS_WIE_CNTL_0(
+         .wgidconstid = work_group_id,
+         .wgsizeconstid = INVALID_REG,
+         .wgoffsetconstid = INVALID_REG,
+         .localidregid = local_invocation_id,
+      ));
+
+      if (CHIP >= A7XX) {
+         /* TODO allow the shader to control the tiling */
+         crb.add(SP_CS_WIE_CNTL_1(CHIP,
+            .linearlocalidregid = INVALID_REG,
+            .threadsize = thrsz,
+            .workitemrastorder = WORKITEMRASTORDER_LINEAR,
+         ));
+      } else {
+         crb.add(SP_CS_WIE_CNTL_1(CHIP,
+            .linearlocalidregid = INVALID_REG,
+            .threadsize = thrsz,
+         ));
+      }
+   }
+
+   crb.attach_bo(v->bo);
+
+   crb.add(A6XX_SP_CS_BASE(v->bo));
+   crb.add(A6XX_SP_CS_INSTR_SIZE(v->instrlen));
+
+   if (v->pvtmem_size > 0) {
+      uint32_t per_fiber_size = v->pvtmem_size;
+      uint32_t per_sp_size =
+         align(per_fiber_size * a6xx_backend->info->fibers_per_sp, 1 << 12);
+      uint32_t total_size = per_sp_size * a6xx_backend->info->num_sp_cores;
+
+      struct fd_bo *pvtmem = fd_bo_new(a6xx_backend->dev, total_size, 0, "pvtmem");
+      crb.add(A6XX_SP_CS_PVT_MEM_PARAM(.memsizeperitem = per_fiber_size));
+      crb.add(A6XX_SP_CS_PVT_MEM_BASE(pvtmem));
+      crb.add(A6XX_SP_CS_PVT_MEM_SIZE(
+         .totalpvtmemsize = per_sp_size,
+         .perwavememlayout = v->pvtmem_per_wave,
+      ));
+
+      crb.add(A6XX_SP_CS_PVT_MEM_STACK_OFFSET(.offset = per_sp_size));
+   }
+}
+
+template<chip CHIP>
+static void
+cs_program_emit(fd_cs &cs, struct kernel *kernel)
+{
+   struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
+   struct a6xx_backend *a6xx_backend = to_a6xx_backend(ir3_kernel->backend);
+   struct ir3_shader_variant *v = ir3_kernel->v;
+
+   cs_program_emit_regs<CHIP>(cs, kernel);
+
+   uint32_t shader_preload_size =
+      MIN2(v->instrlen, a6xx_backend->info->props.instr_cache_size);
+
+   fd_pkt7(cs, CP_LOAD_STATE6_FRAG, 3)
+      .add(CP_LOAD_STATE6_0(
+         .state_type = ST6_SHADER,
+         .state_src = SS6_INDIRECT,
+         .state_block = SB6_CS_SHADER,
+         .num_unit = shader_preload_size,
+      ))
+      .add(CP_LOAD_STATE6_EXT_SRC_ADDR(v->bo));
+}
+
+template<chip CHIP>
+static void
+emit_const(fd_cs &cs, uint32_t regid, uint32_t sizedwords, const uint32_t *dwords)
+{
+   uint32_t zero[4] = {};
+   uint32_t align_sz;
+
+   assert((regid % 4) == 0);
+
+   align_sz = align(sizedwords, 4);
+
+   fd_pkt7(cs, CP_LOAD_STATE6_FRAG, 3 + align_sz)
+      .add(CP_LOAD_STATE6_0(
+         .dst_off = regid / 4,
+         .state_type = ST6_CONSTANTS,
+         .state_src = SS6_DIRECT,
+         .state_block = SB6_CS_SHADER,
+         .num_unit = DIV_ROUND_UP(sizedwords, 4)
+      ))
+      .add(CP_LOAD_STATE6_EXT_SRC_ADDR())
+      .add(dwords, sizedwords)
+      /* Zero-pad to multiple of 4 dwords */
+      .add(zero, align_sz - sizedwords);
+}
+
+template<chip CHIP>
+static void
+cs_const_emit(fd_cs &cs, struct kernel *kernel, uint32_t grid[3])
+{
+   struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
+   struct ir3_shader_variant *v = ir3_kernel->v;
+
+   const struct ir3_const_state *const_state = ir3_const_state(v);
+   uint32_t base = const_state->allocs.max_const_offset_vec4;
+   const struct ir3_imm_const_state *imm_state = &v->imm_state;
+   int size = DIV_ROUND_UP(imm_state->count, 4);
+
+   if (ir3_kernel->info.numwg != INVALID_REG) {
+      assert((ir3_kernel->info.numwg & 0x3) == 0);
+      int idx = ir3_kernel->info.numwg >> 2;
+      imm_state->values[idx * 4 + 0] = grid[0];
+      imm_state->values[idx * 4 + 1] = grid[1];
+      imm_state->values[idx * 4 + 2] = grid[2];
+   }
+
+   for (int i = 0; i < MAX_BUFS; i++) {
+      if (kernel->buf_addr_regs[i] != INVALID_REG) {
+         assert((kernel->buf_addr_regs[i] & 0x3) == 0);
+         int idx = kernel->buf_addr_regs[i] >> 2;
+
+         uint64_t iova = fd_bo_get_iova(kernel->bufs[i]);
+
+         imm_state->values[idx * 4 + 1] = iova >> 32;
+         imm_state->values[idx * 4 + 0] = (iova << 32) >> 32;
+      }
+   }
+
+   /* truncate size to avoid writing constants that shader
+    * does not use:
+    */
+   size = MIN2(size + base, v->constlen) - base;
+
+   /* convert out of vec4: */
+   base *= 4;
+   size *= 4;
+
+   if (size > 0) {
+      emit_const<CHIP>(cs, base, size, imm_state->values);
+   }
+}
+
+static unsigned
+kernel_num_bufs(struct kernel *kernel, enum kernel_buf_type buf_type)
+{
+   unsigned num_bufs = 0;
+
+   for (unsigned i = 0; i < kernel->num_bufs; i++) {
+      if (kernel->buf_types[i] == buf_type) {
+         num_bufs++;
+      }
+   }
+
+   return num_bufs;
+}
+
+template<chip CHIP>
+static void
+cs_uav_emit(fd_cs &cs, struct fd_device *dev, struct kernel *kernel)
+{
+   unsigned num_bufs = kernel_num_bufs(kernel, KERNEL_BUF_UAV);
+
+   if (num_bufs == 0) {
+      return;
+   }
+
+   struct fd_bo *state = fd_bo_new(dev, kernel->num_bufs * 16 * 4,
+                                   FD_BO_GPUREADONLY | FD_BO_HINT_COMMAND,
+                                   "tex_desc");
+   fd_bo_mark_for_dump(state);
+
+   cs.attach_bo(state);
+
+   uint32_t *buf = (uint32_t *)fd_bo_map(state);
+
+   for (unsigned i = 0; i < kernel->num_bufs; i++) {
+      if (kernel->buf_types[i] != KERNEL_BUF_UAV) {
+         continue;
+      }
+
+      cs.attach_bo(kernel->bufs[i]);
+
+      uint64_t iova = fd_bo_get_iova(kernel->bufs[i]);
+      uint32_t descriptor[16];
+
+      static const uint8_t swiz_identity[4] = {
+         PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
+         PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W,
+      };
+
+      fdl6_buffer_view_init<CHIP>(descriptor, PIPE_FORMAT_R32_UINT, swiz_identity,
+                                  iova, kernel->buf_sizes[i] * 4);
+
+      memcpy(buf, descriptor, 16 * 4);
+      buf += 16;
+   }
+
+   fd_pkt7(cs, CP_LOAD_STATE6_FRAG, 3)
+      .add(CP_LOAD_STATE6_0(
+         .state_type = ST6_UAV,
+         .state_src = SS6_INDIRECT,
+         .state_block = SB6_CS_SHADER,
+         .num_unit = num_bufs,
+      ))
+      .add(CP_LOAD_STATE6_EXT_SRC_ADDR(state));
+
+   fd_crb crb(cs, 3);
+
+   crb.add(SP_CS_UAV_BASE(CHIP, state));
+   crb.add(A6XX_SP_CS_USIZE(num_bufs));
+
+   fd_bo_del(state);
+}
+
+static void
+cs_ubo_emit(fd_cs &cs, struct kernel *kernel)
+{
+   unsigned num_bufs = kernel_num_bufs(kernel, KERNEL_BUF_UBO);
+
+   if (num_bufs == 0) {
+      return;
+   }
+
+   for (unsigned i = 0, offset = 0; i < kernel->num_bufs; i++) {
+      if (kernel->buf_types[i] != KERNEL_BUF_UBO) {
+         continue;
+      }
+
+      cs.attach_bo(kernel->bufs[i]);
+
+      unsigned size_vec4s = DIV_ROUND_UP(kernel->buf_sizes[i], 4);
+
+      fd_pkt7(cs, CP_LOAD_STATE6_FRAG, 5)
+         .add(CP_LOAD_STATE6_0(
+            .dst_off = offset,
+            .state_type = ST6_UBO,
+            .state_src = SS6_DIRECT,
+            .state_block = SB6_CS_SHADER,
+            .num_unit = 1,
+         ))
+         .add(CP_LOAD_STATE6_EXT_SRC_ADDR())
+         .add(A6XX_UBO_DESC(0, kernel->bufs[i], 0, size_vec4s));
+
+      offset++;
+   }
+}
+
+template<chip CHIP>
+static inline unsigned
+event_write(fd_cs &cs, struct kernel *kernel, enum vgt_event_type evt, bool timestamp)
+{
+   unsigned seqno = 0;
+   unsigned len = timestamp ? 4 : 1;
+
+   fd_pkt7 pkt(cs, CP_EVENT_WRITE, len);
+
+   if (CHIP == A6XX) {
+      pkt.add(CP_EVENT_WRITE_0_EVENT(evt));
+   } else {
+      pkt.add(CP_EVENT_WRITE7_0_EVENT(evt) |
+              CP_EVENT_WRITE7_0_WRITE_SRC(EV_WRITE_USER_32B) |
+              COND(timestamp, CP_EVENT_WRITE7_0_WRITE_ENABLED));
+   }
+
+   if (timestamp) {
+      struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
+      struct a6xx_backend *a6xx_backend = to_a6xx_backend(ir3_kernel->backend);
+      seqno = ++a6xx_backend->seqno;
+      pkt.add(CP_EVENT_WRITE_ADDR(control_ptr(a6xx_backend, seqno)));
+      pkt.add(seqno);
+   }
+
+   return seqno;
+}
+
+template<chip CHIP>
+static inline void
+cache_flush(fd_cs &cs, struct kernel *kernel)
+{
+   struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
+   struct a6xx_backend *a6xx_backend = to_a6xx_backend(ir3_kernel->backend);
+   unsigned seqno;
+
+   seqno = event_write<CHIP>(cs, kernel, RB_DONE_TS, true);
+
+   fd_pkt7(cs, CP_WAIT_REG_MEM, 6)
+      .add(CP_WAIT_REG_MEM_0(.function = WRITE_EQ, .poll = POLL_MEMORY))
+      .add(CP_WAIT_REG_MEM_POLL_ADDR(control_ptr(a6xx_backend, seqno)))
+      .add(CP_WAIT_REG_MEM_3(.ref = seqno))
+      .add(CP_WAIT_REG_MEM_4(.mask = ~0))
+      .add(CP_WAIT_REG_MEM_5(.delay_loop_cycles = 16));
+
+   if (CHIP == A6XX) {
+      seqno = event_write<CHIP>(cs, kernel, CACHE_FLUSH_TS, true);
+
+      fd_pkt7(cs, CP_WAIT_MEM_GTE, 4)
+         .add(CP_WAIT_MEM_GTE_0())
+         .add(CP_WAIT_MEM_GTE_POLL_ADDR(control_ptr(a6xx_backend, seqno)))
+         .add(CP_WAIT_MEM_GTE_3(.ref = seqno));
+   } else {
+      event_write<CHIP>(cs, kernel, CACHE_FLUSH7, false);
+   }
+}
+
+template<chip CHIP>
+static void
+a6xx_emit_grid(struct kernel *kernel, uint32_t grid[3],
+               struct fd_submit *submit)
+{
+   struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
+   struct a6xx_backend *a6xx_backend = to_a6xx_backend(ir3_kernel->backend);
+   fd_cs cs(fd_submit_new_ringbuffer(submit, 0,
+      (enum fd_ringbuffer_flags)(FD_RINGBUFFER_PRIMARY | FD_RINGBUFFER_GROWABLE)));
+
+   cs.attach_bo(a6xx_backend->control_mem);
+
+   cs_restore_emit<CHIP>(cs, a6xx_backend);
+   cs_program_emit<CHIP>(cs, kernel);
+   cs_const_emit<CHIP>(cs, kernel, grid);
+   cs_uav_emit<CHIP>(cs, a6xx_backend->dev, kernel);
+   cs_ubo_emit(cs, kernel);
+
+   if (CHIP >= A8XX) {
+      fd_pkt7(cs, CP_SET_MARKER, 1)
+         .add(A8XX_CP_SET_MARKER_0(.mode = RM6_COMPUTE));
+   } else{
+      fd_pkt7(cs, CP_SET_MARKER, 1)
+         .add(A6XX_CP_SET_MARKER_0(.mode = RM6_COMPUTE));
+   }
+
+   const unsigned *local_size = kernel->local_size;
+   const unsigned *num_groups = grid;
+
+   unsigned work_dim = 0;
+   for (int i = 0; i < 3; i++) {
+      if (!grid[i])
+         break;
+      work_dim++;
+   }
+
+   with_crb (cs, 11) {
+      crb.add(SP_CS_NDRANGE_0(CHIP,
+         .kerneldim = work_dim,
+         .localsizex = local_size[0] - 1,
+         .localsizey = local_size[1] - 1,
+         .localsizez = local_size[2] - 1,
+      ));
+
+      if (CHIP >= A7XX) {
+         crb.add(SP_CS_NDRANGE_7(CHIP,
+            .localsizex = local_size[0] - 1,
+            .localsizey = local_size[1] - 1,
+            .localsizez = local_size[2] - 1,
+         ));
+      }
+
+      crb.add(SP_CS_NDRANGE_1(CHIP,
+         .globalsize_x = local_size[0] * num_groups[0],
+      ));
+      crb.add(SP_CS_NDRANGE_2(CHIP, 0));
+      crb.add(SP_CS_NDRANGE_3(CHIP,
+         .globalsize_y = local_size[1] * num_groups[1],
+      ));
+      crb.add(SP_CS_NDRANGE_4(CHIP, 0));
+      crb.add(SP_CS_NDRANGE_5(CHIP,
+         .globalsize_z = local_size[2] * num_groups[2],
+      ));
+      crb.add(SP_CS_NDRANGE_6(CHIP, 0));
+
+      crb.add(SP_CS_KERNEL_GROUP_X(CHIP, 1));
+      crb.add(SP_CS_KERNEL_GROUP_Y(CHIP, 1));
+      crb.add(SP_CS_KERNEL_GROUP_Z(CHIP, 1));
+   }
+
+   if (a6xx_backend->num_perfcntrs > 0) {
+      a6xx_backend->query_mem = fd_bo_new(
+         a6xx_backend->dev,
+         a6xx_backend->num_perfcntrs * sizeof(struct fd6_query_sample), 0, "query");
+
+      /* configure the performance counters to count the requested
+       * countables:
+       */
+      for (unsigned i = 0; i < a6xx_backend->num_perfcntrs; i++) {
+         const struct perfcntr *counter = &a6xx_backend->perfcntrs[i];
+
+         fd_pkt4(cs, 1).add({
+            .reg = counter->select_reg,
+            .value = counter->selector,
+         });
+      }
+
+      fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
+
+      /* and snapshot the start values: */
+      for (unsigned i = 0; i < a6xx_backend->num_perfcntrs; i++) {
+         const struct perfcntr *counter = &a6xx_backend->perfcntrs[i];
+
+         fd_pkt7(cs, CP_REG_TO_MEM, 3)
+            .add(CP_REG_TO_MEM_0(.reg = counter->counter_reg_lo, ._64b = true))
+            .add(A5XX_CP_REG_TO_MEM_DEST(query_sample_idx(a6xx_backend, i, start)));
+      }
+   }
+
+   fd_pkt7(cs, CP_EXEC_CS, 4)
+      .add(CP_EXEC_CS_0())
+      .add(CP_EXEC_CS_1(.ngroups_x = grid[0]))
+      .add(CP_EXEC_CS_2(.ngroups_y = grid[1]))
+      .add(CP_EXEC_CS_3(.ngroups_z = grid[2]));
+
+   fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
+
+   if (a6xx_backend->num_perfcntrs > 0) {
+      /* snapshot the end values: */
+      for (unsigned i = 0; i < a6xx_backend->num_perfcntrs; i++) {
+         const struct perfcntr *counter = &a6xx_backend->perfcntrs[i];
+
+         fd_pkt7(cs, CP_REG_TO_MEM, 3)
+            .add(CP_REG_TO_MEM_0(.reg = counter->counter_reg_lo, ._64b = true))
+            .add(A5XX_CP_REG_TO_MEM_DEST(query_sample_idx(a6xx_backend, i, stop)));
+      }
+
+      /* and compute the result: */
+      for (unsigned i = 0; i < a6xx_backend->num_perfcntrs; i++) {
+         /* result += stop - start: */
+         fd_pkt7(cs, CP_MEM_TO_MEM, 9)
+            .add(CP_MEM_TO_MEM_0(.neg_c = true, ._double = true))
+            .add(CP_MEM_TO_MEM_DST(query_sample_idx(a6xx_backend, i, result)))
+            .add(CP_MEM_TO_MEM_SRC_A(query_sample_idx(a6xx_backend, i, result)))
+            .add(CP_MEM_TO_MEM_SRC_B(query_sample_idx(a6xx_backend, i, stop)))
+            .add(CP_MEM_TO_MEM_SRC_C(query_sample_idx(a6xx_backend, i, start)));
+      }
+   }
+
+   cache_flush<CHIP>(cs, kernel);
+}
+
+static void
+a6xx_set_perfcntrs(struct backend *b, const struct perfcntr *perfcntrs,
+                   unsigned num_perfcntrs)
+{
+   struct a6xx_backend *a6xx_backend = to_a6xx_backend(b);
+
+   a6xx_backend->perfcntrs = perfcntrs;
+   a6xx_backend->num_perfcntrs = num_perfcntrs;
+}
+
+static void
+a6xx_read_perfcntrs(struct backend *b, uint64_t *results)
+{
+   struct a6xx_backend *a6xx_backend = to_a6xx_backend(b);
+
+   fd_bo_cpu_prep(a6xx_backend->query_mem, NULL, FD_BO_PREP_READ);
+   struct fd6_query_sample *samples =
+      (struct fd6_query_sample *)fd_bo_map(a6xx_backend->query_mem);
+
+   for (unsigned i = 0; i < a6xx_backend->num_perfcntrs; i++) {
+      results[i] = samples[i].result;
+   }
+}
+
+template<chip CHIP>
+struct backend *
+a6xx_init(struct fd_device *dev, const struct fd_dev_id *dev_id)
+{
+   struct a6xx_backend *a6xx_backend =
+      (struct a6xx_backend *)calloc(1, sizeof(*a6xx_backend));
+
+   a6xx_backend->base = (struct backend){
+      .assemble = a6xx_assemble,
+      .disassemble = a6xx_disassemble,
+      .emit_grid = a6xx_emit_grid<CHIP>,
+      .set_perfcntrs = a6xx_set_perfcntrs,
+      .read_perfcntrs = a6xx_read_perfcntrs,
+   };
+
+   struct ir3_compiler_options compiler_options = {
+      .disable_cache = true,
+   };
+   a6xx_backend->compiler =
+      ir3_compiler_create(dev, dev_id, fd_dev_info_raw(dev_id), &compiler_options);
+   a6xx_backend->dev = dev;
+
+   a6xx_backend->info = fd_dev_info_raw(dev_id);
+
+   a6xx_backend->control_mem =
+      fd_bo_new(dev, 0x1000, 0, "control");
+
+   return &a6xx_backend->base;
+}
+FD_GENX(a6xx_init);

src/freedreno/computerator/examples/branch.asm

@@ -0,0 +1,15 @@
+@localsize 16, 1, 1
+@buf 16  ; g[0]
+@invocationid(r0.x) ; r0.xyz
+@branchstack 1
+cmps.u.gt p0.x, r0.x, 0
+mov.u32u32 r1.x, 0x87654321
+(rpt5)nop
+br !p0.x, #endif
+mov.u32u32 r1.x, 0x12345678
+endif:
+(jp)(rpt5)nop
+stib.b.untyped.1d.u32.1.imm r1.x, r0.x, 0
+end
+nop
+

src/freedreno/computerator/examples/buf-init.asm

@@ -0,0 +1,9 @@
+@localsize 8, 1, 1
+@buf 8 1, 2, 3, 4, 5, 6, 7, 8
+@invocationid(r0.x)
+
+ldib.b.untyped.1d.u32.4.imm r1.x, r0.x, 0
+(sy)add.u r1.x, r1.x, 5
+(rpt5)nop
+stib.b.untyped.1d.u32.4.imm r1.x, r0.x, 0
+end

src/freedreno/computerator/examples/early_preamble.asm

@@ -0,0 +1,25 @@
+@localsize 1, 1, 1
+@buf 4  ; g[0]
+@invocationid(r0.x) ; r0.xyz
+@const(c0.x)  0.0, 0.0, 0.0, 0.0
+@earlypreamble
+
+shps #l_preamble_end
+getone #l_preamble_end
+
+mov.u32u32 r48.x, 1
+mov.u32u32 r48.y, 2
+mov.u32u32 r48.z, 3
+mov.u32u32 r48.w, 4
+(rpt5)nop
+stc.u32 c[0], r48.x, 4
+
+(sy)(ss)shpe
+
+l_preamble_end:
+(jp)nop
+
+(rpt3)mov.u32u32 r1.x, (r)c0.x
+(rpt5)nop
+stib.b.untyped.1d.u32.4.imm r1.x, r0.x, 0
+end

src/freedreno/computerator/examples/invocationid.asm

@@ -0,0 +1,13 @@
+@localsize 32, 1, 1
+@buf 32  ; g[0]
+@const(c0.x)  0.0, 0.0, 0.0, 0.0
+@const(c1.x)  1.0, 2.0, 3.0, 4.0
+@wgid(r48.x)        ; r48.xyz
+@invocationid(r0.x) ; r0.xyz
+@numwg(c2.x)        ; c2.xyz
+mov.u32u32 r0.y, r0.x
+(rpt5)nop
+stib.b.untyped.1d.u32.1.imm r0.x, r0.y, 0
+end
+nop
+

src/freedreno/computerator/examples/localmem.asm

@@ -0,0 +1,18 @@
+@localsize 8, 1, 1
+@buf 8
+@invocationid(r0.x)
+@localmem 4
+@branchstack 1
+
+mov.u32u32 r1.x, 0
+
+getone #l_all
+mov.u32u32 r1.y, 5
+(rpt2)nop
+stlw.u32 l[r1.x], r1.y, 1
+
+l_all:
+(jp)ldlw.u32 r1.z, l[r1.x], 1
+(ss)nop
+stib.b.untyped.1d.u32.4.imm r1.z, r0.x, 0
+end

src/freedreno/computerator/examples/pvtmem.asm

@@ -0,0 +1,14 @@
+@localsize 1, 1, 1
+@buf 4  ; g[0]
+@pvtmem 4
+mov.u32u32 r1.x, 0x12345678
+mov.u32u32 r0.x, 0
+(rpt5)nop
+stp.u32 p[r0.x + 0], r1.x, 1
+ldp.u32 r0.x, p[r0.x + 0], 1
+mov.u32u32 r0.y, 0x00000000
+(sy)(rpt5)nop
+stib.b.untyped.1d.u32.1.imm r0.x, r0.y, 0
+end
+nop
+

src/freedreno/computerator/examples/simple.asm

@@ -0,0 +1,28 @@
+@localsize 1, 1, 1
+@buf 4  ; g[0]
+@const(c0.x)  0.0, 0.0, 0.0, 0.0
+@const(c1.x)  1.0, 2.0, 3.0, 4.0
+@wgid(r48.x)        ; r48.xyz
+@invocationid(r0.x) ; r0.xyz
+@numwg(c2.x)        ; c2.xyz
+mov.f32f32 r2.x, c0.y
+mov.u32u32 r0.x, 0x12345678
+mov.u32u32 r0.y, 0x12345678
+mov.u32u32 r0.z, 0x12345678
+add.u r2.x, c0.x, r2.x
+mov.u32u32 r0.w, 0x12345678
+mov.u32u32 r1.x, 0x12345678
+mov.u32u32 r1.y, 0x12345678
+cov.u32s16 hr4.x, r2.x
+mov.u32u32 r1.z, 0x12345678
+mov.u32u32 r1.w, 0x12345678
+nop
+mova a0.x, hr4.x
+(rpt5)nop
+(ul)mov.u32u32 r0.x, r<a0.x>
+mov.u32u32 r0.y, 0x00000000
+(rpt5)nop
+stib.b.untyped.1d.u32.1.imm r0.x, r0.y, 0
+end
+nop
+

src/freedreno/computerator/examples/stg_ldg_offset.asm

@@ -0,0 +1,17 @@
+@localsize 16, 1, 1
+@buf 128 (c2.x)  ; c2.xy
+@invocationid(r0.x) ; r0.xyz
+mov.u32u32 r0.y, r0.x
+mov.u32u32 r1.x, c2.x
+mov.u32u32 r1.y, c2.y
+mov.u32u32 r2.x, 0xff
+(rpt5)nop
+stg.a.u32 g[r1.x+r0.y<<4+2<<2], r2.x, 1
+nop(sy)
+ldg.a.u32 r4.x, g[r1.x+r0.y<<4+2<<2], 1
+nop(sy)
+add.u r4.x, r4.x, 1
+(rpt3)nop
+stg.a.u32 g[r1.x+r0.y<<4+1<<2], r4.x, 1
+end
+nop

src/freedreno/computerator/examples/test-flut.sh

@@ -0,0 +1,40 @@
+#!/bin/bash
+
+set -e
+
+gen_shader() {
+	imm=$1
+	if [ "$2" = "half" ]; then
+		h="h"
+		mov="cov.u16u32"
+	else
+		h=""
+		mov="mov.u32u32"
+	fi
+	cat <<EOF
+@localsize 1, 1, 1
+@buf 4  ; g[0]
+mov.u32u32 r0.x, 0
+(rpt5)nop
+(rpt5)nop
+add.f ${h}r2.x, ${h}r0.x, $imm
+(rpt5)nop
+$mov r1.x, ${h}r2.x
+(rpt5)nop
+; and store results:
+stib.b.untyped.1d.u32.1.imm r1.x, r0.x, 0
+(sy)nop
+end
+EOF
+}
+
+
+run() {
+	echo "TEST: $*"
+	gen_shader $* | ./computerator -g 1,1,1 -d
+}
+
+for n in `seq 0 16`; do
+	run "$n" "full"
+	run "h($n)" "half"
+done

src/freedreno/computerator/examples/test-opcodes.sh

@@ -0,0 +1,297 @@
+#!/bin/bash
+#
+# Test various instructions to check whether half<->full widening/narrowing
+# works.  The basic premise is to perform the same instruction with and
+# without the widening/narrowing folded in and check if the results match.
+#
+# Note this doesn't currently diferentiate between signed/unsigned/bool,
+# and just assumes int is signed (since unsigned is basically(ish) like
+# signed but without sign extension)
+#
+# TODO probably good pick numeric src values that are better at triggering
+# edge cases, while still not loosing precision in a full->half->full
+# seqeuence.. but some instructions like absneg don't even appear to be
+# subtlely wrong when you try to fold in a precision conversion.
+#
+# add '-v' arg to see the result values
+
+set -e
+
+#
+# Templates for float->float instructions:
+#
+f2f_instrs=(
+	'add.f $dst, $src1, $src2'
+	'min.f $dst, $src1, $src2'
+	'min.f $dst, $src2, $src1'
+	'max.f $dst, $src1, $src2'
+	'max.f $dst, $src2, $src1'
+	'mul.f $dst, $src1, $src2'
+	'sign.f $dst, $src1'
+	'absneg.f $dst, \(neg\)$src1'
+	'absneg.f $dst, \(abs\)$src1'
+	'floor.f $dst, $src1'
+	'ceil.f $dst, $src1'
+	'rndne.f $dst, $src1'
+	'rndaz.f $dst, $src1'
+	'trunc.f $dst, $src1'
+)
+
+#
+# Templates for float->int instructions:
+#
+f2i_instrs=(
+	'cmps.f.gt $dst, $src1, $src2'
+	'cmps.f.lt $dst, $src1, $src2'
+	'cmpv.f.gt $dst, $src1, $src2'
+	'cmpv.f.lt $dst, $src1, $src2'
+)
+
+#
+# Templates for int->int instructions:
+#
+i2i_instrs=(
+	'add.u $dst, $src1, $src2'
+	'add.s $dst, $src1, $src2'
+	'sub.u $dst, $src1, $src2'
+	'sub.s $dst, $src1, $src2'
+	'cmps.f.gt $dst, $src1, $src2'
+	'cmps.f.lt $dst, $src1, $src2'
+	'min.u $dst, $src1, $src2'
+	'min.u $dst, $src2, $src1'
+	'min.s $dst, $src1, $src2'
+	'min.s $dst, $src2, $src1'
+	'max.u $dst, $src1, $src2'
+	'max.u $dst, $src2, $src1'
+	'max.s $dst, $src1, $src2'
+	'max.s $dst, $src2, $src1'
+	'absneg.s $dst, \(neg\)$src1'
+	'absneg.s $dst, \(abs\)$src1'
+	'and.b $dst, $src2, $src3'
+	'or.b $dst, $src1, $src2'
+	'not.b $dst, $src1'
+	'xor.b $dst, $src1, $src2'
+	'cmpv.u.gt $dst, $src1, $src2'
+	'cmpv.u.lt $dst, $src1, $src2'
+	'cmpv.s.gt $dst, $src1, $src2'
+	'cmpv.s.lt $dst, $src1, $src2'
+	'mul.u24 $dst, $src1, $src2'
+	'mul.s24 $dst, $src1, $src2'
+	'mull.u $dst, $src1, $src2'
+	'bfrev.b $dst, $src1'
+	'clz.s $dst, $src2'
+	'clz.b $dst, $src2'
+	'shl.b $dst, $src1, $src2'
+	'shr.b $dst, $src3, $src1'
+	'ashr.b $dst, $src3, $src1'
+	'mgen.b $dst, $src1, $src2'
+	'getbit.b $dst, $src3, $src2'
+	'setrm $dst, $src1'
+	'cbits.b $dst, $src3'
+	'shb $dst, $src1, $src2'
+	'msad $dst, $src1, $src2'
+)
+
+#
+# Helper to expand instruction template:
+#
+expand() {
+	instr=$1
+	dst=$2
+	src1=$3
+	src2=$4
+	src3=$5
+	eval echo $instr
+}
+
+expand_test() {
+	instr=$1
+
+	echo '; control, half->half:'
+	expand $instr "hr1.x" "hr0.x" "hr0.y" "hr0.z"
+	echo '; test, full->half:'
+	expand $instr "hr1.y" "r1.x" "r1.y" "r1.z"
+
+	echo '; control, full->full:'
+	expand $instr "r2.x" "r1.x" "r1.y" "r1.z"
+	echo '; test, half->full:'
+	expand $instr "r2.y" "hr0.x" "hr0.y" "hr0.z"
+
+	echo "(rpt5)nop"
+}
+
+#
+# Helpers to construct test program assembly:
+#
+header_asm() {
+	cat <<EOF
+@localsize 1, 1, 1
+@buf 4  ; g[0]
+EOF
+}
+
+footer_asm() {
+	cat <<EOF
+; dest offsets:
+mov.u32u32 r3.x, 0
+mov.u32u32 r3.y, 1
+mov.u32u32 r3.z, 2
+mov.u32u32 r3.w, 3
+(rpt5)nop
+
+; and store results:
+stib.untyped.1d.u32.1 r2.x, r3.x, 0   ; control: full->full
+stib.untyped.1d.u32.1 r2.y, r3.y, 0   ; test:    half->full
+stib.untyped.1d.u32.1 r2.z, r3.z, 0   ; control: half->half
+stib.untyped.1d.u32.1 r2.w, r3.w, 0   ; test:    full->half
+(sy)nop
+end
+EOF
+}
+
+setup_asm_float() {
+	cat <<EOF
+; hr0->hr1 (r0) avail for half, hr0 for src, hr1 for dst
+; r1->r2 avail for full, r1 for src, r2 for dst
+cov.f32f16 hr0.x, (1.0)
+cov.f32f16 hr0.y, (2.0)
+cov.f32f16 hr0.z, (3.0)
+mov.f32f32 r1.x,  (1.0)
+mov.f32f32 r1.y,  (2.0)
+mov.f32f32 r1.z,  (3.0)
+(rpt5)nop
+EOF
+}
+
+setup_asm_int() {
+	cat <<EOF
+; hr0->hr1 (r0) avail for half, hr0 for src, hr1 for dst
+; r1->r2 avail for full, r1 for src, r2 for dst
+cov.s32s16 hr0.x,  1
+cov.s32s16 hr0.y, -2
+cov.s32s16 hr0.z,  3
+mov.s32s32 r1.x,   1
+mov.s32s32 r1.y,  -2
+mov.s32s32 r1.z,   3
+(rpt5)nop
+EOF
+}
+
+#
+# Generate assembly code to test float->float opcode
+#
+f2f_asm() {
+	instr=$1
+
+	header_asm
+	setup_asm_float
+	expand_test $instr
+
+	cat <<EOF
+; convert half results back to full:
+cov.f16f32 r2.z, hr1.x
+cov.f16f32 r2.w, hr1.y
+EOF
+
+	footer_asm
+}
+
+#
+# Generate assembly code to test float->int opcode
+#
+f2i_asm() {
+	instr=$1
+
+	header_asm
+	setup_asm_float
+	expand_test $instr
+
+	cat <<EOF
+; convert half results back to full:
+cov.s16s32 r2.z, hr1.x
+cov.s16s32 r2.w, hr1.y
+EOF
+
+	footer_asm
+}
+
+#
+# Generate assembly code to test int->int opcode
+#
+i2i_asm() {
+	instr=$1
+
+	header_asm
+	setup_asm_int
+	expand_test $instr
+
+	cat <<EOF
+; convert half results back to full:
+cov.s16s32 r2.z, hr1.x
+cov.s16s32 r2.w, hr1.y
+EOF
+
+	footer_asm
+}
+
+
+#
+# Helper to parse computerator output and print results:
+#
+check_results() {
+	str=`cat - | grep "	" | head -1 | xargs`
+
+	if [ "$verbose" = "true" ]; then
+		echo $str
+	fi
+
+	# Split components of result buffer:
+	cf=$(echo $str | cut -f1 -d' ')
+	tf=$(echo $str | cut -f2 -d' ')
+	ch=$(echo $str | cut -f3 -d' ')
+	th=$(echo $str | cut -f4 -d' ')
+
+	# Sanity test, make sure the control results match:
+	if [ $cf != $ch ]; then
+		echo "    FAIL: control results do not match!  Half vs full op is not equivalent!"
+		echo "    full=$cf half=$ch"
+	fi
+
+	# Compare test (with conversion folded) to control:
+	if [ $cf != $tf ]; then
+		echo "    FAIL: half -> full widening result does not match control!"
+		echo "    control=$cf result=$tf"
+	fi
+	if [ $ch != $th ]; then
+		echo "    FAIL: full -> half narrowing result does not match control!"
+		echo "    control=$ch result=$th"
+	fi
+
+	# HACK without a delay different invocations
+	# of computerator seem to somehow clobber each
+	# other.. which isn't great..
+	sleep 0.1
+}
+
+#
+# Run the tests!
+#
+
+if [ "$1" = "-v" ]; then
+	verbose="true"
+fi
+
+IFS=""
+for instr in ${f2f_instrs[@]}; do
+	echo "TEST: $instr"
+	f2f_asm $instr | ./computerator -g 1,1,1 | check_results
+done
+for instr in ${f2i_instrs[@]}; do
+	echo "TEST: $instr"
+	f2i_asm $instr | ./computerator -g 1,1,1 | check_results
+done
+for instr in ${i2i_instrs[@]}; do
+	echo "TEST: $instr"
+	i2i_asm $instr | ./computerator -g 1,1,1 | check_results
+done
+

src/freedreno/computerator/examples/test-regfile.sh

@@ -0,0 +1,53 @@
+#!/bin/bash
+
+# This tests for the size of the register file. We do this by launching a
+# lot of workgroups with only one invocation, which causes the GPU to be
+# saturated with in-flight waves. Each thread records its wave id using "getwid"
+# (only available in a6xx+!) and stores it in the buffer. We then vary the
+# register footprint by introducing uses of higher and higher registers. This
+# lets us determine:
+# 1. The total number of waves available (always 16 for known models)
+# 2. The wave granularity (how many waves are always launched together, always 2
+# for known models).
+# 3. The total size of the register file that is divvied up between the waves.
+
+set -e
+
+gen_shader() {
+	n=$1;
+	cat <<EOF
+@localsize 1, 1, 1
+@buf 128  ; g[0]
+@wgid(r48.x)
+getwid.u32 r1.x
+mov.u32u32 r0.x, r48.x
+
+; busy loop to make sure it actually uses all possible waves
+mov.u32u32 r0.y, 16
+(rpt2)nop
+loop:
+cmps.u.gt p0.x, r0.y, 0
+sub.u r0.y, r0.y, 1
+(rpt5)nop
+br p0.x, #loop
+add.f r1.y, r1.x, r$n.w
+
+(ss)(sy)(rpt5)nop
+stib.b.untyped.1d.u32.1.imm r1.x, r0.x, 0
+end
+nop
+EOF
+}
+
+# generate reference:
+gen_shader 1 | ./computerator -g 128,1,1 | tee reference.log
+
+for n in `seq 2 32`; do
+	echo "Trying max reg: r$n"
+	gen_shader $n | ./computerator -g 128,1,1 | tee new.log
+	diff reference.log new.log
+	if [ "$?" != "0" ]; then
+		echo "Changes at r$n"
+		break
+	fi
+done