init

src/intel/blorp/blorp.c

@@ -0,0 +1,405 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "blorp_priv.h"
+#include "compiler/intel_nir.h"
+#include "dev/intel_device_info.h"
+#include "util/u_math.h"
+
+enum intel_measure_snapshot_type
+blorp_op_to_intel_measure_snapshot(enum blorp_op op)
+{
+   enum intel_measure_snapshot_type vals[] = {
+#define MAP(name) [BLORP_OP_##name] = INTEL_SNAPSHOT_##name
+      MAP(BLIT),
+      MAP(COPY),
+      MAP(CCS_AMBIGUATE),
+      MAP(CCS_COLOR_CLEAR),
+      MAP(CCS_PARTIAL_RESOLVE),
+      MAP(CCS_RESOLVE),
+      MAP(FAST_STENCIL_CLEAR),
+      MAP(HIZ_AMBIGUATE),
+      MAP(HIZ_CLEAR),
+      MAP(HIZ_STENCIL_CLEAR),
+      MAP(HIZ_RESOLVE),
+      MAP(HIZ_PARTIAL_RESOLVE),
+      MAP(MCS_AMBIGUATE),
+      MAP(MCS_COLOR_CLEAR),
+      MAP(MCS_PARTIAL_RESOLVE),
+      MAP(LINEAR_SURFACE_CLEAR),
+      MAP(SLOW_COLOR_CLEAR),
+      MAP(SLOW_STENCIL_CLEAR),
+      MAP(SLOW_DEPTH_STENCIL_CLEAR),
+      MAP(SLOW_DEPTH_CLEAR),
+#undef MAP
+   };
+   assert(op < ARRAY_SIZE(vals));
+
+   return vals[op];
+}
+
+const char *blorp_op_to_name(enum blorp_op op)
+{
+   const char *names[] = {
+#define MAP(name) [BLORP_OP_##name] = #name
+      MAP(BLIT),
+      MAP(COPY),
+      MAP(CCS_AMBIGUATE),
+      MAP(CCS_COLOR_CLEAR),
+      MAP(CCS_PARTIAL_RESOLVE),
+      MAP(CCS_RESOLVE),
+      MAP(FAST_STENCIL_CLEAR),
+      MAP(HIZ_AMBIGUATE),
+      MAP(HIZ_CLEAR),
+      MAP(HIZ_STENCIL_CLEAR),
+      MAP(HIZ_RESOLVE),
+      MAP(HIZ_PARTIAL_RESOLVE),
+      MAP(MCS_AMBIGUATE),
+      MAP(MCS_COLOR_CLEAR),
+      MAP(MCS_PARTIAL_RESOLVE),
+      MAP(LINEAR_SURFACE_CLEAR),
+      MAP(SLOW_COLOR_CLEAR),
+      MAP(SLOW_STENCIL_CLEAR),
+      MAP(SLOW_DEPTH_STENCIL_CLEAR),
+      MAP(SLOW_DEPTH_CLEAR),
+#undef MAP
+   };
+   assert(op < ARRAY_SIZE(names));
+
+   return names[op];
+}
+
+const char *
+blorp_shader_type_to_name(enum blorp_shader_type type)
+{
+   static const char *shader_name[] = {
+      [BLORP_SHADER_TYPE_COPY]                = "BLORP-copy",
+      [BLORP_SHADER_TYPE_BLIT]                = "BLORP-blit",
+      [BLORP_SHADER_TYPE_CLEAR]               = "BLORP-clear",
+      [BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE] = "BLORP-mcs-partial-resolve",
+      [BLORP_SHADER_TYPE_LAYER_OFFSET_VS]     = "BLORP-layer-offset-vs",
+      [BLORP_SHADER_TYPE_GFX4_SF]             = "BLORP-gfx4-sf",
+   };
+   assert(type < ARRAY_SIZE(shader_name));
+
+   return shader_name[type];
+}
+
+const char *
+blorp_shader_pipeline_to_name(enum blorp_shader_pipeline pipe)
+{
+   static const char *pipeline_name[] = {
+      [BLORP_SHADER_PIPELINE_RENDER]  = "render",
+      [BLORP_SHADER_PIPELINE_COMPUTE] = "compute",
+   };
+   assert(pipe < ARRAY_SIZE(pipeline_name));
+
+   return pipeline_name[pipe];
+}
+
+void
+blorp_init(struct blorp_context *blorp, void *driver_ctx,
+           struct isl_device *isl_dev, const struct blorp_config *config)
+{
+   memset(blorp, 0, sizeof(*blorp));
+
+   blorp->driver_ctx = driver_ctx;
+   blorp->isl_dev = isl_dev;
+   if (config)
+      blorp->config = *config;
+
+   blorp->compiler = rzalloc(NULL, struct blorp_compiler);
+}
+
+void
+blorp_finish(struct blorp_context *blorp)
+{
+   ralloc_free(blorp->compiler);
+   blorp->driver_ctx = NULL;
+}
+
+void
+blorp_batch_init(struct blorp_context *blorp,
+                 struct blorp_batch *batch, void *driver_batch,
+                 enum blorp_batch_flags flags)
+{
+   batch->blorp = blorp;
+   batch->driver_batch = driver_batch;
+   batch->flags = flags;
+}
+
+void
+blorp_batch_finish(struct blorp_batch *batch)
+{
+   batch->blorp = NULL;
+}
+
+void
+blorp_surface_info_init(struct blorp_batch *batch,
+                        struct blorp_surface_info *info,
+                        const struct blorp_surf *surf,
+                        unsigned int level, float layer,
+                        enum isl_format format, bool is_dest)
+{
+   struct blorp_context *blorp = batch->blorp;
+   memset(info, 0, sizeof(*info));
+   assert(level < surf->surf->levels);
+   assert(layer < MAX2(surf->surf->logical_level0_px.depth >> level,
+                       surf->surf->logical_level0_px.array_len));
+
+   info->enabled = true;
+
+   if (format == ISL_FORMAT_UNSUPPORTED)
+      format = surf->surf->format;
+
+   info->surf = *surf->surf;
+   info->addr = surf->addr;
+
+   info->aux_usage = surf->aux_usage;
+   info->aux_format = surf->surf->format;
+   if (!blorp_address_is_null(surf->aux_addr)) {
+      info->aux_surf = *surf->aux_surf;
+      info->aux_addr = surf->aux_addr;
+   }
+
+   info->clear_color = surf->clear_color;
+   info->clear_color_addr = surf->clear_color_addr;
+   info->has_replicated_pixel = surf->has_replicated_pixel;
+
+   isl_surf_usage_flags_t view_usage;
+   if (is_dest) {
+      if (batch->flags & BLORP_BATCH_USE_COMPUTE)
+         view_usage = ISL_SURF_USAGE_STORAGE_BIT;
+      else
+         view_usage = ISL_SURF_USAGE_RENDER_TARGET_BIT;
+   } else {
+      view_usage = ISL_SURF_USAGE_TEXTURE_BIT;
+   }
+
+   info->view = (struct isl_view) {
+      .usage = view_usage,
+      .format = format,
+      .base_level = level,
+      .levels = 1,
+      .swizzle = ISL_SWIZZLE_IDENTITY,
+   };
+
+   info->view.array_len =
+      MAX2(u_minify(info->surf.logical_level0_px.depth, level),
+           info->surf.logical_level0_px.array_len);
+
+   if (!is_dest &&
+       (info->surf.dim == ISL_SURF_DIM_3D ||
+        info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
+      /* 3-D textures don't support base_array layer and neither do 2-D
+       * multisampled textures on IVB so we need to pass it through the
+       * sampler in those cases.  These are also two cases where we are
+       * guaranteed that we won't be doing any funny surface hacks.
+       */
+      info->view.base_array_layer = 0;
+      info->z_offset = layer;
+   } else {
+      info->view.base_array_layer = layer;
+
+      assert(info->view.array_len >= info->view.base_array_layer);
+      info->view.array_len -= info->view.base_array_layer;
+      info->z_offset = 0;
+   }
+
+   /* Sandy Bridge and earlier have a limit of a maximum of 512 layers for
+    * layered rendering.
+    */
+   if (is_dest && blorp->isl_dev->info->ver <= 6)
+      info->view.array_len = MIN2(info->view.array_len, 512);
+
+   if (surf->tile_x_sa || surf->tile_y_sa) {
+      /* This is only allowed on simple 2D surfaces without MSAA */
+      assert(info->surf.dim == ISL_SURF_DIM_2D);
+      assert(info->surf.samples == 1);
+      assert(info->surf.levels == 1);
+      assert(info->surf.logical_level0_px.array_len == 1);
+      assert(info->aux_usage == ISL_AUX_USAGE_NONE);
+
+      info->tile_x_sa = surf->tile_x_sa;
+      info->tile_y_sa = surf->tile_y_sa;
+
+      /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we
+       * place the image at the tile boundary and offset our sampling or
+       * rendering.  For this reason, we need to grow the image by the offset
+       * to ensure that the hardware doesn't think we've gone past the edge.
+       */
+      info->surf.logical_level0_px.w += surf->tile_x_sa;
+      info->surf.logical_level0_px.h += surf->tile_y_sa;
+      info->surf.phys_level0_sa.w += surf->tile_x_sa;
+      info->surf.phys_level0_sa.h += surf->tile_y_sa;
+   }
+
+   if (blorp->isl_dev->requires_padding && !is_dest &&
+       (batch->flags & BLORP_BATCH_SRC_UNPADDED)) {
+      blorp_assert_is_buffer(info->surf, info->view);
+
+      /* Infers the page boundaries for a buffer to image copy based on the
+       * surface address and dimensions, following Vulkan semantics to
+       * determine the extent of the final row.
+       */
+      uint64_t size_B =
+         (uint64_t) info->surf.phys_level0_sa.w *
+            (isl_format_get_layout(info->view.format)->bpb / 8) +
+         (uint64_t) (info->surf.phys_level0_sa.h - 1) *
+            info->surf.row_pitch_B;
+
+      uint64_t mask = blorp->isl_dev->info->mem_alignment - 1;
+      uint64_t address = batch->blorp->get_surface_address(batch, info->addr);
+      info->page_base = address & ~mask;
+      info->page_limit = (address + size_B + mask) & ~mask;
+   }
+}
+
+
+void
+blorp_params_init(struct blorp_params *params)
+{
+   memset(params, 0, sizeof(*params));
+   params->num_samples = 1;
+   params->num_draw_buffers = 1;
+   params->num_layers = 1;
+}
+
+void
+blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
+             uint32_t level, uint32_t start_layer, uint32_t num_layers,
+             enum isl_aux_op op)
+{
+   const struct intel_device_info *devinfo = batch->blorp->isl_dev->info;
+
+   struct blorp_params params;
+   blorp_params_init(&params);
+
+   params.hiz_op = op;
+   params.full_surface_hiz_op = true;
+   switch (op) {
+   case ISL_AUX_OP_FULL_RESOLVE:
+      params.op = BLORP_OP_HIZ_RESOLVE;
+      break;
+   case ISL_AUX_OP_PARTIAL_RESOLVE:
+      params.op = BLORP_OP_HIZ_PARTIAL_RESOLVE;
+      break;
+   case ISL_AUX_OP_AMBIGUATE:
+      params.op = BLORP_OP_HIZ_AMBIGUATE;
+      break;
+   case ISL_AUX_OP_FAST_CLEAR:
+      params.op = BLORP_OP_HIZ_CLEAR;
+      break;
+   case ISL_AUX_OP_NONE:
+      UNREACHABLE("Invalid HiZ op");
+   }
+
+   for (uint32_t a = 0; a < num_layers; a++) {
+      const uint32_t layer = start_layer + a;
+
+      blorp_surface_info_init(batch, &params.depth, surf, level,
+                              layer, surf->surf->format, true);
+
+      /* Align the rectangle primitive to 8x4 pixels.
+       *
+       * During fast depth clears, the emitted rectangle primitive  must be
+       * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
+       * 11.5.3.1 Depth Buffer Clear (and the matching section in the
+       * Sandybridge PRM):
+       *
+       *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
+       *     aligned to an 8x4 pixel block relative to the upper left corner
+       *     of the depth buffer [...]
+       *
+       * For hiz resolves, the rectangle must also be 8x4 aligned. Item
+       * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
+       * Ivybridge simulator require the alignment.
+       *
+       * To be safe, let's just align the rect for all hiz operations and all
+       * hardware generations.
+       *
+       * However, for some miptree slices of a Z24 texture, emitting an 8x4
+       * aligned rectangle that covers the slice may clobber adjacent slices
+       * if we strictly adhered to the texture alignments specified in the
+       * PRM.  The Ivybridge PRM, Section "Alignment Unit Size", states that
+       * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24
+       * surfaces, not 8. But commit 1f112cc increased the alignment from 4 to
+       * 8, which prevents the clobbering.
+       */
+      params.x1 = u_minify(params.depth.surf.logical_level0_px.width,
+                           params.depth.view.base_level);
+      params.y1 = u_minify(params.depth.surf.logical_level0_px.height,
+                           params.depth.view.base_level);
+      params.x1 = align(params.x1, 8);
+      params.y1 = align(params.y1, 4);
+
+      if (params.depth.view.base_level == 0) {
+         /* TODO: What about MSAA? */
+         params.depth.surf.logical_level0_px.width = params.x1;
+         params.depth.surf.logical_level0_px.height = params.y1;
+      } else if (devinfo->ver >= 8 && devinfo->ver <= 9 &&
+                 op == ISL_AUX_OP_AMBIGUATE) {
+         /* On some platforms, it's not enough to just adjust the clear
+          * rectangle when the LOD is greater than 0.
+          *
+          * From the BDW and SKL PRMs, Vol 7, "Optimized Hierarchical Depth
+          * Buffer Resolve":
+          *
+          *    The following is required when performing a hierarchical depth
+          *    buffer resolve:
+          *
+          *    - A rectangle primitive covering the full render target must be
+          *      programmed on Xmin, Ymin, Xmax, and Ymax in the
+          *      3DSTATE_WM_HZ_OP command.
+          *
+          *    - The rectangle primitive size must be aligned to 8x4 pixels.
+          *
+          * And from the Clear Rectangle programming note in 3DSTATE_WM_HZ_OP
+          * (Vol 2a):
+          *
+          *    Hence the max values must be less than or equal to: ( Surface
+          *    Width » LOD ) and ( Surface Height » LOD ) for X Max and Y Max
+          *    respectively.
+          *
+          * This means that the extent of the LOD must be naturally
+          * 8x4-aligned after minification of the base LOD. Since the base LOD
+          * dimensions affect the placement of smaller LODs, it's not trivial
+          * (nor possible, at times) to satisfy the requirement by adjusting
+          * the base LOD extent. Just assert that the caller is accessing an
+          * LOD that satisfies this requirement.
+          */
+         assert(u_minify(params.depth.surf.logical_level0_px.width,
+                         params.depth.view.base_level) == params.x1);
+         assert(u_minify(params.depth.surf.logical_level0_px.height,
+                         params.depth.view.base_level) == params.y1);
+      }
+
+      params.dst.surf.samples = params.depth.surf.samples;
+      params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
+      params.depth_format =
+         isl_format_get_depth_format(surf->surf->format, false);
+      params.num_samples = params.depth.surf.samples;
+
+      batch->blorp->exec(batch, &params);
+   }
+}

src/intel/blorp/blorp.h

@@ -0,0 +1,428 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef BLORP_H
+#define BLORP_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "isl/isl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct brw_compiler;
+struct elk_compiler;
+
+typedef struct nir_shader nir_shader;
+
+enum blorp_op {
+   BLORP_OP_BLIT,
+   BLORP_OP_COPY,
+   BLORP_OP_COPY_INDIRECT,
+   BLORP_OP_COPY_IMAGE_INDIRECT,
+   BLORP_OP_CCS_AMBIGUATE,
+   BLORP_OP_CCS_COLOR_CLEAR,
+   BLORP_OP_CCS_PARTIAL_RESOLVE,
+   BLORP_OP_CCS_RESOLVE,
+   BLORP_OP_FAST_STENCIL_CLEAR,
+   BLORP_OP_HIZ_AMBIGUATE,
+   BLORP_OP_HIZ_CLEAR,
+   BLORP_OP_HIZ_STENCIL_CLEAR,
+   BLORP_OP_HIZ_RESOLVE,
+   BLORP_OP_HIZ_PARTIAL_RESOLVE,
+   BLORP_OP_MCS_AMBIGUATE,
+   BLORP_OP_MCS_COLOR_CLEAR,
+   BLORP_OP_MCS_PARTIAL_RESOLVE,
+   BLORP_OP_LINEAR_SURFACE_CLEAR,
+   BLORP_OP_SLOW_COLOR_CLEAR,
+   BLORP_OP_SLOW_STENCIL_CLEAR,
+   BLORP_OP_SLOW_DEPTH_STENCIL_CLEAR,
+   BLORP_OP_SLOW_DEPTH_CLEAR,
+};
+
+struct blorp_batch;
+struct blorp_params;
+
+struct blorp_config {
+   bool use_mesh_shading;
+   bool use_unrestricted_depth_range;
+   bool use_cached_dynamic_states;
+};
+
+enum blorp_dynamic_state {
+   BLORP_DYNAMIC_STATE_BLEND,
+   BLORP_DYNAMIC_STATE_CC_VIEWPORT,
+   BLORP_DYNAMIC_STATE_COLOR_CALC,
+   BLORP_DYNAMIC_STATE_SAMPLER,
+
+   BLORP_DYNAMIC_STATE_COUNT,
+};
+
+struct blorp_address {
+   void *buffer;
+   int64_t offset;
+   unsigned reloc_flags;
+   uint32_t mocs;
+
+   /**
+    * True if this buffer is intended to live in device-local memory.
+    * This is only a performance hint; it's OK to set it to true even
+    * if eviction has temporarily forced the buffer to system memory.
+    */
+   bool local_hint;
+};
+
+struct blorp_context {
+   void *driver_ctx;
+
+   const struct isl_device *isl_dev;
+
+   struct blorp_compiler *compiler;
+
+   bool enable_tbimr;
+
+   nir_shader *(*get_fp64_nir)(struct blorp_context *context);
+
+   void (*upload_dynamic_state)(struct blorp_context *context,
+                                const void *data, uint32_t size,
+                                uint32_t alignment,
+                                enum blorp_dynamic_state name);
+
+   bool (*lookup_shader)(struct blorp_batch *batch,
+                         const void *key, uint32_t key_size,
+                         uint32_t *kernel_out, void *prog_data_out);
+   bool (*upload_shader)(struct blorp_batch *batch,
+                         uint32_t stage,
+                         const void *key, uint32_t key_size,
+                         const void *kernel, uint32_t kernel_size,
+                         const void *prog_data,
+                         uint32_t prog_data_size,
+                         uint32_t *kernel_out, void *prog_data_out);
+   uint64_t (*get_surface_address)(struct blorp_batch *batch,
+                                   struct blorp_address addr);
+   void (*exec)(struct blorp_batch *batch, const struct blorp_params *params);
+
+   struct blorp_config config;
+};
+
+void blorp_init_brw(struct blorp_context *blorp, void *driver_ctx,
+                    struct isl_device *isl_dev, const struct brw_compiler *brw,
+                    const struct blorp_config *config);
+
+void blorp_init_elk(struct blorp_context *blorp, void *driver_ctx,
+                    struct isl_device *isl_dev, const struct elk_compiler *brw,
+                    const struct blorp_config *config);
+
+void blorp_finish(struct blorp_context *blorp);
+
+
+enum blorp_batch_flags {
+   /**
+    * This flag indicates that blorp should *not* re-emit the depth and
+    * stencil buffer packets.  Instead, the driver guarantees that all depth
+    * and stencil images passed in will match what is currently set in the
+    * hardware.
+    */
+   BLORP_BATCH_NO_EMIT_DEPTH_STENCIL = BITFIELD_BIT(0),
+
+   /* This flag indicates that the blorp call should be predicated. */
+   BLORP_BATCH_PREDICATE_ENABLE      = BITFIELD_BIT(1),
+
+   /* This flag indicates that blorp should use a compute program for the
+    * operation.
+    */
+   BLORP_BATCH_USE_COMPUTE           = BITFIELD_BIT(2),
+
+   /** Use the hardware blitter to perform any operations in this batch */
+   BLORP_BATCH_USE_BLITTER           = BITFIELD_BIT(3),
+
+   /** Wa_18038825448 */
+   BLORP_BATCH_FORCE_CPS_DEPENDENCY  = BITFIELD_BIT(4),
+
+   /** Emit 3DSTATE_VF
+    *
+    * Might be needed by the driver it enabled VF component packing
+    */
+   BLORP_BATCH_EMIT_3DSTATE_VF       = BITFIELD_BIT(5),
+
+   /** Disable geometry distribution
+    *
+    * Mostly for debug
+    */
+   BLORP_BATCH_DISABLE_VF_DISTRIBUTION = BITFIELD_BIT(6),
+
+   /** Source buffer is unpadded and needs careful accesses
+    */
+   BLORP_BATCH_SRC_UNPADDED          = BITFIELD_BIT(7),
+};
+
+struct blorp_batch {
+   struct blorp_context *blorp;
+   void *driver_batch;
+   enum blorp_batch_flags flags;
+};
+
+void blorp_batch_init(struct blorp_context *blorp, struct blorp_batch *batch,
+                      void *driver_batch, enum blorp_batch_flags flags);
+void blorp_batch_finish(struct blorp_batch *batch);
+
+static inline isl_surf_usage_flags_t
+blorp_batch_isl_copy_usage(const struct blorp_batch *batch, bool is_dest,
+                           bool _protected)
+{
+   isl_surf_usage_flags_t usage;
+
+   if (batch->flags & BLORP_BATCH_USE_COMPUTE)
+      usage = is_dest ? ISL_SURF_USAGE_STORAGE_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
+   else if (batch->flags & BLORP_BATCH_USE_BLITTER)
+      usage = is_dest ? ISL_SURF_USAGE_BLITTER_DST_BIT : ISL_SURF_USAGE_BLITTER_SRC_BIT;
+   else
+      usage = is_dest ? ISL_SURF_USAGE_RENDER_TARGET_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
+
+   if (_protected)
+      usage |= ISL_SURF_USAGE_PROTECTED_BIT;
+
+   return usage;
+}
+
+static inline bool
+blorp_address_is_null(struct blorp_address address)
+{
+   return address.buffer == NULL && address.offset == 0;
+}
+
+struct blorp_surf
+{
+   const struct isl_surf *surf;
+   struct blorp_address addr;
+
+   const struct isl_surf *aux_surf;
+   struct blorp_address aux_addr;
+   enum isl_aux_usage aux_usage;
+
+   union isl_color_value clear_color;
+
+   /**
+    * If set (bo != NULL), clear_color is ignored and the actual clear color
+    * is fetched from this address.  On gfx7-8, this is all of dword 7 of
+    * RENDER_SURFACE_STATE and is the responsibility of the caller to ensure
+    * that it contains a swizzle of RGBA and resource min LOD of 0.
+    */
+   struct blorp_address clear_color_addr;
+
+   /* Whether or not the indirect clear color contains a replicated pixel
+    * value. Allows blorp_copy() to widen the surface format of compressed
+    * sources for increased performance on gfx12.
+    */
+   bool has_replicated_pixel;
+
+   /* Only allowed for simple 2D non-MSAA surfaces */
+   uint32_t tile_x_sa, tile_y_sa;
+};
+
+enum blorp_filter {
+   BLORP_FILTER_NONE,
+   BLORP_FILTER_NEAREST,
+   BLORP_FILTER_BILINEAR,
+   BLORP_FILTER_SAMPLE_0,
+   BLORP_FILTER_AVERAGE,
+   BLORP_FILTER_MIN_SAMPLE,
+   BLORP_FILTER_MAX_SAMPLE,
+};
+
+void
+blorp_blit(struct blorp_batch *batch,
+           const struct blorp_surf *src_surf,
+           unsigned src_level, float src_layer,
+           enum isl_format src_format, struct isl_swizzle src_swizzle,
+           const struct blorp_surf *dst_surf,
+           unsigned dst_level, unsigned dst_layer,
+           enum isl_format dst_format, struct isl_swizzle dst_swizzle,
+           float src_x0, float src_y0,
+           float src_x1, float src_y1,
+           float dst_x0, float dst_y0,
+           float dst_x1, float dst_y1,
+           enum blorp_filter filter,
+           bool mirror_x, bool mirror_y);
+
+/* Returns the format the blorp_copy() call can be assumed to use if it
+ * receives a blorp surface which enables lossless compression.
+ */
+enum isl_format
+blorp_copy_get_color_format(const struct isl_device *isl_dev,
+                            enum isl_format surf_format);
+
+/* Returns the format the blorp_copy() call can be assumed to use if it
+ * receives a blorp surface which enables lossless compression.
+ */
+void
+blorp_copy_get_formats(const struct isl_device *isl_dev,
+                       const struct isl_surf *src_surf,
+                       const struct isl_surf *dst_surf,
+                       enum isl_format *src_view_format,
+                       enum isl_format *dst_view_format);
+
+void
+blorp_copy(struct blorp_batch *batch,
+           const struct blorp_surf *src_surf,
+           unsigned src_level, unsigned src_layer,
+           const struct blorp_surf *dst_surf,
+           unsigned dst_level, unsigned dst_layer,
+           uint32_t src_x, uint32_t src_y,
+           uint32_t dst_x, uint32_t dst_y,
+           uint32_t src_width, uint32_t src_height);
+
+void
+blorp_buffer_copy(struct blorp_batch *batch,
+                  struct blorp_address src,
+                  struct blorp_address dst,
+                  uint64_t size);
+
+void
+blorp_copy_memory_indirect(struct blorp_batch *batch,
+                           uint64_t indirect_buf_addr,
+                           uint32_t copy_count,
+                           uint64_t stride);
+
+void
+blorp_copy_memory_to_image_indirect(struct blorp_batch *batch,
+                                    const struct blorp_surf *img_blorp_surf,
+                                    uint64_t indirect_buf_addr,
+                                    uint64_t indirect_buf_stride,
+                                    uint32_t first_copy_idx,
+                                    uint32_t img_mip_level,
+                                    int layer_count,
+                                    int forced_layer_or_z);
+
+void
+blorp_fast_clear(struct blorp_batch *batch,
+                 const struct blorp_surf *surf,
+                 enum isl_format format, struct isl_swizzle swizzle,
+                 uint32_t level, uint32_t start_layer, uint32_t num_layers,
+                 uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1);
+
+bool
+blorp_clear_supports_compute(struct blorp_context *blorp,
+                             uint8_t color_write_disable, bool blend_enabled,
+                             enum isl_aux_usage aux_usage);
+
+bool
+blorp_clear_supports_blitter(struct blorp_context *blorp,
+                             const struct blorp_surf *surf,
+                             uint8_t color_write_disable, bool blend_enabled);
+
+bool
+blorp_copy_supports_compute(struct blorp_context *blorp,
+                            const struct isl_surf *src_surf,
+                            const struct isl_surf *dst_surf,
+                            enum isl_aux_usage dst_aux_usage);
+
+bool
+blorp_blit_supports_compute(struct blorp_context *blorp,
+                            const struct isl_surf *src_surf,
+                            const struct isl_surf *dst_surf,
+                            enum isl_aux_usage dst_aux_usage);
+
+bool
+blorp_copy_supports_blitter(struct blorp_context *blorp,
+                            const struct isl_surf *src_surf,
+                            const struct isl_surf *dst_surf,
+                            enum isl_aux_usage src_aux_usage,
+                            enum isl_aux_usage dst_aux_usage);
+
+void
+blorp_clear(struct blorp_batch *batch,
+            const struct blorp_surf *surf,
+            enum isl_format format, struct isl_swizzle swizzle,
+            uint32_t level, uint32_t start_layer, uint32_t num_layers,
+            uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
+            union isl_color_value clear_color,
+            uint8_t color_write_disable);
+
+void
+blorp_clear_depth_stencil(struct blorp_batch *batch,
+                          const struct blorp_surf *depth,
+                          const struct blorp_surf *stencil,
+                          uint32_t level, uint32_t start_layer,
+                          uint32_t num_layers,
+                          uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
+                          bool clear_depth, float depth_value,
+                          uint8_t stencil_mask, uint8_t stencil_value);
+
+void
+blorp_hiz_clear_depth_stencil(struct blorp_batch *batch,
+                              const struct blorp_surf *depth,
+                              const struct blorp_surf *stencil,
+                              uint32_t level,
+                              uint32_t start_layer, uint32_t num_layers,
+                              uint32_t x0, uint32_t y0,
+                              uint32_t x1, uint32_t y1,
+                              bool clear_depth, float depth_value,
+                              bool clear_stencil, uint8_t stencil_value);
+void
+blorp_clear_attachments(struct blorp_batch *batch,
+                        uint32_t binding_table_offset,
+                        enum isl_format depth_format,
+                        uint32_t num_samples,
+                        uint32_t start_layer, uint32_t num_layers,
+                        uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
+                        bool clear_color, union isl_color_value color_value,
+                        bool clear_depth, float depth_value,
+                        uint8_t stencil_mask, uint8_t stencil_value);
+
+void
+blorp_ccs_resolve(struct blorp_batch *batch,
+                  struct blorp_surf *surf, uint32_t level,
+                  uint32_t start_layer, uint32_t num_layers,
+                  enum isl_format format,
+                  enum isl_aux_op resolve_op);
+
+void
+blorp_ccs_ambiguate(struct blorp_batch *batch,
+                    struct blorp_surf *surf,
+                    uint32_t level, uint32_t layer);
+
+void
+blorp_mcs_partial_resolve(struct blorp_batch *batch,
+                          struct blorp_surf *surf,
+                          enum isl_format format,
+                          uint32_t start_layer, uint32_t num_layers);
+
+void
+blorp_mcs_ambiguate(struct blorp_batch *batch,
+                    struct blorp_surf *surf,
+                    uint32_t start_layer, uint32_t num_layers);
+
+void
+blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
+             uint32_t level, uint32_t start_layer, uint32_t num_layers,
+             enum isl_aux_op op);
+
+#ifdef __cplusplus
+} /* end extern "C" */
+#endif /* __cplusplus */
+
+#endif /* BLORP_H */

src/intel/blorp/blorp_brw.c

@@ -0,0 +1,369 @@
+/*
+ * Copyright 2012 Intel Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "blorp_priv.h"
+#include "blorp_nir_builder.h"
+#include "brw/brw_compiler.h"
+#include "brw/brw_nir.h"
+#include "dev/intel_debug.h"
+
+static debug_archiver *
+blorp_debug_archiver_open(void *mem_ctx,
+                         const struct nir_shader *nir,
+                         const void *key,
+                         unsigned key_size)
+{
+   if (!INTEL_DEBUG(DEBUG_MDA) || !INTEL_DEBUG(DEBUG_BLORP))
+      return NULL;
+
+   uint8_t blake3[BLAKE3_KEY_LEN];
+   _mesa_blake3_compute(key, key_size, blake3);
+   char name[BLAKE3_HEX_LEN + 6] = {};
+   _mesa_blake3_format(name, blake3);
+   memcpy(&name[BLAKE3_HEX_LEN - 1], ".blorp", 6);
+
+   debug_archiver *archiver = debug_archiver_open(mem_ctx, name, "blorp");
+   debug_archiver_set_prefix(
+      archiver,
+      _mesa_shader_stage_to_abbrev(nir->info.stage));
+
+   return archiver;
+}
+
+static const nir_shader_compiler_options *
+blorp_nir_options_brw(struct blorp_context *blorp,
+                      mesa_shader_stage stage)
+{
+   const struct brw_compiler *compiler = blorp->compiler->brw;
+   return &compiler->nir_options[stage];
+}
+
+static struct blorp_program
+blorp_compile_fs_brw(struct blorp_context *blorp, void *mem_ctx,
+                     struct nir_shader *nir,
+                     bool multisample_fbo,
+                     bool is_fast_clear,
+                     bool use_repclear,
+                     const void *key, uint32_t key_size)
+{
+   const struct brw_compiler *compiler = blorp->compiler->brw;
+
+   struct brw_fs_prog_data *fs_prog_data = rzalloc(mem_ctx, struct brw_fs_prog_data);
+
+   nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+
+   struct brw_nir_compiler_opts opts = {
+      .softfp64 = ((nir->info.bit_sizes_float & 64) &&
+                   !compiler->devinfo->has_64bit_float) ?
+                  blorp->get_fp64_nir(blorp) : NULL,
+   };
+   brw_preprocess_nir(compiler, nir, &opts);
+   nir_remove_dead_variables(nir, nir_var_shader_in, NULL);
+   nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+   if (is_fast_clear || use_repclear) {
+      nir->info.api_subgroup_size = 16;
+      nir->info.max_subgroup_size = 16;
+      nir->info.min_subgroup_size = 16;
+   }
+
+   struct brw_fs_prog_key wm_key;
+   memset(&wm_key, 0, sizeof(wm_key));
+   wm_key.multisample_fbo = multisample_fbo ? INTEL_ALWAYS : INTEL_NEVER;
+   wm_key.nr_color_regions = 1;
+
+   debug_archiver *archiver =
+      blorp_debug_archiver_open(mem_ctx, nir, key, key_size);
+
+   struct brw_compile_fs_params params = {
+      .base = {
+         .mem_ctx = mem_ctx,
+         .nir = nir,
+         .key = &wm_key.base,
+         .prog_data = (struct brw_stage_prog_data *)fs_prog_data,
+         .log_data = blorp->driver_ctx,
+         .debug_flag = DEBUG_BLORP,
+         .archiver = archiver,
+      },
+
+      .use_rep_send = use_repclear,
+      .max_polygons = 1,
+   };
+
+   const unsigned *kernel = brw_compile(compiler, &params.base);
+
+   debug_archiver_close(archiver);
+
+   return (struct blorp_program){
+      .kernel         = kernel,
+      .kernel_size    = fs_prog_data->base.program_size,
+      .prog_data      = fs_prog_data,
+      .prog_data_size = sizeof(*fs_prog_data),
+   };
+}
+
+static struct blorp_program
+blorp_compile_vs_brw(struct blorp_context *blorp, void *mem_ctx,
+                     struct nir_shader *nir,
+                     const void *key, uint32_t key_size)
+{
+   const struct brw_compiler *compiler = blorp->compiler->brw;
+
+   struct brw_nir_compiler_opts opts = {};
+   brw_preprocess_nir(compiler, nir, &opts);
+   nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+
+   struct brw_vs_prog_data *vs_prog_data = rzalloc(mem_ctx, struct brw_vs_prog_data);
+   vs_prog_data->inputs_read = nir->info.inputs_read;
+
+   brw_compute_vue_map(compiler->devinfo,
+                       &vs_prog_data->base.vue_map,
+                       nir->info.outputs_written,
+                       nir->info.separate_shader,
+                       1);
+
+   struct brw_vs_prog_key vs_key = { 0, };
+
+   debug_archiver *archiver =
+      blorp_debug_archiver_open(mem_ctx, nir, key, key_size);
+
+   struct brw_compile_vs_params params = {
+      .base = {
+         .mem_ctx = mem_ctx,
+         .nir = nir,
+         .key = &vs_key.base,
+         .prog_data = (struct brw_stage_prog_data *)vs_prog_data,
+         .log_data = blorp->driver_ctx,
+         .debug_flag = DEBUG_BLORP,
+         .archiver = archiver,
+      },
+   };
+
+   const unsigned *kernel = brw_compile(compiler, &params.base);
+
+   debug_archiver_close(archiver);
+
+   return (struct blorp_program) {
+      .kernel         = kernel,
+      .kernel_size    = vs_prog_data->base.base.program_size,
+      .prog_data      = vs_prog_data,
+      .prog_data_size = sizeof(*vs_prog_data),
+   };
+}
+
+static bool
+lower_base_workgroup_id(nir_builder *b, nir_intrinsic_instr *intrin,
+                        UNUSED void *data)
+{
+   if (intrin->intrinsic != nir_intrinsic_load_base_workgroup_id)
+      return false;
+
+   b->cursor = nir_instr_remove(&intrin->instr);
+   nir_def_rewrite_uses(&intrin->def, nir_imm_zero(b, 3, 32));
+   return true;
+}
+
+static bool
+lower_load_uniform(nir_builder *b, nir_intrinsic_instr *intrin, void *data)
+{
+   if (intrin->intrinsic != nir_intrinsic_load_uniform)
+      return false;
+
+   const struct intel_device_info *devinfo = data;
+
+   b->cursor = nir_instr_remove(&intrin->instr);
+   nir_def *value;
+   if (b->shader->info.stage == MESA_SHADER_COMPUTE &&
+       devinfo->verx10 >= 125) {
+      value = nir_load_shader_indirect_data_intel(
+         b,
+         intrin->def.num_components,
+         intrin->def.bit_size,
+         nir_iadd(b, nir_load_indirect_address_intel(b), intrin->src[0].ssa),
+         .base = nir_intrinsic_base(intrin),
+         .range = nir_intrinsic_range(intrin));
+   } else {
+      value = nir_load_push_data_intel(b,
+                                       intrin->def.num_components,
+                                       intrin->def.bit_size,
+                                       intrin->src[0].ssa,
+                                       .base = nir_intrinsic_base(intrin),
+                                       .range = nir_intrinsic_range(intrin));
+   }
+   nir_def_rewrite_uses(&intrin->def, value);
+   return true;
+}
+
+static struct blorp_program
+blorp_compile_cs_brw(struct blorp_context *blorp, void *mem_ctx,
+                     struct nir_shader *nir,
+                     const void *key, uint32_t key_size)
+{
+   const struct brw_compiler *compiler = blorp->compiler->brw;
+
+   struct brw_nir_compiler_opts opts = {};
+   brw_preprocess_nir(compiler, nir, &opts);
+   nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+
+   NIR_PASS(_, nir, nir_lower_io, nir_var_uniform, type_size_scalar_bytes,
+              (nir_lower_io_options)0);
+
+   NIR_PASS(_, nir, nir_shader_intrinsics_pass, lower_load_uniform,
+               nir_metadata_control_flow, (void *) compiler->devinfo);
+
+   STATIC_ASSERT(offsetof(struct blorp_wm_inputs, subgroup_id) + 4 ==
+                 sizeof(struct blorp_wm_inputs));
+
+   struct brw_cs_prog_data *cs_prog_data = rzalloc(mem_ctx, struct brw_cs_prog_data);
+   cs_prog_data->base.push_sizes[0] = sizeof(struct blorp_wm_inputs);
+
+   brw_cs_fill_push_const_info(compiler->devinfo, cs_prog_data,
+                               offsetof(struct blorp_wm_inputs, subgroup_id) / 4);
+   cs_prog_data->base.push_sizes[0] = align(cs_prog_data->base.push_sizes[0], REG_SIZE);
+
+   NIR_PASS(_, nir, brw_nir_lower_cs_intrinsics, compiler->devinfo,
+              cs_prog_data);
+   NIR_PASS(_, nir, brw_nir_lower_cs_subgroup_id, compiler->devinfo,
+               offsetof(struct blorp_wm_inputs, subgroup_id));
+   NIR_PASS(_, nir, nir_shader_intrinsics_pass, lower_base_workgroup_id,
+               nir_metadata_control_flow, NULL);
+
+   struct brw_cs_prog_key cs_key;
+   memset(&cs_key, 0, sizeof(cs_key));
+
+   debug_archiver *archiver =
+      blorp_debug_archiver_open(mem_ctx, nir, key, key_size);
+
+   struct brw_compile_cs_params params = {
+      .base = {
+         .mem_ctx = mem_ctx,
+         .nir = nir,
+         .key = &cs_key.base,
+         .prog_data = (struct brw_stage_prog_data *)cs_prog_data,
+         .log_data = blorp->driver_ctx,
+         .debug_flag = DEBUG_BLORP,
+         .archiver = archiver,
+      },
+   };
+
+   const unsigned *kernel = brw_compile(compiler, &params.base);
+
+   debug_archiver_close(archiver);
+
+   return (struct blorp_program) {
+      .kernel         = kernel,
+      .kernel_size    = cs_prog_data->base.program_size,
+      .prog_data      = cs_prog_data,
+      .prog_data_size = sizeof(*cs_prog_data),
+   };
+}
+
+#pragma pack(push, 1)
+struct layer_offset_vs_key {
+   struct blorp_base_key base;
+   unsigned num_inputs;
+};
+#pragma pack(pop)
+
+/* In the case of doing attachment clears, we are using a surface state that
+ * is handed to us so we can't set (and don't even know) the base array layer.
+ * In order to do a layered clear in this scenario, we need some way of adding
+ * the base array layer to the instance id.  Unfortunately, our hardware has
+ * no real concept of "base instance", so we have to do it manually in a
+ * vertex shader.
+ */
+static bool
+blorp_params_get_layer_offset_vs_brw(struct blorp_batch *batch,
+                                     struct blorp_params *params)
+{
+   struct blorp_context *blorp = batch->blorp;
+   struct layer_offset_vs_key blorp_key = {
+      .base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_LAYER_OFFSET_VS),
+   };
+
+   struct brw_fs_prog_data *fs_prog_data = params->fs_prog_data;
+   if (fs_prog_data)
+      blorp_key.num_inputs = fs_prog_data->num_varying_inputs;
+
+   if (blorp->lookup_shader(batch, &blorp_key, sizeof(blorp_key),
+                            &params->vs_prog_kernel, &params->vs_prog_data))
+      return true;
+
+   void *mem_ctx = ralloc_context(NULL);
+
+   nir_builder b;
+   blorp_nir_init_shader(&b, blorp, mem_ctx, MESA_SHADER_VERTEX,
+                         blorp_shader_type_to_name(blorp_key.base.shader_type));
+
+   const struct glsl_type *uvec4_type = glsl_vector_type(GLSL_TYPE_UINT, 4);
+
+   /* First we deal with the header which has instance and base instance */
+   nir_variable *a_header = nir_variable_create(b.shader, nir_var_shader_in,
+                                                uvec4_type, "header");
+   a_header->data.location = VERT_ATTRIB_GENERIC0;
+
+   nir_variable *v_layer = nir_variable_create(b.shader, nir_var_shader_out,
+                                               glsl_int_type(), "layer_id");
+   v_layer->data.location = VARYING_SLOT_LAYER;
+
+   /* Compute the layer id */
+   nir_def *header = nir_load_var(&b, a_header);
+   nir_def *base_layer = nir_channel(&b, header, 0);
+   nir_def *instance = nir_channel(&b, header, 1);
+   nir_store_var(&b, v_layer, nir_iadd(&b, instance, base_layer), 0x1);
+
+   /* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
+   nir_variable *a_vertex = nir_variable_create(b.shader, nir_var_shader_in,
+                                                glsl_vec4_type(), "a_vertex");
+   a_vertex->data.location = VERT_ATTRIB_GENERIC1;
+
+   nir_variable *v_pos = nir_variable_create(b.shader, nir_var_shader_out,
+                                             glsl_vec4_type(), "v_pos");
+   v_pos->data.location = VARYING_SLOT_POS;
+
+   nir_copy_var(&b, v_pos, a_vertex);
+
+   /* Then we copy everything else */
+   for (unsigned i = 0; i < blorp_key.num_inputs; i++) {
+      nir_variable *a_in = nir_variable_create(b.shader, nir_var_shader_in,
+                                               uvec4_type, "input");
+      a_in->data.location = VERT_ATTRIB_GENERIC2 + i;
+
+      nir_variable *v_out = nir_variable_create(b.shader, nir_var_shader_out,
+                                                uvec4_type, "output");
+      v_out->data.location = VARYING_SLOT_VAR0 + i;
+
+      nir_copy_var(&b, v_out, a_in);
+   }
+
+   const struct blorp_program p =
+      blorp_compile_vs(blorp, mem_ctx, b.shader, &blorp_key, sizeof(blorp_key));
+
+   bool result =
+      blorp->upload_shader(batch, MESA_SHADER_VERTEX,
+                           &blorp_key, sizeof(blorp_key),
+                           p.kernel, p.kernel_size,
+                           p.prog_data, p.prog_data_size,
+                           &params->vs_prog_kernel, &params->vs_prog_data);
+
+   ralloc_free(mem_ctx);
+   return result;
+}
+
+void
+blorp_init_brw(struct blorp_context *blorp, void *driver_ctx,
+               struct isl_device *isl_dev, const struct brw_compiler *brw,
+               const struct blorp_config *config)
+{
+   blorp_init(blorp, driver_ctx, isl_dev, config);
+   assert(brw);
+
+   blorp->compiler->brw = brw;
+   blorp->compiler->nir_options = blorp_nir_options_brw;
+   blorp->compiler->compile_fs = blorp_compile_fs_brw;
+   blorp->compiler->compile_vs = blorp_compile_vs_brw;
+   blorp->compiler->compile_cs = blorp_compile_cs_brw;
+   blorp->compiler->params_get_layer_offset_vs =
+      blorp_params_get_layer_offset_vs_brw;
+}

src/intel/blorp/blorp_elk.c

@@ -0,0 +1,360 @@
+/*
+ * Copyright 2012 Intel Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "blorp_priv.h"
+#include "blorp_nir_builder.h"
+#include "compiler/elk/elk_compiler.h"
+#include "compiler/elk/elk_nir.h"
+#include "compiler/intel_nir.h"
+#include "dev/intel_debug.h"
+
+static const nir_shader_compiler_options *
+blorp_nir_options_elk(struct blorp_context *blorp,
+                      mesa_shader_stage stage)
+{
+   const struct elk_compiler *compiler = blorp->compiler->elk;
+   return compiler->nir_options[stage];
+}
+
+static struct blorp_program
+blorp_compile_fs_elk(struct blorp_context *blorp, void *mem_ctx,
+                     struct nir_shader *nir,
+                     bool multisample_fbo,
+                     bool is_fast_clear,
+                     bool use_repclear,
+                     const void *key, uint32_t key_size)
+{
+   const struct elk_compiler *compiler = blorp->compiler->elk;
+
+   struct elk_fs_prog_data *fs_prog_data = rzalloc(mem_ctx, struct elk_fs_prog_data);
+   fs_prog_data->base.nr_params = 0;
+   fs_prog_data->base.param = NULL;
+
+   struct elk_nir_compiler_opts opts = {};
+   elk_preprocess_nir(compiler, nir, &opts);
+   nir_remove_dead_variables(nir, nir_var_shader_in, NULL);
+   nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+
+   struct elk_fs_prog_key wm_key;
+   memset(&wm_key, 0, sizeof(wm_key));
+   wm_key.multisample_fbo = multisample_fbo ? ELK_ALWAYS : ELK_NEVER;
+   wm_key.nr_color_regions = 1;
+
+   if (compiler->devinfo->ver < 6) {
+      if (nir->info.fs.uses_discard)
+         wm_key.iz_lookup |= ELK_WM_IZ_PS_KILL_ALPHATEST_BIT;
+
+      wm_key.input_slots_valid = nir->info.inputs_read | VARYING_BIT_POS;
+   }
+
+   struct elk_compile_fs_params params = {
+      .base = {
+         .mem_ctx = mem_ctx,
+         .nir = nir,
+         .log_data = blorp->driver_ctx,
+         .debug_flag = DEBUG_BLORP,
+      },
+      .key = &wm_key,
+      .prog_data = fs_prog_data,
+
+      .use_rep_send = use_repclear,
+      .max_polygons = 1,
+   };
+
+   const unsigned *kernel = elk_compile_fs(compiler, &params);
+   return (struct blorp_program){
+      .kernel         = kernel,
+      .kernel_size    = fs_prog_data->base.program_size,
+      .prog_data      = fs_prog_data,
+      .prog_data_size = sizeof(*fs_prog_data),
+   };
+}
+
+static struct blorp_program
+blorp_compile_vs_elk(struct blorp_context *blorp, void *mem_ctx,
+                     struct nir_shader *nir,
+                     const void *key, uint32_t key_size)
+{
+   const struct elk_compiler *compiler = blorp->compiler->elk;
+
+   struct elk_nir_compiler_opts opts = {};
+   elk_preprocess_nir(compiler, nir, &opts);
+   nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+
+   struct elk_vs_prog_data *vs_prog_data = rzalloc(mem_ctx, struct elk_vs_prog_data);
+   vs_prog_data->inputs_read = nir->info.inputs_read;
+
+   elk_compute_vue_map(compiler->devinfo,
+                       &vs_prog_data->base.vue_map,
+                       nir->info.outputs_written,
+                       nir->info.separate_shader ?
+                       INTEL_VUE_LAYOUT_SEPARATE :
+                       INTEL_VUE_LAYOUT_FIXED,
+                       1);
+
+   struct elk_vs_prog_key vs_key = { 0, };
+
+   struct elk_compile_vs_params params = {
+      .base = {
+         .mem_ctx = mem_ctx,
+         .nir = nir,
+         .log_data = blorp->driver_ctx,
+         .debug_flag = DEBUG_BLORP,
+      },
+      .key = &vs_key,
+      .prog_data = vs_prog_data,
+   };
+
+   const unsigned *kernel = elk_compile_vs(compiler, &params);
+   return (struct blorp_program) {
+      .kernel         = kernel,
+      .kernel_size    = vs_prog_data->base.base.program_size,
+      .prog_data      = vs_prog_data,
+      .prog_data_size = sizeof(*vs_prog_data),
+   };
+}
+
+static bool
+lower_base_workgroup_id(nir_builder *b, nir_intrinsic_instr *intrin,
+                        UNUSED void *data)
+{
+   if (intrin->intrinsic != nir_intrinsic_load_base_workgroup_id)
+      return false;
+
+   b->cursor = nir_instr_remove(&intrin->instr);
+   nir_def_rewrite_uses(&intrin->def, nir_imm_zero(b, 3, 32));
+   return true;
+}
+
+static struct blorp_program
+blorp_compile_cs_elk(struct blorp_context *blorp, void *mem_ctx,
+                     struct nir_shader *nir,
+                     const void *key, uint32_t key_size)
+{
+   const struct elk_compiler *compiler = blorp->compiler->elk;
+
+   struct elk_nir_compiler_opts opts = {};
+   elk_preprocess_nir(compiler, nir, &opts);
+   nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+
+   NIR_PASS(_, nir, nir_lower_io, nir_var_uniform, elk_type_size_scalar_bytes,
+              (nir_lower_io_options)0);
+
+   STATIC_ASSERT(offsetof(struct blorp_wm_inputs, subgroup_id) + 4 ==
+                 sizeof(struct blorp_wm_inputs));
+   nir->num_uniforms = offsetof(struct blorp_wm_inputs, subgroup_id);
+   unsigned nr_params = nir->num_uniforms / 4;
+
+   struct elk_cs_prog_data *cs_prog_data = rzalloc(mem_ctx, struct elk_cs_prog_data);
+   cs_prog_data->base.nr_params = nr_params;
+   cs_prog_data->base.param = rzalloc_array(NULL, uint32_t, nr_params);
+
+   NIR_PASS(_, nir, elk_nir_lower_cs_intrinsics, compiler->devinfo,
+              cs_prog_data);
+   NIR_PASS(_, nir, nir_shader_intrinsics_pass, lower_base_workgroup_id,
+              nir_metadata_control_flow, NULL);
+
+   struct elk_cs_prog_key cs_key;
+   memset(&cs_key, 0, sizeof(cs_key));
+
+   struct elk_compile_cs_params params = {
+      .base = {
+         .mem_ctx = mem_ctx,
+         .nir = nir,
+         .log_data = blorp->driver_ctx,
+         .debug_flag = DEBUG_BLORP,
+      },
+      .key = &cs_key,
+      .prog_data = cs_prog_data,
+   };
+
+   const unsigned *kernel = elk_compile_cs(compiler, &params);
+
+   ralloc_free(cs_prog_data->base.param);
+   cs_prog_data->base.param = NULL;
+
+   return (struct blorp_program) {
+      .kernel         = kernel,
+      .kernel_size    = cs_prog_data->base.program_size,
+      .prog_data      = cs_prog_data,
+      .prog_data_size = sizeof(*cs_prog_data),
+   };
+}
+
+struct blorp_sf_key {
+   struct blorp_base_key base;
+   struct elk_sf_prog_key key;
+};
+
+static bool
+blorp_ensure_sf_program_elk(struct blorp_batch *batch,
+                            struct blorp_params *params)
+{
+   struct blorp_context *blorp = batch->blorp;
+   const struct elk_compiler *compiler = blorp->compiler->elk;
+   const struct elk_fs_prog_data *fs_prog_data = params->fs_prog_data;
+   assert(params->fs_prog_data);
+
+   /* Gfx6+ doesn't need a strips and fans program */
+   if (compiler->devinfo->ver >= 6)
+      return true;
+
+   struct blorp_sf_key key = {
+      .base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_GFX4_SF),
+   };
+
+   /* Everything gets compacted in vertex setup, so we just need a
+    * pass-through for the correct number of input varyings.
+    */
+   const uint64_t slots_valid = VARYING_BIT_POS |
+      ((1ull << fs_prog_data->num_varying_inputs) - 1) << VARYING_SLOT_VAR0;
+
+   key.key.attrs = slots_valid;
+   key.key.primitive = ELK_SF_PRIM_TRIANGLES;
+   key.key.contains_flat_varying = fs_prog_data->contains_flat_varying;
+
+   STATIC_ASSERT(sizeof(key.key.interp_mode) ==
+                 sizeof(fs_prog_data->interp_mode));
+   memcpy(key.key.interp_mode, fs_prog_data->interp_mode,
+          sizeof(key.key.interp_mode));
+
+   if (blorp->lookup_shader(batch, &key, sizeof(key),
+                            &params->sf_prog_kernel, &params->sf_prog_data))
+      return true;
+
+   void *mem_ctx = ralloc_context(NULL);
+
+   const unsigned *program;
+   unsigned program_size;
+
+   /* Some fields that are not set can be read in debug paths, so initialization is required */
+   struct intel_vue_map vue_map = {0};
+   elk_compute_vue_map(compiler->devinfo, &vue_map, slots_valid,
+                       INTEL_VUE_LAYOUT_FIXED, 1);
+
+   struct elk_sf_prog_data prog_data_tmp;
+   program = elk_compile_sf(compiler, mem_ctx, &key.key,
+                            &prog_data_tmp, &vue_map, &program_size);
+
+   bool result =
+      blorp->upload_shader(batch, MESA_SHADER_NONE,
+                           &key, sizeof(key), program, program_size,
+                           (void *)&prog_data_tmp, sizeof(prog_data_tmp),
+                           &params->sf_prog_kernel, &params->sf_prog_data);
+
+   ralloc_free(mem_ctx);
+
+   return result;
+}
+
+#pragma pack(push, 1)
+struct layer_offset_vs_key {
+   struct blorp_base_key base;
+   unsigned num_inputs;
+};
+#pragma pack(pop)
+
+/* In the case of doing attachment clears, we are using a surface state that
+ * is handed to us so we can't set (and don't even know) the base array layer.
+ * In order to do a layered clear in this scenario, we need some way of adding
+ * the base array layer to the instance id.  Unfortunately, our hardware has
+ * no real concept of "base instance", so we have to do it manually in a
+ * vertex shader.
+ */
+static bool
+blorp_params_get_layer_offset_vs_elk(struct blorp_batch *batch,
+                                     struct blorp_params *params)
+{
+   struct blorp_context *blorp = batch->blorp;
+   struct layer_offset_vs_key blorp_key = {
+      .base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_LAYER_OFFSET_VS),
+   };
+
+   struct elk_fs_prog_data *fs_prog_data = params->fs_prog_data;
+   if (fs_prog_data)
+      blorp_key.num_inputs = fs_prog_data->num_varying_inputs;
+
+   if (blorp->lookup_shader(batch, &blorp_key, sizeof(blorp_key),
+                            &params->vs_prog_kernel, &params->vs_prog_data))
+      return true;
+
+   void *mem_ctx = ralloc_context(NULL);
+
+   nir_builder b;
+   blorp_nir_init_shader(&b, blorp, mem_ctx, MESA_SHADER_VERTEX,
+                         blorp_shader_type_to_name(blorp_key.base.shader_type));
+
+   const struct glsl_type *uvec4_type = glsl_vector_type(GLSL_TYPE_UINT, 4);
+
+   /* First we deal with the header which has instance and base instance */
+   nir_variable *a_header = nir_variable_create(b.shader, nir_var_shader_in,
+                                                uvec4_type, "header");
+   a_header->data.location = VERT_ATTRIB_GENERIC0;
+
+   nir_variable *v_layer = nir_variable_create(b.shader, nir_var_shader_out,
+                                               glsl_int_type(), "layer_id");
+   v_layer->data.location = VARYING_SLOT_LAYER;
+
+   /* Compute the layer id */
+   nir_def *header = nir_load_var(&b, a_header);
+   nir_def *base_layer = nir_channel(&b, header, 0);
+   nir_def *instance = nir_channel(&b, header, 1);
+   nir_store_var(&b, v_layer, nir_iadd(&b, instance, base_layer), 0x1);
+
+   /* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
+   nir_variable *a_vertex = nir_variable_create(b.shader, nir_var_shader_in,
+                                                glsl_vec4_type(), "a_vertex");
+   a_vertex->data.location = VERT_ATTRIB_GENERIC1;
+
+   nir_variable *v_pos = nir_variable_create(b.shader, nir_var_shader_out,
+                                             glsl_vec4_type(), "v_pos");
+   v_pos->data.location = VARYING_SLOT_POS;
+
+   nir_copy_var(&b, v_pos, a_vertex);
+
+   /* Then we copy everything else */
+   for (unsigned i = 0; i < blorp_key.num_inputs; i++) {
+      nir_variable *a_in = nir_variable_create(b.shader, nir_var_shader_in,
+                                               uvec4_type, "input");
+      a_in->data.location = VERT_ATTRIB_GENERIC2 + i;
+
+      nir_variable *v_out = nir_variable_create(b.shader, nir_var_shader_out,
+                                                uvec4_type, "output");
+      v_out->data.location = VARYING_SLOT_VAR0 + i;
+
+      nir_copy_var(&b, v_out, a_in);
+   }
+
+   const struct blorp_program p =
+      blorp_compile_vs(blorp, mem_ctx, b.shader, &blorp_key, sizeof(blorp_key));
+
+   bool result =
+      blorp->upload_shader(batch, MESA_SHADER_VERTEX,
+                           &blorp_key, sizeof(blorp_key),
+                           p.kernel, p.kernel_size,
+                           p.prog_data, p.prog_data_size,
+                           &params->vs_prog_kernel, &params->vs_prog_data);
+
+   ralloc_free(mem_ctx);
+   return result;
+}
+
+void
+blorp_init_elk(struct blorp_context *blorp, void *driver_ctx,
+               struct isl_device *isl_dev, const struct elk_compiler *elk,
+               const struct blorp_config *config)
+{
+   blorp_init(blorp, driver_ctx, isl_dev, config);
+   assert(elk);
+
+   blorp->compiler->elk = elk;
+   blorp->compiler->nir_options = blorp_nir_options_elk;
+   blorp->compiler->compile_fs = blorp_compile_fs_elk;
+   blorp->compiler->compile_vs = blorp_compile_vs_elk;
+   blorp->compiler->compile_cs = blorp_compile_cs_elk;
+   blorp->compiler->ensure_sf_program = blorp_ensure_sf_program_elk;
+   blorp->compiler->params_get_layer_offset_vs =
+      blorp_params_get_layer_offset_vs_elk;
+}

src/intel/blorp/blorp_indirect_copy.c

@@ -0,0 +1,373 @@
+/* Copyright © 2025 Intel Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "blorp_nir_builder.h"
+
+#include "blorp_priv.h"
+#include "blorp_shaders.h"
+
+struct blorp_indirect_copy_mem2img_key {
+   struct blorp_base_key base;
+
+   /* How many dimensions does our image have? 1, 2 or 3. */
+   uint32_t dimensions;
+
+   /* When compressed formats are used, we pretend they are a non-compressed
+    * format, of the same bpb. Since we can't maintain the exact same layout
+    * of mipmap and layer offsets, we're forced to make adjustments to where X
+    * and Y actually start, and are also forced to copy only one layer (or Z
+    * axis position) per shader invocation.
+    */
+   int forced_layer_or_z;
+
+   /* Info taken from isl_format_layout. */
+   uint16_t format_Bpb;
+   uint16_t format_bw;
+   uint16_t format_bh;
+   uint16_t format_bd;
+};
+
+/* Refer to struct blorp_wm_inputs_indirect. */
+struct blorp_indirect_vars {
+   nir_variable *indirect_buf_addr;
+   nir_variable *stride;
+   nir_variable *copy_count;
+   nir_variable *copy_idx;
+   nir_variable *max_layer;
+   nir_variable *x_offset;
+   nir_variable *y_offset;
+};
+
+static enum isl_format
+get_format_for_copy(int format_bpb)
+{
+   switch (format_bpb) {
+   case 8:   return ISL_FORMAT_R8_UINT;
+   case 16:  return ISL_FORMAT_R16_UINT;
+   case 24:  return ISL_FORMAT_R8G8B8_UINT;
+   case 32:  return ISL_FORMAT_R32_UINT;
+   case 48:  return ISL_FORMAT_R16G16B16_UINT;
+   case 64:  return ISL_FORMAT_R32G32_UINT;
+   case 96:  return ISL_FORMAT_R32G32B32_UINT;
+   case 128: return ISL_FORMAT_R32G32B32A32_UINT;
+   default:
+      mesa_loge("unexpected format bpb: %d", format_bpb);
+      assert(false);
+      return ISL_FORMAT_UNSUPPORTED;
+   }
+}
+
+static void
+blorp_indirect_vars_init(nir_builder *b, struct blorp_indirect_vars *v)
+{
+   v->copy_count =
+      BLORP_CREATE_NIR_INPUT(b->shader, indirect.copy_count,
+                             glsl_uint_type());
+   v->indirect_buf_addr =
+      BLORP_CREATE_NIR_INPUT(b->shader, indirect.indirect_buf_addr,
+                             glsl_uint64_t_type());
+   v->stride =
+      BLORP_CREATE_NIR_INPUT(b->shader, indirect.indirect_buf_stride,
+                             glsl_uint64_t_type());
+   v->copy_idx =
+      BLORP_CREATE_NIR_INPUT(b->shader, indirect.copy_idx,
+                             glsl_uint_type());
+   v->max_layer =
+      BLORP_CREATE_NIR_INPUT(b->shader, indirect.max_layer,
+                             glsl_uint_type());
+   v->x_offset =
+      BLORP_CREATE_NIR_INPUT(b->shader, indirect.x_offset,
+                             glsl_uint_type());
+   v->y_offset =
+      BLORP_CREATE_NIR_INPUT(b->shader, indirect.y_offset,
+                             glsl_uint_type());
+}
+
+static nir_shader *
+blorp_build_copy_mem_indirect_shader(struct blorp_batch *batch,
+                                     void *mem_ctx)
+{
+
+   struct blorp_context *blorp = batch->blorp;
+
+   mesa_shader_stage stage = MESA_SHADER_COMPUTE;
+   const nir_shader_compiler_options *nir_options =
+      blorp->compiler->nir_options(blorp, stage);
+   nir_builder b = nir_builder_init_simple_shader(stage, nir_options,
+                                                  "copy mem indirect");
+   ralloc_steal(mem_ctx, b.shader);
+
+   b.shader->info.workgroup_size[0] = 32;
+   b.shader->info.workgroup_size[1] = 1;
+   b.shader->info.workgroup_size[2] = 1;
+
+   struct blorp_indirect_vars v;
+   blorp_indirect_vars_init(&b, &v);
+
+   /* The indirect buffer is an array containing 'copy_count'
+    * VkCopyMemoryIndirectCommandKHR structures, separated by 'stride' bytes.
+    */
+   nir_def *copy_count = nir_load_var(&b, v.copy_count);
+   nir_def *indirect_buf_addr = nir_load_var(&b, v.indirect_buf_addr);
+   nir_def *stride = nir_load_var(&b, v.stride);
+   nir_def *global_id =
+      nir_channel(&b, nir_load_global_invocation_id(&b, 32), 0);
+
+   blorp_copy_memory_indirect_shader(&b, indirect_buf_addr, copy_count,
+                                     stride, global_id);
+
+   return b.shader;
+}
+
+static nir_shader *
+blorp_build_copy_mem2img_indirect_shader(struct blorp_batch *batch,
+                                         void *mem_ctx,
+                                         struct blorp_indirect_copy_mem2img_key *key)
+{
+   struct blorp_context *blorp = batch->blorp;
+
+   mesa_shader_stage stage = MESA_SHADER_COMPUTE;
+   const nir_shader_compiler_options *nir_options =
+      blorp->compiler->nir_options(blorp, stage);
+   nir_builder b = nir_builder_init_simple_shader(stage, nir_options,
+                                                  "copy mem2img indirect");
+   ralloc_steal(mem_ctx, b.shader);
+
+   b.shader->info.workgroup_size[0] = 4;
+   b.shader->info.workgroup_size[1] = 8;
+   b.shader->info.workgroup_size[2] = 1;
+
+   struct blorp_indirect_vars v;
+   blorp_indirect_vars_init(&b, &v);
+
+   /* The indirect buffer is an array containing 'copy_count'
+    * VkCopyMemoryToImageIndirectCommandKHR structures, separated by 'stride'
+    * bytes.
+    */
+   nir_def *indirect_buf_addr = nir_load_var(&b, v.indirect_buf_addr);
+   nir_def *stride = nir_load_var(&b, v.stride);
+   nir_def *copy_idx = nir_load_var(&b, v.copy_idx);
+   nir_def *max_layer = nir_load_var(&b, v.max_layer);
+   nir_def *dest_coord_offsets_arr[2] = {
+      nir_load_var(&b, v.x_offset),
+      nir_load_var(&b, v.y_offset),
+   };
+   nir_def *dest_coord_offsets = nir_vec(&b, dest_coord_offsets_arr, 2);
+
+   nir_def *global_id = nir_load_global_invocation_id(&b, 32);
+
+   /* Shader keys (constants). */
+   nir_def *dimensions = nir_imm_int(&b, key->dimensions);
+   nir_def *forced_layer_or_z = nir_imm_int(&b, key->forced_layer_or_z);
+   nir_def *format_Bpb = nir_imm_intN_t(&b, key->format_Bpb, 16);
+   nir_def *format_block_size_arr[3] = {
+      nir_imm_int(&b, key->format_bw),
+      nir_imm_int(&b, key->format_bh),
+      nir_imm_int(&b, key->format_bd),
+   };
+   nir_def *format_block_size = nir_vec(&b, format_block_size_arr, 3);
+
+   /* Constants derived from the shader keys. */
+   nir_def *is_block_compressed =
+      nir_imm_bool(&b, key->format_bw > 1 || key->format_bh > 1 ||
+                       key->format_bd > 1);
+
+   blorp_copy_memory_to_image_indirect_shader(&b, indirect_buf_addr,
+                                              stride,
+                                              copy_idx,
+                                              max_layer,
+                                              dest_coord_offsets,
+                                              global_id,
+                                              dimensions,
+                                              forced_layer_or_z,
+                                              format_Bpb,
+                                              format_block_size,
+                                              is_block_compressed);
+
+   return b.shader;
+}
+
+static bool
+blorp_get_copy_mem_indirect_kernel_cs(struct blorp_batch *batch,
+                                      struct blorp_params *params)
+{
+   struct blorp_context *blorp = batch->blorp;
+   const char *key = "copy_mem_indirect_kernel_cs";
+   uint32_t key_size = strlen(key);
+
+   if (blorp->lookup_shader(batch, key, key_size, &params->cs_prog_kernel,
+                            &params->cs_prog_data))
+      return true;
+
+   void *mem_ctx = ralloc_context(NULL);
+
+   nir_shader *nir =
+      blorp_build_copy_mem_indirect_shader(batch, mem_ctx);
+
+   const struct blorp_program prog =
+      blorp_compile_cs(blorp, mem_ctx, nir, key, key_size);
+
+   bool result = blorp->upload_shader(batch, MESA_SHADER_COMPUTE,
+                                      key, key_size,
+                                      prog.kernel, prog.kernel_size,
+                                      prog.prog_data, prog.prog_data_size,
+                                      &params->cs_prog_kernel,
+                                      &params->cs_prog_data);
+
+   ralloc_free(mem_ctx);
+   return result;
+
+}
+
+static bool
+blorp_get_copy_mem2img_indirect_kernel_cs(struct blorp_batch *batch,
+                                          struct blorp_params *params,
+                                          struct blorp_indirect_copy_mem2img_key *key)
+{
+   struct blorp_context *blorp = batch->blorp;
+
+   if (blorp->lookup_shader(batch, key, sizeof(*key), &params->cs_prog_kernel,
+                            &params->cs_prog_data))
+      return true;
+
+   void *mem_ctx = ralloc_context(NULL);
+
+   nir_shader *nir =
+      blorp_build_copy_mem2img_indirect_shader(batch, mem_ctx, key);
+
+   const struct blorp_program prog =
+      blorp_compile_cs(blorp, mem_ctx, nir, key, sizeof(*key));
+
+   bool result = blorp->upload_shader(batch, MESA_SHADER_COMPUTE,
+                                      key, sizeof(*key),
+                                      prog.kernel, prog.kernel_size,
+                                      prog.prog_data, prog.prog_data_size,
+                                      &params->cs_prog_kernel,
+                                      &params->cs_prog_data);
+
+   ralloc_free(mem_ctx);
+   return result;
+}
+
+void
+blorp_copy_memory_indirect(struct blorp_batch *batch,
+                           uint64_t indirect_buf_addr,
+                           uint32_t copy_count,
+                           uint64_t stride)
+{
+   struct blorp_params params;
+   blorp_params_init(&params);
+
+   params.op = BLORP_OP_COPY_INDIRECT;
+   params.shader_type = BLORP_SHADER_TYPE_COPY_INDIRECT;
+   params.shader_pipeline = BLORP_SHADER_PIPELINE_COMPUTE;
+
+   params.x0 = 0;
+   params.y0 = 0;
+   params.x1 = 1;
+   params.y1 = 1;
+
+   params.wm_inputs.indirect.indirect_buf_addr = indirect_buf_addr;
+   params.wm_inputs.indirect.indirect_buf_stride = stride;
+   params.wm_inputs.indirect.copy_count = copy_count;
+
+   if (!blorp_get_copy_mem_indirect_kernel_cs(batch, &params)) {
+      mesa_loge("failed to get copy_memory_indirect CS kernel");
+      assert(false);
+      return;
+   }
+
+   batch->blorp->exec(batch, &params);
+}
+
+void
+blorp_copy_memory_to_image_indirect(struct blorp_batch *batch,
+                                    const struct blorp_surf *img_blorp_surf,
+                                    uint64_t indirect_buf_addr,
+                                    uint64_t indirect_buf_stride,
+                                    uint32_t copy_idx,
+                                    uint32_t img_mip_level,
+                                    int layer_count,
+                                    int forced_layer_or_z)
+{
+   enum isl_format original_format = img_blorp_surf->surf->format;
+   const struct isl_format_layout *fmtl =
+      isl_format_get_layout(original_format);
+   enum isl_format copy_format = get_format_for_copy(fmtl->bpb);
+   int dimensions = img_blorp_surf->surf->dim + 1;
+
+   struct blorp_indirect_copy_mem2img_key key = {
+      .base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_COPY_INDIRECT),
+      .dimensions = dimensions,
+      .forced_layer_or_z = forced_layer_or_z,
+      .format_Bpb = fmtl->bpb / 8,
+      .format_bw = fmtl->bw,
+      .format_bh = fmtl->bh,
+      .format_bd = fmtl->bd,
+   };
+
+   struct blorp_params params;
+   blorp_params_init(&params);
+
+   params.op = BLORP_OP_COPY_IMAGE_INDIRECT;
+   params.shader_type = BLORP_SHADER_TYPE_COPY_INDIRECT;
+   params.shader_pipeline = BLORP_SHADER_PIPELINE_COMPUTE;
+
+   params.wm_inputs.indirect.indirect_buf_addr = indirect_buf_addr;
+   params.wm_inputs.indirect.indirect_buf_stride = indirect_buf_stride;
+   params.wm_inputs.indirect.copy_idx = copy_idx;
+   params.wm_inputs.indirect.dimensions = dimensions;
+   params.wm_inputs.indirect.max_layer =
+      img_blorp_surf->surf->logical_level0_px.array_len - 1;
+   params.wm_inputs.indirect.forced_layer_or_z = forced_layer_or_z;
+
+   /* params.dst is our image. */
+   blorp_surface_info_init(batch, &params.dst, img_blorp_surf,
+                           img_mip_level,
+                           forced_layer_or_z == -1 ? 0 : forced_layer_or_z,
+                           copy_format,
+                           true /* is_dest */);
+
+   struct isl_extent3d mip_dimensions = {
+      .width = MAX2(params.dst.surf.logical_level0_px.w >> img_mip_level, 1),
+      .height = MAX2(params.dst.surf.logical_level0_px.h >> img_mip_level, 1),
+      .depth = MAX2(params.dst.surf.logical_level0_px.d >> img_mip_level, 1),
+   };
+
+   if (fmtl->bw > 1 || fmtl->bh > 1 || fmtl->bd > 1) {
+      blorp_surf_convert_to_uncompressed(batch->blorp->isl_dev,
+                                         &params.dst, NULL, NULL, NULL, NULL);
+      params.wm_inputs.indirect.x_offset = params.dst.tile_x_sa;
+      params.wm_inputs.indirect.y_offset = params.dst.tile_y_sa;
+
+      mip_dimensions.width = params.dst.surf.logical_level0_px.w;
+      mip_dimensions.height = params.dst.surf.logical_level0_px.h;
+      mip_dimensions.depth = params.dst.surf.logical_level0_px.d;
+   }
+
+   /* These settings control the number of workgroups in the shader, see
+    * blorp_exec_compute(). We don't need to divide by the local sizes here,
+    * this will be done later.
+    */
+   params.x0 = 0;
+   params.y0 = 0;
+   params.x1 = mip_dimensions.width;
+   params.y1 = mip_dimensions.height;
+   if (forced_layer_or_z == -1) {
+      /* We set this here so blorp_indirect_buf2img_get_dispatch_size() can
+       * read it while figuring out how many shader instances we'll need.
+       */
+      params.num_layers = layer_count;
+   } else {
+      params.num_layers = 1;
+   }
+
+   if (!blorp_get_copy_mem2img_indirect_kernel_cs(batch, &params, &key)) {
+      mesa_loge("failed to get copy_memory_to_image_indirect CS kernel");
+      assert(false);
+      return;
+   }
+
+   batch->blorp->exec(batch, &params);
+}

src/intel/blorp/blorp_nir_builder.h

@@ -0,0 +1,109 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "dev/intel_device_info.h"
+
+#include "compiler/nir/nir_builder.h"
+#include "blorp_priv.h"
+
+static inline void
+blorp_nir_init_shader(nir_builder *b,
+                      struct blorp_context *blorp,
+                      void *mem_ctx,
+                      mesa_shader_stage stage,
+                      const char *name)
+{
+   const nir_shader_compiler_options *nir_options =
+      blorp->compiler->nir_options(blorp, stage);
+
+   *b = nir_builder_init_simple_shader(stage, nir_options,
+                                       "%s", name ? name : "");
+   ralloc_steal(mem_ctx, b->shader);
+   if (stage == MESA_SHADER_FRAGMENT)
+      b->shader->info.fs.origin_upper_left = true;
+}
+
+static inline nir_def *
+blorp_nir_txf_ms_mcs(nir_builder *b, nir_def *xy_pos, nir_def *layer,
+                     const struct intel_device_info *devinfo)
+{
+   nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
+   tex->op = nir_texop_txf_ms_mcs_intel;
+   tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
+   tex->dest_type = nir_type_int32;
+
+   nir_def *coord;
+   if (layer) {
+      tex->is_array = true;
+      tex->coord_components = 3;
+      coord = nir_vec3(b, nir_channel(b, xy_pos, 0),
+                          nir_channel(b, xy_pos, 1),
+                          layer);
+   } else {
+      tex->is_array = false;
+      tex->coord_components = 2;
+      coord = nir_trim_vector(b, xy_pos, 2);
+   }
+   tex->src[0] = nir_tex_src_for_ssa(
+      nir_tex_src_coord,
+      devinfo->verx10 >= 125 ? nir_u2u16(b, coord) : coord);
+
+   /* Blorp only has one texture and it's bound at unit 0 */
+   tex->texture_index = 0;
+   tex->sampler_index = 0;
+
+   nir_def_init(&tex->instr, &tex->def, 4, 32);
+   nir_builder_instr_insert(b, &tex->instr);
+
+   return &tex->def;
+}
+
+static inline nir_def *
+blorp_nir_mcs_is_clear_color(nir_builder *b,
+                             nir_def *mcs,
+                             uint32_t samples)
+{
+   switch (samples) {
+   case 2:
+      /* Empirical evidence suggests that the value returned from the
+       * sampler is not always 0x3 for clear color so we need to mask it.
+       */
+      return nir_ieq_imm(b, nir_iand(b, nir_channel(b, mcs, 0),
+                                        nir_imm_int(b, 0x3)),
+                            0x3);
+
+   case 4:
+      return nir_ieq_imm(b, nir_channel(b, mcs, 0), 0xff);
+
+   case 8:
+      return nir_ieq_imm(b, nir_channel(b, mcs, 0), ~0);
+
+   case 16:
+      /* For 16x MSAA, the MCS is actually an ivec2 */
+      return nir_iand(b, nir_ieq_imm(b, nir_channel(b, mcs, 0), ~0),
+                         nir_ieq_imm(b, nir_channel(b, mcs, 1), ~0));
+
+   default:
+      UNREACHABLE("Invalid sample count");
+   }
+}

src/intel/blorp/blorp_priv.h

@@ -0,0 +1,672 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef BLORP_PRIV_H
+#define BLORP_PRIV_H
+
+#include <stdint.h>
+
+#include "common/intel_measure.h"
+#include "compiler/nir/nir.h"
+
+#include "blorp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define BLORP_INLINE_PARAM_THREAD_GROUP_ID_Z_DIMENSION (0)
+
+void blorp_init(struct blorp_context *blorp, void *driver_ctx,
+                struct isl_device *isl_dev, const struct blorp_config *config);
+
+struct blorp_compiler {
+   const struct brw_compiler *brw;
+   const struct elk_compiler *elk;
+
+   const nir_shader_compiler_options *(*nir_options)(struct blorp_context *blorp,
+                                                     mesa_shader_stage stage);
+
+   struct blorp_program (*compile_fs)(struct blorp_context *blorp, void *mem_ctx,
+                                      struct nir_shader *nir,
+                                      bool multisample_fbo,
+                                      bool is_fast_clear,
+                                      bool use_repclear,
+                                      const void *key, uint32_t key_size);
+   struct blorp_program (*compile_vs)(struct blorp_context *blorp, void *mem_ctx,
+                                      struct nir_shader *nir,
+                                      const void *key, uint32_t key_size);
+
+   struct blorp_program (*compile_cs)(struct blorp_context *blorp, void *mem_ctx,
+                                      struct nir_shader *nir,
+                                      const void *key, uint32_t key_size);
+
+   bool (*ensure_sf_program)(struct blorp_batch *batch,
+                             struct blorp_params *params);
+
+   bool (*params_get_layer_offset_vs)(struct blorp_batch *batch,
+                                      struct blorp_params *params);
+};
+
+/**
+ * Binding table indices used by BLORP.
+ */
+enum {
+   BLORP_RENDERBUFFER_BT_INDEX,
+   BLORP_TEXTURE_BT_INDEX,
+   BLORP_TEXBUF_BT_INDEX,
+   BLORP_NUM_BT_ENTRIES
+};
+
+#define BLORP_SAMPLER_INDEX 0
+
+struct blorp_surface_info
+{
+   bool enabled;
+
+   /* Should we unpack the last few rows using a texel buffer? */
+   bool buffer;
+   uint32_t buffer_rows;
+
+   struct isl_surf surf;
+   struct blorp_address addr;
+
+   /* Inferred page boundaries of the surface address */
+   uint64_t page_base, page_limit;
+
+   struct isl_surf aux_surf;
+   struct blorp_address aux_addr;
+   enum isl_aux_usage aux_usage;
+   enum isl_format aux_format;
+
+   union isl_color_value clear_color;
+   struct blorp_address clear_color_addr;
+   bool has_replicated_pixel;
+
+   struct isl_view view;
+
+   /* Z offset into a 3-D texture or slice of a 2-D array texture. */
+   float z_offset;
+
+   uint32_t tile_x_sa, tile_y_sa;
+};
+
+void
+blorp_surface_info_init(struct blorp_batch *batch,
+                        struct blorp_surface_info *info,
+                        const struct blorp_surf *surf,
+                        unsigned int level, float layer,
+                        enum isl_format format, bool is_dest);
+void
+blorp_surf_convert_to_single_slice(const struct isl_device *isl_dev,
+                                   struct blorp_surface_info *info);
+void
+surf_fake_rgb_with_red(const struct isl_device *isl_dev,
+                       struct blorp_surface_info *info);
+void
+blorp_surf_convert_to_uncompressed(const struct isl_device *isl_dev,
+                                   struct blorp_surface_info *info,
+                                   uint32_t *x, uint32_t *y,
+                                   uint32_t *width, uint32_t *height);
+void
+blorp_surf_fake_interleaved_msaa(const struct isl_device *isl_dev,
+                                 struct blorp_surface_info *info);
+void
+blorp_surf_retile_w_to_y(const struct isl_device *isl_dev,
+                         struct blorp_surface_info *info);
+
+
+struct blorp_coord_transform
+{
+   float multiplier;
+   float offset;
+};
+
+/**
+ * Bounding rectangle telling pixel discard which pixels are to be touched.
+ * This is needed in when surfaces are configured as something else what they
+ * really are:
+ *
+ *    - writing W-tiled stencil as Y-tiled
+ *    - writing interleaved multisampled as single sampled.
+ *
+ * See blorp_check_in_bounds().
+ */
+struct blorp_bounds_rect
+{
+   uint32_t x0;
+   uint32_t x1;
+   uint32_t y0;
+   uint32_t y1;
+};
+
+/**
+ * Grid needed for blended and scaled blits of integer formats, see
+ * blorp_nir_manual_blend_bilinear().
+ */
+struct blorp_rect_grid
+{
+   float x1;
+   float y1;
+   float pad[2];
+};
+
+struct blorp_surf_offset {
+   uint32_t x;
+   uint32_t y;
+};
+
+/* Parameters used in blorp_blit.c. */
+struct blorp_wm_inputs_blit
+{
+   struct blorp_bounds_rect bounds_rect;
+   struct blorp_rect_grid rect_grid;
+   struct blorp_coord_transform coord_transform[2];
+
+   struct blorp_surf_offset src_offset;
+   struct blorp_surf_offset dst_offset;
+
+   /* (1/width, 1/height) for the source surface */
+   float src_inv_size[2];
+
+   uint32_t src_buffer_first_row;
+   uint32_t src_buffer_row_pitch;
+
+   /* Minimum layer setting works for all the textures types but texture_3d
+    * for which the setting has no effect. Use the z-coordinate instead.
+    */
+   float src_z;
+};
+
+/* Parameters used in blorp_clear.c. */
+struct blorp_wm_inputs_clear {
+   uint32_t clear_color[4];
+   struct blorp_bounds_rect bounds_rect;
+};
+
+/* Parameters using in blorp_indirect_copy.c */
+struct blorp_wm_inputs_indirect {
+   /* The address of the indirect buffer containing the information about the
+    * indirect copy.
+    */
+   uint64_t indirect_buf_addr;
+
+   /* How far apart the information about each copy is inside the indirect
+    * buffer.
+    */
+   uint64_t indirect_buf_stride;
+
+   /* How many copies we have to do. */
+   uint32_t copy_count;
+
+   /* For memory to image copies, we do a single copy per shader. This
+    * represents the index of the copy to be done.
+    */
+   uint32_t copy_idx;
+
+   /* How many dimensions does our image have? 1, 2 or 3. */
+   uint32_t dimensions;
+
+   /* The maximum array layer of the image. */
+   uint32_t max_layer;
+
+   /* When compressed formats are used, we pretend they are a non-compressed
+    * format, of the same bpb. Since we can't maintain the exact same layout
+    * of mipmap and layer offsets, we're forced to make adjustments to where X
+    * and Y actually start, and are also forced to copy only one layer (or Z
+    * axis position) per shader invocation.
+    */
+   uint32_t x_offset;
+   uint32_t y_offset;
+   int forced_layer_or_z;
+};
+
+struct blorp_wm_inputs
+{
+   union {
+      struct blorp_wm_inputs_blit blit;
+      struct blorp_wm_inputs_clear clear;
+      struct blorp_wm_inputs_indirect indirect;
+   };
+
+   /* Note: Pad out to an integral number of registers when extending, but
+    * make sure subgroup_id is the last 32-bit item.
+    */
+   uint32_t pad[1];
+   uint32_t subgroup_id;
+};
+
+static inline nir_variable *
+blorp_create_nir_input(struct nir_shader *nir,
+                       const char *name,
+                       const struct glsl_type *type,
+                       unsigned int offset)
+{
+   nir_variable *input;
+   if (nir->info.stage == MESA_SHADER_COMPUTE) {
+      input = nir_variable_create(nir, nir_var_uniform, type, name);
+      input->data.driver_location = offset;
+      input->data.location = offset;
+   } else {
+      input = nir_variable_create(nir, nir_var_shader_in, type, name);
+      input->data.location = VARYING_SLOT_VAR0 + offset / (4 * sizeof(float));
+      input->data.location_frac = (offset / sizeof(float)) % 4;
+   }
+   if (nir->info.stage == MESA_SHADER_FRAGMENT)
+      input->data.interpolation = INTERP_MODE_FLAT;
+   return input;
+}
+
+#define BLORP_CREATE_NIR_INPUT(shader, name, type) \
+   blorp_create_nir_input((shader), #name, (type), \
+                          offsetof(struct blorp_wm_inputs, name))
+
+struct blorp_vs_inputs {
+   uint32_t base_layer;
+   uint32_t _instance_id; /* Set in hardware by SGVS */
+   uint32_t pad[2];
+};
+
+enum blorp_shader_type {
+   BLORP_SHADER_TYPE_COPY,
+   BLORP_SHADER_TYPE_BLIT,
+   BLORP_SHADER_TYPE_CLEAR,
+   BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE,
+   BLORP_SHADER_TYPE_LAYER_OFFSET_VS,
+   BLORP_SHADER_TYPE_GFX4_SF,
+   BLORP_SHADER_TYPE_COPY_INDIRECT,
+};
+
+enum blorp_shader_pipeline {
+   BLORP_SHADER_PIPELINE_RENDER,
+   BLORP_SHADER_PIPELINE_COMPUTE,
+};
+
+struct blorp_params
+{
+   enum blorp_op op;
+
+   uint32_t x0;
+   uint32_t y0;
+   uint32_t x1;
+   uint32_t y1;
+   float z;
+
+   struct blorp_surface_info src;
+   struct blorp_surface_info dst;
+   struct blorp_surface_info depth;
+   struct blorp_surface_info stencil;
+
+   uint32_t depth_format;
+   uint8_t stencil_mask;
+   uint8_t stencil_ref;
+
+   bool full_surface_hiz_op;
+   uint8_t color_write_disable;
+   enum isl_aux_op fast_clear_op;
+   enum isl_aux_op hiz_op;
+
+   struct blorp_wm_inputs wm_inputs;
+   struct blorp_vs_inputs vs_inputs;
+
+   unsigned num_samples;
+   unsigned num_draw_buffers;
+   unsigned num_layers;
+   bool dst_clear_color_as_input;
+
+   bool use_pre_baked_binding_table;
+   uint32_t pre_baked_binding_table_offset;
+
+   uint32_t vs_prog_kernel;
+   uint32_t sf_prog_kernel;
+   uint32_t wm_prog_kernel;
+   uint32_t cs_prog_kernel;
+
+   /* These are pointers to struct {brw,elk}_stage_prog_data. */
+   void *vs_prog_data;
+   void *sf_prog_data;
+   void *fs_prog_data;
+   void *cs_prog_data;
+
+   enum blorp_shader_type shader_type;
+   enum blorp_shader_pipeline shader_pipeline;
+};
+
+enum intel_measure_snapshot_type
+blorp_op_to_intel_measure_snapshot(enum blorp_op op);
+
+const char *blorp_op_to_name(enum blorp_op op);
+
+void blorp_params_init(struct blorp_params *params);
+
+struct blorp_base_key
+{
+   char name[8];
+   enum blorp_shader_type shader_type;
+   enum blorp_shader_pipeline shader_pipeline;
+};
+
+#define BLORP_BASE_KEY_INIT(_type)                      \
+   (struct blorp_base_key) {                            \
+      .name = "blorp",                                  \
+      .shader_type = _type,                             \
+      .shader_pipeline = BLORP_SHADER_PIPELINE_RENDER,  \
+   }
+
+struct blorp_blit_prog_key
+{
+   struct blorp_base_key base;
+
+   /* Number of samples per pixel that have been configured in the surface
+    * state for texturing from.
+    */
+   unsigned tex_samples;
+
+   /* MSAA layout that has been configured in the surface state for texturing
+    * from.
+    */
+   enum isl_msaa_layout tex_layout;
+
+   enum isl_aux_usage tex_aux_usage;
+
+   /* Actual number of samples per pixel in the source image. */
+   unsigned src_samples;
+
+   /* Actual MSAA layout used by the source image. */
+   enum isl_msaa_layout src_layout;
+
+   /* The swizzle to apply to the source in the shader */
+   struct isl_swizzle src_swizzle;
+
+   /* The format of the source if format-specific workarounds are needed
+    * and 0 (ISL_FORMAT_R32G32B32A32_FLOAT) if the destination is natively
+    * renderable.
+    */
+   enum isl_format src_format;
+
+   /* True if the source requires normalized coordinates */
+   bool src_coords_normalized;
+
+   /* Number of samples per pixel that have been configured in the render
+    * target.
+    */
+   unsigned rt_samples;
+
+   /* MSAA layout that has been configured in the render target. */
+   enum isl_msaa_layout rt_layout;
+
+   /* Actual number of samples per pixel in the destination image. */
+   unsigned dst_samples;
+
+   /* Actual MSAA layout used by the destination image. */
+   enum isl_msaa_layout dst_layout;
+
+   /* The swizzle to apply to the destination in the shader */
+   struct isl_swizzle dst_swizzle;
+
+   /* The format of the destination if format-specific workarounds are needed
+    * and 0 (ISL_FORMAT_R32G32B32A32_FLOAT) if the destination is natively
+    * renderable.
+    */
+   enum isl_format dst_format;
+
+   /* Whether or not the format workarounds are a bitcast operation */
+   bool format_bit_cast;
+
+   /** True if we need to perform SINT -> UINT clamping. */
+   bool sint32_to_uint;
+
+   /** True if we need to perform UINT -> SINT clamping. */
+   bool uint32_to_sint;
+
+   /* Type of the data to be read from the texture (one of
+    * nir_type_(int|uint|float)).
+    */
+   nir_alu_type texture_data_type;
+
+   /* True if the source image is W tiled.  If true, the surface state for the
+    * source image must be configured as Y tiled, and tex_samples must be 0.
+    */
+   bool src_tiled_w;
+
+   /* True if the destination image is W tiled.  If true, the surface state
+    * for the render target must be configured as Y tiled, and rt_samples must
+    * be 0.
+    */
+   bool dst_tiled_w;
+
+   /* True if the destination is an RGB format.  If true, the surface state
+    * for the render target must be configured as red with three times the
+    * normal width.  We need to do this because you cannot render to
+    * non-power-of-two formats.
+    */
+   bool dst_rgb;
+
+   isl_surf_usage_flags_t dst_usage;
+
+   enum blorp_filter filter;
+
+   /* True if the rectangle being sent through the rendering pipeline might be
+    * larger than the destination rectangle, so the WM program should kill any
+    * pixels that are outside the destination rectangle.
+    */
+   bool use_kill;
+
+   /**
+    * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
+    * than one sample per pixel.
+    */
+   bool persample_msaa_dispatch;
+
+   /* True if this blit operation may involve intratile offsets on the source.
+    * In this case, we need to add the offset before texturing.
+    */
+   bool need_src_offset;
+
+   /* True if this blit operation is unpacking the last few rows of the 2D image
+    * from a 1D buffer. This is part of a workaround for performing buffer-to-image
+    * copies when the source is straddling an extra page due to a misaligned cache.
+    */
+   bool need_src_buffer;
+
+   /* True if this blit operation may involve intratile offsets on the
+    * destination.  In this case, we need to add the offset to gl_FragCoord.
+    */
+   bool need_dst_offset;
+
+   /* Scale factors between the pixel grid and the grid of samples. We're
+    * using grid of samples for bilinear filetring in multisample scaled blits.
+    */
+   float x_scale;
+   float y_scale;
+
+   /* If a compute shader is used, this is the local size y dimension.
+    */
+   uint8_t local_y;
+};
+
+/**
+ * \name BLORP internals
+ * \{
+ *
+ * Used internally by gfx6_blorp_exec() and gfx7_blorp_exec().
+ */
+
+bool blorp_blitter_supports_aux(const struct intel_device_info *devinfo,
+                                enum isl_aux_usage aux_usage);
+
+const char *blorp_shader_type_to_name(enum blorp_shader_type type);
+const char *blorp_shader_pipeline_to_name(enum blorp_shader_pipeline pipe);
+
+struct blorp_program {
+   const void *kernel;
+   uint32_t    kernel_size;
+
+   const void *prog_data;
+   uint32_t    prog_data_size;
+};
+
+static inline struct blorp_program
+blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx,
+                 struct nir_shader *nir,
+                 bool multisample_fbo,
+                 bool is_fast_clear,
+                 bool use_repclear,
+                 const void *key, uint32_t key_size)
+{
+   return blorp->compiler->compile_fs(blorp, mem_ctx, nir, multisample_fbo,
+                                      is_fast_clear, use_repclear,
+                                      key, key_size);
+}
+
+static inline struct blorp_program
+blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
+                 struct nir_shader *nir, const void *key, uint32_t key_size)
+{
+   return blorp->compiler->compile_vs(blorp, mem_ctx, nir, key, key_size);
+}
+
+static inline bool
+blorp_ensure_sf_program(struct blorp_batch *batch,
+                        struct blorp_params *params)
+{
+   struct blorp_compiler *c = batch->blorp->compiler;
+   /* Absence of callback indicates it is not needed.  This is the case for
+    * brw, which is Gfx9+.
+    */
+   return !c->ensure_sf_program || c->ensure_sf_program(batch, params);
+}
+
+static inline uint8_t
+blorp_get_cs_local_y(struct blorp_params *params)
+{
+   uint32_t height = params->y1 - params->y0;
+   uint32_t or_ys = params->y0 | params->y1;
+   if (height > 32 || util_is_aligned(or_ys, 4)) {
+      return 4;
+   } else if (util_is_aligned(or_ys, 2)) {
+      return 2;
+   } else {
+      return 1;
+   }
+}
+
+static inline void
+blorp_set_cs_dims(struct nir_shader *nir, uint8_t local_y)
+{
+   assert(local_y != 0 && (16 % local_y == 0));
+   nir->info.workgroup_size[0] = 16 / local_y;
+   nir->info.workgroup_size[1] = local_y;
+   nir->info.workgroup_size[2] = 1;
+}
+
+static inline struct blorp_program
+blorp_compile_cs(struct blorp_context *blorp, void *mem_ctx,
+                 struct nir_shader *nir, const void *key, uint32_t key_size)
+{
+   return blorp->compiler->compile_cs(blorp, mem_ctx, nir, key, key_size);
+}
+
+static inline bool
+blorp_params_get_layer_offset_vs(struct blorp_batch *batch,
+                                 struct blorp_params *params)
+{
+   return batch->blorp->compiler->params_get_layer_offset_vs(batch, params);
+}
+
+/* This means: blorp_params->wm_inputs.blit should be used. */
+static inline bool
+blorp_op_type_is_blit(enum blorp_op op)
+{
+   switch (op) {
+   case BLORP_OP_BLIT:
+   case BLORP_OP_COPY:
+      return true;
+   default:
+      return false;
+   }
+}
+
+/* This means: blorp_params->wm_inputs.clear should be used. */
+static inline bool
+blorp_op_type_is_clear(enum blorp_op op)
+{
+   switch (op) {
+   case BLORP_OP_CCS_AMBIGUATE:
+   case BLORP_OP_CCS_COLOR_CLEAR:
+   case BLORP_OP_CCS_PARTIAL_RESOLVE:
+   case BLORP_OP_CCS_RESOLVE:
+   case BLORP_OP_FAST_STENCIL_CLEAR:
+   case BLORP_OP_HIZ_AMBIGUATE:
+   case BLORP_OP_HIZ_CLEAR:
+   case BLORP_OP_HIZ_RESOLVE:
+   case BLORP_OP_HIZ_STENCIL_CLEAR:
+   case BLORP_OP_MCS_AMBIGUATE:
+   case BLORP_OP_MCS_COLOR_CLEAR:
+   case BLORP_OP_MCS_PARTIAL_RESOLVE:
+   case BLORP_OP_LINEAR_SURFACE_CLEAR:
+   case BLORP_OP_SLOW_COLOR_CLEAR:
+   case BLORP_OP_SLOW_STENCIL_CLEAR:
+   case BLORP_OP_SLOW_DEPTH_STENCIL_CLEAR:
+   case BLORP_OP_SLOW_DEPTH_CLEAR:
+      return true;
+   default:
+      return false;
+   }
+}
+
+/* This means: blorp->wm_inputs.indirect should be used. */
+static inline bool
+blorp_op_type_is_indirect(enum blorp_op op)
+{
+   switch (op) {
+   case BLORP_OP_COPY_INDIRECT:
+   case BLORP_OP_COPY_IMAGE_INDIRECT:
+      return true;
+   default:
+      return false;
+   }
+}
+
+/* Asserts unless the surface is a buffer to image copy */
+#define blorp_assert_is_buffer(surf, view)                     \
+   do {                                                        \
+      assert((surf).dim == ISL_SURF_DIM_2D);                   \
+      assert((surf).tiling == ISL_TILING_LINEAR);              \
+      assert((surf).logical_level0_px.d == 1);                 \
+      assert((surf).logical_level0_px.array_len == 1);         \
+      assert((surf).samples == 1);                             \
+      assert((surf).levels == 1);                              \
+      UNUSED const struct isl_format_layout *fmtl =            \
+         isl_format_get_layout((view).format);                 \
+      assert((surf).row_pitch_B % (fmtl->bpb / 8) == 0);       \
+   } while (false)
+
+/** \} */
+
+#ifdef __cplusplus
+} /* end extern "C" */
+#endif /* __cplusplus */
+
+#endif /* BLORP_PRIV_H */

src/intel/blorp/blorp_shaders.cl

@@ -0,0 +1,294 @@
+/* Copyright © 2025 Intel Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "compiler/libcl/libcl.h"
+#include "compiler/libcl/libcl_vk.h"
+#include "compiler/nir/nir_defines.h"
+#include "compiler/shader_enums.h"
+
+bool
+blorp_check_in_bounds(uint4 bounds_rect, uint2 pos)
+{
+   uint x0 = bounds_rect[0], x1 = bounds_rect[1];
+   uint y0 = bounds_rect[2], y1 = bounds_rect[3];
+
+   return pos.x >= x0 && pos.x < x1 &&
+          pos.y >= y0 && pos.y < y1;
+}
+
+void nir_image_store(uint handle, int4 coords, uint sample_index,
+                     uint4 colors, uint lod, uint image_dim,
+                     uint image_array, uint format, uint access,
+                     uint range_base, uint src_type);
+
+/* Used by vkCmdCopyMemoryIndirectKHR. */
+void
+blorp_copy_memory_indirect_shader(
+   global uint *indirect_buf,
+   uint copy_count,
+   ulong stride_bytes,
+   uint global_id)
+{
+   for (uint c = 0; c < copy_count; c++) {
+      uint idx = (uint)(c * (stride_bytes / 4));
+
+      /* The spec says the minimum alignment is 4 instead of 8, so we have to
+       * do these tricks.
+       */
+      VkCopyMemoryIndirectCommandKHR cmd =
+         (*(global VkCopyMemoryIndirectCommandKHR*)&indirect_buf[idx]);
+
+      uint copy_size_ints = cmd.size / 4;
+
+      global int *src = (global int*)cmd.srcAddress;
+      global int *dst = (global int*)cmd.dstAddress;
+
+      if (global_id < copy_size_ints)
+         dst[global_id] = src[global_id];
+   }
+}
+
+struct img_copy_params {
+   ulong src_address;
+   uint2 row_size_px;
+   uint base_layer;
+   uint layer_count;
+   uint3 offset;
+   uint3 extent;
+};
+
+void
+read_img_params(
+   global uint *indirect_buf,
+   uint copy_idx,
+   ulong stride_bytes,
+   uint dimensions,
+   uint max_layer,
+   uint3 format_block_size,
+   bool is_block_compressed,
+   struct img_copy_params *p)
+{
+   uint idx = copy_idx * (stride_bytes / 4);
+
+   VkCopyMemoryToImageIndirectCommandKHR cmd =
+         (*(global VkCopyMemoryToImageIndirectCommandKHR*)&indirect_buf[idx]);
+
+   p->src_address = cmd.srcAddress;
+   p->row_size_px = (uint2)(cmd.bufferRowLength, cmd.bufferImageHeight);
+
+   /* We don't use imageSubresource.aspectMask and imageSubresource.mipLevel,
+    * those are dealt with when the application calls
+    * vkCmdCopyMemoryToImageIndirectKHR().
+    */
+
+   p->base_layer = cmd.imageSubresource.baseArrayLayer;
+   p->layer_count = cmd.imageSubresource.layerCount;
+
+   p->offset = (uint3)(cmd.imageOffset.x, cmd.imageOffset.y,
+                       cmd.imageOffset.z);
+   p->extent = (uint3)(cmd.imageExtent.width, cmd.imageExtent.height,
+                       cmd.imageExtent.depth);
+
+   if (p->row_size_px.x == 0)
+      p->row_size_px.x = p->extent.x;
+   if (p->row_size_px.y == 0)
+      p->row_size_px.y = p->extent.y;
+
+   /* Our code deals with blocks, not pixels. */
+   if (is_block_compressed) {
+      p->offset /= format_block_size;
+      p->extent = DIV_ROUND_UP(p->extent, format_block_size);
+   }
+
+   /* Users can pass 3D images with the Z axis as an array layer. */
+   if (dimensions == 3 && (p->base_layer != 0 || p->layer_count != 1)) {
+      p->offset.z = p->base_layer;
+      p->extent.z = p->layer_count;
+      p->base_layer = 0;
+      p->layer_count = 1;
+   }
+
+   /* This handles VK_REMAINING_ARRAY_LAYERS and bugs. */
+   if (p->base_layer + p->layer_count > max_layer + 1)
+      p->layer_count = max_layer - p->base_layer + 1;
+}
+
+uint4
+get_pixel(
+   ulong src_address,
+   uint format_Bpb)
+{
+   switch (format_Bpb) {
+   case 1: {
+      global uchar *src_buf = (global uchar *)src_address;
+      return (uint4)(src_buf[0], 0, 0, 0);
+   }
+   case 2: {
+      global ushort *src_buf = (global ushort *)src_address;
+      return (uint4)(src_buf[0], 0, 0, 0);
+   }
+   case 4: {
+      global uint *src_buf = (global uint *)src_address;
+      return (uint4)(src_buf[0], 0, 0, 0);
+   }
+   case 8: {
+      global uint *src_buf = (global uint *)src_address;
+      return (uint4)(vload2(0, src_buf), 0, 0);
+   }
+   case 16: {
+      global uint *src_buf = (global uint *)src_address;
+      return (uint4)(vload4(0, src_buf));
+   }
+   default:
+      /* TODO: support 3, 6, 12. */
+      return (uint4)(0xFF, 0, 0, 0xFF);
+   }
+}
+
+int4
+get_coords(
+   uint3 pos,
+   uint layer,
+   uint2 dest_coord_offsets,
+   int dimensions,
+   int forced_layer_or_z)
+{
+   int4 ret;
+
+   pos.xy += dest_coord_offsets;
+
+   switch (dimensions) {
+   case 1:
+      ret = (int4)(pos.x, layer, 0, 0);
+      break;
+   case 2:
+      ret = (int4)(pos.x, pos.y, layer, 0);
+      break;
+   case 3:
+   default:
+      ret = (int4)(pos.x, pos.y, pos.z, 0);
+      break;
+   }
+
+   if (forced_layer_or_z != -1) {
+      ret.z = 0;
+      ret.w = 0;
+   }
+
+   return ret;
+}
+
+void
+write_pixel(
+   const int4 coords,
+   const uint4 colors)
+{
+   /* We don't seem to need to set image_array to true if we set sampler_dim
+    * to 3D.
+    * Setting mip_level does not do anything on Intel, we set mip levels
+    * through the bindings.
+    */
+   nir_image_store(0 /* The image handle. */,
+                   coords, /* See get_coords(). */
+                   0, /* Sample index for multi-sampling. */
+                   colors, /* The RGBA pixels, in src_type. */
+                   0 /* mip_level */,
+                   GLSL_SAMPLER_DIM_3D,
+                   false, /* image_array */
+                   0, /* format */
+                   ACCESS_NON_READABLE, /* access */
+                   0, /* range_base */
+                   nir_type_int32 /* src_type */);
+}
+
+/* Used by vkCmdCopyMemoryToImageIndirectKHR. */
+void
+blorp_copy_memory_to_image_indirect_shader(
+   /* Actual parameters. */
+   global uint *indirect_buf,
+   ulong stride_bytes,
+   uint copy_idx,
+   uint max_layer,
+   uint2 dest_coord_offsets,
+   uint3 global_id,
+
+   /* These are shader keys, they are NIR immediates. */
+   uint dimensions,
+   int forced_layer_or_z,
+   ushort format_Bpb,
+   uint3 format_block_size,
+   bool is_block_compressed)
+{
+   /* We have one invocation per texel of a given a mip level.  This means
+    * that for the pixels outside the copy area, we'll hit the 'continue'
+    * below.
+    */
+   uint3 src_pos = global_id;
+   uint layer;
+
+   /* 'forced_layer_or_z' means that whatever slice or layer we're
+    * trying to work with is set as part of our binding (view) as depth
+    * 0 or layer 0, depending on the dimensionality. This can happen
+    * when we're trying to pretend a format is something that it's not
+    * (e.g., we're treating a block compressed 4x4 64bpp format as an
+    * r32g32 format).
+    */
+   if (forced_layer_or_z != -1) {
+      if (dimensions == 3) {
+         src_pos.z = forced_layer_or_z;
+         layer = 0;
+      } else {
+         src_pos.z = 0;
+         layer = forced_layer_or_z;
+      }
+   } else {
+      if (dimensions == 3) {
+         src_pos.z = global_id.z;
+         layer = 0;
+      } else {
+         src_pos.z = 0;
+         layer = global_id.z;
+      }
+   }
+
+   struct img_copy_params p;
+   read_img_params(indirect_buf, copy_idx, stride_bytes, dimensions,
+                   max_layer, format_block_size, is_block_compressed, &p);
+
+   if (any(src_pos >= p.extent))
+      return;
+
+   uint3 dst_pos = src_pos + p.offset;
+   if (forced_layer_or_z == -1 && dimensions != 3)
+      layer = global_id.z + p.base_layer;
+
+   if (layer > p.base_layer + p.layer_count - 1)
+      return;
+
+   uint2 row_size_blocks = p.row_size_px;
+   if (is_block_compressed) {
+      row_size_blocks = DIV_ROUND_UP(row_size_blocks,
+                                     format_block_size.xy);
+   }
+   uint row_length_bytes = row_size_blocks.x * format_Bpb;
+   uint row_height_bytes = row_size_blocks.y * row_length_bytes;
+
+   uint buf_z_offset_bytes = src_pos.z * row_height_bytes;
+   uint buf_y_offset_bytes = src_pos.y * row_length_bytes;
+   uint buf_x_offset_bytes = src_pos.x * format_Bpb;
+
+   uint layer_offset_bytes = (layer - p.base_layer) * row_height_bytes;
+   uint buf_offset_bytes = layer_offset_bytes +
+                           buf_z_offset_bytes +
+                           buf_y_offset_bytes +
+                           buf_x_offset_bytes;
+
+   uint4 colors = get_pixel(p.src_address + buf_offset_bytes,
+                            format_Bpb);
+
+   int4 coords = get_coords(dst_pos, layer, dest_coord_offsets, dimensions,
+                            forced_layer_or_z);
+
+   write_pixel(coords, colors);
+}

src/intel/blorp/meson.build

@@ -0,0 +1,92 @@
+# Copyright © 2017 Intel Corporation
+# SPDX-License-Identifier: MIT
+
+blorp_shader_files = files(
+  'blorp_shaders.cl',
+)
+
+blorp_shaders_spv = custom_target(
+  input : blorp_shader_files,
+  output : 'blorp_shaders.spv',
+  command : [
+    prog_mesa_clc, '-o', '@OUTPUT@', '--depfile', '@DEPFILE@',
+    blorp_shader_files, '--',
+    '-I' + join_paths(meson.project_source_root(), 'include'),
+    '-I' + join_paths(meson.project_source_root(), 'src/compiler/libcl'),
+    '-I' + join_paths(meson.project_source_root(), 'src'),
+    '-I' + join_paths(meson.current_source_dir(), '.'),
+    cl_args,
+    ],
+  depends : [gen_cl_xml_pack],
+  depfile : 'blorp_shaders.h.d',
+)
+
+blorp_shaders = custom_target(
+  input : blorp_shaders_spv,
+  output : ['blorp_shaders.cpp', 'blorp_shaders.h'],
+  command : [prog_vtn_bindgen2, blorp_shaders_spv, '@OUTPUT0@', '@OUTPUT1@'],
+)
+
+idep_blorp_shaders = declare_dependency(
+  sources : [blorp_shaders],
+  include_directories : include_directories('.'),
+)
+
+files_libblorp = files(
+  'blorp.c',
+  'blorp.h',
+  'blorp_blit.c',
+  'blorp_clear.c',
+  'blorp_indirect_copy.c',
+  'blorp_nir_builder.h',
+  'blorp_priv.h',
+)
+
+files_blorp_brw = files(
+  'blorp_genX_exec_brw.h',
+  'blorp_brw.c',
+)
+
+files_blorp_elk = files(
+  'blorp_genX_exec_elk.h',
+  'blorp_elk.c',
+)
+
+libblorp = static_library(
+  'blorp',
+  [files_libblorp, files_blorp_brw],
+  include_directories : [inc_include, inc_src, inc_intel, inc_intel_compiler],
+  c_args : [no_override_init_args, soong_compat_c_args],
+  gnu_symbol_visibility : 'hidden',
+  dependencies : [
+    idep_nir_headers, idep_genxml, idep_mesautil, idep_intel_dev,
+    idep_blorp_shaders
+  ],
+  build_by_default: false,
+)
+
+idep_intel_blorp = declare_dependency(
+  link_with: libblorp,
+)
+
+if with_intel_elk
+  libblorp_elk = static_library(
+    'blorp_elk',
+    [files_libblorp, files_blorp_elk],
+    include_directories : [inc_include, inc_src, inc_intel],
+    c_args : [no_override_init_args, soong_compat_c_args],
+    gnu_symbol_visibility : 'hidden',
+    dependencies : [
+      idep_nir_headers, idep_genxml, idep_mesautil, idep_intel_dev,
+      idep_blorp_shaders
+    ],
+    build_by_default: false,
+  )
+
+  idep_intel_blorp_elk = declare_dependency(
+    dependencies: [idep_intel_dev],
+    link_with: libblorp_elk,
+  )
+else
+  idep_intel_blorp_elk = null_dep
+endif

src/intel/ci/angle-anv-adl-slow-skips.txt

@@ -0,0 +1,2 @@
+# Slow test that may hit 60s timeout pre-merge, but passes otherwise
+KHR-GLES31.core.tessellation_shader.vertex.vertex_ordering

src/intel/ci/angle-anv-jsl-fails.txt

@@ -0,0 +1,15 @@
+# https://gitlab.freedesktop.org/mesa/mesa/-/issues/9795
+dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_xyz,Fail
+dEQP-GLES3.functional.shaders.builtin_variable.fragcoord_xyz,Fail
+multisample-dEQP-GLES3.functional.shaders.builtin_variable.fragcoord_xyz,Fail
+
+# ANGLE marks non-shadow linear-filtered textures incomplete (see GLES 3.2 spec
+# 8.17 Texture Completeness), so you get a fallback texture sample, while Mesa
+# incorrectly marks it complete.  The CTS incorrectly expects texture
+# completeness.
+# https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/4292
+# https://bugs.chromium.org/p/angleproject/issues/detail?id=7877
+KHR-GLES31.core.texture_border_clamp.Texture2DDC16Linear,Fail
+
+# new with ANGLE 2024-10-17
+KHR-GLES31.core.blend_equation_advanced.test_coherency.multiplySequence,Fail

src/intel/ci/angle-anv-jsl-flakes.txt

@@ -0,0 +1,24 @@
+# non-gpu-hang, frequent flakes that can happen deep in a series of copy_image tests.
+# multiple fails per caselist, with those fails separated by passes!
+dEQP-GLES31.functional.copy_image.mixed.viewclass_.*_mixed.*
+dEQP-GLES31.functional.copy_image.*viewclass_.*
+
+# https://gitlab.freedesktop.org/mesa/mesa/-/issues/9794
+.*dEQP-GLES31.functional.draw_indirect.compute_interop.large.*
+
+# 2024-05-15, after the
+# https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19414/
+dEQP-GLES3.functional.multisample.fbo_8_samples.constancy_both
+dEQP-GLES3.functional.multisample.fbo_max_samples.constancy_both_inverted
+dEQP-GLES3.functional.multisample.fbo_max_samples.constancy_both
+
+KHR-GLES31.core.tessellation_shader.vertex.vertex_ordering
+KHR-GLES31.core.tessellation_shader.vertex.vertex_spacing
+
+# Seen in https://gitlab.freedesktop.org/mesa/mesa/-/pipelines/1364513
+dEQP-GLES3.functional.multisample.fbo_8_samples.constancy_both
+
+# uprev ANGLE in Mesa
+KHR-GLES31.core.blend_equation_advanced.test_coherency.multiplySequence
+
+dEQP-GLES3.functional.multisample.fbo_max_samples.constancy_alpha_to_coverage

src/intel/ci/angle-anv-tgl-flakes.txt

@@ -0,0 +1,19 @@
+# May be bogus, happened around a bunch of interpolate_at_sample hangs
+dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.interpolation.lines_wide
+
+# The last quad that was supposed to be overwritten by red has a green triangle showing.
+dEQP-GLES3.functional.multisample.fbo_8_samples.constancy_alpha_to_coverage
+dEQP-GLES3.functional.multisample.fbo_max_samples.constancy_alpha_to_coverage
+
+dEQP-GLES3.functional.multisample.fbo_8_samples.constancy_both_inverted
+dEQP-GLES3.functional.multisample.fbo_max_samples.constancy_both
+
+# "Failure: Non-zero green color component detected - should have been completely overwritten by red quad"
+# the "rendered image" looks suspiciously black, though, which is the clear color?
+dEQP-GLES3.functional.multisample.fbo_max_samples.constancy_sample_coverage
+dEQP-GLES3.functional.multisample.fbo_max_samples.constancy_sample_coverage_inverted
+
+# non-gpu-hang, frequent flakes that can happen deep in a series of copy_image tests.
+# multiple fails per caselist, with those fails separated by passes!
+dEQP-GLES31.functional.copy_image.mixed.viewclass_.*_mixed.*
+dEQP-GLES31.functional.copy_image.*viewclass_.*

src/intel/ci/anv-adl-fails.txt

@@ -0,0 +1,494 @@
+# Tiny mismatch in the bottom right of the image.
+# Fails on ADL and TGL but passes on RPL
+dEQP-VK.drm_format_modifiers.export_import.b10g11r11_ufloat_pack32,Fail
+
+# New crash with Xe KMD
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.buffer_size_2_24,Crash
+
+# New failures with VKCTS 1.4.4.0
+dEQP-VK.sparse_resources.buffer.ssbo.read_write.sparse_residency_non_resident_strict,Fail
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.non_resident_buffer_copy_src_alloc_none_16777216,Crash
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.non_resident_buffer_copy_src_alloc_partial_16777216,Crash
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.non_resident_buffer_strict_copy_src_alloc_none_16777216,Crash
+
+dEQP-VK.video.capabilities.av1_decode_dpb_video_format_support_query,Fail
+dEQP-VK.video.capabilities.av1_decode_dst_video_format_support_query,Fail
+dEQP-VK.video.decode.vp9.basic_10_not_matching_order_layered_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.basic_10_not_matching_order_separated_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.inter_intra_only_layered_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.inter_intra_only_separated_dpb_video_layout,Fail
+
+# fluster
+GStreamer-H.264-Vulkan-Gst1.0@CVFC1_Sony_C,Fail
+GStreamer-H.264-Vulkan-Gst1.0@FM1_BT_B,Fail
+GStreamer-H.264-Vulkan-Gst1.0@FM1_FT_E,Fail
+GStreamer-H.264-Vulkan-Gst1.0@FM2_SVA_C,Crash
+GStreamer-H.264-Vulkan-Gst1.0@FREH10-1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@FREH10-2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@FREXT1_TANDBERG_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@FREXT2_TANDBERG_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@FREXT3_TANDBERG_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@FRExt1_Panasonic_D,Fail
+GStreamer-H.264-Vulkan-Gst1.0@FRExt2_Panasonic_C,Fail
+GStreamer-H.264-Vulkan-Gst1.0@FRExt3_Panasonic_E,Fail
+GStreamer-H.264-Vulkan-Gst1.0@FRExt4_Panasonic_B,Fail
+GStreamer-H.264-Vulkan-Gst1.0@FRExt_MMCO4_Sony_B,Fail
+GStreamer-H.264-Vulkan-Gst1.0@HPCAMOLQ_BRCM_B,Crash
+GStreamer-H.264-Vulkan-Gst1.0@HPCAQ2LQ_BRCM_B,Fail
+GStreamer-H.264-Vulkan-Gst1.0@HPCVMOLQ_BRCM_B,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR10_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR11_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR12_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR13_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR14_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR15_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR1_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR2_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR3_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR4_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR6_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR7_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR8_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FR9_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FREXT16_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FREXT17_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FREXT18_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@Hi422FREXT19_SONY_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MR6_BT_B,Fail
+GStreamer-H.264-Vulkan-Gst1.0@MR8_BT_B,Fail
+GStreamer-H.264-Vulkan-Gst1.0@MVCDS-4,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCDS-5,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCDS-6,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCDS1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCDS2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCDS3,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCICT-1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCICT-2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCNV-2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCNV-3,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCNV1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCNV4,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCRP_1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCRP_2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCRP_3,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCRP_4,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCRP_5,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCRP_6,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCSPS-1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@MVCSPS-2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPCV444I1_2008,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPCV444I2_2008,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPCV444I3_2008,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPCV444I4_Mitsubishi_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPCV444I5_Mitsubishi_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPCV444I6_Mitsubishi_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPCV444I7_SejongUniv_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH10I1_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH10I2_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH10I3_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH10I4_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH10I5_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH10I6_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH10I7_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH422I1_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH422I2_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH422I3_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH422I4_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH422I5_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH422I6_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH422I7_Panasonic_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444I1_2008,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444I2_2008,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444I3_2008,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444I4_Mitsubishi_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444I5_Mitsubishi_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444I6_Mitsubishi_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444I7_SejongUniv_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444P10_SejongUniv_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444P1_2008,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444P2_2008,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444P3_2008,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444P4_2008,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444P5_2008,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444P6_Mitsubishi_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444P7_Mitsubishi_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444P8_Mitsubishi_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@PPH444P9_Mitsubishi_A,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SP1_BT_A,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBC-1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBCT-1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-1-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-1-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-2-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-2-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-3-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBCTS-3-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-2-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-2-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-3-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-3-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-4-r1-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-4-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-4-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-5-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-5-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-5-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBM-5-L3,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-2-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-2-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-2-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-3-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-3-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMST-3-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-10-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-10-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-11-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-11-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-12-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-12-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-13-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-13-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-13-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-2-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-3-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-3-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-4-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-4-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-5-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-5-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-6-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-6-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-7-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-7-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-8-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-8-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-9-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBMT-9-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBS-1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBS-2-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBS-2-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBS-3-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBS-4-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBS-5-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBS-6-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBS-6-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBS-7-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBS-8-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-10-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-10-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-11-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-11-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-12-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-12-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-13-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-13-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-14-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-14-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-14-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-15-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-15-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-15-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-16-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-16-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-16-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-17-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-17-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-17-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-18-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-18-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-18-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-19-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-2-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-2-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-20-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-3-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-3-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-4-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-4-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-5-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-5-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-6-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-6-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-7-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-7-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-8-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-8-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-9-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCBST-9-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBSTC-1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCBSTC-1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L3,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L4,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L5,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L6,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHCTS-1-r1-L7,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHICS-1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHICS-1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHICS-1-L3,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-2-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-2-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-3-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHIS-3-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHM-1-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHM-1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHM-1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHM-1-L3,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHM-2-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHM-2-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHM-3-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHM-3-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHM-4-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHM-4-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHM-4-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L3,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L4,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-1-r1-L5,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-2-r1-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-2-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHMTS-2-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHS-1-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHS-2-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHST-1-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCHST-1-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHST-1-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHST-2-r1-L0,Fail
+GStreamer-H.264-Vulkan-Gst1.0@SVCHST-2-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHST-2-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHST-3-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHST-4-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHSTC-1-r1-L0,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHSTC-1-r1-L1,Crash
+GStreamer-H.264-Vulkan-Gst1.0@SVCHSTC-1-r1-L2,Crash
+GStreamer-H.264-Vulkan-Gst1.0@brcm_freh6,Fail
+GStreamer-H.264-Vulkan-Gst1.0@freh1_b,Fail
+GStreamer-H.264-Vulkan-Gst1.0@freh2_b,Fail
+GStreamer-H.264-Vulkan-Gst1.0@freh7_b,Fail
+GStreamer-H.264-Vulkan-Gst1.0@sp2_bt_b,Fail
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_C_A_HHI_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_C_B_HHI_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_C_C_Sharp_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_A_HHI_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_B_HHI_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_C_RWTH_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_D_RWTH_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_E_MediaTek_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_F_MediaTek_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_G_Hisilicon_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_D1_H_Hisilicon_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_D2_A_Samsung_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_D2_B_LGE_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_DT_A_MediaTek_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_DT_B_NTT_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_DT_C_Hisilicon_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_DT_D_NTT_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_TD_A_Qualcomm_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_TD_B_MediaTek_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_TD_C_MediaTek_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_TD_D_HHI_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_TD_E_HHI_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_T_A_Qualcomm_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_T_B_MediaTek_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_T_C_Sharp_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_T_D_Sharp_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@3DHC_T_E_HHI_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@ADAPTRES_A_ERICSSON_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@ADJUST_IPRED_ANGLE_A_RExt_Mitsubishi_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@ALPHA_A_BBC_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@Bipred_8by8_A_Qualcomm_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@Bitdepth_A_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@Bitdepth_B_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CAINIT_G_SHARP_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CAINIT_H_SHARP_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CCP_10bit_RExt_QCOM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CCP_12bit_RExt_QCOM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CCP_8bit_RExt_QCOM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CGS_A_TECHNICOLOR_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CGS_B_TECHNICOLOR_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CGS_C_TECHNICOLOR_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CGS_D_TECHNICOLOR_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CGS_E_TECHNICOLOR_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CGS_F_TECHNICOLOR_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CGS_G_TECHNICOLOR_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CGS_H_TECHNICOLOR_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CGS_I_TECHNICOLOR_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CONFCROP_A_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CONFCROP_B_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CONFCROP_C_VIDYO_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@CONFWIN_A_Sony_1,Fail
+GStreamer-H.265-Vulkan-Gst1.0@DBLK_A_MAIN10_VIXS_4,Crash
+GStreamer-H.265-Vulkan-Gst1.0@DBLK_C_SONY_3,Fail
+GStreamer-H.265-Vulkan-Gst1.0@DBLK_D_VIXS_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@DEPTH_A_NOKIA_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@DISFLAG_A_QUALCOMM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@DPB_A_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@DPB_B_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@DPB_Loop_Filters_A_MediaTek_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@DSLICE_A_HHI_5,Crash
+GStreamer-H.265-Vulkan-Gst1.0@DSLICE_B_HHI_5,Crash
+GStreamer-H.265-Vulkan-Gst1.0@DSLICE_C_HHI_5,Crash
+GStreamer-H.265-Vulkan-Gst1.0@Delta_QP_Chroma_QP_Offsets_A_Qualcomm_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_10BIT_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_12BIT_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_16BIT_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_HIGHTHROUGHPUT_444_16_INTRA_8BIT_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_MAIN_444_16_INTRA_10BIT_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_MAIN_444_16_INTRA_12BIT_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_MAIN_444_16_INTRA_16BIT_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@EXTPREC_MAIN_444_16_INTRA_8BIT_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@EXT_A_ericsson_4,Crash
+GStreamer-H.265-Vulkan-Gst1.0@ExplicitRdpcm_A_BBC_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@ExplicitRdpcm_B_BBC_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_10b_420_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_10b_422_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_10b_444_RExt_Sony_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_12b_400_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_12b_420_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_12b_422_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_12b_444_RExt_Sony_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_16b_400_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_16b_444_RExt_Sony_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_16b_444_highThroughput_RExt_Sony_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_8b_400_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_8b_420_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@GENERAL_8b_444_RExt_Sony_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@HT_A_SCC_Apple_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@HT_B_SCC_Apple_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@HT_C_SCC_Apple_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@HYBRID_A_QUALCOMM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@IBF_Disabled_A_MediaTek_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@IBF_Disabled_B_MediaTek_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@INACTIVE_A_QCOM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@INBLD_A_NOKIA_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@INITQP_B_Main10_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@IPCM_A_RExt_NEC_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@IPCM_B_RExt_NEC,Crash
+GStreamer-H.265-Vulkan-Gst1.0@IPRED_B_Nokia_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@LAYERID63_A_HHI_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@LAYERID_A_NOKIA_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@LTRPSPS_A_Qualcomm_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MAXTID_A_ETRI_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MAXTID_B_ETRI_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MAXTID_C_ETRI_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVD_A_IDCC_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVD_A_NOKIA_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_A_Qualcomm_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_B_Sharp_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_C_Sony_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_D_NTT_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_E_Qualcomm_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_F_Qualcomm_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_G_NTT_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_H_LGE_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVHEVCS_I_Nokia_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVRESIDC_A_MS_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVRESIDC_B_MS_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@MVRESIDC_C_MS_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@Main_422_10_A_RExt_Sony_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@Main_422_10_B_RExt_Sony_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@NONVUI_A_QUALCOMM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@NONVUI_B_QUALCOMM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@NONVUI_C_QUALCOMM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@OLS_A_NOKIA_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@OLS_B_NOKIA_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@OLS_C_NOKIA_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@PERSIST_RPARAM_A_RExt_Sony_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@PICSIZE_A_Bossen_1,Fail
+GStreamer-H.265-Vulkan-Gst1.0@POC_A_Ericsson_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@POC_B_Ericsson_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@PPI_A_InterDigital_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@PPI_B_InterDigital_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@PPSSLIST_A_Sony_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@PSEXT_A_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@QMATRIX_A_RExt_Sony_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@RAP_B_Bossen_2,Fail
+GStreamer-H.265-Vulkan-Gst1.0@REFLAYER_A_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@REFLAYER_B_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@REFLAYER_C_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@REFLAYER_D_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@REFREGOFF_A_SHARP_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@REPFMT_A_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@REPFMT_B_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@REPFMT_C_VIDYO_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@RESCHANGE_A_VIDYO_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@RESPHASE_A_SAMSUNG_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@RPLM_A_qualcomm_4,Crash
+GStreamer-H.265-Vulkan-Gst1.0@RPLM_B_qualcomm_4,Crash
+GStreamer-H.265-Vulkan-Gst1.0@RPS_B_qualcomm_5,Crash
+GStreamer-H.265-Vulkan-Gst1.0@RPS_C_ericsson_5,Crash
+GStreamer-H.265-Vulkan-Gst1.0@RPS_E_qualcomm_5,Crash
+GStreamer-H.265-Vulkan-Gst1.0@RPS_F_docomo_2,Fail
+GStreamer-H.265-Vulkan-Gst1.0@SAO_A_RExt_MediaTek_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SCREFOFF_A_QCOM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SIM_A_IDCC_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SIM_B_IDCC_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SLIST_A_Sony_5,Fail
+GStreamer-H.265-Vulkan-Gst1.0@SLIST_B_Sony_9,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SLIST_C_Sony_4,Fail
+GStreamer-H.265-Vulkan-Gst1.0@SLIST_D_Sony_9,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SLLEV_A_VIDYO_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SNR_A_IDCC_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SNR_B_IDCC_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SNR_C_IDCC_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SPLITFLAG_A_HHI_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SPSREPFMT_A_Sony_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SPSSLIST_A_Sony_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SRATIOS_A_SAMSUNG_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SRATIOS_B_SAMSUNG_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SREXT_A_FUJITSU_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SREXT_B_FUJITSU_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SREXT_C_FUJITSU_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SREXT_D_FUJITSU_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SREXT_E_FUJITSU_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@SREXT_F_FUJITSU_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@Slice_ACT_QP_Offsets_A_Qualcomm_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@TSCTX_10bit_I_RExt_SHARP_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@TSCTX_10bit_RExt_SHARP_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@TSCTX_12bit_I_RExt_SHARP_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@TSCTX_12bit_RExt_SHARP_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@TSCTX_8bit_I_RExt_SHARP_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@TSCTX_8bit_RExt_SHARP_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@TSUNEQBD_A_MAIN10_Technicolor_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@VPSSPSPPS_A_MainConcept_1,Fail
+GStreamer-H.265-Vulkan-Gst1.0@VUI_A_QUALCOMM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@VUI_B_QUALCOMM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@VUI_C_QUALCOMM_1,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WAVETILES_RExt_Sony_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_AND_TILE_10Bit422Test_HIGH_TP_444_10BIT_RExt_Apple_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_AND_TILE_AND_CABAC_BYPASS_ALIGN_0_HIGH_TP_444_14BIT_RExt_Apple_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_AND_TILE_AND_CABAC_BYPASS_ALIGN_1_HIGH_TP_444_14BIT_RExt_Apple_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_AND_TILE_AND_CABAC_EXT_PREC_1_HIGH_TP_444_14BIT_RExt_Apple_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_AND_TILE_HIGH_TP_444_8BIT_RExt_Apple_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_A_ericsson_MAIN10_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_A_ericsson_MAIN_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_B_ericsson_MAIN10_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_B_ericsson_MAIN_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_C_ericsson_MAIN10_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_C_ericsson_MAIN_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_D_ericsson_MAIN10_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_D_ericsson_MAIN_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_E_ericsson_MAIN10_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_E_ericsson_MAIN_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_F_ericsson_MAIN10_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_F_ericsson_MAIN_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WPP_HIGH_TP_444_8BIT_RExt_Apple_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WP_A_MAIN10_Toshiba_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@WP_MAIN10_B_Toshiba_3,Crash
+GStreamer-H.265-Vulkan-Gst1.0@Zero_and_One_Palette_Size_A_Canon_2,Crash
+GStreamer-H.265-Vulkan-Gst1.0@cip_B_NEC_3,Fail
+GStreamer-H.265-Vulkan-Gst1.0@ipcm_A_NEC_3,Fail
+GStreamer-H.265-Vulkan-Gst1.0@ipcm_B_NEC_3,Fail
+GStreamer-H.265-Vulkan-Gst1.0@ipcm_E_NEC_2,Fail

src/intel/ci/anv-adl-flakes.txt

@@ -0,0 +1,25 @@
+# initial flakes
+dEQP-VK.wsi.direct_drm.maintenance1.present_fence.fifo.ordering
+shaderquery-dEQP-VK.query_pool.performance_query.query_compute
+
+# Seen in https://gitlab.freedesktop.org/mesa/mesa/-/pipelines/1364513
+dEQP-VK.pipeline.monolithic.creation_cache_control.compute_pipelines.single_pipeline_no_compile
+
+dEQP-VK.synchronization2.signal_order.shared_binary_semaphore.write_copy_image_read_image_tess_eval.image_64x64x8_r32_sfloat_opaque_fd
+
+# various valgrind errors, driver is mapping buffer at command buffer
+# building time, this is out of spec
+dEQP-VK.video.encode.h265.i_p
+dEQP-VK.video.encode.h265.resolution_change_dpb
+
+# Flakes seen in the nightly https://gitlab.freedesktop.org/mesa/mesa/-/jobs/71664021
+dEQP-VK.video.encode.h264.rc_disable
+dEQP-VK.video.encode.h264.resolution_change_dpb
+dEQP-VK.video.encode.h265.query_with_status
+dEQP-VK.video.encode.h265.rc_disable
+dEQP-VK.video.encode.h265.resources_without_profiles
+
+# New flakes with VKCTS 1.4.4.0
+dEQP-VK.sparse_resources.buffer.ssbo.sparse_residency.non_resident_buffer_strict_copy_src_alloc_partial_16777216
+
+dEQP-VK.wsi.display.create_display_mode

src/intel/ci/anv-adl-skips.txt

@@ -0,0 +1,11 @@
+# initial skips
+dEQP-VK.reconvergence.subgroup_uniform_control_flow_ballot.compute.nesting4.0.40
+dEQP-VK.reconvergence.subgroup_uniform_control_flow_ballot.compute.nesting4.7.10
+dEQP-VK.reconvergence.subgroup_uniform_control_flow_elect.compute.nesting4.0.40
+dEQP-VK.reconvergence.subgroup_uniform_control_flow_elect.compute.nesting4.7.10
+dEQP-VK.reconvergence.workgroup_uniform_control_flow_ballot.compute.nesting4.7.10
+dEQP-VK.reconvergence.workgroup_uniform_control_flow_elect.compute.nesting4.7.10
+
+# Not supported on ADL
+dEQP-VK.binding_model.descriptor_buffer.sparse_binding_buffer.*
+dEQP-VK.binding_model.descriptor_buffer.sparse_residency_buffer.*

src/intel/ci/anv-adl-vkd3d-fails.txt

@@ -0,0 +1,12 @@
+# Undefined behavior not supported unless EXT_descriptor_buffer is
+# used or running on Gfx12.5+ where we don't do descriptor indirection
+# (prior generations have a descriptor heap too small 64MB)
+test_undefined_read_typed_buffer_as_untyped_simple_dxbc,Fail
+test_undefined_read_typed_buffer_as_untyped_simple_dxil,Fail
+test_undefined_structured_raw_read_typed_dxbc,Fail
+test_undefined_structured_raw_read_typed_dxil,Fail
+test_undefined_typed_read_structured_raw_dxbc,Fail
+test_undefined_typed_read_structured_raw_dxil,Fail
+
+# xe 0000:00:02.0: [drm] GT0: Timedout job: seqno=4294967172, lrc_seqno=4294967172, guc_id=2, flags=0x0 in d3d12 [871]
+test_fence_pending_signal_cpu_rewind_plain,Crash

src/intel/ci/anv-jsl-fails.txt

@@ -0,0 +1,6 @@
+# New failures with VK CTS 1.4.4.0
+dEQP-VK.video.decode.h264.i_p_b_13_separated_dpb_video_layout,Crash
+dEQP-VK.video.decode.vp9.basic_10_not_matching_order_layered_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.basic_10_not_matching_order_separated_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.inter_intra_only_layered_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.inter_intra_only_separated_dpb_video_layout,Fail

src/intel/ci/anv-jsl-flakes.txt

@@ -0,0 +1,3 @@
+# Appeared after decreasing the fraction
+dEQP-VK.synchronization.timeline_semaphore.one_to_n.write_image_compute_indirect_read_image_fragment.image_128_r32_uint
+dEQP-VK.synchronization.timeline_semaphore.one_to_n.write_copy_buffer_to_image_read_copy_image_to_buffer.image_128x128_d16_unorm

src/intel/ci/anv-jsl-slow-skips.txt

@@ -0,0 +1,4 @@
+# These are pretty slow, so just run the 2d cases in non-"full" jobs.
+dEQP-VK.*robustness.*.no_fmt_qual.*samples_1.*_array.frag
+dEQP-VK.*robustness.*.no_fmt_qual.*samples_1.3d.frag
+dEQP-VK.*robustness.*.no_fmt_qual.*samples_1.cube.frag

src/intel/ci/anv-rpl-fails.txt

@@ -0,0 +1,11 @@
+dEQP-VK.video.capabilities.av1_decode_dpb_video_format_support_query,Fail
+dEQP-VK.video.capabilities.av1_decode_dst_video_format_support_query,Fail
+dEQP-VK.video.decode.vp9.basic_10_not_matching_order_layered_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.basic_10_not_matching_order_separated_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.inter_intra_only_layered_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.inter_intra_only_separated_dpb_video_layout,Fail
+
+# VKCTS 1.4.4.2 -> 1.4.5.3 uprev
+dEQP-VK.sparse_resources.buffer.ssbo.read_write.sparse_residency_non_resident_strict,Fail
+dEQP-VK.wsi.display_control.swapchain_counter,Crash
+dEQP-VK.wsi.display.create_display_mode,Fail

src/intel/ci/anv-rpl-flakes.txt

@@ -0,0 +1,3 @@
+
+# Maybe flaky as of CTS 1.4.4.2 -> 1.4.5.3 uprev
+dEQP-VK.video.encode.h265.resolution_change_dpb_separated_src_video_layout

src/intel/ci/anv-skips.txt

@@ -0,0 +1,6 @@
+# Timeouts
+dEQP-VK.api.external.semaphore.sync_fd.export_multiple_times_temporary
+dEQP-VK.api.external.fence.sync_fd.export_multiple_times_temporary
+
+# Can occasionally time out as of VKCTS 1.4.1.1
+dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.basic

src/intel/ci/anv-tgl-fails.txt

@@ -0,0 +1,14 @@
+# Tiny mismatch in the bottom right of the image.
+# Fails on ADL and TGL but passes on RPL
+dEQP-VK.drm_format_modifiers.export_import.b10g11r11_ufloat_pack32,Fail
+
+# This is a bug of CTS: https://gitlab.khronos.org/Tracker/vk-gl-cts/issues/6033
+dEQP-VK.video.capabilities.av1_decode_dst_video_format_support_query,Fail
+dEQP-VK.video.capabilities.av1_decode_dpb_video_format_support_query,Fail
+
+# New failures with VKCTS 1.4.4.0
+dEQP-VK.sparse_resources.buffer.ssbo.read_write.sparse_residency_non_resident_strict,Fail
+dEQP-VK.video.decode.vp9.basic_10_not_matching_order_layered_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.basic_10_not_matching_order_separated_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.inter_intra_only_layered_dpb_video_layout,Fail
+dEQP-VK.video.decode.vp9.inter_intra_only_separated_dpb_video_layout,Fail

src/intel/ci/anv-tgl-flakes.txt

@@ -0,0 +1,2 @@
+dEQP-VK.subgroups.clustered.compute.subgroupclusteredmul_u64vec4_requiredsubgroupsize
+dEQP-VK.video.encode.h265.usage_layered_src_video_layout

src/intel/ci/anv-tgl-skips.txt

@@ -0,0 +1,6 @@
+# times out since 1.3.9.0 uprev
+dEQP-VK.reconvergence.subgroup_uniform_control_flow_elect.compute.nesting4.7.10
+
+# Not supported on TGL
+dEQP-VK.binding_model.descriptor_buffer.sparse_binding_buffer.*
+dEQP-VK.binding_model.descriptor_buffer.sparse_residency_buffer.*

src/intel/ci/deqp-anv-adl-angle.toml

@@ -0,0 +1,66 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2"
+renderer_check = "ANGLE.*ADL"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# 565-no-depth-no-stencil: Not supported with angle on X11?
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+

src/intel/ci/deqp-anv-adl-full.toml

@@ -0,0 +1,6 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "ADL"
+tests_per_group = 5000

src/intel/ci/deqp-anv-adl.toml

@@ -0,0 +1,56 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+fraction = 6
+renderer_check = "ADL"
+tests_per_group = 5000
+
+# Rerun query tests with shader query optimizations (14443 tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "ADL"
+include = ["dEQP-VK.query_pool.*"]
+prefix = "shaderquery-"
+tests_per_group = 5000
+[deqp.env]
+  query_clear_with_blorp_threshold = "0"
+  query_copy_with_shader_threshold = "0"
+
+# Rerun indirect tests with in-place generation shader optimizations
+# (3814 tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "ADL"
+include = ["dEQP-VK.draw.*indirect*"]
+prefix = "indirectgen-inplace-"
+tests_per_group = 5000
+[deqp.env]
+  generated_indirect_threshold = "0"
+
+# Rerun indirect tests with ring-buffer generation shader optimizations
+# (3814 tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "ADL GT2"
+include = ["dEQP-VK.draw.*indirect*"]
+prefix = "indirectgen-inring-"
+tests_per_group = 5000
+[deqp.env]
+  generated_indirect_threshold = "0"
+  generated_indirect_ring_threshold = "0"
+
+# Rerun load/store without format tests with emulation support (2352
+# tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "ADL GT2"
+include = ["dEQP-VK.image.load_store.without_format*"]
+prefix = "without-format-emulation-"
+tests_per_group = 5000
+[deqp.env]
+  anv_emulate_read_without_format = "true"

src/intel/ci/deqp-anv-fluster.toml

@@ -0,0 +1,8 @@
+[[fluster]]
+bin = "/fluster/fluster.py"
+decoders = [
+  # "GStreamer-AV1-Vulkan-Gst1.0", # uncomment when updating to gstreamer >= 1.28
+  # "GStreamer-VP9-Vulkan-Gst1.0", # uncomment when updating to gstreamer >= 1.28
+  "GStreamer-H.264-Vulkan-Gst1.0",
+  "GStreamer-H.265-Vulkan-Gst1.0",
+]

src/intel/ci/deqp-anv-jsl-angle-full.toml

@@ -0,0 +1,65 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2"
+renderer_check = "ANGLE.*JSL"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# 565-no-depth-no-stencil: Not supported with angle on X11?
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"

src/intel/ci/deqp-anv-jsl-angle.toml

@@ -0,0 +1,69 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2"
+renderer_check = "ANGLE.*JSL"
+fraction = 15
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 15
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 15
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 15
+
+# 565-no-depth-no-stencil: Not supported with angle on X11?
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"

src/intel/ci/deqp-anv-jsl-full.toml

@@ -0,0 +1,6 @@
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "JSL"
+timeout = 180
+tests_per_group = 5000

src/intel/ci/deqp-anv-jsl.toml

@@ -0,0 +1,6 @@
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+fraction = 15
+renderer_check = "JSL"
+tests_per_group = 5000

src/intel/ci/deqp-anv-rpl.toml

@@ -0,0 +1,55 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "RPL-U"
+tests_per_group = 5000
+
+# Rerun query tests with shader query optimizations (14443 tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "RPL-U"
+include = ["dEQP-VK.query_pool.*"]
+prefix = "shaderquery-"
+tests_per_group = 5000
+[deqp.env]
+  query_clear_with_blorp_threshold = "0"
+  query_copy_with_shader_threshold = "0"
+
+# Rerun indirect tests with in-place generation shader optimizations
+# (3814 tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "RPL-U"
+include = ["dEQP-VK.draw.*indirect*"]
+prefix = "indirectgen-inplace-"
+tests_per_group = 5000
+[deqp.env]
+  generated_indirect_threshold = "0"
+
+# Rerun indirect tests with ring-buffer generation shader optimizations
+# (3814 tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "RPL-U"
+include = ["dEQP-VK.draw.*indirect*"]
+prefix = "indirectgen-inring-"
+tests_per_group = 5000
+[deqp.env]
+  generated_indirect_threshold = "0"
+  generated_indirect_ring_threshold = "0"
+
+# Rerun load/store without format tests with emulation support (2352
+# tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "RPL-U"
+include = ["dEQP-VK.image.load_store.without_format*"]
+prefix = "without-format-emulation-"
+tests_per_group = 5000
+[deqp.env]
+  anv_emulate_read_without_format = "true"

src/intel/ci/deqp-anv-tgl-angle-full.toml

@@ -0,0 +1,65 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2"
+renderer_check = "ANGLE.*TGL"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# 565-no-depth-no-stencil: Not supported with angle on X11?
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"

src/intel/ci/deqp-anv-tgl-angle.toml

@@ -0,0 +1,67 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2"
+renderer_check = "ANGLE.*TGL"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 3
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 3
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# 565-no-depth-no-stencil: Not supported with angle on X11?
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"

src/intel/ci/deqp-anv-tgl-full.toml

@@ -0,0 +1,6 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "TGL GT2"
+tests_per_group = 5000

src/intel/ci/deqp-anv-tgl.toml

@@ -0,0 +1,56 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+fraction = 10
+renderer_check = "TGL GT2"
+tests_per_group = 5000
+
+# Rerun query tests with shader query optimizations (14443 tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "TGL GT2"
+include = ["dEQP-VK.query_pool.*"]
+prefix = "shaderquery-"
+tests_per_group = 5000
+[deqp.env]
+  query_clear_with_blorp_threshold = "0"
+  query_copy_with_shader_threshold = "0"
+
+# Rerun indirect tests with in-place generation shader optimizations
+# (3814 tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "TGL GT2"
+include = ["dEQP-VK.draw.*indirect*"]
+prefix = "indirectgen-inplace-"
+tests_per_group = 5000
+[deqp.env]
+  generated_indirect_threshold = "0"
+
+# Rerun indirect tests with ring-buffer generation shader optimizations
+# (3814 tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "TGL GT2"
+include = ["dEQP-VK.draw.*indirect*"]
+prefix = "indirectgen-inring-"
+tests_per_group = 5000
+[deqp.env]
+  generated_indirect_threshold = "0"
+  generated_indirect_ring_threshold = "0"
+
+# Rerun load/store without format tests with emulation support (2352
+# tests)
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "TGL GT2"
+include = ["dEQP-VK.image.load_store.without_format*"]
+prefix = "without-format-emulation-"
+tests_per_group = 5000
+[deqp.env]
+  anv_emulate_read_without_format = "true"

src/intel/ci/deqp-hasvk-hsw.toml

@@ -0,0 +1,5 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-vk/external/vulkancts/modules/vulkan/deqp-vk"
+caselists = ["/deqp-vk/mustpass/vk-main.txt"]
+renderer_check = "HSW"

src/intel/ci/deqp-intel-adl-cl.toml

@@ -0,0 +1,10 @@
+[[piglit]]
+piglit_folder = "/piglit"
+profile = "cl"
+process_isolation = true
+timeout = 180
+  [piglit.env]
+  PIGLIT_PLATFORM = "mixed_glx_egl"
+  RUSTICL_ENABLE = "iris"
+  RUSTICL_FEATURES = "fp64"
+  INTEL_DEBUG = "cl-quiet"

src/intel/ci/deqp-intel-adl-skqp.toml

@@ -0,0 +1,4 @@
+[[skqp]]
+skqp = "/skqp/skqp"
+skqp_assets = "/skqp/assets"
+

src/intel/ci/deqp-intel-tgl-skqp.toml

@@ -0,0 +1,3 @@
+[[skqp]]
+skqp = "/skqp/skqp"
+skqp_assets = "/skqp/assets"

src/intel/ci/deqp-intel-whl-skqp.toml

@@ -0,0 +1,3 @@
+[[skqp]]
+skqp = "/skqp/skqp"
+skqp_assets = "/skqp/assets"

src/intel/ci/deqp-iris-adl.toml

@@ -0,0 +1,99 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2.*git"
+renderer_check = "ADL"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gl/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gl/mustpass/gl46-main.txt",
+    "/deqp-gl/mustpass/gl46-khr-single.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# 565-nozs
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"

src/intel/ci/deqp-iris-amly-egl.toml

@@ -0,0 +1,20 @@
+# x11
+[[deqp]]
+deqp = "/deqp-gles/modules/egl/deqp-egl-x11"
+caselists = ["/deqp-gles/mustpass/egl-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "x11-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/egl/deqp-egl-wayland"
+caselists = ["/deqp-gles/mustpass/egl-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "wayland-"

src/intel/ci/deqp-iris-amly.toml

@@ -0,0 +1,99 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2.*git"
+renderer_check = "AML"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gl/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gl/mustpass/gl46-main.txt",
+    "/deqp-gl/mustpass/gl46-khr-single.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# 565-nozs
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"

src/intel/ci/deqp-iris-apl-egl.toml

@@ -0,0 +1,20 @@
+# x11
+[[deqp]]
+deqp = "/deqp-gles/modules/egl/deqp-egl-x11"
+caselists = ["/deqp-gles/mustpass/egl-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "x11-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/egl/deqp-egl-wayland"
+caselists = ["/deqp-gles/mustpass/egl-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "wayland-"

src/intel/ci/deqp-iris-apl-glk.toml

@@ -0,0 +1,20 @@
+# x11
+[[deqp]]
+deqp = "/deqp-gles/modules/egl/deqp-egl-x11"
+caselists = ["/deqp-gles/mustpass/egl-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "x11-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/egl/deqp-egl-wayland"
+caselists = ["/deqp-gles/mustpass/egl-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "wayland-"

src/intel/ci/deqp-iris-apl.toml

@@ -0,0 +1,101 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2.*git"
+renderer_check = "APL"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 3
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 3
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gl/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gl/mustpass/gl46-main.txt",
+    "/deqp-gl/mustpass/gl46-khr-single.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# 565-nozs
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"

src/intel/ci/deqp-iris-cml.toml

@@ -0,0 +1,99 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2.*git"
+renderer_check = "CML"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gl/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gl/mustpass/gl46-main.txt",
+    "/deqp-gl/mustpass/gl46-khr-single.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# 565-nozs
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"

src/intel/ci/deqp-iris-glk-egl.toml

@@ -0,0 +1,20 @@
+# x11
+[[deqp]]
+deqp = "/deqp-gles/modules/egl/deqp-egl-x11"
+caselists = ["/deqp-gles/mustpass/egl-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "x11-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/egl/deqp-egl-wayland"
+caselists = ["/deqp-gles/mustpass/egl-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+prefix = "wayland-"

src/intel/ci/deqp-iris-glk.toml

@@ -0,0 +1,108 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 20
+version_check = "GL ES 3.2.*git"
+renderer_check = "GLK"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 20
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 20
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 5
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gl/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gl/mustpass/gl46-main.txt",
+    "/deqp-gl/mustpass/gl46-khr-single.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+fraction = 5
+
+# 565-nozs
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+fraction = 5
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+fraction = 5
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+fraction = 5
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+fraction = 5

src/intel/ci/deqp-iris-jsl.toml

@@ -0,0 +1,101 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2.*git"
+renderer_check = "JSL"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+timeout = 90.0  # Some tests take a bit over 60 seconds
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gl/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gl/mustpass/gl46-main.txt",
+    "/deqp-gl/mustpass/gl46-khr-single.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+timeout = 90.0  # Some tests take a bit over 60 seconds
+
+# 565-nozs
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"

src/intel/ci/deqp-iris-kbl-piglit.toml

@@ -0,0 +1,6 @@
+[[piglit]]
+piglit_folder = "/piglit"
+profile = "gpu"
+process_isolation = true
+  [piglit.env]
+  PIGLIT_PLATFORM = "mixed_glx_egl"

src/intel/ci/deqp-iris-kbl.toml

@@ -0,0 +1,99 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2.*git"
+renderer_check = "KBL"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gl/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gl/mustpass/gl46-main.txt",
+    "/deqp-gl/mustpass/gl46-khr-single.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# 565-nozs
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"

src/intel/ci/deqp-iris-whl.toml

@@ -0,0 +1,99 @@
+# Basic test set
+[[deqp]]
+deqp = "/deqp-gles/modules/gles2/deqp-gles2"
+caselists = ["/deqp-gles/mustpass/gles2-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+version_check = "GL ES 3.2.*git"
+renderer_check = "WHL"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-main.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+[[deqp]]
+deqp = "/deqp-gles/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gles/mustpass/gles2-khr-main.txt",
+    "/deqp-gles/mustpass/gles3-khr-main.txt",
+    "/deqp-gles/mustpass/gles31-khr-main.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# Note that KHR-GL3* test sets include all tests from the previous
+# version, so we only need to run one test list (unlike dEQP-GLES,
+# where the test sets are separate).
+[[deqp]]
+deqp = "/deqp-gl/external/openglcts/modules/glcts"
+caselists = [
+    "/deqp-gl/mustpass/gl46-main.txt",
+    "/deqp-gl/mustpass/gl46-khr-single.txt",
+]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms0",
+]
+
+# 565-nozs
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-565-no-depth-no-stencil.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgb565d0s0ms0",
+]
+prefix = "565-nozs-"
+
+# multisample
+[[deqp]]
+deqp = "/deqp-gles/modules/gles3/deqp-gles3"
+caselists = ["/deqp-gles/mustpass/gles3-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"
+
+[[deqp]]
+deqp = "/deqp-gles/modules/gles31/deqp-gles31"
+caselists = ["/deqp-gles/mustpass/gles31-multisample.txt"]
+deqp_args = [
+    "--deqp-surface-width=256", "--deqp-surface-height=256",
+    "--deqp-surface-type=pbuffer", "--deqp-visibility=hidden",
+    "--deqp-gl-config-name=rgba8888d24s8ms4",
+]
+prefix = "multisample-"

src/intel/ci/gitlab-ci-inc.yml

@@ -0,0 +1,511 @@
+.intel-common-rules:
+  stage: intel
+  rules:
+    - changes: &intel_common_file_list
+        - src/intel/*
+        - src/intel/blorp/**/*
+        - src/intel/common/**/*
+        - src/intel/compiler/**/*
+        - src/intel/dev/**/*
+        - src/intel/ds/**/*
+        - src/intel/genxml/**/*
+        - src/intel/isl/**/*
+        - src/intel/nullhw-layer/**/*
+        - src/intel/perf/**/*
+        - src/intel/tools/**/*
+        - src/intel/ci/gitlab-ci.yml
+        - src/intel/ci/gitlab-ci-inc.yml
+        - src/intel/ci/deqp-$DEQP_SUITE.toml
+        - src/intel/ci/$GPU_VERSION-fails.txt
+        - src/intel/ci/$GPU_VERSION-flakes.txt
+        - src/intel/ci/$GPU_VERSION-skips.txt
+        - src/intel/ci/$GPU_VERSION-slow-skips.txt
+        - src/intel/ci/$VK_DRIVER-skips.txt
+        - src/intel/ci/$GALLIUM_DRIVER-skips.txt
+        - src/intel/ci/$DRIVER_NAME-skips.txt
+        - src/intel/ci/$PIGLIT_TRACES_FILE
+        - src/intel/ci/$REPLAY_CONFIG
+      when: on_success
+
+.intel-common-manual-rules:
+  stage: intel-nightly
+  rules:
+    - changes:
+        *intel_common_file_list
+      when: manual
+
+.i915g-rules:
+  stage: intel
+  rules:
+    - !reference [.test, rules]
+    - !reference [.ondracka-farm-rules, rules]
+    - !reference [.gl-rules, rules]
+    - !reference [.intel-common-rules, rules]
+    - changes: &i915g_file_list
+        - src/gallium/drivers/i915/*
+        - src/gallium/winsys/i915/**/*
+        - src/gallium/drivers/i915/ci/$GPU_VERSION-fails.txt
+        - src/gallium/drivers/i915/ci/$GPU_VERSION-flakes.txt
+        - src/gallium/drivers/i915/ci/$GPU_VERSION-skips.txt
+        - src/gallium/drivers/i915/ci/deqp-$DEQP_SUITE.toml
+        - src/gallium/drivers/i915/ci/gitlab-ci.yml
+      when: on_success
+
+.i915g-manual-rules:
+  stage: intel-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.ondracka-farm-manual-rules, rules]
+    - !reference [.gl-manual-rules, rules]
+    - !reference [.intel-common-manual-rules, rules]
+    - changes:
+        *i915g_file_list
+      when: manual
+
+.crocus-rules:
+  stage: intel
+  rules:
+    - !reference [.test, rules]
+    - !reference [.anholt-farm-rules, rules]
+    - !reference [.gl-rules, rules]
+    - !reference [.intel-common-rules, rules]
+    - changes: &crocus_file_list
+        - src/gallium/drivers/crocus/**/*
+        - src/gallium/winsys/crocus/**/*
+      when: on_success
+
+.crocus-manual-rules:
+  stage: intel-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.anholt-farm-manual-rules, rules]
+    - !reference [.gl-manual-rules, rules]
+    - !reference [.intel-common-manual-rules, rules]
+    - changes:
+        *crocus_file_list
+      when: manual
+
+.iris-rules:
+  stage: intel
+  rules:
+    - !reference [.test, rules]
+    - !reference [.no_scheduled_pipelines-rules, rules]
+    - !reference [.collabora-farm-rules, rules]
+    - !reference [.gl-rules, rules]
+    - !reference [.intel-common-rules, rules]
+    - changes: &iris_file_list
+        - src/gallium/drivers/iris/**/*
+        - src/gallium/winsys/iris/**/*
+      when: on_success
+
+.iris-manual-rules:
+  stage: intel-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.collabora-farm-manual-rules, rules]
+    - !reference [.gl-manual-rules, rules]
+    - !reference [.intel-common-manual-rules, rules]
+    - changes:
+        *iris_file_list
+      when: manual
+
+# Unfortunately we can't sed the on_success from another rules set, so we have
+# to do duplicate the files lists to set the job to manual (see
+# .performance-rules)
+.iris-rules-performance:
+  stage: performance
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.collabora-farm-manual-rules, rules]
+    - !reference [.performance-rules, rules]
+    - !reference [.gl-manual-rules, rules]
+    - changes:
+        *iris_file_list
+      when: manual
+  needs:
+    - job: debian/x86_64_test-gl
+      optional: true
+    - job: debian-release
+
+.anv-rules:
+  stage: intel
+  rules:
+    - !reference [.test, rules]
+    - !reference [.no_scheduled_pipelines-rules, rules]
+    - !reference [.collabora-farm-rules, rules]
+    - !reference [.vulkan-rules, rules]
+    - !reference [.intel-common-rules, rules]
+    - changes: &anv_file_list
+        - src/intel/vulkan/**/*
+      when: on_success
+
+.anv-restricted-rules:
+  stage: intel
+  rules:
+    - !reference [.test, rules]
+    - !reference [.restricted-rules, rules]
+    - !reference [.anv-rules, rules]
+
+.anv-manual-rules:
+  stage: intel-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.collabora-farm-manual-rules, rules]
+    - !reference [.vulkan-manual-rules, rules]
+    - !reference [.intel-common-manual-rules, rules]
+    - changes:
+        *anv_file_list
+      when: manual
+
+.hasvk-rules:
+  stage: intel
+  rules:
+    - !reference [.test, rules]
+    - !reference [.anholt-farm-rules, rules]
+    - !reference [.vulkan-rules, rules]
+    - !reference [.intel-common-rules, rules]
+    - changes: &hasvk_file_list
+        - src/intel/vulkan_hasvk/**/*
+      when: on_success
+
+.hasvk-manual-rules:
+  stage: intel-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.anholt-farm-manual-rules, rules]
+    - !reference [.vulkan-manual-rules, rules]
+    - !reference [.intel-common-manual-rules, rules]
+    - changes:
+        *hasvk_file_list
+      when: manual
+
+# ruleset to trigger on changes affecting either anv or iris, for jobs using both (piglit, skqp)
+.intel-rules:
+  stage: intel
+  rules:
+    - !reference [.test, rules]
+    - !reference [.iris-rules, rules]
+    - !reference [.anv-rules, rules]
+
+.intel-manual-rules:
+  stage: intel-nightly
+  extends: .no-auto-retry
+  rules:
+    - !reference [.test, rules]
+    - !reference [.iris-manual-rules, rules]
+    - !reference [.anv-manual-rules, rules]
+
+
+# Status: https://lava.collabora.dev/scheduler/device_type/acer-cb317-1h-c3z6-dedede
+.lava-acer-cb317-1h-c3z6-dedede:x86_64:
+  variables:
+    DEVICE_TYPE: acer-cb317-1h-c3z6-dedede
+    FARM: collabora
+    FDO_CI_CONCURRENT: 3
+    GPU_VERSION: anv-jsl
+    HWCI_KERNEL_MODULES: i915
+    RUNNER_TAG: mesa-ci-x86-64-lava-acer-cb317-1h-c3z6-dedede
+
+# Status: https://lava.collabora.dev/scheduler/device_type/acer-cbv514-1h-34uz-brya
+.lava-acer-cbv514-1h-34uz-brya:x86_64:
+  variables:
+    DEVICE_TYPE: acer-cbv514-1h-34uz-brya
+    FARM: collabora
+    FDO_CI_CONCURRENT: 9
+    GPU_VERSION: anv-adl
+    HWCI_KERNEL_MODULES: xe
+    RUNNER_TAG: mesa-ci-x86-64-lava-acer-cbv514-1h-34uz-brya
+    LAVA_CMDLINE: "i915.force_probe=!46b3 xe.force_probe=46b3"
+    INTEL_XE_IGNORE_EXPERIMENTAL_WARNING: 1
+
+# Status: https://lava.collabora.dev/scheduler/device_type/asus-CX3402CVA-brya
+.lava-asus-CX3402CVA-brya:x86_64:
+  variables:
+    DEVICE_TYPE: asus-CX3402CVA-brya
+    FARM: collabora
+    FDO_CI_CONCURRENT: 13
+    GPU_VERSION: anv-rpl
+    HWCI_KERNEL_MODULES: xe
+    RUNNER_TAG: mesa-ci-x86-64-lava-asus-CX3402CVA-brya
+    LAVA_CMDLINE: "i915.force_probe=!a7a1 xe.force_probe=a7a1"
+    INTEL_XE_IGNORE_EXPERIMENTAL_WARNING: 1
+
+# Status: https://lava.collabora.dev/scheduler/device_type/acer-chromebox-cxi5-brask
+.lava-acer-chromebox-cxi5-brask:x86_64:
+  variables:
+    DEVICE_TYPE: acer-chromebox-cxi5-brask
+    FARM: collabora
+    FDO_CI_CONCURRENT: 6
+    GPU_VERSION: anv-adl
+    HWCI_KERNEL_MODULES: xe
+    RUNNER_TAG: mesa-ci-x86-64-lava-acer-chromebox-cxi5-brask
+    LAVA_CMDLINE: "i915.force_probe=!46b3 xe.force_probe=46b3"
+    INTEL_XE_IGNORE_EXPERIMENTAL_WARNING: 1
+
+# Status: https://lava.collabora.dev/scheduler/device_type/acer-n20q11-r856ltn-p1s2-nissa
+.lava-acer-n20q11-r856ltn-p1s2-nissa:x86_64:
+  variables:
+    DEVICE_TYPE: acer-n20q11-r856ltn-p1s2-nissa
+    FARM: collabora
+    FDO_CI_CONCURRENT: 5
+    GPU_VERSION: anv-adl
+    HWCI_KERNEL_MODULES: xe
+    RUNNER_TAG: mesa-ci-x86-64-lava-acer-n20q11-r856ltn-p1s2-nissa
+    LAVA_CMDLINE: "i915.force_probe=!46d0 xe.force_probe=46d0"
+    INTEL_XE_IGNORE_EXPERIMENTAL_WARNING: 1
+
+# Status: https://lava.collabora.dev/scheduler/device_type/asus-C523NA-A20057-coral
+.lava-asus-C523NA-A20057-coral:x86_64:
+  variables:
+    DEVICE_TYPE: asus-C523NA-A20057-coral
+    FARM: collabora
+    FDO_CI_CONCURRENT: 5
+    GPU_VERSION: iris-apl
+    HWCI_KERNEL_MODULES: i915
+    RUNNER_TAG: mesa-ci-x86-64-lava-asus-C523NA-A20057-coral
+
+# Status: https://lava.collabora.dev/scheduler/device_type/hp-x360-12b-ca0010nr-n4020-octopus
+.lava-hp-x360-12b-ca0010nr-n4020-octopus:x86_64:
+  variables:
+    DEVICE_TYPE: hp-x360-12b-ca0010nr-n4020-octopus
+    FARM: collabora
+    FDO_CI_CONCURRENT: 3
+    GPU_VERSION: iris-glk
+    HWCI_KERNEL_MODULES: i915
+    RUNNER_TAG: mesa-ci-x86-64-lava-hp-x360-12b-ca0010nr-n4020-octopus
+
+# Status: https://lava.collabora.dev/scheduler/device_type/acer-cp514-2h-1130g7-volteer
+.lava-acer-cp514-2h-1130g7-volteer:x86_64:
+  variables:
+    DEVICE_TYPE: acer-cp514-2h-1130g7-volteer
+    FARM: collabora
+    FDO_CI_CONCURRENT: 9
+    GPU_VERSION: anv-tgl
+    HWCI_KERNEL_MODULES: i915
+    RUNNER_TAG: mesa-ci-x86-64-lava-acer-cp514-2h-1130g7-volteer
+
+# Status: https://lava.collabora.dev/scheduler/device_type/acer-cp514-2h-1160g7-volteer
+.lava-acer-cp514-2h-1160g7-volteer:x86_64:
+  variables:
+    DEVICE_TYPE: acer-cp514-2h-1160g7-volteer
+    FARM: collabora
+    FDO_CI_CONCURRENT: 9
+    GPU_VERSION: anv-tgl
+    HWCI_KERNEL_MODULES: i915
+    RUNNER_TAG: mesa-ci-x86-64-lava-acer-cp514-2h-1160g7-volteer
+
+# Status: https://lava.collabora.dev/scheduler/device_type/asus-C433TA-AJ0005-rammus
+.lava-asus-C433TA-AJ0005-rammus:x86_64:
+  variables:
+    DEVICE_TYPE: asus-C433TA-AJ0005-rammus
+    FARM: collabora
+    FDO_CI_CONCURRENT: 5
+    GPU_VERSION: iris-amly
+    HWCI_KERNEL_MODULES: i915
+    RUNNER_TAG: mesa-ci-x86-64-lava-asus-C433TA-AJ0005-rammus
+
+# Status: https://lava.collabora.dev/scheduler/device_type/hp-x360-14-G1-sona
+.lava-hp-x360-14-G1-sona:x86_64:
+  variables:
+    DEVICE_TYPE: hp-x360-14-G1-sona
+    FARM: collabora
+    FDO_CI_CONCURRENT: 9
+    GPU_VERSION: iris-kbl
+    HWCI_KERNEL_MODULES: i915
+    RUNNER_TAG: mesa-ci-x86-64-lava-hp-x360-14-G1-sona
+
+# Status: https://lava.collabora.dev/scheduler/device_type/dell-latitude-5400-8665U-sarien
+.lava-dell-latitude-5400-8665U-sarien:x86_64:
+  variables:
+    DEVICE_TYPE: dell-latitude-5400-8665U-sarien
+    FARM: collabora
+    FDO_CI_CONCURRENT: 9
+    GPU_VERSION: iris-whl
+    HWCI_KERNEL_MODULES: i915
+    RUNNER_TAG: mesa-ci-x86-64-lava-dell-latitude-5400-8665U-sarien
+
+# Status: https://lava.collabora.dev/scheduler/device_type/asus-C436FA-Flip-hatch
+.lava-asus-C436FA-Flip-hatch:x86_64:
+  variables:
+    DEVICE_TYPE: asus-C436FA-Flip-hatch
+    FARM: collabora
+    FDO_CI_CONCURRENT: 9
+    GPU_VERSION: iris-cml
+    HWCI_KERNEL_MODULES: i915
+    RUNNER_TAG: mesa-ci-x86-64-lava-asus-C436FA-Flip-hatch
+
+# Status: https://lava.collabora.dev/scheduler/device_type/acer-chromebox-cxi4-puff
+.lava-acer-chromebox-cxi4-puff:x86_64:
+  variables:
+    DEVICE_TYPE: acer-chromebox-cxi4-puff
+    FARM: collabora
+    FDO_CI_CONCURRENT: 3
+    GPU_VERSION: iris-cml
+    HWCI_KERNEL_MODULES: i915
+    RUNNER_TAG: mesa-ci-x86-64-lava-acer-chromebox-cxi4-puff
+
+
+.intel-common-test:
+  variables:
+    DTB: ""
+    BOOT_METHOD: depthcharge
+    KERNEL_IMAGE_TYPE: ""
+    FLAKES_CHANNEL: "#intel-ci"
+    HWCI_FREQ_MAX: "true"
+    LAVA_FIRMWARE: i915
+
+.anv-test:
+  extends:
+    - .intel-common-test
+    - .anv-rules
+  variables:
+    DRIVER_NAME: anv
+    VK_DRIVER: intel
+    ANV_DEBUG: "video-decode,video-encode"
+
+.iris-test:
+  extends:
+    - .lava-x86_64-test-gl
+    - .intel-common-test
+    - .iris-rules
+  variables:
+    DRIVER_NAME: iris
+
+.intel-test:
+  extends:
+    - .intel-common-test
+    - .intel-rules
+
+## ANV only
+.anv-angle-test:
+  extends:
+    - .lava-x86_64-test-gl
+    - .intel-common-test
+    - .anv-rules
+    - .test-angle
+  variables:
+    VK_DRIVER: intel
+
+## Iris only
+.iris-apl-test:
+  extends:
+    - .iris-test
+    - .lava-asus-C523NA-A20057-coral:x86_64
+
+.iris-glk-test:
+  extends:
+    - .iris-test
+    - .lava-hp-x360-12b-ca0010nr-n4020-octopus:x86_64
+
+.iris-amly-test:
+  extends:
+    - .iris-test
+    - .iris-manual-rules  # GPU being occasionally stuck
+    - .lava-asus-C433TA-AJ0005-rammus:x86_64
+
+.iris-kbl-test:
+  extends:
+    - .iris-test
+    - .lava-hp-x360-14-G1-sona:x86_64
+
+.iris-whl-test:
+  extends:
+    - .iris-test
+    - .lava-dell-latitude-5400-8665U-sarien:x86_64
+
+.iris-cml-test:
+  extends:
+    - .iris-test
+    - .lava-acer-chromebox-cxi4-puff:x86_64
+  variables:
+    LAVA_FORCE_UART: 1
+
+.iris-adl-test:
+  extends:
+    - .iris-test
+    - .lava-acer-n20q11-r856ltn-p1s2-nissa:x86_64
+  variables:
+    DEQP_SUITE: iris-adl
+
+.iris-whl-deqp:
+  extends:
+    - .iris-whl-test
+  variables:
+    DEQP_SUITE: iris-whl
+  parallel: 4
+
+.iris-traces:
+  extends:
+    - .lava-piglit-traces
+  variables:
+    EGL_PLATFORM: surfaceless
+    PIGLIT_TRACES_FILE: traces-iris.yml
+
+.iris-whl-traces:
+  variables:
+    GPU_VERSION: intel-whl
+  extends:
+    - .iris-whl-test
+    - .iris-traces
+
+.profile-traces:
+  extends:
+    - .iris-traces
+    - .iris-rules-performance
+    - .piglit-performance-base
+  rules:
+    - !reference [.piglit-performance-base, rules]
+    - !reference [.iris-rules-performance, rules]
+
+.iris-whl-traces-performance:
+  extends:
+    - .iris-whl-test
+    - .profile-traces
+  variables:
+    GPU_VERSION: intel-whl
+
+.iris-cml-traces-performance:
+  extends:
+    - .iris-cml-test
+    - .profile-traces
+  variables:
+    GPU_VERSION: intel-cml
+
+## Intel (anv + iris)
+.intel-adl-test:
+  extends:
+    - .lava-x86_64-test-gl
+    - .anv-test
+    - .intel-test
+  variables:
+    GPU_VERSION: intel-adl
+
+.intel-tgl-test:
+  extends:
+    - .lava-x86_64-test-gl
+    - .anv-test
+    - .intel-test
+  variables:
+    GPU_VERSION: intel-tgl
+
+.intel-whl-test:
+  extends:
+    - .lava-x86_64-test-gl
+    - .iris-whl-test
+    - .intel-test
+  variables:
+    GPU_VERSION: intel-whl
+
+.intel-whl-skqp:
+  extends:
+    - .intel-whl-test
+  variables:
+    DEQP_SUITE: intel-whl-skqp
+    VK_DRIVER: intel
+    HWCI_START_XORG: 1

src/intel/ci/gitlab-ci.yml

@@ -0,0 +1,364 @@
+include:
+  - local: 'src/intel/ci/gitlab-ci-inc.yml'
+
+anv-jsl-vk:
+  extends:
+    - .lava-x86_64-test-vk
+    - .anv-test
+    - .lava-acer-cb317-1h-c3z6-dedede:x86_64
+  variables:
+    DEQP_SUITE: anv-jsl
+  parallel: 5
+
+anv-jsl-vk-full:
+  extends:
+    - anv-jsl-vk
+    - .anv-manual-rules
+  variables:
+    DEQP_SUITE: anv-jsl-full
+    FDO_CI_CONCURRENT: 2
+  parallel: 4
+  timeout: 2h 30m
+
+anv-adl-vk:
+  extends:
+    - .lava-x86_64-test-vk
+    - .anv-test
+    - .lava-acer-cbv514-1h-34uz-brya:x86_64
+  variables:
+    DEQP_SUITE: anv-adl
+    # Xe regression in 6.19
+    # https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/7584
+    KERNEL_TAG: "v6.17-mesa-ddf6"
+  parallel: 4
+
+anv-adl-vk-full:
+  extends:
+    - anv-adl-vk
+    - .anv-manual-rules
+  variables:
+    DEQP_SUITE: anv-adl-full
+  timeout: 1h 40m
+  parallel: 3
+
+anv-rpl-vk:
+  extends:
+    - .lava-x86_64-test-vk
+    - .anv-test
+    - .lava-asus-CX3402CVA-brya:x86_64
+  variables:
+    DEQP_SUITE: anv-rpl
+    FDO_CI_CONCURRENT: 6  # We get OOMkills if we go too wide since VKCTS 1.4.4.0, persisting in 1.4.5.3.
+    # Xe regression in 6.19
+    # https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/7584
+    KERNEL_TAG: "v6.17-mesa-ddf6"
+  parallel: 10
+
+anv-tgl-vk:
+  extends:
+    - .lava-x86_64-test-vk
+    - .anv-test
+    - .lava-acer-cp514-2h-1160g7-volteer:x86_64
+  variables:
+    DEQP_SUITE: anv-tgl
+  parallel: 5
+
+anv-tgl-vk-full:
+  extends:
+    - anv-tgl-vk
+    - .anv-manual-rules
+  variables:
+    DEQP_SUITE: anv-tgl-full
+  timeout: 100m
+  parallel: 4
+
+anv-adl-fluster:
+  extends:
+    - .lava-x86_64-test-video
+    - .anv-test
+    - .lava-acer-chromebox-cxi5-brask:x86_64
+    - .test-fluster
+  variables:
+    DEQP_SUITE: anv-fluster
+
+# Takes too long since the 1.3.7.0 CTS uprev.
+.hasvk-hsw-full:
+  extends:
+    - .anholt-hsw-test
+    - .test-vk
+    - .deqp-test
+    - .hasvk-manual-rules
+  variables:
+    GPU_VERSION: hasvk-hsw
+    DEQP_SUITE: hasvk-hsw
+    VK_DRIVER: intel_hasvk
+    MESA_VK_IGNORE_CONFORMANCE_WARNING: 1
+  timeout: 2h
+
+.hasvk-hsw:
+  extends:
+    - .hasvk-hsw-full
+  variables:
+    DEQP_FRACTION: 10
+
+anv-jsl-angle:
+  extends:
+    - .anv-angle-test
+    - .lava-acer-cb317-1h-c3z6-dedede:x86_64
+  variables:
+    DEQP_SUITE: anv-jsl-angle
+    GPU_VERSION: angle-anv-jsl
+
+anv-jsl-angle-full:
+  extends:
+    - anv-jsl-angle
+    - .anv-manual-rules
+  variables:
+    DEQP_SUITE: anv-jsl-angle-full
+  parallel: 2
+
+anv-adl-angle:
+  extends:
+    - .anv-angle-test
+    - .lava-acer-chromebox-cxi5-brask:x86_64
+  variables:
+    DEQP_SUITE: anv-adl-angle
+    GPU_VERSION: angle-anv-adl
+  parallel: 5
+
+anv-adl-traces-restricted:
+  extends:
+    - .lava-x86_64-test-vk
+    - .traces-test
+    - .test-wine
+    - .anv-test
+    - .lava-acer-chromebox-cxi5-brask:x86_64
+    - .anv-restricted-rules
+  variables:
+    HWCI_START_WESTON: 1
+    ANGLE_TRACE_FILES_TAG: "2025-03-28"
+    REPLAY_CONFIG: traces-intel-restricted.toml
+    FDO_CI_CONCURRENT: 5  # Run the 10 traces in 2 sets of 5 to avoid OOMs
+  allow_failure: true
+
+anv-tgl-angle:
+  extends:
+    - .anv-angle-test
+    - .lava-acer-cp514-2h-1130g7-volteer:x86_64
+  variables:
+    DEQP_SUITE: anv-tgl-angle
+    GPU_VERSION: angle-anv-tgl
+  parallel: 2
+
+anv-adl-vkd3d:
+  extends:
+    - .lava-x86_64-test-vk
+    - .anv-test
+    - .test-vkd3d-proton
+    - .lava-acer-n20q11-r856ltn-p1s2-nissa:x86_64
+  variables:
+    # Random tests fail/crash when trying to run them in parallel
+    FDO_CI_CONCURRENT: 1
+
+anv-tgl-angle-full:
+  extends:
+    - anv-tgl-angle
+    - .anv-manual-rules
+  variables:
+    DEQP_SUITE: anv-tgl-angle-full
+  parallel: null
+
+iris-apl-deqp:
+  extends:
+    - .iris-apl-test
+    - .iris-manual-rules
+  variables:
+    DEQP_SUITE: iris-apl
+  parallel: 3
+
+iris-apl-egl:
+  extends:
+    - .iris-apl-test
+  variables:
+    PIGLIT_NO_WINDOW: 0
+    HWCI_START_WESTON: 1
+    DEQP_SUITE: iris-apl-egl
+
+iris-glk-deqp:
+  extends:
+    - .iris-glk-test
+  variables:
+    DEQP_SUITE: iris-glk
+
+iris-glk-egl:
+  extends:
+    - .iris-glk-test
+  variables:
+    PIGLIT_NO_WINDOW: 0
+    HWCI_START_WESTON: 1
+    DEQP_SUITE: iris-glk-egl
+
+iris-amly-deqp:
+  extends:
+    - .iris-amly-test
+  variables:
+    DEQP_SUITE: iris-amly
+  parallel: 3
+
+iris-kbl-deqp:
+  extends:
+    - .iris-kbl-test
+  variables:
+    DEQP_SUITE: iris-kbl
+  parallel: 3
+
+iris-cml-deqp:
+  extends:
+    - .iris-cml-test
+    # moved to nightly because of networking issues, gpu tests are all passing as expected
+    - .iris-manual-rules
+  variables:
+    DEQP_SUITE: iris-cml
+  parallel: 8
+
+iris-jsl-deqp:
+  extends:
+    - .iris-test
+    - .lava-acer-cb317-1h-c3z6-dedede:x86_64
+  variables:
+    DEQP_SUITE: iris-jsl
+    GPU_VERSION: iris-jsl
+    DEQP_FRACTION: 8
+  parallel: 2
+
+iris-adl-deqp:
+  extends:
+    - .iris-adl-test
+  variables:
+    DEQP_SUITE: iris-adl
+    GPU_VERSION: iris-adl
+  parallel: 5
+
+iris-amly-egl:
+  extends:
+    - .iris-amly-test
+  variables:
+    PIGLIT_NO_WINDOW: 0
+    HWCI_START_WESTON: 1
+    DEQP_SUITE: iris-amly-egl
+
+iris-kbl-piglit:
+  extends:
+    - .iris-kbl-test
+    - .test-piglit
+  parallel: 2
+  variables:
+    HWCI_START_XORG: 1
+    PIGLIT_NO_WINDOW: 0
+    DEQP_SUITE: iris-kbl-piglit
+
+iris-apl-traces:
+  variables:
+    GPU_VERSION: intel-apl
+  extends:
+    - .iris-apl-test
+    - .iris-traces
+
+iris-glk-traces:
+  variables:
+    GPU_VERSION: intel-glk
+  extends:
+    - .iris-glk-test
+    - .iris-traces
+
+iris-amly-traces:
+  variables:
+    GPU_VERSION: intel-amly
+  extends:
+    - .iris-amly-test
+    - .iris-traces
+
+iris-kbl-traces:
+  variables:
+    GPU_VERSION: intel-kbl
+  extends:
+    - .iris-kbl-test
+    - .iris-traces
+
+iris-cml-traces:
+  variables:
+    GPU_VERSION: intel-cml
+  extends:
+    - .iris-cml-test
+    - .iris-traces
+    # moved to nightly because of networking issues, gpu tests are all passing as expected
+    - .iris-manual-rules
+
+iris-apl-traces-performance:
+  extends:
+    - .iris-apl-test
+    - .profile-traces
+  variables:
+    GPU_VERSION: intel-apl
+
+iris-glk-traces-performance:
+  extends:
+    - .iris-glk-test
+    - .profile-traces
+  variables:
+    GPU_VERSION: intel-glk
+
+iris-amly-traces-performance:
+  extends:
+    - .iris-amly-test
+    - .profile-traces
+  variables:
+    GPU_VERSION: intel-amly
+
+iris-kbl-traces-performance:
+  extends:
+    - .iris-kbl-test
+    - .profile-traces
+  variables:
+    GPU_VERSION: intel-kbl
+
+iris-adl-traces-performance:
+  extends:
+    - .iris-adl-test
+    - .profile-traces
+  variables:
+    GPU_VERSION: intel-adl
+
+intel-adl-cl:
+  extends:
+    - .intel-adl-test
+    - .lava-acer-n20q11-r856ltn-p1s2-nissa:x86_64
+    - .intel-rules
+    - .test-piglit
+  rules:
+    - !reference [.intel-adl-test, rules]
+    - !reference [.intel-rules, rules]
+    - !reference [.rusticl-rules, rules]
+  variables:
+    DEQP_SUITE: intel-adl-cl
+    GPU_VERSION: intel-adl
+    VK_DRIVER: intel
+    HWCI_START_WESTON: 1
+
+intel-adl-skqp:
+  extends:
+    - .intel-adl-test
+    - .lava-acer-n20q11-r856ltn-p1s2-nissa:x86_64
+  variables:
+    DEQP_SUITE: intel-adl-skqp
+    VK_DRIVER: intel
+    HWCI_START_XORG: 1
+
+intel-tgl-skqp:
+  extends:
+    - .intel-tgl-test
+    - .lava-acer-cp514-2h-1130g7-volteer:x86_64
+  variables:
+    DEQP_SUITE: intel-tgl-skqp
+    VK_DRIVER: intel
+    HWCI_START_XORG: 1

src/intel/ci/hasvk-hsw-flakes.txt

@@ -0,0 +1,6 @@
+# Occasional segfaults after a DEVICE_LOST.
+dEQP-VK.synchronization.timeline_semaphore.device_host.write_copy_buffer_to_image_read_image_fragment.image_128x128_r8_unorm
+dEQP-VK.synchronization.timeline_semaphore.device_host.write_copy_image_read_copy_image.image_128x128_s8_uint
+
+# Flaked to have bad rendering
+dEQP-VK.memory.external_memory_host.synchronization.synchronization

src/intel/ci/hasvk-hsw-skips.txt

@@ -0,0 +1,7 @@
+# These definitely hang the GPU (VK_ERROR_DEVICE_LOST), and they take other
+# tests out with them.
+dEQP-VK.compute.basic.empty_workgroup_.*
+
+# Events are not implemented on gen7, and we seem to get GPU hangs that leak
+# into other tests when these tests fail.
+dEQP-VK.synchronization.*op.single_queue.event.*

src/intel/ci/intel-adl-fails.txt

@@ -0,0 +1,40 @@
+api@clbuildprogram,Fail
+api@clcompileprogram,Fail
+api@clgetcommandqueueinfo,Fail
+api@clgetdeviceinfo,Fail
+api@clgetextensionfunctionaddressforplatform,Fail
+api@clgetkernelarginfo,Fail
+api@cllinkprogram,Fail
+program@execute@global-offset,Fail
+program@execute@global-offset@3d- input dependent,Fail
+program@execute@vstore@vstore-char-private,Crash
+program@execute@vstore@vstore-short-private,Crash
+program@execute@vstore@vstore-uchar-private,Crash
+program@execute@vstore@vstore-ushort-private,Crash
+program@execute@vstore@vstore_half-float-private,Crash
+
+# (file=input,line=0,column=0,index=0): Unresolved external reference to "_Z21convert_char4_sat_rteDv4_i".
+program@execute@vector-conversion,Fail
+
+# Piglit CL bug
+api@clgetmemobjectinfo,Fail
+api@clsetkernelarg,Fail
+api@clsetkernelarg@Input checks,Fail
+program@execute@[email protected],Fail
+program@execute@[email protected]@nextafter float1,Fail
+program@execute@[email protected]@nextafter float16,Fail
+program@execute@[email protected]@nextafter float2,Fail
+program@execute@[email protected]@nextafter float4,Fail
+program@execute@[email protected]@nextafter float8,Fail
+
+# RUSTICL_FEATURES="fp64" bugs
+program@execute@amdgcn-f32-inline-immediates,Crash
+program@execute@amdgcn-f64-inline-immediates,Crash
+program@execute@fdiv-modifiers-f64,Crash
+program@execute@scalar-arithmetic-double,Crash
+program@execute@vstore@vstore_half-double-global,Crash
+program@execute@vstore@vstore_half-double-local,Crash
+program@execute@vstore@vstore_half-double-private,Crash
+program@execute@vstore@vstorea_half-double-global,Crash
+program@execute@vstore@vstorea_half-double-local,Crash
+program@execute@vstore@vstorea_half-double-private,Crash

src/intel/ci/intel-adl-flakes.txt

@@ -0,0 +1,10 @@
+# initial flakes
+gl_atlastext
+
+# uprev Piglit in Mesa
+program@execute@[email protected]
+program@execute@builtin@builtin-shuffle2-double-ulong
+program@execute@builtin@builtin-shuffle2-long-ulong
+
+# With linux kernel 6.13-rc4 uprev
+gl_degenerate_gradients

src/intel/ci/intel-tgl-flakes.txt

@@ -0,0 +1,8 @@
+gl_androidblendmodes
+gl_atlastext
+gl_localmatriximagefilter
+gl_typefacestyles
+gles_androidblendmodes
+gles_arithmode
+gles_localmatriximagefilter
+vk_crbug_899512

src/intel/ci/iris-adl-flakes.txt

@@ -0,0 +1,6 @@
+dEQP-GLES31.functional.primitive_bounding_box.lines.global_state.vertex_geometry_fragment.fbo_bbox_larger
+dEQP-GLES31.functional.primitive_bounding_box.lines.tessellation_set_per_draw.vertex_tessellation_fragment.fbo_bbox_smaller
+
+# Occasional GPU hang, devcore dump in the following job:
+# https://gitlab.freedesktop.org/mesa/mesa/-/jobs/82888653
+dEQP-GLES31.functional.fbo.no_attachments.maximums.all

src/intel/ci/iris-adl-skips.txt

@@ -0,0 +1,8 @@
+# Timeouts
+KHR-GL46.gpu_shader_fp64.builtin.inverse_dmat4
+KHR-GL46.gpu_shader_fp64.fp64.varyings
+KHR-GLES3.texture_lod_bias.texture_lod_bias_all
+KHR-Single-GL46.enhanced_layouts.xfb_global_buffer_dmat2x3
+KHR-Single-GL46.enhanced_layouts.xfb_global_buffer_dmat2x4
+KHR-Single-GL46.enhanced_layouts.xfb_global_buffer_dmat3x2
+KHR-Single-GL46.enhanced_layouts.xfb_global_buffer_dmat4x2

src/intel/ci/iris-amly-flakes.txt

@@ -0,0 +1,32 @@
+# Sometimes crashes with no log information
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copyteximage2d.1
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copyteximage2d.4
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copyteximage2d.12
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copytexsubimage2d.1
+
+dEQP-EGL.functional.color_clears.*.rgb888_pbuffer
+dEQP-EGL.functional.color_clears.*.rgba8888_pbuffer
+dEQP-EGL.functional.render.*.rgb888_pbuffer
+dEQP-EGL.functional.render.*.rgba8888_pbuffer
+
+# Some flaky tests found:
+#   spec@arb_query_buffer_object@qbo@query-GL_ANY_SAMPLES_PASSED-SYNC-GL_INT
+#   spec@arb_query_buffer_object@qbo@query-GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED-ASYNC-GL_UNSIGNED_INT64_ARB
+#   spec@arb_query_buffer_object@qbo@query-GL_SAMPLES_PASSED-ASYNC-GL_UNSIGNED_INT64_ARB
+#   spec@arb_query_buffer_object@qbo@query-GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN-ASYNC_CPU_READ_AFTER-GL_UNSIGNED_INT64_ARB
+#   spec@arb_query_buffer_object@qbo@query-GL_VERTEX_SHADER_INVOCATIONS-ASYNC_CPU_READ_AFTER-GL_UNSIGNED_INT64_ARB
+#   spec@arb_query_buffer_object@qbo@query-GL_TIMESTAMP-ASYNC_CPU_READ_BEFORE-GL_UNSIGNED_INT
+spec@arb_query_buffer_object@qbo@query-.*
+# Some flaky tests found:
+#   spec@arb_query_buffer_object@qbo@query-GL_ANY_SAMPLES_PASSED-SYNC-GL_INT
+#   spec@arb_query_buffer_object@qbo@query-GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED-ASYNC-GL_UNSIGNED_INT64_ARB
+#   spec@arb_query_buffer_object@qbo@query-GL_SAMPLES_PASSED-ASYNC-GL_UNSIGNED_INT64_ARB
+#   spec@arb_query_buffer_object@qbo@query-GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN-ASYNC_CPU_READ_AFTER-GL_UNSIGNED_INT64_ARB
+#   spec@arb_query_buffer_object@qbo@query-GL_VERTEX_SHADER_INVOCATIONS-ASYNC_CPU_READ_AFTER-GL_UNSIGNED_INT64_ARB
+#   spec@arb_query_buffer_object@qbo@query-GL_TIMESTAMP-ASYNC_CPU_READ_BEFORE-GL_UNSIGNED_INT
+spec@arb_query_buffer_object@qbo
+
+# The tests below are not actually detected as flaky, but they do behave as such
+spec@egl_chromium_sync_control@conformance
+spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test
+KHR-Single-GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive

src/intel/ci/iris-amly-skips.txt

@@ -0,0 +1,12 @@
+# triggers oomkiller and kills innocent tests!
+spec@!opengl 1.1@max-texture-size
+.*tex3d-maxsize.*
+
+# WGL is Windows-only
+wgl@.*
+# triggers oomkiller and kills innocent tests!
+spec@!opengl 1.1@max-texture-size
+.*tex3d-maxsize.*
+
+# WGL is Windows-only
+wgl@.*

src/intel/ci/iris-apl-flakes.txt

@@ -0,0 +1,27 @@
+# Sometimes crashes with no log information
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copyteximage2d.1
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copyteximage2d.4
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copyteximage2d.12
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copytexsubimage2d.1
+
+# Flakes from Mar-May 2022
+dEQP-EGL.functional.color_clears.*.rgb888_pbuffer
+dEQP-EGL.functional.color_clears.*.rgba8888_pbuffer
+dEQP-EGL.functional.render.*.rgb888_pbuffer
+dEQP-EGL.functional.render.*.rgba8888_pbuffer
+dEQP-EGL.functional.sharing.gles2.multithread.random_egl_sync.programs.link.7
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copyteximage2d.19
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copyteximage2d.6
+dEQP-EGL.functional.sharing.gles2.multithread.simple.buffers.bufferdata_render
+dEQP-EGL.functional.sharing.gles2.multithread.simple.buffers.buffersubdata_render
+
+# 2022-05-05 18:40:38.338304: [  830.056851] i915 0000:00:02.0: [drm] Resetting rcs0 for preemption time out
+# 2022-05-05 18:40:38.338503: [  830.064660] i915 0000:00:02.0: [drm] deqp-gles31[2571] context reset due to GPU hang
+# 2022-05-05 18:40:38.338548: [  830.144153] i915 0000:00:02.0: [drm] GPU HANG: ecode 9:1:87d79ffe, in deqp-gles31 [2571]
+dEQP-GLES31.functional.primitive_bounding_box.clear.scissored_clear_with_triangles
+dEQP-GLES31.functional.primitive_bounding_box.clear.scissored_clear_with_triangles_per_primitive_bbox
+
+# Nightly run expectations update
+KHR-Single-GL46.arrays_of_arrays_gl.AtomicDeclaration
+KHR-Single-GL46.arrays_of_arrays_gl.ConstructorsAndUnsizedDeclConstructorSizing1
+

src/intel/ci/iris-apl-skips.txt

@@ -0,0 +1,9 @@
+# timeouts
+wayland-dEQP-EGL.functional.buffer_age.no_preserve.*
+wayland-dEQP-EGL.functional.query_context.get_current_context.*
+wayland-dEQP-EGL.functional.query_context.get_current_surface.*
+wayland-dEQP-EGL.functional.resize.surface_size.stretch.*
+wayland-dEQP-EGL.functional.swap_buffers_with_damage.*
+
+KHR-Single-GL46.arrays_of_arrays_gl.ConstructorsAndUnsizedDeclConstructors1
+KHR-Single-GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive

src/intel/ci/iris-cml-fails.txt

@@ -0,0 +1,3 @@
+# Timed out after raising the iris-cml-deqp parallel number from 4 to 8.
+# https://gitlab.freedesktop.org/mesa/mesa/-/jobs/66875845
+KHR-Single-GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive,Timeout

src/intel/ci/iris-cml-flakes.txt

@@ -0,0 +1,6 @@
+spec@arb_query_buffer_object@qbo
+
+# Timed out after raising the iris-cml-deqp parallel number from 4 to 8.
+# https://gitlab.freedesktop.org/mesa/mesa/-/jobs/66875845
+KHR-Single-GL46.arrays_of_arrays_gl.AtomicDeclaration
+KHR-Single-GL46.arrays_of_arrays_gl.ConstructorsAndUnsizedDeclConstructorSizing1

src/intel/ci/iris-glk-fails.txt

@@ -0,0 +1,4 @@
+# "Result is different than expected at index: 33 Expected value: 664128 Result value: 658538 "
+KHR-GL46.texture_buffer.texture_buffer_atomic_functions,Fail
+
+KHR-GLES31.core.texture_buffer.texture_buffer_atomic_functions,Fail

src/intel/ci/iris-glk-flakes.txt

@@ -0,0 +1,18 @@
+KHR-GL46.texture_buffer.texture_buffer_atomic_functions
+KHR-GLES31.core.texture_buffer.texture_buffer_atomic_functions
+
+# Fails most likely due to a previous test hanging
+dEQP-GLES31.functional.primitive_bounding_box.clear.scissored_clear_with_triangles_per_primitive_bbox
+
+# Sometimes crashes with no log information
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copyteximage2d.1
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copyteximage2d.4
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copyteximage2d.12
+dEQP-EGL.functional.sharing.gles2.multithread.random.images.copytexsubimage2d.1
+
+dEQP-EGL.functional.color_clears.*.rgb888_pbuffer
+dEQP-EGL.functional.color_clears.*.rgba8888_pbuffer
+dEQP-EGL.functional.render.*.rgb888_pbuffer
+dEQP-EGL.functional.render.*.rgba8888_pbuffer
+
+dEQP-GLES31.functional.synchronization.inter_invocation.ssbo_atomic_alias_overwrite

src/intel/ci/iris-glk-skips.txt

@@ -0,0 +1,11 @@
+# timeouts
+wayland-dEQP-EGL.functional.buffer_age.no_preserve.*
+wayland-dEQP-EGL.functional.query_context.get_current_context.*
+wayland-dEQP-EGL.functional.query_context.get_current_display.*
+wayland-dEQP-EGL.functional.query_context.get_current_surface.*
+wayland-dEQP-EGL.functional.query_context.query_context.*
+wayland-dEQP-EGL.functional.resize.surface_size.*
+wayland-dEQP-EGL.functional.swap_buffers_with_damage.*
+wayland-dEQP-EGL.functional.wide_color.*
+
+KHR-Single-GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive

src/intel/ci/iris-jsl-flakes.txt

@@ -0,0 +1,7 @@
+# Happening since the introduction of testing it looks like.
+dEQP-GLES3.functional.fbo.invalidate.default.sub_bind_all
+KHR-GL46.geometry_shader.limits.max_combined_texture_units
+KHR-GL46.texture_cube_map_array.stencil_attachments_mutable_layered
+
+# With linux kernel 6.13-rc4 uprev
+dEQP-VK.subgroups.clustered.compute.subgroupclusteredmul_u64vec4_requiredsubgroupsize

src/intel/ci/iris-jsl-skips.txt

@@ -0,0 +1,5 @@
+# Randomly time out, even after 90 seconds
+KHR-GL46.gpu_shader_fp64.fp64.varyings
+KHR-GL46.gpu_shader_fp64.builtin.inverse_dmat4
+KHR-Single-GL46.enhanced_layouts.xfb_global_buffer
+KHR-Single-GL46.enhanced_layouts.xfb_override_qualifiers_with_api

src/intel/ci/iris-kbl-fails.txt

@@ -0,0 +1,112 @@
+glx@glx-make-current,Fail
+
+glx@glx-multi-window-single-context,Fail
+
+glx@glx-swap-pixmap-bad,Fail
+
+spec@!opengl 1.0@rasterpos,Fail
+
+spec@!opengl 1.0@rasterpos@glsl_vs_gs_linked,Fail
+spec@!opengl 1.0@rasterpos@glsl_vs_tes_linked,Fail
+
+spec@!opengl 1.1@linestipple,Fail
+spec@!opengl 1.1@linestipple@Factor 2x,Fail
+spec@!opengl 1.1@linestipple@Factor 3x,Fail
+spec@!opengl 1.1@linestipple@Line loop,Fail
+spec@!opengl 1.1@linestipple@Line strip,Fail
+
+# Fail: nothing rendered.
+spec@!opengl 2.0@vs-point_size-zero,Fail
+
+spec@arb_query_buffer_object@qbo,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIMESTAMP-ASYNC_CPU_READ_AFTER-GL_INT,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIMESTAMP-ASYNC_CPU_READ_AFTER-GL_UNSIGNED_INT,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIMESTAMP-ASYNC_CPU_READ_AFTER-GL_UNSIGNED_INT64_ARB,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIMESTAMP-ASYNC_CPU_READ_BEFORE-GL_INT,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIMESTAMP-ASYNC_CPU_READ_BEFORE-GL_UNSIGNED_INT,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIMESTAMP-SYNC_CPU_READ_AFTER_CACHE_TEST-GL_INT,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIMESTAMP-SYNC_CPU_READ_AFTER_CACHE_TEST-GL_UNSIGNED_INT,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIMESTAMP-SYNC_CPU_READ_AFTER_CACHE_TEST-GL_UNSIGNED_INT64_ARB,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIME_ELAPSED-ASYNC_CPU_READ_AFTER-GL_INT,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIME_ELAPSED-ASYNC_CPU_READ_AFTER-GL_UNSIGNED_INT,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIME_ELAPSED-ASYNC_CPU_READ_AFTER-GL_UNSIGNED_INT64_ARB,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIME_ELAPSED-SYNC_CPU_READ_AFTER_CACHE_TEST-GL_INT,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIME_ELAPSED-SYNC_CPU_READ_AFTER_CACHE_TEST-GL_UNSIGNED_INT,Fail
+spec@arb_query_buffer_object@qbo@query-GL_TIME_ELAPSED-SYNC_CPU_READ_AFTER_CACHE_TEST-GL_UNSIGNED_INT64_ARB,Fail
+
+spec@arb_shader_image_load_store@early-z,Fail
+spec@arb_shader_image_load_store@early-z@occlusion query test/early-z pass,Fail
+
+spec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,Fail
+
+# error: main:90: eglChooseConfig() returned no configs
+spec@egl 1.4@eglterminate then unbind context,Fail
+
+spec@egl_chromium_sync_control@conformance,Fail
+# piglit: error: SBC did not change after second SwapBuffers: 0
+spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test,Fail
+
+# Failed blit src(0,0;1,1) - dst(0,0;2147483647,2147483647)
+# Failed blit src(0,0;40,40) - dst(0,0;134217727,134217727)
+# Failed blit src(0,0;40,40) - dst(0,0;2147483647,2147483647)
+# Failed blit src(0,0;80,80) - dst(0,0;134217727,134217727)
+# Failed blit src(0,0;80,80) - dst(0,0;2147483647,2147483647)
+# Failed blit src(0,0;160,160) - dst(0,0;134217727,134217727)
+# Failed blit src(0,0;160,160) - dst(0,0;2147483647,2147483647)
+# Failed blit src(0,0;2147483647,2147483647) - dst(0,0;2147483647,2147483647)
+spec@ext_framebuffer_blit@fbo-blit-check-limits,Fail
+
+# Unexpected GL error: GL_INVALID_OPERATION 0x502
+# (Error at tests/egl/spec/egl_khr_gl_image/egl_khr_gl_renderbuffer_image-clear-shared-image.c:181)
+spec@egl_khr_gl_image@egl_khr_gl_renderbuffer_image-clear-shared-image gl_depth_component24,Fail
+
+# eglChooseConfig() failed
+spec@egl_khr_surfaceless_context@viewport,Fail
+spec@egl_mesa_configless_context@basic,Fail
+
+spec@ext_transform_feedback@tessellation triangle_fan flat_first,Fail
+
+# Testing GL_POINTS(1 vertices)
+#  Expected 0 GS invocations, got 1
+#  Expected vertex IDs:
+#  Actual vertex IDs:   1 1
+[email protected]@execution@geometry@primitive-types gl_line_loop,Fail
+
+# piglit: error: Miplevel 0
+# piglit: error: Mode ldrs Block 4x4.
+spec@khr_texture_compression_astc@miptree-gl srgb-fp,Fail
+spec@khr_texture_compression_astc@miptree-gl srgb-fp@sRGB decode full precision,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb-fp,Fail
+spec@khr_texture_compression_astc@miptree-gles srgb-fp@sRGB decode full precision,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl srgb-fp,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gl srgb-fp@sRGB decode full precision,Fail
+# piglit: error: Mode: ldrs Block: 5x5.
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp,Fail
+spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp@sRGB decode full precision,Fail
+
+spec@!opengl 1.1@line-smooth-coverage,Fail
+spec@!opengl 1.1@line-smooth-stipple,Fail
+
+# Uprev Piglit in Mesa
+spec@!opengl 1.1@large-tex,Fail
+spec@!opengl 1.1@large-tex@test_image_load_store,Fail
+spec@arb_framebuffer_object@execution@msaa-alpha-to-coverage_alpha-to-one,Fail
+spec@arb_framebuffer_object@execution@msaa-alpha-to-coverage_alpha-to-one_write-z,Fail
+spec@arb_framebuffer_object@execution@msaa-alpha-to-coverage,Fail
+spec@ext_external_objects@vk-image-display,Crash
+spec@ext_external_objects@vk-semaphores,Crash
+spec@ext_external_objects@vk-semaphores-2,Crash
+glx@glx-multithread-buffer-busy-tracking-bug,Fail
+
+# failed to create drawable
+# X Error of failed request:  BadValue (integer parameter out of range for operation)
+#   Major opcode of failed request:  53 (X_CreatePixmap)
+#   Value in failed request:  0x1e
+#   Serial number of failed request:  1177
+#   Current serial number in output stream:  1181
+glx@glx-visuals-depth -pixmap,Fail
+glx@glx-visuals-stencil -pixmap,Fail
+
+# uprev Piglit in Mesa
+spec@khr_shader_subgroup@execution@bitonic_sort,Fail
+

src/intel/ci/iris-kbl-flakes.txt

@@ -0,0 +1,26 @@
+spec@arb_query_buffer_object@qbo
+spec@amd_performance_monitor@measure
+spec@amd_performance_monitor@measure@change counters while active
+spec@amd_performance_monitor@measure@counters in range
+
+#X Error of failed request:  BadValue (integer parameter out of range for operation)
+#  Major opcode of failed request:  148 ()
+#  Minor opcode of failed request:  4
+#  Value in failed request:  0xa00007
+#  Serial number of failed request:  41
+#  Current serial number in output stream:  45
+glx@glx-multi-context-ib-1
+
+# The following two case are xfails, but sometimes pass.
+spec@egl_chromium_sync_control@conformance
+# piglit: error: SBC did not change after second SwapBuffers: 0
+spec@egl_chromium_sync_control@conformance@eglGetSyncValuesCHROMIUM_msc_and_sbc_test
+
+# See the https://gitlab.freedesktop.org/mesa/mesa/-/issues/7547
+spec@egl 1.4@largest possible eglcreatepbuffersurface and then glclear
+
+# uprev Piglit in Mesa
+spec@!opengl 1.2@tex3d-maxsize
+
+KHR-Single-GL46.arrays_of_arrays_gl.ConstructorsAndUnsizedDeclConstructors1
+KHR-Single-GL46.arrays_of_arrays_gl.ConstructorsAndUnsizedDeclConstructorSizing1

src/intel/ci/iris-kbl-skips.txt

@@ -0,0 +1,8 @@
+# Too slow for CI, can flake due to timeouts
+shaders@glsl-max-varyings >max_varying_components
+shaders@glsl-max-varyings
+spec@arb_compute_shader@local-id-explosion
+spec@ext_transform_feedback@max-varyings
+
+# Random timeout
+KHR-Single-GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive

src/intel/ci/iris-skips.txt

@@ -0,0 +1,17 @@
+# 60s timeout in CI
+dEQP-GLES31.functional.ubo.random.all_per_block_buffers.20
+KHR-GL46.copy_image.functional
+KHR-GL46.enhanced_layouts.uniform_block_member_align_non_power_of_2
+KHR-GL46.enhanced_layouts.uniform_block_member_invalid_offset_alignment
+KHR-GL46.enhanced_layouts.ssb_member_align_non_power_of_2
+KHR-GL46.enhanced_layouts.ssb_member_invalid_offset_alignment
+KHR-GL46.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_MaxPatchVertices_Position_PointSize
+KHR-GL46.texture_swizzle.functional
+KHR-GL46.texture_swizzle.smoke
+KHR-GLES31.core.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_MaxPatchVertices_Position_PointSize
+
+KHR-Single-GL46.arrays_of_arrays_gl.AtomicUsage
+KHR-Single-GL46.enhanced_layouts.ssb_member_align_non_power_of_2
+KHR-Single-GL46.enhanced_layouts.ssb_member_invalid_offset_alignment
+KHR-Single-GL46.enhanced_layouts.uniform_block_member_align_non_power_of_2
+KHR-Single-GL46.enhanced_layouts.uniform_block_member_invalid_offset_alignment

src/intel/ci/iris-whl-flakes.txt

@@ -0,0 +1 @@
+spec@arb_query_buffer_object@qbo

src/intel/ci/traces-intel-restricted.toml

@@ -0,0 +1,98 @@
+[traces_db]
+download_url = "https://s3.freedesktop.org/mesa-tracie-private/"
+
+[[traces]]
+path = "angle/angle_trace_tests/among_us"
+[traces.devices]
+anv-adl = { checksum = "54494f980da7e7af996f48aca9a2b74946ce3248ae4d05578190b450520bd19e" }
+
+[[traces]]
+path = "angle/angle_trace_tests/asphalt_9"
+[traces.devices]
+anv-adl = { checksum = "726844c6243ff9f2782ffd1e0e29f636239c9c58885336d08b86a55562a1a73d" }
+
+[[traces]]
+path = "angle/angle_trace_tests/brawl_starts"
+[traces.devices]
+anv-adl = { checksum = "3845dd1a5ca119c2ca13d918023201d462b9d6969a61c7114bdef65869445d49" }
+
+[[traces]]
+path = "angle/angle_trace_tests/candy_crush_soda_saga"
+[traces.devices]
+anv-adl = { checksum = "57450987a3587607ec5813fc13b6f0a990cceab28e676d027b76af11279e891b" }
+
+[[traces]]
+path = "angle/angle_trace_tests/free_fire"
+[traces.devices]
+anv-adl = { checksum = "a55f7e1bcf8004fadbe722dfd86c09bc026f7cf414efd57d13b973344df9175b" }
+
+[[traces]]
+path = "angle/angle_trace_tests/google_maps"
+[traces.devices]
+anv-adl = { checksum = "f0c803f23cb4a40b7bc78145a309772baa32c147acd46162ce39b5b22b6a0b4f" }
+
+[[traces]]
+path = "angle/angle_trace_tests/minetest"
+[traces.devices]
+anv-adl = { checksum = "63bcea065b22589bf4f0cf26a6b5f174d8e1d48819214dc32eb19258e7a3e22f" }
+
+[[traces]]
+path = "angle/angle_trace_tests/mobile_legends"
+[traces.devices]
+anv-adl = { checksum = "c5538bd3b68a8048c06ee925ac723e1bc24543960105a92997a85754dc7f145e" }
+
+[[traces]]
+path = "angle/angle_trace_tests/pubg_mobile_battle_royale"
+[traces.devices]
+anv-adl = { checksum = "baa2fa1d2f5b7ab2606a48ee6a599e8dbabb526f6466590f2b58629cfcb9f680" }
+
+[[traces]]
+path = "angle/angle_trace_tests/temple_run_300"
+[traces.devices]
+anv-adl = { checksum = "843e12d5a56ffa3d37682d69054476665859e4af896129d9ac54da00a4506319" }
+
+[[traces]]
+path = "steam-d3d9/deadspace3_unknown_dx9_unknown_unknown_none.trace"
+[traces.devices]
+anv-adl = { checksum = "8a7f5047a8c2587da500a97ba28074c34f555e9d2d796cb55879b8b366a6942b" }
+
+[[traces]]
+path = "steam-d3d9/drakensang_unknown_dx9_unknown_unknown_none.trace"
+[traces.devices]
+# Uses about 1GB on our device with 3GB available.
+anv-adl = { checksum = "1e5c0225c36659ad9515ddb5eabb0f8e26846cc8e89649405163576c7ae7d195", singlethread = true }
+
+[[traces]]
+path = "steam-d3d9/FalloutNewVegas_unknown_dx9_YesMan_ultra_1080p.trace"
+[traces.devices]
+anv-adl = { checksum = "5a408c19dbcf30cf3344ac93d88b0a2804f0f15104f2a4423de1f66ca2c8b259" }
+
+# steam-d3d9/FarCry2_unknown_dx9_unknown_unknown_none.trace: Had a crash flake.
+
+[[traces]]
+path = "steam-d3d9/KbWoTn_unknown_dx9_unknown_unknown_none.trace"
+[traces.devices]
+# Uses about 1.5GB on our device with 3GB available.
+anv-adl = { checksum = "99849e5cfc168931ff56b8cb9f915b2d463ccb56ba7f4f94d12503bd70594c93", singlethread = true }
+
+[[traces]]
+path = "steam-d3d9/Oblivion_unknown_dx9_unknown_unknown_none.trace"
+[traces.devices]
+anv-adl = { checksum = "2a50d28ae44c750354bdffcfb04d46adfa21434a1b1f99b4ff6ad6115e02c7dd" }
+
+[[traces]]
+path = "steam-d3d9/SpiderMan_unknown_dx9_unknown_unknown_none.trace"
+[traces.devices]
+anv-adl = { checksum = "082ac3af6a833f52ab0826d03a68d1b9c42afa21aaf928d5e3d5c78638f2684e" }
+
+[[traces]]
+path = "steam-d3d9/psychonauts_unknown_dx9_unknown_unknown_none.trace"
+nonloopable = true
+[traces.devices]
+anv-adl = { checksum = "06fac809f402e90d93809bc9cba4b8112091bfbc4462bc8422a58376a698ef1c" }
+
+[[traces]]
+path = "steam-d3d9/TFT_unknown_dx9_unknown_unknown_none.trace"
+[traces.devices]
+# Uses about 1GB on our device with 3GB available.
+anv-adl = { checksum = "d6e11e7b3c3b4af355a565e6cdbc3c32bead81100660a5f3e90ebe04536f6fc3", singlethread = true  }

src/intel/ci/traces-iris.yml

@@ -0,0 +1,629 @@
+%YAML 1.2
+---
+traces-db:
+  download-url: https://s3.freedesktop.org/mesa-tracie-public/
+
+traces:
+  behdad-glyphy/glyphy-v2.trace:
+    gl-intel-apl:
+      checksum: 5c7e2fc5961b43a18ea65523fe025b96
+    gl-intel-glk:
+      checksum: 5c7e2fc5961b43a18ea65523fe025b96
+    gl-intel-amly:
+      checksum: 5c7e2fc5961b43a18ea65523fe025b96
+    gl-intel-kbl:
+      checksum: 5c7e2fc5961b43a18ea65523fe025b96
+    gl-intel-whl:
+      checksum: 5c7e2fc5961b43a18ea65523fe025b96
+    gl-intel-cml:
+      checksum: 5c7e2fc5961b43a18ea65523fe025b96
+    gl-intel-adl:
+      checksum: 5c7e2fc5961b43a18ea65523fe025b96
+  glxgears/glxgears-2-v2.trace:
+    gl-intel-apl:
+      checksum: f53ac20e17da91c0359c31f2fa3f401e
+    gl-intel-glk:
+      checksum: f53ac20e17da91c0359c31f2fa3f401e
+    gl-intel-amly:
+      checksum: f53ac20e17da91c0359c31f2fa3f401e
+    gl-intel-kbl:
+      checksum: f53ac20e17da91c0359c31f2fa3f401e
+    gl-intel-whl:
+      checksum: f53ac20e17da91c0359c31f2fa3f401e
+    gl-intel-cml:
+      checksum: f53ac20e17da91c0359c31f2fa3f401e
+    gl-intel-adl:
+      checksum: f53ac20e17da91c0359c31f2fa3f401e
+  0ad/0ad-v2.trace:
+    gl-intel-apl:
+      checksum: 6c9f66db38f03847574c543de48fa203
+    gl-intel-glk:
+      checksum: 6c9f66db38f03847574c543de48fa203
+    gl-intel-amly:
+      checksum: 6c9f66db38f03847574c543de48fa203
+    gl-intel-kbl:
+      checksum: 6c9f66db38f03847574c543de48fa203
+    gl-intel-whl:
+      checksum: e67b7a93bac02e41de0326419ee17a3e
+    gl-intel-cml:
+      checksum: 6c9f66db38f03847574c543de48fa203
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 6c9f66db38f03847574c543de48fa203
+  pathfinder/demo-v2.trace:
+    gl-intel-apl:
+      checksum: d9b33f0a2efe17c21b7933242afd9ec7
+    gl-intel-glk:
+      checksum: d9b33f0a2efe17c21b7933242afd9ec7
+    gl-intel-amly:
+      checksum: d9b33f0a2efe17c21b7933242afd9ec7
+    gl-intel-kbl:
+      checksum: d9b33f0a2efe17c21b7933242afd9ec7
+    gl-intel-whl:
+      checksum: d9b33f0a2efe17c21b7933242afd9ec7
+    gl-intel-cml:
+      checksum: d9b33f0a2efe17c21b7933242afd9ec7
+    gl-intel-adl:
+      checksum: d9b33f0a2efe17c21b7933242afd9ec7
+  pathfinder/canvas_moire-v2.trace:
+    gl-intel-apl:
+      checksum: 21bccd42f2deb6416cf6591cd6a99258
+    gl-intel-glk:
+      checksum: 21bccd42f2deb6416cf6591cd6a99258
+    gl-intel-amly:
+      checksum: 21bccd42f2deb6416cf6591cd6a99258
+    gl-intel-kbl:
+      checksum: 21bccd42f2deb6416cf6591cd6a99258
+    gl-intel-whl:
+      checksum: 21bccd42f2deb6416cf6591cd6a99258
+    gl-intel-cml:
+      checksum: 21bccd42f2deb6416cf6591cd6a99258
+    gl-intel-adl:
+      checksum: 21bccd42f2deb6416cf6591cd6a99258
+  pathfinder/canvas_text_v2-v2.trace:
+    gl-intel-apl:
+      checksum: 448886e3b24f6408e013ea13f7c96d28
+    gl-intel-glk:
+      checksum: 448886e3b24f6408e013ea13f7c96d28
+    gl-intel-amly:
+      checksum: 448886e3b24f6408e013ea13f7c96d28
+    gl-intel-kbl:
+      checksum: 448886e3b24f6408e013ea13f7c96d28
+    gl-intel-whl:
+      checksum: 448886e3b24f6408e013ea13f7c96d28
+    gl-intel-cml:
+      checksum: 448886e3b24f6408e013ea13f7c96d28
+    gl-intel-adl:
+      checksum: 448886e3b24f6408e013ea13f7c96d28
+  gputest/furmark-v2.trace:
+    gl-intel-apl:
+      checksum: 54305eb5dd7fea9e34bd61567bbd4c08
+    gl-intel-glk:
+      checksum: 54305eb5dd7fea9e34bd61567bbd4c08
+    gl-intel-amly:
+      checksum: 54305eb5dd7fea9e34bd61567bbd4c08
+    gl-intel-kbl:
+      checksum: 54305eb5dd7fea9e34bd61567bbd4c08
+    gl-intel-whl:
+      checksum: 06d587a2b934295da6ad874b750b9c9d
+    gl-intel-cml:
+      checksum: 54305eb5dd7fea9e34bd61567bbd4c08
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 06f4222f7f5737f93ed1d191cbdc0798
+  gputest/triangle-v2.trace:
+    gl-intel-apl:
+      checksum: 0a1524303e0772f6d869e4875fe1f401
+    gl-intel-glk:
+      checksum: 0a1524303e0772f6d869e4875fe1f401
+    gl-intel-amly:
+      checksum: 0a1524303e0772f6d869e4875fe1f401
+    gl-intel-kbl:
+      checksum: 0a1524303e0772f6d869e4875fe1f401
+    gl-intel-whl:
+      checksum: 0a1524303e0772f6d869e4875fe1f401
+    gl-intel-cml:
+      checksum: 0a1524303e0772f6d869e4875fe1f401
+    gl-intel-adl:
+      checksum: 0a1524303e0772f6d869e4875fe1f401
+  godot/Material Testers.x86_64_2020.04.08_13.38_frame799.rdc:
+    gl-intel-apl:
+      label: [skip]
+      text: Nothing wrong with it, proxy issues. Revert ASAP.
+      checksum: dbe1de4e2e812413f173ea6c423117ff
+    gl-intel-glk:
+      label: [skip]
+      text: Nothing wrong with it, proxy issues. Revert ASAP.
+      checksum: dbe1de4e2e812413f173ea6c423117ff
+    gl-intel-amly:
+      label: [skip]
+      text: Nothing wrong with it, proxy issues. Revert ASAP.
+      checksum: dbe1de4e2e812413f173ea6c423117ff
+    gl-intel-kbl:
+      label: [skip]
+      text: Nothing wrong with it, proxy issues. Revert ASAP.
+      checksum: dbe1de4e2e812413f173ea6c423117ff
+    gl-intel-whl:
+      label: [skip]
+      text: Nothing wrong with it, proxy issues. Revert ASAP.
+      checksum: dbe1de4e2e812413f173ea6c423117ff
+    gl-intel-cml:
+      label: [skip]
+      text: Nothing wrong with it, proxy issues. Revert ASAP.
+      checksum: dbe1de4e2e812413f173ea6c423117ff
+    gl-intel-adl:
+      label: [skip, no-perf]
+      text: Nothing wrong with it, proxy issues. Revert ASAP.
+      checksum: dbe1de4e2e812413f173ea6c423117ff
+  gputest/pixmark-julia-fp32-v2.trace:
+    gl-intel-apl:
+      checksum: 9d0245893820b58fafb56e6d50b1e84b
+    gl-intel-glk:
+      checksum: 9d0245893820b58fafb56e6d50b1e84b
+    gl-intel-amly:
+      checksum: 9d0245893820b58fafb56e6d50b1e84b
+    gl-intel-kbl:
+      checksum: 9d0245893820b58fafb56e6d50b1e84b
+    gl-intel-whl:
+      checksum: a5ec72a5da355dfcd689411f89164f0c
+    gl-intel-cml:
+      checksum: 9d0245893820b58fafb56e6d50b1e84b
+    gl-intel-adl:
+      checksum: 9d0245893820b58fafb56e6d50b1e84b
+  gputest/pixmark-julia-fp64-v2.trace:
+    gl-intel-apl:
+      checksum: f56761af17be6231bce480115cde3cec
+    gl-intel-glk:
+      checksum: f56761af17be6231bce480115cde3cec
+    gl-intel-amly:
+      checksum: f56761af17be6231bce480115cde3cec
+    gl-intel-kbl:
+      checksum: f56761af17be6231bce480115cde3cec
+    gl-intel-whl:
+      checksum: 95235e084d88bc41f8a1a05b79e88e33
+    gl-intel-cml:
+      checksum: f56761af17be6231bce480115cde3cec
+    gl-intel-adl:
+      checksum: f56761af17be6231bce480115cde3cec
+  gputest/pixmark-volplosion-v2.trace:
+    gl-intel-apl:
+      checksum: 8463a40fbc699c9cf887b97dae831786
+    gl-intel-glk:
+      checksum: 8463a40fbc699c9cf887b97dae831786
+    gl-intel-amly:
+      checksum: 8463a40fbc699c9cf887b97dae831786
+    gl-intel-kbl:
+      checksum: 8463a40fbc699c9cf887b97dae831786
+    gl-intel-whl:
+      checksum: 9c891fd21b0cdc79f7071001d95d549c
+    gl-intel-cml:
+      checksum: 8463a40fbc699c9cf887b97dae831786
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 9c891fd21b0cdc79f7071001d95d549c
+  gputest/plot3d-v2.trace:
+    gl-intel-apl:
+      checksum: 8510dc46ba2d5a25030d07fdf1710f90
+    gl-intel-glk:
+      checksum: 8510dc46ba2d5a25030d07fdf1710f90
+    gl-intel-amly:
+      checksum: 8510dc46ba2d5a25030d07fdf1710f90
+    gl-intel-kbl:
+      checksum: 8510dc46ba2d5a25030d07fdf1710f90
+    gl-intel-whl:
+      checksum: cea8f26227763a3c3b2a2a6af9a0c1da
+    gl-intel-cml:
+      checksum: 8510dc46ba2d5a25030d07fdf1710f90
+    gl-intel-adl:
+      checksum: cea8f26227763a3c3b2a2a6af9a0c1da
+  gputest/tessmark-v2.trace:
+    gl-intel-apl:
+      checksum: f9309a25e696938c0372c1afc781d01b
+    gl-intel-glk:
+      checksum: f9309a25e696938c0372c1afc781d01b
+    gl-intel-amly:
+      checksum: f9309a25e696938c0372c1afc781d01b
+    gl-intel-kbl:
+      checksum: f9309a25e696938c0372c1afc781d01b
+    gl-intel-whl:
+      checksum: 10e49cd5a5e12d4a01f504c14b4335cc
+    gl-intel-cml:
+      checksum: f9309a25e696938c0372c1afc781d01b
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: f9309a25e696938c0372c1afc781d01b
+  humus/AmbientAperture-v2.trace:
+    gl-intel-apl:
+      checksum: 5d0d439423d38d2f0f2520e6a1c4c819
+    gl-intel-glk:
+      checksum: 5d0d439423d38d2f0f2520e6a1c4c819
+    gl-intel-amly:
+      checksum: 5d0d439423d38d2f0f2520e6a1c4c819
+    gl-intel-kbl:
+      checksum: 5d0d439423d38d2f0f2520e6a1c4c819
+    gl-intel-whl:
+      checksum: 5d0d439423d38d2f0f2520e6a1c4c819
+    gl-intel-cml:
+      checksum: 5d0d439423d38d2f0f2520e6a1c4c819
+    gl-intel-adl:
+      checksum: 5d0d439423d38d2f0f2520e6a1c4c819
+  humus/Portals-v2.trace:
+    gl-intel-apl:
+      checksum: 4b50340b8898687c37a908e799f9238e
+    gl-intel-glk:
+      checksum: 4b50340b8898687c37a908e799f9238e
+    gl-intel-amly:
+      checksum: 4b50340b8898687c37a908e799f9238e
+    gl-intel-kbl:
+      checksum: 4b50340b8898687c37a908e799f9238e
+    gl-intel-whl:
+      checksum: 4b50340b8898687c37a908e799f9238e
+    gl-intel-cml:
+      checksum: 4b50340b8898687c37a908e799f9238e
+    gl-intel-adl:
+      checksum: 4b50340b8898687c37a908e799f9238e
+  humus/CelShading-v2.trace:
+    gl-intel-apl:
+      checksum: 5476bd1ed551e20fbe118dc8b4b5d515
+    gl-intel-glk:
+      checksum: 5476bd1ed551e20fbe118dc8b4b5d515
+    gl-intel-amly:
+      checksum: 5476bd1ed551e20fbe118dc8b4b5d515
+    gl-intel-kbl:
+      checksum: 5476bd1ed551e20fbe118dc8b4b5d515
+    gl-intel-whl:
+      checksum: 5476bd1ed551e20fbe118dc8b4b5d515
+    gl-intel-cml:
+      checksum: 5476bd1ed551e20fbe118dc8b4b5d515
+    gl-intel-adl:
+      checksum: 5476bd1ed551e20fbe118dc8b4b5d515
+  humus/DynamicBranching3-v2.trace:
+    gl-intel-apl:
+      checksum: 51d5ffe732076a80ffaa7f935c528c42
+    gl-intel-glk:
+      checksum: 51d5ffe732076a80ffaa7f935c528c42
+    gl-intel-amly:
+      checksum: 51d5ffe732076a80ffaa7f935c528c42
+    gl-intel-kbl:
+      checksum: 51d5ffe732076a80ffaa7f935c528c42
+    gl-intel-whl:
+      checksum: 51d5ffe732076a80ffaa7f935c528c42
+    gl-intel-cml:
+      checksum: 51d5ffe732076a80ffaa7f935c528c42
+    gl-intel-adl:
+      checksum: 51d5ffe732076a80ffaa7f935c528c42
+  humus/HDR-v2.trace:
+    gl-intel-apl:
+      checksum: e23bfd9704f3cc6ce3fd38685f5d3c61
+    gl-intel-glk:
+      checksum: e23bfd9704f3cc6ce3fd38685f5d3c61
+    gl-intel-amly:
+      checksum: e23bfd9704f3cc6ce3fd38685f5d3c61
+    gl-intel-kbl:
+      checksum: e23bfd9704f3cc6ce3fd38685f5d3c61
+    gl-intel-whl:
+      checksum: e23bfd9704f3cc6ce3fd38685f5d3c61
+    gl-intel-cml:
+      checksum: e23bfd9704f3cc6ce3fd38685f5d3c61
+    gl-intel-adl:
+      checksum: e23bfd9704f3cc6ce3fd38685f5d3c61
+  humus/RaytracedShadows-v2.trace:
+    gl-intel-apl:
+      checksum: c6ecea7b8ddb60526af4de7ec1a5be62
+    gl-intel-glk:
+      checksum: c6ecea7b8ddb60526af4de7ec1a5be62
+    gl-intel-amly:
+      checksum: c6ecea7b8ddb60526af4de7ec1a5be62
+    gl-intel-kbl:
+      checksum: c6ecea7b8ddb60526af4de7ec1a5be62
+    gl-intel-whl:
+      checksum: c6ecea7b8ddb60526af4de7ec1a5be62
+    gl-intel-cml:
+      checksum: c6ecea7b8ddb60526af4de7ec1a5be62
+    gl-intel-adl:
+      checksum: c6ecea7b8ddb60526af4de7ec1a5be62
+  humus/VolumetricFogging2-v2.trace:
+    gl-intel-apl:
+      checksum: 2224e04e0aa162c19a22cbeb5bf16114
+    gl-intel-glk:
+      checksum: 2224e04e0aa162c19a22cbeb5bf16114
+    gl-intel-amly:
+      checksum: 2224e04e0aa162c19a22cbeb5bf16114
+    gl-intel-kbl:
+      checksum: 2224e04e0aa162c19a22cbeb5bf16114
+    gl-intel-whl:
+      checksum: 2224e04e0aa162c19a22cbeb5bf16114
+    gl-intel-cml:
+      checksum: 2224e04e0aa162c19a22cbeb5bf16114
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 2224e04e0aa162c19a22cbeb5bf16114
+  neverball/neverball-v2.trace:
+    gl-intel-apl:
+      checksum: 75acd3160d268de2c5f286ff4546258c
+    gl-intel-glk:
+      checksum: 75acd3160d268de2c5f286ff4546258c
+    gl-intel-amly:
+      checksum: 75acd3160d268de2c5f286ff4546258c
+    gl-intel-kbl:
+      checksum: 75acd3160d268de2c5f286ff4546258c
+    gl-intel-whl:
+      checksum: 75acd3160d268de2c5f286ff4546258c
+    gl-intel-cml:
+      checksum: 75acd3160d268de2c5f286ff4546258c
+    gl-intel-adl:
+      checksum: 75acd3160d268de2c5f286ff4546258c
+  paraview/pv-manyspheres-v2.trace:
+    gl-intel-apl:
+      checksum: 73e5d34fb13268b0c7126297bfc34965
+    gl-intel-glk:
+      checksum: 73e5d34fb13268b0c7126297bfc34965
+    gl-intel-amly:
+      checksum: 73e5d34fb13268b0c7126297bfc34965
+    gl-intel-kbl:
+      checksum: 73e5d34fb13268b0c7126297bfc34965
+    gl-intel-whl:
+      checksum: 73e5d34fb13268b0c7126297bfc34965
+    gl-intel-cml:
+      checksum: 73e5d34fb13268b0c7126297bfc34965
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 73e5d34fb13268b0c7126297bfc34965
+  paraview/pv-waveletcontour-v2.trace:
+    gl-intel-apl:
+      checksum: b384e3e81e4843fbd1d50e0c542e600a
+    gl-intel-glk:
+      checksum: b384e3e81e4843fbd1d50e0c542e600a
+    gl-intel-amly:
+      checksum: b384e3e81e4843fbd1d50e0c542e600a
+    gl-intel-kbl:
+      checksum: b384e3e81e4843fbd1d50e0c542e600a
+    gl-intel-whl:
+      checksum: b384e3e81e4843fbd1d50e0c542e600a
+    gl-intel-cml:
+      checksum: b384e3e81e4843fbd1d50e0c542e600a
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: b384e3e81e4843fbd1d50e0c542e600a
+  paraview/pv-waveletvolume-v2.trace:
+    gl-intel-apl:
+      checksum: 6517788d0f65166239e4f3000ebf5d95
+    gl-intel-glk:
+      checksum: 6517788d0f65166239e4f3000ebf5d95
+    gl-intel-amly:
+      checksum: 6517788d0f65166239e4f3000ebf5d95
+    gl-intel-kbl:
+      checksum: 6517788d0f65166239e4f3000ebf5d95
+    gl-intel-whl:
+      checksum: 0199b30fe719261436d6d48fe51353c8
+    gl-intel-cml:
+      checksum: 6517788d0f65166239e4f3000ebf5d95
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 6517788d0f65166239e4f3000ebf5d95
+  supertuxkart/supertuxkart-antediluvian-abyss.rdc:
+    gl-intel-apl:
+      checksum: 61c806382a69a91c5ea19e621b379031
+    gl-intel-glk:
+      checksum: 61c806382a69a91c5ea19e621b379031
+    gl-intel-amly:
+      checksum: 61c806382a69a91c5ea19e621b379031
+    gl-intel-kbl:
+      checksum: 61c806382a69a91c5ea19e621b379031
+    gl-intel-whl:
+      checksum: 0af2faa0d9183c1bc4dc7612befe1f0a
+    gl-intel-cml:
+      checksum: 61c806382a69a91c5ea19e621b379031
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 0af2faa0d9183c1bc4dc7612befe1f0a
+  supertuxkart/supertuxkart-menu.rdc:
+    gl-intel-apl:
+      checksum: 0a4095dc7b441643a3336975b61c9e6a
+    gl-intel-glk:
+      checksum: 0a4095dc7b441643a3336975b61c9e6a
+    gl-intel-amly:
+      checksum: 0a4095dc7b441643a3336975b61c9e6a
+    gl-intel-kbl:
+      checksum: 0a4095dc7b441643a3336975b61c9e6a
+    gl-intel-whl:
+      checksum: 0a4095dc7b441643a3336975b61c9e6a
+    gl-intel-cml:
+      checksum: 0a4095dc7b441643a3336975b61c9e6a
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 0a4095dc7b441643a3336975b61c9e6a
+  supertuxkart/supertuxkart-ravenbridge-mansion.rdc:
+    gl-intel-apl:
+      checksum: 2b461f3b03c6450ab6a7b3f49203a2ee
+    gl-intel-glk:
+      checksum: 2b461f3b03c6450ab6a7b3f49203a2ee
+    gl-intel-amly:
+      checksum: 2b461f3b03c6450ab6a7b3f49203a2ee
+    gl-intel-kbl:
+      checksum: 2b461f3b03c6450ab6a7b3f49203a2ee
+    gl-intel-whl:
+      checksum: ca0b64f1a62e01765146be8391eae636
+    gl-intel-cml:
+      checksum: 2b461f3b03c6450ab6a7b3f49203a2ee
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: ca0b64f1a62e01765146be8391eae636
+  valve/counterstrike-v2.trace:
+    gl-intel-apl:
+      checksum: 757e0c9a37ecfc5a2efb10505f98ad95
+    gl-intel-glk:
+      checksum: 757e0c9a37ecfc5a2efb10505f98ad95
+    gl-intel-amly:
+      checksum: 757e0c9a37ecfc5a2efb10505f98ad95
+    gl-intel-kbl:
+      checksum: 757e0c9a37ecfc5a2efb10505f98ad95
+    gl-intel-whl:
+      checksum: 757e0c9a37ecfc5a2efb10505f98ad95
+    gl-intel-cml:
+      checksum: 757e0c9a37ecfc5a2efb10505f98ad95
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 757e0c9a37ecfc5a2efb10505f98ad95
+  ror/ror-default.trace:
+    gl-intel-apl:
+      checksum: dde3a4118bca61afdb5fcd94c30e61cd
+    gl-intel-glk:
+      checksum: dde3a4118bca61afdb5fcd94c30e61cd
+    gl-intel-amly:
+      checksum: dde3a4118bca61afdb5fcd94c30e61cd
+    gl-intel-kbl:
+      checksum: dde3a4118bca61afdb5fcd94c30e61cd
+    gl-intel-whl:
+      checksum: dde3a4118bca61afdb5fcd94c30e61cd
+    gl-intel-cml:
+      checksum: dde3a4118bca61afdb5fcd94c30e61cd
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: dde3a4118bca61afdb5fcd94c30e61cd
+  valve/counterstrike-source-v2.trace:
+    gl-intel-apl:
+      checksum: bba796c4723b651c4a8d0c7a9ebbfadc
+    gl-intel-glk:
+      checksum: bba796c4723b651c4a8d0c7a9ebbfadc
+    gl-intel-amly:
+      checksum: bba796c4723b651c4a8d0c7a9ebbfadc
+    gl-intel-kbl:
+      checksum: bba796c4723b651c4a8d0c7a9ebbfadc
+    gl-intel-whl:
+      checksum: 838ed7482efd5e9d7bde2b67e62314c4
+    gl-intel-cml:
+      checksum: bba796c4723b651c4a8d0c7a9ebbfadc
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 7d736f5ab20cf3cd29d97a40c2144229
+  valve/half-life-2-v2.trace:
+    gl-intel-apl:
+      checksum: a50f5f1e004d17261c2e9e1dea2801f8
+    gl-intel-glk:
+      checksum: a50f5f1e004d17261c2e9e1dea2801f8
+    gl-intel-amly:
+      checksum: a50f5f1e004d17261c2e9e1dea2801f8
+    gl-intel-kbl:
+      checksum: a50f5f1e004d17261c2e9e1dea2801f8
+    gl-intel-whl:
+      checksum: c4ba4cdc96396b354b0040278b374b15
+    gl-intel-cml:
+      checksum: a50f5f1e004d17261c2e9e1dea2801f8
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 21fb5eeb7215f6856d9af6827788ad77
+  valve/portal-2-v2.trace:
+    gl-intel-apl:
+      checksum: b3c0a68ab6dbcfde8fe72c8d0c44f528
+    gl-intel-glk:
+      checksum: b3c0a68ab6dbcfde8fe72c8d0c44f528
+    gl-intel-amly:
+      checksum: b3c0a68ab6dbcfde8fe72c8d0c44f528
+    gl-intel-kbl:
+      checksum: b3c0a68ab6dbcfde8fe72c8d0c44f528
+    gl-intel-whl:
+      checksum: b3c0a68ab6dbcfde8fe72c8d0c44f528
+    gl-intel-cml:
+      checksum: b3c0a68ab6dbcfde8fe72c8d0c44f528
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: b3c0a68ab6dbcfde8fe72c8d0c44f528
+  xonotic/xonotic-keybench-high-v2.trace:
+    gl-intel-apl:
+      checksum: 3d419f45bc5ce210a7df583e92143089
+    gl-intel-glx:
+      checksum: 3d419f45bc5ce210a7df583e92143089
+    gl-intel-amly:
+      checksum: 3d419f45bc5ce210a7df583e92143089
+    gl-intel-kbl:
+      checksum: 3d419f45bc5ce210a7df583e92143089
+    gl-intel-whl:
+      checksum: 3d419f45bc5ce210a7df583e92143089
+    gl-intel-cml:
+      checksum: 3d419f45bc5ce210a7df583e92143089
+    gl-intel-adl:
+      checksum: 3d419f45bc5ce210a7df583e92143089
+  blender/blender-demo-cube_diorama.trace:
+    gl-intel-apl:
+      label: [skip, flakes, no-perf]
+      checksum: 6a0e17d98eca33e80810b6158e998aa1
+      text: causes intermittent timeouts
+    gl-intel-glx:
+      label: [no-perf]
+      checksum: 6a0e17d98eca33e80810b6158e998aa1
+    gl-intel-amly:
+      label: [no-perf]
+      checksum: 46555aa91e3f9b3f12f93a28b4ff069b
+    gl-intel-kbl:
+      label: [no-perf]
+      checksum: 46555aa91e3f9b3f12f93a28b4ff069b
+    gl-intel-whl:
+      label: [no-perf]
+      checksum: 6a0e17d98eca33e80810b6158e998aa1
+    gl-intel-cml:
+      label: [no-perf]
+      checksum: 46555aa91e3f9b3f12f93a28b4ff069b
+    gl-intel-adl:
+      label: [no-perf]
+      checksum: 85b4f3279fde206dace85ffd727057ea
+  blender/blender-demo-ellie_pose.trace:
+    gl-intel-apl:
+      checksum: 61d144ac9cd8cbba11b19bb1174855bc
+    gl-intel-glx:
+      checksum: 61d144ac9cd8cbba11b19bb1174855bc
+    gl-intel-amly:
+      checksum: 61d144ac9cd8cbba11b19bb1174855bc
+    gl-intel-kbl:
+      checksum: 61d144ac9cd8cbba11b19bb1174855bc
+    gl-intel-whl:
+      checksum: 61d144ac9cd8cbba11b19bb1174855bc
+    gl-intel-cml:
+      checksum: 61d144ac9cd8cbba11b19bb1174855bc
+    gl-intel-adl:
+      checksum: 61d144ac9cd8cbba11b19bb1174855bc
+  unvanquished/unvanquished-lowest.trace:
+    gl-intel-apl:
+      checksum: 884096b6dd40e2f500d0837501287fac
+    gl-intel-glx:
+      checksum: 884096b6dd40e2f500d0837501287fac
+    gl-intel-amly:
+      checksum: 884096b6dd40e2f500d0837501287fac
+    gl-intel-kbl:
+      checksum: 884096b6dd40e2f500d0837501287fac
+    gl-intel-whl:
+      checksum: 884096b6dd40e2f500d0837501287fac
+    gl-intel-cml:
+      checksum: 884096b6dd40e2f500d0837501287fac
+    gl-intel-adl:
+      checksum: 884096b6dd40e2f500d0837501287fac
+  unvanquished/unvanquished-ultra.trace:
+    gl-intel-apl:
+      checksum: c4ff3894eaf7fb4b3632fd46e50b0128
+    gl-intel-glx:
+      checksum: c4ff3894eaf7fb4b3632fd46e50b0128
+    gl-intel-amly:
+      checksum: c4ff3894eaf7fb4b3632fd46e50b0128
+    gl-intel-kbl:
+      checksum: c4ff3894eaf7fb4b3632fd46e50b0128
+    gl-intel-whl:
+      checksum: c4ff3894eaf7fb4b3632fd46e50b0128
+    gl-intel-cml:
+      checksum: c4ff3894eaf7fb4b3632fd46e50b0128
+    gl-intel-adl:
+      checksum: c4ff3894eaf7fb4b3632fd46e50b0128
+  warzone2100/warzone2100-default.trace:
+    gl-intel-apl:
+      checksum: ceeba6125a74145fc7ab38157239f6f5
+    gl-intel-glx:
+      checksum: ceeba6125a74145fc7ab38157239f6f5
+    gl-intel-amly:
+      checksum: ceeba6125a74145fc7ab38157239f6f5
+    gl-intel-kbl:
+      checksum: ceeba6125a74145fc7ab38157239f6f5
+    gl-intel-whl:
+      checksum: ceeba6125a74145fc7ab38157239f6f5
+    gl-intel-cml:
+      checksum: ceeba6125a74145fc7ab38157239f6f5
+    gl-intel-adl:
+      checksum: ceeba6125a74145fc7ab38157239f6f5

src/intel/common/i915/intel_defines.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef INTEL_DEFINES_H
+#define INTEL_DEFINES_H
+
+#include "drm-uapi/i915_drm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * \file gen_defines.h
+ *
+ * Common defines we want to share between GL And Vulkan.
+ */
+
+#define INTEL_CONTEXT_LOW_PRIORITY ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
+#define INTEL_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
+#define INTEL_CONTEXT_HIGH_PRIORITY ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
+/* We don't have a strict notion of RT (yet, and when we do it is likely
+ * to be more complicated than a mere priority value!), but we can give
+ * it the absolute most priority available to us. By convention, this
+ * is higher than any other client, except for blocked interactive
+ * clients.
+ */
+#define INTEL_CONTEXT_REALTIME_PRIORITY I915_CONTEXT_MAX_USER_PRIORITY
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* INTEL_DEFINES_H */

src/intel/common/i915/intel_engine.c

@@ -0,0 +1,130 @@
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "i915/intel_engine.h"
+
+#include <stdlib.h>
+
+#include "i915/intel_gem.h"
+
+static enum intel_engine_class
+i915_engine_class_to_intel(enum drm_i915_gem_engine_class i915)
+{
+   switch (i915) {
+   case I915_ENGINE_CLASS_RENDER:
+      return INTEL_ENGINE_CLASS_RENDER;
+   case I915_ENGINE_CLASS_COPY:
+      return INTEL_ENGINE_CLASS_COPY;
+   case I915_ENGINE_CLASS_VIDEO:
+      return INTEL_ENGINE_CLASS_VIDEO;
+   case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+      return INTEL_ENGINE_CLASS_VIDEO_ENHANCE;
+   case I915_ENGINE_CLASS_COMPUTE:
+      return INTEL_ENGINE_CLASS_COMPUTE;
+   default:
+      return INTEL_ENGINE_CLASS_INVALID;
+   }
+}
+
+enum drm_i915_gem_engine_class
+intel_engine_class_to_i915(enum intel_engine_class intel)
+{
+   switch (intel) {
+   case INTEL_ENGINE_CLASS_RENDER:
+      return I915_ENGINE_CLASS_RENDER;
+   case INTEL_ENGINE_CLASS_COPY:
+      return I915_ENGINE_CLASS_COPY;
+   case INTEL_ENGINE_CLASS_VIDEO:
+      return I915_ENGINE_CLASS_VIDEO;
+   case INTEL_ENGINE_CLASS_VIDEO_ENHANCE:
+      return I915_ENGINE_CLASS_VIDEO_ENHANCE;
+   case INTEL_ENGINE_CLASS_COMPUTE:
+      return I915_ENGINE_CLASS_COMPUTE;
+   default:
+      return I915_ENGINE_CLASS_INVALID;
+   }
+}
+
+struct intel_query_engine_info *
+i915_engine_get_info(int fd)
+{
+   struct drm_i915_query_engine_info *i915_engines_info;
+   i915_engines_info = intel_i915_query_alloc(fd, DRM_I915_QUERY_ENGINE_INFO, NULL);
+   if (!i915_engines_info)
+      return NULL;
+
+   struct intel_query_engine_info *intel_engines_info;
+   intel_engines_info = calloc(1, sizeof(*intel_engines_info) +
+                               sizeof(*intel_engines_info->engines) *
+                               i915_engines_info->num_engines);
+   if (!intel_engines_info) {
+      free(i915_engines_info);
+      return NULL;
+   }
+
+   for (int i = 0; i < i915_engines_info->num_engines; i++) {
+      struct drm_i915_engine_info *i915_engine = &i915_engines_info->engines[i];
+      struct intel_engine_class_instance *intel_engine = &intel_engines_info->engines[i];
+
+      intel_engine->engine_class = i915_engine_class_to_intel(i915_engine->engine.engine_class);
+      intel_engine->engine_instance = i915_engine->engine.engine_instance;
+      intel_engine->gt_id = 0;
+   }
+
+   intel_engines_info->num_engines = i915_engines_info->num_engines;
+
+   free(i915_engines_info);
+   return intel_engines_info;
+}
+
+bool
+i915_engines_is_guc_semaphore_functional(int fd, const struct intel_device_info *info)
+{
+   struct drm_i915_query_guc_submission_version *guc_submission_ver =
+      intel_i915_query_alloc(fd, DRM_I915_QUERY_GUC_SUBMISSION_VERSION, NULL);
+   uint32_t read_ver, min_ver;
+
+   if (guc_submission_ver == NULL)
+      return false;
+
+   /* branch == 0 is mainline branch, any other branch value indicates that
+    * other version numbers cannot be used to infer whether features or fixes
+    * are present in the release.
+    *
+    * major, minor and patch are u8 for GuC, uAPI have it as u32 because of HuC.
+    */
+   if (guc_submission_ver->branch == 0) {
+      read_ver = guc_submission_ver->major << 16;
+      read_ver |= guc_submission_ver->minor << 8;
+      read_ver |= guc_submission_ver->patch;
+   } else {
+      read_ver = 0;
+   }
+
+   free(guc_submission_ver);
+
+   /* Requires at least GuC submission version 1.1.3 */
+   min_ver = 1ULL << 16 | 1ULL << 8 | 3;
+
+   return read_ver >= min_ver;
+}

src/intel/common/i915/intel_engine.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+
+#include "common/intel_engine.h"
+
+#include "drm-uapi/i915_drm.h"
+
+enum drm_i915_gem_engine_class
+intel_engine_class_to_i915(enum intel_engine_class intel);
+struct intel_query_engine_info *
+i915_engine_get_info(int fd);
+
+bool
+i915_engines_is_guc_semaphore_functional(int fd, const struct intel_device_info *info);

src/intel/common/i915/intel_gem.c

@@ -0,0 +1,366 @@
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "i915/intel_gem.h"
+
+#include "common/intel_gem.h"
+#include "i915/intel_engine.h"
+
+#include "drm-uapi/i915_drm.h"
+#include "drm-uapi/dma-buf.h"
+
+#include <fcntl.h>
+
+bool
+i915_gem_create_context(int fd, uint32_t *context_id)
+{
+   struct drm_i915_gem_context_create create = {};
+   if (intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create))
+      return false;
+   *context_id = create.ctx_id;
+   return true;
+}
+
+bool
+i915_gem_destroy_context(int fd, uint32_t context_id)
+{
+   struct drm_i915_gem_context_destroy destroy = {
+      .ctx_id = context_id,
+   };
+   return intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY, &destroy) == 0;
+}
+
+bool
+i915_gem_create_context_engines(int fd,
+                                enum intel_gem_create_context_flags flags,
+                                const struct intel_query_engine_info *info,
+                                int num_engines, enum intel_engine_class *engine_classes,
+                                uint32_t vm_id,
+                                uint32_t *context_id)
+{
+   assert(info != NULL);
+   assert(num_engines <= 64);
+   I915_DEFINE_CONTEXT_PARAM_ENGINES(engines_param, 64);
+   engines_param.extensions = 0;
+
+   /* For each type of intel_engine_class of interest, we keep track of
+    * the previous engine instance used.
+    */
+   int last_engine_idx[] = {
+      [INTEL_ENGINE_CLASS_RENDER] = -1,
+      [INTEL_ENGINE_CLASS_COPY] = -1,
+      [INTEL_ENGINE_CLASS_COMPUTE] = -1,
+      [INTEL_ENGINE_CLASS_VIDEO] = -1,
+   };
+
+   int engine_counts[] = {
+      [INTEL_ENGINE_CLASS_RENDER] =
+         intel_engines_count(info, INTEL_ENGINE_CLASS_RENDER),
+      [INTEL_ENGINE_CLASS_COPY] =
+         intel_engines_count(info, INTEL_ENGINE_CLASS_COPY),
+      [INTEL_ENGINE_CLASS_COMPUTE] =
+         intel_engines_count(info, INTEL_ENGINE_CLASS_COMPUTE),
+      [INTEL_ENGINE_CLASS_VIDEO] =
+         intel_engines_count(info, INTEL_ENGINE_CLASS_VIDEO),
+   };
+
+   /* For each queue, we look for the next instance that matches the class we
+    * need.
+    */
+   for (int i = 0; i < num_engines; i++) {
+      enum intel_engine_class engine_class = engine_classes[i];
+      assert(engine_class == INTEL_ENGINE_CLASS_RENDER ||
+             engine_class == INTEL_ENGINE_CLASS_COPY ||
+             engine_class == INTEL_ENGINE_CLASS_COMPUTE ||
+             engine_class == INTEL_ENGINE_CLASS_VIDEO);
+      if (engine_counts[engine_class] <= 0)
+         return false;
+
+      /* Run through the engines reported by the kernel looking for the next
+       * matching instance. We loop in case we want to create multiple
+       * contexts on an engine instance.
+       */
+      int engine_instance = -1;
+      for (int i = 0; i < info->num_engines; i++) {
+         int *idx = &last_engine_idx[engine_class];
+         if (++(*idx) >= info->num_engines)
+            *idx = 0;
+         if (info->engines[*idx].engine_class == engine_class) {
+            engine_instance = info->engines[*idx].engine_instance;
+            break;
+         }
+      }
+      if (engine_instance < 0)
+         return false;
+
+      engines_param.engines[i].engine_class = intel_engine_class_to_i915(engine_class);
+      engines_param.engines[i].engine_instance = engine_instance;
+   }
+
+   uint32_t size = sizeof(engines_param.extensions);
+   size += sizeof(engines_param.engines[0]) * num_engines;
+   struct drm_i915_gem_context_create_ext_setparam set_engines = {
+      .param = {
+         .param = I915_CONTEXT_PARAM_ENGINES,
+         .value = (uintptr_t)&engines_param,
+         .size = size,
+      }
+   };
+   struct drm_i915_gem_context_create_ext_setparam protected_param = {
+      .param = {
+         .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+         .value = flags & INTEL_GEM_CREATE_CONTEXT_EXT_PROTECTED_FLAG,
+      },
+   };
+   struct drm_i915_gem_context_create_ext_setparam recoverable_param = {
+      .param = {
+         .param = I915_CONTEXT_PARAM_RECOVERABLE,
+         .value = flags & INTEL_GEM_CREATE_CONTEXT_EXT_RECOVERABLE_FLAG,
+      },
+   };
+   struct drm_i915_gem_context_create_ext_setparam low_latency_param = {
+      .param = {
+         .param = I915_CONTEXT_PARAM_LOW_LATENCY,
+         .value = flags & INTEL_GEM_CREATE_CONTEXT_EXT_LOW_LATENCY_FLAG,
+      }
+   };
+   struct drm_i915_gem_context_create_ext create = {
+      .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+   };
+   struct drm_i915_gem_context_create_ext_setparam vm_param = {
+      .param = {
+         .param = I915_CONTEXT_PARAM_VM,
+         .value = vm_id,
+      },
+   };
+
+   intel_i915_gem_add_ext(&create.extensions,
+                          I915_CONTEXT_CREATE_EXT_SETPARAM,
+                          &set_engines.base);
+   intel_i915_gem_add_ext(&create.extensions,
+                          I915_CONTEXT_CREATE_EXT_SETPARAM,
+                          &recoverable_param.base);
+
+   if (vm_id != 0) {
+      intel_i915_gem_add_ext(&create.extensions,
+                             I915_CONTEXT_CREATE_EXT_SETPARAM,
+                             &vm_param.base);
+   }
+
+   if (flags & INTEL_GEM_CREATE_CONTEXT_EXT_PROTECTED_FLAG) {
+      intel_i915_gem_add_ext(&create.extensions,
+                             I915_CONTEXT_CREATE_EXT_SETPARAM,
+                             &protected_param.base);
+   }
+
+   if (flags & INTEL_GEM_CREATE_CONTEXT_EXT_LOW_LATENCY_FLAG) {
+      intel_i915_gem_add_ext(&create.extensions,
+                             I915_CONTEXT_CREATE_EXT_SETPARAM,
+                             &low_latency_param.base);
+   }
+
+   int ret;
+   bool retry;
+   do {
+      ret = intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &create);
+      retry = ret == -1 && errno == EIO &&
+              (flags & INTEL_GEM_CREATE_CONTEXT_EXT_PROTECTED_FLAG);
+      if (retry)
+         usleep(1000);
+   } while (retry);
+
+   if (ret)
+      return false;
+
+   *context_id = create.ctx_id;
+   return true;
+}
+
+bool
+i915_gem_set_context_param(int fd, uint32_t context, uint32_t param,
+                           uint64_t value)
+{
+   struct drm_i915_gem_context_param p = {
+      .ctx_id = context,
+      .param = param,
+      .value = value,
+   };
+   return intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &p) == 0;
+}
+
+bool
+i915_gem_get_context_param(int fd, uint32_t context, uint32_t param,
+                           uint64_t *value)
+{
+   struct drm_i915_gem_context_param gp = {
+      .ctx_id = context,
+      .param = param,
+   };
+   if (intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &gp))
+      return false;
+   *value = gp.value;
+   return true;
+}
+
+bool
+i915_gem_read_render_timestamp(int fd, uint64_t *value)
+{
+   struct drm_i915_reg_read reg_read = {
+      .offset = RCS_TIMESTAMP | I915_REG_READ_8B_WA,
+   };
+
+   int ret = intel_ioctl(fd, DRM_IOCTL_I915_REG_READ, &reg_read);
+   if (ret == 0)
+      *value = reg_read.val;
+   return ret == 0;
+}
+
+bool
+i915_gem_create_context_ext(int fd,
+                            enum intel_gem_create_context_flags flags,
+                            uint32_t *ctx_id)
+{
+   struct drm_i915_gem_context_create_ext_setparam recoverable_param = {
+      .param = {
+         .param = I915_CONTEXT_PARAM_RECOVERABLE,
+         .value = flags & INTEL_GEM_CREATE_CONTEXT_EXT_RECOVERABLE_FLAG,
+      },
+   };
+   struct drm_i915_gem_context_create_ext_setparam protected_param = {
+      .param = {
+         .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+         .value = flags & INTEL_GEM_CREATE_CONTEXT_EXT_PROTECTED_FLAG,
+      },
+   };
+   struct drm_i915_gem_context_create_ext create = {
+      .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+   };
+
+   intel_i915_gem_add_ext(&create.extensions,
+                          I915_CONTEXT_CREATE_EXT_SETPARAM,
+                          &recoverable_param.base);
+   intel_i915_gem_add_ext(&create.extensions,
+                          I915_CONTEXT_CREATE_EXT_SETPARAM,
+                          &protected_param.base);
+
+   if (intel_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &create))
+      return false;
+
+   *ctx_id = create.ctx_id;
+   return true;
+}
+
+bool
+i915_gem_supports_protected_context(int fd)
+{
+   int val = 0;
+   uint32_t ctx_id;
+   bool ret;
+
+   errno = 0;
+   if (!i915_gem_get_param(fd, I915_PARAM_PXP_STATUS, &val)) {
+      if (errno == ENODEV)
+         return false;
+   } else {
+      return (val > 0);
+   }
+
+   /* failed without ENODEV, so older kernels require a creation test */
+   ret = i915_gem_create_context_ext(fd,
+                                     INTEL_GEM_CREATE_CONTEXT_EXT_PROTECTED_FLAG,
+                                     &ctx_id);
+   if (!ret)
+      return ret;
+
+   i915_gem_destroy_context(fd, ctx_id);
+   return ret;
+}
+
+bool
+i915_gem_get_param(int fd, uint32_t param, int *value)
+{
+   drm_i915_getparam_t gp = {
+      .param = param,
+      .value = value,
+   };
+   return intel_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) == 0;
+}
+
+bool
+i915_gem_can_render_on_fd(int fd)
+{
+   int val;
+   return intel_gem_get_param(fd, I915_PARAM_CHIPSET_ID, &val) && val > 0;
+}
+
+bool
+i915_gem_supports_dma_buf_sync_file(int fd)
+{
+   uint32_t handle = 0;
+   int err = 0, dma_buf_fd = -1;
+
+   struct drm_i915_gem_create gem_create = {
+      .size = 64 << 10,
+   };
+   if (intel_ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create))
+      return false;
+
+   handle = gem_create.handle;
+
+   struct drm_prime_handle handle_to_fd = {
+      .handle = handle,
+      .flags = DRM_CLOEXEC | DRM_RDWR,
+   };
+   err = intel_ioctl(fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &handle_to_fd);
+   if (err)
+      goto fail;
+
+   dma_buf_fd = handle_to_fd.fd;
+
+   struct dma_buf_export_sync_file export = {
+      .flags = DMA_BUF_SYNC_RW,
+      .fd = -1,
+   };
+   err = intel_ioctl(dma_buf_fd, DMA_BUF_IOCTL_EXPORT_SYNC_FILE, &export);
+   if (err)
+      goto fail;
+
+   struct dma_buf_import_sync_file import = {
+      .flags = DMA_BUF_SYNC_RW,
+      .fd = export.fd,
+   };
+   err = intel_ioctl(dma_buf_fd, DMA_BUF_IOCTL_IMPORT_SYNC_FILE, &import);
+   close(export.fd);
+
+fail:
+   if (dma_buf_fd >= 0)
+      close(dma_buf_fd);
+
+   if (handle != 0) {
+      struct drm_gem_close gem_close = { .handle = handle };
+      err = intel_ioctl(fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
+      assert(err == 0);
+   }
+
+   return !err;
+}

src/intel/common/i915/intel_gem.h

@@ -0,0 +1,169 @@
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "common/intel_gem.h"
+#include "util/os_time.h"
+
+#include "drm-uapi/i915_drm.h"
+
+bool i915_gem_create_context(int fd, uint32_t *context_id);
+bool i915_gem_destroy_context(int fd, uint32_t context_id);
+bool i915_gem_create_context_engines(int fd,
+                                     enum intel_gem_create_context_flags flags,
+                                     const struct intel_query_engine_info *info,
+                                     int num_engines, enum intel_engine_class *engine_classes,
+                                     uint32_t vm_id,
+                                     uint32_t *context_id);
+bool i915_gem_set_context_param(int fd, uint32_t context, uint32_t param,
+                                uint64_t value);
+bool i915_gem_get_context_param(int fd, uint32_t context, uint32_t param,
+                                uint64_t *value);
+bool i915_gem_read_render_timestamp(int fd, uint64_t *value);
+bool
+i915_gem_create_context_ext(int fd,
+                            enum intel_gem_create_context_flags flags,
+                            uint32_t *ctx_id);
+bool i915_gem_supports_protected_context(int fd);
+bool i915_gem_get_param(int fd, uint32_t param, int *value);
+bool i915_gem_can_render_on_fd(int fd);
+bool i915_gem_supports_dma_buf_sync_file(int fd);
+
+/**
+ * A wrapper around DRM_IOCTL_I915_QUERY
+ *
+ * Unfortunately, the error semantics of this ioctl are rather annoying so
+ * it's better to have a common helper.
+ */
+static inline int
+intel_i915_query_flags(int fd, uint64_t query_id, uint32_t flags,
+                       void *buffer, int32_t *buffer_len)
+{
+   struct drm_i915_query_item item = {
+      .query_id = query_id,
+      .length = *buffer_len,
+      .flags = flags,
+      .data_ptr = (uintptr_t)buffer,
+   };
+
+   struct drm_i915_query args = {
+      .num_items = 1,
+      .flags = 0,
+      .items_ptr = (uintptr_t)&item,
+   };
+
+   int ret = intel_ioctl(fd, DRM_IOCTL_I915_QUERY, &args);
+   if (ret != 0)
+      return -errno;
+   else if (item.length < 0)
+      return item.length;
+
+   *buffer_len = item.length;
+   return 0;
+}
+
+static inline int
+intel_i915_query(int fd, uint64_t query_id, void *buffer,
+                 int32_t *buffer_len)
+{
+   return intel_i915_query_flags(fd, query_id, 0, buffer, buffer_len);
+}
+
+/**
+ * Query for the given data, allocating as needed
+ *
+ * The caller is responsible for freeing the returned pointer.
+ */
+static inline void *
+intel_i915_query_alloc(int fd, uint64_t query_id, int32_t *query_length)
+{
+   if (query_length)
+      *query_length = 0;
+
+   int32_t length = 0;
+   int ret = intel_i915_query(fd, query_id, NULL, &length);
+   if (ret < 0)
+      return NULL;
+
+   void *data = calloc(1, length);
+   assert(data != NULL); /* This shouldn't happen in practice */
+   if (data == NULL)
+      return NULL;
+
+   ret = intel_i915_query(fd, query_id, data, &length);
+   assert(ret == 0); /* We should have caught the error above */
+   if (ret < 0) {
+      free(data);
+      return NULL;
+   }
+
+   if (query_length)
+      *query_length = length;
+
+   return data;
+}
+
+static inline void
+intel_i915_gem_add_ext(__u64 *ptr, uint32_t ext_name,
+                  struct i915_user_extension *ext)
+{
+   __u64 *iter = ptr;
+
+   while (*iter != 0) {
+      iter = (__u64 *) &((struct i915_user_extension *)(uintptr_t)*iter)->next_extension;
+   }
+
+   ext->name = ext_name;
+
+   *iter = (uintptr_t) ext;
+}
+
+static inline int
+i915_gem_execbuf_ioctl(int fd, const struct intel_device_info *info,
+                       struct drm_i915_gem_execbuffer2 *execbuf)
+{
+   int ret, retries;
+
+   assert((execbuf->flags & I915_EXEC_FENCE_OUT) == 0);
+
+   if (unlikely(info->no_hw))
+      return 0;
+
+   for (retries = 0; retries < INTEL_EXEC_IOCTL_MAX_RETRIES; retries++) {
+      ret = intel_ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, execbuf);
+
+      if (likely(!(ret && errno == ENOMEM)))
+         break;
+
+      if (unlikely(retries == INTEL_EXEC_IOCTL_RETRY_WARN))
+         fprintf(stderr, "intel: the execbuf ioctl keeps returning ENOMEM\n");
+
+      os_time_sleep(intel_exec_ioctl_sleep_us(retries));
+   }
+
+   return ret;
+}

src/intel/common/intel_aux_map.c

@@ -0,0 +1,787 @@
+/*
+ * Copyright (c) 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/**
+ * The aux map provides a multi-level lookup of the main surface address which
+ * ends up providing information about the auxiliary surface data, including
+ * the address where the auxiliary data resides.
+ *
+ * The below sections depict address splitting and formats of table entries of
+ * TGL platform. These may vary on other platforms.
+ *
+ * The 48-bit VMA (GPU) address of the main surface is split to do the address
+ * lookup:
+ *
+ *  48 bit address of main surface
+ * +--------+--------+--------+------+
+ * | 47:36  | 35:24  | 23:16  | 15:0 |
+ * | L3-idx | L2-idx | L1-idx | ...  |
+ * +--------+--------+--------+------+
+ *
+ * The GFX_AUX_TABLE_BASE_ADDR points to a buffer. The L3 Table Entry is
+ * located by indexing into this buffer as a uint64_t array using the L3-idx
+ * value. The 64-bit L3 entry is defined as:
+ *
+ * +-------+-------------+------+---+
+ * | 63:48 | 47:15       | 14:1 | 0 |
+ * |  ...  | L2-tbl-addr | ...  | V |
+ * +-------+-------------+------+---+
+ *
+ * If the `V` (valid) bit is set, then the L2-tbl-addr gives the address for
+ * the level-2 table entries, with the lower address bits filled with zero.
+ * The L2 Table Entry is located by indexing into this buffer as a uint64_t
+ * array using the L2-idx value. The 64-bit L2 entry is similar to the L3
+ * entry, except with 2 additional address bits:
+ *
+ * +-------+-------------+------+---+
+ * | 63:48 | 47:13       | 12:1 | 0 |
+ * |  ...  | L1-tbl-addr | ...  | V |
+ * +-------+-------------+------+---+
+ *
+ * If the `V` bit is set, then the L1-tbl-addr gives the address for the
+ * level-1 table entries, with the lower address bits filled with zero. The L1
+ * Table Entry is located by indexing into this buffer as a uint64_t array
+ * using the L1-idx value. The 64-bit L1 entry is defined as:
+ *
+ * +--------+------+-------+-------+-------+---------------+-----+---+
+ * | 63:58  | 57   | 56:54 | 53:52 | 51:48 | 47:8          | 7:1 | 0 |
+ * | Format | Y/Cr | Depth |  TM   |  ...  | aux-data-addr | ... | V |
+ * +--------+------+-------+-------+-------+---------------+-----+---+
+ *
+ * Where:
+ *  - Format: See `get_format_encoding`
+ *  - Y/Cr: 0=Y(Luma), 1=Cr(Chroma)
+ *  - (bit) Depth: See `get_bpp_encoding`
+ *  - TM (Tile-mode): 0=Ys, 1=Y, 2=rsvd, 3=rsvd
+ *  - aux-data-addr: VMA/GPU address for the aux-data
+ *  - V: entry is valid
+ *
+ * BSpec 44930
+ */
+
+#include "intel_aux_map.h"
+#include "intel_gem.h"
+
+#include "dev/intel_device_info.h"
+#include "isl/isl.h"
+
+#include "util/list.h"
+#include "util/ralloc.h"
+#include "util/u_atomic.h"
+#include "util/u_math.h"
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <pthread.h>
+
+#define INTEL_AUX_MAP_FORMAT_BITS_MASK   0xfff0000000000000ull
+
+/* Mask with the firt 48bits set */
+#define VALID_ADDRESS_MASK ((1ull << 48) - 1)
+
+#define L3_ENTRY_L2_ADDR_MASK 0xffffffff8000ull
+
+#define L3_L2_BITS_PER_LEVEL 12
+#define L3_L2_SUB_TABLE_LEN (sizeof(uint64_t) * (1ull << L3_L2_BITS_PER_LEVEL))
+
+static const bool aux_map_debug = false;
+
+/**
+ * Auxiliary surface mapping formats
+ *
+ * Several formats of AUX mapping exist. The supported formats
+ * are designated by generation and granularity here. A device
+ * can support more than one format, depending on Hardware, but
+ * we expect only one of them of a device is needed. Otherwise,
+ * we could need to change this enum into a bit map in such case
+ * later.
+ */
+enum intel_aux_map_format {
+   /**
+    * 64KB granularity format on GFX12 devices
+    */
+   INTEL_AUX_MAP_GFX12_64KB = 0,
+
+   /**
+    * 1MB granularity format on GFX125 devices
+    */
+   INTEL_AUX_MAP_GFX125_1MB,
+
+   INTEL_AUX_MAP_LAST,
+};
+
+/**
+ * An incomplete description of AUX mapping formats
+ *
+ * Theoretically, many things can be different, depending on hardware
+ * design like level of page tables, address splitting, format bits
+ * etc. We only manage the known delta to simplify the implementation
+ * this time.
+ */
+struct aux_format_info {
+   /**
+    * Granularity of main surface in compression. It must be power of 2.
+    */
+   uint64_t main_page_size;
+   /**
+    * Page size of level 1 page table. It must be power of 2.
+    */
+   uint64_t l1_page_size;
+   /**
+    * Mask of index bits of level 1 page table in address splitting.
+    */
+   uint64_t l1_index_mask;
+   /**
+    * Offset of index bits of level 1 page table in address splitting.
+    */
+   uint64_t l1_index_offset;
+};
+
+static const struct aux_format_info aux_formats[] = {
+   [INTEL_AUX_MAP_GFX12_64KB] = {
+      .main_page_size = 64 * 1024,
+      .l1_page_size = 8 * 1024,
+      .l1_index_mask = 0xff,
+      .l1_index_offset = 16,
+   },
+   [INTEL_AUX_MAP_GFX125_1MB] = {
+      .main_page_size = 1024 * 1024,
+      .l1_page_size = 2 * 1024,
+      .l1_index_mask = 0xf,
+      .l1_index_offset = 20,
+   },
+};
+
+struct aux_map_buffer {
+   struct list_head link;
+   struct intel_buffer *buffer;
+};
+
+struct intel_aux_level {
+   /* GPU address of the  current level */
+   uint64_t address;
+
+   /* Pointer to the GPU entries of this level */
+   uint64_t *entries;
+
+   union {
+      /* Host tracking of a parent level to its children (only use on L3/L2
+       * levels which have 4096 entries)
+       */
+      struct intel_aux_level *children[4096];
+
+      /* Refcount of AUX pages at the L1 level (MTL has only 16 entries in L1,
+       * which Gfx12 has 256 entries)
+       */
+      uint32_t ref_counts[256];
+   };
+};
+
+struct intel_aux_map_context {
+   void *driver_ctx;
+   pthread_mutex_t mutex;
+   struct intel_aux_level *l3_level;
+   struct intel_mapped_pinned_buffer_alloc *buffer_alloc;
+   uint32_t num_buffers;
+   struct list_head buffers;
+   uint32_t tail_offset, tail_remaining;
+   uint32_t state_num;
+   const struct aux_format_info *format;
+};
+
+static inline uint64_t
+get_page_mask(const uint64_t page_size)
+{
+   return page_size - 1;
+}
+
+static inline uint64_t
+get_meta_page_size(const struct aux_format_info *info)
+{
+   return info->main_page_size / INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN;
+}
+
+static inline uint64_t
+get_index(const uint64_t main_address,
+      const uint64_t index_mask, const uint64_t index_offset)
+{
+   return (main_address >> index_offset) & index_mask;
+}
+
+uint64_t
+intel_aux_get_meta_address_mask(struct intel_aux_map_context *ctx)
+{
+   return (~get_page_mask(get_meta_page_size(ctx->format))) & VALID_ADDRESS_MASK;
+}
+
+uint64_t
+intel_aux_main_to_aux_offset(struct intel_aux_map_context *ctx,
+                             uint64_t main_offset)
+{
+   return main_offset / INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN;
+}
+
+static const struct aux_format_info *
+get_format(enum intel_aux_map_format format)
+{
+
+   assert(format < INTEL_AUX_MAP_LAST);
+   assert(ARRAY_SIZE(aux_formats) == INTEL_AUX_MAP_LAST);
+   return &aux_formats[format];
+}
+
+static enum intel_aux_map_format
+select_format(const struct intel_device_info *devinfo)
+{
+   if (devinfo->verx10 >= 125)
+      return INTEL_AUX_MAP_GFX125_1MB;
+   else if (devinfo->verx10 == 120)
+      return INTEL_AUX_MAP_GFX12_64KB;
+   else
+      return INTEL_AUX_MAP_LAST;
+}
+
+static bool
+add_buffer(struct intel_aux_map_context *ctx)
+{
+   struct aux_map_buffer *buf = rzalloc(ctx, struct aux_map_buffer);
+   if (!buf)
+      return false;
+
+   const uint32_t size = 0x100000;
+   buf->buffer = ctx->buffer_alloc->alloc(ctx->driver_ctx, size);
+   if (!buf->buffer) {
+      ralloc_free(buf);
+      return false;
+   }
+
+   assert(buf->buffer->map != NULL);
+
+   list_addtail(&buf->link, &ctx->buffers);
+   ctx->tail_offset = 0;
+   ctx->tail_remaining = size;
+   p_atomic_inc(&ctx->num_buffers);
+
+   return true;
+}
+
+static void
+advance_current_pos(struct intel_aux_map_context *ctx, uint32_t size)
+{
+   assert(ctx->tail_remaining >= size);
+   ctx->tail_remaining -= size;
+   ctx->tail_offset += size;
+}
+
+static bool
+align_and_verify_space(struct intel_aux_map_context *ctx, uint32_t size,
+                       uint32_t alignment)
+{
+   if (ctx->tail_remaining < size)
+      return false;
+
+   struct aux_map_buffer *tail =
+      list_last_entry(&ctx->buffers, struct aux_map_buffer, link);
+   uint64_t gpu = tail->buffer->gpu + ctx->tail_offset;
+   uint64_t aligned = align64(gpu, alignment);
+
+   if ((aligned - gpu) + size > ctx->tail_remaining) {
+      return false;
+   } else {
+      if (aligned - gpu > 0)
+         advance_current_pos(ctx, aligned - gpu);
+      return true;
+   }
+}
+
+static void
+get_current_pos(struct intel_aux_map_context *ctx, uint64_t *gpu, uint64_t **map)
+{
+   assert(!list_is_empty(&ctx->buffers));
+   struct aux_map_buffer *tail =
+      list_last_entry(&ctx->buffers, struct aux_map_buffer, link);
+   if (gpu)
+      *gpu = tail->buffer->gpu + ctx->tail_offset;
+   if (map)
+      *map = (uint64_t*)((uint8_t*)tail->buffer->map + ctx->tail_offset);
+}
+
+static struct intel_aux_level *
+add_sub_table(struct intel_aux_map_context *ctx,
+              struct intel_aux_level *parent,
+              uint32_t parent_index,
+              uint32_t size, uint32_t align)
+{
+   if (!align_and_verify_space(ctx, size, align)) {
+      if (!add_buffer(ctx))
+         return NULL;
+      UNUSED bool aligned = align_and_verify_space(ctx, size, align);
+      assert(aligned);
+   }
+
+   struct intel_aux_level *level = rzalloc(ctx, struct intel_aux_level);
+
+   get_current_pos(ctx, &level->address, &level->entries);
+   memset(level->entries, 0, size);
+   advance_current_pos(ctx, size);
+
+   if (parent != NULL) {
+      assert(parent->children[parent_index] == NULL);
+      parent->children[parent_index] = level;
+   }
+
+   return level;
+}
+
+uint32_t
+intel_aux_map_get_state_num(struct intel_aux_map_context *ctx)
+{
+   return p_atomic_read(&ctx->state_num);
+}
+
+struct intel_aux_map_context *
+intel_aux_map_init(void *driver_ctx,
+                   struct intel_mapped_pinned_buffer_alloc *buffer_alloc,
+                   const struct intel_device_info *devinfo)
+{
+   struct intel_aux_map_context *ctx;
+
+   enum intel_aux_map_format format = select_format(devinfo);
+   if (format == INTEL_AUX_MAP_LAST)
+      return NULL;
+
+   ctx = ralloc(NULL, struct intel_aux_map_context);
+   if (!ctx)
+      return NULL;
+
+   if (pthread_mutex_init(&ctx->mutex, NULL))
+      return NULL;
+
+   ctx->format = get_format(format);
+   ctx->driver_ctx = driver_ctx;
+   ctx->buffer_alloc = buffer_alloc;
+   ctx->num_buffers = 0;
+   list_inithead(&ctx->buffers);
+   ctx->tail_offset = 0;
+   ctx->tail_remaining = 0;
+   ctx->state_num = 0;
+
+   ctx->l3_level = add_sub_table(ctx, NULL, 0,
+                                 L3_L2_SUB_TABLE_LEN, L3_L2_SUB_TABLE_LEN);
+   if (ctx->l3_level != NULL) {
+      if (aux_map_debug)
+         fprintf(stderr, "AUX-MAP L3: 0x%"PRIx64", map=%p\n",
+                 ctx->l3_level->address, ctx->l3_level->entries);
+      p_atomic_inc(&ctx->state_num);
+      return ctx;
+   } else {
+      ralloc_free(ctx);
+      return NULL;
+   }
+}
+
+void
+intel_aux_map_finish(struct intel_aux_map_context *ctx)
+{
+   if (!ctx)
+      return;
+
+   pthread_mutex_destroy(&ctx->mutex);
+   list_for_each_entry_safe(struct aux_map_buffer, buf, &ctx->buffers, link) {
+      ctx->buffer_alloc->free(ctx->driver_ctx, buf->buffer);
+      list_del(&buf->link);
+      p_atomic_dec(&ctx->num_buffers);
+      ralloc_free(buf);
+   }
+
+   ralloc_free(ctx);
+}
+
+uint32_t
+intel_aux_map_get_alignment(struct intel_aux_map_context *ctx)
+{
+   return ctx->format->main_page_size;
+}
+
+uint64_t
+intel_aux_map_get_base(struct intel_aux_map_context *ctx)
+{
+   /**
+    * This get initialized in intel_aux_map_init, and never changes, so there is
+    * no need to lock the mutex.
+    */
+   return ctx->l3_level->address;
+}
+
+static uint8_t
+get_bpp_encoding(enum isl_format format)
+{
+   if (isl_format_is_yuv(format)) {
+      switch (format) {
+      case ISL_FORMAT_YCRCB_NORMAL:
+      case ISL_FORMAT_YCRCB_SWAPY:
+      case ISL_FORMAT_PLANAR_420_8: return 3;
+      case ISL_FORMAT_PLANAR_420_12: return 2;
+      case ISL_FORMAT_PLANAR_420_10: return 1;
+      case ISL_FORMAT_PLANAR_420_16: return 0;
+      default:
+         UNREACHABLE("Unsupported format!");
+         return 0;
+      }
+   } else {
+      switch (isl_format_get_layout(format)->bpb) {
+      case 16:  return 0;
+      case 8:   return 4;
+      case 32:  return 5;
+      case 64:  return 6;
+      case 128: return 7;
+      default:
+         UNREACHABLE("Unsupported bpp!");
+         return 0;
+      }
+   }
+}
+
+#define INTEL_AUX_MAP_ENTRY_Ys_TILED_BIT  (0x0ull << 52)
+#define INTEL_AUX_MAP_ENTRY_Y_TILED_BIT   (0x1ull << 52)
+
+uint64_t
+intel_aux_map_format_bits(enum isl_tiling tiling, enum isl_format format,
+                          uint8_t plane)
+{
+   /* gfx12.5+ uses tile-4 rather than y-tiling, and gfx12.5+ also uses
+    * compression info from the surface state and ignores the aux-map format
+    * bits metadata.
+    */
+   if (!isl_tiling_is_any_y(tiling))
+      return 0;
+
+   if (aux_map_debug)
+      fprintf(stderr, "AUX-MAP entry %s, bpp_enc=%d\n",
+              isl_format_get_name(format),
+              isl_format_get_aux_map_encoding(format));
+
+   assert(tiling == ISL_TILING_ICL_Ys ||
+          tiling == ISL_TILING_Y0);
+
+   uint64_t format_bits =
+      ((uint64_t)isl_format_get_aux_map_encoding(format) << 58) |
+      ((uint64_t)(plane > 0) << 57) |
+      ((uint64_t)get_bpp_encoding(format) << 54) |
+      (tiling == ISL_TILING_ICL_Ys ? INTEL_AUX_MAP_ENTRY_Ys_TILED_BIT :
+                                     INTEL_AUX_MAP_ENTRY_Y_TILED_BIT);
+
+   assert((format_bits & INTEL_AUX_MAP_FORMAT_BITS_MASK) == format_bits);
+
+   return format_bits;
+}
+
+uint64_t
+intel_aux_map_format_bits_for_isl_surf(const struct isl_surf *isl_surf)
+{
+   assert(!isl_format_is_planar(isl_surf->format));
+   return intel_aux_map_format_bits(isl_surf->tiling, isl_surf->format, 0);
+}
+
+static uint64_t
+get_l1_addr_mask(struct intel_aux_map_context *ctx)
+{
+   uint64_t l1_addr = ~get_page_mask(ctx->format->l1_page_size);
+   return l1_addr & VALID_ADDRESS_MASK;
+}
+
+static bool
+get_aux_entry(struct intel_aux_map_context *ctx, uint64_t main_address,
+              uint32_t *l1_index_out, uint64_t *l1_entry_addr_out,
+              uint64_t **l1_entry_map_out,
+              struct intel_aux_level **l1_aux_level_out,
+              bool create)
+{
+   struct intel_aux_level *l3_level = ctx->l3_level;
+   struct intel_aux_level *l2_level;
+   struct intel_aux_level *l1_level;
+
+   uint32_t l3_index = (main_address >> 36) & 0xfff;
+
+   if (l3_level->children[l3_index] == NULL) {
+      if (!create)
+         return false;
+      l2_level =
+         add_sub_table(ctx, ctx->l3_level, l3_index,
+                       L3_L2_SUB_TABLE_LEN, L3_L2_SUB_TABLE_LEN);
+      if (l2_level != NULL) {
+         if (aux_map_debug)
+            fprintf(stderr, "AUX-MAP L3[0x%x]: 0x%"PRIx64", map=%p\n",
+                    l3_index, l2_level->address, l2_level->entries);
+      } else {
+         UNREACHABLE("Failed to add L2 Aux-Map Page Table!");
+      }
+      l3_level->entries[l3_index] = (l2_level->address & L3_ENTRY_L2_ADDR_MASK) |
+                                    INTEL_AUX_MAP_ENTRY_VALID_BIT;
+   } else {
+      l2_level = l3_level->children[l3_index];
+   }
+   uint32_t l2_index = (main_address >> 24) & 0xfff;
+   uint64_t l1_page_size = ctx->format->l1_page_size;
+   if (l2_level->children[l2_index] == NULL) {
+      if (!create)
+         return false;
+      l1_level = add_sub_table(ctx, l2_level, l2_index, l1_page_size, l1_page_size);
+      if (l1_level != NULL) {
+         if (aux_map_debug)
+            fprintf(stderr, "AUX-MAP L2[0x%x]: 0x%"PRIx64", map=%p\n",
+                    l2_index, l1_level->address, l1_level->entries);
+      } else {
+         UNREACHABLE("Failed to add L1 Aux-Map Page Table!");
+      }
+      l2_level->entries[l2_index] = (l1_level->address & get_l1_addr_mask(ctx)) |
+                                    INTEL_AUX_MAP_ENTRY_VALID_BIT;
+   } else {
+      l1_level = l2_level->children[l2_index];
+   }
+   uint32_t l1_index = get_index(main_address, ctx->format->l1_index_mask,
+                                 ctx->format->l1_index_offset);
+   if (l1_index_out)
+      *l1_index_out = l1_index;
+   if (l1_entry_addr_out)
+      *l1_entry_addr_out = intel_canonical_address(l1_level->address + l1_index * sizeof(uint64_t));
+   if (l1_entry_map_out)
+      *l1_entry_map_out = &l1_level->entries[l1_index];
+   if (l1_aux_level_out)
+      *l1_aux_level_out = l1_level;
+   return true;
+}
+
+static bool
+add_mapping(struct intel_aux_map_context *ctx, uint64_t main_address,
+            uint64_t aux_address, uint64_t format_bits,
+            bool *state_changed)
+{
+   if (aux_map_debug)
+      fprintf(stderr, "AUX-MAP 0x%"PRIx64" => 0x%"PRIx64"\n", main_address,
+              aux_address);
+
+   uint32_t l1_index;
+   uint64_t *l1_entry;
+   struct intel_aux_level *l1_aux_level;
+   get_aux_entry(ctx, main_address, &l1_index, NULL, &l1_entry,
+                 &l1_aux_level, true);
+
+   const uint64_t l1_data =
+      (aux_address & intel_aux_get_meta_address_mask(ctx)) |
+      format_bits |
+      INTEL_AUX_MAP_ENTRY_VALID_BIT;
+
+   const uint64_t current_l1_data = *l1_entry;
+   if ((current_l1_data & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) {
+      assert(l1_aux_level->ref_counts[l1_index] == 0);
+      assert((aux_address & 0xffULL) == 0);
+      if (aux_map_debug)
+         fprintf(stderr, "AUX-MAP L1[0x%x] 0x%"PRIx64" -> 0x%"PRIx64"\n",
+                 l1_index, current_l1_data, l1_data);
+      /**
+       * We use non-zero bits in 63:1 to indicate the entry had been filled
+       * previously. If these bits are non-zero and they don't exactly match
+       * what we want to program into the entry, then we must force the
+       * aux-map tables to be flushed.
+       */
+      if (current_l1_data != 0 && \
+          (current_l1_data | INTEL_AUX_MAP_ENTRY_VALID_BIT) != l1_data)
+         *state_changed = true;
+      *l1_entry = l1_data;
+   } else {
+      if (aux_map_debug)
+         fprintf(stderr, "AUX-MAP L1[0x%x] is already marked valid!\n",
+                 l1_index);
+
+      if (*l1_entry != l1_data) {
+         if (aux_map_debug)
+            fprintf(stderr,
+                    "AUX-MAP L1[0x%x] overwrite 0x%"PRIx64" != 0x%"PRIx64"\n",
+                    l1_index, current_l1_data, l1_data);
+
+         return false;
+      }
+   }
+
+   l1_aux_level->ref_counts[l1_index]++;
+
+   return true;
+}
+
+uint64_t *
+intel_aux_map_get_entry(struct intel_aux_map_context *ctx,
+                        uint64_t main_address,
+                        uint64_t *aux_entry_address)
+{
+   pthread_mutex_lock(&ctx->mutex);
+   uint64_t *l1_entry_map;
+   get_aux_entry(ctx, main_address, NULL, aux_entry_address, &l1_entry_map,
+                 NULL, true);
+   pthread_mutex_unlock(&ctx->mutex);
+
+   return l1_entry_map;
+}
+
+/**
+ * We mark the leaf entry as invalid, but we don't attempt to cleanup the
+ * other levels of translation mappings. Since we attempt to re-use VMA
+ * ranges, hopefully this will not lead to unbounded growth of the translation
+ * tables.
+ */
+static void
+remove_l1_mapping_locked(struct intel_aux_map_context *ctx, uint64_t main_address,
+                         bool reset_refcount, bool *state_changed)
+{
+   uint32_t l1_index;
+   uint64_t *l1_entry;
+   struct intel_aux_level *l1_aux_level;
+   if (!get_aux_entry(ctx, main_address, &l1_index, NULL, &l1_entry,
+                 &l1_aux_level, false))
+      return;
+
+   const uint64_t current_l1_data = *l1_entry;
+   const uint64_t l1_data = current_l1_data & ~INTEL_AUX_MAP_ENTRY_VALID_BIT;
+
+   if ((current_l1_data & INTEL_AUX_MAP_ENTRY_VALID_BIT) == 0) {
+      assert(l1_aux_level->ref_counts[l1_index] == 0);
+      return;
+   } else if (reset_refcount) {
+      l1_aux_level->ref_counts[l1_index] = 0;
+      if (unlikely(l1_data == 0))
+         *state_changed = true;
+      *l1_entry = l1_data;
+   } else {
+      assert(l1_aux_level->ref_counts[l1_index] > 0);
+      if (--l1_aux_level->ref_counts[l1_index] == 0) {
+         /**
+          * We use non-zero bits in 63:1 to indicate the entry had been filled
+          * previously. In the unlikely event that these are all zero, we
+          * force a flush of the aux-map tables.
+          */
+         if (unlikely(l1_data == 0))
+            *state_changed = true;
+         *l1_entry = l1_data;
+      }
+   }
+}
+
+static void
+remove_mapping_locked(struct intel_aux_map_context *ctx, uint64_t main_address,
+                      uint64_t size, bool reset_refcount, bool *state_changed)
+{
+   if (aux_map_debug)
+      fprintf(stderr, "AUX-MAP remove 0x%"PRIx64"-0x%"PRIx64"\n", main_address,
+              main_address + size);
+
+   uint64_t main_inc_addr = main_address;
+   uint64_t main_page_size = ctx->format->main_page_size;
+   assert((main_address & get_page_mask(main_page_size)) == 0);
+   while (main_inc_addr - main_address < size) {
+      remove_l1_mapping_locked(ctx, main_inc_addr, reset_refcount,
+                               state_changed);
+      main_inc_addr += main_page_size;
+   }
+}
+
+bool
+intel_aux_map_add_mapping(struct intel_aux_map_context *ctx, uint64_t main_address,
+                          uint64_t aux_address, uint64_t main_size_B,
+                          uint64_t format_bits)
+{
+   bool state_changed = false;
+   pthread_mutex_lock(&ctx->mutex);
+   uint64_t main_inc_addr = main_address;
+   uint64_t aux_inc_addr = aux_address;
+   const uint64_t main_page_size = ctx->format->main_page_size;
+   assert((main_address & get_page_mask(main_page_size)) == 0);
+   const uint64_t aux_page_size = get_meta_page_size(ctx->format);
+   assert((aux_address & get_page_mask(aux_page_size)) == 0);
+   while (main_inc_addr - main_address < main_size_B) {
+      if (!add_mapping(ctx, main_inc_addr, aux_inc_addr, format_bits,
+                       &state_changed)) {
+         break;
+      }
+      main_inc_addr = main_inc_addr + main_page_size;
+      aux_inc_addr = aux_inc_addr + aux_page_size;
+   }
+   bool success = main_inc_addr - main_address >= main_size_B;
+   if (!success && (main_inc_addr > main_address)) {
+      /* If the mapping failed, remove the mapped portion. */
+      remove_mapping_locked(ctx, main_address,
+                            main_inc_addr - main_address,
+                            false /* reset_refcount */, &state_changed);
+   }
+   pthread_mutex_unlock(&ctx->mutex);
+   if (state_changed)
+      p_atomic_inc(&ctx->state_num);
+
+
+   return success;
+}
+
+void
+intel_aux_map_del_mapping(struct intel_aux_map_context *ctx, uint64_t main_address,
+                          uint64_t size)
+{
+   bool state_changed = false;
+   pthread_mutex_lock(&ctx->mutex);
+   remove_mapping_locked(ctx, main_address, size, false /* reset_refcount */,
+                         &state_changed);
+   pthread_mutex_unlock(&ctx->mutex);
+   if (state_changed)
+      p_atomic_inc(&ctx->state_num);
+}
+
+void
+intel_aux_map_unmap_range(struct intel_aux_map_context *ctx, uint64_t main_address,
+                          uint64_t size)
+{
+   bool state_changed = false;
+   pthread_mutex_lock(&ctx->mutex);
+   remove_mapping_locked(ctx, main_address, size, true /* reset_refcount */,
+                         &state_changed);
+   pthread_mutex_unlock(&ctx->mutex);
+   if (state_changed)
+      p_atomic_inc(&ctx->state_num);
+}
+
+uint32_t
+intel_aux_map_get_num_buffers(struct intel_aux_map_context *ctx)
+{
+   return p_atomic_read(&ctx->num_buffers);
+}
+
+void
+intel_aux_map_fill_bos(struct intel_aux_map_context *ctx, void **driver_bos,
+                       uint32_t max_bos)
+{
+   assert(p_atomic_read(&ctx->num_buffers) >= max_bos);
+   uint32_t i = 0;
+   list_for_each_entry(struct aux_map_buffer, buf, &ctx->buffers, link) {
+      if (i >= max_bos)
+         return;
+      driver_bos[i++] = buf->buffer->driver_bo;
+   }
+}

src/intel/common/intel_aux_map.h

@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef INTEL_AUX_MAP_H
+#define INTEL_AUX_MAP_H
+
+#include "intel_buffer_alloc.h"
+
+#include "isl/isl.h"
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Auxiliary surface mapping implementation
+ *
+ * These functions are implemented in common code shared by drivers.
+ */
+
+struct intel_aux_map_context;
+struct intel_device_info;
+
+#define INTEL_AUX_MAP_ENTRY_VALID_BIT    0x1ull
+
+/**
+ * The ratio between the granularity of main surface pitch and AUX data pitch
+ * (when viewed as a surface).
+ *
+ * In agreement with Bspec 44930, the kernel expects that every 512B of the
+ * main surface pitch maps to 64B of the AUX data pitch. This is not
+ * documented in drm_fourcc.h.
+ */
+#define INTEL_AUX_MAP_MAIN_PITCH_SCALEDOWN (512 / 64)
+
+/**
+ * The ratio between the granularity of main surface and AUX data.
+ *
+ * The value is from Bspec 47709, MCS/CCS Buffers for Render Target(s):
+ *
+ *    "CCS is a linear buffer created for storing meta-data (AUX data) for
+ *    lossless compression. This buffer related information is mentioned in
+ *    Render Surface State. CCS buffer's size is based on the padded main
+ *    surface (after following Halign and Valign requirements mentioned in the
+ *    Render Surface State). CCS_Buffer_Size = Padded_Main_Surface_Size/256"
+ *
+ * The aux-map only exists on Xe, so this is equivalent to
+ * ISL_MAIN_TO_CCS_SIZE_RATIO_XE.
+ */
+#define INTEL_AUX_MAP_MAIN_SIZE_SCALEDOWN 256
+
+/**
+ * The alignment at which the AUX data virtual addresses should start.
+ *
+ * The diagram in Bspec 44930 shows that the CCS is indexed in 256B chunks for
+ * TGL, 4K chunks for MTL. However, when modifiers are in use, the 4K
+ * alignment requirement of the PLANE_AUX_DIST::Auxiliary Surface Distance
+ * field must be considered (Bspec 50379). Keep things simple and just use 4K.
+ */
+#define INTEL_AUX_MAP_META_ALIGNMENT_B 4096
+
+struct intel_aux_map_context *
+intel_aux_map_init(void *driver_ctx,
+                   struct intel_mapped_pinned_buffer_alloc *buffer_alloc,
+                   const struct intel_device_info *devinfo);
+
+uint32_t
+intel_aux_map_get_alignment(struct intel_aux_map_context *ctx);
+
+void
+intel_aux_map_finish(struct intel_aux_map_context *ctx);
+
+uint32_t
+intel_aux_map_get_state_num(struct intel_aux_map_context *ctx);
+
+/**
+ * Returns the current number of buffers used by the aux-map tables
+ *
+ * When preparing to execute a new batch, use this function to determine how
+ * many buffers will be required. More buffers may be added by concurrent
+ * accesses of the aux-map functions, but they won't be required for since
+ * they involve surfaces not used by this batch.
+ */
+uint32_t
+intel_aux_map_get_num_buffers(struct intel_aux_map_context *ctx);
+
+/**
+ * Returns the mask of meta data address in L1 entry
+ *
+ * The mask value is effected by page size of meta data specific to a platform.
+ */
+uint64_t
+intel_aux_get_meta_address_mask(struct intel_aux_map_context *ctx);
+
+/**
+ * Takes a relative offset in the main surface and returns a relative offset
+ * in the aux surface that maps to the main offset.
+ */
+uint64_t
+intel_aux_main_to_aux_offset(struct intel_aux_map_context *ctx,
+                             uint64_t main_offset);
+
+/**
+ * Fill an array of exec_object2 with aux-map buffer handles
+ *
+ * The intel_aux_map_get_num_buffers call should be made, then the driver can
+ * make sure the `obj` array is large enough before calling this function.
+ */
+void
+intel_aux_map_fill_bos(struct intel_aux_map_context *ctx, void **driver_bos,
+                       uint32_t max_bos);
+
+uint64_t
+intel_aux_map_get_base(struct intel_aux_map_context *ctx);
+
+uint64_t
+intel_aux_map_format_bits(enum isl_tiling tiling, enum isl_format format,
+                          uint8_t plane);
+
+uint64_t
+intel_aux_map_format_bits_for_isl_surf(const struct isl_surf *isl_surf);
+
+uint64_t *
+intel_aux_map_get_entry(struct intel_aux_map_context *ctx,
+                        uint64_t main_address,
+                        uint64_t *aux_entry_address);
+
+/* Fails if a mapping is attempted that would conflict with an existing one.
+ * This increase the refcount of the mapped region if already mapped, sets it
+ * to 1 otherwise.
+ */
+bool
+intel_aux_map_add_mapping(struct intel_aux_map_context *ctx, uint64_t main_address,
+                          uint64_t aux_address, uint64_t main_size_B,
+                          uint64_t format_bits);
+
+/* Decrease the refcount of a mapped region. When the refcount reaches 0, the
+ * region is unmapped.
+ */
+void
+intel_aux_map_del_mapping(struct intel_aux_map_context *ctx, uint64_t main_address,
+                          uint64_t size);
+
+/* Unmaps a region, refcount is reset to 0.
+ */
+void
+intel_aux_map_unmap_range(struct intel_aux_map_context *ctx, uint64_t main_address,
+                          uint64_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* INTEL_AUX_MAP_H */

src/intel/common/intel_bind_timeline.c

@@ -0,0 +1,79 @@
+/*
+ * Copyright 2023 Intel Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "intel_bind_timeline.h"
+
+#include "drm-uapi/drm.h"
+#include "intel_gem.h"
+
+bool intel_bind_timeline_init(struct intel_bind_timeline *bind_timeline, int fd)
+{
+   struct drm_syncobj_create syncobj_create = { .flags = DRM_SYNCOBJ_CREATE_SIGNALED };
+
+   if (intel_ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create))
+      return false;
+
+   simple_mtx_init(&bind_timeline->mutex, mtx_plain);
+   bind_timeline->syncobj = syncobj_create.handle;
+   bind_timeline->point = 0;
+
+   return true;
+}
+
+void intel_bind_timeline_finish(struct intel_bind_timeline *bind_timeline, int fd)
+{
+   if (bind_timeline->syncobj == 0)
+      return;
+
+   uint64_t point = intel_bind_timeline_get_last_point(bind_timeline);
+   struct drm_syncobj_timeline_wait syncobj_wait = {
+      .timeout_nsec = INT64_MAX,
+      .handles = (uintptr_t)&bind_timeline->syncobj,
+      .count_handles = 1,
+      .points = (uintptr_t)&point,
+   };
+   struct drm_syncobj_destroy syncobj_destroy = {
+      .handle = bind_timeline->syncobj,
+   };
+
+   /* Makes sure last unbind was signaled otherwise it can trigger job
+    * timeouts in KMD
+    */
+   intel_ioctl(fd, DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT, &syncobj_wait);
+   intel_ioctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, &syncobj_destroy);
+
+   simple_mtx_destroy(&bind_timeline->mutex);
+}
+
+uint32_t intel_bind_timeline_get_syncobj(struct intel_bind_timeline *bind_timeline)
+{
+   return bind_timeline->syncobj;
+}
+
+uint64_t intel_bind_timeline_bind_begin(struct intel_bind_timeline *bind_timeline)
+{
+   simple_mtx_lock(&bind_timeline->mutex);
+   return ++bind_timeline->point;
+}
+
+void intel_bind_timeline_bind_end(struct intel_bind_timeline *bind_timeline)
+{
+   simple_mtx_unlock(&bind_timeline->mutex);
+}
+
+/*
+ * Returns the timeline point that should be waited on before execute any
+ * batch buffers.
+ */
+uint64_t intel_bind_timeline_get_last_point(struct intel_bind_timeline *bind_timeline)
+{
+   uint64_t ret;
+
+   simple_mtx_lock(&bind_timeline->mutex);
+   ret = bind_timeline->point;
+   simple_mtx_unlock(&bind_timeline->mutex);
+
+   return ret;
+}