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/*
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* Copyright © 2012 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#include "brw_shader.h"
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#include "brw_analysis.h"
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#define MAX_INSTRUCTION (1 << 30)
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/** @file
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*
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* Support for calculating liveness information about virtual GRFs.
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*
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* This produces a live interval for each whole virtual GRF. We could
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* choose to expose per-component live intervals for VGRFs of size > 1,
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* but we currently do not. It is easier for the consumers of this
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* information to work with whole VGRFs.
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*
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* However, we internally track use/def information at the per-GRF level for
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* greater accuracy. Large VGRFs may be accessed piecemeal over many
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* (possibly non-adjacent) instructions. In this case, examining a single
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* instruction is insufficient to decide whether a whole VGRF is ultimately
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* used or defined. Tracking individual components allows us to easily
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* assemble this information.
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*
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* See Muchnick's Advanced Compiler Design and Implementation, section
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* 14.1 (p444).
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*/
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void
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brw_live_variables::setup_one_read(struct block_data *bd,
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int ip, int var)
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{
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assert(var < num_vars);
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vars_range[var] = merge(vars_range[var], ip);
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/* The use[] bitset marks when the block makes use of a variable (VGRF
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* channel) without having completely defined that variable within the
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* block.
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*/
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if (!BITSET_TEST(bd->def, var))
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BITSET_SET(bd->use, var);
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}
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void
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brw_live_variables::setup_one_write(struct block_data *bd, brw_inst *inst,
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int ip, int var)
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{
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assert(var < num_vars);
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vars_range[var] = merge(vars_range[var], ip);
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/* The def[] bitset marks when an initialization in a block completely
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* screens off previous updates of that variable (VGRF channel).
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*/
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if (!inst->is_partial_write() && !BITSET_TEST(bd->use, var))
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BITSET_SET(bd->def, var);
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BITSET_SET(bd->defout, var);
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}
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/**
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* Sets up the use[] and def[] bitsets.
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*
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* The basic-block-level live variable analysis needs to know which
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* variables get used before they're completely defined, and which
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* variables are completely defined before they're used.
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*
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* These are tracked at the per-component level, rather than whole VGRFs.
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*/
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void
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brw_live_variables::setup_def_use()
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{
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int ip = 0;
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foreach_block (block, cfg) {
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struct block_data *bd = &block_data[block->num];
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assert(ip == bd->ip_range.start);
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if (block->num > 0)
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assert(block_data[block->num - 1].ip_range.end == ip);
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foreach_inst_in_block(brw_inst, inst, block) {
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/* Set use[] for this instruction */
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for (unsigned int i = 0; i < inst->sources; i++) {
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if (inst->src[i].file != VGRF)
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continue;
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const int var = var_from_reg(inst->src[i]);
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const unsigned read = regs_read(devinfo, inst, i);
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for (unsigned j = 0; j < read; j++)
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setup_one_read(bd, ip, var + j);
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}
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bd->flag_use[0] |= inst->flags_read(devinfo) & ~bd->flag_def[0];
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/* Set def[] for this instruction */
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if (inst->dst.file == VGRF) {
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const int var = var_from_reg(inst->dst);
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const unsigned written = regs_written(inst);
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for (unsigned j = 0; j < written; j++)
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setup_one_write(bd, inst, ip, var + j);
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}
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if (!inst->predicate && inst->exec_size >= 8)
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bd->flag_def[0] |= inst->flags_written(devinfo) & ~bd->flag_use[0];
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ip++;
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}
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}
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}
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/**
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* The algorithm incrementally sets bits in liveout and livein,
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* propagating it through control flow. It will eventually terminate
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* because it only ever adds bits, and stops when no bits are added in
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* a pass.
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*/
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void
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brw_live_variables::compute_live_variables()
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{
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bool cont = true;
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/* Propagate defin and defout down the CFG to calculate the union of live
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* variables potentially defined along any possible control flow path.
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*/
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do {
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cont = false;
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foreach_block (block, cfg) {
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const struct block_data *bd = &block_data[block->num];
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brw_foreach_list_typed(bblock_link, child_link, link, &block->children) {
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struct block_data *child_bd = &block_data[child_link->block->num];
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for (int i = 0; i < bitset_words; i++) {
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const BITSET_WORD new_def = bd->defout[i] & ~child_bd->defin[i];
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child_bd->defin[i] |= new_def;
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child_bd->defout[i] |= new_def;
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cont |= new_def;
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}
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}
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}
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} while (cont);
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do {
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cont = false;
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foreach_block_reverse (block, cfg) {
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struct block_data *bd = &block_data[block->num];
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/* Update liveout */
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brw_foreach_list_typed(bblock_link, child_link, link, &block->children) {
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struct block_data *child_bd = &block_data[child_link->block->num];
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_liveout = (child_bd->livein[i] &
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~bd->liveout[i]);
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new_liveout &= bd->defout[i]; /* Screen off uses with no reaching def */
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if (new_liveout)
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bd->liveout[i] |= new_liveout;
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}
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BITSET_WORD new_liveout = (child_bd->flag_livein[0] &
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~bd->flag_liveout[0]);
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if (new_liveout)
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bd->flag_liveout[0] |= new_liveout;
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}
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/* Update livein */
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for (int i = 0; i < bitset_words; i++) {
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BITSET_WORD new_livein = (bd->use[i] |
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(bd->liveout[i] &
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~bd->def[i]));
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new_livein &= bd->defin[i]; /* Screen off uses with no reaching def */
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if (new_livein & ~bd->livein[i]) {
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bd->livein[i] |= new_livein;
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cont = true;
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}
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}
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BITSET_WORD new_livein = (bd->flag_use[0] |
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(bd->flag_liveout[0] &
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~bd->flag_def[0]));
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if (new_livein & ~bd->flag_livein[0]) {
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bd->flag_livein[0] |= new_livein;
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cont = true;
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}
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}
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} while (cont);
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}
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/**
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* Extend the start/end ranges for each variable to account for the
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* new information calculated from control flow.
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*/
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void
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brw_live_variables::compute_start_end()
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{
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foreach_block (block, cfg) {
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struct block_data *bd = &block_data[block->num];
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unsigned i;
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BITSET_FOREACH_SET(i, bd->livein, (unsigned)num_vars)
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vars_range[i] = merge(vars_range[i], bd->ip_range.start);
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BITSET_FOREACH_SET(i, bd->liveout, (unsigned)num_vars)
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vars_range[i] = merge(vars_range[i], bd->ip_range.last());
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}
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}
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brw_live_variables::brw_live_variables(const brw_shader *s)
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: devinfo(s->devinfo), cfg(s->cfg)
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{
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mem_ctx = ralloc_context(NULL);
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linear_ctx *lin_ctx = linear_context(mem_ctx);
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num_vgrfs = s->alloc.count;
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num_vars = 0;
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max_vgrf_size = 0;
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var_from_vgrf = linear_alloc_array(lin_ctx, int, num_vgrfs);
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for (int i = 0; i < num_vgrfs; i++) {
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var_from_vgrf[i] = num_vars;
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num_vars += s->alloc.sizes[i];
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max_vgrf_size = MAX2(max_vgrf_size, s->alloc.sizes[i]);
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}
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vgrf_from_var = linear_alloc_array(lin_ctx, int, num_vars);
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for (int i = 0; i < num_vgrfs; i++) {
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for (unsigned j = 0; j < s->alloc.sizes[i]; j++) {
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vgrf_from_var[var_from_vgrf[i] + j] = i;
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}
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}
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vars_range = linear_zalloc_array(lin_ctx, brw_range, num_vars);
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vgrf_range = linear_zalloc_array(lin_ctx, brw_range, num_vgrfs);
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block_data = linear_alloc_array(lin_ctx, struct block_data, cfg->num_blocks);
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bitset_words = BITSET_WORDS(num_vars);
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for (int i = 0; i < cfg->num_blocks; i++) {
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block_data[i].def = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
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block_data[i].use = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
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block_data[i].livein = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
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block_data[i].liveout = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
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block_data[i].defin = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
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block_data[i].defout = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
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block_data[i].flag_def[0] = 0;
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block_data[i].flag_use[0] = 0;
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block_data[i].flag_livein[0] = 0;
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block_data[i].flag_liveout[0] = 0;
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}
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const brw_ip_ranges &ips = s->ip_ranges_analysis.require();
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for (int i = 0; i < cfg->num_blocks; i++)
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block_data[i].ip_range = ips.range(cfg->blocks[i]);
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setup_def_use();
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compute_live_variables();
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compute_start_end();
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/* Merge the per-component live ranges to whole VGRF live ranges. */
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for (int i = 0; i < num_vars; i++) {
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const unsigned vgrf = vgrf_from_var[i];
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vgrf_range[vgrf] = merge(vgrf_range[vgrf], vars_range[i]);
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}
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}
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brw_live_variables::~brw_live_variables()
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{
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ralloc_free(mem_ctx);
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}
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static bool
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check_register_live_range(const brw_live_variables *live, int ip,
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const brw_reg ®, unsigned n)
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{
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const unsigned var = live->var_from_reg(reg);
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if (var + n > unsigned(live->num_vars) ||
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!live->vgrf_range[reg.nr].contains(ip))
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return false;
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for (unsigned j = 0; j < n; j++) {
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if (!live->vars_range[var + j].contains(ip))
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return false;
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}
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return true;
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}
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bool
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brw_live_variables::validate(const brw_shader *s) const
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{
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int ip = 0;
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foreach_block_and_inst(block, brw_inst, inst, s->cfg) {
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for (unsigned i = 0; i < inst->sources; i++) {
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if (inst->src[i].file == VGRF &&
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!check_register_live_range(this, ip,
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inst->src[i], regs_read(devinfo, inst, i)))
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return false;
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}
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if (inst->dst.file == VGRF &&
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!check_register_live_range(this, ip, inst->dst, regs_written(inst)))
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return false;
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ip++;
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}
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return true;
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}
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bool
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brw_live_variables::vars_interfere(int a, int b) const
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{
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/* Clip the ranges so the end of a live range can overlap with
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* the start of another live range. See details in vgrfs_interfere().
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*/
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return overlaps(clip_end(vars_range[a], 1),
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clip_end(vars_range[b], 1));
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}
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bool
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brw_live_variables::vgrfs_interfere(int a, int b) const
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{
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/* The live ranges are constructed such that at the start
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* of the range there's a WRITE to the VGRF and at the
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* end of the range there's a READ of the VGRF.
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*
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* Two VGRFs will not interfere if the same IP has both
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* the READ at the end for one and the WRITE at the start
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* for the other.
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*
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* Clip the ranges to cover this edge case.
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*/
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return overlaps(clip_end(vgrf_range[a], 1),
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clip_end(vgrf_range[b], 1));
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}
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