mirror of
https://github.com/elwrcl/intel-hard-graphics.git
synced 2026-11-01 03:18:02 +03:00
init
This commit is contained in:
12511 files changed
+6156641
No files matched your search
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,144 @@
|
||||
/*
|
||||
* Copyright 2026 Intel Corporation
|
||||
* SPDX-License-Identifier: MIT
|
||||
*/
|
||||
|
||||
#include "libintel_shaders.h"
|
||||
|
||||
#define CMD(cmd_type, cmd_subtype, _opcode, _subopcode) \
|
||||
(((cmd_type) << 29) | \
|
||||
((cmd_subtype) << 27) | \
|
||||
((_opcode) << 24) | \
|
||||
((_subopcode) << 16))
|
||||
#define CMD5(cmd_type, cmd_subtype, _opcode, _subopcode, _variant) \
|
||||
(((cmd_type) << 29) | \
|
||||
((cmd_subtype) << 27) | \
|
||||
((_opcode) << 24) | \
|
||||
((_subopcode) << 18) | \
|
||||
((_variant) << 16))
|
||||
|
||||
void
|
||||
genX(libanv_dgc_dump)(global uint32_t *cmd_base,
|
||||
uint32_t n_dwords,
|
||||
global void *call_addr)
|
||||
{
|
||||
printf("call from 0x%016lx\n", call_addr);
|
||||
uint32_t bbs_count = 0;
|
||||
for (uint32_t i = 0; i < n_dwords && bbs_count < 2; ) {
|
||||
uint32_t n_dwords = cmd_base[i] & 0xff;
|
||||
uint32_t bias_dwords = 0;
|
||||
printf("0x%016lx: ", cmd_base + i);
|
||||
switch (cmd_base[i] & 0xffff0000) {
|
||||
case CMD(3, 3, 3, 0):
|
||||
printf("3DPRIMITIVE\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 3, 2):
|
||||
printf("3DMESH_3D\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 21):
|
||||
printf("3DSTATE_CONSTANT_VS\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 25):
|
||||
printf("3DSTATE_CONSTANT_HS\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 26):
|
||||
printf("3DSTATE_CONSTANT_DS\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 22):
|
||||
printf("3DSTATE_CONSTANT_GS\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 23):
|
||||
printf("3DSTATE_CONSTANT_PS\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 109):
|
||||
printf("3DSTATE_CONSTANT_ALL\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 123):
|
||||
printf("3DSTATE_MESH_SHADER_DATA\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 126):
|
||||
printf("3DSTATE_TASK_SHADER_DATA\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 10):
|
||||
printf("3DSTATE_INDEX_BUFFER\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 8):
|
||||
printf("3DSTATE_VERTEX_BUFFERS\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 27):
|
||||
printf("3DSTATE_HS\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 3, 0, 29):
|
||||
printf("3DSTATE_DS\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 2, 0, 4):
|
||||
printf("MEDIA_STATE_FLUSH\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 2, 0, 0):
|
||||
printf("MEDIA_VFE_STATE\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 2, 0, 1):
|
||||
printf("MEDIA_CURBE_LOAD\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 2, 0, 2):
|
||||
printf("MEDIA_INTERFACE_DESCRIPTOR_LOAD\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD(3, 2, 1, 5):
|
||||
printf("GPGPU_WALKER\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case CMD5(3, 2, 2, 2, 0):
|
||||
printf("COMPUTE_WALKER\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case 0x10000000:
|
||||
printf("MI_STORE_DATA_IMM\n");
|
||||
bias_dwords = 2;
|
||||
break;
|
||||
case 0x02800000:
|
||||
printf("MI_ARB_CHECK\n");
|
||||
bias_dwords = 1;
|
||||
break;
|
||||
case 0x18800000:
|
||||
printf("MI_BATCH_BUFFER_START\n");
|
||||
bias_dwords = 2;
|
||||
bbs_count++;
|
||||
break;
|
||||
case 0x00000000:
|
||||
printf("MI_NOOP\n");
|
||||
bias_dwords = 1;
|
||||
break;
|
||||
default:
|
||||
printf("unknown : 0x%08x\n", cmd_base[i]);
|
||||
return;
|
||||
}
|
||||
|
||||
printf(" ");
|
||||
for (uint32_t j = 0; j < (bias_dwords + n_dwords); j++) {
|
||||
if (j > 0 && (j % 8) == 0)
|
||||
printf("\n ");
|
||||
printf("0x%08x ", cmd_base[i + j]);
|
||||
}
|
||||
printf("\n");
|
||||
|
||||
i += bias_dwords + n_dwords;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,270 @@
|
||||
/* Copyright © 2023 Intel Corporation
|
||||
* SPDX-License-Identifier: MIT
|
||||
*/
|
||||
|
||||
#include "libintel_shaders.h"
|
||||
|
||||
void genX(write_address)(global void *dst_ptr, global void *address, uint64_t value)
|
||||
{
|
||||
struct GENX(MI_STORE_DATA_IMM) v = {
|
||||
GENX(MI_STORE_DATA_IMM_header),
|
||||
.DWordLength = GENX(MI_STORE_DATA_IMM_length) -
|
||||
GENX(MI_STORE_DATA_IMM_length_bias) + 1,
|
||||
#if GFX_VER >= 12
|
||||
.ForceWriteCompletionCheck = true,
|
||||
#endif
|
||||
.Address = (uint64_t)address,
|
||||
.ImmediateData = value,
|
||||
};
|
||||
GENX(MI_STORE_DATA_IMM_pack)(dst_ptr, &v);
|
||||
}
|
||||
|
||||
void genX(write_3DSTATE_VF_TOPOLOGY)(global void *dst_ptr,
|
||||
uint32_t topology)
|
||||
{
|
||||
struct GENX(3DSTATE_VF_TOPOLOGY) v = {
|
||||
GENX(3DSTATE_VF_TOPOLOGY_header),
|
||||
.PrimitiveTopologyType = topology,
|
||||
};
|
||||
GENX(3DSTATE_VF_TOPOLOGY_pack)(dst_ptr, &v);
|
||||
}
|
||||
|
||||
void genX(write_3DSTATE_VERTEX_BUFFERS)(global void *dst_ptr,
|
||||
uint32_t buffer_count)
|
||||
{
|
||||
struct GENX(3DSTATE_VERTEX_BUFFERS) v = {
|
||||
GENX(3DSTATE_VERTEX_BUFFERS_header),
|
||||
.DWordLength = 1 + (buffer_count * 4) -
|
||||
GENX(3DSTATE_VERTEX_BUFFERS_length_bias),
|
||||
};
|
||||
GENX(3DSTATE_VERTEX_BUFFERS_pack)(dst_ptr, &v);
|
||||
}
|
||||
|
||||
void genX(write_VERTEX_BUFFER_STATE)(global void *dst_ptr,
|
||||
uint32_t mocs,
|
||||
uint32_t buffer_idx,
|
||||
uint64_t address,
|
||||
uint32_t size,
|
||||
uint32_t stride)
|
||||
{
|
||||
bool buffer_null = address == 0;
|
||||
struct GENX(VERTEX_BUFFER_STATE) v = {
|
||||
.BufferPitch = stride,
|
||||
.NullVertexBuffer = address == 0,
|
||||
.AddressModifyEnable = true,
|
||||
.MOCS = mocs,
|
||||
#if GFX_VER >= 12
|
||||
.L3BypassDisable = true,
|
||||
#endif
|
||||
.VertexBufferIndex = buffer_idx,
|
||||
.BufferStartingAddress = address,
|
||||
.BufferSize = size,
|
||||
};
|
||||
GENX(VERTEX_BUFFER_STATE_pack)(dst_ptr, &v);
|
||||
}
|
||||
|
||||
void genX(write_3DSTATE_INDEX_BUFFER)(global void *dst_ptr,
|
||||
uint64_t buffer_addr,
|
||||
uint32_t buffer_size,
|
||||
uint32_t index_format,
|
||||
uint32_t mocs)
|
||||
{
|
||||
struct GENX(3DSTATE_INDEX_BUFFER) v = {
|
||||
GENX(3DSTATE_INDEX_BUFFER_header),
|
||||
.MOCS = mocs,
|
||||
.IndexFormat = index_format,
|
||||
#if GFX_VER >= 12
|
||||
.L3BypassDisable = true,
|
||||
#endif
|
||||
.BufferStartingAddress = buffer_addr,
|
||||
.BufferSize = buffer_size,
|
||||
};
|
||||
GENX(3DSTATE_INDEX_BUFFER_pack)(dst_ptr, &v);
|
||||
}
|
||||
|
||||
void genX(write_3DPRIMITIVE)(global void *dst_ptr,
|
||||
bool is_predicated,
|
||||
bool is_indexed,
|
||||
bool uses_tbimr,
|
||||
uint32_t vertex_count_per_instance,
|
||||
uint32_t start_vertex_location,
|
||||
uint32_t instance_count,
|
||||
uint32_t start_instance_location,
|
||||
uint32_t base_vertex_location)
|
||||
{
|
||||
struct GENX(3DPRIMITIVE) v = {
|
||||
GENX(3DPRIMITIVE_header),
|
||||
#if GFX_VERx10 >= 125
|
||||
.TBIMREnable = uses_tbimr,
|
||||
#endif
|
||||
.PredicateEnable = is_predicated,
|
||||
.VertexAccessType = is_indexed ? RANDOM : SEQUENTIAL,
|
||||
.VertexCountPerInstance = vertex_count_per_instance,
|
||||
.StartVertexLocation = start_vertex_location,
|
||||
.InstanceCount = instance_count,
|
||||
.StartInstanceLocation = start_instance_location,
|
||||
.BaseVertexLocation = base_vertex_location,
|
||||
};
|
||||
GENX(3DPRIMITIVE_pack)(dst_ptr, &v);
|
||||
}
|
||||
|
||||
#if GFX_VER >= 11
|
||||
void genX(write_3DPRIMITIVE_EXTENDED)(global void *dst_ptr,
|
||||
bool is_predicated,
|
||||
bool is_indexed,
|
||||
bool uses_tbimr,
|
||||
uint32_t vertex_count_per_instance,
|
||||
uint32_t start_vertex_location,
|
||||
uint32_t instance_count,
|
||||
uint32_t start_instance_location,
|
||||
uint32_t base_vertex_location,
|
||||
uint32_t param_base_vertex,
|
||||
uint32_t param_base_instance,
|
||||
uint32_t param_draw_id)
|
||||
{
|
||||
struct GENX(3DPRIMITIVE_EXTENDED) v = {
|
||||
GENX(3DPRIMITIVE_EXTENDED_header),
|
||||
#if GFX_VERx10 >= 125
|
||||
.TBIMREnable = uses_tbimr,
|
||||
#endif
|
||||
.PredicateEnable = is_predicated,
|
||||
.VertexAccessType = is_indexed ? RANDOM : SEQUENTIAL,
|
||||
.VertexCountPerInstance = vertex_count_per_instance,
|
||||
.StartVertexLocation = start_vertex_location,
|
||||
.InstanceCount = instance_count,
|
||||
.StartInstanceLocation = start_instance_location,
|
||||
.BaseVertexLocation = base_vertex_location,
|
||||
.ExtendedParameter0 = param_base_vertex,
|
||||
.ExtendedParameter1 = param_base_instance,
|
||||
.ExtendedParameter2 = param_draw_id,
|
||||
};
|
||||
GENX(3DPRIMITIVE_EXTENDED_pack)(dst_ptr, &v);
|
||||
}
|
||||
#endif
|
||||
|
||||
void genX(write_MI_BATCH_BUFFER_START)(global void *dst_ptr, uint64_t addr)
|
||||
{
|
||||
struct GENX(MI_BATCH_BUFFER_START) v = {
|
||||
GENX(MI_BATCH_BUFFER_START_header),
|
||||
.AddressSpaceIndicator = ASI_PPGTT,
|
||||
.BatchBufferStartAddress = addr,
|
||||
};
|
||||
GENX(MI_BATCH_BUFFER_START_pack)(dst_ptr, &v);
|
||||
}
|
||||
|
||||
void genX(write_draw)(global uint32_t *dst_ptr,
|
||||
global void *indirect_ptr,
|
||||
global uint32_t *draw_id_ptr,
|
||||
uint32_t draw_id,
|
||||
uint32_t instance_multiplier,
|
||||
bool is_indexed,
|
||||
bool is_predicated,
|
||||
bool uses_tbimr,
|
||||
bool uses_base,
|
||||
bool uses_drawid,
|
||||
uint32_t mocs)
|
||||
{
|
||||
#if GFX_VER <= 9
|
||||
if (uses_base || uses_drawid) {
|
||||
uint32_t vertex_buffer_count =
|
||||
(uses_base ? 1 : 0) + (uses_drawid ? 1 : 0);
|
||||
genX(write_3DSTATE_VERTEX_BUFFERS)(dst_ptr, vertex_buffer_count);
|
||||
dst_ptr += 1; /* GENX(3DSTATE_VERTEX_BUFFERS_length); */
|
||||
if (uses_base) {
|
||||
uint64_t base_addr = (uint64_t)indirect_ptr + (is_indexed ? 12 : 8);
|
||||
genX(write_VERTEX_BUFFER_STATE)(dst_ptr, mocs, 31, base_addr, 8, 0);
|
||||
dst_ptr += GENX(VERTEX_BUFFER_STATE_length);
|
||||
}
|
||||
if (uses_drawid) {
|
||||
*draw_id_ptr = draw_id;
|
||||
genX(write_VERTEX_BUFFER_STATE)(dst_ptr, mocs, 32,
|
||||
(uint64_t)draw_id_ptr, 4, 0);
|
||||
dst_ptr += GENX(VERTEX_BUFFER_STATE_length);
|
||||
}
|
||||
}
|
||||
|
||||
if (is_indexed) {
|
||||
VkDrawIndexedIndirectCommand data =
|
||||
*((global VkDrawIndexedIndirectCommand *)indirect_ptr);
|
||||
|
||||
genX(write_3DPRIMITIVE)(dst_ptr,
|
||||
is_predicated,
|
||||
is_indexed,
|
||||
uses_tbimr,
|
||||
data.indexCount,
|
||||
data.firstIndex,
|
||||
data.instanceCount * instance_multiplier,
|
||||
data.firstInstance,
|
||||
data.vertexOffset);
|
||||
} else {
|
||||
VkDrawIndirectCommand data =
|
||||
*((global VkDrawIndirectCommand *)indirect_ptr);
|
||||
|
||||
genX(write_3DPRIMITIVE)(dst_ptr,
|
||||
is_predicated,
|
||||
is_indexed,
|
||||
uses_tbimr,
|
||||
data.vertexCount,
|
||||
data.firstVertex,
|
||||
data.instanceCount * instance_multiplier,
|
||||
data.firstInstance,
|
||||
0 /* base_vertex_location */);
|
||||
}
|
||||
#else
|
||||
if (is_indexed) {
|
||||
VkDrawIndexedIndirectCommand data =
|
||||
*((global VkDrawIndexedIndirectCommand *)indirect_ptr);
|
||||
|
||||
genX(write_3DPRIMITIVE_EXTENDED)(dst_ptr,
|
||||
is_predicated,
|
||||
is_indexed,
|
||||
uses_tbimr,
|
||||
data.indexCount,
|
||||
data.firstIndex,
|
||||
data.instanceCount * instance_multiplier,
|
||||
data.firstInstance,
|
||||
data.vertexOffset,
|
||||
data.vertexOffset,
|
||||
data.firstInstance,
|
||||
draw_id);
|
||||
} else {
|
||||
VkDrawIndirectCommand data =
|
||||
*((global VkDrawIndirectCommand *)indirect_ptr);
|
||||
|
||||
genX(write_3DPRIMITIVE_EXTENDED)(dst_ptr,
|
||||
is_predicated,
|
||||
is_indexed,
|
||||
uses_tbimr,
|
||||
data.vertexCount,
|
||||
data.firstVertex,
|
||||
data.instanceCount * instance_multiplier,
|
||||
data.firstInstance,
|
||||
0 /* base_vertex_location */,
|
||||
data.firstVertex,
|
||||
data.firstInstance,
|
||||
draw_id);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#if GFX_VERx10 >= 125
|
||||
void genX(write_3DMESH_3D)(global uint32_t *dst_ptr,
|
||||
global void *indirect_ptr,
|
||||
bool is_predicated,
|
||||
bool uses_tbimr)
|
||||
{
|
||||
VkDrawMeshTasksIndirectCommandEXT data =
|
||||
*((global VkDrawMeshTasksIndirectCommandEXT *)indirect_ptr);
|
||||
|
||||
struct GENX(3DMESH_3D) v = {
|
||||
GENX(3DMESH_3D_header),
|
||||
.TBIMREnabled = uses_tbimr,
|
||||
.PredicateEnable = is_predicated,
|
||||
.ThreadGroupCountX = data.groupCountX,
|
||||
.ThreadGroupCountY = data.groupCountY,
|
||||
.ThreadGroupCountZ = data.groupCountZ,
|
||||
|
||||
};
|
||||
GENX(3DMESH_3D_pack)(dst_ptr, &v);
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,99 @@
|
||||
/* Copyright © 2023 Intel Corporation
|
||||
* SPDX-License-Identifier: MIT
|
||||
*/
|
||||
|
||||
#include "libintel_shaders.h"
|
||||
#include "dev/intel_wa.h"
|
||||
|
||||
static void end_generated_draws(global void *dst_ptr,
|
||||
uint32_t item_idx,
|
||||
uint32_t draw_id, uint32_t draw_count,
|
||||
uint32_t ring_count, uint32_t max_draw_count,
|
||||
uint32_t flags, uint32_t _3dprim_size_B,
|
||||
uint64_t gen_addr, uint64_t end_addr)
|
||||
{
|
||||
bool indirect_count = (flags & ANV_GENERATED_FLAG_COUNT) != 0;
|
||||
bool ring_mode = (flags & ANV_GENERATED_FLAG_RING_MODE) != 0;
|
||||
/* We can have an indirect draw count = 0. */
|
||||
uint32_t last_draw_id = draw_count == 0 ? 0 : (min(draw_count, max_draw_count) - 1);
|
||||
global void *jump_dst = draw_count == 0 ? dst_ptr : (dst_ptr + _3dprim_size_B);
|
||||
|
||||
if (ring_mode) {
|
||||
if (draw_id == last_draw_id) {
|
||||
/* Exit the ring buffer to the next user commands */
|
||||
genX(write_MI_BATCH_BUFFER_START)(jump_dst, end_addr);
|
||||
} else if (item_idx == (ring_count - 1)) {
|
||||
/* Jump back to the generation shader to generate mode draws */
|
||||
genX(write_MI_BATCH_BUFFER_START)(jump_dst, gen_addr);
|
||||
}
|
||||
} else {
|
||||
if (draw_id == last_draw_id && draw_count < max_draw_count) {
|
||||
/* Skip forward to the end of the generated draws */
|
||||
genX(write_MI_BATCH_BUFFER_START)(jump_dst, end_addr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
genX(libanv_write_draw)(global void *dst_base,
|
||||
global void *wa_insts_ptr,
|
||||
global void *indirect_base,
|
||||
global void *draw_id_base,
|
||||
uint32_t indirect_stride,
|
||||
global uint32_t *_draw_count,
|
||||
uint32_t draw_base,
|
||||
uint32_t instance_multiplier,
|
||||
uint32_t max_draw_count,
|
||||
uint32_t flags,
|
||||
uint32_t mocs,
|
||||
uint32_t _3dprim_size_B,
|
||||
uint32_t ring_count,
|
||||
uint64_t gen_addr,
|
||||
uint64_t end_addr,
|
||||
uint32_t item_idx)
|
||||
{
|
||||
uint32_t draw_id = draw_base + item_idx;
|
||||
uint32_t draw_count = *_draw_count;
|
||||
global void *dst_ptr = dst_base + item_idx * _3dprim_size_B;
|
||||
global void *indirect_ptr = indirect_base + draw_id * indirect_stride;
|
||||
global void *draw_id_ptr = draw_id_base + item_idx * 4;
|
||||
|
||||
if (draw_id < min(draw_count, max_draw_count)) {
|
||||
bool is_indexed = (flags & ANV_GENERATED_FLAG_INDEXED) != 0;
|
||||
bool is_predicated = (flags & ANV_GENERATED_FLAG_PREDICATED) != 0;
|
||||
bool uses_tbimr = (flags & ANV_GENERATED_FLAG_TBIMR) != 0;
|
||||
bool uses_base = (flags & ANV_GENERATED_FLAG_BASE) != 0;
|
||||
bool uses_drawid = (flags & ANV_GENERATED_FLAG_DRAWID) != 0;
|
||||
uint32_t inst_offset_B = 0;
|
||||
|
||||
#if INTEL_WA_16011107343_GFX_VER
|
||||
if (flags & ANV_GENERATED_FLAG_WA_16011107343) {
|
||||
genX(copy_data)(dst_ptr + inst_offset_B,
|
||||
wa_insts_ptr + inst_offset_B,
|
||||
GENX(3DSTATE_HS_length) * 4);
|
||||
inst_offset_B += GENX(3DSTATE_HS_length) * 4;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if INTEL_WA_22018402687_GFX_VER
|
||||
if (flags & ANV_GENERATED_FLAG_WA_22018402687) {
|
||||
genX(copy_data)(dst_ptr + inst_offset_B,
|
||||
wa_insts_ptr + inst_offset_B,
|
||||
GENX(3DSTATE_DS_length) * 4);
|
||||
inst_offset_B += GENX(3DSTATE_DS_length) * 4;
|
||||
}
|
||||
#endif
|
||||
|
||||
genX(write_draw)(dst_ptr + inst_offset_B,
|
||||
indirect_ptr, draw_id_ptr,
|
||||
draw_id, instance_multiplier,
|
||||
is_indexed, is_predicated,
|
||||
uses_tbimr, uses_base, uses_drawid,
|
||||
mocs);
|
||||
}
|
||||
|
||||
end_generated_draws(dst_ptr, item_idx, draw_id, draw_count,
|
||||
ring_count, max_draw_count,
|
||||
flags, _3dprim_size_B,
|
||||
gen_addr, end_addr);
|
||||
}
|
||||
@@ -0,0 +1,193 @@
|
||||
/* Copyright © 2023 Intel Corporation
|
||||
* SPDX-License-Identifier: MIT
|
||||
*/
|
||||
|
||||
#include "libintel_shaders.h"
|
||||
|
||||
/* As defined in src/gallium/include/pipe/p_state.h : */
|
||||
struct indirect_indexed_draw {
|
||||
uint32_t count;
|
||||
uint32_t instance_count;
|
||||
uint32_t start;
|
||||
int32_t index_bias;
|
||||
uint32_t start_instance;
|
||||
};
|
||||
|
||||
struct indirect_draw {
|
||||
uint32_t count;
|
||||
uint32_t instance_count;
|
||||
uint32_t start;
|
||||
uint32_t start_instance;
|
||||
};
|
||||
|
||||
static global void *write_vertex_inputs_iris(global uint32_t *dst_ptr,
|
||||
global void *indirect_ptr,
|
||||
global uint32_t *draw_id_ptr,
|
||||
uint32_t draw_id,
|
||||
bool is_indexed,
|
||||
bool uses_base,
|
||||
bool uses_drawid,
|
||||
uint32_t sgvs_id,
|
||||
uint32_t mocs)
|
||||
{
|
||||
if (!uses_base && !uses_drawid)
|
||||
return dst_ptr;
|
||||
|
||||
uint32_t vertex_buffer_count =
|
||||
(uses_base ? 1 : 0) + (uses_drawid ? 1 : 0);
|
||||
genX(write_3DSTATE_VERTEX_BUFFERS)(dst_ptr, vertex_buffer_count);
|
||||
dst_ptr += 1; /* GENX(3DSTATE_VERTEX_BUFFERS_length); */
|
||||
if (uses_base) {
|
||||
genX(write_VERTEX_BUFFER_STATE)(dst_ptr, mocs, sgvs_id++,
|
||||
(uint64_t)indirect_ptr, 8, 0);
|
||||
dst_ptr += GENX(VERTEX_BUFFER_STATE_length);
|
||||
}
|
||||
if (uses_drawid) {
|
||||
draw_id_ptr[0] = draw_id;
|
||||
draw_id_ptr[1] = is_indexed ? -1 : 0;
|
||||
genX(write_VERTEX_BUFFER_STATE)(dst_ptr, mocs, sgvs_id++,
|
||||
(uint64_t)draw_id_ptr, 8, 0);
|
||||
dst_ptr += GENX(VERTEX_BUFFER_STATE_length);
|
||||
}
|
||||
return dst_ptr;
|
||||
}
|
||||
|
||||
static void write_draw_iris(global uint32_t *dst_ptr,
|
||||
global void *indirect_ptr,
|
||||
global uint32_t *draw_id_ptr,
|
||||
uint32_t draw_id,
|
||||
bool is_indexed,
|
||||
bool is_predicated,
|
||||
bool uses_tbimr,
|
||||
bool uses_base,
|
||||
bool uses_drawid,
|
||||
uint32_t sgvs_id,
|
||||
uint32_t mocs)
|
||||
{
|
||||
if (is_indexed) {
|
||||
dst_ptr = write_vertex_inputs_iris(dst_ptr, indirect_ptr + 12,
|
||||
draw_id_ptr,
|
||||
draw_id, is_indexed,
|
||||
uses_base, uses_drawid,
|
||||
sgvs_id, mocs);
|
||||
|
||||
|
||||
struct indirect_indexed_draw data =
|
||||
*((global struct indirect_indexed_draw *)indirect_ptr);
|
||||
|
||||
genX(write_3DPRIMITIVE)(dst_ptr,
|
||||
is_predicated,
|
||||
is_indexed,
|
||||
uses_tbimr,
|
||||
data.count,
|
||||
data.start,
|
||||
data.instance_count,
|
||||
data.start_instance,
|
||||
data.index_bias);
|
||||
} else {
|
||||
dst_ptr = write_vertex_inputs_iris(dst_ptr, indirect_ptr + 8,
|
||||
draw_id_ptr,
|
||||
draw_id, is_indexed,
|
||||
uses_base, uses_drawid,
|
||||
sgvs_id, mocs);
|
||||
|
||||
struct indirect_draw data =
|
||||
*((global struct indirect_draw *)indirect_ptr);
|
||||
|
||||
genX(write_3DPRIMITIVE)(dst_ptr,
|
||||
is_predicated,
|
||||
is_indexed,
|
||||
uses_tbimr,
|
||||
data.count,
|
||||
data.start,
|
||||
data.instance_count,
|
||||
data.start_instance,
|
||||
0 /* base_vertex_location */);
|
||||
}
|
||||
}
|
||||
|
||||
static void end_generated_draws_iris(global void *dst_ptr,
|
||||
uint32_t item_idx,
|
||||
uint32_t draw_id, uint32_t draw_count,
|
||||
uint32_t ring_count,
|
||||
uint32_t flags,
|
||||
uint64_t gen_addr, uint64_t end_addr)
|
||||
{
|
||||
uint32_t _3dprim_size = ((flags >> 16) & 0xff) * 4;
|
||||
/* We can have an indirect draw count = 0. */
|
||||
uint32_t last_draw_id = draw_count == 0 ? 0 : (draw_count - 1);
|
||||
global void *jump_dst = draw_count == 0 ? dst_ptr : (dst_ptr + _3dprim_size);
|
||||
|
||||
if (draw_id == last_draw_id) {
|
||||
/* Exit the ring buffer to the next user commands */
|
||||
genX(write_MI_BATCH_BUFFER_START)(jump_dst, end_addr);
|
||||
} else if (item_idx == (ring_count - 1)) {
|
||||
/* Jump back to the generation shader to generate mode draws */
|
||||
genX(write_MI_BATCH_BUFFER_START)(jump_dst, gen_addr);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
genX(libiris_write_draw)(global void *dst_base,
|
||||
global void *indirect_base,
|
||||
global void *draw_id_base,
|
||||
uint32_t indirect_stride,
|
||||
global uint32_t *indirect_draw_count,
|
||||
uint32_t draw_base,
|
||||
uint32_t max_draw_count,
|
||||
uint32_t flags,
|
||||
uint32_t ring_count,
|
||||
uint64_t gen_addr,
|
||||
uint64_t end_addr,
|
||||
uint32_t item_idx)
|
||||
{
|
||||
uint32_t _3dprim_size = ((flags >> 16) & 0xff) * 4;
|
||||
uint32_t sgvs_id = flags >> 24;
|
||||
uint32_t draw_id = draw_base + item_idx;
|
||||
uint32_t draw_count = max_draw_count;
|
||||
global void *dst_ptr = dst_base +
|
||||
#if GFX_VER >= 12
|
||||
GENX(MI_ARB_CHECK_length) * 4 +
|
||||
#endif
|
||||
item_idx * _3dprim_size;
|
||||
global void *indirect_ptr = indirect_base + draw_id * indirect_stride;
|
||||
global void *draw_id_ptr = draw_id_base + item_idx * 8;
|
||||
|
||||
/* Only read the indirect count if we have a valid pointer */
|
||||
if (indirect_draw_count != 0)
|
||||
draw_count = min(draw_count, *indirect_draw_count);
|
||||
|
||||
#if GFX_VER >= 12
|
||||
/* Reenable CS prefetching */
|
||||
if (item_idx == 0) {
|
||||
struct GENX(MI_ARB_CHECK) v = {
|
||||
GENX(MI_ARB_CHECK_header),
|
||||
/* This is a trick to get the CLC->SPIRV not to use a constant
|
||||
* variable for this. Otherwise we run into issues trying to store
|
||||
* that variable in constant memory which is inefficient for a single
|
||||
* dword and also not handled in our backend.
|
||||
*/
|
||||
.PreParserDisableMask = item_idx == 0,
|
||||
.PreParserDisable = false,
|
||||
};
|
||||
GENX(MI_ARB_CHECK_pack)(dst_base, &v);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (draw_id < draw_count) {
|
||||
bool is_indexed = (flags & ANV_GENERATED_FLAG_INDEXED) != 0;
|
||||
bool is_predicated = (flags & ANV_GENERATED_FLAG_PREDICATED) != 0;
|
||||
bool uses_tbimr = (flags & ANV_GENERATED_FLAG_TBIMR) != 0;
|
||||
bool uses_base = (flags & ANV_GENERATED_FLAG_BASE) != 0;
|
||||
bool uses_drawid = (flags & ANV_GENERATED_FLAG_DRAWID) != 0;
|
||||
uint32_t mocs = (flags >> 8) & 0xff;
|
||||
|
||||
write_draw_iris(dst_ptr, indirect_ptr, draw_id_ptr,
|
||||
draw_id, is_indexed, is_predicated,
|
||||
uses_tbimr, uses_base, uses_drawid,
|
||||
sgvs_id, mocs);
|
||||
}
|
||||
|
||||
end_generated_draws_iris(dst_ptr, item_idx, draw_id, draw_count,
|
||||
ring_count, flags, gen_addr, end_addr);
|
||||
}
|
||||
@@ -0,0 +1,149 @@
|
||||
/* Copyright © 2023 Intel Corporation
|
||||
* SPDX-License-Identifier: MIT
|
||||
*/
|
||||
|
||||
#ifndef _LIBANV_SHADERS_H_
|
||||
#define _LIBANV_SHADERS_H_
|
||||
|
||||
/* Define stdint types compatible between the CPU and GPU for shared headers */
|
||||
#ifndef __OPENCL_VERSION__
|
||||
#include <stdint.h>
|
||||
|
||||
#include <vulkan/vulkan_core.h>
|
||||
|
||||
#include "util/macros.h"
|
||||
|
||||
#include "compiler/intel_shader_enums.h"
|
||||
|
||||
#else
|
||||
#include "libcl_vk.h"
|
||||
|
||||
#include "genxml/gen_macros.h"
|
||||
#include "genxml/genX_cl_pack.h"
|
||||
#include "genxml/genX_rt_cl_pack.h"
|
||||
|
||||
#include "compiler/intel_shader_enums.h"
|
||||
|
||||
#define _3DPRIM_PATCHLIST(n) (0x20 + (n - 1))
|
||||
#endif
|
||||
|
||||
#define ANV_GENERATED_MAX_VES (29)
|
||||
|
||||
/**
|
||||
* Flags for generated_draws.cl
|
||||
*/
|
||||
enum anv_generated_draw_flags {
|
||||
ANV_GENERATED_FLAG_INDEXED = BITFIELD_BIT(0),
|
||||
ANV_GENERATED_FLAG_PREDICATED = BITFIELD_BIT(1),
|
||||
/* Only used on Gfx9, means the pipeline is using gl_DrawID */
|
||||
ANV_GENERATED_FLAG_DRAWID = BITFIELD_BIT(2),
|
||||
/* Only used on Gfx9, means the pipeline is using gl_BaseVertex or
|
||||
* gl_BaseInstance
|
||||
*/
|
||||
ANV_GENERATED_FLAG_BASE = BITFIELD_BIT(3),
|
||||
/* Whether the count is indirect */
|
||||
ANV_GENERATED_FLAG_COUNT = BITFIELD_BIT(4),
|
||||
/* Whether the generation shader writes to the ring buffer */
|
||||
ANV_GENERATED_FLAG_RING_MODE = BITFIELD_BIT(5),
|
||||
/* Whether TBIMR tile-based rendering shall be enabled. */
|
||||
ANV_GENERATED_FLAG_TBIMR = BITFIELD_BIT(6),
|
||||
/* Wa_16011107343 */
|
||||
ANV_GENERATED_FLAG_WA_16011107343 = BITFIELD_BIT(7),
|
||||
/* Wa_22018402687 */
|
||||
ANV_GENERATED_FLAG_WA_22018402687 = BITFIELD_BIT(8),
|
||||
/* Wa_16014912113 */
|
||||
ANV_GENERATED_FLAG_WA_16014912113 = BITFIELD_BIT(9),
|
||||
/* Wa_18022330953 / Wa_22011440098 */
|
||||
ANV_GENERATED_FLAG_WA_18022330953 = BITFIELD_BIT(10)
|
||||
};
|
||||
|
||||
/**
|
||||
* Flags for query_copy.cl
|
||||
*/
|
||||
#define ANV_COPY_QUERY_FLAG_RESULT64 BITFIELD_BIT(0)
|
||||
#define ANV_COPY_QUERY_FLAG_AVAILABLE BITFIELD_BIT(1)
|
||||
#define ANV_COPY_QUERY_FLAG_DELTA BITFIELD_BIT(2)
|
||||
#define ANV_COPY_QUERY_FLAG_PARTIAL BITFIELD_BIT(3)
|
||||
|
||||
#ifdef __OPENCL_VERSION__
|
||||
|
||||
void genX(write_address)(global void *dst_ptr,
|
||||
global void *address, uint64_t value);
|
||||
|
||||
void genX(write_3DSTATE_VERTEX_BUFFERS)(global void *dst_ptr,
|
||||
uint32_t buffer_count);
|
||||
|
||||
void genX(write_VERTEX_BUFFER_STATE)(global void *dst_ptr,
|
||||
uint32_t mocs,
|
||||
uint32_t buffer_idx,
|
||||
uint64_t address,
|
||||
uint32_t size,
|
||||
uint32_t stride);
|
||||
|
||||
void genX(write_3DSTATE_INDEX_BUFFER)(global void *dst_ptr,
|
||||
uint64_t buffer_addr,
|
||||
uint32_t buffer_size,
|
||||
uint32_t index_format,
|
||||
uint32_t mocs);
|
||||
|
||||
void genX(write_3DSTATE_VF_TOPOLOGY)(global void *dst_ptr,
|
||||
uint32_t topology);
|
||||
|
||||
void genX(write_3DPRIMITIVE)(global void *dst_ptr,
|
||||
bool is_predicated,
|
||||
bool is_indexed,
|
||||
bool use_tbimr,
|
||||
uint32_t vertex_count_per_instance,
|
||||
uint32_t start_vertex_location,
|
||||
uint32_t instance_count,
|
||||
uint32_t start_instance_location,
|
||||
uint32_t base_vertex_location);
|
||||
|
||||
#if GFX_VER >= 11
|
||||
void genX(write_3DPRIMITIVE_EXTENDED)(global void *dst_ptr,
|
||||
bool is_predicated,
|
||||
bool is_indexed,
|
||||
bool use_tbimr,
|
||||
uint32_t vertex_count_per_instance,
|
||||
uint32_t start_vertex_location,
|
||||
uint32_t instance_count,
|
||||
uint32_t start_instance_location,
|
||||
uint32_t base_vertex_location,
|
||||
uint32_t param_base_vertex,
|
||||
uint32_t param_base_instance,
|
||||
uint32_t param_draw_id);
|
||||
#endif
|
||||
|
||||
#if GFX_VERx10 >= 125
|
||||
void genX(write_3DMESH_3D)(global uint32_t *dst_ptr,
|
||||
global void *indirect_ptr,
|
||||
bool is_predicated,
|
||||
bool uses_tbimr);
|
||||
#endif
|
||||
|
||||
void genX(write_MI_BATCH_BUFFER_START)(global void *dst_ptr, uint64_t addr);
|
||||
|
||||
void genX(write_draw)(global uint32_t *dst_ptr,
|
||||
global void *indirect_ptr,
|
||||
global uint32_t *draw_id_ptr,
|
||||
uint32_t draw_id,
|
||||
uint32_t instance_multiplier,
|
||||
bool is_indexed,
|
||||
bool is_predicated,
|
||||
bool uses_tbimr,
|
||||
bool uses_base,
|
||||
bool uses_draw_id,
|
||||
uint32_t mocs);
|
||||
|
||||
|
||||
void genX(copy_data)(global void *dst_ptr,
|
||||
global void *src_ptr,
|
||||
uint32_t size);
|
||||
|
||||
void genX(set_data)(global void *dst_ptr,
|
||||
uint32_t data,
|
||||
uint32_t size);
|
||||
|
||||
#endif /* __OPENCL_VERSION__ */
|
||||
|
||||
#endif /* _LIBANV_SHADERS_H_ */
|
||||
@@ -0,0 +1,85 @@
|
||||
# Copyright © 2023 Intel Corporation
|
||||
# SPDX-License-Identifier: MIT
|
||||
|
||||
if with_intel_vk
|
||||
intel_float64_spv_h = custom_target(
|
||||
'float64_spv.h',
|
||||
input : [glsl2spirv, float64_glsl_file],
|
||||
output : 'float64_spv.h',
|
||||
command : [
|
||||
prog_python, '@INPUT@', '@OUTPUT@',
|
||||
prog_glslang,
|
||||
'--vn', 'float64_spv_source',
|
||||
'--glsl-version', '450',
|
||||
'-Olib',
|
||||
glslang_depfile,
|
||||
],
|
||||
depfile : 'float64_spv.h.d',
|
||||
)
|
||||
endif
|
||||
|
||||
intel_shader_files = files(
|
||||
'libintel_shaders.h',
|
||||
'dgc.cl',
|
||||
'dgc_debug.cl',
|
||||
'generate.cl',
|
||||
'generate_draws.cl',
|
||||
'generate_draws_iris.cl',
|
||||
'query_copy.cl',
|
||||
'util.cl',
|
||||
)
|
||||
|
||||
intel_shaders_gens = [ [ 80, 8],
|
||||
[ 90, 9],
|
||||
[110, 11],
|
||||
[120, 12],
|
||||
[125, 125],
|
||||
[200, 20],
|
||||
[300, 30],
|
||||
[350, 35],
|
||||
]
|
||||
intel_shaders = []
|
||||
intel_shaders_headers = []
|
||||
foreach gen : intel_shaders_gens
|
||||
intel_shaders_spv = custom_target(
|
||||
input : intel_shader_files,
|
||||
output : 'intel_gfx@0@_shaders.spv'.format(gen[0]),
|
||||
command : [
|
||||
prog_mesa_clc,
|
||||
intel_shader_files, '-o', '@OUTPUT@', '--depfile', '@DEPFILE@', '--',
|
||||
'-Wno-initializer-overrides',
|
||||
'-DGFX_VERx10=@0@'.format(gen[0]),
|
||||
'-I' + join_paths(meson.current_source_dir(), '.'),
|
||||
'-I' + join_paths(dir_source_root, 'src/compiler/libcl'),
|
||||
'-I' + join_paths(dir_source_root, 'src'),
|
||||
'-I' + join_paths(dir_source_root, 'src/intel'),
|
||||
'-I' + join_paths(meson.project_build_root(), 'src/intel'),
|
||||
'-I' + join_paths(dir_source_root, 'src/intel/genxml'),
|
||||
cl_args,
|
||||
],
|
||||
depends : [gen_cl_xml_pack, intel_dev_wa_src],
|
||||
depfile : 'intel_gfx@0@_shaders.spv.d'.format(gen[0]),
|
||||
)
|
||||
|
||||
_intel_shaders = custom_target(
|
||||
input : intel_shaders_spv,
|
||||
output : ['intel_gfx@0@_shaders_binding.cpp'.format(gen[0]),
|
||||
'intel_gfx@0@_shaders_binding.h'.format(gen[0])],
|
||||
command : [prog_vtn_bindgen2, intel_shaders_spv, '@OUTPUT0@', '@OUTPUT1@'],
|
||||
)
|
||||
|
||||
intel_shaders += _intel_shaders
|
||||
intel_shaders_headers += _intel_shaders[1]
|
||||
endforeach
|
||||
|
||||
libintel_shaders = static_library(
|
||||
'intel_shaders',
|
||||
intel_shaders,
|
||||
dependencies : idep_nir,
|
||||
)
|
||||
|
||||
idep_intel_shaders = declare_dependency(
|
||||
link_with : libintel_shaders,
|
||||
sources : intel_shaders_headers,
|
||||
include_directories : include_directories('.'),
|
||||
)
|
||||
@@ -0,0 +1,74 @@
|
||||
/* Copyright © 2023 Intel Corporation
|
||||
* SPDX-License-Identifier: MIT
|
||||
*/
|
||||
|
||||
#include "libintel_shaders.h"
|
||||
|
||||
void
|
||||
genX(libanv_query_copy)(global void *destination_base,
|
||||
uint32_t destination_stride,
|
||||
global void *query_data,
|
||||
uint32_t first_query,
|
||||
uint32_t num_queries,
|
||||
uint32_t query_data_offset,
|
||||
uint32_t query_stride,
|
||||
uint32_t num_query_items,
|
||||
uint32_t copy_flags,
|
||||
uint32_t copy_item_idx)
|
||||
{
|
||||
if (copy_item_idx >= num_queries)
|
||||
return;
|
||||
|
||||
bool is_result64 = (copy_flags & ANV_COPY_QUERY_FLAG_RESULT64) != 0;
|
||||
bool write_available = (copy_flags & ANV_COPY_QUERY_FLAG_AVAILABLE) != 0;
|
||||
bool compute_delta = (copy_flags & ANV_COPY_QUERY_FLAG_DELTA) != 0;
|
||||
bool partial_result = (copy_flags & ANV_COPY_QUERY_FLAG_PARTIAL) != 0;
|
||||
|
||||
|
||||
uint query_byte = (first_query + copy_item_idx) * query_stride;
|
||||
uint query_data_byte = query_byte + query_data_offset;
|
||||
|
||||
global uint64_t *query = query_data + (first_query + copy_item_idx) * query_stride;
|
||||
global uint64_t *dest64 = destination_base + copy_item_idx * destination_stride;
|
||||
global uint32_t *dest32 = destination_base + copy_item_idx * destination_stride;
|
||||
|
||||
uint64_t availability = *(global uint32_t *)(query_data + query_byte);
|
||||
|
||||
if (write_available) {
|
||||
if (is_result64)
|
||||
dest64[num_query_items] = availability;
|
||||
else
|
||||
dest32[num_query_items] = availability;
|
||||
}
|
||||
|
||||
for (uint32_t i = 0; i < num_query_items; i++) {
|
||||
uint32_t qw_offset = 1 + i * 2;
|
||||
uint64_t v;
|
||||
if (compute_delta) {
|
||||
struct delta64 {
|
||||
uint64_t v0;
|
||||
uint64_t v1;
|
||||
} data = *((global struct delta64 *)&query[qw_offset]);
|
||||
v = data.v1 - data.v0;
|
||||
} else {
|
||||
v = query[qw_offset + 0];
|
||||
}
|
||||
|
||||
/* vkCmdCopyQueryPoolResults:
|
||||
*
|
||||
* "If VK_QUERY_RESULT_PARTIAL_BIT is set, then for any query that is
|
||||
* unavailable, an intermediate result between zero and the final
|
||||
* result value is written for that query."
|
||||
*
|
||||
* We write 0 as the values not being written yet, we can't really make
|
||||
* provide any sensible value.
|
||||
*/
|
||||
if (partial_result && availability == 0)
|
||||
v = 0;
|
||||
|
||||
if (is_result64)
|
||||
dest64[i] = v;
|
||||
else
|
||||
dest32[i] = v;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,65 @@
|
||||
/* Copyright © 2024 Intel Corporation
|
||||
* SPDX-License-Identifier: MIT
|
||||
*/
|
||||
|
||||
#include "libintel_shaders.h"
|
||||
|
||||
/* Memcpy data using multiple lanes. */
|
||||
void genX(libanv_memcpy)(global void *dst_base,
|
||||
global void *src_base,
|
||||
uint num_dwords,
|
||||
uint dword_offset)
|
||||
{
|
||||
global void *dst = dst_base + 4 * dword_offset;
|
||||
global void *src = src_base + 4 * dword_offset;
|
||||
|
||||
if (dword_offset + 4 <= num_dwords) {
|
||||
*(global uint4 *)(dst) = *(global uint4 *)(src);
|
||||
} else if (dword_offset + 3 <= num_dwords) {
|
||||
*(global uint3 *)(dst) = *(global uint3 *)(src);
|
||||
} else if (dword_offset + 2 <= num_dwords) {
|
||||
*(global uint2 *)(dst) = *(global uint2 *)(src);
|
||||
} else if (dword_offset + 1 <= num_dwords) {
|
||||
*(global uint *)(dst) = *(global uint *)(src);
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy size from src_ptr to dst_ptr for using a single lane with size
|
||||
* multiple of 4.
|
||||
*/
|
||||
void genX(copy_data)(global void *dst_ptr,
|
||||
global void *src_ptr,
|
||||
uint32_t size)
|
||||
{
|
||||
for (uint32_t offset = 0; offset < size; offset += 16) {
|
||||
if (offset + 16 <= size) {
|
||||
*(global uint4 *)(dst_ptr + offset) = *(global uint4 *)(src_ptr + offset);
|
||||
} else if (offset + 12 <= size) {
|
||||
*(global uint3 *)(dst_ptr + offset) = *(global uint3 *)(src_ptr + offset);
|
||||
} else if (offset + 8 <= size) {
|
||||
*(global uint2 *)(dst_ptr + offset) = *(global uint2 *)(src_ptr + offset);
|
||||
} else if (offset + 4 <= size) {
|
||||
*(global uint *)(dst_ptr + offset) = *(global uint *)(src_ptr + offset);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy size from src_ptr to dst_ptr for using a single lane with size
|
||||
* multiple of 4.
|
||||
*/
|
||||
void genX(set_data)(global void *dst_ptr,
|
||||
uint32_t size,
|
||||
uint32_t data)
|
||||
{
|
||||
for (uint32_t offset = 0; offset < size; offset += 16) {
|
||||
if (offset + 16 <= size) {
|
||||
*(global uint4 *)(dst_ptr + offset) = (uint4)(data);
|
||||
} else if (offset + 12 <= size) {
|
||||
*(global uint3 *)(dst_ptr + offset) = (uint3)(data);
|
||||
} else if (offset + 8 <= size) {
|
||||
*(global uint2 *)(dst_ptr + offset) = (uint2)(data);
|
||||
} else if (offset + 4 <= size) {
|
||||
*(global uint *)(dst_ptr + offset) = data;
|
||||
}
|
||||
}
|
||||
}
|
||||
Reference in new issue
Block a user