From cd91e8f22fe914819faab4068e8eca1a8b34cc62 Mon Sep 17 00:00:00 2001 From: dancingmirrors Date: Thu, 16 Jul 2026 08:01:54 -0600 Subject: [PATCH] hasvk: Remove now unreachable layered clamping. --- src/intel/vulkan_hasvk/anv_image.c | 5 +- src/intel/vulkan_hasvk/anv_private.h | 2 - src/intel/vulkan_hasvk/genX_cmd_video.c | 63 ++++++------------------- 3 files changed, 15 insertions(+), 55 deletions(-) diff --git a/src/intel/vulkan_hasvk/anv_image.c b/src/intel/vulkan_hasvk/anv_image.c index 2516198..054662f 100644 --- a/src/intel/vulkan_hasvk/anv_image.c +++ b/src/intel/vulkan_hasvk/anv_image.c @@ -1018,7 +1018,6 @@ static VkResult add_all_surfaces_implicit_interleaved_arrays_layout( struct anv_device *device, struct anv_image *image, - const VkImageFormatListCreateInfo *format_list_info, isl_tiling_flags_t isl_tiling_flags, isl_surf_usage_flags_t isl_extra_usage_flags) { @@ -1094,8 +1093,6 @@ add_all_surfaces_implicit_interleaved_arrays_layout( return result; } - image->vid_layered_interleaved = true; - return VK_SUCCESS; } @@ -1121,7 +1118,7 @@ add_all_surfaces_implicit_layout( VK_IMAGE_USAGE_VIDEO_DECODE_DPB_BIT_KHR))) { assert(stride == 0); return add_all_surfaces_implicit_interleaved_arrays_layout( - device, image, format_list_info, isl_tiling_flags, + device, image, isl_tiling_flags, isl_extra_usage_flags); } diff --git a/src/intel/vulkan_hasvk/anv_private.h b/src/intel/vulkan_hasvk/anv_private.h index aa4d11b..9e82245 100644 --- a/src/intel/vulkan_hasvk/anv_private.h +++ b/src/intel/vulkan_hasvk/anv_private.h @@ -3227,8 +3227,6 @@ struct anv_image { bool vid_neutral_chroma_init; - bool vid_layered_interleaved; - /** * The memory bindings created by vkCreateImage and vkBindImageMemory. * diff --git a/src/intel/vulkan_hasvk/genX_cmd_video.c b/src/intel/vulkan_hasvk/genX_cmd_video.c index e24c33b..4796fda 100644 --- a/src/intel/vulkan_hasvk/genX_cmd_video.c +++ b/src/intel/vulkan_hasvk/genX_cmd_video.c @@ -163,31 +163,6 @@ anv_h264_sane_field_pocs(const int32_t poc[2], int32_t *top, int32_t *bottom) *top = t; *bottom = b; } -static inline struct anv_address -anv_h264_dpb_addr(const struct anv_image_view *iv, uint32_t layer, bool clamp0) -{ - if (clamp0) - return anv_image_address(iv->image, - &iv->image->planes[0].primary_surface.memory_range); - return anv_image_dpb_address(iv, layer); -} - -static inline struct anv_address -anv_h264_dmv_top(const struct anv_image_view *iv, uint32_t layer, bool clamp0) -{ - if (clamp0) - return anv_image_address(iv->image, &iv->image->vid_dmv_top_surface); - return anv_image_dmv_top_address(iv, layer); -} - -static inline struct anv_address -anv_h264_dmv_bottom(const struct anv_image_view *iv, uint32_t layer, bool clamp0) -{ - if (clamp0) - return anv_image_address(iv->image, &iv->image->vid_dmv_bottom_surface); - return anv_image_dmv_bottom_address(iv, layer); -} - static void anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer, const VkVideoDecodeInfoKHR *frame_info) @@ -250,15 +225,6 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer, const struct anv_image_view *iv = anv_image_view_from_handle(frame_info->dstPictureResource.imageViewBinding); const struct anv_image *img = iv->image; -#if GFX_VER < 8 - const bool gen7_layered_clamp = - img->vk.array_layers > 1 && !img->vid_layered_interleaved; - if (gen7_layered_clamp) - mesa_logw_once("Layered DPB is broken on GFX 7 when the array pitch is not tile aligned."); -#else - const bool gen7_layered_clamp = false; -#endif - if (ANV_DEBUG(VIDEO_DEBUG)) { const StdVideoDecodeH264PictureInfo *p = h264_pic_info->pStdPictureInfo; mesa_logi("f_num=%d poc=%d/%d field=%u bot=%u idr=%u ref=%u " @@ -342,7 +308,7 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer, buf.CommandType = 3; struct anv_address dst_addr = - anv_h264_dpb_addr(iv, frame_info->dstPictureResource.baseArrayLayer, gen7_layered_clamp); + anv_image_dpb_address(iv, frame_info->dstPictureResource.baseArrayLayer); #if GFX_VERx10 == 70 buf.PostDeblockingDestinationAddress = dst_addr; buf.PostDeblockingDestinationCacheabilityControl = 2; @@ -394,9 +360,8 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer, continue; const struct anv_image_view *ref_iv = anv_image_view_from_handle(frame_info->pReferenceSlots[i].pPictureResource->imageViewBinding); struct anv_address ref_addr = - anv_h264_dpb_addr(ref_iv, - frame_info->pReferenceSlots[i].pPictureResource->baseArrayLayer, - gen7_layered_clamp); + anv_image_dpb_address(ref_iv, + frame_info->pReferenceSlots[i].pPictureResource->baseArrayLayer); buf.ReferencePictureAddress[hw] = ref_addr; #if GFX_VERx10 == 70 @@ -675,7 +640,7 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer, uint32_t ref_layer = frame_info->pReferenceSlots[i].pPictureResource->baseArrayLayer; if (i == 0) - dmv_bo = anv_h264_dmv_top(ref_iv, ref_layer, gen7_layered_clamp).bo; + dmv_bo = anv_image_dmv_top_address(ref_iv, ref_layer).bo; #if GFX_VERx10 == 70 { bool ref_is_field = ref_info && @@ -683,16 +648,16 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer, bool ref_dmv_bottom = ref_is_field && !sps->flags.direct_8x8_inference_flag; avc_directmode.DirectMVBufferAddress[hw * 2] = - anv_h264_dmv_top(ref_iv, ref_layer, gen7_layered_clamp); + anv_image_dmv_top_address(ref_iv, ref_layer); avc_directmode.DirectMVBufferAddress[hw * 2 + 1] = ref_dmv_bottom ? - anv_h264_dmv_bottom(ref_iv, ref_layer, gen7_layered_clamp) : - anv_h264_dmv_top(ref_iv, ref_layer, gen7_layered_clamp); + anv_image_dmv_bottom_address(ref_iv, ref_layer) : + anv_image_dmv_top_address(ref_iv, ref_layer); } avc_directmode.DirectMVBufferCacheabilityControl[hw * 2] = 2; avc_directmode.DirectMVBufferCacheabilityControl[hw * 2 + 1] = 2; #elif GFX_VERx10 == 75 { - struct anv_address dmv_addr = anv_h264_dmv_top(ref_iv, ref_layer, gen7_layered_clamp); + struct anv_address dmv_addr = anv_image_dmv_top_address(ref_iv, ref_layer); if (hw == 0) { avc_directmode.DirectMVBuffer0Address = dmv_addr; avc_directmode.DirectMVBufferMOCS = anv_mocs(cmd_buffer->device, dmv_addr.bo, 0); @@ -702,7 +667,7 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer, } } #elif GFX_VERx10 == 80 - avc_directmode.DirectMVBufferAddress[hw] = anv_h264_dmv_top(ref_iv, ref_layer, gen7_layered_clamp); + avc_directmode.DirectMVBufferAddress[hw] = anv_image_dmv_top_address(ref_iv, ref_layer); #endif { int32_t ref_top, ref_bot; @@ -716,21 +681,21 @@ anv_h264_decode_video(struct anv_cmd_buffer *cmd_buffer, { bool cur_dmv_bottom = field_pic && !sps->flags.direct_8x8_inference_flag; avc_directmode.DirectMVBufferWriteAddress[0] = - anv_h264_dmv_top(iv, dst_layer, gen7_layered_clamp); + anv_image_dmv_top_address(iv, dst_layer); avc_directmode.DirectMVBufferWriteAddress[1] = cur_dmv_bottom ? - anv_h264_dmv_bottom(iv, dst_layer, gen7_layered_clamp) : - anv_h264_dmv_top(iv, dst_layer, gen7_layered_clamp); + anv_image_dmv_bottom_address(iv, dst_layer) : + anv_image_dmv_top_address(iv, dst_layer); } avc_directmode.DirectMVBufferWriteCacheabilityControl[0] = 2; avc_directmode.DirectMVBufferWriteCacheabilityControl[1] = 2; #elif GFX_VERx10 == 75 - avc_directmode.DirectMVBufferWriteAddress = anv_h264_dmv_top(iv, dst_layer, gen7_layered_clamp); + avc_directmode.DirectMVBufferWriteAddress = anv_image_dmv_top_address(iv, dst_layer); avc_directmode.DirectMVBufferWriteMOCS = anv_mocs(cmd_buffer->device, avc_directmode.DirectMVBufferWriteAddress.bo, 0); if (!avc_directmode.DirectMVBufferMOCS) avc_directmode.DirectMVBufferMOCS = anv_mocs(cmd_buffer->device, avc_directmode.DirectMVBufferWriteAddress.bo, 0); #elif GFX_VERx10 == 80 avc_directmode.DirectMVBufferAttributes.TargetCache = 2; /* LLC/eLLC */ - avc_directmode.DirectMVBufferWriteAddress = anv_h264_dmv_top(iv, dst_layer, gen7_layered_clamp); + avc_directmode.DirectMVBufferWriteAddress = anv_image_dmv_top_address(iv, dst_layer); avc_directmode.DirectMVBufferWriteAttributes.TargetCache = 2; #endif {