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81 lines
2.8 KiB
C
81 lines
2.8 KiB
C
/*
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* Copyright 2008 Corbin Simpson <[email protected]>
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* SPDX-License-Identifier: MIT
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*/
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#ifndef R300_CHIPSET_H
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#define R300_CHIPSET_H
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#include "util/compiler.h"
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/* these are sizes in dwords */
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#define R300_HIZ_LIMIT 10240
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#define RV530_HIZ_LIMIT 15360
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/* rv3xx have only one pipe */
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#define PIPE_ZMASK_SIZE 4096
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#define RV3xx_ZMASK_SIZE 5120
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/* The size of a compressed tile. Each compressed tile takes 2 bits
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* in the ZMASK RAM, so there is always 16 tiles per one dword. */
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enum r300_zmask_compression {
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R300_ZCOMP_4X4 = 4,
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R300_ZCOMP_8X8 = 8
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};
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/* Structure containing all the possible information about a specific Radeon
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* in the R3xx, R4xx, and R5xx families. */
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struct r300_capabilities {
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/* Chipset family */
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int family;
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/* The number of vertex floating-point units */
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unsigned num_vert_fpus;
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/* The number of texture units. */
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unsigned num_tex_units;
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/* Whether or not TCL is physically present. */
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bool has_hardware_tcl;
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/* Whether or not hardware TCL is enabled. Debug options may disable it. */
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bool has_tcl;
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/* Some chipsets do not have HiZ RAM - other have varying amounts. */
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int hiz_ram;
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/* Some chipsets have zmask ram per pipe some don't. */
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int zmask_ram;
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/* CMASK is for MSAA colorbuffer compression and fast clear. */
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bool has_cmask;
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/* Compression mode for ZMASK. */
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enum r300_zmask_compression z_compress;
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/* Whether or not this is RV350 or newer, including all r400 and r500
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* chipsets. The differences compared to the oldest r300 chips are:
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* - Blend LTE/GTE thresholds
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* - Better MACRO_SWITCH in texture tiling
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* - Half float vertex
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* - More HyperZ optimizations */
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bool is_rv350;
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/* Whether or not this is R400. The differences compared their rv350
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* cousins are:
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* - Extended fragment shader registers
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* - 3DC texture compression (RGTC2) */
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bool is_r400;
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/* Whether or not this is an RV515 or newer; R500s have many differences
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* that require extra consideration, compared to their rv350 cousins:
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* - Extra bit of width and height on texture sizes
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* - Blend color is split across two registers
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* - Universal Shader (US) block used for fragment shaders
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* - FP16 blending and multisampling
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* - Full RGTC texture compression
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* - 24-bit depth textures
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* - Stencil back-face reference value
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* - Ability to render up to 2^24 - 1 vertices with signed index offset */
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bool is_r500;
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/* Whether or not the second pixel pipe is accessed with the high bit */
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bool high_second_pipe;
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/* DXTC texture swizzling. */
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bool dxtc_swizzle;
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/* Whether R500_US_FORMAT0_0 exists (R520-only and depends on DRM). */
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bool has_us_format;
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};
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void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps);
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#endif /* R300_CHIPSET_H */
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