mirror of
https://github.com/elwrcl/intel-hard-graphics.git
synced 2026-11-01 11:18:03 +03:00
621 lines
18 KiB
Rust
621 lines
18 KiB
Rust
// Copyright © 2022 Collabora, Ltd.
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// SPDX-License-Identifier: MIT
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use crate::api::{GetDebugFlags, DEBUG};
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use crate::const_tracker::ConstTracker;
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use crate::ir::*;
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use crate::liveness::{BlockLiveness, Liveness, SimpleLiveness};
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use rustc_hash::{FxHashMap, FxHashSet};
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pub fn src_is_upred_reg(src: &Src) -> bool {
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match &src.src_ref {
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SrcRef::True | SrcRef::False => false,
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SrcRef::SSA(ssa) => {
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assert!(ssa.comps() == 1);
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match ssa[0].file() {
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RegFile::Pred => false,
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RegFile::UPred => true,
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_ => panic!("Not a predicate source"),
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}
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}
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SrcRef::Reg(_) => panic!("Not in SSA form"),
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_ => panic!("Not a predicate source"),
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}
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}
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pub fn src_is_reg(src: &Src, reg_file: RegFile) -> bool {
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match &src.src_ref {
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SrcRef::Zero | SrcRef::True | SrcRef::False => true,
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SrcRef::SSA(ssa) => ssa.file() == reg_file,
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SrcRef::Imm32(_) | SrcRef::CBuf(_) => false,
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SrcRef::Reg(_) => panic!("Not in SSA form"),
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}
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}
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pub fn swap_srcs_if_not_reg(
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x: &mut Src,
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y: &mut Src,
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reg_file: RegFile,
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) -> bool {
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if !src_is_reg(x, reg_file) && src_is_reg(y, reg_file) {
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std::mem::swap(x, y);
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true
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} else {
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false
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}
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}
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fn src_is_imm(src: &Src) -> bool {
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matches!(src.src_ref, SrcRef::Imm32(_))
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}
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pub enum PadValue {
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Zero,
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#[allow(dead_code)]
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Undefined,
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}
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pub trait LegalizeBuildHelpers: SSABuilder {
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fn copy_ssa(&mut self, ssa: &mut SSAValue, reg_file: RegFile) {
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let tmp = self.alloc_ssa(reg_file);
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self.copy_to(tmp.into(), (*ssa).into());
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*ssa = tmp;
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}
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fn copy_ssa_ref(&mut self, vec: &mut SSARef, reg_file: RegFile) {
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for ssa in &mut vec[..] {
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self.copy_ssa(ssa, reg_file);
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}
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}
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fn copy_pred_ssa_if_uniform(&mut self, ssa: &mut SSAValue) {
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match ssa.file() {
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RegFile::Pred => (),
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RegFile::UPred => self.copy_ssa(ssa, RegFile::Pred),
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_ => panic!("Not a predicate value"),
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}
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}
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fn copy_pred_if_upred(&mut self, pred: &mut Pred) {
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match &mut pred.pred_ref {
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PredRef::None => (),
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PredRef::SSA(ssa) => {
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self.copy_pred_ssa_if_uniform(ssa);
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}
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PredRef::Reg(_) => panic!("Not in SSA form"),
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}
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}
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fn copy_src_if_upred(&mut self, src: &mut Src) {
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match &mut src.src_ref {
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SrcRef::True | SrcRef::False => (),
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SrcRef::SSA(ssa) => {
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assert!(ssa.comps() == 1);
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self.copy_pred_ssa_if_uniform(&mut ssa[0]);
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}
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SrcRef::Reg(_) => panic!("Not in SSA form"),
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_ => panic!("Not a predicate source"),
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}
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}
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fn copy_src_if_not_same_file(&mut self, src: &mut Src) {
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let SrcRef::SSA(vec) = &mut src.src_ref else {
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return;
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};
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if vec.comps() == 1 {
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return;
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}
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let mut all_same = true;
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let file = vec[0].file();
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for i in 1..vec.comps() {
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let c_file = vec[usize::from(i)].file();
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if c_file != file {
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debug_assert!(c_file.to_warp() == file.to_warp());
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all_same = false;
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}
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}
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if !all_same {
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self.copy_ssa_ref(vec, file.to_warp());
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}
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}
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fn align_reg(
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&mut self,
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src: &mut Src,
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n_comps: usize,
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pad_value: PadValue,
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) {
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debug_assert!(!matches!(src.src_ref, SrcRef::Reg(_)));
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let SrcRef::SSA(ref old_val) = src.src_ref else {
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return;
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};
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assert!(old_val.len() <= n_comps);
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assert!(src.is_unmodified());
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let pad_fn = || {
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Some(match pad_value {
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PadValue::Zero => self.copy(0.into()),
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PadValue::Undefined => self.undef(),
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})
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};
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// Pad the given ssa_ref with either undefined or zero
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let ssa_vals: Vec<_> = old_val
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.iter()
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.copied()
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.chain(std::iter::from_fn(pad_fn))
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.take(n_comps)
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.collect();
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// Collect it in a new ssa_ref and replace it with the original.
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let val = SSARef::try_from(ssa_vals).expect("Cannot create SSARef");
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src.src_ref = val.into();
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}
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fn copy_alu_src(
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&mut self,
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src: &mut Src,
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reg_file: RegFile,
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src_type: SrcType,
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) {
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let val = match src_type {
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SrcType::GPR
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| SrcType::ALU
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| SrcType::F32
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| SrcType::F16
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| SrcType::F16v2
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| SrcType::I32
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| SrcType::B32 => self.alloc_ssa_vec(reg_file, 1),
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SrcType::F64 => self.alloc_ssa_vec(reg_file, 2),
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SrcType::Pred => self.alloc_ssa_vec(reg_file, 1),
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_ => panic!("Unknown source type"),
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};
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if DEBUG.annotate() {
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self.push_instr(Instr::new(OpAnnotate {
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annotation: "copy generated by legalizer".into(),
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}));
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}
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let old_src_ref =
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std::mem::replace(&mut src.src_ref, val.clone().into());
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if val.comps() == 1 {
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self.copy_to(val[0].into(), old_src_ref.into());
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} else {
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match old_src_ref {
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SrcRef::Imm32(u) => {
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// Immediates go in the top bits
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self.copy_to(val[0].into(), 0.into());
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self.copy_to(val[1].into(), u.into());
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}
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SrcRef::CBuf(cb) => {
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// CBufs load 8B
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self.copy_to(val[0].into(), cb.clone().into());
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self.copy_to(val[1].into(), cb.offset(4).into());
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}
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SrcRef::SSA(vec) => {
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assert!(vec.comps() == 2);
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self.copy_to(val[0].into(), vec[0].into());
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self.copy_to(val[1].into(), vec[1].into());
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}
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_ => panic!("Invalid 64-bit SrcRef"),
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}
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}
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}
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fn copy_alu_src_if_not_reg(
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&mut self,
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src: &mut Src,
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reg_file: RegFile,
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src_type: SrcType,
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) {
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if !src_is_reg(src, reg_file) {
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self.copy_alu_src(src, reg_file, src_type);
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}
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}
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fn copy_alu_src_if_not_reg_or_imm(
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&mut self,
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src: &mut Src,
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reg_file: RegFile,
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src_type: SrcType,
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) {
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if !src_is_reg(src, reg_file)
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&& !matches!(&src.src_ref, SrcRef::Imm32(_))
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{
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self.copy_alu_src(src, reg_file, src_type);
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}
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}
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fn copy_alu_src_if_imm(
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&mut self,
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src: &mut Src,
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reg_file: RegFile,
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src_type: SrcType,
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) {
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if src_is_imm(src) {
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self.copy_alu_src(src, reg_file, src_type);
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}
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}
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fn copy_alu_src_if_ineg_imm(
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&mut self,
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src: &mut Src,
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reg_file: RegFile,
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src_type: SrcType,
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) {
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assert!(src_type == SrcType::I32);
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if src_is_imm(src) && src.src_mod.is_ineg() {
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self.copy_alu_src(src, reg_file, src_type);
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}
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}
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fn copy_alu_src_if_both_not_reg(
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&mut self,
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src1: &Src,
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src2: &mut Src,
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reg_file: RegFile,
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src_type: SrcType,
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) {
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if !src_is_reg(src1, reg_file) && !src_is_reg(src2, reg_file) {
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self.copy_alu_src(src2, reg_file, src_type);
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}
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}
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fn copy_alu_src_and_lower_fmod(
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&mut self,
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src: &mut Src,
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reg_file: RegFile,
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src_type: SrcType,
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) {
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match src_type {
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SrcType::F16 | SrcType::F16v2 => {
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let val = self.alloc_ssa(reg_file);
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let old_src = std::mem::replace(src, val.into());
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self.push_op(OpHAdd2 {
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dst: val.into(),
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srcs: [Src::ZERO.fneg(), old_src],
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saturate: false,
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ftz: false,
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f32: false,
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});
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}
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SrcType::F32 => {
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let val = self.alloc_ssa(reg_file);
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let old_src = std::mem::replace(src, val.into());
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self.push_op(OpFAdd {
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dst: val.into(),
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srcs: [Src::ZERO.fneg(), old_src],
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saturate: false,
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rnd_mode: FRndMode::NearestEven,
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ftz: false,
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});
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}
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SrcType::F64 => {
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let val = self.alloc_ssa_vec(reg_file, 2);
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let old_src = std::mem::replace(src, val.clone().into());
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self.push_op(OpDAdd {
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dst: val.into(),
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srcs: [Src::ZERO.fneg(), old_src],
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rnd_mode: FRndMode::NearestEven,
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});
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}
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_ => panic!("Invalid ffabs srouce type"),
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}
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}
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fn copy_alu_src_and_lower_ineg(
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&mut self,
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src: &mut Src,
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reg_file: RegFile,
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src_type: SrcType,
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) {
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assert!(src_type == SrcType::I32);
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let val = self.alloc_ssa(reg_file);
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let old_src = std::mem::replace(src, val.into());
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if self.sm() >= 70 {
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self.push_op(OpIAdd3 {
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srcs: [Src::ZERO, old_src, Src::ZERO],
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overflow: [Dst::None, Dst::None],
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dst: val.into(),
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});
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} else {
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self.push_op(OpIAdd2 {
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dst: val.into(),
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carry_out: Dst::None,
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srcs: [Src::ZERO, old_src],
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});
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}
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}
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fn copy_alu_src_if_fabs(
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&mut self,
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src: &mut Src,
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reg_file: RegFile,
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src_type: SrcType,
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) {
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if src.src_mod.has_fabs() {
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self.copy_alu_src_and_lower_fmod(src, reg_file, src_type);
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}
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}
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fn copy_alu_src_if_i20_overflow(
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&mut self,
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src: &mut Src,
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reg_file: RegFile,
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src_type: SrcType,
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) {
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if src.as_imm_not_i20().is_some() {
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self.copy_alu_src(src, reg_file, src_type);
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}
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}
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fn copy_alu_src_if_f20_overflow(
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&mut self,
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src: &mut Src,
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reg_file: RegFile,
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src_type: SrcType,
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) {
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if src.as_imm_not_f20().is_some() {
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self.copy_alu_src(src, reg_file, src_type);
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}
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}
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fn copy_ssa_ref_if_uniform(&mut self, ssa_ref: &mut SSARef) {
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for ssa in &mut ssa_ref[..] {
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if ssa.is_uniform() {
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let warp = self.alloc_ssa(ssa.file().to_warp());
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self.copy_to(warp.into(), (*ssa).into());
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*ssa = warp;
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}
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}
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}
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fn copy_src_if_uniform(&mut self, src: &mut Src) {
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match &mut src.src_ref {
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SrcRef::SSA(ssa) => self.copy_ssa_ref_if_uniform(ssa),
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SrcRef::Imm32(_) | SrcRef::False | SrcRef::True | SrcRef::Zero => {}
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_ => panic!("Unsupported source reference"),
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}
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}
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}
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pub struct LegalizeBuilder<'a> {
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b: SSAInstrBuilder<'a>,
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const_tracker: &'a mut ConstTracker,
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}
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impl<'a> LegalizeBuilder<'a> {
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fn new(
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sm: &'a ShaderModelInfo,
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alloc: &'a mut SSAValueAllocator,
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const_tracker: &'a mut ConstTracker,
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) -> Self {
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LegalizeBuilder {
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b: SSAInstrBuilder::new(sm, alloc),
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const_tracker,
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}
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}
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pub fn into_vec(self) -> Vec<Instr> {
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self.b.into_vec()
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}
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#[allow(dead_code)]
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pub fn into_mapped_instrs(self) -> MappedInstrs {
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self.b.into_mapped_instrs()
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}
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}
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impl<'a> Builder for LegalizeBuilder<'a> {
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fn push_instr(&mut self, instr: Instr) -> &mut Instr {
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self.b.push_instr(instr)
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}
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fn sm(&self) -> u8 {
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self.b.sm()
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}
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fn copy_to(&mut self, dst: Dst, mut src: Src) {
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if let Some(ssa_ref) = src.as_ssa() {
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if let &[ssa_value] = &ssa_ref[..] {
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if let Some(new_src) = self.const_tracker.get(&ssa_value) {
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src = new_src.clone().into();
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}
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}
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};
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self.b.copy_to(dst, src);
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}
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}
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impl<'a> SSABuilder for LegalizeBuilder<'a> {
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fn alloc_ssa(&mut self, file: RegFile) -> SSAValue {
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self.b.alloc_ssa(file)
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}
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fn alloc_ssa_vec(&mut self, file: RegFile, comps: u8) -> SSARef {
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self.b.alloc_ssa_vec(file, comps)
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}
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}
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impl LegalizeBuildHelpers for LegalizeBuilder<'_> {}
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fn legalize_instr(
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sm: &ShaderModelInfo,
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b: &mut LegalizeBuilder,
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bl: &impl BlockLiveness,
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block_uniform: bool,
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pinned: &FxHashSet<SSARef>,
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ip: usize,
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instr: &mut Instr,
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) {
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// Handle a few no-op cases up-front
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match &instr.op {
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Op::Annotate(_) => {
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// OpAnnotate does nothing. There's nothing to legalize.
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return;
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}
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Op::Undef(_)
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| Op::PhiSrcs(_)
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| Op::PhiDsts(_)
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| Op::Pin(_)
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| Op::Unpin(_)
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| Op::RegOut(_) => {
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// These are implemented by RA and can take pretty much anything
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// you can throw at them.
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debug_assert!(instr.pred.is_true());
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return;
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}
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Op::Copy(_) => {
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// OpCopy is implemented in a lowering pass and can handle anything
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return;
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}
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Op::SrcBar(_) => {
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// This is turned into a nop by calc_instr_deps
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return;
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}
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Op::Swap(_) | Op::ParCopy(_) => {
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// These are generated by RA and should not exist yet
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panic!("Unsupported instruction");
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}
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_ => (),
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}
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|
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if !instr.is_uniform() {
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b.copy_pred_if_upred(&mut instr.pred);
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}
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let src_types = instr.src_types();
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for (i, src) in instr.srcs_mut().iter_mut().enumerate() {
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if matches!(src.src_ref, SrcRef::Imm32(_)) {
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// Fold modifiers on Imm32 sources whenever possible. Not all
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// instructions suppport modifiers and immediates at the same time.
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// But leave Zero sources alone as we don't want to make things
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// immediates that could just be rZ.
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if let Some(u) = src.as_u32(src_types[i]) {
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*src = u.into();
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}
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}
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b.copy_src_if_not_same_file(src);
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|
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if !block_uniform {
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// In non-uniform control-flow, we can't collect uniform vectors so
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// we need to insert copies to warp regs which we can collect.
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|
match &mut src.src_ref {
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SrcRef::SSA(vec) => {
|
|
if vec.is_uniform()
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&& vec.comps() > 1
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&& !pinned.contains(vec)
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{
|
|
b.copy_ssa_ref(vec, vec.file().to_warp());
|
|
}
|
|
}
|
|
SrcRef::CBuf(CBufRef {
|
|
buf: CBuf::BindlessSSA(handle),
|
|
..
|
|
}) => assert!(pinned.contains(&SSARef::new(handle))),
|
|
_ => (),
|
|
}
|
|
}
|
|
}
|
|
|
|
// OpBreak and OpBSsy impose additional RA constraints
|
|
let mut legalize_break_bssy = |bar_in: &mut Src, bar_out: &mut Dst| {
|
|
let bar_in_ssa = bar_in.src_ref.as_ssa().unwrap();
|
|
if !bar_out.is_none() && bl.is_live_after_ip(&bar_in_ssa[0], ip) {
|
|
let gpr = b.bmov_to_gpr(bar_in.clone());
|
|
let tmp = b.bmov_to_bar(gpr.into());
|
|
*bar_in = tmp.into();
|
|
}
|
|
};
|
|
match &mut instr.op {
|
|
Op::Break(op) => legalize_break_bssy(&mut op.bar_in, &mut op.bar_out),
|
|
Op::BSSy(op) => legalize_break_bssy(&mut op.bar_in, &mut op.bar_out),
|
|
_ => (),
|
|
}
|
|
|
|
sm.legalize_op(b, &mut instr.op);
|
|
|
|
let mut vec_src_map: FxHashMap<SSARef, SSARef> = Default::default();
|
|
let mut vec_comps: FxHashSet<_> = Default::default();
|
|
for src in instr.srcs_mut() {
|
|
if let SrcRef::SSA(vec) = &src.src_ref {
|
|
if vec.comps() == 1 {
|
|
continue;
|
|
}
|
|
|
|
// If the same vector shows up twice in one instruction, that's
|
|
// okay. Just make it look the same as the previous source we
|
|
// fixed up.
|
|
if let Some(new_vec) = vec_src_map.get(vec) {
|
|
src.src_ref = new_vec.clone().into();
|
|
continue;
|
|
}
|
|
|
|
let mut new_vec = vec.clone();
|
|
for c in 0..vec.comps() {
|
|
let ssa = vec[usize::from(c)];
|
|
// If the same SSA value shows up in multiple non-identical
|
|
// vector sources or as multiple components in the same
|
|
// source, we need to make a copy so it can get assigned to
|
|
// multiple different registers.
|
|
if vec_comps.contains(&ssa) {
|
|
let copy = b.alloc_ssa(ssa.file());
|
|
b.copy_to(copy.into(), ssa.into());
|
|
new_vec[usize::from(c)] = copy;
|
|
} else {
|
|
vec_comps.insert(ssa);
|
|
}
|
|
}
|
|
|
|
vec_src_map.insert(vec.clone(), new_vec.clone());
|
|
src.src_ref = new_vec.into();
|
|
}
|
|
}
|
|
}
|
|
|
|
impl Shader<'_> {
|
|
pub fn legalize(&mut self) {
|
|
let sm = self.sm;
|
|
for f in &mut self.functions {
|
|
let live = SimpleLiveness::for_function(f);
|
|
let mut pinned: FxHashSet<_> = Default::default();
|
|
let mut const_tracker = ConstTracker::new();
|
|
|
|
for (bi, b) in f.blocks.iter_mut().enumerate() {
|
|
let bl = live.block_live(bi);
|
|
let bu = b.uniform;
|
|
|
|
let mut instrs = Vec::new();
|
|
for (ip, mut instr) in b.instrs.drain(..).enumerate() {
|
|
match &instr.op {
|
|
Op::Pin(pin) => {
|
|
if let Dst::SSA(ssa) = &pin.dst {
|
|
pinned.insert(ssa.clone());
|
|
}
|
|
}
|
|
Op::Copy(copy) => {
|
|
const_tracker.add_copy(copy);
|
|
}
|
|
_ => (),
|
|
}
|
|
|
|
let mut b = LegalizeBuilder::new(
|
|
sm,
|
|
&mut f.ssa_alloc,
|
|
&mut const_tracker,
|
|
);
|
|
legalize_instr(sm, &mut b, bl, bu, &pinned, ip, &mut instr);
|
|
b.push_instr(instr);
|
|
instrs.append(&mut b.into_vec());
|
|
}
|
|
b.instrs = instrs;
|
|
}
|
|
}
|
|
}
|
|
}
|