commit 0bbe6b34e64751bc6f779829a9e5038cb0924844 Author: elwrcl Date: Sun Aug 23 04:59:41 2026 +0300 first commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..02accb4 --- /dev/null +++ b/.gitignore @@ -0,0 +1,18 @@ +/.icd-vendors +/ivb-test/result/ +/cts/cts-run-* +/media/* +!/media/.gitkeep +*.aub +*.qpa +*.h264 +*.y4m +*.mp4 +*.o +*.log +__pycache__/ +*.pyc +/cts-run-* +/hangs/ +/.gcroots/ +/cts-chunked/ diff --git a/cts/cts-exclude-gen7.txt b/cts/cts-exclude-gen7.txt new file mode 100644 index 0000000..65e2a0d --- /dev/null +++ b/cts/cts-exclude-gen7.txt @@ -0,0 +1,13219 @@ +dEQP-VK.renderpasses.dynamic_rendering.complete_secondary_cmd_buff.suballocation.multisample.d24_unorm_s8_uint.samples_8 +dEQP-VK.renderpasses.dynamic_rendering.complete_secondary_cmd_buff.suballocation.multisample.d32_sfloat_s8_uint.samples_8 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+dEQP-VK.video.encode.av1.720x480_10le_420.idr_p_b3_13_15.qindex128_tiling_4x4_rc_disabled_lf_lr_cdef +dEQP-VK.video.encode.av1.720x480_10le_420.idr_p_b3_13_15.qindex128_tiling_4x4_rc_disabled_lf_lr_cdef_layered_dpb +dEQP-VK.video.encode.av1.720x480_10le_420.idr_p_b3_13_15.qindex128_tiling_4x4_rc_disabled_lf_lr_layered_dpb +dEQP-VK.video.encode.av1.720x480_10le_420.idr_p_b3_13_15.qindex128_tiling_4x4_rc_disabled_lr +dEQP-VK.video.encode.av1.720x480_10le_420.idr_p_b3_13_15.qindex128_tiling_4x4_rc_disabled_lr_cdef +dEQP-VK.video.encode.av1.720x480_10le_420.idr_p_b3_13_15.qindex128_tiling_4x4_rc_disabled_lr_cdef_layered_dpb +dEQP-VK.video.encode.av1.720x480_10le_420.idr_p_b3_13_15.qindex128_tiling_4x4_rc_disabled_lr_layered_dpb +dEQP-VK.video.encode.av1.720x480_10le_420.idr_p_b3_13_15.qindex192_rc_disabled +dEQP-VK.video.encode.av1.720x480_10le_420.idr_p_b3_13_15.qindex192_rc_disabled_cdef +dEQP-VK.video.encode.av1.720x480_10le_420.idr_p_b3_13_15.qindex192_rc_disabled_cdef_layered_dpb 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+dEQP-VK.video.synchronization.decode_vp9.basic.timeline_semaphore.one_queue +dEQP-VK.video.synchronization.decode_vp9.basic.timeline_semaphore.two_threads +dEQP-VK.video.synchronization.decode_vp9.basic.timeline_semaphore.wait_for_all_current_value +dEQP-VK.video.synchronization.decode_vp9.basic.timeline_semaphore.wait_for_all_lesser_value +dEQP-VK.video.synchronization.decode_vp9.basic.timeline_semaphore.wait_for_any_current_value +dEQP-VK.video.synchronization.decode_vp9.basic.timeline_semaphore.wait_for_any_lesser_value +dEQP-VK.video.synchronization.encode_av1.basic.binary_semaphore.chain +dEQP-VK.video.synchronization.encode_av1.basic.binary_semaphore.multi_queue +dEQP-VK.video.synchronization.encode_av1.basic.binary_semaphore.multi_queue_typed +dEQP-VK.video.synchronization.encode_av1.basic.binary_semaphore.one_queue +dEQP-VK.video.synchronization.encode_av1.basic.binary_semaphore.one_queue_typed +dEQP-VK.video.synchronization.encode_av1.basic.event.device_set_reset +dEQP-VK.video.synchronization.encode_av1.basic.event.host_set_reset +dEQP-VK.video.synchronization.encode_av1.basic.event.multi_submit_multi_command_buffer +dEQP-VK.video.synchronization.encode_av1.basic.event.single_submit_multi_command_buffer +dEQP-VK.video.synchronization.encode_av1.basic.fence.empty_submit +dEQP-VK.video.synchronization.encode_av1.basic.fence.multi +dEQP-VK.video.synchronization.encode_av1.basic.fence.multiple_signaled +dEQP-VK.video.synchronization.encode_av1.basic.fence.multi_waitall_false +dEQP-VK.video.synchronization.encode_av1.basic.fence.one +dEQP-VK.video.synchronization.encode_av1.basic.fence.one_signaled +dEQP-VK.video.synchronization.encode_av1.basic.timeline_semaphore.chain +dEQP-VK.video.synchronization.encode_av1.basic.timeline_semaphore.multi_queue +dEQP-VK.video.synchronization.encode_av1.basic.timeline_semaphore.one_queue +dEQP-VK.video.synchronization.encode_av1.basic.timeline_semaphore.two_threads +dEQP-VK.video.synchronization.encode_av1.basic.timeline_semaphore.wait_for_all_current_value +dEQP-VK.video.synchronization.encode_av1.basic.timeline_semaphore.wait_for_all_lesser_value +dEQP-VK.video.synchronization.encode_av1.basic.timeline_semaphore.wait_for_any_current_value +dEQP-VK.video.synchronization.encode_av1.basic.timeline_semaphore.wait_for_any_lesser_value +dEQP-VK.video.synchronization.encode_h264.basic.binary_semaphore.chain +dEQP-VK.video.synchronization.encode_h264.basic.binary_semaphore.multi_queue +dEQP-VK.video.synchronization.encode_h264.basic.binary_semaphore.multi_queue_typed +dEQP-VK.video.synchronization.encode_h264.basic.binary_semaphore.one_queue +dEQP-VK.video.synchronization.encode_h264.basic.binary_semaphore.one_queue_typed +dEQP-VK.video.synchronization.encode_h264.basic.event.device_set_reset +dEQP-VK.video.synchronization.encode_h264.basic.event.host_set_reset +dEQP-VK.video.synchronization.encode_h264.basic.event.multi_submit_multi_command_buffer +dEQP-VK.video.synchronization.encode_h264.basic.event.single_submit_multi_command_buffer +dEQP-VK.video.synchronization.encode_h264.basic.fence.empty_submit +dEQP-VK.video.synchronization.encode_h264.basic.fence.multi +dEQP-VK.video.synchronization.encode_h264.basic.fence.multiple_signaled +dEQP-VK.video.synchronization.encode_h264.basic.fence.multi_waitall_false +dEQP-VK.video.synchronization.encode_h264.basic.fence.one +dEQP-VK.video.synchronization.encode_h264.basic.fence.one_signaled +dEQP-VK.video.synchronization.encode_h264.basic.timeline_semaphore.chain +dEQP-VK.video.synchronization.encode_h264.basic.timeline_semaphore.multi_queue +dEQP-VK.video.synchronization.encode_h264.basic.timeline_semaphore.one_queue +dEQP-VK.video.synchronization.encode_h264.basic.timeline_semaphore.two_threads +dEQP-VK.video.synchronization.encode_h264.basic.timeline_semaphore.wait_for_all_current_value +dEQP-VK.video.synchronization.encode_h264.basic.timeline_semaphore.wait_for_all_lesser_value +dEQP-VK.video.synchronization.encode_h264.basic.timeline_semaphore.wait_for_any_current_value +dEQP-VK.video.synchronization.encode_h264.basic.timeline_semaphore.wait_for_any_lesser_value +dEQP-VK.video.synchronization.encode_h265.basic.binary_semaphore.chain +dEQP-VK.video.synchronization.encode_h265.basic.binary_semaphore.multi_queue +dEQP-VK.video.synchronization.encode_h265.basic.binary_semaphore.multi_queue_typed +dEQP-VK.video.synchronization.encode_h265.basic.binary_semaphore.one_queue +dEQP-VK.video.synchronization.encode_h265.basic.binary_semaphore.one_queue_typed +dEQP-VK.video.synchronization.encode_h265.basic.event.device_set_reset +dEQP-VK.video.synchronization.encode_h265.basic.event.host_set_reset +dEQP-VK.video.synchronization.encode_h265.basic.event.multi_submit_multi_command_buffer +dEQP-VK.video.synchronization.encode_h265.basic.event.single_submit_multi_command_buffer +dEQP-VK.video.synchronization.encode_h265.basic.fence.empty_submit +dEQP-VK.video.synchronization.encode_h265.basic.fence.multi +dEQP-VK.video.synchronization.encode_h265.basic.fence.multiple_signaled +dEQP-VK.video.synchronization.encode_h265.basic.fence.multi_waitall_false +dEQP-VK.video.synchronization.encode_h265.basic.fence.one +dEQP-VK.video.synchronization.encode_h265.basic.fence.one_signaled +dEQP-VK.video.synchronization.encode_h265.basic.timeline_semaphore.chain +dEQP-VK.video.synchronization.encode_h265.basic.timeline_semaphore.multi_queue +dEQP-VK.video.synchronization.encode_h265.basic.timeline_semaphore.one_queue +dEQP-VK.video.synchronization.encode_h265.basic.timeline_semaphore.two_threads +dEQP-VK.video.synchronization.encode_h265.basic.timeline_semaphore.wait_for_all_current_value +dEQP-VK.video.synchronization.encode_h265.basic.timeline_semaphore.wait_for_all_lesser_value +dEQP-VK.video.synchronization.encode_h265.basic.timeline_semaphore.wait_for_any_current_value +dEQP-VK.video.synchronization.encode_h265.basic.timeline_semaphore.wait_for_any_lesser_value diff --git a/cts/hang_watch.py b/cts/hang_watch.py new file mode 100644 index 0000000..2b88821 --- /dev/null +++ b/cts/hang_watch.py @@ -0,0 +1,104 @@ +#!/usr/bin/env python3 +import glob +import os +import subprocess +import sys +import time +from datetime import datetime +from pathlib import Path + + +def now_iso(): + return datetime.now().astimezone().isoformat(timespec="seconds") + + +def meminfo(): + d = {} + with open("/proc/meminfo") as f: + for line in f: + k, v = line.split(":", 1) + d[k.strip()] = int(v.split()[0]) + return d + + +def main(): + outdir = Path(sys.argv[1]) if len(sys.argv) > 1 else Path.cwd() / "hangs" + poll = int(sys.argv[2]) if len(sys.argv) > 2 else 10 + + err = "" + for c in sorted(glob.glob("/sys/class/drm/card*/error")): + err = c + break + + if not err: + print("no /sys/class/drm/card*/error — is i915 loaded?", file=sys.stderr) + elif not os.access(err, os.R_OK): + print(f"cannot read {err} — rerun with sudo for GPU hang capture", file=sys.stderr) + err = "" + + outdir.mkdir(parents=True, exist_ok=True) + hangs_txt = outdir / "hangs.txt" + mem_log = outdir / "mem.log" + + print(f"watching {err or '(memory only)'} every {poll}s -> {outdir}") + with open(hangs_txt, "a") as f: + f.write(f"{now_iso()} watch started\n") + + n = 0 + while True: + if err and os.path.getsize(err) > 0: + n += 1 + stamp = datetime.now().strftime("%Y%m%d-%H%M%S") + hang_f = outdir / f"hang-{stamp}.txt" + data = open(err, "rb").read() + hang_f.write_bytes(data) + + with open(hangs_txt, "a") as hf: + for line in data.decode(errors="replace").splitlines(): + if line.startswith(("GPU HANG", "Kernel", "Time")): + hf.write(line + "\n") + break + msg = f"{now_iso()} hang #{n} -> {hang_f} ({hang_f.stat().st_size} B)" + hf.write(msg + "\n") + print(msg) + + dmesg = subprocess.run(["dmesg"], capture_output=True, text=True).stdout + matched = [l for l in dmesg.splitlines() + if any(k.lower() in l.lower() for k in ("GPU HANG", "reset", "hangcheck"))] + (outdir / f"dmesg-{stamp}.txt").write_text("\n".join(matched[-20:]) + ("\n" if matched else "")) + + with open(err, "w") as ef: + ef.write("1") + + mi = meminfo() + avail = mi.get("MemAvailable", 0) + swtot = mi.get("SwapTotal", 0) + swfree = mi.get("SwapFree", 0) + sunrecl = mi.get("SUnreclaim", 0) + ptbl = mi.get("PageTables", 0) + + ps = subprocess.run(["ps", "-eo", "rss,comm", "--sort=-rss", "--no-headers"], + capture_output=True, text=True).stdout + top3 = [] + for line in ps.splitlines()[:3]: + parts = line.split(None, 1) + if len(parts) == 2: + rss, comm = parts + top3.append(f"{comm}:{int(rss) // 1024}M") + top3_str = " ".join(top3) + (" " if top3 else "") + + line = (f"{now_iso()} avail={avail // 1024}M swapused={(swtot - swfree) // 1024}M " + f"sunreclaim={sunrecl // 1024}M pagetables={ptbl // 1024}M {top3_str}\n") + with open(mem_log, "a") as mf: + mf.write(line) + try: + subprocess.run(["sync", "-d", str(mem_log)], check=True, + stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL) + except subprocess.CalledProcessError: + subprocess.run(["sync"]) + + time.sleep(poll) + + +if __name__ == "__main__": + main() diff --git a/cts/mem_guard.py b/cts/mem_guard.py new file mode 100644 index 0000000..530ea51 --- /dev/null +++ b/cts/mem_guard.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 +import os +import subprocess +import sys +import time +from datetime import datetime + + +def now_iso(): + return datetime.now().astimezone().isoformat(timespec="seconds") + + +def mem_available_mb(): + with open("/proc/meminfo") as f: + for line in f: + if line.startswith("MemAvailable:"): + return int(line.split()[1]) // 1024 + return None + + +def proc_alive(name): + return subprocess.run(["pgrep", "-x", name], + stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL).returncode == 0 + + +def main(): + threshold = int(sys.argv[1]) if len(sys.argv) > 1 else 1500 + proc = sys.argv[2] if len(sys.argv) > 2 else "deqp-vk" + poll = int(sys.argv[3]) if len(sys.argv) > 3 else 3 + + print(f"guarding: kill {proc} when MemAvailable < {threshold}M (poll {poll}s)") + + while True: + avail = mem_available_mb() + if avail is not None and avail < threshold: + print(f"{now_iso()} avail={avail}M below {threshold}M — terminating {proc}") + subprocess.run(["pkill", "-TERM", "-x", proc]) + time.sleep(10) + if proc_alive(proc): + print("still alive, SIGKILL") + subprocess.run(["pkill", "-KILL", "-x", proc]) + + outdir = os.environ.get("OUTDIR", ".") + with open(os.path.join(outdir, "mem-guard.log"), "a") as f: + f.write(f"{now_iso()} killed {proc} at avail={avail}M\n") + subprocess.run(["sync"]) + sys.exit(1) + + time.sleep(poll) + + +if __name__ == "__main__": + main() diff --git a/cts/run_chunked.py b/cts/run_chunked.py new file mode 100644 index 0000000..56325c6 --- /dev/null +++ b/cts/run_chunked.py @@ -0,0 +1,240 @@ +#!/usr/bin/env python3 +import collections +import glob +import os +import re +import subprocess +import sys +import time +from datetime import datetime +from pathlib import Path + + +def now_iso(): + return datetime.now().astimezone().isoformat(timespec="seconds") + + +def wc_l(path): + if not os.path.exists(path): + return 0 + with open(path, "rb") as f: + return sum(1 for _ in f) + + +def read_lines(path): + if not os.path.exists(path): + return [] + with open(path) as f: + return [l.rstrip("\n") for l in f if l.strip()] + + +def write_lines(path, lines): + with open(path, "w") as f: + for l in lines: + f.write(l + "\n") + + +def begin_test_case_names(qpa_path): + names = set() + if not os.path.exists(qpa_path): + return names + txt = open(qpa_path, errors="replace").read() + for line in txt.splitlines(): + if line.startswith("#beginTestCaseResult "): + names.add(line[len("#beginTestCaseResult "):].strip()) + return names + + +def main(): + lab_root = Path(os.environ.get("LAB_ROOT", Path(__file__).resolve().parent.parent)) + drivers_root = Path(os.environ.get("DRIVERS_ROOT", lab_root.parent)) + mesa_src = Path(os.environ.get("MESA_SRC", drivers_root / "intel-hard-graphics")) + mesa_build = Path(os.environ.get("MESA_BUILD", mesa_src / "build")) + cts_dir = Path(os.environ.get("CTS_DIR", mesa_src / "VK-GL-CTS/build-cts/external/vulkancts/modules/vulkan")) + cts_mustpass = Path(os.environ.get("CTS_MUSTPASS", mesa_src / "VK-GL-CTS/external/vulkancts/mustpass/main/vk-default")) + icd = Path(os.environ.get("VK_DRIVER_FILES", mesa_build / "src/intel/vulkan_hasvk/intel_hasvk13_devenv_icd.x86_64.json")) + exclude = Path(os.environ.get("EXCLUDE", lab_root / "cts/cts-exclude-gen7.txt")) + + scope = sys.argv[1] if len(sys.argv) > 1 else "mustpass" + chunk_size = int(sys.argv[2]) if len(sys.argv) > 2 else 100000 + pause = int(sys.argv[3]) if len(sys.argv) > 3 else 30 + outdir = Path(os.environ.get("OUTDIR", Path.cwd() / "cts-chunked")) + + stop_on_hang = os.environ.get("STOP_ON_HANG", "0") == "1" + max_hangs = int(os.environ.get("MAX_HANGS", "3")) + max_chunks = int(os.environ.get("MAX_CHUNKS", "3")) + max_subruns = int(os.environ.get("MAX_SUBRUNS", "40")) + hangs = 0 + + deqp = cts_dir / "deqp-vk" + for p in (deqp, icd): + if not p.exists(): + print(f"missing: {p}", file=sys.stderr) + sys.exit(1) + + outdir.mkdir(parents=True, exist_ok=True) + os.chdir(cts_dir) + + src_txt = outdir / "src.txt" + cases_txt = outdir / "cases.txt" + if not (src_txt.exists() and src_txt.stat().st_size > 0): + if scope == "all": + out = subprocess.run([str(deqp), "--deqp-runmode=stdout-caselist"], + capture_output=True, text=True).stdout + lines = [l[len("TEST: "):] for l in out.splitlines() if l.startswith("TEST: ")] + write_lines(src_txt, lines) + else: + lines = [] + for f in sorted(glob.glob(str(cts_mustpass / "*.txt"))): + lines.extend(l for l in read_lines(f) if l.startswith("dEQP-VK")) + write_lines(src_txt, lines) + + if exclude.exists() and exclude.stat().st_size > 0: + excl = set(read_lines(exclude)) + write_lines(cases_txt, [l for l in read_lines(src_txt) if l not in excl]) + else: + write_lines(cases_txt, read_lines(src_txt)) + + todo_txt = outdir / "todo.txt" + prev = sorted(glob.glob(str(outdir / "chunk-*.qpa"))) + if prev: + done = set() + for f in prev: + done |= begin_test_case_names(f) + done_txt = outdir / "done.txt" + write_lines(done_txt, sorted(done)) + cases = read_lines(cases_txt) + todo = [l for l in cases if l not in done] + write_lines(todo_txt, todo) + print(f"resume: {len(done)} recorded, {len(todo)} left") + else: + cases = read_lines(cases_txt) + write_lines(todo_txt, cases) + print(f"{len(cases)} cases to run") + + if not (todo_txt.exists() and todo_txt.stat().st_size > 0): + print("nothing left to run — summarising") + + todo = read_lines(todo_txt) + total = len(todo) + n = 0 + start = 1 + ran = 0 + rc = 0 + sub = 0 + + while todo and start <= total: + n += 1 + while glob.glob(str(outdir / f"chunk-{n}.*.qpa")): + n += 1 + + list_path = outdir / f"chunk-{n}.txt" + chunk_lines = todo[start - 1: start - 1 + chunk_size] + write_lines(list_path, chunk_lines) + if not chunk_lines: + break + + print(f"chunk {n}: {len(chunk_lines)} cases (from line {start} of {total})") + want = len(chunk_lines) + work_path = outdir / f"chunk-{n}.work" + write_lines(work_path, chunk_lines) + sub = 0 + + while work_path.exists() and work_path.stat().st_size > 0: + sub += 1 + if sub > max_subruns: + print(f" gave up after {max_subruns} subruns") + break + + qpa = outdir / f"chunk-{n}.{sub}.qpa" + log = outdir / f"chunk-{n}.{sub}.log" + env = dict(os.environ, VK_DRIVER_FILES=str(icd)) + with open(log, "w") as lf: + proc = subprocess.run( + [str(deqp), f"--deqp-caselist-file={work_path}", + f"--deqp-log-filename={qpa}", + "--deqp-log-images=disable", "--deqp-log-shader-sources=disable"], + stdout=lf, stderr=subprocess.STDOUT, env=env) + rc = proc.returncode + + work_lines = read_lines(work_path) + left = len(work_lines) + got = sum(1 for l in open(qpa, errors="replace").read().splitlines() + if l.startswith("#beginTestCaseResult")) if qpa.exists() else 0 + if got >= left: + break + + done_now = begin_test_case_names(qpa) + next_lines = [l for l in work_lines if l not in done_now] + if len(next_lines) == left: + culprit = work_lines[0] if work_lines else "" + with open(outdir / "crashers.txt", "a") as cf: + cf.write(f"{now_iso()} crashed before recording: {culprit}\n") + next_lines = work_lines[1:] + write_lines(work_path, next_lines) + print(f" subrun {sub}: rc={rc}, {got} done, {len(next_lines)} left — restarting") + time.sleep(pause) + + for suffix in (".work", ".work.done", ".work.next"): + p = outdir / f"chunk-{n}{suffix}" + if p.exists(): + p.unlink() + + done_n = 0 + bad_log = False + for f in sorted(glob.glob(str(outdir / f"chunk-{n}.*.qpa"))): + done_n += sum(1 for l in open(f, errors="replace").read().splitlines() + if l.startswith("#beginTestCaseResult")) + for f in sorted(glob.glob(str(outdir / f"chunk-{n}.*.log"))): + if "DeviceLost" in open(f, errors="replace").read(): + bad_log = True + print(f" rc={rc}, {done_n}/{want} results ({sub} subrun)") + + bad = done_n < want or bad_log + wait_s = pause + if bad: + hangs += 1 + with open(outdir / "hangs.txt", "a") as hf: + hf.write(f"{now_iso()} chunk {n} ended badly (rc={rc})\n") + if stop_on_hang: + print(" chunk ended badly — stopping (STOP_ON_HANG=1)") + print(" rerun the same command to continue from here") + break + wait_s = pause * 4 + print(f" chunk ended badly (#{hangs}) — cooling down {wait_s}s") + if max_hangs > 0 and hangs >= max_hangs: + print(f" {hangs} bad chunks — stopping (MAX_HANGS={max_hangs})") + break + + start += chunk_size + ran += 1 + if max_chunks > 0 and ran >= max_chunks and start <= total: + print() + print(f"{ran} chunks done this boot (MAX_CHUNKS={max_chunks}) — stopping here.") + print(f"REBOOT, then rerun the same command to continue from case {start}.") + break + if start <= total: + time.sleep(wait_s) + + res = {} + for f in sorted(glob.glob(str(outdir / "chunk-*.qpa"))): + txt = open(f, errors="replace").read() + for block in re.split(r"#beginTestCaseResult ", txt)[1:]: + name = block.split("\n", 1)[0].strip() + m = re.search(r'', block) + res[name] = m.group(1) if m else "Crash" + + counts = collections.Counter(res.values()) + print(f"\n{sum(counts.values())} results") + for k, v in counts.most_common(): + print(f" {k:16} {v}") + + with open(outdir / "failures.txt", "w") as fh: + for name, status in sorted(res.items()): + if status not in ("Pass", "NotSupported"): + fh.write(f"{status}\t{name}\n") + print(f"\nfailures -> {outdir}/failures.txt") + + +if __name__ == "__main__": + main() diff --git a/cts/run_cts.py b/cts/run_cts.py new file mode 100644 index 0000000..c3b1dc3 --- /dev/null +++ b/cts/run_cts.py @@ -0,0 +1,199 @@ +#!/usr/bin/env python3 +import collections +import glob +import os +import re +import subprocess +import sys +import threading +import time +from datetime import datetime +from pathlib import Path + + +def now_iso(): + return datetime.now().astimezone().isoformat(timespec="seconds") + + +def read_lines(path): + if not os.path.exists(path): + return [] + with open(path) as f: + return [l.rstrip("\n") for l in f if l.strip()] + + +def write_lines(path, lines): + with open(path, "w") as f: + for l in lines: + f.write(l + "\n") + + +def begin_test_case_names(qpa_path): + names = set() + if not os.path.exists(qpa_path): + return names + txt = open(qpa_path, errors="replace").read() + for line in txt.splitlines(): + if line.startswith("#beginTestCaseResult "): + names.add(line[len("#beginTestCaseResult "):].strip()) + return names + + +def last_begin_test_case_name(qpa_path): + last = None + if not os.path.exists(qpa_path): + return last + for line in open(qpa_path, errors="replace"): + if line.startswith("#beginTestCaseResult "): + last = line[len("#beginTestCaseResult "):].strip() + return last + + +def nproc(): + return os.cpu_count() or 1 + + +def main(): + lab_root = Path(os.environ.get("LAB_ROOT", Path(__file__).resolve().parent.parent)) + drivers_root = Path(os.environ.get("DRIVERS_ROOT", lab_root.parent)) + mesa_src = Path(os.environ.get("MESA_SRC", drivers_root / "intel-hard-graphics")) + mesa_build = Path(os.environ.get("MESA_BUILD", mesa_src / "build")) + cts_dir = Path(os.environ.get("CTS_DIR", mesa_src / "VK-GL-CTS/build-cts/external/vulkancts/modules/vulkan")) + cts_mustpass = Path(os.environ.get("CTS_MUSTPASS", mesa_src / "VK-GL-CTS/external/vulkancts/mustpass/main/vk-default")) + icd = Path(os.environ.get("VK_DRIVER_FILES", mesa_build / "src/intel/vulkan_hasvk/intel_hasvk13_devenv_icd.x86_64.json")) + exclude = lab_root / "cts/cts-exclude-gen7.txt" + + scope = sys.argv[1] if len(sys.argv) > 1 else "mustpass" + shards = int(sys.argv[2]) if len(sys.argv) > 2 else nproc() + cooldown = int(os.environ.get("COOLDOWN", "60")) + outdir = Path(os.environ.get( + "OUTDIR", Path.cwd() / f"cts-run-{datetime.now().strftime('%Y%m%d-%H%M%S')}")) + + deqp = cts_dir / "deqp-vk" + for p in (deqp, icd): + if not p.exists(): + print(f"missing: {p}", file=sys.stderr) + sys.exit(1) + + outdir.mkdir(parents=True, exist_ok=True) + os.chdir(cts_dir) + + cases_txt = outdir / "cases.txt" + if scope == "all": + out = subprocess.run([str(deqp), "--deqp-runmode=stdout-caselist"], + capture_output=True, text=True).stdout + lines = [l[len("TEST: "):] for l in out.splitlines() if l.startswith("TEST: ")] + src_txt = outdir / "all.txt" + write_lines(src_txt, lines) + else: + lines = [] + for f in sorted(glob.glob(str(cts_mustpass / "*.txt"))): + lines.extend(l for l in read_lines(f) if l.startswith("dEQP-VK")) + src_txt = outdir / "mustpass.txt" + write_lines(src_txt, lines) + + src_lines = read_lines(src_txt) + if exclude.exists() and exclude.stat().st_size > 0: + excl = set(read_lines(exclude)) + case_lines = [l for l in src_lines if l not in excl] + else: + case_lines = list(src_lines) + write_lines(cases_txt, case_lines) + print(f"{len(src_lines)} cases, {len(src_lines) - len(case_lines)} excluded, {len(case_lines)} to run") + + prev = sorted(glob.glob(str(outdir / "*.qpa"))) + sorted(glob.glob(str(outdir / "attempt-*/*.qpa"))) + if prev: + done = set() + for f in prev: + done |= begin_test_case_names(f) + done_txt = outdir / "done.txt" + write_lines(done_txt, sorted(done)) + if done: + case_lines = [l for l in read_lines(cases_txt) if l not in done] + write_lines(cases_txt, case_lines) + print(f"resume: {len(done)} already recorded, {len(case_lines)} left") + + n = 1 + while (outdir / f"attempt-{n}").exists(): + n += 1 + attempt_dir = outdir / f"attempt-{n}" + attempt_dir.mkdir(parents=True, exist_ok=True) + for f in list(glob.glob(str(outdir / "shard*.qpa"))) + list(glob.glob(str(outdir / "shard*.log"))): + os.rename(f, attempt_dir / os.path.basename(f)) + print(f"previous attempt parked in attempt-{n}/") + + case_lines = read_lines(cases_txt) + if not case_lines: + print("nothing left to run") + sys.exit(0) + + def run_shard(i): + list_path = outdir / f"shard{i}.txt" + shard_lines = [l for j, l in enumerate(case_lines) if (j + 1) % shards == i] + write_lines(list_path, shard_lines) + pass_n = 1 + + while list_path.exists() and list_path.stat().st_size > 0: + qpa = outdir / f"shard{i}.pass{pass_n}.qpa" + log = outdir / f"shard{i}.pass{pass_n}.log" + env = dict(os.environ, VK_DRIVER_FILES=str(icd)) + with open(log, "w") as lf: + subprocess.run( + [str(deqp), f"--deqp-caselist-file={list_path}", + f"--deqp-log-filename={qpa}", + "--deqp-log-images=disable", "--deqp-log-shader-sources=disable"], + stdout=lf, stderr=subprocess.STDOUT, env=env) + + log_text = open(log, errors="replace").read() if log.exists() else "" + if "ABORTED" not in log_text: + break + + last = last_begin_test_case_name(qpa) + if not last: + break + + print(f"shard {i} aborted at {last} -- cooling down {cooldown}s", file=sys.stderr) + with open(outdir / "aborted.txt", "a") as af: + af.write(last + "\n") + time.sleep(cooldown) + + shard_lines = read_lines(list_path) + seen = False + remaining = [] + for l in shard_lines: + if seen: + remaining.append(l) + if l == last: + seen = True + write_lines(list_path, remaining) + pass_n += 1 + + threads = [threading.Thread(target=run_shard, args=(i,)) for i in range(shards)] + for t in threads: + t.start() + for t in threads: + t.join() + + res = {} + for f in sorted(glob.glob(str(outdir / "shard*.qpa"))) + sorted(glob.glob(str(outdir / "attempt-*/shard*.qpa"))): + txt = open(f, errors="replace").read() + for block in re.split(r"#beginTestCaseResult ", txt)[1:]: + name = block.split("\n", 1)[0].strip() + m = re.search(r'', block) + if m: + res[name] = m.group(1) + + counts = collections.Counter(res.values()) + print(f"\n{sum(counts.values())} results") + for k, v in counts.most_common(): + print(f" {k:16} {v}") + + with open(outdir / "failures.txt", "w") as fh: + for name, status in sorted(res.items()): + if status not in ("Pass", "NotSupported"): + fh.write(f"{status}\t{name}\n") + print(f"\nfailures -> {outdir}/failures.txt") + + +if __name__ == "__main__": + main() diff --git a/cts/scan-2026-08-20/failures.txt b/cts/scan-2026-08-20/failures.txt new file mode 100644 index 0000000..d66f3d1 --- /dev/null +++ b/cts/scan-2026-08-20/failures.txt @@ -0,0 +1,23080 @@ +Fail dEQP-VK.api.buffer_view.access.uniform_texel_buffer.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.buffer_view.access.uniform_texel_buffer.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.buffer_view.access.uniform_texel_buffer.r16g16b16_sfloat +Fail dEQP-VK.api.copy_and_blit.copy_commands2.depth_stencil_msaa_copy.array_to_array.d24_unorm_s8_uint_S_4_bit +Fail dEQP-VK.api.copy_and_blit.copy_commands2.depth_stencil_msaa_copy.array_to_array.d24_unorm_s8_uint_S_8_bit +Fail dEQP-VK.api.copy_and_blit.copy_commands2.depth_stencil_msaa_copy.array_to_array.s8_uint_S_4_bit +Fail dEQP-VK.api.copy_and_blit.copy_commands2.depth_stencil_msaa_copy.array_to_array.s8_uint_S_8_bit +Fail dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.layer_copy_before_resolving.4_bit +Fail dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.layer_copy_before_resolving.8_bit +Fail dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.whole_array_image.4_bit +Fail dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.whole_array_image.8_bit +Fail dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.whole_array_image_one_region.4_bit +Fail dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.whole_array_image_one_region.4_bit_all_remaining_layers +Fail dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.whole_array_image_one_region.4_bit_not_all_remaining_layers +Fail dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.whole_array_image_one_region.8_bit +Fail dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.whole_array_image_one_region.8_bit_all_remaining_layers +Fail dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.whole_array_image_one_region.8_bit_not_all_remaining_layers +Fail dEQP-VK.api.copy_and_blit.core.depth_stencil_msaa_copy.array_to_array.d24_unorm_s8_uint_S_4_bit +Fail dEQP-VK.api.copy_and_blit.core.depth_stencil_msaa_copy.array_to_array.d24_unorm_s8_uint_S_4_bit_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.depth_stencil_msaa_copy.array_to_array.d24_unorm_s8_uint_S_8_bit +Fail dEQP-VK.api.copy_and_blit.core.depth_stencil_msaa_copy.array_to_array.d24_unorm_s8_uint_S_8_bit_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.depth_stencil_msaa_copy.array_to_array.s8_uint_S_4_bit +Fail dEQP-VK.api.copy_and_blit.core.depth_stencil_msaa_copy.array_to_array.s8_uint_S_4_bit_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.depth_stencil_msaa_copy.array_to_array.s8_uint_S_8_bit +Fail dEQP-VK.api.copy_and_blit.core.depth_stencil_msaa_copy.array_to_array.s8_uint_S_8_bit_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.layer_copy_before_resolving.4_bit +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.layer_copy_before_resolving.4_bit_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.layer_copy_before_resolving.8_bit +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.layer_copy_before_resolving.8_bit_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image.4_bit +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image.4_bit_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image.8_bit +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image.8_bit_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.4_bit +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.4_bit_all_remaining_layers +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.4_bit_all_remaining_layers_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.4_bit_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.4_bit_not_all_remaining_layers +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.4_bit_not_all_remaining_layers_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.8_bit +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.8_bit_all_remaining_layers +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.8_bit_all_remaining_layers_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.8_bit_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.8_bit_not_all_remaining_layers +Fail dEQP-VK.api.copy_and_blit.core.resolve_image.whole_array_image_one_region.8_bit_not_all_remaining_layers_bind_offset +Fail dEQP-VK.api.copy_and_blit.core.use_after_copy.b5g6r5_unorm_pack16.general.32x32x2_img2img_msaa +Fail dEQP-VK.api.copy_and_blit.core.use_after_copy.b5g6r5_unorm_pack16.general.32x32x2_regions_img2img_msaa +Fail dEQP-VK.api.copy_and_blit.core.use_after_copy.b5g6r5_unorm_pack16.transfer_dst_optimal.1024x1024x2_color_att_flag_img2img_msaa +Fail dEQP-VK.api.copy_and_blit.core.use_after_copy.b5g6r5_unorm_pack16.transfer_dst_optimal.1024x1024x2_regions_color_att_flag_img2img_msaa +Fail dEQP-VK.api.copy_and_blit.core.use_after_copy.b5g6r5_unorm_pack16.transfer_dst_optimal.32x32x2_img2img_msaa +Fail dEQP-VK.api.copy_and_blit.core.use_after_copy.b5g6r5_unorm_pack16.transfer_dst_optimal.32x32x2_regions_img2img_msaa +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.depth_stencil_msaa_copy.array_to_array.d24_unorm_s8_uint_S_4_bit +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.depth_stencil_msaa_copy.array_to_array.d24_unorm_s8_uint_S_8_bit +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.depth_stencil_msaa_copy.array_to_array.s8_uint_S_4_bit +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.depth_stencil_msaa_copy.array_to_array.s8_uint_S_8_bit +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.layer_copy_before_resolving.4_bit +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.layer_copy_before_resolving.8_bit +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image.4_bit +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image.8_bit +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image_one_region.4_bit +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image_one_region.4_bit_all_remaining_layers +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image_one_region.4_bit_not_all_remaining_layers +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image_one_region.8_bit +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image_one_region.8_bit_all_remaining_layers +Fail dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_array_image_one_region.8_bit_not_all_remaining_layers +Fail dEQP-VK.api.driver_properties.conformance_version +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.cube_layers.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.cube_layers.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_1x33 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_200x180_sample_count_4 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_200x180_sample_count_8 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_64x11_sample_count_4 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_64x11_sample_count_8 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_1x33 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_200x180_sample_count_4 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_200x180_sample_count_8 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_64x11_sample_count_4 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_64x11_sample_count_8 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_1x33 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_200x180_sample_count_4 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_200x180_sample_count_8 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_64x11_sample_count_4 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_64x11_sample_count_8 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_1x33 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_200x180_sample_count_4 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_200x180_sample_count_8 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_64x11_sample_count_4 +Fail dEQP-VK.api.image_clearing.core.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_64x11_sample_count_8 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.cube_layers.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.cube_layers.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.single_layer.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.single_layer.b5g6r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.single_layer.b5g6r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.core.partial_clear_color_attachment.single_layer.b5g6r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.cube_layers.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.cube_layers.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_1x33 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_200x180_sample_count_4 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_200x180_sample_count_8 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_64x11_sample_count_4 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_64x11_sample_count_8 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_1x33 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_200x180_sample_count_4 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_200x180_sample_count_8 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_64x11_sample_count_4 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_64x11_sample_count_8 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_1x33 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_200x180_sample_count_4 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_200x180_sample_count_8 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_64x11_sample_count_4 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_64x11_sample_count_8 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_1x33 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_200x180_sample_count_4 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_200x180_sample_count_8 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_64x11_sample_count_4 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_attachment.single_layer.b5g6r5_unorm_pack16_64x11_sample_count_8 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.cube_layers.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.cube_layers.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.multiple_layers.a1b5g5r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.multiple_layers.b5g6r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.single_layer.a1b5g5r5_unorm_pack16_64x11 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.single_layer.b5g6r5_unorm_pack16 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.single_layer.b5g6r5_unorm_pack16_200x180 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.single_layer.b5g6r5_unorm_pack16_33x128 +Fail dEQP-VK.api.image_clearing.dedicated_allocation.partial_clear_color_attachment.single_layer.b5g6r5_unorm_pack16_64x11 +QualityWarning dEQP-VK.api.object_management.alloc_callback_fail.descriptor_set_layout_empty +QualityWarning dEQP-VK.api.object_management.alloc_callback_fail.descriptor_set_layout_single +Fail dEQP-VK.api.object_management.alloc_callback_fail.graphics_pipeline +Fail dEQP-VK.api.object_management.alloc_callback_fail_multiple.graphics_pipeline +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.mutable_source.host_only_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.mutable_source.host_only_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.mutable_source.host_only_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.mutable_source.normal_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.mutable_source.normal_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.mutable_source.normal_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.nonmutable_source.host_only_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.nonmutable_source.host_only_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.nonmutable_source.host_only_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.nonmutable_source.normal_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.nonmutable_source.normal_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_copy.nonmutable_source.normal_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_write.no_source.no_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_write.no_source.no_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.combined_image_sampler_input_attachment.update_write.no_source.no_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.mutable_source.host_only_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.mutable_source.host_only_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.mutable_source.host_only_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.mutable_source.normal_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.mutable_source.normal_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.mutable_source.normal_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.nonmutable_source.host_only_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.nonmutable_source.host_only_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.nonmutable_source.host_only_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.nonmutable_source.normal_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.nonmutable_source.normal_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_copy.nonmutable_source.normal_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_write.no_source.no_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_write.no_source.no_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_combined_image_sampler.update_write.no_source.no_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.mutable_source.host_only_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.mutable_source.host_only_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.mutable_source.host_only_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.mutable_source.normal_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.mutable_source.normal_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.mutable_source.normal_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.nonmutable_source.host_only_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.nonmutable_source.host_only_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.nonmutable_source.host_only_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.nonmutable_source.normal_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.nonmutable_source.normal_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_copy.nonmutable_source.normal_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_write.no_source.no_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_write.no_source.no_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.input_attachment_sampled_image.update_write.no_source.no_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.mutable_source.host_only_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.mutable_source.host_only_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.mutable_source.host_only_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.mutable_source.normal_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.mutable_source.normal_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.mutable_source.normal_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.nonmutable_source.host_only_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.nonmutable_source.host_only_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.nonmutable_source.host_only_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.nonmutable_source.normal_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.nonmutable_source.normal_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_copy.nonmutable_source.normal_source.pool_same_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_write.no_source.no_source.pool_expand_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_write.no_source.no_source.pool_no_types.pre_update.no_array.frag +Fail dEQP-VK.binding_model.mutable_descriptor.single.switches.sampled_image_input_attachment.update_write.no_source.no_source.pool_same_types.pre_update.no_array.frag +Crash dEQP-VK.binding_model.shader_access.secondary_cmd_buf.bind2.with_template.combined_image_sampler_mutable.no_access.multiple_descriptor_sets.multiple_discontiguous_descriptors.2d +DeviceLost dEQP-VK.compute.pipeline.basic.empty_workgroup_all +Fail dEQP-VK.conditional_rendering.transform_feedback.draw +Fail dEQP-VK.conditional_rendering.transform_feedback.draw_indexed +Fail dEQP-VK.conditional_rendering.transform_feedback.draw_indexed_indirect +Fail dEQP-VK.conditional_rendering.transform_feedback.draw_indexed_indirect_count +Fail dEQP-VK.conditional_rendering.transform_feedback.draw_indirect +Fail dEQP-VK.conditional_rendering.transform_feedback.draw_indirect_count +Fail dEQP-VK.conditional_rendering.transform_feedback.draw_multi_ext +Fail dEQP-VK.conditional_rendering.transform_feedback.draw_multi_indexed_ext +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_line_list_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.draw_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.draw_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.draw_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_line_list_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.dynamic_state_draw_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.dynamic_state_draw_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.dynamic_rendering.partial_secondary_cmd_buff.instanced.dynamic_state_draw_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_line_list_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_line_strip_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_line_strip_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_point_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_point_list_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_strip_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_strip_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indirect_vk_primitive_topology_line_strip_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indirect_vk_primitive_topology_point_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.draw_indirect_vk_primitive_topology_triangle_strip_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_line_list_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_line_strip_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_line_strip_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_point_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_point_list_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_strip_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_strip_multiview_maintenance_5 +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indirect_vk_primitive_topology_line_strip_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indirect_vk_primitive_topology_point_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.instanced.dynamic_state_draw_indirect_vk_primitive_topology_triangle_strip_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_line_list_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_line_strip_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_line_strip_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_point_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_point_list_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_strip_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indexed_indirect_vk_primitive_topology_triangle_strip_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.draw_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indirect_vk_primitive_topology_line_strip_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indirect_vk_primitive_topology_point_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.draw_indirect_vk_primitive_topology_triangle_strip_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_line_list_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_line_strip_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_line_strip_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_point_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_point_list_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_fan_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_list_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_strip_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indexed_indirect_vk_primitive_topology_triangle_strip_multiview_maintenance_5 +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indirect_vk_primitive_topology_line_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indirect_vk_primitive_topology_line_strip_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indirect_vk_primitive_topology_point_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indirect_vk_primitive_topology_triangle_fan_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indirect_vk_primitive_topology_triangle_list_multiview +Fail dEQP-VK.draw.renderpass.instanced.dynamic_state_draw_indirect_vk_primitive_topology_triangle_strip_multiview +QualityWarning dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_samples_4 +QualityWarning dEQP-VK.fragment_operations.early_fragment.sample_count_early_fragment_tests_depth_samples_8 +Fail dEQP-VK.glsl.builtin.precision.cos.highp.scalar +Fail dEQP-VK.glsl.builtin.precision.cos.highp.vec2 +Fail dEQP-VK.glsl.builtin.precision.cos.highp.vec3 +Fail dEQP-VK.glsl.builtin.precision.cos.highp.vec4 +Fail dEQP-VK.glsl.builtin.precision.cos.mediump.scalar +Fail dEQP-VK.glsl.builtin.precision.cos.mediump.vec2 +Fail dEQP-VK.glsl.builtin.precision.cos.mediump.vec3 +Fail dEQP-VK.glsl.builtin.precision.cos.mediump.vec4 +Fail dEQP-VK.glsl.builtin.precision.sin.highp.scalar +Fail dEQP-VK.glsl.builtin.precision.sin.highp.vec2 +Fail dEQP-VK.glsl.builtin.precision.sin.highp.vec3 +Fail dEQP-VK.glsl.builtin.precision.sin.highp.vec4 +Fail dEQP-VK.glsl.builtin.precision.sin.mediump.scalar +Fail dEQP-VK.glsl.builtin.precision.sin.mediump.vec2 +Fail dEQP-VK.glsl.builtin.precision.sin.mediump.vec3 +Fail dEQP-VK.glsl.builtin.precision.sin.mediump.vec4 +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.const_expression.compute.isamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.const_expression.compute.usamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.const_expression.fragment.isamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.const_expression.fragment.usamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.const_literal.compute.isamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.const_literal.compute.usamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.const_literal.fragment.isamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.const_literal.fragment.usamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.dynamically_uniform.compute.isamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.dynamically_uniform.compute.usamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.dynamically_uniform.fragment.isamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.dynamically_uniform.fragment.usamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.uniform.compute.isamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.uniform.compute.usamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.uniform.fragment.isamplercube +Fail dEQP-VK.glsl.opaque_type_indexing.sampler.uniform.fragment.usamplercube +Fail dEQP-VK.glsl.texture_functions.texturegrad.usamplercube_fragment +Fail dEQP-VK.glsl.texture_functions.texturegrad.usamplercube_vertex +Fail dEQP-VK.glsl.texture_functions.texturegrad.usamplercubearray_fragment +Fail dEQP-VK.glsl.texture_functions.texturegrad.usamplercubearray_vertex +Fail dEQP-VK.glsl.texture_functions.texturegradoffset.clamp_to_border.usampler1darray_fragment +Fail dEQP-VK.glsl.texture_functions.texturegradoffset.clamp_to_border.usampler1darray_vertex +Fail dEQP-VK.glsl.texture_functions.texturegradoffset.clamp_to_border.usampler2darray_fragment +Fail dEQP-VK.glsl.texture_functions.texturelod.usamplercube_fragment +Fail dEQP-VK.glsl.texture_functions.texturelod.usamplercube_vertex +Fail dEQP-VK.glsl.texture_functions.texturelod.usamplercubearray_fragment +Fail dEQP-VK.glsl.texture_functions.texturelod.usamplercubearray_vertex +Fail dEQP-VK.glsl.texture_functions.texturelodoffset.clamp_to_border.usampler1darray_fragment +Fail dEQP-VK.glsl.texture_functions.texturelodoffset.clamp_to_border.usampler1darray_vertex +Fail dEQP-VK.glsl.texture_functions.textureoffset.clamp_to_border.isampler1darray_fragment +Fail dEQP-VK.glsl.texture_functions.textureoffset.clamp_to_border.isampler2darray_fragment +Fail dEQP-VK.glsl.texture_functions.textureoffset.clamp_to_border.usampler1darray_bias_fragment +Fail dEQP-VK.glsl.texture_functions.textureoffset.clamp_to_border.usampler1darray_fragment +Fail dEQP-VK.glsl.texture_functions.textureoffset.clamp_to_border.usampler2darray_bias_fragment +Fail dEQP-VK.glsl.texture_functions.textureoffset.clamp_to_border.usampler2darray_fragment +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8i.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8i.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8i.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8i.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8i.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8ui.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8ui.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8ui.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8ui.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d.rgba8ui.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8i.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8i.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8i.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8i.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8i.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8ui.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8ui.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8ui.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8ui.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.basic.2d_array.rgba8ui.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8i.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8i.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8i.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8i.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8i.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8ui.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8ui.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8ui.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8ui.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.basic.cube.rgba8ui.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8i.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8i.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8i.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8i.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8i.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8ui.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8ui.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8ui.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8ui.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d.rgba8ui.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8i.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8i.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8i.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8i.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8i.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8ui.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8ui.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8ui.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8ui.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset.implementation_offset.2d_array.rgba8ui.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d_array.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d_array.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d_array.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d_array.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d_array.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d_array.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d_array.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset.min_required_offset.2d_array.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8i.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8i.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8i.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8i.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8i.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8ui.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8ui.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8ui.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8ui.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d.rgba8ui.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8i.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8i.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8i.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8i.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8i.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8ui.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8ui.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8ui.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8ui.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.implementation_offset.2d_array.rgba8ui.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d_array.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d_array.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d_array.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d_array.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d_array.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d_array.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d_array.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offset_dynamic.min_required_offset.2d_array.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8i.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8i.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8i.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8i.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8i.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8ui.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8ui.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8ui.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8ui.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d.rgba8ui.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8i.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8i.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8i.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8i.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8i.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8ui.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8ui.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8ui.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8ui.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.implementation_offset.2d_array.rgba8ui.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8i.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8i.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8i.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8i.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8i.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8ui.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8ui.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8ui.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8ui.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d.rgba8ui.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.depth32f.size_npot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.depth32f.size_npot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.depth32f.size_npot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.depth32f.size_npot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.depth32f.size_pot.compare_greater.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.depth32f.size_pot.compare_greater.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.depth32f.size_pot.compare_less.mirrored_repeat_clamp_to_edge +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.depth32f.size_pot.compare_less.repeat_mirrored_repeat +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8i.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8i.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8i.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8i.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8i.texture_swizzle.zero_one_red_green +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8ui.texture_swizzle.alpha_zero_one_red +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8ui.texture_swizzle.blue_alpha_zero_one +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8ui.texture_swizzle.green_blue_alpha_zero +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8ui.texture_swizzle.one_red_green_blue +Fail dEQP-VK.glsl.texture_gather.graphics.offsets.min_required_offset.2d_array.rgba8ui.texture_swizzle.zero_one_red_green +Crash dEQP-VK.graphicsfuzz.spv-access-chains +Crash dEQP-VK.graphicsfuzz.spv-copy-object +Crash dEQP-VK.graphicsfuzz.spv-dead-break-and-unroll +Crash dEQP-VK.graphicsfuzz.spv-stable-maze-O-dead-code +Crash dEQP-VK.graphicsfuzz.spv-stable-maze-O-memory-accesses +Crash dEQP-VK.graphicsfuzz.spv-stable-maze-flatten-copy-composite +Fail dEQP-VK.info.device_mandatory_features +Fail dEQP-VK.memory.pipeline_barrier.host_write_storage_texel_buffer.1024 +Fail dEQP-VK.memory.pipeline_barrier.host_write_storage_texel_buffer.1048576 +Fail dEQP-VK.memory.pipeline_barrier.host_write_storage_texel_buffer.65536 +Fail dEQP-VK.memory.pipeline_barrier.host_write_storage_texel_buffer.8192 +Fail dEQP-VK.memory.pipeline_barrier.transfer_dst_storage_image.1048576 +Fail dEQP-VK.memory.pipeline_barrier.transfer_dst_storage_image.65536 +Fail dEQP-VK.memory.pipeline_barrier.transfer_dst_storage_texel_buffer.1024 +Fail dEQP-VK.memory.pipeline_barrier.transfer_dst_storage_texel_buffer.8192 +Fail dEQP-VK.multiview.draw_indirect.no_queries.15 +Fail dEQP-VK.multiview.draw_indirect.no_queries.15_15_15_15 +Fail dEQP-VK.multiview.draw_indirect.no_queries.5_10_5_10 +Fail dEQP-VK.multiview.draw_indirect_indexed.no_queries.15 +Fail dEQP-VK.multiview.draw_indirect_indexed.no_queries.15_15_15_15 +Fail dEQP-VK.multiview.draw_indirect_indexed.no_queries.5_10_5_10 +Fail dEQP-VK.multiview.dynamic_rendering.draw_indirect.no_queries.15 +Fail dEQP-VK.multiview.dynamic_rendering.draw_indirect.no_queries.15_15_15_15 +Fail dEQP-VK.multiview.dynamic_rendering.draw_indirect.no_queries.5_10_5_10 +Fail dEQP-VK.multiview.dynamic_rendering.draw_indirect_indexed.no_queries.15 +Fail dEQP-VK.multiview.dynamic_rendering.draw_indirect_indexed.no_queries.15_15_15_15 +Fail dEQP-VK.multiview.dynamic_rendering.draw_indirect_indexed.no_queries.5_10_5_10 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries.cmd_copy_query_pool_results.15 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries.cmd_copy_query_pool_results.15_15_15_15 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries.cmd_copy_query_pool_results.1_2_4_8 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries.cmd_copy_query_pool_results.1_2_4_8_16_32 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries.cmd_copy_query_pool_results.5_10_5_10 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries.cmd_copy_query_pool_results.8 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries.cmd_copy_query_pool_results.8_1_1_8 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries.cmd_copy_query_pool_results.max_multi_view_view_count +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries_with_availability.cmd_copy_query_pool_results.15 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries_with_availability.cmd_copy_query_pool_results.15_15_15_15 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries_with_availability.cmd_copy_query_pool_results.1_2_4_8 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries_with_availability.cmd_copy_query_pool_results.1_2_4_8_16_32 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries_with_availability.cmd_copy_query_pool_results.5_10_5_10 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries_with_availability.cmd_copy_query_pool_results.8 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries_with_availability.cmd_copy_query_pool_results.8_1_1_8 +Fail dEQP-VK.multiview.dynamic_rendering.non_precise_queries_with_availability.cmd_copy_query_pool_results.max_multi_view_view_count +Fail dEQP-VK.multiview.dynamic_rendering.queries.cmd_copy_query_pool_results.15 +Fail dEQP-VK.multiview.dynamic_rendering.queries.cmd_copy_query_pool_results.15_15_15_15 +Fail dEQP-VK.multiview.dynamic_rendering.queries.cmd_copy_query_pool_results.1_2_4_8 +Fail dEQP-VK.multiview.dynamic_rendering.queries.cmd_copy_query_pool_results.1_2_4_8_16_32 +Fail dEQP-VK.multiview.dynamic_rendering.queries.cmd_copy_query_pool_results.5_10_5_10 +Fail dEQP-VK.multiview.dynamic_rendering.queries.cmd_copy_query_pool_results.8 +Fail dEQP-VK.multiview.dynamic_rendering.queries.cmd_copy_query_pool_results.8_1_1_8 +Fail dEQP-VK.multiview.dynamic_rendering.queries.cmd_copy_query_pool_results.max_multi_view_view_count +Fail dEQP-VK.multiview.non_precise_queries.cmd_copy_query_pool_results.15 +Fail dEQP-VK.multiview.non_precise_queries.cmd_copy_query_pool_results.15_15_15_15 +Fail dEQP-VK.multiview.non_precise_queries.cmd_copy_query_pool_results.1_2_4_8 +Fail dEQP-VK.multiview.non_precise_queries.cmd_copy_query_pool_results.1_2_4_8_16_32 +Fail dEQP-VK.multiview.non_precise_queries.cmd_copy_query_pool_results.5_10_5_10 +Fail dEQP-VK.multiview.non_precise_queries.cmd_copy_query_pool_results.8 +Fail dEQP-VK.multiview.non_precise_queries.cmd_copy_query_pool_results.8_1_1_8 +Fail dEQP-VK.multiview.non_precise_queries.cmd_copy_query_pool_results.max_multi_view_view_count +Fail dEQP-VK.multiview.non_precise_queries_with_availability.cmd_copy_query_pool_results.15 +Fail dEQP-VK.multiview.non_precise_queries_with_availability.cmd_copy_query_pool_results.15_15_15_15 +Fail dEQP-VK.multiview.non_precise_queries_with_availability.cmd_copy_query_pool_results.1_2_4_8 +Fail dEQP-VK.multiview.non_precise_queries_with_availability.cmd_copy_query_pool_results.1_2_4_8_16_32 +Fail dEQP-VK.multiview.non_precise_queries_with_availability.cmd_copy_query_pool_results.5_10_5_10 +Fail dEQP-VK.multiview.non_precise_queries_with_availability.cmd_copy_query_pool_results.8 +Fail dEQP-VK.multiview.non_precise_queries_with_availability.cmd_copy_query_pool_results.8_1_1_8 +Fail dEQP-VK.multiview.non_precise_queries_with_availability.cmd_copy_query_pool_results.max_multi_view_view_count +Fail dEQP-VK.multiview.queries.cmd_copy_query_pool_results.15 +Fail dEQP-VK.multiview.queries.cmd_copy_query_pool_results.15_15_15_15 +Fail dEQP-VK.multiview.queries.cmd_copy_query_pool_results.1_2_4_8 +Fail dEQP-VK.multiview.queries.cmd_copy_query_pool_results.1_2_4_8_16_32 +Fail dEQP-VK.multiview.queries.cmd_copy_query_pool_results.5_10_5_10 +Fail dEQP-VK.multiview.queries.cmd_copy_query_pool_results.8 +Fail dEQP-VK.multiview.queries.cmd_copy_query_pool_results.8_1_1_8 +Fail dEQP-VK.multiview.queries.cmd_copy_query_pool_results.max_multi_view_view_count +Fail dEQP-VK.multiview.renderpass2.draw_indirect.no_queries.15 +Fail dEQP-VK.multiview.renderpass2.draw_indirect.no_queries.15_15_15_15 +Fail dEQP-VK.multiview.renderpass2.draw_indirect.no_queries.5_10_5_10 +Fail dEQP-VK.multiview.renderpass2.draw_indirect_indexed.no_queries.15 +Fail dEQP-VK.multiview.renderpass2.draw_indirect_indexed.no_queries.15_15_15_15 +Fail dEQP-VK.multiview.renderpass2.draw_indirect_indexed.no_queries.5_10_5_10 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries.cmd_copy_query_pool_results.15 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries.cmd_copy_query_pool_results.15_15_15_15 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries.cmd_copy_query_pool_results.1_2_4_8 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries.cmd_copy_query_pool_results.1_2_4_8_16_32 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries.cmd_copy_query_pool_results.5_10_5_10 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries.cmd_copy_query_pool_results.8 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries.cmd_copy_query_pool_results.8_1_1_8 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries.cmd_copy_query_pool_results.max_multi_view_view_count +Fail dEQP-VK.multiview.renderpass2.non_precise_queries_with_availability.cmd_copy_query_pool_results.15 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries_with_availability.cmd_copy_query_pool_results.15_15_15_15 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries_with_availability.cmd_copy_query_pool_results.1_2_4_8 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries_with_availability.cmd_copy_query_pool_results.1_2_4_8_16_32 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries_with_availability.cmd_copy_query_pool_results.5_10_5_10 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries_with_availability.cmd_copy_query_pool_results.8 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries_with_availability.cmd_copy_query_pool_results.8_1_1_8 +Fail dEQP-VK.multiview.renderpass2.non_precise_queries_with_availability.cmd_copy_query_pool_results.max_multi_view_view_count +Fail dEQP-VK.multiview.renderpass2.queries.cmd_copy_query_pool_results.15 +Fail dEQP-VK.multiview.renderpass2.queries.cmd_copy_query_pool_results.15_15_15_15 +Fail dEQP-VK.multiview.renderpass2.queries.cmd_copy_query_pool_results.1_2_4_8 +Fail dEQP-VK.multiview.renderpass2.queries.cmd_copy_query_pool_results.1_2_4_8_16_32 +Fail dEQP-VK.multiview.renderpass2.queries.cmd_copy_query_pool_results.5_10_5_10 +Fail dEQP-VK.multiview.renderpass2.queries.cmd_copy_query_pool_results.8 +Fail dEQP-VK.multiview.renderpass2.queries.cmd_copy_query_pool_results.8_1_1_8 +Fail dEQP-VK.multiview.renderpass2.queries.cmd_copy_query_pool_results.max_multi_view_view_count +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_query_with_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_query_with_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_query_with_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_query_without_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_query_without_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_query_without_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_queue_with_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_queue_with_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_queue_with_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_queue_without_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_queue_without_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_32_wait_queue_without_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_query_with_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_query_with_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_query_with_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_query_without_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_query_without_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_query_without_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_queue_with_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_queue_with_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_queue_with_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_queue_without_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_queue_without_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_conservative_size_64_wait_queue_without_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_query_with_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_query_with_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_query_with_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_query_without_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_query_without_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_query_without_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_queue_with_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_queue_with_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_queue_with_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_queue_without_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_queue_without_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_32_wait_queue_without_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_query_with_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_query_with_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_query_with_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_query_without_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_query_without_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_query_without_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_queue_with_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_queue_with_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_queue_with_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_queue_without_availability_draw_points +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_queue_without_availability_draw_triangles +Fail dEQP-VK.query_pool.occlusion_query.copy_results_precise_size_64_wait_queue_without_availability_draw_triangles_discard +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_0_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_0_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_12_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_12_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_12_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_12_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_16_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_16_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_16_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_16_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_20_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_20_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_20_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_20_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_4096_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_4096_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_4096_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_4096_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_4_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_4_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_52_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_52_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_52_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_52_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_8_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_8_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_8_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_32_stride_8_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_0_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_0_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_104_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_104_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_104_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_104_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_16_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_16_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_16_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_16_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_24_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_24_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_24_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_24_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_32_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_32_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_32_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_32_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_40_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_40_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_40_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_40_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_8192_with_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_8192_with_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_8192_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_8192_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_8_without_availability +Fail dEQP-VK.query_pool.occlusion_query.copy_results_size_64_stride_8_without_availability_dstoffset +Fail dEQP-VK.query_pool.occlusion_query.no_attachments_multisample +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_cmdcopyquerypoolresults_stride_zero_primary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_cmdcopyquerypoolresults_stride_zero_secondary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_cmdcopyquerypoolresults_stride_zero_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_stride_zero_primary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_stride_zero_secondary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_stride_zero_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_cmdcopyquerypoolresults_stride_zero_primary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_cmdcopyquerypoolresults_stride_zero_secondary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_cmdcopyquerypoolresults_stride_zero_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_stride_zero_primary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_stride_zero_secondary +Fail dEQP-VK.query_pool.statistics_query.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_stride_zero_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.32bits_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.32bits_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.32bits_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.64bits_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.64bits_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.64bits_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.32bits_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.32bits_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.32bits_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.64bits_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.64bits_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.64bits_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_after_copy.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.32bits_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.primary.64bits_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.32bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary.64bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.32bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_invocations.secondary_inherited.64bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.32bits_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_line_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_patch_list_with_no_color_attachments_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_patch_list_with_no_color_attachments_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_point_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_point_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_fan_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_fan_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_list_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_with_adjacency_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_with_adjacency_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_with_no_color_attachments_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.primary.64bits_triangle_strip_with_no_color_attachments_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.32bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_patch_list_clear_color_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_patch_list_clear_color_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_patch_list_clear_depth_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_patch_list_clear_depth_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_point_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_point_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_point_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_point_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_fan_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_fan_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_fan_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_fan_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_with_adjacency_clear_color_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_with_adjacency_clear_color_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_with_adjacency_clear_depth_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_with_adjacency_clear_depth_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary.64bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.32bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_line_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_line_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_line_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_line_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_line_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_line_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_line_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_line_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_patch_list_tessellation +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_patch_list_tessellation_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_point_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_point_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_triangle_fan_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_triangle_fan_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_triangle_list_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_triangle_list_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_triangle_list_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_triangle_list_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_triangle_strip_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_triangle_strip_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_triangle_strip_with_adjacency_geometry +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.clipping_primitives.secondary_inherited.64bits_triangle_strip_with_adjacency_vertex +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.32bits_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.32bits_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.32bits_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.32bits_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.32bits_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.32bits_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.64bits_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.64bits_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.64bits_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.64bits_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.64bits_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.compute_shader_invocations.64bits_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.32bits_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.primary.64bits_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.fragment_shader_invocations.secondary_inherited.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.32bits_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.primary.64bits_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.32bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary.64bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_invocations.secondary_inherited.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.32bits_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.primary.64bits_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.32bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary.64bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.geometry_shader_primitives.secondary_inherited.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_patch_list_v28_p3_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_line_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_patch_list_v28_p3_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_fan_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.32bits_triangle_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_patch_list_v28_p3_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_line_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_patch_list_v28_p3_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_fan_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_strip_with_adjacency_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.primary.64bits_triangle_strip_with_no_color_attachments_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.32bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_patch_list_v28_p3_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_patch_list_v28_p3_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary.64bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.32bits_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_patch_list_v28_p3 +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_primitives.secondary_inherited.64bits_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_primary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_primary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_primary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_primary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_primary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_primary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_primary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_primary_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_inherited_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_inherited_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_inherited_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_inherited_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_inherited_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_cmdcopyquerypoolresults_secondary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_primary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_primary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_primary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_primary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_primary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_primary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_primary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_primary_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_dstoffset_cmdcopyquerypoolresults_secondary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_primary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_primary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_primary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_primary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_primary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_primary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_primary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_primary_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_inherited_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_inherited_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_inherited_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_inherited_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_inherited_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.32bits_secondary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_primary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_primary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_primary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_primary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_primary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_primary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_primary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_primary_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_inherited_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_inherited_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_inherited_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_inherited_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_inherited_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_cmdcopyquerypoolresults_secondary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_primary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_primary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_primary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_primary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_primary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_primary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_primary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_primary_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_inherited_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_dstoffset_cmdcopyquerypoolresults_secondary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_primary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_primary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_primary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_primary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_primary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_primary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_primary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_primary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_primary_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_inherited_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_inherited_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_inherited_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_inherited_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_inherited_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_line_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_line_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_triangle_fan_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_triangle_strip_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.input_assembly_vertices.64bits_secondary_triangle_strip_with_adjacency_restart +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_cmdcopyquerypoolresults_tes_control_patches +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_cmdcopyquerypoolresults_tes_control_patches_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_cmdcopyquerypoolresults_tes_control_patches_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_cmdcopyquerypoolresults_tes_control_patches_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_cmdcopyquerypoolresults_tes_control_patches_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_cmdcopyquerypoolresults_tes_control_patches_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_cmdcopyquerypoolresults_tes_control_patches_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_cmdcopyquerypoolresults_tes_control_patches_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_tes_control_patches +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_tes_control_patches_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_tes_control_patches_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_tes_control_patches_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_tes_control_patches_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_tes_control_patches_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_tes_control_patches_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.32bits_tes_control_patches_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_cmdcopyquerypoolresults_tes_control_patches +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_cmdcopyquerypoolresults_tes_control_patches_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_cmdcopyquerypoolresults_tes_control_patches_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_cmdcopyquerypoolresults_tes_control_patches_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_cmdcopyquerypoolresults_tes_control_patches_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_cmdcopyquerypoolresults_tes_control_patches_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_cmdcopyquerypoolresults_tes_control_patches_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_cmdcopyquerypoolresults_tes_control_patches_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_dstoffset_cmdcopyquerypoolresults_tes_control_patches_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_tes_control_patches +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_tes_control_patches_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_tes_control_patches_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_tes_control_patches_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_tes_control_patches_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_tes_control_patches_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_tes_control_patches_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_control_patches.64bits_tes_control_patches_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_tes_evaluation_shader_invocations +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_tes_evaluation_shader_invocations_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_tes_evaluation_shader_invocations_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_tes_evaluation_shader_invocations_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_tes_evaluation_shader_invocations_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_tes_evaluation_shader_invocations_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_tes_evaluation_shader_invocations_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.32bits_tes_evaluation_shader_invocations_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_dstoffset_cmdcopyquerypoolresults_tes_evaluation_shader_invocations_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_tes_evaluation_shader_invocations +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_tes_evaluation_shader_invocations_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_tes_evaluation_shader_invocations_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_tes_evaluation_shader_invocations_secondary +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_tes_evaluation_shader_invocations_secondary_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_tes_evaluation_shader_invocations_secondary_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_tes_evaluation_shader_invocations_secondary_inherited +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.tes_evaluation_shader_invocations.64bits_tes_evaluation_shader_invocations_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.32bits_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_line_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_point_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_fan_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_list_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_list_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_strip_with_adjacency_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.primary.64bits_triangle_strip_with_no_color_attachments +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.32bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_line_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_point_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_point_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_fan_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_fan_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_list_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_list_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_list_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_list_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_strip_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_strip_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_strip_with_adjacency_clear_color +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary.64bits_triangle_strip_with_adjacency_clear_depth +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.32bits_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_dstoffset_cmdcopyquerypoolresults_triangle_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_line_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_line_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_line_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_line_strip_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_point_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_triangle_fan +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_triangle_list +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_triangle_list_with_adjacency +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_triangle_strip +Fail dEQP-VK.query_pool.statistics_query.reset_before_copy.vertex_shader_invocations.secondary_inherited.64bits_triangle_strip_with_adjacency +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed0 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed0_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed0_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed0_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed0_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed0_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed0_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed0_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed1 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed10 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed10_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed10_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed10_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed10_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed10_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed10_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed10_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed11 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed11_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed11_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed11_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed11_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed11_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed11_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed11_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed12 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed12_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed12_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed12_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed12_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed12_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed12_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed12_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed13 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed13_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed13_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed13_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed13_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed13_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed13_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed13_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed14 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed14_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed14_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed14_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed14_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed14_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed14_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed14_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed15 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed15_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed15_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed15_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed15_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed15_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed15_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed15_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed16 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed16_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed16_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed16_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed16_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed16_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed16_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed16_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed17 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed17_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed17_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed17_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed17_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed17_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed17_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed17_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed18 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed18_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed18_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed18_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed18_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed18_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed18_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed18_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed19 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed19_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed19_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed19_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed19_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed19_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed19_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed19_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed1_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed1_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed1_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed1_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed1_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed1_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed1_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed2 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed20 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed20_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed20_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed20_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed20_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed20_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed20_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed20_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed21 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed21_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed21_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed21_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed21_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed21_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed21_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed21_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed22 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed22_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed22_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed22_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed22_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed22_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed22_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed22_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed23 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed23_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed23_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed23_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed23_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed23_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed23_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed23_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed24 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed24_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed24_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed24_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed24_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed24_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed24_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed24_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed25 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed25_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed25_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed25_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed25_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed25_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed25_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed25_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed26 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed26_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed26_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed26_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed26_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed26_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed26_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed26_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed27 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed27_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed27_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed27_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed27_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed27_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed27_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed27_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed28 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed28_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed28_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed28_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed28_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed28_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed28_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed28_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed29 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed29_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed29_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed29_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed29_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed29_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed29_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed29_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed2_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed2_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed2_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed2_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed2_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed2_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed2_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed3 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed30 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed30_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed30_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed30_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed30_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed30_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed30_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed30_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed31 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed31_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed31_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed31_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed31_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed31_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed31_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed31_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed32 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed32_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed32_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed32_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed32_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed32_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed32_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed32_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed33 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed33_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed33_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed33_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed33_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed33_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed33_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed33_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed34 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed34_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed34_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed34_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed34_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed34_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed34_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed34_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed35 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed35_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed35_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed35_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed35_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed35_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed35_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed35_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed36 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed36_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed36_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed36_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed36_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed36_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed36_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed36_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed37 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed37_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed37_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed37_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed37_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed37_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed37_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed37_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed38 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed38_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed38_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed38_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed38_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed38_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed38_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed38_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed39 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed39_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed39_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed39_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed39_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed39_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed39_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed39_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed3_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed3_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed3_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed3_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed3_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed3_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed3_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed4 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed40 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed40_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed40_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed40_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed40_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed40_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed40_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed40_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed41 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed41_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed41_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed41_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed41_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed41_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed41_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed41_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed42 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed42_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed42_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed42_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed42_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed42_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed42_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed42_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed43 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed43_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed43_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed43_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed43_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed43_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed43_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed43_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed44 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed44_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed44_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed44_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed44_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed44_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed44_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed44_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed45 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed45_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed45_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed45_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed45_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed45_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed45_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed45_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed46 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed46_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed46_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed46_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed46_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed46_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed46_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed46_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed47 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed47_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed47_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed47_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed47_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed47_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed47_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed47_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed48 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed48_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed48_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed48_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed48_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed48_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed48_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed48_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed49 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed49_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed49_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed49_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed49_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed49_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed49_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed49_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed4_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed4_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed4_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed4_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed4_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed4_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed4_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed5 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed50 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed50_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed50_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed50_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed50_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed50_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed50_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed50_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed51 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed51_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed51_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed51_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed51_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed51_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed51_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed51_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed52 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed52_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed52_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed52_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed52_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed52_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed52_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed52_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed53 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed53_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed53_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed53_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed53_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed53_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed53_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed53_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed54 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed54_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed54_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed54_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed54_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed54_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed54_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed54_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed55 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed55_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed55_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed55_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed55_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed55_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed55_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed55_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed56 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed56_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed56_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed56_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed56_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed56_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed56_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed56_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed57 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed57_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed57_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed57_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed57_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed57_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed57_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed57_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed58 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed58_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed58_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed58_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed58_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed58_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed58_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed58_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed59 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed59_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed59_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed59_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed59_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed59_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed59_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed59_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed5_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed5_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed5_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed5_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed5_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed5_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed5_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed6 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed60 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed60_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed60_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed60_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed60_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed60_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed60_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed60_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed61 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed61_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed61_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed61_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed61_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed61_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed61_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed61_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed62 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed62_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed62_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed62_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed62_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed62_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed62_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed62_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed63 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed63_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed63_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed63_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed63_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed63_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed63_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed63_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed64 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed64_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed64_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed64_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed64_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed64_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed64_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed64_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed65 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed65_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed65_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed65_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed65_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed65_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed65_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed65_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed66 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed66_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed66_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed66_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed66_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed66_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed66_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed66_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed67 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed67_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed67_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed67_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed67_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed67_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed67_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed67_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed68 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed68_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed68_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed68_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed68_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed68_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed68_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed68_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed69 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed69_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed69_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed69_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed69_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed69_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed69_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed69_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed6_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed6_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed6_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed6_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed6_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed6_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed6_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed7 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed70 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed70_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed70_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed70_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed70_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed70_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed70_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed70_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed71 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed71_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed71_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed71_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed71_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed71_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed71_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed71_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed72 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed72_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed72_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed72_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed72_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed72_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed72_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed72_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed73 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed73_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed73_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed73_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed73_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed73_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed73_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed73_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed74 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed74_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed74_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed74_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed74_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed74_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed74_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed74_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed75 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed75_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed75_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed75_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed75_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed75_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed75_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed75_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed76 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed76_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed76_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed76_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed76_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed76_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed76_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed76_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed77 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed77_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed77_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed77_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed77_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed77_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed77_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed77_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed78 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed78_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed78_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed78_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed78_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed78_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed78_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed78_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed79 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed79_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed79_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed79_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed79_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed79_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed79_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed79_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed7_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed7_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed7_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed7_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed7_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed7_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed7_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed8 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed80 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed80_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed80_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed80_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed80_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed80_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed80_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed80_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed81 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed81_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed81_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed81_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed81_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed81_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed81_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed81_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed82 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed82_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed82_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed82_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed82_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed82_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed82_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed82_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed83 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed83_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed83_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed83_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed83_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed83_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed83_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed83_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed84 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed84_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed84_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed84_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed84_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed84_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed84_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed84_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed85 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed85_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed85_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed85_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed85_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed85_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed85_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed85_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed86 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed86_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed86_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed86_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed86_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed86_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed86_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed86_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed87 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed87_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed87_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed87_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed87_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed87_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed87_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed87_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed88 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed88_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed88_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed88_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed88_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed88_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed88_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed88_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed89 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed89_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed89_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed89_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed89_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed89_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed89_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed89_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed8_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed8_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed8_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed8_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed8_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed8_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed8_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed9 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed90 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed90_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed90_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed90_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed90_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed90_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed90_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed90_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed91 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed91_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed91_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed91_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed91_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed91_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed91_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed91_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed92 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed92_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed92_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed92_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed92_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed92_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed92_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed92_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed93 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed93_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed93_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed93_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed93_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed93_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed93_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed93_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed94 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed94_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed94_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed94_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed94_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed94_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed94_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed94_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed95 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed95_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed95_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed95_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed95_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed95_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed95_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed95_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed96 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed96_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed96_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed96_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed96_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed96_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed96_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed96_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed97 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed97_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed97_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed97_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed97_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed97_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed97_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed97_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed98 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed98_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed98_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed98_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed98_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed98_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed98_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed98_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed99 +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed99_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed99_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed99_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed99_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed99_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed99_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed99_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed9_geometry +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed9_geometry_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed9_geometry_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed9_geometry_tessellation_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed9_multiview +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed9_tessellation +Fail dEQP-VK.renderpasses.dynamic_rendering.primary_cmd_buff.random.seed9_tessellation_multiview +DeviceLost dEQP-VK.renderpasses.renderpass1.suballocation.multisample.d24_unorm_s8_uint.samples_8 +DeviceLost dEQP-VK.renderpasses.renderpass1.suballocation.multisample.d32_sfloat_s8_uint.samples_8 +DeviceLost dEQP-VK.renderpasses.renderpass1.suballocation.multisample.separate_stencil_usage.d24_unorm_s8_uint.samples_8.test_depth +DeviceLost dEQP-VK.renderpasses.renderpass1.suballocation.multisample.separate_stencil_usage.d32_sfloat_s8_uint.samples_8.test_depth +DeviceLost dEQP-VK.renderpasses.renderpass2.suballocation.multisample.d24_unorm_s8_uint.samples_8 +DeviceLost dEQP-VK.renderpasses.renderpass2.suballocation.multisample.d32_sfloat_s8_uint.samples_8 +Fail dEQP-VK.robustness.bind_index_buffer2.offset_0.draw_indexed.oo_size +Fail dEQP-VK.robustness.bind_index_buffer2.offset_0.draw_indexed_indirect.oo_size +Fail dEQP-VK.robustness.bind_index_buffer2.offset_0.draw_indexed_indirect_count.oo_size +Fail dEQP-VK.robustness.bind_index_buffer2.offset_0.draw_multi_indexed.oo_size +Fail dEQP-VK.robustness.bind_index_buffer2.offset_100.draw_indexed.oo_size +Fail dEQP-VK.robustness.bind_index_buffer2.offset_100.draw_indexed_indirect.oo_size +Fail dEQP-VK.robustness.bind_index_buffer2.offset_100.draw_indexed_indirect_count.oo_size +Fail dEQP-VK.robustness.bind_index_buffer2.offset_100.draw_multi_indexed.oo_size +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.bind.notemplate.rgba32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.cube_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.image_robustness.push.notemplate.rgba32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.cube_array.comp +Fail dEQP-VK.robustness.index_access.draw_indexed_2 +Fail dEQP-VK.robustness.robustness2.bind.notemplate.r32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.r32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.r32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.r32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.r32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.r32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.r32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.r32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rg32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.dontunroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.dontunroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.cube_array.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.notemplate.rgba32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.r32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.r32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.r32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.r32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.r32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.r32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.r32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.r32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rg32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rg32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rg32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rg32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rg32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rg32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rg32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rg32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32i.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32i.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32i.dontunroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32i.dontunroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32ui.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32ui.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32ui.dontunroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32ui.dontunroll.nonvolatile.uniform_buffer_dynamic.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.bind.template.rgba32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.r32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.r32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.r32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.r32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.r32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.r32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.r32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.r32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rg32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32f.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.2d_array.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.3d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.cube_array.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_12.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_16.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_20.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_31.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_32.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_33.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_35.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_36.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_39.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_4.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_41.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_buffer.no_fmt_qual.len_8.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.notemplate.rgba32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.r32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.r32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.r32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.r32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.r32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.r32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.r32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.r32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.rg32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.rg32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.rg32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.rg32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.rg32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.rg32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.rg32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.rg32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.rgba32i.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.rgba32i.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.rgba32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.rgba32i.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.rgba32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.rgba32i.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.rgba32ui.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.rgba32ui.dontunroll.nonvolatile.uniform_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.rgba32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.rgba32ui.dontunroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +Fail dEQP-VK.robustness.robustness2.push.template.rgba32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.comp +Fail dEQP-VK.robustness.robustness2.push.template.rgba32ui.unroll.nonvolatile.uniform_texel_buffer.no_fmt_qual.null_descriptor.samples_1.1d.frag +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32f.depth_property.depth +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32i.depth_property.depth +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32i.depth_property.non_depth +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32i.depth_property.unknown +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32i_nontemporal.depth_property.depth +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32i_nontemporal.depth_property.non_depth +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32i_nontemporal.depth_property.unknown +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32ui.depth_property.depth +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32ui.depth_property.non_depth +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32ui.depth_property.unknown +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32ui_nontemporal.depth_property.depth +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32ui_nontemporal.depth_property.non_depth +DeviceLost dEQP-VK.spirv_assembly.instruction.compute.image_sampler.imageread.storage_image.optypeimage_mismatch_rgba32ui_nontemporal.depth_property.unknown +DeviceLost dEQP-VK.spirv_assembly.instruction.graphics.image_sampler.imageread.storage_image.optypeimage_mismatch.rgba32f.depth_property.depth.shader_frag +DeviceLost dEQP-VK.spirv_assembly.instruction.graphics.image_sampler.imageread.storage_image.optypeimage_mismatch.rgba32f.depth_property.non_depth.shader_frag +DeviceLost dEQP-VK.spirv_assembly.instruction.graphics.image_sampler.imageread.storage_image.optypeimage_mismatch.rgba32i.depth_property.depth.shader_frag +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_bit_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_bit_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_bit_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_bit_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_to_exponent_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_to_exponent_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_to_exponent_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_to_exponent_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.inf_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.inf_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.inf_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.inf_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_inf_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_inf_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_inf_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_inf_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_round_up_or_round_down_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_round_up_or_round_down_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_round_up_or_round_down_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_round_up_or_round_down_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.positive_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.positive_round_up_or_round_down_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.positive_round_up_or_round_down_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.positive_round_up_or_round_down_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.positive_round_up_or_round_down_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.positive_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.positive_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.positive_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_inf_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_inf_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_inf_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_inf_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_negative_inf_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_negative_inf_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_negative_inf_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_negative_inf_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_bit_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_bit_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_bit_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_bit_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_to_exponent_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_to_exponent_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_to_exponent_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_to_exponent_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_negative_round_up_or_round_down_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_negative_round_up_or_round_down_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_negative_round_up_or_round_down_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_negative_round_up_or_round_down_vert +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_positive_round_up_or_round_down_geom +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_positive_round_up_or_round_down_tessc +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_positive_round_up_or_round_down_tesse +Fail dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_positive_round_up_or_round_down_vert +DeviceLost dEQP-VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_frag +ResourceError dEQP-VK.tessellation.tess_io.max_in_out.32_bits_only.permutation_0.tcs_patch_writes_reads_tes_reads +ResourceError dEQP-VK.tessellation.tess_io.max_in_out.32_bits_only.permutation_0.tcs_patch_writes_tes_reads +ResourceError dEQP-VK.tessellation.tess_io.max_in_out.32_bits_only.permutation_5.tcs_patch_writes_tes_reads +ResourceError dEQP-VK.tessellation.tess_io.max_in_out.32_bits_only.permutation_6.tcs_patch_writes_reads_tes_reads +ResourceError dEQP-VK.tessellation.tess_io.max_in_out.32_bits_only.permutation_6.tcs_patch_writes_tes_reads +ResourceError dEQP-VK.tessellation.tess_io.max_in_out.32_bits_only.permutation_9.tcs_patch_writes_reads_tes_reads +ResourceError dEQP-VK.tessellation.tess_io.max_in_out.32_bits_only.permutation_9.tcs_patch_writes_tes_reads +Fail dEQP-VK.texture.filtering.cube.formats.d24_unorm_s8_uint_stencil.nearest.seamless +Fail dEQP-VK.texture.filtering.cube.formats.d32_sfloat_s8_uint_stencil.nearest.seamless +Fail dEQP-VK.texture.filtering.cube.formats.s8_uint.nearest.seamless +Fail dEQP-VK.texture.filtering.unnormal.formats.d24_unorm_s8_uint_stencil.nearest +Fail dEQP-VK.texture.filtering.unnormal.formats.s8_uint.nearest +Fail dEQP-VK.texture.mipmap.2d.image_view_min_lod.base_level.nearest_linear_integer_texel_coord +Fail dEQP-VK.texture.mipmap.2d.image_view_min_lod.min_lod.linear_linear_integer_texel_coord +Fail dEQP-VK.texture.mipmap.2d.image_view_min_lod.min_lod.nearest_linear_integer_texel_coord +Fail dEQP-VK.texture.mipmap.3d.image_view_min_lod.base_level.nearest_linear_integer_texel_coord +Fail dEQP-VK.texture.mipmap.cubemap.max_level.linear_nearest +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.host_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_list_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.line_strip_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_list_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.no_xfb.rast.triangle_strip_with_adjacency.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.no_xfb.rast.patch_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.line_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.point_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_fan.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_list.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.no_xfb.rast.triangle_strip.pgq_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_32bit_xfb_64bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_list_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_0_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_0.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_1.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.geom.xfb.rast.triangle_strip_with_adjacency.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.tese.xfb.rast.patch_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.line_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.point_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_fan.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.pqg_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.after_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.before_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.single_draw.xfbq_first.none_with_availability +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_list.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.single_draw.xfbq_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.pqg_first.none_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.after_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.before_2_queries +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none +Fail dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.pgq_64bit_xfb_32bit.vert.xfb.rast.triangle_strip.pgq_default_xfb_default.two_draws.xfbq_first.none_2_queries +ResourceError dEQP-VK.video.decode.h264.420_8bit_high_176x144_30frames_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.420_8bit_high_176x144_30frames_separated_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.i_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.i_p_b_13_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.i_p_b_13_not_matching_order_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.i_p_b_13_not_matching_order_separated_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.i_p_b_13_separated_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.i_p_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.i_p_not_matching_order_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.i_p_not_matching_order_separated_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.i_p_separated_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.i_separated_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.inline_session_params_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.inline_session_params_separated_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.interleaved_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.interleaved_separated_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.relaxed_session_params_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.relaxed_session_params_separated_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.resolution_change_dpb_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.resolution_change_dpb_separated_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.resolution_change_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.resolution_change_separated_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.resources_without_profiles_layered_dpb_video_layout +ResourceError dEQP-VK.video.decode.h264.resources_without_profiles_separated_dpb_video_layout +ResourceError dEQP-VK.video.encode.h264.i_layered_src_video_layout +ResourceError dEQP-VK.video.encode.h264.i_p_layered_src_video_layout +ResourceError dEQP-VK.video.encode.h264.i_p_not_matching_order_layered_src_video_layout +ResourceError dEQP-VK.video.encode.h264.i_p_not_matching_order_separated_src_video_layout +ResourceError dEQP-VK.video.encode.h264.i_p_separated_src_video_layout +ResourceError dEQP-VK.video.encode.h264.i_separated_src_video_layout +ResourceError dEQP-VK.video.encode.h264.inline_query_layered_src_video_layout +ResourceError dEQP-VK.video.encode.h264.inline_query_separated_src_video_layout +ResourceError dEQP-VK.video.encode.h264.quality_level_layered_src_video_layout +ResourceError dEQP-VK.video.encode.h264.quality_level_separated_src_video_layout +ResourceError dEQP-VK.video.encode.h264.rc_disable_layered_src_video_layout +ResourceError dEQP-VK.video.encode.h264.rc_disable_separated_src_video_layout +ResourceError dEQP-VK.video.encode.h264.resolution_change_dpb_layered_src_video_layout +ResourceError dEQP-VK.video.encode.h264.resolution_change_dpb_separated_src_video_layout +ResourceError dEQP-VK.video.encode.h264.resources_without_profiles_layered_src_video_layout +ResourceError dEQP-VK.video.encode.h264.resources_without_profiles_separated_src_video_layout +CapabilityWarning dEQP-VK.video.profiles.encode.h264.baseline_420_luma_8bit_chroma_8bit +CapabilityWarning dEQP-VK.video.profiles.encode.h264.main_420_luma_8bit_chroma_8bit +DeviceLost dEQP-VK.video.synchronization.decode_h264.basic.event.device_set_reset +Fail dEQP-VK.video.synchronization.decode_h264.basic.event.multi_submit_multi_command_buffer +Fail dEQP-VK.video.synchronization.decode_h264.basic.event.single_submit_multi_command_buffer +DeviceLost dEQP-VK.video.synchronization.encode_h264.basic.event.device_set_reset +Fail dEQP-VK.wsi.headless.surface.query_presentation_support diff --git a/cts/scan-2026-08-20/hangs.txt b/cts/scan-2026-08-20/hangs.txt new file mode 100644 index 0000000..1a3ef06 --- /dev/null +++ b/cts/scan-2026-08-20/hangs.txt @@ -0,0 +1,8 @@ +2026-08-20T16:08:40+03:00 chunk 1 ended badly (rc=1) +2026-08-20T16:13:52+03:00 chunk 2 ended badly (rc=1) +2026-08-20T16:24:23+03:00 chunk 3 ended badly (rc=1) +2026-08-20T18:03:06+03:00 chunk 6 ended badly (rc=1) +2026-08-20T18:48:18+03:00 chunk 10 ended badly (rc=139) +2026-08-20T18:54:08+03:00 chunk 11 ended badly (rc=139) +2026-08-20T20:28:44+03:00 chunk 9 ended badly (rc=0) +2026-08-20T21:15:33+03:00 chunk 13 ended badly (rc=1) diff --git a/cts/scan-2026-08-20/results-full.tsv.gz b/cts/scan-2026-08-20/results-full.tsv.gz new file mode 100644 index 0000000..0bef76b Binary files /dev/null and b/cts/scan-2026-08-20/results-full.tsv.gz differ diff --git a/docs/ivb_2012/ivb_ihd_os_vol1_part1.pdf b/docs/ivb_2012/ivb_ihd_os_vol1_part1.pdf new file mode 100644 index 0000000..76356b4 Binary files /dev/null and b/docs/ivb_2012/ivb_ihd_os_vol1_part1.pdf differ diff --git a/docs/ivb_2012/ivb_ihd_os_vol1_part2.pdf b/docs/ivb_2012/ivb_ihd_os_vol1_part2.pdf new file mode 100644 index 0000000..1aebe30 Binary files /dev/null and b/docs/ivb_2012/ivb_ihd_os_vol1_part2.pdf differ diff --git a/docs/ivb_2012/ivb_ihd_os_vol1_part3.pdf b/docs/ivb_2012/ivb_ihd_os_vol1_part3.pdf new file mode 100644 index 0000000..532f916 Binary files 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b/docs/ivb_2012/ivb_ihd_os_vol4_part3.pdf new file mode 100644 index 0000000..c1d142d Binary files /dev/null and b/docs/ivb_2012/ivb_ihd_os_vol4_part3.pdf differ diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol1_part1.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part1.txt new file mode 100644 index 0000000..b7e0588 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part1.txt @@ -0,0 +1,6838 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 1 Part 1: Graphics Core™ +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S +TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY +WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO +SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO +FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY +PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. + +A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly +or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 2 + Contents +1. Introduction ................................................................................................................................................. 6 + 1.1 Reserved Bits and Software Compatibility ........................................................................................... 7 + 1.2 Terminology ......................................................................................................................................... 8 +2. Graphics Device Overview ................................................................................................................. 15 + 2.1 Graphics Processing Unit (GPU) ....................................................................................................... 15 +3. Graphics Processing Engine (GPE) .................................................................................................. 16 + 3.1 Introduction to the GPE ...................................................................................................................... 16 + 3.2 Overview ............................................................................................................................................ 16 + 3.2.1 Graphics Processing Engine Block Diagram ................................................................................ 17 + 3.2.2 Command Stream (CS) Unit......................................................................................................... 17 + 3.2.3 3D Pipeline ................................................................................................................................... 17 + 3.2.4 Media Pipeline .............................................................................................................................. 17 + 3.2.5 Subsystem .................................................................................................................................... 18 + 3.2.6 Execution Units (EUs) .................................................................................................................. 18 + 3.2.7 GPE Function IDs ......................................................................................................................... 18 + 3.3 Pipeline Selection ............................................................................................................................... 18 + 3.4 Memory Object Control State ............................................................................................................. 19 + 3.4.1 MEMORY_OBJECT_CONTROL_STATE .................................................................................... 20 + 3.5 Memory Access Indirection ................................................................................................................ 21 + 3.5.1 STATE_BASE_ADDRESS ........................................................................................................... 22 + 3.5.2 SWTESS_BASE_ADDRESS ....................................................................................................... 28 + 3.6 Instruction and State Prefetch ............................................................................................................ 30 + 3.6.1 STATE_PREFETCH ..................................................................................................................... 30 + 3.7 System Thread Configuration ............................................................................................................ 31 + 3.7.1 STATE_SIP .................................................................................................................................. 31 + 3.8 Command Ordering Rules ................................................................................................................. 32 + 3.8.1 PIPELINE_SELECT ..................................................................................................................... 33 + 3.8.2 PIPE_CONTROL .......................................................................................................................... 33 + 3.8.3 URB-Related State-Setting Commands ....................................................................................... 34 + 3.8.4 Common Pipeline State-Setting Commands ................................................................................ 34 + 3.8.5 3D Pipeline-Specific State-Setting Commands ............................................................................ 34 + 3.8.6 Media Pipeline-Specific State-Setting Commands ....................................................................... 35 + 3.8.7 CONSTANT_BUFFER (CURBE Load) ........................................................................................ 35 + 3.8.8 3DPRIMITIVE ............................................................................................................................... 35 + 3.8.9 MEDIA_OBJECT .......................................................................................................................... 35 +4. Video Codec Engine ............................................................................................................................ 36 + 4.1 Video Command Streamer (VCS) ...................................................................................................... 36 +5. Graphics Command Formats ............................................................................................................. 38 + 5.1 Command Formats ............................................................................................................................ 38 + 5.1.1 Memory Interface Commands ...................................................................................................... 38 + 5.1.2 2D Commands .............................................................................................................................. 39 + 5.1.3 3D/Media Commands ................................................................................................................... 39 + 5.1.4 Video Codec Commands.............................................................................................................. 39 + 5.1.5 Command Header ........................................................................................................................ 39 + 5.2 Command Map ................................................................................................................................... 41 + 5.2.1 Memory Interface Command Map ................................................................................................ 41 + 5.2.2 2D Command Map ....................................................................................................................... 43 + 5.2.3 3D/Media Command Map ............................................................................................................. 44 + 5.2.4 Video Codec Command Map ....................................................................................................... 47 +6. Memory Data Formats ......................................................................................................................... 50 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 3 + 6.1 Memory Object Overview ................................................................................................................... 50 + 6.1.1 Memory Object Types .................................................................................................................. 50 + 6.2 Channel Formats................................................................................................................................ 51 + 6.2.1 Unsigned Normalized (UNORM) .................................................................................................. 51 + 6.2.2 Gamma Conversion (SRGB) ........................................................................................................ 51 + 6.2.3 Signed Normalized (SNORM) ...................................................................................................... 51 + 6.2.4 Unsigned Integer (UINT/USCALED) ............................................................................................ 51 + 6.2.5 Signed Integer (SINT/SSCALED) ................................................................................................. 52 + 6.2.6 Floating Point (FLOAT) ................................................................................................................. 52 + 6.2.7 Non-Video Surface Formats ......................................................................................................... 55 + 6.2.8 Surface Format Naming ............................................................................................................... 55 + 6.2.9 Intensity Formats .......................................................................................................................... 55 + 6.2.10 Luminance Formats .................................................................................................................... 55 + 6.2.11 R1_UNORM (same as R1_UINT) and MONO8 ......................................................................... 56 + 6.2.12 Palette Formats .......................................................................................................................... 56 + 6.3 Compressed Surface Formats ........................................................................................................... 58 + 6.3.1 FXT Texture Formats ................................................................................................................... 58 + 6.3.2 DXT Texture Formats ................................................................................................................... 67 + 6.3.3 BC4 ............................................................................................................................................... 72 + 6.3.4 BC5 ............................................................................................................................................... 73 + 6.3.5 BC6H ............................................................................................................................................ 75 + 6.3.6 BC7 ............................................................................................................................................... 86 + 6.4 Video Pixel/Texel Formats ................................................................................................................. 95 + 6.4.1 Packed Memory Organization ...................................................................................................... 95 + 6.4.2 Planar Memory Organization ........................................................................................................ 95 + 6.5 Additional Video Formats ................................................................................................................... 97 + 6.6 Raw Format ...................................................................................................................................... 102 + 6.7 Surface Memory Organizations ....................................................................................................... 102 + 6.8 Graphics Translation Tables ............................................................................................................ 102 + 6.9 Hardware Status Page ..................................................................................................................... 103 + 6.10 Instruction Ring Buffers .................................................................................................................. 103 + 6.11 Instruction Batch Buffers................................................................................................................. 103 + 6.12 2D Render Surfaces ....................................................................................................................... 103 + 6.13 2D Monochrome Source ................................................................................................................. 103 + 6.14 2D Color Pattern ............................................................................................................................. 104 + 6.15 3D Color Buffer (Destination) Surfaces .......................................................................................... 104 + 6.16 3D Depth Buffer Surfaces ............................................................................................................... 104 + 6.17 3D Separate Stencil Buffer Surfaces .............................................................................................. 105 + 6.18 Surface Layout ................................................................................................................................ 105 + 6.18.1 Buffers ...................................................................................................................................... 105 + 6.18.2 Structured Buffers ..................................................................................................................... 106 + 6.18.3 1D Surfaces .............................................................................................................................. 106 + 6.18.4 2D Surfaces .............................................................................................................................. 107 + 6.18.5 Cube Surfaces .......................................................................................................................... 112 + 6.18.6 3D Surfaces .............................................................................................................................. 114 + 6.19 Surface Padding Requirements ...................................................................................................... 116 + 6.19.1 Sampling Engine Surfaces ....................................................................................................... 116 + 6.19.2 Render Target and Media Surfaces ......................................................................................... 117 + 6.20 BSD Logical Context Data (MFX) ................................................................................................... 117 + 6.20.1 Register/State Context ............................................................................................................. 117 + 6.20.2 The Per-Process Hardware Status Page ................................................................................. 118 + 6.21 Copy Engine Logical Context Data ................................................................................................. 119 + 6.21.1 Register/State Context ............................................................................................................. 119 + 6.21.2 The Per-Process Hardware Status Page ................................................................................. 120 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 4 + 6.22 Render Logical Context Data ......................................................................................................... 120 + 6.22.1 Overall Context Layout ............................................................................................................. 120 + 6.22.2 Pipelined State Page ................................................................................................................ 132 + 6.22.3 Ring Buffer ................................................................................................................................ 132 + 6.22.4 The Per-Process Hardware Status Page ................................................................................. 133 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 5 + 1. Introduction + ® +This Intel HD Graphics Open Source Programmer’s Reference Manual (PRM) describes the +architectural behavior and programming environment of the Ivy Bridge chipset family. The Graphics +Controller (GC) contains an extensive set of registers and instructions for configuration, 2D, 3D, and +video systems. The PRM describes the register, instruction, and memory interfaces, and the device +behaviors as controlled and observed through those interfaces. The PRM also describes the registers +and instructions, and provides detailed bit/field descriptions. + +The PRM is organized into four volumes, with each volume split into multiple parts for easy accessibility: + +PRM Volume 1: Intel Graphics Core™ +This volume contains an introduction to the: + +  Graphics Processing Unit (GPU) + +  Graphics Processing Engine (GPE) + + The GPE is a collective term for 3D, Media, the subsystem, and the parts of the memory interface + that are used by these units. Display, blitter, and their memory interfaces are not included in the + GPE. + +  Graphics Memory Interface Functions + +  Device Programming Environment + +  Command Streamers, including the Render, Blitter, and Video Codec command streamers + +  GT Interface Registers + +  L3 Cache and Unified Return Buffer + +PRM Volume 2: 3D / Media +This volume includes: + +  An introduction to the 3D Pipeline and its stages, including Vertex Fetch, Vertex Shader, Hull + Shader, Tesselation Engine, Domain Shader, Geometry Shader, Stream Output Logic, Clip, + Strips and Fans, Windower and Color Calculator stages + +  The single Media fixed function, Variable Length Decode (VLD), describing how to initiate generic + threads using the thread spawner (TS). Generic threads are used for the majority of media + functions. Programmable kernels handle the algorithms for media functions such as IDCT, Motion + Compensation, and Motion Estimation (used for encoding MPEG streams). + +  Details about the Media pipeline, which is positioned in parallel with the 3D fixed function pipeline. + +  The Multi-Format Codec (MFX) engine, the hardware fixed-function popeline for decoding and + encoding. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 6 + PRM Volume 3: Display Registers +Volume 3 describes the control registers for the display. This information includes: + +  VGA and Extended VGA Registers + +  PCI Registers + +  North Display Engine Registers + +  South Display Engine Registers + +PRM Volume 4: Subsystem and Cores/ Shared Functions +The subsystem contains the programmable cores, or Executable Units (EUs), and the “shared functions” +that are shared by more than one EU and perform I/O functions and complex math functions. + +The shared functions consist of the sampler: + +  Extended math unit + +  Data port (the interface to memory for 3D and media) + +  Unified Return Buffer (URB) + +  The Message Gateway used by EU threads to signal each other + +The EUs use messages to send data to and receive data from the subsystem; the messages are +described with the shared functions. The generic message ‘send EU instruction’ is described with the rest +of the instructions in the Instruction Set Architecture (ISA) chapters. + +The latter part of this volume describes the GMHC core, or EU, and the associated instructions used to +program it. The instruction descriptions make up an Instruction Set Architecture, or ISA. The ISA +describes all of the instructions that the core can execute, along with the registers that are used to store +local data. + + +1.1 Reserved Bits and Software Compatibility +In many register, instruction, and memory layout descriptions, certain bits are marked as “Reserved”. +When bits are marked as reserved, it is essential for compatibility with future devices that the software +treat these bits as having a future, though unknown, effect. The behavior of reserved bits should be +regarded as undefined and unpredictable. Software should follow these guidelines in dealing with +reserved bits: + 1. Do not depend on the states of any reserved bits when testing values of registers that contain + such bits. + 2. Mask out the reserved bits before testing. + 3. Do not depend on the states of any reserved bits when storing to an instruction or to a + register. + 4. When loading a register or formatting an instruction, always load the reserved bits with the + values indicated in the documentation (if any), or reload them with the values previously read + from the register. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 7 + 1.2 Terminology + Term Abbr. Definition +3D Pipeline -- + One of the two pipelines supported in the GPE. The 3D Pipeline is a set of fixed- + function units arranged in a pipelined fashion, which process 3D-related commands + by spawning EU threads. Typically this processing includes rendering primitives. + See 3D Pipeline. + +Adjacency -- + One can consider a single line object as existing in a strip of connected lines. The + neighboring line objects are called “adjacent objects”, with the non-shared endpoints + called the “adjacent vertices.” The same concept can be applied to a single triangle + object, considering it as existing in a mesh of connected triangles. Each triangle + shares edges with three other adjacent triangles, each defined by an non-shared + adjacent vertex. Knowledge of these adjacent objects/vertices is required by some + object processing algorithms (e.g., silhouette edge detection). See 3D Pipeline. + +Application IP AIP Application Instruction Pointer. This is part of the control registers for exception + handling for a thread. Upon an exception, hardware moves the current IP into this + register and then jumps to SIP. +Architectural ARF A collection of architecturally visible registers for a thread such as address registers, +Register File accumulator, flags, notification registers, IP, null, etc. ARF should not be mistaken as + just the address registers. +Array of Cores -- Refers to a group of EUs, which are physically organized in two or more rows. The + fact that the EUs are arranged in an array is (to a great extent) transparent to CPU + software or EU kernels. +Binding Table -- Memory-resident list of pointers to surface state blocks (also in memory). +Binding Table BTP Pointer to a binding table, specified as an offset from the Surface State Base Address +Pointer register. +Bypass Mode -- Mode where a given fixed function unit is disabled and forwards data down the + pipeline unchanged. Not supported by all FF units. +Byte B A numerical data type of 8 bits, B represents a signed byte integer. +Child Thread A branch-node or a leaf-node thread that is created by another thread. It is a kind of + thread associated with the media fixed function pipeline. A child thread is originated + from a thread (the parent) executing on an EU and forwarded to the Thread + Dispatcher by the TS unit. A child thread may or may not have child threads + depending on whether it is a branch-node or a leaf-node thread. All pre-allocated + resources such as URB and scratch memory for a child thread are managed by its + parent thread. +Clip Space -- A 4-dimensional coordinate system within which a clipping frustum is defined. Object + positions are projected from Clip Space to NDC space via “perspecitive divide” by the + W coordinate, and then viewport mapped into Screen Space +Clipper -- 3D fixed function unit that removes invisible portions of the drawing sequence by + discarding (culling) primitives or by “replacing” primitives with one or more primitives + that replicate only the visible portion of the original primitive. +Color Calculator CC Part of the Data Port shared function, the color calculator performs fixed-function + pixel operations (e.g., blending) prior to writing a result pixel into the render cache. +Command -- Directive fetched from a ring buffer in memory by the Command Streamer and routed + down a pipeline. Should not be confused with instructions which are fetched by the + instruction cache subsystem and executed on an EU. +Command Streamer CS or CSI Functional unit of the Graphics Processing Engine that fetches commands, parses + them and routes them to the appropriate pipeline. +Constant URB Entry CURBE A UE that contains “constant” data for use by various stages of the pipeline. +Control Register CR The read-write registers are used for thread mode control and exception handling for + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 8 + Term Abbr. Definition + a thread. +Data Port DP Shared function unit that performs a majority of the memory access types on behalf of + programs. The Data Port contains the render cache and the constant cache and + performs all memory accesses requested by programs except those performed by the + Sampler. See DataPort. +Degenerate Object -- Object that is invisible due to coincident vertices or because does not intersect any + sample points (usually due to being tiny or a very thin sliver). +Destination -- Describes an output or write operand. +Destination Size The number of data elements in the destination of an SIMD instruction. +Destination Width The size of each of (possibly) many elements of the destination of an SIMD + instruction. +Double Quad word DQ A fundamental data type, DQ represents 16 bytes. +(DQword) +Double word D or DW A fundamental data type, D or DW represents 4 bytes. +(DWord) +Drawing Rectangle -- + A screen-space rectangle within which 3D primitives are rendered. An objects + screen-space positions are relative to the Drawing Rectangle origin. See Strips and + Fans. + +End of Block EOB A 1-bit flag in the non-zero DCT coefficient data structure indicating the end of an 8x8 + block in a DCT coefficient data buffer. +End Of Thread EOT a message sideband signal on the Output message bus signifying that the message + requester thread is terminated. A thread must have at least one SEND instruction + with the EOT bit in the message descriptor field set in order to properly terminate. +Exception -- Type of (normally rare) interruption to EU execution of a thread’s instructions. An + exception occurrence causes the EU thread to begin executing the System Routine + which is designed to handle exceptions. +Execution Channel -- +Execution Size ExecSize Execution Size indicates the number of data elements processed by an SIMD + instruction. It is one of the instruction fields and can be changed per instruction. +Execution Unit EU Execution Unit. An EU is a multi-threaded processor within the multi-processor + system. Each EU is a fully-capable processor containing instruction fetch and + decode, register files, source operand swizzle and SIMD ALU, etc. An EU is also + referred to as a Core. +Execution Unit EUID The 4-bit field within a thread state register (SR0) that identifies the row and column +Identifier location of the EU a thread is located. A thread can be uniquely identified by the EUID + and TID. +Execution Width ExecWidth The width of each of several data elements that may be processed by a single SIMD + instruction. +Extended Math Unit EM A Shared Function that performs more complex math operations on behalf of several + EUs. + -- + FF Unit A Fixed-Function Unit is the hardware component of a 3D Pipeline Stage. A FF Unit + typically has a unique FF ID associated with it. + +Fixed Function FF Function of the pipeline that is performed by dedicated (vs. programmable) hardware. +Fixed Function ID FFID Unique identifier for a fixed function unit. +FLT_MAX fmax The magnitude of the maximum representable single precision floating number + according to IEEE-754 standard. FLT_MAX has an exponent of 0xFE and a mantissa + of all one’s. +Gateway GW See Message Gateway. +Core Alternative name for an EU in the multi-processor system. +General Register GRF Large read/write register file shared by all the EUs for operand sources and +File destinations. This is the most commonly used read-write register space organized as + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 9 + Term Abbr. Definition + an array of 256-bit registers for a thread. +General State Base -- + The Graphics Address of a block of memory-resident “state data”, which includes +Address + state blocks, scratch space, constant buffers and kernel programs. The contents of + this memory block are referenced via offsets from the contents of the General State + Base Address register. See Graphics Processing Engine. + +Geometry Shader GS + Fixed-function unit between the vertex shader and the clipper that (if enabled) + dispatches “geometry shader” threads on its input primitives. Application-supplied + geometry shaders normally expand each input primitive into several output primitives + in order to perform 3D modeling algorithms such as fur/fins. See Geometry Shader. + +Graphics Address The GPE virtual address of some memory-resident object. This virtual address gets + mapped by a GTT or PGTT to a physical memory address. Note that many memory- + resident objects are referenced not with Graphics Addresses, but instead with offsets + from a “base address register”. +Graphics GPE Collective name for the Subsystem, the 3D and Media pipelines, and the Command +Processing Engine Streamer. +Guardband GB Region that may be clipped against to make sure objects do not exceed the + limitations of the renderer’s coordinate space. +Horizontal Stride HorzStride The distance in element-sized units between adjacent elements of a region-based + GRF access. +Immediate floating VF A numerical data type of 32 bits, an immediate floating point vector of type VF +point vector contains 4 floating point elements with 8-bit each. The 8-bit floating point element + contains a sign field, a 3-bit exponent field and a 4-bit mantissa field. It may be used + to specify the type of an immediate operand in an instruction. +Immediate integer V A numerical data type of 32 bits, an immediate integer vector of type V contains 8 +vector signed integer elements with 4-bit each. The 4-bit integer element is in 2’s + compliment form. It may be used to specify the type of an immediate operand in an + instruction. +Index Buffer IB Buffer in memory containing vertex indices. +In-loop Deblocking ILDB + The deblocking filter operation in the decoding loop. It is a stage after MC in the +Filter + video decoding pipe. +Instance In the context of the VF unit, an instance is one of a sequence of sets of similar + primitive data. Each set has identical vertex data but may have unique instance data + that differentiates it from other sets in the sequence. +Instruction -- Data in memory directing an EU operation. Instructions are fetched from memory, + stored in a cache and executed on one or more cores. Not to be confused with + commands which are fetched and parsed by the command streamer and dispatched + down the 3D or Media pipeline. +Instruction Pointer IP The address (really an offset) of the instruction currently being fetched by an EU. + Each EU has its own IP. +Instruction Set ISA The ISA describes the instructions supported by an EU. +Architecture +Instruction State ISC On-chip memory that holds recently-used instructions and state variable values. +Cache +Interface Descriptor -- Media analog of a State Descriptor. +Intermediate Z IZ Completion of the Z (depth) test at the front end of the Windower/Masker unit when + certain conditions are met (no alpha, no pixel-shader computed Z values, etc.) +Inverse Discrete IDCT the stage in the video decoding pipe between IQ and MC +Cosine Transform +Inverse IQ A stage in the video decoding pipe between IS and IDCT. +Quantization + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 10 + Term Abbr. Definition +Inverse Scan IS + A stage in the video decoding pipe between VLD and IQ. In this stage, a sequence + of none-zero DCT coefficients are converted into a block (e.g. an 8x8 block) of + coefficients. VFE unit has fixed functions to support IS for both MPEG-2. +Jitter Just-in-time compiler. +Kernel -- A sequence of instructions that is logically part of the driver or generated by the jitter. + Differentiated from a Shader which is an application supplied program that is + translated by the jitter to instructions. +Least Significant Bit LSB +MathBox -- See Extended Math Unit +Media -- Term for operations such as video decode and encode that are normally performed + by the Media pipeline. +Media Pipeline -- Fixed function stages dedicated to media and “generic” processing, sometimes + referred to as the generic pipeline. +Message -- Messages are data packages transmitted from a thread to another thread, another + shared function or another fixed function. Message passing is the primary + communication mechanism of architecture. +Message Gateway -- Shared function that enables thread-to-thread message + communication/synchronization used solely by the Media pipeline. +Message Register MRF Write-only registers used by EUs to assemble messages prior to sending and as the +File operand of a send instruction. +Most Significant Bit MSB +Motion MC Part of the video decoding pipe. +Compensation +Motion Picture MPEG MPEG is the international standard body JTC1/SC29/WG11 under ISO/IEC that has +Expert Group defined audio and video compression standards such as MPEG-1, MPEG-2, and + MPEG-4, etc. +Motion Vector Field MVFS A four-bit field selecting reference fields for the motion vectors of the current +Selection macroblock. +Multi Render MRT Multiple independent surfaces that may be the target of a sequence of 3D or Media +Targets commands that use the same surface state. +Normalized Device NDC Clip Space Coordinates that have been divided by the Clip Space “W” component. +Coordinates +Object -- A single triangle, line or point. +Open GL OGL A Graphics API specification associated with Linux. +Parent Thread -- A thread corresponding to a root-node or a branch-node in thread generation + hierarchy. A parent thread may be a root thread or a child thread depending on its + position in the thread generation hierarchy. +Pipeline Stage -- A abstracted element of the 3D Pipeline, providing functions performed by a + combination of the corresponding hardware FF unit and the threads spawned by that + FF unit. +Pipelined State PSP Pointers to state blocks in memory that are passed down the pipeline. +Pointers +Pixel Shader PS Shader that is supplied by the application, translated by the jitter and is dispatched to + the EU by the Windower (conceptually) once per pixel. +Point -- A drawing object characterized only by position coordinates and width. +Primitive -- Synonym for object: triangle, rectangle, line or point. +Primitive Topology -- A composite primitive such as a triangle strip, or line list. Also includes the objects + triangle, line and point as degenerate cases. +Provoking Vertex -- The vertex of a primitive topology from which vertex attributes that are constant + across the primitive are taken. +Quad Quad word QQ A fundamental data type, QQ represents 32 bytes. +(QQword) + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 11 + Term Abbr. Definition +Quad Word QW A fundamental data type, QW represents 8 bytes. +(QWord) +Rasterization Conversion of an object represented by vertices into the set of pixels that make up + the object. +Region-based -- Collective term for the register addressing modes available in the EU instruction set +addressing that permit discontiguous register data to be fetched and used as a single operand. +Render Cache RC Cache in which pixel color and depth information is written prior to being written to + memory, and where prior pixel destination attributes are read in preparation for + blending and Z test. +Render Target RT A destination surface in memory where render results are written. +Render Target -- Selector of which of several render targets the current operation is targeting. +Array Index +Root Thread -- A root-node thread. A thread corresponds to a root-node in a thread generation + hierarchy. It is a kind of thread associated with the media fixed function pipeline. A + root thread is originated from the VFE unit and forwarded to the Thread Dispatcher by + the TS unit. A root thread may or may not have child threads. A root thread may have + scratch memory managed by TS. A root thread with children has its URB resource + managed by the VFE. +Sampler -- Shared function that samples textures and reads data from buffers on behalf of EU + programs. +Scratch Space -- Memory allocated to the subsystem that is used by EU threads for data storage that + exceeds their register allocation, persistent storage, storage of mask stack entries + beyond the first 16, etc. +Shader -- A program that is supplied by the application in a high level shader language, and + translated to instructions by the jitter. +Shared Function SF Function unit that is shared by EUs. EUs send messages to shared functions; they + consume the data and may return a result. The Sampler, Data Port and Extended + Math unit are all shared functions. +Shared Function ID SFID Unique identifier used by kernels and shaders to target shared functions and to + identify their returned messages. +Single Instruction SIMD The term SIMD can be used to describe the kind of parallel processing architecture +Multiple Data that exploits data parallelism at instruction level. It can also be used to describe the + instructions in such architecture. +Source -- Describes an input or read operand +Spawn -- To initiate a thread for execution on an EU. Done by the thread spawner as well as + most FF units in the 3D Pipeline. +Sprite Point -- Point object using full range texture coordinates. Points that are not sprite points use + the texture coordinates of the point’s center across the entire point object. +State Descriptor -- Blocks in memory that describe the state associated with a particular FF, including its + associated kernel pointer, kernel resource allowances, and a pointer to its surface + state. +State Register SR The read-only registers containing the state information of the current thread, + including the EUID/TID, Dispatcher Mask, and System IP. +State Variable SV An individual state element that can be varied to change the way given primitives are + rendered or media objects processed. On state variables persist only in memory and + are cached as needed by rendering/processing operations except for a small amount + of non-pipelined state. +Stream Output -- A term for writing the output of a FF unit directly to a memory buffer instead of, or in + addition to, the output passing to the next FF unit in the pipeline. Currently only + supported for the Geometry Shader (GS) FF unit. +Strips and Fans SF Fixed function unit whose main function is to decompose primitive topologies such as + strips and fans into primitives or objects. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 12 + Term Abbr. Definition +Sub-Register + Subfield of a SIMD register. A SIMD register is an aligned fixed size register for a + register file or a register type. For example, a GRF register, r2, is 256-bit wide, 256- + bit aligned register. A sub-register, r2.3:d, is the fourth dword of GRF register r2. + +Subsystem -- The name given to the resources shared by the FF units, including shared functions + and EUs. +Surface -- A rendering operand or destination, including textures, buffers, and render targets. +Surface State -- State associated with a render surface including +Surface State Base -- Base address used when referencing binding table and surface state data. +Pointer +Synchronized Root -- A root thread that is dispatched by TS upon a ‘dispatch root thread’ message. +Thread +System IP SIP There is one global System IP register for all the threads. From a thread’s point of + view, this is a virtual read only register. Upon an exception, hardware performs some + bookkeeping and then jumps to SIP. +System Routine -- Sequence of instructions that handles exceptions. SIP is programmed to point to this + routine, and all threads encountering an exception will call it. +Thread An instance of a kernel program executed on an EU. The life cycle for a thread starts + from the executing the first instruction after being dispatched from Thread Dispatcher + to an EU to the execution of the last instruction – a send instruction with EOT that + signals the thread termination. Threads in the system may be independent from each + other or communicate with each other through Message Gateway share function. +Thread Dispatcher TD Functional unit that arbitrates thread initiation requests from Fixed Functions units + and instantiates the threads on EUs. +Thread Identifier TID The field within a thread state register (SR0) that identifies which thread slots on an + EU a thread occupies. A thread can be uniquely identified by the EUID and TID. +Thread Payload Prior to a thread starting execution, some amount of data will be pre-loaded in to the + thread’s GRF (starting at r0). This data is typically a combination of control + information provided by the spawning entity (FF Unit) and data read from the URB. +Thread Spawner TS The second and the last fixed function stage of the media pipeline that initiates new + threads on behalf of generic/media processing. +Topology See Primitive Topology. +Unified Return URB The on-chip memory managed/shared by Fixed Functions in order for a thread to +Buffer return data that will be consumed either by a Fixed Function or other threads. +Unsigned Byte UB A numerical data type of 8 bits. +integer +Unsigned Double UD A numerical data type of 32 bits. It may be used to specify the type of an operand in +Word integer an instruction. +Unsigned Word UW A numerical data type of 16 bits. It may be used to specify the type of an operand in +integer an instruction. +Unsynchronized -- A root thread that is automatically dispatched by TS. +Root Thread +URB Dereference -- +URB Entry UE URB Entry: A logical entity stored in the URB (such as a vertex), referenced via a + URB Handle. +URB Entry -- Number of URB entries allocated to a Fixed Function unit. +Allocation Size +URB Fence Fence Virtual, movable boundaries between the URB regions owned by each FF unit. +URB Handle -- A unique identifier for a URB entry that is passed down a pipeline. +URB Reference -- +Variable Length VLD The first stage of the video decoding pipe that consists mainly of bit-wide operations. +Decode The GPU supports hardware VLD acceleration in the VFE fixed function stage. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 13 + Term Abbr. Definition +VC-1 VC-1 + VC-1 is the informal name of the SMPTE 421M video codec standard +Vertex Buffer VB Buffer in memory containing vertex attributes. +Vertex Cache VC Cache of Vertex URB Entry (VUE) handles tagged with vertex indices. See the VS + chapter for details on this cache. +Vertex Fetcher VF The first FF unit in the 3D Pipeline responsible for fetching vertex data from memory. + Sometimes referred to as the Vertex Formatter. +Vertex Header -- Vertex data required for every vertex appearing at the beginning of a Vertex URB + Entry. +Vertex ID -- Unique ID for each vertex that can optionally be included in vertex attribute data sent + down the pipeline and used by kernel/shader threads. +Vertex Index -- + Offset (in vertex-sized units) of a given vertex in a vertex buffer. Not unique per + vertex instance. + +Vertex Sequence -- + Unique ID for each vertex sent down the south bus . +Number +Vertex Shader VS An API-supplied program that calculates vertex attributes. Also refers to the FF unit + that dispatches threads to “shade” (calculate attributes for) vertices. +Vertex URB Entry VUE A URB entry that contains data for a specific vertex. +Vertical Stride VertStride The distance in element-sized units between 2 vertically-adjacent elements of a + region-based GRF access. +Video Front End VFE The first fixed function in the generic pipeline; performs fixed-function media + operations. +Viewport VP +Windower IZ WIZ Term for Windower/Masker that encapsulates its early (“intermediate”) depth test + function. +Windower/Masker WM Fixed function triangle/line rasterizer. +Word W A numerical data type of 16 bits, W represents a signed word integer. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 14 + 2. Graphics Device Overview +2.1 Graphics Processing Unit (GPU) +The Graphics Processing Unit is controlled by the CPU through a direct interface of memory-mapped IO +registers, and indirectly by parsing commands that the CPU has placed in memory. The display interface +and blitter (block image transferrer) are controlled primarily by direct CPU register addresses, while the +3D and Media pipelines and the parallel Video Codec Engine (VCE) are controlled primarily through +instruction lists in memory. + +The subsystem contains an array of cores, or execution units, with a number of “shared functions”, which +receive and process messages at the request of programs running on the cores. The shared functions +perform critical tasks, such as sampling textures and updating the render target (usually the frame buffer). +The cores themselves are described by an instruction set architecture, or ISA. + +Logical Block Diagram + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 15 + 3. Graphics Processing Engine (GPE) +3.1 Introduction to the GPE +This chapter serves two purposes: +  It provides a high-level description of the Graphics Processing Engine (GPE) of the Graphics + Processing Unit (GPU). +  It also specifies the programming and behaviors of the functions common to both pipelines (3D, + Media) within the GPE. However, details specific to either pipeline are not addressed here. + + +3.2 Overview +The Graphics Processing Engine (GPE) performs the bulk of the graphics processing provided by the +GPU. It consists of the 3D and Media fixed-function pipelines, the Command Streamer (CS) unit that +feeds them, and the Subsystem that provides the bulk of the computations required by the pipelines. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 16 + 3.2.1 Graphics Processing Engine Block Diagram +The Graphics Processing Engine + + + + +3.2.2 Command Stream (CS) Unit +The Command Stream (CS) unit manages the use of the 3D and Media pipelines; it performs switching +between pipelines and forwarding command streams to the currently active pipeline. It manages +allocation of the URB and helps support the Constant URB Entry (CURBE) function. + + +3.2.3 3D Pipeline +The 3D Pipeline provides specialized 3D primitive processing functions. These functions are provided by +a pipeline of “fixed function” stages (units) and threads spawned by these units. See 3D Pipeline +Overview. + + +3.2.4 Media Pipeline +The Media pipeline provides both specialized media-related processing functions and the ability to +perform more general (“generic”) functionality. These Media-specific functions are provided by a Video +Front End (VFE) unit. A Thread Spawner (TS) unit is utilized to spawn threads requested by the VFE +unit, or as required when the pipeline is used for general processing. See Media Pipeline Overview. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 17 + 3.2.5 Subsystem +The Subsystem is the collective name for the programmable cores, the Shared Functions accessed by +them (including the Sampler, Extended Math Unit (“MathBox”), the DataPort, and the Inter-Thread +Communication (ITC) Gateway), and the Dispatcher that manages threads running on the cores. + + +3.2.6 Execution Units (EUs) +While the number of EU cores in the subsystem is almost entirely transparent to the programming model, +there are a few areas where this parameter comes into play: + +  The amount of scratch space required is a function of (#EUs * #Threads/EU) + Device # of EUs #Threads/EU + Ivy Bridge 16 8 + Ivy Bridge 6 6 + + +3.2.7 GPE Function IDs +The following table lists the assignments (encodings) of the Shared Function and Fixed Function IDs +used within the GPE. A Shared Function is a valid target of a message initiated via a ‘send’ instruction. A +Fixed Function is an identifiable unit of the 3D or Media pipeline. Note that the Thread Spawner is both a +Shared Function and Fixed Function. + +Function IDs +ID[3:0] SFID Shared Function FFID Fixed Function + 0x0 SFID_NULL Null FFID_NULL Null + 0x1 Reserved --- Reserved --- + 0x2 SFID_SAMPLER Sampler Reserved --- + 0x3 SFID_GATEWAY Message Gateway Reserved --- + 0x4 SFID_DP_SAMPLER Sampler Cache Data Port FFID_HS Hull Shader + 0x5 SFID_DP_RC Render Cache Data Port FFID_DS Domain Shader + 0x6 SFID_URB URB Reserved --- + 0x7 SFID_SPAWNER Thread Spawner FFID_SPAWNER Thread Spawner + 0x8 SFID_VME Video Motion Estimation FFID_VFE Video Front End + 0x9 SFID_DP_CC Constant Cache Data Port FFID_VS Vertex Shader + 0xA SFID_DP_DC Data Cache Data Port FFID_CS Command Stream + 0xB SFID_PI Pixel Interpolator FFID_VF Vertex Fetch + 0xC Reserved --- FFID_GS Geometry Shader + 0xD Reserved --- FFID_CLIP Clipper Unit + 0xE Reserved --- FFID_SF Strip/Fan Unit + 0xF Reserved --- FFID_WM Windower/Masker Unit + + + +3.3 Pipeline Selection +The PIPELINE_SELECT command is used to specify which GPE pipeline (3D or Media orGPGPU ) is to +be considered the “current” active pipeline. Issuing 3D-pipeline-specific commands when the Media +pipeline is selected, or vice versa, is UNDEFINED. +This command causes the URB deallocation of the previously selected pipe. For example, switching from +the 3D pipe to the Media pipe (either within or between contexts) will cause the CS to send a +“Deallocating Flush” down the 3D pipe, and each 3D FF will start a URB deallocation sequence after the + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 18 + current tasks are done. Then, the WM will de-reference the current Constant URB Entry, and all 3D URB +entries will be deallocated (after some north bus delay) , which allows the CS to set the URB fences for +the media pipe. The process relatively is the same for switching from Media to 3D pipes. The deallocating +flush goes down the Media pipe, causing each Media function to start a URB deallocation sequence, and +the WM will de-reference the current Constant URB entry and all media entries will be de-allocated to +allow the CS to set the 3D pipe. +Programming Restriction: +Software must ensure the current pipeline is flushed via an MI_FLUSH or PIPE_CONTROL prior to the +execution of PIPELINE_SELECT. +DWord Bit Description + 31:29 + 0 Instruction Type = GFXPIPE = 3h + + 28:16 + 3D Instruction Opcode = PIPELINE_SELECT + GFXPIPE[28:27 = 1h, 26:24 = 1h, 23:16 = 04h] (Single DW, Non-pipelined) + + 15:2 Reserved: MBZ + 1: 0 + Pipeline Select + 0: 3D Pipeline is selected + 1: Media pipeline is selected (Includes and generic media workloads) + 2: GPGPU pipeline is selected + 3: Reserved + +The Pipeline Select state is contained within the logical context. + + +3.4 Memory Object Control State +The memory object control state defines behavior of memory accesses beyond the graphics core, +graphics data type that allows selective flushing of data from outer caches, and ability to control +cacheability in the outer caches. +This control uses several mechanisms. Control state for all memory accesses can be defined page by +page in the GTT entries. Memory objects that are defined by state per surface generally have additional +memory object control state in the state structure that defines the other surface attributes. Memory +objects without state defining them have memory object state control defined per class in the +STATE_BASE_ADDRESS command, with class divisions the same as the base addresses. Finally, some +memory objects only have the GTT entry mechanism for defining this control. The table below +enumerates the memory objects and location the the control state for each: + Memory Object Location of Control State +surfaces defined by SURFACE_STATE: sampling engine surfaces, SURFACE_STATE +render targets, media surfaces, pull constant buffers, streamed vertex +buffers +depth, stencil, and hierarchical depth buffers corresponding state command that defined + the buffer attributes +stateless buffers accessed by data port STATE_BASE_ADDRESS +indirect state objects STATE_BASE_ADDRESS +kernel instructions STATE_BASE_ADDRESS +push constant buffers 3DSTATE_CONSTANT_(VS | GS | PS) +index buffers 3DSTATE_INDEX_BUFFER + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 19 + Memory Object Location of Control State +vertex buffers 3DSTATE_VERTEX_BUFFERS +indirect media object STATE_BASE_ADDRESS +generic state prefetch GTT control only +ring/batch buffers GTT control only +context save buffers GTT control only +store dword GTT control only + + +3.4.1 MEMORY_OBJECT_CONTROL_STATE + + + MEMORY_OBJECT_CONTROL_STATE + +Default Value: 0x00000000 +DWord Bit Description +0 2 Graphics Data Type (GFDT) + Format: U1 + + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is ignored + for reads. + + The GFDT bit is stored in the LLC and selective cache flushing of lines with GFDT set is supported. It is + intended to be set on displayable data, which enables efficient flushing of data to be displayed after + rendering, since display engine does not snoop the rendering caches. Note that MLC would need to be + completely flushed as it does not allow selective flushing. + + 1 LLC Cacheability Control (LLCCC) + + This is the field used in GT interface block to determine what type of access need to be generated to + uncore. For the cases where the LLCCC is set, cacheable transaction are generated to enable LLC + usage for particular stream. + + 0: use cacheability controls from GTT entry + + 1: Data is cached in LLC + 0 L3 Cacheability Control (L3CC) + + This field is used to control the L3 cacheability (allocation) of the stream. + + 0: not cacheable within L3 + + 1: cacheable in L3 + + Note: even if the surface is not cacheable in L3, it is still kept coherent with L3 content. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 20 + 3.5 Memory Access Indirection +The GPE supports the indirection of certain graphics (GTT-mapped) memory accesses. This support +comes in the form of two base address state variables used in certain memory address computations with +the GPE. +The intent of this functionality is to support the dynamic relocation of certain driver-generated memory +structures after command buffers have been generated but prior to the their submittal for execution. For +example, as the driver builds the command stream it could append pipeline state descriptors, kernel +binaries, etc. to a general state buffer. References to the individual items would be inserting in the +command buffers as offsets from the base address of the state buffer. The state buffer could then be +freely relocated prior to command buffer execution, with the driver only needing to specify the final base +address of the state buffer. Two base addresses are provided to permit surface-related state (binding +tables, surface state tables) to be maintained in a state buffer separate from the general state buffer. +While the use of these base addresses is unconditional, the indirection can be effectively disabled by +setting the base addresses to zero. The following table lists the various GPE memory access paths and +which base address (if any) is relevant. + +Base Address Utilization +Base Address Used Memory Accesses +General State Base +Address + + DataPort memory accesses resulting from ‘stateless’ DataPort Read/Write requests. See + DataPort for a definition of the ‘stateless’ form of requests. + Sampler reads of SAMPLER_STATE data and associated +Dynamic State Base + SAMPLER_BORDER_COLOR_STATE. +Address only + Viewport states used by CLIP, SF, and WM/CC + COLOR_CALC_STATE, DEPTH_STENCIL_STATE, and BLEND_STATE + Push Constants (depeding on state of INSTPM ) + Normal EU instruction stream (non-system routine) +Instruction Base + System routine EU instruction stream (starting address = SIP) +Address only +Surface State Base Sampler and DataPort reads of BINDING_TABLE_STATE, as referenced by BT pointers +Address passed via 3DSTATE_BINDING_TABLE_POINTERS + Sampler and DataPort reads of SURFACE_STATE data +Indirect Object Base MEDIA_OBJECT Indirect Data accessed by the CS unit . +Address +None CS unit reads from Ring Buffers, Batch Buffers + + CS writes resulting from PIPE_CONTROL command + All VF unit memory accesses (Index Buffers, Vertex Buffers) + All Sampler Surface Memory Data accesses (texture fetch, etc.) + All DataPort memory accessesexcept ‘stateless’ DataPort Read/Write requests (e.g., RT + accesses.) See DataPort for a definition of the ‘stateless’ form of requests. + Memory reads resulting from STATE_PREFETCH commands + Any physical memory access by the device + GTT-mapped accesses not included above (i.e., default) + Push Constants (depeding on state of INSTPM ) + +The following notation is used in the BSpec to distinguish between addresses and offsets: + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 21 + Notation Definition +PhysicalAddress[n:m] Corresponding bits of a physical graphics memory byte address (not mapped by a GTT) +GraphicsAddress[n:m] Corresponding bits of an absolute, virtual graphics memory byte address (mapped by a + GTT) +GeneralStateOffset[n:m] Corresponding bits of a relative byte offset added to the General State Base Address + value, the result of which is interpreted as a virtual graphics memory byte address + (mapped by a GTT) +DynamicStateOffset[n:m] Corresponding bits of a relative byte offset added to the Dynamic State Base Address + value, the result of which is interpreted as a virtual graphics memory byte address + (mapped by a GTT) +InstructionBaseOffset[n:m] Corresponding bits of a relative byte offset added to the Instruction Base Address value, + the result of which is interpreted as a virtual graphics memory byte address (mapped by a + GTT) +SurfaceStateOffset[n:m] Corresponding bits of a relative byte offset added to the Surface State Base Address + value, the result of which is interpreted as a virtual graphics memory byte address + (mapped by a GTT) + + +3.5.1 STATE_BASE_ADDRESS +The STATE_BASE_ADDRESS command sets the base pointers for subsequent state, instruction, and +media indirect object accesses by the GPE. (See Memory Access Indirection for details) +Programming Notes: + +  The following commands must be reissued following any change to the base addresses: + o 3DSTATE_PIPELINE_POINTERS + o 3DSTATE_BINDING_TABLE_POINTERS + o MEDIA_STATE_POINTERS. + +  Execution of this command causes a full pipeline flush, thus its use should be minimized for higher + performance. + + + STATE_BASE_ADDRESS + +Length Bias: 2 + +The STATE_BASE_ADDRESS command sets the base pointers for subsequent state, instruction, and media +indirect object accesses by the GPE. (See Table: Base Address Utilization for details) + Programming Notes + +The following commands must be reissued following any change to the base addresses +  3DSTATE_CC_POINTERS +  3DSTATE_BINDING_TABLE_POINTERS +  3DSTATE_SAMPLER_STATE_POINTERS +  3DSTATE_VIEWPORT_STATE_POINTERS +  MEDIA_STATE_POINTERS + +Execution of this command causes a full pipeline flush, thus its use should be minimized for higher performance + +DWord Bit Description +0 31:29 Command Type + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 22 + STATE_BASE_ADDRESS + Default Value: 3h GFXPIPE + 28:27 Command SubType + Default Value: 0h GFXPIPE_COMMON + 26:24 3D Command Opcode + Default Value: 1h GFXPIPE_NONPIPELINED + 23:16 3D Command Sub Opcode + Default Value: 01h STATE_BASE_ADDRESS + 15:8 Reserved + + Format: MBZ + 7:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Description + 8h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 31:12 General State Base Address + + Format: GraphicsAddress[31:12] + Specifies the 4K-byte aligned base address for general state accesses. See Table 4-3 for details on + where this base address is used. + + 11:8 General State Memory Object Control State + + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for indirect state using the General State Base Address, with + the exception of the stateless data port accesses. + + 7:4 Stateless Data Port Access Memory Object Control State + + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for stateless data port accesses. + + 3 Stateless Data Port Access Force Write Thru + + Format: U1 + + 0: If the stateless data port access memory object control indicates L3 cachable the accesses will be + write back cacheable. + + 1: If the stateless data port access memory object control indicates L3 cachable the accesses will be + write thru cacheable. + + 2:1 Reserved + + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 23 + STATE_BASE_ADDRESS + 0 General State Base Address Modify Enable + + Format: Enable + The other fields in this dword are updated only when this bit is set. + Value Name Description Project + 0h Disable Ignore the updated address + 1h Enable Modify the address +2 31:12 Surface State Base Address + + Format: GraphicsAddress[31:12] + Specifies the 4K-byte aligned base address for binding table and surface state accesses. See Table 4- + 3 for details on where this base address is used. + + 11:8 Surface State Memory Object Control State + Project: All + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for indirect state using the Surface State Base Address. + + 7:1 Reserved + + Format: MBZ + 0 Surface State Base Address Modify Enable + + Format: Enable + The other fields in this dword are updated only when this bit is set. + Value Name Description Project + 0h Disable Ignore the updated address + 1h Enable Modify the address +3 31:12 Dynamic State Base Address + + Format: GraphicsAddress[31:12] + Specifies the 4K-byte aligned base address for sampler and viewport state accesses. See Table 4-3 for + details on where this base address is used. + + 11:8 Dynamic State Memory Object Control State + Project: All + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for indirect state using the Dynamic State Base Address. + Push constants defined in 3DSTATE_CONSTANT_(VS | GS | PS) commands do not use this control + state, although they can use the corresponding base address. The memory object control state for + push constants is defined within the command. + + 7:1 Reserved + Project: All + Format: MBZ + 0 Dynamic State Base Address Modify Enable + Project: All + Format: Enable + The other fields in this dword are updated only when this bit is set. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 24 + STATE_BASE_ADDRESS + Value Name Description Project + 0h Disable Ignore the updated address All + 1h Enable Modify the address All +4 31:12 Indirect Object Base Address + Project: All + Format: GraphicsAddress[31:12] + Specifies the 4K-byte aligned base address for indirect object load in MEDIA_OBJECT command. See + Table 4-3 for details on where this base address is used. + + 11:8 Indirect Object Memory Object Control State + Project: All + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for indirect objects using the Indirect Object Base Address. + + 7:1 Reserved + Project: All + Format: MBZ + 0 Indirect Object Base Address Modify Enable + Project: All + Format: Enable + The other fields in this dword are updated only when this bit is set. + Value Name Description Project + 0h Disable Ignore the updated address All + 1h Enable Modify the address All +5 31:12 Instruction Base Address + Project: All + Format: GraphicsAddress[31:12] + Specifies the 4K-byte aligned base address for all EU instruction accesses. + + 11:8 Instruction Memory Object Control State + Project: All + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for EU instructions using the Instruction Base Address. + + 7:1 Reserved + Project: All + Format: MBZ + 0 Instruction Base Address Modify Enable + Project: All + Format: Enable + The other fields in this dword are updated only when this bit is set. + Value Name Description Project + 0h Disable Ignore the updated address All + 1h Enable Modify the address All +6 31:12 General State Access Upper Bound + Project: All + Format: GraphicsAddress[31:12] + + Specifies the 4K-byte aligned (exclusive) maximum Graphics Memory address for + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 25 + STATE_BASE_ADDRESS + general state accesses. This includes all accesses that are offset from + General State Base Address (see Table 4-3). Read accesses from this address + and beyond will return UNDEFINED values. Data port writes to this address and beyond + will be “dropped on the floor” (all data channels will be disabled so no writes occur). + Setting this field to 0 will cause this range check to be ignored. + + + + + If non-zero, this address must be greater than the General State Base Address. + + 11:1 Reserved + Project: All + Format: MBZ + 0 General State Access Upper Bound Modify Enable + Project: All + Format: Enable + The bound in this dword is updated only when this bit is set. + Value Name Description Project + 0h Disable Ignore the updated bound All + 1h Enable Modify the bound All +7 31:12 Dynamic State Access Upper Bound + Project: All + Format: GraphicsAddress[31:12] + + Specifies the 4K-byte aligned (exclusive) maximum Graphics Memory address for dynamic state + accesses. This includes all accesses that are offset from Dynamic State Base Address (see Table 4- + 3). Read accesses from this address and beyond will return UNDEFINED values. Data port writes to + this address and beyond will be “dropped on the floor” (all data channels will be disabled so no writes + occur). Setting this field to 0 will cause this range check to be ignored. + + If non-zero, this address must be greater than the Dynamic State Base Address. + + 11:1 Reserved + Project: All + Format: MBZ + 0 Dynamic State Access Upper Bound Modify Enable + Project: All + Format: Enable + The bound in this dword is updated only when this bit is set. + Value Name Description Project + 0h Disable Ignore the updated bound All + 1h Enable Modify the bound All +8 31:12 Indirect Object Access Upper Bound + Project: All + Format: GraphicsAddress[31:12] + + This field specifies the 4K-byte aligned (exclusive) maximum Graphics Memory address access by an + indirect object load in a MEDIA_OBJECT command. Indirect data accessed at this address and + beyond will appear to be 0. Setting this field to 0 will cause this range check to be ignored. + + If non-zero, this address must be greater than the Indirect Object Base Address. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 26 + STATE_BASE_ADDRESS + Hardware ignores this field if indirect data is not present. + + Setting this field to FFFFFh will cause this range check to be ignored. + + 11:1 Reserved + Project: All + Format: MBZ + 0 Indirect Object Access Upper Bound Modify Enable + Project: All + Format: Enable + The bound in this dword is updated only when this bit is set. + Value Name Description Project + 0h Disable Ignore the updated bound All + 1h Enable Modify the bound All +9 31:12 Instruction Access Upper Bound + Project: All + Format: GraphicsAddress[31:12] + + This field specifies the 4K-byte aligned (exclusive) maximum Graphics Memory address access by an + EU instruction. Instruction data accessed at this address and beyond will return UNDEFINED values. + Setting this field to 0 will cause this range check to be ignored. + + If non-zero, this address must be greater than the Instruction Base Address. + + 11:1 Reserved + Project: All + Format: MBZ + 0 Instruction Access Upper Bound Modify Enable + Project: All + Format: Enable + The bound in this dword is updated only when this bit is set. + Value Name Description Project + 0h Disable Ignore the updated bound All + 1h Enable Modify the bound All + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 27 + 3.5.2 SWTESS_BASE_ADDRESS +The SWTESS_BASE_ADDRESS command sets the base pointers for SW Tessellation data read +accesses by the TE unit. + + SWTESS_BASE_ADDRESS + +Length Bias: 2 +The SWTESS_BASE_ADDRESS command sets the base pointers for SW Tessellation data read access by the TE +unit. + Programming Notes + + This base address must also be comprehended in the SURFACE_STATE used by the HS kernel to write the SW + tessellation data. + + Execution of this command causes a full pipeline flush, thus its use should be minimized for higher performance. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + 28:27 Command SubType + Default Value: 0h GFXPIPE_COMMON + 26:24 3D Command Opcode + Default Value: 1h GFXPIPE_NONPIPELINED + 23:16 3D Command Sub Opcode + Default Value: 03h SWTESS_BASE_ADDRESS + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Description + 0h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 31:12 SW Tessellation Base Address [31:12] + Project: All + Format: GraphicsAddress[31:12] + Specifies the 4K-byte aligned base address for TE unit SW tessellation data read accesses. + + 11:8 SW Tessellation Memory Object Control State + Project: All + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state used by the TE unit to read SW tessellation data from + memory. + + 7:0 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 28 + SWTESS_BASE_ADDRESS + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 29 + 3.6 Instruction and State Prefetch +The STATE_PREFETCH command is provided strictly as an optional mechanism to possibly enhance +pipeline performance by prefetching data into the GPE’s Instruction and State Cache (ISC). + + +3.6.1 STATE_PREFETCH + + STATE_PREFETCH +Project: All +Length Bias: 2 + +(This command is provided strictly for performance optimization opportunities, and likely requires some +experimentation to evaluate the overall impact of additional prefetching.) + + The STATE_PREFETCH command causes the GPE to attempt to prefetch a sequence of 64-byte cache lines into + the GPE-internal cache (“L2 ISC”) used to access EU kernel instructions and fixed/shared function indirect state + data. While state descriptors, surface state, and sampler state are automatically prefetched by the GPE, this + command may be used to prefetch data not automatically prefetched, such as: 3D viewport state; Media pipeline + Interface Descriptors; EU kernel instructions. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + 28:27 Command SubType + Default Value: 0h GFXPIPE_COMMON + 26:24 3D Command Opcode + Default Value: 0h GFXPIPE_PIPELINED + 23:16 3D Command Sub Opcode + Default Value: 03h STATE_PREFETCH + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Description + 0h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 31:6 Prefetch Pointer + Project: All + Format: GraphicsAddress[31:6] + Specifies the 64-byte aligned address to start the prefetch from. This pointer is an absolute virtual + address, it is not relative to any base pointer. + 5:3 Reserved + Project: All + Format: MBZ + 2:0 Prefetch Count + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 30 + STATE_PREFETCH + Project: All + Format: U3-1 count of cache lines + + + Indicates the number of contiguous 64-byte cache lines that will be prefetched. + Value Name Description + [0,7] indicating a count of [1,8] + + + + +3.7 System Thread Configuration + +3.7.1 STATE_SIP + + STATE_SIP +Project: All +Length Bias: 2 +The STATE_SIP command specifies the starting instruction location of the System Routine that is shared by all +threads in execution. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + 28:27 Command SubType + Default Value: 0h GFXPIPE_COMMON + 26:24 3D Command Opcode + Default Value: 1h GFXPIPE_NONPIPELINED + 23:16 3D Command Sub Opcode + Default Value: 02h STATE_SIP + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Description Project + 0h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 31:4 System Instruction Pointer (SIP) + + Format: InstructionBaseOffset[31:4]Kernel + Specifies the instruction address of the system routine associated with the current context as a 128-bit + granular offset from the Instruction Base Address. SIP is shared by all threads in execution. The + address specifies the double quadword aligned instruction location. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 31 + STATE_SIP + 3:0 Reserved + Project: All + Format: MBZ + + + + +3.8 Command Ordering Rules +There are several restrictions regarding the ordering of commands issued to the GPE. This subsection +describes these restrictions along with some explanation of why they exist. Refer to the various command +descriptions for additional information. + +The following flowchart illustrates an example ordering of commands which can be used to perform +activity within the GPE. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 32 + 3.8.1 PIPELINE_SELECT +The previously-active pipeline needs to be flushed via the MI_FLUSH command immediately before +switching to a different pipeline via use of the PIPELINE_SELECT command. Refer to GPE Function IDs +for details on the PIPELINE_SELECT command. + + PIPELINE_SELECT + +Length Bias: 1 +The PIPELINE_SELECT command is used to specify which GPE pipeline (3D or Media or GPGPU) is to be +considered the "current" active pipeline. Issuing 3D-pipeline-specific commands when the Media pipeline is selected, +or vice versa, is UNDEFINED. This command causes the URB deallocation of the previously selected pipe. For +example, switching from the 3D pipe to the Media pipe (either within or between contexts) will cause the CS to send +a "Deallocating Flush" down the 3D pipe, and each 3D FF will start a URB deallocation sequence after the current +tasks are done. Then, the WM will de-reference the current Constant URB Entry, and all 3D URB entries will be +deallocated (after some north bus delay) , which allows the CS to set the URB fences for the media pipe. The +process relatively is the same for switching from Media to 3D pipes. The deallocating flush goes down the Media +pipe, causing each Media function to start a URB deallocation sequence, and the WM will de-reference the current +Constant URB entry and all media entries will be de-allocated to allow the CS to set the 3D pipe. + Programming Notes Project +Software must ensure the current pipeline is flushed via an MI_FLUSH or PIPE_CONTROL prior to the +execution of PIPELINE_SELECT. +Software must send a dummy DRAW after every MI_SET_CONTEXT and after any PIPELINE_SELECT that +is enabling 3D mode. A dummy draw is a 3DPRIMITIVE command with Indirect Parameter Enable set to 0, +UAV Coherency Required set to 0, Predicate Enable set to 0, End Offset Enable set to 0, and Vertex Count +Per Instance set to 0. All other parameters are a don't care. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + 28:27 Command SubType + Default Value: 1h GFXPIPE_COMMON + 26:24 3D Command Opcode + Value Name Project + 1h GFXPIPE_NONPIPELINED [Default] + 23:16 3D Command Sub Opcode + Default Value: 04h GFXPIPE + 15:2 Reserved + 1:0 Pipeline Select + Value Name Description + 0 3D 3D pipeline is selected + 1 Media Media pipeline is selected (Includes HD Video playback and generic media + workloads) + + + + +3.8.2 PIPE_CONTROL +The PIPE_CONTROL command does not require URB fencing/allocation to have been performed, nor +does it rely on any other pipeline state. It is intended to be used on both the 3D pipe and the Media pipe. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 33 + It has special optimizations to support the pipelining capability in the 3D pipe which do not apply to the +Media pipe. + + +3.8.3 URB-Related State-Setting Commands +Several commands are used (among other things) to set state variables used in URB entry allocation --- +specifically, the Number of URB Entries and the URB Entry Allocation Size state variables associated +with various pipeline units. These state variables must be set-up prior to the issuing of a URB_FENCE +command. (See the subsection on URB_FENCE.) +CS_URB_STATE (only) specifies these state variables for the common CS FF unit. +3DSTATE_PIPELINED_POINTERs sets the state variables for FF units in the 3D Pipeline, and +MEDIA_STATE_POINTERS sets them for the Media pipeline. Depending on which pipeline is currently +active, only one of these commands needs to be used. Note that these commands can also be reissued +at a later time to change other state variables, though if a change is made to (a) any Number of URB +Entries and the URB Entry Allocation Size state variables or (b) the Maximum Number of Threads +state for the GS or CLIP FF units, a URB_FENCE command must follow. + + +3.8.4 Common Pipeline State-Setting Commands +The following commands are used to set state common to both the 3D and Media pipelines. This state is +comprised of CS FF unit state, non-pipelined global state (EU, etc.), and Sampler shared-function state. + +  STATE_BASE_ADDRESS +  STATE_SIP +  3DSTATE_SAMPLER_PALETTE_LOAD +  3DSTATE_CHROMA_KEY + +The state variables associated with these commands must be set appropriately prior to initiating activity +within a pipeline (i.e., 3DPRIMITIVE or MEDIA_OBJECT). + + +3.8.5 3D Pipeline-Specific State-Setting Commands +The following commands are used to set state specific to the 3D Pipeline. + +  3DSTATE_PIPELINED_POINTERS +  3DSTATE_BINDING_TABLE_POINTERS +  3DSTATE_VERTEX_BUFFERS +  3DSTATE_VERTEX_ELEMENTS +  3DSTATE_INDEX_BUFFERS +  3DSTATE_VF_STATISTICS +  3DSTATE_DRAWING_RECTANGLE +  3DSTATE_CONSTANT_COLOR +  3DSTATE_DEPTH_BUFFER +  3DSTATE_POLY_STIPPLE_OFFSET +  3DSTATE_POLY_STIPPLE_PATTERN +  3DSTATE_LINE_STIPPLE +  3DSTATE_GLOBAL_DEPTH_OFFSET + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 34 + The state variables associated with these commands must be set appropriately prior to issuing +3DPRIMITIVE. + + +3.8.6 Media Pipeline-Specific State-Setting Commands +The following command is used to set state specific to the Media pipeline: + +  MEDIA_STATE_POINTERS + +The state variables associated with this command must be set appropriately prior to issuing +MEDIA_OBJECT. + + +3.8.7 CONSTANT_BUFFER (CURBE Load) +The CONSTANT_BUFFER command is used to load constant data into the CURBE URB entries owned +by the CS unit. In order to write into the URB, CS URB fencing and allocation must have been +established. Therefore, CONSTANT_BUFFER can only be issued after CS_URB_STATE and +URB_FENCE commands have been issued, and prior to any other pipeline processing (i.e., +3DPRIMITIVE or MEDIA_OBJECT). See the definition of CONSTANT_BUFFER for more details. +Modifying the CS URB allocation via URB_FENCE invalidates any previous CURBE entries. Therefore +software must subsequently [re]issue a CONSTANT_BUFFER command before CURBE data can be +used in the pipeline. + + +3.8.8 3DPRIMITIVE +Before issuing a 3DPRIMITIVE command, all state (with the exception of MEDIA_STATE_POINTERS) +needs to be valid. Thus the commands used to assigned that state must be issued before issuing +3DPRIMITIVE. + + +3.8.9 MEDIA_OBJECT +Before issuing a MEDIA_OBJECT command, all state (with the exception of 3D-pipeline-specific state) +needs to be valid. Therefore the commands used to set this state need to have been issued at some point +prior to the issue of MEDIA_OBJECT. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 35 + 4. Video Codec Engine +The parallel Video Codec Engine (VCE) is a fixed function video decoder and encoder engine. It is also +referred to as the multi-format codec (MFX) engine, as a unified fixed function pipeline is implemented to +support multiple video coding standards such as MPEG2, VC1 and AVC. + +  VCS – VCE Command Streamer unit (also referred to as BCS) +  BSD – Bitstream Decoder unit +  VDS – Video Dispatcher unit +  VMC – Video Motion Compensation unit +  VIP – Video Intra Prediction unit +  VIT – Video Inverse Transform unit +  VLF – Video Loop Filter unit +  VFT – Video Forward Transform unit (encoder only) +  BSC – Bitstream Encoder unit (encoder only) + + +4.1 Video Command Streamer (VCS) +VCS (Video Command Streamer) unit is primarily served as the software programming interface between +the O/S driver and the MFD Engine. It is responsible for fetching, decoding, and dispatching of data +packets (Media Commands with the header DW removed) to the front end interface module of MFX +Engine. +Its logic functions include + +  MMIO register programming interface. +  Management of the Head pointer for the Ring Buffer. +  Decode of ring data and sending it to the appropriate destination; AVC, VC1 or MPEG2 engine +  Handling of user interrupts and ring context switch interrupt. +  Flushing the MFX Engine +  Handle NOP + +The register programming (RM) bus is a dword interface bus that is driven by the Gx Command Streamer. +The VCS unit will only claim memory mapped I/O cycles that are targeted to its range of 0x4000 to +0x4FFFF. The Gx and MFX Engines use semaphore to synchronize their operations. +Any interaction and control protocols between the VCS and Gx CS in IronLake will remain the same as in +Cantiga. But in Gesher, VCS will operate completely independent of the Gx CS. +The simple sequence of events is as follows: a ring (say PRB0) is programmed by a memory-mapped +register write cycle. The DMA inside VCS is kicked off. The DMA fetches commands from memory based +on the starting address and head pointer. The DMA requests cache lines from memory (one cacheline CL +at a time). There is guaranteed space in the DMA FIFO (16 CL deep) for data coming back from memory. +The DMA control logic has copies of the head pointer and the tail pointer. The DMA increments the head +pointer after making requests for ring commands. Once the DMA copy of the head pointer becomes equal +to the tail pointer, the DMA stops requesting. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 36 + The parser starts executing once the DMA FIFO has valid commands. All the commands have a header +dword packet. Based on the encoding in the header packet, the command may be targeted towards +AVC/VC1/MPEG2 engine or the command parser. After execution of every command, the actual head +pointer is updated. The ring is considered empty when the head pointer becomes equal to the tail pointer. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 37 + 5. Graphics Command Formats +5.1 Command Formats +This section describes the general format of the graphics device commands. +Graphics commands are defined with various formats. The first DWord of all commands is called the +header DWord. The header contains the only field common to all commands -- the client field that +determines the device unit that will process the command data. The Command Parser examines the +client field of each command to condition the further processing of the command and route the command +data accordingly. +Some devices include two Command Parsers, each controlling an independent processing engine. These +will be referred to in this document as the Render Command Parser (RCP) and the Video Codec +Command Parser (VCCP). +Valid client values for the Render Command Parser are: +Client # Client + 0 Memory Interface (MI_xxx) + 1 + Miscellaneous + 2 2D Rendering (xxx_BLT_xxx) + 3 Graphics Pipeline (3D and Media) + 4-7 Reserved + +Valid client values for the Video Codec Command Parser are: +Client # Client + 0 Memory Interface (MI_xxx) + 1-2 Reserved + 3 AVC and VC1 State and Object Commands + 4-7 Reserved + +Graphics commands vary in length, though are always multiples of DWords. The length of a command is +either: +  Implied by the client/opcode +  Fixed by the client/opcode yet included in a header field (so the Command Parser + explicitly knows how much data to copy/process) +  Variable, with a field in the header indicating the total length of the command +Note that command sequences require QWord alignment and padding to QWord length to be placed in +Ring and Batch Buffers. +The following subsections provide a brief overview of the graphics commands by client type provides a +diagram of the formats of the header DWords for all commands. Following that is a list of command +mnemonics by client type. + + +5.1.1 Memory Interface Commands +Memory Interface (MI) commands are basically those commands which do not require processing by the +2D or 3D Rendering/Mapping engines. The functions performed by these commands include: + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 38 + Control of the command stream (e.g., Batch Buffer commands, breakpoints, ARB On/Off, etc.) + Hardware synchronization (e.g., flush, wait-for-event) + Software synchronization (e.g., Store DWORD, report head) + Graphics buffer definition (e.g., Display buffer, Overlay buffer) + Miscellaneous functions +Refer to the Memory Interface Commands chapter for a description of these commands. + + +5.1.2 2D Commands +The 2D commands include various flavors of BLT operations, along with commands to set up BLT engine +state without actually performing a BLT. Most commands are of fixed length, though there are a few +commands that include a variable amount of "inline" data at the end of the command. +See the 2D Commands chapter for a description of these commands. + + +5.1.3 3D/Media Commands +The 3D/Media commands are used to program the graphics pipelines for 3D or media operations. +Refer to the 3D chapter for a description of the 3D state and primitive commands and the Media chapter +for a description of the media-related state and object commands. + + +5.1.4 Video Codec Commands + +5.1.4.1 MFX Commands +The MFX (MFD for decode and MFC for encode) commands are used to program the multi-format codec +engine attached to the Video Codec Command Parser. See the MFD and MFC chapters for a description +of these commands. + + +5.1.5 Command Header +RCP Command Header Format + Bits + TYPE 31:29 28:24 23 22 21:0 + 000 +Memory Opcode Identification No./DWord Count +Interface 00h – NOP Command Dependent Data +(MI) 0Xh – Single DWord 5:0 – DWord Count + Commands + 5:0 – DWord Count + 1Xh – Two+ DWord Commands + 5:0 – DWord Count + 2Xh – Store Data Commands + 3Xh – Ring/Batch Buffer Cmds +Reserved 001 Opcode – 11111 + 23:19 18:16 15:0 + Sub Opcode 00h – Re-served DWord Count + + + + +Intel Confidential 6/21/2012 39 + Bits + TYPE 31:29 28:24 23 22 21:0 + 01h +2D 010 Opcode + Command Dependent Data + 4:0 – DWord Count + TYPE 31:29 28:27 26:24 23:16 15:8 7:0 +Common 011 00 Opcode – 000 Sub Opcode Data DWord Count +Common (NP) 011 00 Opcode – 001 Sub Opcode Data DWord Count +Reserved 011 00 Opcode – 010 – 111 +Single Dword 011 01 Opcode – 000 – 001 Sub Opcode N/A +Command +Reserved 011 01 Opcode – 010 – 111 +Media State 011 10 Opcode – 000 Sub Opcode Dword Count +Media Object 011 10 Opcode – 001 – 010 Sub Opcode Dword Count +Reserved 011 10 Opcode – 011 – 111 +3DState 011 11 Opcode – 000 Sub Opcode Data DWord Count +3DState (NP) 011 11 Opcode – 001 Sub Opcode Data DWord Count +PIPE_Control 011 11 Opcode – 010 Data DWord Count +3DPrimitive 011 11 Opcode – 011 Data DWord Count +Reserved 011 11 Opcode – 100 – 111 +Reserved 100 XX +Reserved 101 XX +Reserved 110 XX + 111 XX +Fulsim2 + +Notes: +1. The qualifier “NP” indicates that the state variable is non-pipelined and the render pipe is flushed + before such a state variable is updated. The other state variables are pipelined (default). +2. [31:29] == '111' is reserved for fulsim command decodings. It is invalid for HW to parse this + command. + +VCCP Command Header Format + Bits + TYPE 31:29 28:24 23 22 21:0 + 000 +Memory Opcode Identification No./DWord Count +Interface 00h – NOP Command Dependent Data +(MI) 0Xh – Single DWord Commands 5:0 – DWord Count + 1Xh – Reserved 5:0 – DWord Count + 2Xh – Store Data Commands 5:0 – DWord Count + 3Xh – Ring/Batch Buffer Cmds + TYPE 31:29 28:27 26:24 23:16 15:0 +Reserved 011 00 XXX XX +MFX Single DW 011 01 000 Opcode: 0h 0 +Reserved 011 01 1XX +Reserved 011 10 0XX +AVC State 011 10 100 Opcode: 0h – 4h DWord Count + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 40 + Bits + TYPE 31:29 28:24 23 22 21:0 +AVC Object 011 10 100 Opcode: 8h DWord Count +VC1 State 011 10 101 Opcode: 0h – 4h DWord Count +VC1 Object 011 10 101 Opcode: 8h DWord Count +Reserved 011 10 11X +Reserved 011 11 XXX + TYPE 31:29 28:27 26:24 23:21 20:16 15:0 +MFX Common 011 10 000 000 subopcode DWord Count +Reserved 011 10 000 001-111 subopcode DWord Count +AVC Common 011 10 001 000 subopcode DWord Count +AVC Dec 011 10 001 001 subopcode DWord Count +AVC Enc 011 10 001 010 subopcode DWord Count +Reserved 011 10 001 011-111 subopcode DWord Count +Reserved (for VC1 Common) 011 10 010 000 subopcode DWord Count +VC1 Dec 011 10 010 001 subopcode DWord Count +Reserved (for VC1 Enc) 011 10 010 010 subopcode DWord Count +Reserved 011 10 010 011-111 subopcode DWord Count +Reserved (MPEG2 Common) 011 10 011 000 subopcode DWord Count +MPEG2 Dec 011 10 011 001 subopcode DWord Count +Reserved (for MPEG2 Enc) 011 10 011 010 subopcode DWord Count +Reserved 011 10 011 011-111 subopcode DWord Count +Reserved 011 10 100-111 XXX + + + +5.2 Command Map +This section provides a map of the graphics command opcodes. + + +5.2.1 Memory Interface Command Map +All the following commands are defined in Memory Interface Commands. + +Memory Interface Commands for RCP + Pipe + Blitter + Opcode + (28:23) Command Render + 1-DWord +00h MI_NOOP All All All + All +01h +02h MI_USER_INTERRUPT All All All + All +03h MI_WAIT_FOR_EVENT All All All + All +04h All +05h MI_ARB_CHECK All All All + All + +06h +07h MI_REPORT_HEAD All All All + All + + + + +Intel Confidential 6/21/2012 41 + Pipe + Blitter + Opcode + (28:23) Command Render + 1-DWord +08h + MI_ARB_ON_OFF + +0Ah MI_BATCH_BUFFER_END All All All + All +0Bh MI_SUSPEND_FLUSH +0Ch MI_PREDICATE +0Dh MI_TOPOLOGY_FILTER +0Eh MI_SET_APPID + + 2+ DWord +10h Reserved +11h + Reserved +12h + Reserved + +13h + Reserved +14h All + MI_DISPLAY_FLIP +15h Reserved +16h + MI_SEMAPHORE_MBOX +17h Reserved +18h MI_SET_CONTEXT All +19h +1Ah MI_MATH +1Dh–1Fh Reserved + Store Data +20h MI_STORE_DATA_IMM All All All All +21h MI_STORE_DATA_INDEX All All All All +22h MI_LOAD_REGISTER_IMM All All All All +23h + MI_UPDATE_GTT + +24h MI_STORE_REGISTER_MEM All All All All +25h +26h + MI_FLUSH_DW +27h + MI_CLFLUSH +28h + MI_REPORT_PERF_COUNT +29h + MI_LOAD_REGISTER_MEM + +2Ah +2Bh +2Ch +2Dh + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 42 + Pipe + Blitter + Opcode + (28:23) Command Render + 1-DWord +2Eh +2Fh + Ring/Batch Buffer +30h Reserved +31h MI_BATCH_BUFFER_START All All All All +32h–35h Reserved +36h + MI_CONDITIONAL_BATCH_BUFFER_ + END + +37h–3Fh Reserved + + +5.2.2 2D Command Map +All the following commands are defined in Blitter Instructions. + +2D Command Map + Opcode (28:22) Command +00h Reserved +01h XY_SETUP_BLT +02h Reserved +03h XY_SETUP_CLIP_BLT +04h-10h Reserved +11h XY_SETUP_MONO_PATTERN_SL_BLT +12h-23h Reserved +24h XY_PIXEL_BLT +25h XY_SCANLINES_BLT +26h XY_TEXT_BLT +27h-30h Reserved +31h XY_TEXT_IMMEDIATE_BLT +32h-3Fh Reserved +40h COLOR_BLT +41h-42h Reserved +43h SRC_COPY_BLT +44h-4Fh Reserved +50h XY_COLOR_BLT +51h XY_PAT_BLT +52h XY_MONO_PAT_BLT +53h XY_SRC_COPY_BLT +54h XY_MONO_SRC_COPY_BLT +55h XY_FULL_BLT +56h XY_FULL_MONO_SRC_BLT +57h XY_FULL_MONO_PATTERN_BLT +58h XY_FULL_MONO_PATTERN_MONO_SRC_BLT +59h XY_MONO_PAT_FIXED_BLT +5Ah-70h Reserved +71h XY_MONO_SRC_COPY_IMMEDIATE_BLT + + + + +Intel Confidential 6/21/2012 43 + Opcode (28:22) Command +72h XY_PAT_BLT_IMMEDIATE +73h XY_SRC_COPY_CHROMA_BLT +74h XY_FULL_IMMEDIATE_PATTERN_BLT +75h XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT +76h XY_PAT_CHROMA_BLT +77h XY_PAT_CHROMA_BLT_IMMEDIATE +78h-7Fh Reserved + + +5.2.3 3D/Media Command Map +For all commands listed in 6.2.3, 3D/Media Command Map, the Pipeline Type (bits 28:27) is 3h, +indicating the 3D Pipeline. + +3D/Media Command Map + Opcode Sub Opcode + Bits 26:24 Bits 23:16 Command Definition Chapter + 0h 03h Reserved + 0h 04h 3D Pipeline + 3DSTATE_CLEAR_PARAMS + + 0h 05h 3D Pipeline + 3DSTATE_DEPTH_BUFFER + 0h 06h 3D Pipeline + 3DSTATE_STENCIL_BUFFER + 0h 07h 3D Pipeline + 3DSTATE_HIER_DEPTH_BUFFER + 0h 08h 3DSTATE_VERTEX_BUFFERS Vertex Fetch + 0h 09h 3DSTATE_VERTEX_ELEMENTS Vertex Fetch + 0h 0Ah 3DSTATE_INDEX_BUFFER Vertex Fetch + 0h 0Bh 3DSTATE_VF_STATISTICS Vertex Fetch + 0h 0Ch Reserved + 0h 0Dh 3D Pipeline + 3DSTATE_VIEWPORT_STATE_POINTERS + + 0h 10h Vertex Shader + 3DSTATE_VS + 0h 11h Geometry Shader + 3DSTATE_GS + 0h 12h Clipper + 3DSTATE_CLIP + 0h 13h Strips & Fans + 3DSTATE_SF + + 0h 14h Windower + 3DSTATE_WM + 0h 15h Vertex Shader + 3DSTATE_CONSTANT_VS + 0h 16h Geometry Shader + 3DSTATE_CONSTANT_GS + 0h 17h Windower + 3DSTATE_CONSTANT_PS + + 0h 18h Windower + 3DSTATE_SAMPLE_MASK + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 44 + Opcode Sub Opcode +Bits 26:24 Bits 23:16 Command Definition Chapter + 0h 19h Hull Shader + 3DSTATE_CONSTANT_HS + + 0h 1Ah Domain Shader + 3DSTATE_CONSTANT_DS + 0h 1Bh Hull Shader + 3DSTATE_HS + 0h 1Ch Tesselator + 3DSTATE_TE + 0h 1Dh Domain Shader + 3DSTATE_DS + + 0h 1Eh HW Streamout + 3DSTATE_STREAMOUT + 0h 1Fh Setup + 3DSTATE_SBE + 0h 20h Pixel Shader + 3DSTATE_PS + 0h 21h Reserved + 0h 22h Strips & Fans + 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP + + 0h 23h Windower + 3DSTATE_VIEWPORT_STATE_POINTERS_CC + 0h 24h Pixel Shader + 3DSTATE_BLEND_STATE_POINTERS + 0h 25h Pixel Shader + 3DSTATE_DEPTH_STENCIL_STATE_POINTERS + 0h 26h Vertex Shader + 3DSTATE_BINDING_TABLE_POINTERS_VS + + 0h 27h Hull Shader + 3DSTATE_BINDING_TABLE_POINTERS_HS + 0h 28h Domain Shader + 3DSTATE_BINDING_TABLE_POINTERS_DS + 0h 29h Geometry Shader + 3DSTATE_BINDING_TABLE_POINTERS_GS + 0h 2Ah Pixel Shader + 3DSTATE_BINDING_TABLE_POINTERS_PS + + 0h 2Bh Vertex Shader + 3DSTATE_SAMPLER_STATE_POINTERS_VS + 0h 2Ch Hull Shader + 3DSTATE_SAMPLER_STATE_POINTERS_HS + 0h 2Dh Domain Shader + 3DSTATE_SAMPLER_STATE_POINTERS_DS + 0h 2Eh Geometry Shader + 3DSTATE_SAMPLER_STATE_POINTERS_GS + + 0h 2Fh Reserved + 0h 30h Vertex Shader + 3DSTATE_URB_VS + 0h 31h Hull Shader + 3DSTATE_URB_HS + 0h 32h Domain Shader + 3DSTATE_URB_DS + + + + +Intel Confidential 6/21/2012 45 + Opcode Sub Opcode + Bits 26:24 Bits 23:16 Command Definition Chapter + 0h 33h Geometry Shader + 3DSTATE_URB_GS + + 0h 48h-4Bh + Reserved + 0h 4Ch 3DSTATE_WM_CHROMA_KEY Windower + 0h 4Dh 3DSTATE_PS_BLEND Windower + 0h 4Eh 3DSTATE_WM_DEPTH_STENCIL Windower + 0h 4Fh 3DSTATE_PS_EXTRA Windower + 0h 50h 3DSTATE_RASTER Strips & Fans + 0h 51h 3DSTATE_SBE_SWIZ Strips & Fans + 0h 52h 3DSTATE_WM_HZ_OP Windower + 0h 53h 3DSTATE_INT (internally generated state) 3D Pipeline + 0h 54h Reserved + 0h 56h-FFh Reserved + 1h 00h 3DSTATE_DRAWING_RECTANGLE Strips & Fans + 1h 02h 3DSTATE_SAMPLER_PALETTE_LOAD0 Sampling Engine + 1h 03h Reserved + 1h 04h 3DSTATE_CHROMA_KEY Sampling Engine + 1h 05h + Reserved + 1h 06h 3DSTATE_POLY_STIPPLE_OFFSET Windower + 1h 07h 3DSTATE_POLY_STIPPLE_PATTERN Windower + 1h 08h 3DSTATE_LINE_STIPPLE Windower + 1h 0Ah Windower + 3DSTATE_AA_LINE_PARAMS + 1h 0Bh Geometry Shader + 3DSTATE_GS_SVB_INDEX + + 1h 0Ch Sampling Engine + 3DSTATE_SAMPLER_PALETTE_LOAD1 + 1h 0Dh Windower + 3DSTATE_MULTISAMPLE + 1h 0Eh Windower + 3DSTATE_STENCIL_BUFFER + 1h 0Fh Windower + 3DSTATE_HIER_DEPTH_BUFFER + + 1h 10h Windower + 3DSTATE_CLEAR_PARAMS + 1h 11h Sampling Engine + 3DSTATE_MONOFILTER_SIZE + 1h 12h Vertex Shader + 3DSTATE_PUSH_CONSTANT_ALLOC_VS + 1h 13h Hull Shader + 3DSTATE_PUSH_CONSTANT_ALLOC_HS + + 1h 14h Domain Shader + 3DSTATE_PUSH_CONSTANT_ALLOC_DS + 1h 15h Geometry Shader + 3DSTATE_PUSH_CONSTANT_ALLOC_GS + 1h 16h Pixel Shader + 3DSTATE_PUSH_CONSTANT_ALLOC_PS + 1h 17h 3DSTATE_SO_DECL_LIST HW Streamout + 1h 18h 3DSTATE_SO_BUFFER HW Streamout + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 46 + Opcode Sub Opcode + Bits 26:24 Bits 23:16 Command Definition Chapter + 1h 1Ch 3DSTATE_SAMPLE_PATTERN Windower + 1h 1Dh 3DSTATE_URB_CLEAR 3D Pipeline + 1h 1Eh-FFh Reserved + 2h 00h PIPE_CONTROL 3D Pipeline + 2h 01h-FFh Reserved + 3h 00h 3DPRIMITIVE Vertex Fetch + 3h 01h-FFh Reserved + 4h-7h 00h-FFh Reserved + + + Sub Definition + Pipeline Type (28:27) Opcode Opcode Command Chapter + Bits + Common (pipelined) 26:24 Bits 23:16 +0h 0h 03h STATE_PREFETCH Graphics + Processing + Engine +0h 0h 04h-FFh Reserved + Common (non- Bits + pipelined) 26:24 Bits 23:16 +0h 1h 00h Reserved n/a +0h 1h 01h STATE_BASE_ADDRESS Graphics + Processing + Engine +0h 1h 02h STATE_SIP Graphics + Processing + Engine +0h 1h 03h 3D Pipeline + SWTESS BASE ADDRESS + +0h 1h 04h GPGPU CSR BASE ADDRESS Graphics + Processing + Engine +0h 1h 04h–FFh Reserved n/a + Bits + Reserved 26:24 Bits 23:16 +0h 2h–7h XX Reserved n/a + + +5.2.4 Video Codec Command Map + +5.2.4.1 MFX Common Command Map +MFX state commands support direct state model and indirect state model. Recommended usage of +indirect state model is provided here (as a software usage guideline). + +Pipeline Type Opcode SubopA SubopB Command Chapter Recommended Interruptable +(28:27) (26:24) (23:21) (20:16) Indirect State ? + Pointer Map + +MFX Common +(State) + + + + +Intel Confidential 6/21/2012 47 + Pipeline Type Opcode SubopA SubopB Command Chapter Recommended Interruptable +(28:27) (26:24) (23:21) (20:16) Indirect State ? + Pointer Map + + 2h 0h 0h 0h MFX_PIPE_MODE_SELEC MFX IMAGE n/a + T + 2h 0h 0h 1h MFX_SURFACE_STATE MFX IMAGE n/a + 2h 0h 0h 2h MFX_PIPE_BUF_ADDR_S MFX IMAGE n/a + TATE + 2h 0h 0h 3h MFX_IND_OBJ_BASE_AD MFX IMAGE n/a + DR_STATE + 2h 0h 0h 4h MFX_BSP_BUF_BASE_AD MFX IMAGE n/a + DR_STATE + 2h 0h 0h 5h MFX IMAGE n/a + 2h 0h 0h 6h MFX_ STATE_POINTER MFX IMAGE n/a + 2h 0h 0h 7-8h Reserved n/a n/a n/a +MFX Common +(Object) + 2h 0h 1h 9h MFD_ IT_OBJECT MFX n/a Yes + 2h 0h 0h 4-1Fh Reserved n/a n/a n/a +AVC Common +(State) + + 2h 1h 0h 0h + MFX_AVC_IMG_STATE MFX IMAGE n/a + 2h 1h 0h 1h + MFX_AVC_QM_STATE MFX IMAGE n/a + 2h 1h 0h 2h + MFX_AVC_DIRECTMODE MFX SLICE n/a + _STATE + 2h 1h 0h 3h MFX_AVC_SLICE_STATE MFX SLICE n/a + 2h 1h 0h 4h MFX_AVC_REF_IDX_STA MFX SLICE n/a + TE + 2h 1h 0h 5h MFX_AVC_WEIGHTOFFS MFX SLICE n/a + ET_STATE + 2h 1h 0h 6-1Fh Reserved n/a n/a n/a +AVC Dec + 2h 1h 1h 0-7h Reserved n/a n/a n/a + 2h 1h 1h 8h MFD_AVC_BSD_OBJECT MFX n/a No + 2h 1h 1h 9-1Fh Reserved n/a n/a n/a +AVC Enc + 2h 1h 2h 0-1h Reserved n/a n/a n/a + 2h 1h 2h 2h MFC_AVC_FQM_STATE MFX IMAGE n/a + 2h 1h 2h 3-7h Reserved n/a n/a n/a + 2h 1h 2h 8h MFC_AVC_PAK_INSERT_ MFX n/a n/a + OBJECT + 2h 1h 2h 9h MFC_AVC_PAK_OBJECT MFX n/a Yes + 2h 1h 2h A-1Fh Reserved n/a n/a n/a + 2h 1h 2h 0-1Fh Reserved n/a n/a n/a +VC1 Common + 2h 2h 0h 0h MFX_VC1_PIC_STATE MFX IMAGE n/a + 2h 2h 0h 1h MFX_VC1_PRED_PIPE_S MFX IMAGE n/a + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 48 + Pipeline Type Opcode SubopA SubopB Command Chapter Recommended Interruptable +(28:27) (26:24) (23:21) (20:16) Indirect State ? + Pointer Map + + TATE + 2h 2h 0h 2h MFX_VC1_DIRECTMODE MFX SLICE n/a + _STATE + 2h 2h 0h 2-1Fh Reserved n/a n/a n/a +VC1 Dec + 2h 2h 1h 0-7h Reserved n/a n/a n/a + 2h 2h 1h 8h MFD_VC1_BSD_OBJECT MFX n/a Yes + 2h 2h 1h 9-1Fh Reserved n/a n/a n/a +VC1 Enc + 2h 2h 2h 0-1Fh Reserved n/a n/a n/a +MPEG2Comm +on + + 2h 3h 0h 0h MFX_MPEG2_PIC_STATE MFX IMAGE n/a + 2h 3h 0h 1h MFX_MPEG2_QM_STATE MFX IMAGE n/a + 2h 3h 0h 2-1Fh Reserved n/a n/a n/a +MPEG2 Dec + 2h 3h 1h 1-7h Reserved n/a n/a n/a + 2h 3h 1h 8h MFD_MPEG2_BSD_OBJE MFX n/a Yes + CT + 2h 3h 1h 9-1Fh Reserved n/a n/a n/a +MPEG2 Enc + 2h 3h 2h 0-1Fh Reserved n/a n/a n/a +The Rest + 2h 4-5h, 7h x x Reserved n/a n/a n/a + + + + +Intel Confidential 6/21/2012 49 + 6. Memory Data Formats +This chapter describes the attributes associated with the memory-resident data objects operated on by +the graphics pipeline. This includes object types, pixel formats, memory layouts, and rules/restrictions +placed on the dimensions, physical memory location, pitch, alignment, etc. with respect to the specific +operations performed on the objects. + + +6.1 Memory Object Overview +Any memory data accessed by the device is considered part of a memory object of some memory object +type. + + +6.1.1 Memory Object Types +The following table lists the various memory objects types and an indication of their role in the system. + Memory Object + Type Role +Graphics Translation Contains PTEs used to translate “graphics addresses” into physical memory addresses. +Table (GTT) +Hardware Status Cached page of sysmem used to provide fast driver synchronization. +Page +Logical Context Memory areas used to store (save/restore) images of hardware rendering contexts. Logical +Buffer contexts are referenced via a pointer to the corresponding Logical Context Buffer. +Ring Buffers Buffers used to transfer (DMA) instruction data to the device. Primary means of controlling + rendering operations. +Batch Buffers Buffers of instructions invoked indirectly from Ring Buffers. +State Descriptors Contains state information in a prescribed layout format to be read by hardware. Many different + state descriptor formats are supported. +Vertex Buffers Buffers of 3D vertex data indirectly referenced through “indexed” 3D primitive instructions. + Graphics memory buffer used to drive the display output while in legacy VGA mode. + VGA Buffer +(Must be mapped +UC on PCI) +Display Surface Memory buffer used to display images on display devices. +Overlay Surface Memory buffer used to display overlaid images on display devices. + Memory area used to provide double-buffer for Overlay register and filter coefficient loading. +Overlay Register, +Filter Coefficients +Buffer + +Cursor Surface Hardware cursor pattern in memory. +2D Render Source Surface used as primary input to 2D rendering operations. +2D Render R-M-W 2D rendering output surface that is read in order to be combined in the rendering function. +Destination Destination surfaces that accessed via this Read-Modify-Write mode have somewhat different + restrictions than Write-Only Destination surfaces. +2D Render Write- 2D rendering output surface that is written but not read by the 2D rendering function. +Only Destination Destination surfaces that accessed via a Write-Only mode have somewhat different restrictions + than Read-Modify-Write Destination surfaces. +2D Monochrome 1 bpp surfaces used as inputs to 2D rendering after being converted to foreground/background + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 50 + Memory Object + Type Role +Source colors. +2D Color Pattern 8x8 pixel array used to supply the “pattern” input to 2D rendering functions. +DIB “Device Independent Bitmap” surface containing “logical” pixel values that are converted (via + LUTs) to physical colors. +3D Color Buffer Surface receiving color output of 3D rendering operations. May also be accessed via R-M-W + (aka blending). Also referred to as a Render Target. +3D Depth Buffer Surface used to hold per-pixel depth and stencil values used in 3D rendering operations. + Accessed via RMW. +3D Texture Map Color surface (or collection of surfaces) which provide texture data in 3D rendering operations. + Surface read by Texture Samplers, though not in normal 3D rendering operations (e.g., in video +“Non-3D” Texture + color conversion functions). +Motion Comp These are the Motion Comp reference pictures. +Surfaces +Motion Comp This is Motion Comp intra-coded or inter-coded correction data. +Correction Data +Buffer + + + +6.2 Channel Formats + +6.2.1 Unsigned Normalized (UNORM) +An unsigned normalized value with n bits is interpreted as a value between 0.0 and 1.0. The minimum +value (all 0’s) is interpreted as 0.0, the maximum value (all 1’s) is interpreted as 1.0. Values in between +are equally spaced. For example, a 2-bit UNORM value would have the four values 0, 1/3, 2/3, and 1. +If the incoming value is interpreted as an n-bit integer, the interpreted value can be calculated by dividing +the integer by 2n-1. + + +6.2.2 Gamma Conversion (SRGB) +Gamma conversion is only supported on UNORM formats. If this flag is included in the surface format +name, it indicates that a reverse gamma conversion is to be done after the source surface is read, and a +forward gamma conversion is to be done before the destination surface is written. + + +6.2.3 Signed Normalized (SNORM) +A signed normalized value with n bits is interpreted as a value between -1.0 and +1.0. If the incoming +value is interpreted as a 2’s-complement n-bit signed integer, the interpreted value can be calculated by +dividing the integer by 2n-1-1. Note that the most negative value of -2n-1 will result in a value slightly smaller +than -1.0. This value is clamped to -1.0, thus there are two representations of -1.0 in SNORM format. + + +6.2.4 Unsigned Integer (UINT/USCALED) +The UINT and USCALED formats interpret the source as an unsigned integer value with n bits with a +range of 0 to 2n-1. +The UINT formats copy the source value to the destination (zero-extending if required), keeping the value +as an integer. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 51 + The USCALED formats convert the integer into the corresponding floating point value (e.g., 0x03 --> 3.0f). +For 32-bit sources, the value is rounded to nearest even. + + +6.2.5 Signed Integer (SINT/SSCALED) +A signed integer value with n bits is interpreted as a 2’s complement integer with a range of -2n-1 to +2n-1-1. +The SINT formats copy the source value to the destination (sign-extending if required), keeping the value +as an integer. +The SSCALED formats convert the integer into the corresponding floating point value (e.g., 0xFFFD --> - +3.0f). For 32-bit sources, the value is rounded to nearest even. + + +6.2.6 Floating Point (FLOAT) +Refer to IEEE Standard 754 for Binary Floating-Point Arithmetic. The IA-32 Intel (R) Architecture Software +Developer’s Manual also describes floating point data types. + +6.2.6.1 32-bit Floating Point + Bit Description + 31 + Sign (s) + + 30:23 + Exponent (e) Biased + Exponent + 22:0 + Fraction (f) Does not include + “hidden one” + +The value of this data type is derived as: + +  if e == 255 and f != 0, then v is NaN regardless of s +  if e == 255 and f == 0, then v = (-1)s*infinity (signed infinity) +  if 0 < e < 255, then v = (-1)s*2(e-127)*(1.f) +  if e == 0 and f != 0, then v = (-1)s*2(e-126)*(0.f) (denormalized numbers) +  if e == 0 and f == 0, then v = (-1)s*0 (signed zero) + +6.2.6.2 64-bit Floating Point + Bit Description + 63 + Sign (s) + +62:52 + Exponent (e) Biased Exponent + +51:0 + Fraction (f) Does not include “hidden one” + +The value of this data type is derived as: + +  if e == b’11..11’ and f != 0, then v is NaN regardless of s +  if e == b’11..11’ and f == 0, then v = (-1)s*infinity (signed infinity) + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 52 +  if 0 < e < b’11..11’, then v = (-1)s*2(e-1023)*(1.f) +  if e == 0 and f != 0, then v = (-1)s*2(e-1022)*(0.f) (denormalized numbers) +  if e == 0 and f == 0, then v = (-1)s*0 (signed zero) + +6.2.6.3 16-bit Floating Point + Bit Description + 15 + Sign (s) + + 14:10 + Exponent (e) Biased Exponent + + 9:0 + Fraction (f) Does not include + “hidden one” + +The value of this data type is derived as: + +  if e == 31 and f != 0, then v is NaN regardless of s +  if e == 31 and f == 0, then v = (-1)s*infinity (signed infinity) +  if 0 < e < 31, then v = (-1)s*2(e-15)*(1.f) +  if e == 0 and f != 0, then v = (-1)s*2(e-14)*(0.f) (denormalized numbers) +  if e == 0 and f == 0, then v = (-1)s*0 (signed zero) + +The following table represents relationship between 32 bit and 16 bit floating point ranges: + Unbiased + flt32 exponent exponent flt16 exponent flt16 fraction + 255 + 254 127 + ... + 127+16 16 Infinity 31 1.1111111111 + 127+15 15 Max exponent 30 1.xxxxxxxxxx + 127 0 15 1.xxxxxxxxxx + 113 -14 Min exponent 1 1.xxxxxxxxxx + 112 Denormalized 0 0.1xxxxxxxxx + 111 Denormalized 0 0.01xxxxxxxx + 110 Denormalized 0 0.001xxxxxxx + 109 Denormalized 0 0.0001xxxxxx + 108 Denormalized 0 0.00001xxxxx + 107 Denormalized 0 0.000001xxxx + 106 Denormalized 0 0.0000001xxx + 115 Denormalized 0 0.00000001xx + 114 Denormalized 0 0.000000001x + 113 Denormalized 0 0.0000000001 + 112 Denormalized 0 0.0 + ... + 0 0 0.0 + +Conversion from the 32-bit floating point format to the 16-bit format should be done with round to nearest +even. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 53 + 6.2.6.4 11-bit Floating Point + Bits Description + 10:6 Exponent (e): Biased exponent (the bias depends on e) + 5:0 Fraction (f): Fraction bits to the right of the binary point + +The value v of an 11-bit floating-point number is calculated from e and f as: + +  if e == 31 and f != 0 then v = NaN +  if e == 31 and f == 0 then v = +infinity +  if 0 < e < 31, then v = 2(e-15)*(1.f) +  if e == 0 and f != 0, then v = 2(e-14)*(0.f) (denormalized numbers) +  if e == 0 and f == 0, then v = 0 (zero) + +There is no sign bit and negative values are not represented. +The 11-bit floating-point format has one more bit of fractional precision than the 10-bit floating-point +format. +The maximum representable finite value is 1.111111b * 215 = FE00h = 65024. + +6.2.6.5 10-bit Floating Point + Bits Description + 9:5 Exponent (e): Biased exponent (the bias depends on e) + 4:0 Fraction (f): Fraction bits to the right of the binary point + +The value v of a 10-bit floating-point number is calculated from e and f as: + +  if e == 31 and f != 0 then v = NaN +  if e == 31 and f == 0 then v = +infinity +  if 0 < e < 31, then v = 2(e-15)*(1.f) +  if e == 0 and f != 0, then v = 2(e-14)*(0.f) (denormalized numbers) +  if e == 0 and f == 0, then v = 0 (zero) + +There is no sign bit and negative values are not represented. +The maximum representable finite value is 1.11111b * 215 = FC00h = 64512. + +6.2.6.6 Shared Exponent +The R9G9B9E5_SHAREDEXP format contains three channels that share an exponent. The three +fractions assume an impled “0” rather than an implied “1” as in the other floating point formats. This +format does not support infinity and NaN values. There are no sign bits, only positive numbers and zero +can be represented. The value of each channel is determined as follows, where “f” is the fraction of the +corresponding channel, and “e” is the shared exponent. +v = (0.f)*2(e-15) + Bit Description + 31:27 + Exponent (e) Biased + Exponent + 26:18 + Blue Fraction + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 54 + Bit Description + 17:9 + Green Fraction + + 8:0 + Red Fraction + + + +6.2.7 Non-Video Surface Formats +This section describes the lowest-level organization of a surfaces containing discrete “pixel” oriented data +(e.g., discrete pixel (RGB,YUV) colors, subsampled video data, 3D depth/stencil buffer pixel formats, +bump map values etc. Many of these pixel formats are common to the various pixel-oriented memory +object types. + + +6.2.8 Surface Format Naming +Unless indicated otherwise, all pixels are stored in “little endian” byte order. i.e., pixel bits 7:0 are stored +in byte n, pixel bits 15:8 are stored in byte n+1, and so on. The format labels include color components in +little endian order (e.g., R8G8B8A8 format is physically stored as R, G, B, A). +The name of most of the surface formats specifies its format. Channels are listed in little endian order +(LSB channel on the left, MSB channel on the right), with the channel format specified following the +channels with that format. For example, R5G5_SNORM_B6_UNORM contains, from LSB to MSB, 5 bits +of red in SNORM format, 5 bits of green in SNORM format, and 6 bits of blue in UNORM format. + + +6.2.9 Intensity Formats +All surface formats containing “I” include an intensity value. When used as a source surface for the +sampling engine, the intensity value is replicated to all four channels (R,G,B,A) before being filtered. +Intensity surfaces are not supported as destinations. + + +6.2.10 Luminance Formats +All surface formats contaning “L” include a luminance value. When used as a source surface for the +sampling engine, the luminance value is replicated to the three color channels (R,G,B) before being +filtered. The alpha channel is provided either from another field or receives a default value. Luminance +surfaces are not supported as destinations. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 55 + 6.2.11 R1_UNORM (same as R1_UINT) and MONO8 +When used as a texel format, the R1_UNORM format contains 8 1-bit Intensity (I) values that are +replicated to all color channels. Note that T0 of byte 0 of a R1_UNORM-formatted texture corresponds to +Texel[0,0]. This is different from the format used for monochrome sources in the BLT engine. + 7 6 5 4 3 2 1 0 + T7 T6 T5 T4 T3 T2 T1 T0 + + + Bit Description + T0 + Texel 0 + On texture reads, this (unsigned) 1-bit value is replicated to all + color channels. + Format: U1 + ... + ... + + T7 + Texel 7 + On texture reads, this (unsigned) 1-bit value is replicated to all + color channels. + Format: U1 + +MONO8 format is identical to R1_UNORM but has different semantics for filtering. MONO8 is the only +supported format for the MAPFILTER_MONO filter. See the Sampling Engine chapter. + + +6.2.12 Palette Formats + +6.2.12.1 P4A4_UNORM +This surface format contains a 4-bit Alpha value (in the high nibble) and a 4-bit Palette Index value (in the +low nibble). +7 4 3 0 +Alpha Palette Index + + + Bit Description + 7:4 + Alpha + Alpha value which will be replicated to both the high and low nibble of an 8-bit value, and then divided + by 255 to yield a [0.0,1.0] Alpha value. + Format: U4 + 3:0 + Palette Index + A 4-bit index which is used to lookup a 24-bit (RGB) value in the texture palette (loaded via + 3DSTATE_SAMPLER_PALETTE_LOADx) + Format: U4 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 56 + 6.2.12.2 A4P4_UNORM +This surface format contains a 4-bit Alpha value (in the low nibble) and a 4-bit Color Index value (in the +high nibble). +7 4 3 0 +Palette Index Alpha + + + Bit Description + 7:4 + Palette Index + A 4-bit color index which is used to lookup a 24-bit RGB value in the + texture palette. + Format: U4 + 3:0 + Alpha + Alpha value which will be replicated to both the high and low nibble of + an 8-bit value, and then divided by 255 to yield a [0.0,1.0] alpha value. + Format: U4 + + +6.2.12.3 P8A8_UNORM +This surface format contains an 8-bit Alpha value (in the high byte) and an 8-bit Palette Index value (in +the low byte). +15 8 7 0 +Alpha Palette Index + + +Bit Description +7:4 + Alpha + Alpha value which will be divided by 255 to yield a [0.0,1.0] Alpha value. + Format: U8 +3:0 + Palette Index + An 8-bit index which is used to lookup a 24-bit (RGB) value in the texture palette (loaded via + 3DSTATE_SAMPLER_PALETTE_LOADx) + Format: U8 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 57 + 6.2.12.4 A8P8_UNORM +This surface format contains an 8-bit Alpha value (in the low byte) and an 8-bit Color Index value (in the +high byte). +15 8 7 0 +Palette Index Alpha + + + Bit Description +15:8 + Palette Index + An 8-bit color index which is used to lookup a 24-bit RGB value in the texture palette. + Format: U8 +7:0 + Alpha + Alpha value which will be divided by 255 to yield a [0.0,1.0] alpha value. + Format: U8 + + +6.2.12.5 P8_UNORM +This surface format contains only an 8-bit Color Index value. + Bit Description + 7:0 + Palette Index + An 8-bit color index which is used to lookup a 32-bit ARGB value in the texture palette. + Format: U8 + + +6.2.12.6 P2_UNORM +This surface format contains only a 2-bit Color Index value. +Bit Description +1:0 + Palette Index + A 2-bit color index which is used to lookup a 32-bit ARGB value in the texture palette. + Format: U2 + + + +6.3 Compressed Surface Formats +This section contains information on the internal organization of compressed surface formats. + + +6.3.1 FXT Texture Formats +There are four different FXT1 compressed texture formats. Each of the formats compress two 4x4 texel +blocks into 128 bits. In each compression format, the 32 texels in the two 4x4 blocks are arranged +according to the following diagram: + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 58 + FXT1 Encoded Blocks + + + + +6.3.1.1 Overview of FXT1 Formats +During the compression phase, the encoder selects one of the four formats for each block based on +which encoding scheme results in best overall visual quality. The following table lists the four different +modes and their encodings: + +FXT1 Format Summary + Block + Compression +Bit 127 Bit 126 Bit 125 Mode Summary Description + 0 0 X 2 R5G5B5 colors supplied. Single LUT with 7 interpolated color values and transparent + CC_HI + black + 0 1 0 4 R5G5B5 colors used directly as 4-entry LUT. + CC_CHROMA + + 0 1 1 3 A5R5G5B5 colors supplied. LERP bit selects between 1 LUT with 3 discrete colors + + CC_ALPHA + transparent black and 2 LUTs using interpolated values of Color 0,1 (t0-15) and Color 1,2 + (t16-31). + 1 x x 4 R5G5B5 colors supplied, where Color0,1 LUT is used for t0-t15, and Color2,3 LUT used + CC_MIXED + for t16-31. Alpha bit selects between LUTs with 4 interpolated colors or 3 interpolated + colors + transparent black. + + +6.3.1.2 FXT1 CC_HI Format +In the CC_HI encoding format, two base 15-bit R5G5B5 colors (Color 0, Color 1) are included in the +encoded block. These base colors are then expanded (using high-order bit replication) to 24-bit RGB +colors, and used to define an 8-entry lookup table of interpolated color values (the 8th entry is transparent +black). The encoded block contains a 3-bit index value per texel that is used to lookup a color from the +table. + +6.3.1.2.1 CC_HI Block Encoding +The following table describes the encoding of the 128-bit (DQWord) CC_HI block format: + +FXT CC_HI Block Encoding + Bit Description + 127:126 Mode = ‘00’b (CC_HI) + 125:121 Color 1 Red + 120:116 Color 1 Green + 115:111 Color 1 Blue + 110:106 Color 0 Red + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 59 + Bit Description + 105:101 Color 0 Green + 100:96 Color 0 Blue + 95:93 Texel 31 Select + ... ... + 50:48 Texel 16 Select + 47:45 Texel 15 Select + ... ... + 2:0 Texel 0 Select + + +6.3.1.2.2 CC_HI Block Decoding +The two base colors, Color 0 and Color 1 are converted from R5G5B5 to R8G8B8 by replicating the 3 +MSBs into the 3 LSBs, as shown in the following table: + +FXT CC_HI Decoded Colors +Expanded Color Bit Expanded Channel Bit Encoded Block Source Bit +Color 1 [23:19] Color 1 Red [7:3] [125:121] +Color 1 [18:16] Color 1 Red [2:0] [125:123] +Color 1 [15:11] Color 1 Green [7:3] [120:116] +Color 1 [10:08] Color 1 Green [2:0] [120:118] +Color 1 [07:03] Color 1 Blue [7:3] [115:111] +Color 1 [02:00] Color 1 Blue [2:0] [115:113] +Color 0 [23:19] Color 0 Red [7:3] [110:106] +Color 0 [18:16] Color 0 Red [2:0] [110:108] +Color 0 [15:11] Color 0 Green [7:3] [105:101] +Color 0 [10:08] Color 0 Green [2:0] [105:103] +Color 0 [07:03] Color 0 Blue [7:3] [100:96] +Color 0 [02:00] Color 0 Blue [2:0] [100:98] + +These two 24-bit colors (Color 0, Color 1) are then used to create a table of seven interpolated colors +(with Alpha = 0FFh), along with an eight entry equal to RGBA = 0,0,0,0, as shown in the following table: + +FXT CC_HI Interpolated Color Table + Interpolated + Color Color RGB Alpha + 0 Color0.RGB 0FFh + 1 (5 * Color0.RGB + 1 * Color1.RGB + 3) / 6 0FFh + 2 (4 * Color0.RGB + 2 * Color1.RGB + 3) / 6 0FFh + 3 (3 * Color0.RGB + 3 * Color1.RGB + 3) / 6 0FFh + 4 (2 * Color0.RGB + 4 * Color1.RGB + 3) / 6 0FFh + 5 (1 * Color0.RGB + 5 * Color1.RGB + 3) / 6 0FFh + 6 Color1.RGB 0FFh + 7 RGB = 0,0,0 0 + +This table is then used as an 8-entry Lookup Table, where each 3-bit Texel n Select field of the encoded +CC_HI block is used to index into a 32-bit A8R8G8B8 color from the table completing the decode of the +CC_HI block. + +6.3.1.3 FXT1 CC_CHROMA Format +In the CC_CHROMA encoding format, four 15-bit R5B5G5 colors are included in the encoded block. +These colors are then expanded (using high-order bit replication) to form a 4-entry table of 24-bit RGB + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 60 + colors. The encoded block contains a 2-bit index value per texel that is used to lookup a 24-bit RGB color +from the table. The Alpha component defaults to fully opaque (0FFh). + +6.3.1.3.1 CC_CHROMA Block Encoding +The following table describes the encoding of the 128-bit (DQWord) CC_CHROMA block format: + +FXT CC_CHROMA Block Encoding + Bit Description +127:125 Mode = ‘010’b (CC_CHROMA) +124 Unused +123:119 Color 3 Red +118:114 Color 3 Green +113:109 Color 3 Blue +108:104 Color 2 Red +103:99 Color 2 Green +98:94 Color 2 Blue +93:89 Color 1 Red +88:84 Color 1 Green +83:79 Color 1 Blue +78:74 Color 0 Red +73:69 Color 0 Green +68:64 Color 0 Blue +63:62 Texel 31 Select +... +33:32 Texel 16 Select +31:30 Texel 15 Select +... +1:0 Texel 0 Select + + +6.3.1.3.2 CC_CHROMA Block Decoding +The four colors (Color 0-3) are converted from R5G5B5 to R8G8B8 by replicating the 3 MSBs into the 3 +LSBs, as shown in the following tables: + +FXT CC_CHROMA Decoded Colors +Expanded Color Bit Expanded Channel Bit Encoded Block Source Bit +Color 3 [23:17] Color 3 Red [7:3] [123:119] +Color 3 [18:16] Color 3 Red [2:0] [123:121] +Color 3 [15:11] Color 3 Green [7:3] [118:114] +Color 3 [10:08] Color 3 Green [2:0] [118:116] +Color 3 [07:03] Color 3 Blue [7:3] [113:109] +Color 3 [02:00] Color 3 Blue [2:0] [113:111] +Color 2 [23:17] Color 2 Red [7:3] [108:104] +Color 2 [18:16] Color 2 Red [2:0] [108:106] +Color 2 [15:11] Color 2 Green [7:3] [103:99] +Color 2 [10:08] Color 2 Green [2:0] [103:101] +Color 2 [07:03] Color 2 Blue [7:3] [98:94] +Color 2 [02:00] Color 2 Blue [2:0] [98:96] +Color 1 [23:17] Color 1 Red [7:3] [93:89] +Color 1 [18:16] Color 1 Red [2:0] [93:91] +Color 1 [15:11] Color 1 Green [7:3] [88:84] + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 61 + Expanded Color Bit Expanded Channel Bit Encoded Block Source Bit +Color 1 [10:08] Color 1 Green [2:0] [88:86] +Color 1 [07:03] Color 1 Blue [7:3] [83:79] +Color 1 [02:00] Color 1 Blue [2:0] [83:81] +Color 0 [23:17] Color 0 Red [7:3] [78:74] +Color 0 [18:16] Color 0 Red [2:0] [78:76] +Color 0 [15:11] Color 0 Green [7:3] [73:69] +Color 0 [10:08] Color 0 Green [2:0] [73:71] +Color 0 [07:03] Color 0 Blue [7:3] [68:64] +Color 0 [02:00] Color 0 Blue [2:0] [68:66] + +This table is then used as a 4-entry Lookup Table, where each 2-bit Texel n Select field of the encoded +CC_CHROMA block is used to index into a 32-bit A8R8G8B8 color from the table (Alpha defaults to +0FFh) completing the decode of the CC_CHROMA block. + +FXT CC_CHROMA Interpolated Color Table + Texel Select Color ARGB + 0 Color0.ARGB + 1 Color1.ARGB + 2 Color2.ARGB + 3 Color3.ARGB + + +6.3.1.4 FXT1 CC_MIXED Format +In the CC_MIXED encoding format, four 15-bit R5G5B5 colors are included in the encoded block: Color 0 +and Color 1 are used for Texels 0-15, and Color 2 and Color 3 are used for Texels 16-31. +Each pair of colors are then expanded (using high-order bit replication) to form 4-entry tables of 24-bit +RGB colors. The encoded block contains a 2-bit index value per texel that is used to lookup a 24-bit RGB +color from the table. The Alpha component defaults to fully opaque (0FFh). + +6.3.1.4.1 CC_MIXED Block Encoding +The following table describes the encoding of the 128-bit (DQWord) CC_MIXED block format: + +FXT CC_MIXED Block Encoding + Bit Description +127 Mode = ‘1’b (CC_MIXED) +126 Color 3 Green [0] +125 Color 1 Green [0] +124 Alpha [0] +123:119 Color 3 Red +118:114 Color 3 Green +113:109 Color 3 Blue +108:104 Color 2 Red +103:99 Color 2 Green +98:94 Color 2 Blue +93:89 Color 1 Red +88:84 Color 1 Green +83:79 Color 1 Blue +78:74 Color 0 Red +73:69 Color 0 Green +68:64 Color 0 Blue + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 62 + Bit Description +63:62 Texel 31 Select +... ... +33:32 Texel 16 Select +31:30 Texel 15 Select +... ... +1:0 Texel 0 Select + + +6.3.1.4.2 CC_MIXED Block Decoding +The decode of the CC_MIXED block is modified by Bit 124 (Alpha [0]) of the encoded block. +Alpha[0] = 0 Decoding +When Alpha[0] = 0 the four colors are encoded as 16-bit R5G6B5 values, with the Green LSB defined as +per the following table: + +FXT CC_MIXED (Alpha[0]=0) Decoded Colors +Encoded Color Bit Definition +Color 3 Green [0] Encoded Bit [126] +Color 2 Green [0] Encoded Bit [33] XOR Encoded Bit [126] +Color 1 Green [0] Encoded Bit [125] +Color 0 Green [0] Encoded Bit [1] XOR Encoded Bit [125] + +The four colors (Color 0-3) are then converted from R5G5B6 to R8G8B8 by replicating the 3 MSBs into +the 3 LSBs, as shown in the following table: + +FXT CC_MIXED Decoded Colors (Alpha[0] = 0) +Expanded Color Bit Expanded Channel Bit Encoded Block Source Bit +Color 3 [23:17] Color 3 Red [7:3] [123:119] +Color 3 [18:16] Color 3 Red [2:0] [123:121] +Color 3 [15:11] Color 3 Green [7:3] [118:114] +Color 3 [10] Color 3 Green [2] [126] +Color 3 [09:08] Color 3 Green [1:0] [118:117] +Color 3 [07:03] Color 3 Blue [7:3] [113:109] +Color 3 [02:00] Color 3 Blue [2:0] [113:111] +Color 2 [23:17] Color 2 Red [7:3] [108:104] +Color 2 [18:16] Color 2 Red [2:0] [108:106] +Color 2 [15:11] Color 2 Green [7:3] [103:99] +Color 2 [10] Color 2 Green [2] [33] XOR [126]] +Color 2 [09:08] Color 2 Green [1:0] [103:100] +Color 2 [07:03] Color 2 Blue [7:3] [98:94] +Color 2 [02:00] Color 2 Blue [2:0] [98:96] +Color 1 [23:17] Color 1 Red [7:3] [93:89] +Color 1 [18:16] Color 1 Red [2:0] [93:91] +Color 1 [15:11] Color 1 Green [7:3] [88:84] +Color 1 [10] Color 1 Green [2] [125] +Color 1 [09:08] Color 1 Green [1:0] [88:86] +Color 1 [07:03] Color 1 Blue [7:3] [83:79] +Color 1 [02:00] Color 1 Blue [2:0] [83:81] +Color 0 [23:17] Color 0 Red [7:3] [78:74] +Color 0 [18:16] Color 0 Red [2:0] [78:76] +Color 0 [15:11] Color 0 Green [7:3] [73:69] + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 63 + Expanded Color Bit Expanded Channel Bit Encoded Block Source Bit +Color 0 [10] Color 0 Green [2] [1] XOR [125] +Color 0 [09:08] Color 0 Green [1:0] [73:71] +Color 0 [07:03] Color 0 Blue [7:3] [68:64] +Color 0 [02:00] Color 0 Blue [2:0] [68:66] + +The two sets of 24-bit colors (Color 0,1 and Color 2,3) are then used to create two tables of four +interpolated colors (with Alpha = 0FFh). The Color0,1 table is used as a lookup table for texel 0-15 +indices, and the Color2,3 table used for texels 16-31 indices, as shown in the following figures: + +FXT CC_MIXED Interpolated Color Table (Alpha[0]=0, Texels 0-15) +Texel 0-15 Select Color RGB Alpha + 0 Color0.RGB 0FFh + 1 (2*Color0.RGB + Color1.RGB + 1) /3 0FFh + 2 (Color0.RGB + 2*Color1.RGB + 1) /3 0FFh + 3 Color1.RGB 0FFh + +FXT CC_MIXED Interpolated Color Table (Alpha[0]=0, Texels 16-31) +Texel 16-31 Select Color RGB Alpha + 0 Color2.RGB 0FFh + 1 (2/3) * Color2.RGB + (1/3) * Color3.RGB 0FFh + 2 (1/3) * Color2.RGB + (2/3) * Color3.RGB 0FFh + 3 Color3.RGB 0FFh + +Alpha[0] = 1 Decoding +When Alpha[0] = 1, Color0 and Color2 are encoded as 15-bit R5G5B5 values. Color1 and Color3 are +encoded as RGB565 colors, with the Green LSB obtained as shown in the following table: + +FXT CC_MIXED (Alpha[0]=0) Decoded Colors + Encoded Color Bit Definition +Color 3 Green [0] Encoded Bit [126] +Color 1 Green [0] Encoded Bit [125] + +All four colors are then expanded to 24-bit R8G8B8 colors by bit replication, as show in the following +diagram. + +FXT CC_MIXED Decoded Colors (Alpha[0] = 1) +Expanded Color Bit Expanded Channel Bit Encoded Block Source Bit +Color 3 [23:17] Color 3 Red [7:3] [123:119] +Color 3 [18:16] Color 3 Red [2:0] [123:121] +Color 3 [15:11] Color 3 Green [7:3] [118:114] +Color 3 [10] Color 3 Green [2] [126] +Color 3 [09:08] Color 3 Green [1:0] [118:117] +Color 3 [07:03] Color 3 Blue [7:3] [113:109] +Color 3 [02:00] Color 3 Blue [2:0] [113:111] +Color 2 [23:19] Color 2 Red [7:3] [108:104] +Color 2 [18:16] Color 2 Red [2:0] [108:106] +Color 2 [15:11] Color 2 Green [7:3] [103:99] +Color 2 [10:08] Color 2 Green [2:0] [103:101] +Color 2 [07:03] Color 2 Blue [7:3] [98:94] +Color 2 [02:00] Color 2 Blue [2:0] [98:96] +Color 1 [23:17] Color 1 Red [7:3] [93:89] + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 64 + Expanded Color Bit Expanded Channel Bit Encoded Block Source Bit +Color 1 [18:16] Color 1 Red [2:0] [93:91] +Color 1 [15:11] Color 1 Green [7:3] [88:84] +Color 1 [10] Color 1 Green [2] [125] +Color 1 [09:08] Color 1 Green [1:0] [88:87] +Color 1 [07:03] Color 1 Blue [7:3] [83:79] +Color 1 [02:00] Color 1 Blue [2:0] [83:81] +Color 0 [23:19] Color 0 Red [7:3] [78:74] +Color 0 [18:16] Color 0 Red [2:0] [78:76] +Color 0 [15:11] Color 0 Green [7:3] [73:69] +Color 0 [10:08] Color 0 Green [2:0] [73:71] +Color 0 [07:03] Color 0 Blue [7:3] [68:64] +Color 0 [02:00] Color 0 Blue [2:0] [68:66] + +The two sets of 24-bit colors (Color 0,1 and Color 2,3) are then used to create two tables of four colors. +The Color0,1 table is used as a lookup table for texel 0-15 indices, and the Color2,3 table used for texels +16-31 indices. The color at index 1 is the linear interpolation of the base colors, while the color at index 3 +is defined as Black (0,0,0) with Alpha = 0, as shown in the following figures: + +FXT CC_MIXED Interpolated Color Table (Alpha[0]=1, Texels 0-15) + Texel 0-15 Select Color RGB Alpha + 0 Color0.RGB 0FFh + 1 (Color0.RGB + Color1.RGB) /2 0FFh + 2 Color1.RGB 0FFh + 3 Black (0,0,0) 0 + +FXT CC_MIXED Interpolated Color Table (Alpha[0]=1, Texels 16-31) + Texel 16-31 Select Color RGB Alpha + 0 Color2.RGB 0FFh + 1 (Color2.RGB + Color3.RGB) /2 0FFh + 2 Color3.RGB 0FFh + 3 Black (0,0,0) 0 + +These tables are then used as a 4-entry Lookup Table, where each 2-bit Texel n Select field of the +encoded CC_MIXED block is used to index into the appropriate 32-bit A8R8G8B8 color from the table, +completing the decode of the CC_CMIXED block. + +6.3.1.5 FXT1 CC_ALPHA Format +In the CC_ALPHA encoding format, three A5R5G5B5 colors are provided in the encoded block. A control +bit (LERP) is used to define the lookup table (or tables) used to dereference the 2-bit Texel Selects. + +6.3.1.5.1 CC_ALPHA Block Encoding +The following table describes the encoding of the 128-bit (DQWord) CC_ALPHA block format: + +FXT CC_ALPHA Block Encoding + Bit Description + 127:125 Mode = ‘011’b (CC_ALPHA) + 124 LERP + 123:119 Color 2 Alpha + 118:114 Color 1 Alpha + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 65 + Bit Description + 113:109 Color 0 Alpha + 108:104 Color 2 Red + 103:99 Color 2 Green + 98:94 Color 2 Blue + 93:89 Color 1 Red + 88:84 Color 1 Green + 83:79 Color 1 Blue + 78:74 Color 0 Red + 73:69 Color 0 Green + 68:64 Color 0 Blue + 63:62 Texel 31 Select + ... ... + 33:32 Texel 16 Select + 31:30 Texel 15 Select + ... ... + 1:0 Texel 0 Select + + +6.3.1.5.2 CC_ALPHA Block Decoding +Each of the three colors (Color 0-2) are converted from A5R5G5B5 to A8R8G8B8 by replicating the 3 +MSBs into the 3 LSBs, as shown in the following tables: + +FXT CC_ALPHA Decoded Colors +Expanded Color Bit Expanded Channel Bit Encoded Block Source Bit +Color 2 [31:27] Color 2 Alpha [7:3] [123:119] +Color 2 [26:24] Color 2 Alpha [2:0] [123:121] +Color 2 [23:17] Color 2 Red [7:3] [108:104] +Color 2 [18:16] Color 2 Red [2:0] [108:106] +Color 2 [15:11] Color 2 Green [7:3] [103:99] +Color 2 [10:08] Color 2 Green [2:0] [103:101] +Color 2 [07:03] Color 2 Blue [7:3] [98:94] +Color 2 [02:00] Color 2 Blue [2:0] [98:96] +Color 1 [31:27] Color 1 Alpha [7:3] [118:114] +Color 1 [26:24] Color 1 Alpha [2:0] [118:116] +Color 1 [23:17] Color 1 Red [7:3] [93:89] +Color 1 [18:16] Color 1 Red [2:0] [93:91] +Color 1 [15:11] Color 1 Green [7:3] [88:84] +Color 1 [10:08] Color 1 Green [2:0] [88:86] +Color 1 [07:03] Color 1 Blue [7:3] [83:79] +Color 1 [02:00] Color 1 Blue [2:0] [83:81] +Color 0 [31:27] Color 0 Alpha [7:3] [113:109] +Color 0 [26:24] Color 0 Alpha [2:0] [113:111] +Color 0 [23:17] Color 0 Red [7:3] [78:74] +Color 0 [18:16] Color 0 Red [2:0] [78:76] +Color 0 [15:11] Color 0 Green [7:3] [73:69] +Color 0 [10:08] Color 0 Green [2:0] [73:71] +Color 0 [07:03] Color 0 Blue [7:3] [68:64] +Color 0 [02:00] Color 0 Blue [2:0] [68:66] + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 66 + LERP = 0 Decoding +When LERP = 0, a single 4-entry lookup table is formed using the three expanded colors, with the 4 th +entry defined as transparent black (ARGB=0,0,0,0). Each 2-bit Texel n Select field of the encoded +CC_ALPHA block is used to index into a 32-bit A8R8G8B8 color from the table completing the decode of +the CC_ALPHA block. + +FXT CC_ALPHA Interpolated Color Table (LERP=0) + Texel Select Color Alpha + 0 Color0.RGB Color0.Alpha + 1 Color1.RGB Color1.Alpha + 2 Color2.RGB Color2.Alpha + 3 Black (RGB=0,0,0) 0 + +LERP = 1 Decoding +When LERP = 1, the three expanded colors are used to create two tables of four interpolated colors. The +Color0,1 table is used as a lookup table for texel 0-15 indices, and the Color1,2 table used for texels 16- +31 indices, as shown in the following figures: + +FXT CC_ALPHA Interpolated Color Table (LERP=1, Texels 0-15) + Texel 0-15 Select Color ARGB + 0 Color0.ARGB + 1 (2*Color0.ARGB + Color1.ARGB + 1) /3 + 2 (Color0.ARGB + 2*Color1.ARGB + 1) /3 + 3 Color1.ARGB + +FXT CC_ALPHA Interpolated Color Table (LERP=1, Texels 16-31) + Texel 16-31 Select Color ARGB + 0 Color2.ARGB + 1 (2*Color2.ARGB + Color1.ARGB + 1) /3 + 2 (Color2.ARGB + 2*Color1.ARGB + 1) /3 + 3 Color1.ARGB + + +6.3.2 DXT Texture Formats +Note that non-power-of-2 dimensioned maps may require the surface to be padded out to the next +multiple of four texels – here the pad texels are not referenced by the device. +An 8-byte (QWord) block encoding can be used if the source texture contains no transparency (is +opaque) or if the transparency can be specified by a one-bit alpha. A 16-byte (DQWord) block encoding +can be used to support source textures that require more than one-bit alpha: here the 1st QWord is used +to encode the texel alpha values, and the 2nd QWord is used to encode the texel color values. +These three types of format are discussed in the following sections: + +  Opaque and One-bit Alpha Textures (DXT1) +  Opaque Textures (DXT1_RGB) +  Textures with Alpha Channels (DXT2-5) + +Notes: + +  Any single texture must specify that its data is stored as 64 or 128 bits per group of 16 texels. If 64- + bit blocks—that is, format DXT1—are used for the texture, it is possible to mix the opaque and one- + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 67 + bit alpha formats on a per-block basis within the same texture. In other words, the comparison of the + unsigned integer magnitude of color_0 and color_1 is performed uniquely for each block of 16 texels. +  When 128-bit blocks are used, then the alpha channel must be specified in either explicit (format + DXT2 or DXT3) or interpolated mode (format DXT4 or DXT5) for the entire texture. Note that as with + color, once interpolated mode is selected then either 8 interpolated alphas or 6 interpolated alphas + mode can be used on a block-by-block basis. Again the magnitude comparison of alpha_0 and + alpha_1 is done uniquely on a block-by-block basis. + +6.3.2.1 Opaque and One-bit Alpha Textures (DXT1 / BC1) +Texture format DXT1 is for textures that are opaque or have a single transparent color. For each opaque +or one-bit alpha block, two 16-bit R5G6B5 values and a 4x4 bitmap with 2-bits-per-pixel are stored. This +totals 64 bits (1 QWord) for 16 texels, or 4-bits-per-texel. +In the block bitmap, there are two bits per texel to select between the four colors, two of which are stored +in the encoded data. The other two colors are derived from these stored colors by linear interpolation. +The one-bit alpha format is distinguished from the opaque format by comparing the two 16-bit color +values stored in the block. They are treated as unsigned integers. If the first color is greater than the +second, it implies that only opaque texels are defined. This means four colors will be used to represent +the texels. In four-color encoding, there are two derived colors and all four colors are equally distributed in +RGB color space. This format is analogous to R5G6B5 format. Otherwise, for one-bit alpha transparency, +three colors are used and the fourth is reserved to represent transparent texels. Note that the color blocks +in DXT2-5 formats strictly use four colors, as the alpha values are obtained from the alpha block . +In three-color encoding, there is one derived color and the fourth two-bit code is reserved to indicate a +transparent texel (alpha information). This format is analogous to A1R5G5B5, where the final bit is used +for encoding the alpha mask. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 68 + The following piece of pseudo-code illustrates the algorithm for deciding whether three- or four-color +encoding is selected: +if (color_0 > color_1) +{ + // Four-color block: derive the other two colors. + // 00 = color_0, 01 = color_1, 10 = color_2, 11 = color_3 + // These two bit codes correspond to the 2-bit fields + // stored in the 64-bit block. + color_2 = (2 * color_0 + color_1) / 3; + color_3 = (color 0 + 2 * color_1) / 3; +} +else +{ + // Three-color block: derive the other color. + // 00 = color_0, 01 = color_1, 10 = color_2, + // 11 = transparent. + // These two bit codes correspond to the 2-bit fields + // stored in the 64-bit block. + color_2 = (color_0 + color_1) / 2; + color_3 = transparent; +} + +The following tables show the memory layout for the 8-byte block. It is assumed that the first index +corresponds to the y-coordinate and the second corresponds to the x-coordinate. For example, +Texel[1][2] refers to the texture map pixel at (x,y) = (2,1). +Here is the memory layout for the 8-byte (64-bit) block: + Word Address 16-bit Word + 0 Color_0 + 1 Color_1 + 2 Bitmap Word_0 + 3 Bitmap Word_1 + +Color_0 and Color_1 (colors at the two extremes) are laid out as follows: + Bits Color + 15:11 Red color component + 10:5 Green color component + 4:0 Blue color component + + + Bits Texel + 1:0 (LSB) Texel[0][0] + 3:2 Texel[0][1] + 5:4 Texel[0][2] + 7:6 Texel[0][3] + 9:8 Texel[1][0] + 11:10 Texel[1][1] + 13:12 Texel[1][2] + 15:14 Texel[1][3] + +Bitmap Word_1 is laid out as follows: + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 69 + Bits Texel + 1:0 (LSB) Texel[2][0] + 3:2 Texel[2][1] + 5:4 Texel[2][2] + 7:6 Texel[2][3] + 9:8 Texel[3][0] + 11:10 Texel[3][1] + 13:12 Texel[3][2] + 15:14 (MSB) Texel[3][3] + +Example of Opaque Color Encoding +As an example of opaque encoding, we will assume that the colors red and black are at the extremes. We +will call red color_0 and black color_1. There will be four interpolated colors that form the uniformly +distributed gradient between them. To determine the values for the 4x4 bitmap, the following calculations +are used: +00 ? color_0 +01 ? color_1 +10 ? 2/3 color_0 + 1/3 color_1 +11 ? 1/3 color_0 + 2/3 color_1 + +Example of One-bit Alpha Encoding +This format is selected when the unsigned 16-bit integer, color_0, is less than the unsigned 16-bit integer, +color_1. An example of where this format could be used is leaves on a tree to be shown against a blue +sky. Some texels could be marked as transparent while three shades of green are still available for the +leaves. Two of these colors fix the extremes, and the third color is an interpolated color. +The bitmap encoding for the colors and the transparency is determined using the following calculations: +00 ? color_0 +01 ? color_1 +10 ? 1/2 color_0 + 1/2 color_1 +11 ? Transparent + +6.3.2.2 Opaque Textures (DXT1_RGB) +Texture format DXT1_RGB is identical to DXT1, with the exception that the One-bit Alpha encoding is +removed. Color 0 and Color 1 are not compared, and the resulting texel color is derived strictly from the +Opaque Color Encoding. The alpha channel defaults to 1.0. + +6.3.2.3 Compressed Textures with Alpha Channels (DXT2-5 / BC2-3) +There are two ways to encode texture maps that exhibit more complex transparency. In each case, a +block that describes the transparency precedes the 64-bit block already described. The transparency is +either represented as a 4x4 bitmap with four bits per pixel (explicit encoding), or with fewer bits and linear +interpolation analogous to what is used for color encoding. +The transparency block and the color block are laid out as follows: + Word Address 64-bit Block + 3:0 Transparency block + 7:4 Previously described 64-bit block + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 70 + Explicit Texture Encoding +For explicit texture encoding (DXT2 and DXT3 formats), the alpha components of the texels that describe +transparency are encoded in a 4x4 bitmap with 4 bits per texel. These 4 bits can be achieved through a +variety of means such as dithering or by simply using the 4 most significant bits of the alpha data. +However they are produced, they are used just as they are, without any form of interpolation. +Note: +DirectDraw’s compression method uses the 4 most significant bits. +The following tables illustrate how the alpha information is laid out in memory, for each 16-bit word. +This is the layout for Word 0: + Bits Alpha + 3:0 (LSB) [0][0] + 7:4 [0][1] + 11:8 [0][2] + 15:12 (MSB) [0][3] + +This is the layout for Word 1: + Bits Alpha + 3:0 (LSB) [1][0] + 7:4 [1][1] + 11:8 [1][2] + 15:12 (MSB) [1][3] + +This is the layout for Word 2: + Bits Alpha + 3:0 (LSB) [2][0] + 7:4 [2][1] + 11:8 [2][2] + 15:12 (MSB) [2][3] + +This is the layout for Word 3: + Bits Alpha + 3:0 (LSB) [3][0] + 7:4 [3][1] + 11:8 [3][2] + 15:12 (MSB) [3][3] + +Three-Bit Linear Alpha Interpolation +The encoding of transparency for the DXT4 and DXT5 formats is based on a concept similar to the linear +encoding used for color. Two 8-bit alpha values and a 4x4 bitmap with three bits per pixel are stored in +the first eight bytes of the block. The representative alpha values are used to interpolate intermediate +alpha values. Additional information is available in the way the two alpha values are stored. If alpha_0 is +greater than alpha_1, then six intermediate alpha values are created by the interpolation. Otherwise, four +intermediate alpha values are interpolated between the specified alpha extremes. The two additional +implicit alpha values are 0 (fully transparent) and 255 (fully opaque). +The following pseudo-code illustrates this algorithm: + // 8-alpha or 6-alpha block? + if (alpha_0 > alpha_1) { + // 8-alpha block: derive the other 6 alphas. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 71 + // 000 = alpha_0, 001 = alpha_1, others are interpolated + alpha_2 = (6 * alpha_0 + alpha_1) / 7; // bit code 010 + alpha_3 = (5 * alpha_0 + 2 * alpha_1) / 7; // Bit code 011 + alpha_4 = (4 * alpha_0 + 3 * alpha_1) / 7; // Bit code 100 + alpha_5 = (3 * alpha_0 + 4 * alpha_1) / 7; // Bit code 101 + alpha_6 = (2 * alpha_0 + 5 * alpha_1) / 7; // Bit code 110 + alpha_7 = (alpha_0 + 6 * alpha_1) / 7; // Bit code 111 + } + else { // 6-alpha block: derive the other alphas. + // 000 = alpha_0, 001 = alpha_1, others are interpolated + alpha_2 = (4 * alpha_0 + alpha_1) / 5; // Bit code 010 + alpha_3 = (3 * alpha_0 + 2 * alpha_1) / 5; // Bit code 011 + alpha_4 = (2 * alpha_0 + 3 * alpha_1) / 5; // Bit code 100 + alpha_5 = (alpha_0 + 4 * alpha_1) / 5; // Bit code 101 + alpha_6 = 0; // Bit code 110 + alpha_7 = 255; // Bit code 111 + } + +The memory layout of the alpha block is as follows: + Byte Alpha + 0 Alpha_0 + 1 Alpha_1 + 2 [0][2] (2 LSBs), [0][1], [0][0] + 3 [1][1] (1 LSB), [1][0], [0][3], [0][2] (1 + MSB) + 4 [1][3], [1][2], [1][1] (2 MSBs) + 5 [2][2] (2 LSBs), [2][1], [2][0] + 6 [3][1] (1 LSB), [3][0], [2][3], [2][2] (1 + MSB) + 7 [3][3], [3][2], [3][1] (2 MSBs) + + +6.3.3 BC4 +These formats (BC4_UNORM and BC4_SNORM) compresses single-component UNORM or SNORM +data. An 8-byte compression block represents a 4x4 block of texels. The texels are labeled as +texel[row][column] where both row and column range from 0 to 3. Texel[0][0] is the upper left texel. +The 8-byte compression block is laid out as follows: + Bit Description + 7:0 red_0 + 15:8 red_1 + 18:16 texel[0][0] bit code + 21:19 texel[0][1] bit code + 24:22 texel[0][2] bit code + 27:25 texel[0][3] bit code + 30:28 texel[1][0] bit code + 33:31 texel[1][1] bit code + 36:34 texel[1][2] bit code + 39:37 texel[1][3] bit code + 42:40 texel[2][0] bit code + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 72 + Bit Description + 45:43 texel[2][1] bit code + 48:46 texel[2][2] bit code + 51:49 texel[2][3] bit code + 54:52 texel[3][0] bit code + 57:55 texel[3][1] bit code + 60:58 texel[3][2] bit code + 63:61 texel[3][3] bit code + +There are two interpolation modes, chosen based on which reference color is larger. The first mode has +the two reference colors plus six equal-spaced interpolated colors between the reference colors, chosen +based on the three-bit code for that texel. The second mode has the two reference colors plus four +interpolated colors, chosen by six of the three-bit codes. The remaining two codes select min and max +values for the colors. The values of red_0 through red_7 are computed as follows: + red_0 = red_0; // bit code 000 + red_1 = red_1; // bit code 001 + if (red_0 > red_1) { + red_2 = (6 * red_0 + 1 * red_1) / 7; // bit code 010 + red_3 = (5 * red_0 + 2 * red_1) / 7; // bit code 011 + red_4 = (4 * red_0 + 3 * red_1) / 7; // bit code 100 + red_5 = (3 * red_0 + 4 * red_1) / 7; // bit code 101 + red_6 = (2 * red_0 + 5 * red_1) / 7; // bit code 110 + red_7 = (1 * red_0 + 6 * red_1) / 7; // bit code 111 + } + else { + red_2 = (4 * red_0 + 1 * red_1) / 5; // bit code 010 + red_3 = (3 * red_0 + 2 * red_1) / 5; // bit code 011 + red_4 = (2 * red_0 + 3 * red_1) / 5; // bit code 100 + red_5 = (1 * red_0 + 4 * red_1) / 5; // bit code 101 + red_6 = UNORM ? 0.0 : -1.0; // bit code 110 (0 for UNORM, -1 for SNORM) + red_7 = 1.0; // bit code 111 + } + + + +6.3.4 BC5 +These formats (BC5_UNORM and BC5_SNORM) compresses dual-component UNORM or SNORM +data. A 16-byte compression block represents a 4x4 block of texels. The texels are labeled as +texel[row][column] where both row and column range from 0 to 3. Texel[0][0] is the upper left texel. +The 16-byte compression block is laid out as follows: + Bit Description + 7:0 red_0 + 15:8 red_1 + 18:16 texel[0][0] red bit code + 21:19 texel[0][1] red bit code + 24:22 texel[0][2] red bit code + 27:25 texel[0][3] red bit code + 30:28 texel[1][0] red bit code + 33:31 texel[1][1] red bit code + 36:34 texel[1][2] red bit code + 39:37 texel[1][3] red bit code + 42:40 texel[2][0] red bit code + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 73 + Bit Description + 45:43 texel[2][1] red bit code + 48:46 texel[2][2] red bit code + 51:49 texel[2][3] red bit code + 54:52 texel[3][0] red bit code + 57:55 texel[3][1] red bit code + 60:58 texel[3][2] red bit code + 63:61 texel[3][3] red bit code + 71:64 green_0 + 79:72 green_1 + 82:80 texel[0][0] green bit code + 85:83 texel[0][1] green bit code + 88:86 texel[0][2] green bit code + 91:89 texel[0][3] green bit code + 94:92 texel[1][0] green bit code + 97:95 texel[1][1] green bit code + 100:98 texel[1][2] green bit code + 103:101 texel[1][3] green bit code + 106:104 texel[2][0] green bit code + 109:107 texel[2][1] green bit code + 112:110 texel[2][2] green bit code + 115:113 texel[2][3] green bit code + 118:116 texel[3][0] green bit code + 121:119 texel[3][1] green bit code + 124:122 texel[3][2] green bit code + 127:125 texel[3][3] green bit code + +There are two interpolation modes, chosen based on which reference color is larger. The first mode has +the two reference colors plus six equal-spaced interpolated colors between the reference colors, chosen +based on the three-bit code for that texel. The second mode has the two reference colors plus four +interpolated colors, chosen by six of the three-bit codes. The remaining two codes select min and max +values for the colors. The values of red_0 through red_7 are computed as follows: + red_0 = red_0; // bit code 000 + red_1 = red_1; // bit code 001 + if (red_0 > red_1) { + red_2 = (6 * red_0 + 1 * red_1) / 7; // bit code 010 + red_3 = (5 * red_0 + 2 * red_1) / 7; // bit code 011 + red_4 = (4 * red_0 + 3 * red_1) / 7; // bit code 100 + red_5 = (3 * red_0 + 4 * red_1) / 7; // bit code 101 + red_6 = (2 * red_0 + 5 * red_1) / 7; // bit code 110 + red_7 = (1 * red_0 + 6 * red_1) / 7; // bit code 111 + } + else { + red_2 = (4 * red_0 + 1 * red_1) / 5; // bit code 010 + red_3 = (3 * red_0 + 2 * red_1) / 5; // bit code 011 + red_4 = (2 * red_0 + 3 * red_1) / 5; // bit code 100 + red_5 = (1 * red_0 + 4 * red_1) / 5; // bit code 101 + red_6 = UNORM ? 0.0 : -1.0; // bit code 110 (0 for UNORM, -1 for SNORM) + red_7 = 1.0; // bit code 111 + } + + +The same calculations are done for green, using the corresponding reference colors and bit codes. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 74 + 6.3.5 BC6H +These formats (BC6H_UF16 and BC6H_SF16) compress 3-channel images with high dynamic range (> 8 +bits per channel). BC6H supports floating point denorms but there is no support for INF and NaN, other +than with BC6H_SF16 –INF is supported. The alpha channel is not included, thus alpha is returned at its +default value. +The BC6H block is 16 bytes and represents a 4x4 block of texels. The texels are labeled as +texel[row][column] where both row and column range from 0 to 3. Texel[0][0] is the upper left texel. BC6H +has 14 different modes, the mode that the block is in is contained in the least significant bits (either 2 or 5 +bits). +The basic scheme consists of interpolating colors along either one or two lines, with per-texel indices +indicating which color along the line is chosen for each texel. If a two-line mode is selected, one of 32 +partition sets is indicated which selects which of the two lines each texel is assigned to. + +6.3.5.1 Field Definition +There are 14 possible modes for a BC6H block, the format of each is indicated in the 14 tables below. +The mode is selected by the unique mode bits specified in each table. The first 10 modes use two lines +(“TWO”), and the last 4 use one line (“ONE”). The difference between the various two-line and one-line +modes is with the precision of the first endpoint and the number of bits used to store delta values for the +remaining endpoints. Two modes (9 and 10) specify each endpoint as an original value rather than using +the deltas (these are indicated as having no delta values). +The endpoints values and deltas are indicated in the tables using a two-letter name. The first letter is “r”, +“g”, or “b” indicating the color channel. The second letter is “w”, “x”, “y”, or “z” indicating which of the four +endpoints. The first line has endpoints “w” and “x”, with “w” being the endpoint that is fully specified (i.e. +not as a delta). The second line has endpoints “y” and “z”. Modes using ONE mode do not have +endpoints “y” and “z” as they have only one line. +In addition to the mode and endpoint data, TWO blocks contain a 5-bit “partition” which selects one of the +partition sets, and a 46-bit set of indices. ONE blocks contain a 63-bit set of indices. These are described +in more detail below. +Mode 0: (TWO) Red, Green, Blue: 10-bit endpoint, 5-bit deltas + Bit Description + 1:0 mode = 00 + 2 gy[4] + 3 by[4] + 4 bz[4] + 14:5 rw[9:0] + 24:15 gw[9:0] + 34:25 bw[9:0] + 39:35 rx[4:0] + 40 gz[4] + 44:41 gy[3:0] + 49:45 gx[4:0] + 50 bz[0] + 54:51 gz[3:0] + 59:55 bx[4:0] + 60 bz[1] + 64:61 by[3:0] + 69:65 ry[4:0] + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 75 + Bit Description + 70 bz[2] + 75:71 rz[4:0] + 76 bz[3] + 81:77 partition + 127:82 indices + +Mode 1: (TWO) Red, Green, Blue: 7-bit endpoint, 6-bit deltas + Bit Description + 1:0 mode = 01 + 2 gy[5] + 3 gz[4] + 4 gz[5] + 11:5 rw[6:0] + 12 bz[0] + 13 bz[1] + 14 by[4] + 21:15 gw[6:0] + 22 by[5] + 23 bz[2] + 24 gy[4] + 31:25 bw[6:0] + 32 bz[3] + 33 bz[5] + 34 bz[4] + 40:35 rx[5:0] + 44:41 gy[3:0] + 50:45 gx[5:0] + 54:51 gz[3:0] + 60:55 bx[5:0] + 64:61 by[3:0] + 70:65 ry[5:0] + 76:71 rz[5:0] + 81:77 partition + 127:82 indices + +Mode 2: (TWO) Red: 11-bit endpoint, 5-bit deltas +Green, Blue: 11-bit endpoint, 4-bit deltas + Bit Description + 4:0 mode = 00010 + 14:5 rw[9:0] + 24:15 gw[9:0] + 34:25 bw[9:0] + 39:35 rx[4:0] + 40 rw[10] + 44:41 gy[3:0] + 48:45 gx[3:0] + 49 gw[10] + 50 bz[0] + 54:51 gz[3:0] + 58:55 bx[3:0] + 59 bw[10] + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 76 + Bit Description + 60 bz[1] + 64:61 by[3:0] + 69:65 ry[4:0] + 70 bz[2] + 75:71 rz[4:0] + 76 bz[3] + 81:77 partition + 127:82 indices + +Mode 3: (TWO) Red, Blue: 11-bit endpoint, 4-bit deltas +Green: 11-bit endpoint, 5-bit deltas + Bit Description + 4:0 mode = 00110 + 14:5 rw[9:0] + 24:15 gw[9:0] + 34:25 bw[9:0] + 38:35 rx[3:0] + 39 rw[10] + 40 gz[4] + 44:41 gy[3:0] + 49:45 gx[4:0] + 50 gw[10] + 54:51 gz[3:0] + 58:55 bx[3:0] + 59 bw[10] + 60 bz[1] + 64:61 by[3:0] + 68:65 ry[3:0] + 69 bz[0] + 70 bz[2] + 74:71 rz[3:0] + 75 gy[4] + 76 bz[3] + 81:77 partition + 127:82 indices + +Mode 4: (TWO) Red, Green: 11-bit endpoint, 4-bit deltas +Blue: 11-bit endpoint, 5-bit deltas + Bit Description + 4:0 mode = 01010 + 14:5 rw[9:0] + 24:15 gw[9:0] + 34:25 bw[9:0] + 38:35 rx[3:0] + 39 rw[10] + 40 by[4] + 44:41 gy[3:0] + 48:45 gx[3:0] + 49 gw[10] + 50 bz[0] + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 77 + Bit Description + 54:51 gz[3:0] + 59:55 bx[4:0] + 60 bw[10] + 64:61 by[3:0] + 68:65 ry[3:0] + 69 bz[1] + 70 bz[2] + 74:71 rz[3:0] + 75 bz[4] + 76 bz[3] + 81:77 partition + 127:82 indices + +Mode 5: (TWO) Red, Green, Blue: 9-bit endpoint, 5-bit deltas + Bit Description + 4:0 mode = 01110 + 13:5 rw[8:0] + 14 by[4] + 23:15 gw[8:0] + 24 gy[4] + 33:25 bw[8:0] + 34 bz[4] + 39:35 rx[4:0] + 40 gz[4] + 44:41 gy[3:0] + 49:45 gx[3:0] + 50 bz[0] + 54:51 gz[3:0] + 59:55 bx[4:0] + 60 bz[1] + 64:61 by[3:0] + 69:65 ry[4:0] + 70 bz[2] + 75:71 rz[4:0] + 76 bz[3] + 81:77 partition + 127:82 indices + +Mode 6: (TWO) Red: 8-bit endpoint, 6-bit deltas +Green, Blue: 8-bit endpoint, 5-bit deltas + Bit Description + 4:0 mode = 10010 + 12:5 rw[7:0] + 13 gz[4] + 14 by[4] + 22:15 gw[7:0] + 23 bz[2] + 24 gy[4] + 32:25 bw[7:0] + 33 bz[3] + 34 bz[4] + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 78 + Bit Description + 40:35 rx[5:0] + 44:41 gy[3:0] + 49:45 gx[4:0] + 50 bz[0] + 54:51 gz[3:0] + 59:55 bx[4:0] + 60 gz[1] + 64:61 by[3:0] + 70:65 ry[5:0] + 76:71 rz[5:0] + 81:77 partition + 127:82 indices + +Mode 7: (TWO) Red, Blue: 8-bit endpoint, 5-bit deltas +Green: 8-bit endpoint, 6-bit deltas + Bit Description + 4:0 mode = 10110 + 12:5 rw[7:0] + 13 bz[0] + 14 by[4] + 22:15 gw[7:0] + 23 gy[5] + 24 gy[4] + 32:25 bw[7:0] + 33 gz[5] + 34 bz[4] + 39:35 rx[4:0] + 40 gz[4] + 44:41 gy[3:0] + 50:45 gx[5:0] + 54:51 gz[3:0] + 59:55 bx[4:0] + 60 bz[1] + 64:61 by[3:0] + 69:65 ry[4:0] + 70 bz[2] + 75:71 rz[4:0] + 76 bz[3] + 81:77 partition + 127:82 indices + +Mode 8: (TWO) Red, Green: 8-bit endpoint, 5-bit deltas +Blue: 8-bit endpoint, 6-bit deltas + Bit Description + 4:0 mode = 11010 + 12:5 rw[7:0] + 13 bz[1] + 14 by[4] + 22:15 gw[7:0] + 23 by[5] + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 79 + Bit Description + 24 gy[4] + 32:25 bw[7:0] + 33 bz[5] + 34 bz[4] + 39:35 rx[4:0] + 40 gz[4] + 44:41 gy[3:0] + 49:45 gx[4:0] + 50 bz[0] + 54:51 gz[3:0] + 60:55 bx[5:0] + 64:61 by[3:0] + 69:65 ry[4:0] + 70 bz[2] + 75:71 rz[4:0] + 76 bz[3] + 81:77 partition + 127:82 indices + +Mode 9: (TWO) Red, Green, Blue: 6-bit endpoints for all four, no deltas + Bit Description + 4:0 mode = 11110 + 10:5 rw[5:0] + 11 gz[4] + 12 bz[0] + 13 bz[1] + 14 by[4] + 20:15 gw[5:0] + 21 gy[5] + 22 by[5] + 23 bz[2] + 24 gy[4] + 30:25 bw[5:0] + 31 gz[5] + 32 bz[3] + 33 bz[5] + 34 bz[4] + 40:35 rx[5:0] + 44:41 gy[3:0] + 50:45 gx[5:0] + 54:51 gz[3:0] + 60:55 bx[5:0] + 64:61 by[3:0] + 70:65 ry[5:0] + 76:71 rz[5:0] + 81:77 partition + 127:82 indices + +Mode 10: (ONE) Red, Green, Blue: 10-bit endpoints for both, no deltas + Bit Description + 4:0 mode = 00011 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 80 + Bit Description + 14:5 rw[9:0] + 24:15 gw[9:0] + 34:25 bw[9:0] + 44:35 rx[9:0] + 54:45 gx[9:0] + 64:55 bx[9:0] + 127:65 indices + +Mode 11: (ONE) Red, Green, Blue: 11-bit endpoints, 9-bit deltas + Bit Description + 4:0 mode = 00111 + 14:5 rw[9:0] + 24:15 gw[9:0] + 34:25 bw[9:0] + 43:35 rx[8:0] + 44 rw[10] + 53:45 gx[8:0] + 54 gw[10] + 63:55 bx[8:0] + 64 bw[10] + 127:65 indices + +Mode 12: (ONE) Red, Green, Blue: 12-bit endpoints, 8-bit deltas + Bit Description + 4:0 mode = 01011 + 14:5 rw[9:0] + 24:15 gw[9:0] + 34:25 bw[9:0] + 42:35 rx[7:0] + 43 rw[11] + 44 rw[10] + 52:45 gx[7:0] + 53 gw[11] + 54 gw[10] + 62:55 bx[7:0] + 63 bw[11] + 64 bw[10] + 127:65 indices + +Mode 13: (ONE) Red, Green, Blue: 16-bit endpoints, 4-bit deltas + Bit Description + 4:0 mode = 01111 + 14:5 rw[9:0] + 24:15 gw[9:0] + 34:25 bw[9:0] + 38:35 rx[3:0] + 39 rw[15] + 40 rw[14] + 41 rw[13] + 42 rw[12] + 43 rw[11] + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 81 + Bit Description + 44 rw[10] + 48:45 gx[3:0] + 49 gw[15] + 50 gw[14] + 51 gw[13] + 52 gw[12] + 53 gw[11] + 54 gw[10] + 58:55 bx[3:0] + 59 bw[15] + 60 bw[14] + 61 bw[13] + 62 bw[12] + 63 bw[11] + 64 bw[10] + 127:65 indices + +Undefined mode values (10011, 10111, 11011, and 11111) return zero in the RGB channels. +The “indices” fields are defined as follows: +TWO mode indices field with fix-up index [1] at texel[3][3] + Bit Description + 83:82 texel[0][0] index + 86:84 texel[0][1] index + 89:87 texel[0][2] index + 92:90 texel[0][3] index + 95:93 texel[1][0] index + 98:96 texel[1][1] index + 101:99 texel[1][2] index + 104:102 texel[1][3] index + 107:105 texel[2][0] index + 110:108 texel[2][1] index + 113:111 texel[2][2] index + 116:114 texel[2][3] index + 119:117 texel[3][0] index + 122:120 texel[3][1] index + 125:123 texel[3][2] index + 127:126 texel[3][3] index + +TWO mode indices field with fix-up index [1] at texel[0][2] + Bit Description + 83:82 texel[0][0] index + 86:84 texel[0][1] index + 88:87 texel[0][2] index + 91:89 texel[0][3] index + 94:92 texel[1][0] index + 97:95 texel[1][1] index + 100:98 texel[1][2] index + 103:101 texel[1][3] index + 106:104 texel[2][0] index + 109:107 texel[2][1] index + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 82 + Bit Description + 112:110 texel[2][2] index + 115:113 texel[2][3] index + 118:116 texel[3][0] index + 121:119 texel[3][1] index + 124:122 texel[3][2] index + 127:125 texel[3][3] index + +TWO mode indices field with fix-up index [1] at texel[2][0] + Bit Description + 83:82 texel[0][0] index + 86:84 texel[0][1] index + 89:87 texel[0][2] index + 92:90 texel[0][3] index + 95:93 texel[1][0] index + 98:96 texel[1][1] index + 101:99 texel[1][2] index + 104:102 texel[1][3] index + 106:105 texel[2][0] index + 109:107 texel[2][1] index + 112:110 texel[2][2] index + 115:113 texel[2][3] index + 118:116 texel[3][0] index + 121:119 texel[3][1] index + 124:122 texel[3][2] index + 127:125 texel[3][3] index + +ONE mode indices field + Bit Description + 67:65 texel[0][0] index + 71:68 texel[0][1] index + 75:72 texel[0][2] index + 79:76 texel[0][3] index + 83:80 texel[1][0] index + 87:84 texel[1][1] index + 91:88 texel[1][2] index + 95:92 texel[1][3] index + 99:96 texel[2][0] index + 103:100 texel[2][1] index + 107:104 texel[2][2] index + 111:108 texel[2][3] index + 115:112 texel[3][0] index + 119:116 texel[3][1] index + 123:120 texel[3][2] index + 127:124 texel[3][3] index + + +6.3.5.2 Endpoint Computation +The endpoints can be defined in many different ways, as shown above. This section describes how the +endpoints are computed from the bits in the compression block. The method used depends on whether +the BC6H format is signed (BC6H_SF16) or unsigned (BC6H_UF16). + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 83 + First, each channel (RGB) of each endpoint is extended to 16 bits. Each is handled identically and +independently, however in some modes different channels have different incoming precision which must +be accounted for. The following rules are employed: + +  If the format is BC6H_SF16 or the endpoint is a delta value, the value is sign-extended to 16 bits +  For all other cases, the value is zero-extended to 16 bits + +If there are no endpoints that are delta values, endpoint computation is complete. For endpoints that are +delta values, the next step involves computing the absolute endpoint. The “w” endpoint is always absolute +and acts as a base value for the other three endpoints. Each channel is handled identically and +independently. + x = w + x + y = w + y + z = w + z + + +The above is performed using 16-bit integer arithmetic. Overflows beyond 16 bits are ignored (any +resulting high bits are dropped). + +6.3.5.3 Palette Color Computation +The next step involves computing the color palette values that provide the available values for each +texel’s color. The color palette for each line consists of the two endpoint colors plus 6 (TWO mode) or 14 +(ONE mode) interpolated colors. Again each channel is processed independently. +First the endpoints are unquantized, with each channel of each endpoint being processed independently. +The number of bits in the original base “w” value represents the precision of the endpoints. The input +endpoint is called “e”, and the resulting endpoints are represented as 17-bit signed integers and called e’ +below. +For the BC6H_UF16 format: + +  if the precision is already 16 bits, e’ = e +  if e = 0, e’ = 0 +  if e is the maximum representible in the precision, e’ = 0xFFFF +  otherwise, e’ = ((e << 16) + 0x8000) >> precision + +For the BC6H_SF16 format, the value is treated as sign magnitude. The sign is not changed, e’ and e +refer only to the magnitude portion: + +  if the precision is already 16 bits, e’ = e +  if e = 0, e’ = 0 +  if e is the maximum representible in the precision, e’ = 0x7FFF +  otherwise, e’ = ((e << 15) + 0x4000) >> (precision – 1) + +Next, the palette values are generated using predefined weights, using the tables below: +palette[i] = (w’ * (64 – weight[i]) + x’ * weight[i] + 32) >> 6 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 84 + TWO mode weights: + 0 1 2 3 4 5 6 7 +palette +index + + 0 9 18 27 37 46 55 64 +weight + +ONE mode weights: + 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +pal +ette +ind +ex + + 0 4 9 13 17 21 26 30 34 38 43 47 51 55 60 64 +wei +ght + +Note that the two end palette indices are equal to the two endpoints given that the weights are 0 and 64. +In the above equation w’ and x’ represent the endpoints e’ computed in the previous step corresponding +to w and x, respectively. For the second line in TWO mode, w and x are replaced with y and z. +The final step in computing the palette colors is to rescale the final results. For BC6H_UF16 format, the +values are multiplied by 31/64. For BC6H_SF16, the values are multiplied by 31/32, treating them as sign +magnitude. These final 16-bit results are ultimately treated as 16-bit floats. + +6.3.5.4 Texel Selection +The final step is to select the appropriate palette index for each texel. This index then selects the 16-bit +per channel palette value, which is re-interpreted as a 16-bit floating point result for input into the filter. +This procedure differs depending on whether the mode is TWO or ONE. + +6.3.5.4.1 TWO Mode +32 partitions are defined for TWO, which are defined below. Each of the 32 cases shows the 4x4 block of +texels, and is indexed by adding its hexadecimal row number (00-1C) to its column number (0-3). Each +texel in the 4x4 block indicates whether that texel is part of line 0 (endpoints w and x) or line 1 (endpoints +y and z). Each case has one texel each of “[0]” and “[1]”, the index that this is at is termed the “fix-up +index”. These texels have one less bit in the index. + + 0 1 2 3 + [0] 0 1 1 [0] 0 0 1 [0] 1 1 1 [0] 0 0 1 +00 + 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 + 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 + 0 0 1 [1] 0 0 0 [1] 0 1 1 [1] 0 1 1 [1] + [0] 0 0 0 [0] 0 1 1 [0] 0 0 1 [0] 0 0 0 +04 + 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 + 0 0 0 1 0 1 1 1 0 1 1 1 0 0 1 1 + 0 0 1 [1] 1 1 1 [1] 1 1 1 [1] 0 1 1 [1] + [0] 0 0 0 [0] 0 1 1 [0] 0 0 0 [0] 0 0 0 +08 + 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 + 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 1 + 0 0 1 [1] 1 1 1 [1] 1 1 1 [1] 0 1 1 [1] + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 85 + [0] 0 0 1 [0] 0 0 0 [0] 0 0 0 [0] 0 0 0 +0C + 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 + 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 + 1 1 1 [1] 1 1 1 [1] 1 1 1 [1] 1 1 1 [1] + [0] 0 0 0 [0] 1 [1] 1 [0] 0 0 0 [0] 1 [1] 1 +10 + 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 + 1 1 1 0 0 0 0 0 [1] 0 0 0 0 0 0 1 + 1 1 1 [1] 0 0 0 0 1 1 1 0 0 0 0 0 + [0] 0 [1] 1 [0] 0 0 0 [0] 0 0 0 [0] 1 1 1 +14 + 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 + 0 0 0 0 [1] 1 0 0 [1] 0 0 0 0 0 1 1 + 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 [1] + [0] 0 [1] 1 [0] 0 0 0 [0] 1 [1] 0 [0] 0 [1] 1 +18 + 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 + 0 0 0 1 [1] 0 0 0 0 1 1 0 0 1 1 0 + 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 + [0] 0 0 1 [0] 0 0 0 [0] 1 [1] 1 [0] 0 [1] 1 +1C + 0 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 + [1] 1 1 0 [1] 1 1 1 1 0 0 0 1 0 0 1 + 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 + +The 46-bit “indices” field consists of a 3-bit palette index for each of the 16 texels, with the exception of +the bracketed texels that have only two bits each. The high bit of these texels is set to zero. + +6.3.5.4.2 ONE Mode +In ONE mode, there is only one set of palette colors, but the “indices” field is 63 bits. This field consists of +a 4-bit palette index for each of the 16 texels, with the exception of the texel at [0][0] which has only 3 +bits, the missing high bit being set to zero. + + +6.3.6 BC7 +These formats (BC7_UNORM and BC7_UNORM_SRGB) compresses 3-channel and 4-channel fixed +point images. +The BC7 block is 16 bytes and represents a 4x4 block of texels. The texels are labeled as +texel[row][column] where both row and column range from 0 to 3. Texel[0][0] is the upper left texel. BC7 +has 8 different modes, the mode that the block is in is contained in the least significant bits (1-8 bits +depending on mode). +The basic scheme consists of interpolating colors and alpha in some modes along either one, two, or +three lines, with per-texel indices indicating which color/alpha along the line is chosen for each texel. If a +two- or three-line mode is selected, one of 64 partition sets is indicated which selects which of the two +lines each texel is assigned to, although some modes are limited to the first 16 partition sets. In the color- +only modes, alpha is always returned at its default value of 1.0. +Some modes contain the following fields: + +  P-bits. These represent shared LSB for all components of the endpoint, which increases the + endpoint precision by one bit. In some cases both endpoints of a line share a P-bit. +  Rotation bits. For blocks with separate color and alpha, this 2-bit field allows selection of which of + the four components has its own indexes (scalar) vs. the other three components (vector). +  Index selector. This 1-bit field selects whether the scalar or vector components uses the 3-bit index + vs. the 2-bit index. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 86 + 6.3.6.1 Field Definition +There are 8 possible modes for a BC7 block, the format of each is indicated in the 8 tables below. The +mode is selected by the unique mode bits specified in each table. Each mode has particular +characteristics described at the top of the table. +Mode 0: Color only, 3 lines (THREE), 4-bit endpoints with one P-bit per endpoint, 3-bit indices, 16 +partitions + Bit Description + 0 mode = 0 + 4:1 partition + 8:5 R0 + 12:9 R1 + 16:13 R2 + 20:17 R3 + 24:21 R4 + 28:25 R5 + 32:29 G0 + 36:33 G1 + 40:37 G2 + 44:41 G3 + 48:45 G4 + 52:49 G5 + 56:53 B0 + 60:57 B1 + 64:61 B2 + 68:65 B3 + 72:69 B4 + 76:73 B5 + 77 P0 + 78 P1 + 79 P2 + 80 P3 + 81 P4 + 82 P5 + 127:83 indices + +Mode 1: Color only, 2 lines (TWO), 6-bit endpoints with one shared P-bit per line, 3-bit indices, 64 +partitions + Bit Description + 1:0 mode = 10 + 7:2 partition + 13:8 R0 + 19:14 R1 + 25:20 R2 + 31:26 R3 + 37:32 G0 + 43:38 G1 + 49:44 G2 + 55:50 G3 + 61:56 B0 + 67:62 B1 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 87 + Bit Description + 73:68 B2 + 79:74 B3 + 80 P0 + 81 P1 + 127:82 indices + +Mode 2: Color only, 3 lines (THREE), 5-bit endpoints, 2-bit indices, 64 partitions + Bit Description + 2:0 mode = 100 + 8:3 partition + 13:9 R0 + 18:14 R1 + 23:19 R2 + 28:24 R3 + 33:29 R4 + 38:34 R5 + 43:39 G0 + 48:44 G1 + 53:49 G2 + 58:54 G3 + 63:59 G4 + 68:64 G5 + 73:69 B0 + 78:74 B1 + 83:79 B2 + 88:84 B3 + 93:89 B4 + 98:94 B5 + 127:99 indices + +Mode 3: Color only, 2 lines (TWO), 7-bit endpoints with one P-bit per endpoint, 2-bit indices, 64 partitions + Bit Description + 3:0 mode = 1000 + 9:4 partition + 16:10 R0 + 23:17 R1 + 30:24 R2 + 37:31 R3 + 44:38 G0 + 51:45 G1 + 58:52 G2 + 65:59 G3 + 72:66 B0 + 79:73 B1 + 86:80 B2 + 93:87 B3 + 94 P0 + 95 P1 + 96 P2 + 97 P3 + 127:98 indices + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 88 + Mode 4: Color and alpha, 1 line (ONE), 5-bit color endpoints, 6-bit alpha endpoints, 16 2-bit indices, 16 3- +bit indices, 2-bit component rotation, 1-bit index selector + Bit Description + 4:0 mode = 10000 + 6:5 rotation + 7 index selector + 12:8 R0 + 17:13 R1 + 22:18 G0 + 27:23 G1 + 32:28 B0 + 37:33 B1 + 43:38 A0 + 49:44 A1 + 80:50 2-bit indices + 127:81 3-bit indices + +Mode 5: Color and alpha, 1 line (ONE), 7-bit color endpoints, 8-bit alpha endpoints, 2-bit color indices, 2- +bit alpha indices, 2-bit component rotation + Bit Description + 5:0 mode = 100000 + 7:6 rotation + 14:8 R0 + 21:15 R1 + 28:22 G0 + 35:29 G1 + 42:36 B0 + 49:43 B1 + 57:50 A0 + 65:58 A1 + 96:66 color indices + 127:97 alpha indices + +Mode 6: Combined color and alpha, 1 line (ONE), 7-bit endpoints with one P-bit per endpoint, 4-bit +indices + Bit Description + 6:0 mode = 1000000 + 13:7 R0 + 20:14 R1 + 27:21 G0 + 34:28 G1 + 41:35 B0 + 48:42 B1 + 55:49 A0 + 62:56 A1 + 63 P0 + 64 P1 + 127:65 indices + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 89 + Mode 7: Combined color and alpha, 2 lines (TWO), 5-bit endpoints with one P-bit per endpoint, 2-bit +indices, 64 partitions + Bit Description + 7:0 mode = 10000000 + 13:8 partition + 18:14 R0 + 23:19 R1 + 28:24 R2 + 33:29 R3 + 38:34 G0 + 43:39 G1 + 48:44 G2 + 53:49 G3 + 58:54 B0 + 63:59 B1 + 68:64 B2 + 73:69 B3 + 78:74 A0 + 83:79 A1 + 88:84 A2 + 93:89 A3 + 94 P0 + 95 P1 + 96 P2 + 97 P3 + 127:98 indices + +Undefined mode values (bits 7:0 = 00000000) return zero in the RGB channels. +The indices fields are variable in length and due to the different locations of the fix-up indices depending +on partition set there are a very large number of possible configurations. Each mode above indicates how +many bits each index has, and the fix-up indices (one in ONE mode, two in TWO mode, and three in +THREE mode) each have one less bit than indicated. However, the indices are always packed into the +index fields according to the table below, with the specific bit assignments of each texel following the +rules just given. + Bit Description + LSBs texel[0][0] index + texel[0][1] index + texel[0][2] index + texel[0][3] index + texel[1][0] index + texel[1][1] index + texel[1][2] index + texel[1][3] index + texel[2][0] index + texel[2][1] index + texel[2][2] index + texel[2][3] index + texel[3][0] index + texel[3][1] index + texel[3][2] index + MSBs texel[3][3] index + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 90 + 6.3.6.2 Endpoint Computation +The endpoints can be defined with different precision depending on mode, as shown above. This section +describes how the endpoints are computed from the bits in the compression block. Each component of +each endpoint follows the same steps. +If a P-bit is defined for the endpoint, it is first added as an additional LSB at the bottom of the endpoint +value. The endpoint is then bit-replicated to create an 8-bit fixed point endpoint value with a range from +0x00 to 0xFF. + +6.3.6.3 Palette Color Computation +The next step involves computing the color palette values that provide the available values for each +texel’s color. The color palette for each line consists of the two endpoint colors plus 2, 6, or 14 +interpolated colors, depending on the number of bits in the indices. Again each channel is processed +independently. +The equation to compute each palette color with index i, given two endpoints is as follows, using the +tables below to determine the weight for each palette index: +palette[i] = (E0 * (64 – weight[i]) + E1 * weight[i] + 32) >> 6 + +2-bit index weights: + 0 1 2 3 +palette index + + 0 21 43 64 +weight + +3-bit index weights: + 0 1 2 3 4 5 6 7 +palette +index + + 0 9 18 27 37 46 55 64 +weight + +4-bit index weights: + 0 1 2 3 4 5 6 7 8 9 10 11 12 13 +palette +index + + 0 4 9 13 17 21 26 30 34 38 43 47 51 55 +weight + +Note that the two end palette indices are equal to the two endpoints given that the weights are 0 and 64. +In the above equation E0 and E1 represent the even-numbered and odd-numbered endpoints computed +in the previous step for the component and line currently being computed. + +6.3.6.4 Texel Selection +The final step is to select the appropriate palette index for each texel. This index then selects the 8-bit per +channel palette value, which is interpreted as an 8-bit UNORM value for input into the filter (In +BC7_UNORM_SRGB to UNORM values first go through inverse gamma conversion). This procedure +differs depending on whether the mode is ONE, TWO, or THREE. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 91 + 6.3.6.4.1 ONE Mode +In ONE mode, there is only one set of palette colors, thus there is only a single “partition set” defined, with +all texels selecting line 0 and texel [0][0] being the “fix-up index” with one less bit in the index. + +6.3.6.4.2 TWO Mode +64 partitions are defined for TWO, which are defined below. Each of the 64 cases shows the 4x4 block of +texels, and is indexed by adding its hexadecimal row number (00-3C) to its column number (0-3). Each +texel in the 4x4 block indicates whether that texel is part of line 0 (endpoints 0 and 1) or line 1 (endpoints +2 and 3). Each case has one texel each of “[0]” and “[1]”, the index that this is at is termed the “fix-up +index”. These texels have one less bit in the index. + + 0 1 2 3 + [0] 0 1 1 [0] 0 0 1 [0] 1 1 1 [0] 0 0 1 +00 + 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 + 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 + 0 0 1 [1] 0 0 0 [1] 0 1 1 [1] 0 1 1 [1] + [0] 0 0 0 [0] 0 1 1 [0] 0 0 1 [0] 0 0 0 +04 + 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 + 0 0 0 1 0 1 1 1 0 1 1 1 0 0 1 1 + 0 0 1 [1] 1 1 1 [1] 1 1 1 [1] 0 1 1 [1] + [0] 0 0 0 [0] 0 1 1 [0] 0 0 0 [0] 0 0 0 +08 + 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 + 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 1 + 0 0 1 [1] 1 1 1 [1] 1 1 1 [1] 0 1 1 [1] + [0] 0 0 1 [0] 0 0 0 [0] 0 0 0 [0] 0 0 0 +0C + 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 + 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 + 1 1 1 [1] 1 1 1 [1] 1 1 1 [1] 1 1 1 [1] + [0] 0 0 0 [0] 1 [1] 1 [0] 0 0 0 [0] 1 [1] 1 +10 + 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 + 1 1 1 0 0 0 0 0 [1] 0 0 0 0 0 0 1 + 1 1 1 [1] 0 0 0 0 1 1 1 0 0 0 0 0 + [0] 0 [1] 1 [0] 0 0 0 [0] 0 0 0 [0] 1 1 1 +14 + 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 + 0 0 0 0 [1] 1 0 0 [1] 0 0 0 0 0 1 1 + 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 [1] + [0] 0 [1] 1 [0] 0 0 0 [0] 1 [1] 0 [0] 0 [1] 1 +18 + 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 + 0 0 0 1 [1] 0 0 0 0 1 1 0 0 1 1 0 + 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 + [0] 0 0 1 [0] 0 0 0 [0] 1 [1] 1 [0] 0 [1] 1 +1C + 0 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 + [1] 1 1 0 [1] 1 1 1 1 0 0 0 1 0 0 1 + 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 + [0] 1 0 1 [0] 0 0 0 [0] 1 0 1 [0] 0 1 1 +20 + 0 1 0 1 1 1 1 1 1 0 [1] 0 0 0 1 1 + 0 1 0 1 0 0 0 0 0 1 0 1 [1] 1 0 0 + 0 1 0 [1] 1 1 1 [1] 1 0 1 0 1 1 0 0 + [0] 0 [1] 1 [0] 1 0 1 [0] 1 1 0 [0] 1 0 1 +24 + 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 92 + 0 1 2 3 + 0 0 1 1 [1] 0 1 0 0 1 1 0 1 0 1 0 + 1 1 0 0 1 0 1 0 1 0 0 [1] 0 1 0 [1] + [0] 1 [1] 1 [0] 0 0 1 [0] 0 [1] 1 [0] 0 [1] 1 +28 + 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 1 + 1 1 0 0 [1] 1 0 0 0 1 0 0 1 1 0 1 + 1 1 1 0 1 0 0 0 1 1 0 0 1 1 0 0 + [0] 1 [1] 0 [0] 0 1 1 [0] 1 1 0 [0] 0 0 0 +2C + 1 0 0 1 1 1 0 0 0 1 1 0 0 1 [1] 0 + 1 0 0 1 1 1 0 0 1 0 0 1 0 1 1 0 + 0 1 1 0 0 0 1 [1] 1 0 0 [1] 0 0 0 0 + [0] 1 0 0 [0] 0 [1] 0 [0] 0 0 0 [0] 0 0 0 +30 + 1 1 [1] 0 0 1 1 1 0 0 [1] 0 0 1 0 0 + 0 1 0 0 0 0 1 0 0 1 1 1 [1] 1 1 0 + 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 + [0] 1 1 0 [0] 0 1 1 [0] 1 [1] 0 [0] 0 [1] 1 +34 + 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 + 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 + 0 0 1 [1] 1 0 0 [1] 1 1 0 0 0 1 1 0 + [0] 1 1 0 [0] 1 1 0 [0] 1 1 1 [0] 0 0 1 +38 + 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 0 + 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 + 1 0 0 [1] 1 0 0 [1] 0 0 0 [1] 0 1 1 [1] + [0] 0 0 0 [0] 0 [1] 1 [0] 0 [1] 0 [0] 1 0 0 +3C + 1 1 1 1 0 0 1 1 0 0 1 0 0 1 0 0 + 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 + 0 0 1 [1] 0 0 0 0 1 1 1 0 0 1 1 [1] + + +6.3.6.4.3 THREE Mode +64 partitions are defined for THREE, which are defined below. Each of the 64 cases shows the 4x4 block +of texels, and is indexed by adding its hexadecimal row number (00-3C) to its column number (0-3). Each +texel in the 4x4 block indicates whether that texel is part of line 0 (endpoints 0 and 1), line 1 (endpoints 2 +and 3), or line 2 (endpoints 4 and 5). Each case has one texel each of “[0]”, “[1]”, and “[2]”, the index that +this is at is termed the “fix-up index”. These texels have one less bit in the index. + + 0 1 2 3 + + [0] 0 1 [1] [0] 0 0 [1] [0] 0 0 0 [0] 2 2 [2] +00 + 0 0 1 1 0 0 1 1 2 0 0 1 0 0 2 2 + 0 2 2 1 [2] 2 1 1 [2] 2 1 1 0 0 1 1 + 2 2 2 [2] 2 2 2 1 2 2 1 [1] 0 1 1 [1] + [0] 0 0 0 [0] 0 1 [1] [0] 0 2 [2] [0] 0 1 1 +04 + 0 0 0 0 0 0 1 1 0 0 2 2 0 0 1 1 + [1] 1 2 2 0 0 2 2 1 1 1 1 [2] 2 1 1 + 1 1 2 [2] 0 0 2 [2] 1 1 1 [1] 2 2 1 [1] + [0] 0 0 0 [0] 0 0 0 [0] 0 0 0 [0] 0 1 2 +08 + 0 0 0 0 1 1 1 1 1 1 [1] 1 0 0 [1] 2 + [1] 1 1 1 [1] 1 1 1 2 2 2 2 0 0 1 2 + 2 2 2 [2] 2 2 2 [2] 2 2 2 [2] 0 0 1 [2] + [0] 1 1 2 [0] 1 2 2 [0] 0 1 [1] [0] 0 1 [1] +0C + 0 1 [1] 2 0 [1] 2 2 0 1 1 2 2 0 0 1 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 93 + 0 1 2 3 + 0 1 1 2 0 1 2 2 1 1 2 2 [2] 2 0 0 + 0 1 1 [2] 0 1 2 [2] 1 2 2 [2] 2 2 2 0 + [0] 0 0 [1] [0] 1 1 [1] [0] 0 0 0 [0] 0 2 [2] +10 + 0 0 1 1 0 0 1 1 1 1 2 2 0 0 2 2 + 0 1 1 2 [2] 0 0 1 [1] 1 2 2 0 0 2 2 + 1 1 2 [2] 2 2 0 0 1 1 2 [2] 1 1 1 [1] + [0] 1 1 [1] [0] 0 0 [1] [0] 0 0 0 [0] 0 0 0 +14 + 0 1 1 1 0 0 0 1 0 0 [1] 1 1 1 0 0 + 0 2 2 2 [2] 2 2 1 0 1 2 2 [2] 2 [1] 0 + 0 2 2 [2] 2 2 2 1 0 1 2 [2] 2 2 1 0 + [0] 1 2 [2] [0] 0 1 2 [0] 1 1 0 [0] 0 0 0 +18 + 0 [1] 2 2 0 0 1 2 1 2 [2] 1 0 1 [1] 0 + 0 0 1 1 [1] 1 2 2 [1] 2 2 1 1 2 [2] 1 + 0 0 0 0 2 2 2 [2] 0 1 1 0 1 2 2 1 + [0] 0 2 2 [0] 1 1 0 [0] 0 1 1 [0] 0 0 0 +1C + 1 1 0 2 0 [1] 1 0 0 1 2 2 2 0 0 0 + [1] 1 0 2 2 0 0 2 0 1 [2] 2 [2] 2 1 1 + 0 0 2 [2] 2 2 2 [2] 0 0 1 [1] 2 2 2 [1] + [0] 0 0 0 [0] 2 2 [2] [0] 0 1 [1] [0] 1 2 0 +20 + 0 0 0 2 0 0 2 2 0 0 1 2 0 [1] 2 0 + [1] 1 2 2 0 0 1 2 0 0 2 2 0 1 [2] 0 + 1 2 2 [2] 0 0 1 [1] 0 2 2 [2] 0 1 2 0 + [0] 0 0 0 [0] 1 2 0 [0] 1 2 0 [0] 0 1 1 +24 + 1 1 [1] 1 1 2 0 1 2 0 1 2 2 2 0 0 + 2 2 [2] 2 [2] 0 [1] 2 [1] [2] 0 1 1 1 [2] 2 + 0 0 0 0 0 1 2 0 0 1 2 0 0 0 1 [1] + [0] 0 1 1 [0] 1 0 [1] [0] 0 0 0 [0] 0 2 2 +28 + 1 1 [2] 2 0 1 0 1 0 0 0 0 1 [1] 2 2 + 2 2 0 0 2 2 2 2 [2] 1 2 1 0 0 2 2 + 0 0 1 [1] 2 2 2 [2] 2 1 2 [1] 1 1 2 [2] + [0] 0 2 [2] [0] 2 2 0 [0] 1 0 1 [0] 0 0 0 +2C + 0 0 1 1 1 2 [2] 1 2 2 [2] 2 2 1 2 1 + 0 0 2 2 0 2 2 0 2 2 2 2 [2] 1 2 1 + 0 0 1 [1] 1 2 2 [1] 0 1 0 [1] 2 1 2 [1] + [0] 1 0 [1] [0] 2 2 [2] [0] 0 0 2 [0] 0 0 0 +30 + 0 1 0 1 0 1 1 1 1 [1] 1 2 2 [1] 1 2 + 0 1 0 1 0 2 2 2 0 0 0 2 2 1 1 2 + 2 2 2 [2] 0 1 1 [1] 1 1 1 [2] 2 1 1 [2] + [0] 2 2 2 [0] 0 0 2 [0] 1 1 0 [0] 0 0 0 +34 + 0 [1] 1 1 1 1 1 2 0 [1] 1 0 0 0 0 0 + 0 1 1 1 [1] 1 1 2 0 1 1 0 2 1 [1] 2 + 0 2 2 [2] 0 0 0 [2] 2 2 2 [2] 2 1 1 [2] + [0] 1 1 0 [0] 0 2 2 [0] 0 2 2 [0] 0 0 0 +38 + 0 [1] 1 0 0 0 1 1 1 1 2 2 0 0 0 0 + 2 2 2 2 0 0 [1] 1 [1] 1 2 2 0 0 0 0 + 2 2 2 [2] 0 0 2 [2] 0 0 2 [2] 2 [1] 1 [2] + [0] 0 0 [2] [0] 2 2 2 [0] 1 0 [1] [0] 1 1 [1] +3C + 0 0 0 1 1 2 2 2 2 2 2 2 2 0 1 1 + 0 0 0 2 0 2 2 2 2 2 2 2 [2] 2 0 1 + 0 0 0 [1] [1] 2 2 [2] 2 2 2 [2] 2 2 2 0 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 94 + 6.4 Video Pixel/Texel Formats +This section describes the “video” pixel/texel formats with respect to memory layout. See the Overlay +chapter for a description of how the Y, U, V components are sampled. + + +6.4.1 Packed Memory Organization +Color components are all 8 bits in size for YUV formats. For YUV 4:2:2 formats each DWord will contain +two pixels and only the byte order affects the memory organization. +The following four YUV 4:2:2 surface formats are supported, listed with alternate names: + +  YCRCB_NORMAL (YUYV/YUY2) +  YCRCB_SWAPUVY (VYUY) (R8G8_B8G8_UNORM) +  YCRCB_SWAPUV(YVYU) (G8R8_G8B8_UNORM) +  YCRCB_SWAPY (UYVY) + +The channels are mapped as follows: +Cr (V) Red +Y Green +Cb (U) Blue + +Memory layout of packed YUV 4:2:2 formats + + + + +6.4.2 Planar Memory Organization +Planar formats use what could be thought of as separate buffers for the three color components. Because +there is a separate stride for the Y and U/V data buffers, several memory footprints can be supported. +Note: There is no direct support for use of planar video surfaces as textures. The sampling engine can be +used to operate on each of the 8bpp buffers separately (via a single-channel 8-bit format such as +I8_UNORM). The U and V buffers can be written concurrently by using multiple render targets from the +pixel shader. The Y buffer must be written in a separate pass due to its different size. +The following figure shows two types of memory organization for the YUV 4:2:0 planar video data: + 1. The memory organization of the common YV12 data, where all three planes are contiguous + and the strides of U and V components are half of that of the Y component. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 95 + 2. An alternative memory structure that the addresses of the three planes are independent but + satisfy certain alignment restrictions. + +YUV 4:2:0 Format Memory Organization + + + + +The following figure shows memory organization of the planar YUV 4:1:0 format where the planes are +contiguous. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 96 + YUV 4:1:0 Format Memory Organization + + + + +6.5 Additional Video Formats + # + Pack Surfa + Dx YUV ed / ce + format Plana State Surface Surface + name DxRGB format name r s Surface Format #1 Format #2 Format #3 Support By +DXGI_FOR DXGI_FORMAT_R8G8B Pack 1 R8G8B8A8_UNORM NA NA Sampler, PB +MAT_AYUV 8A8_UNORM ed + (V->R8, U->G8, Y->B8, + A->A8) +DXGI_FOR Pack 1 R8G8B8A8_UINT NA NA Sampler, + DXGI_FORMAT_R8G8 +MAT_AYUV ed HDC, PB + B8A8_UINT + (V->R8, U->G8, Y->B8, + A->A8) +DXGI_FOR Pack 1 R8G8B8A8_UNORM NA NA Sampler, + DXGI_FORMAT_R8G8 +MAT_YUY2 ed + B8A8_UNORM + (Y0->R8, U0->G8, Y1- + >B8, V0->A8) +NA NA Pack 1 R16G16B16A16_UINT NA NA Sampler, + ed HDC +NA NA Pack 1 R16G16B16A16_UINT NA NA Sampler, + ed HDC +NA NA Pack 1 R16G16B16A16_UINT NA NA Sampler, + ed HDC +DXGI_FOR Pack 1 R8G8B8A8_UINT NA NA Sampler, + DXGI_FORMAT_R8G8 +MAT_YUY2 ed HDC + B8A8_UINT + (Y0->R8, U0->G8, Y1- + >B8, V0->A8) +DXGI_FOR DXGI_FORMAT_R8G8_ Pack 1 NA NA Sampler + R8G8B8A8_UNORM +MAT_YUY2 B8G8_UNORM ed + In this case the width of + the view will appear to + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 97 + # + Pack Surfa + Dx YUV ed / ce + format Plana State Surface Surface + name DxRGB format name r s Surface Format #1 Format #2 Format #3 Support By + be twice the R8G8B8A8 + view, with hardware + reconstruction of RGBA + done automatically on + read (and before + filtering). +NA NA Pack 1 R16G16B16A16_UINT NA NA Sampler, + ed HDC +NA NA Pack 1 R16G16B16A16_UINT NA NA Sampler, + ed HDC +NA NA Pack 1 R16G16B16A16_UINT NA NA Sampler, + ed HDC +NA NA Pack 1 R8G8B8A8_UINT NA NA Sampler, + ed HDC +DXGI_FOR Plana 2 R8_UNORM NA Sampler, PB + Y= R8G8_UN +MAT_NV12 r + DXGI_FORMAT_R8_U ORM + NORM + chomra + U/V = pixel + DXGI_FORMAT_R8G8 dimensions + _UNORM 1/2 in both + (U->R8, V->G8) x and y + from the + Luma view + +NA NA Plana 3 R16_UNIT R16_UNIT R16_UNIT Sampler + r +NA NA Plana 3 R16_UNIT R16_UNIT R16_UNIT Sampler + r +NA NA Plana 3 R16_UNIT R16_UNIT R16_UNIT Sampler + r +NA NA Plana 3 R8_UNIT R8_UNIT R8_UNIT Sampler + r +NA NA Plana 2 R16_UNIT NA Sampler, + R16G16_U + r HDC + INT + chomra + pixel + dimensions + halved in + both x and + y from the + Luma view +NA NA Plana 2 R16_UNIT NA Sampler, + R16G16_U + r HDC + INT + chomra + pixel + dimensions + halved in + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 98 + # + Pack Surfa + Dx YUV ed / ce + format Plana State Surface Surface + name DxRGB format name r s Surface Format #1 Format #2 Format #3 Support By + both x and + y from the + Luma view +NA NA Plana 2 R16_UNIT NA Sampler, + R16G16_U + r HDC + INT + chomra + pixel + dimensions + halved in + both x and + y from the + Luma view + +DXGI_FOR Plana 2 R8_UNIT NA Sampler, + Y= R8G8_UIN +MAT_NV12 r HDC, PB + DXGI_FORMAT_R8_UI T + NT + chomra + U/V = pixel + DXGI_FORMAT_R8G8 dimensions + _UINT halved in + (U->R8, V->G8) both x and + y from the + Luma view +DXGI_FOR Plana 2 R8_UNORM NA Sampler, PB + Y= R8G8_UN +MAT_NV11 r + DXGI_FORMAT_R8_U ORM + NORM + chomra + U/V = pixel + DXGI_FORMAT_R8G8 dimensions + _UNORM 1/4 in both + (U->R8, V->G8) x and y + from the + Luma view +DXGI_FOR Plana 2 R8_UNIT NA Sampler, + Y= R8G8_UIN +MAT_NV11 r HDC, PB + DXGI_FORMAT_R8_UI T + NT + chomra + U/V = pixel + DXGI_FORMAT_R8G8 dimensions + _UINT 1/4 in both + (U->R8, V->G8) x and y + from the + Luma view +DXGI_FOR Plana 2 R16_UNORM NA Sampler, + Y= R16G16_U +MAT_P016 r HDC, PB + DXGI_FORMAT_R16_ NORM + UNORM + chomra + U/V = pixel + DXGI_FORMAT_R16G dimensions + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 99 + # + Pack Surfa + Dx YUV ed / ce + format Plana State Surface Surface + name DxRGB format name r s Surface Format #1 Format #2 Format #3 Support By + 16_UNORM 1/2 in both + (U->R16, V->G16) x and y + from the + Luma view +DXGI_FOR Plana 2 R16_UNIT NA Sampler, PB + Y= R16G16_U +MAT_P016 r + DXGI_FORMAT_R16_ INT + UINT + chomra + U/V = pixel + DXGI_FORMAT_R16G dimensions + 16_UINT 1/2 in both + (U->R16, V->G16) x and y + from the + Luma view + +DXGI_FOR Plana 2 R16_UNORM NA Sampler, + Y= R16G16_U +MAT_P010 r HDC, PB + DXGI_FORMAT_R16_ NORM + UNORM + chroma + U/V = pixel + DXGI_FORMAT_R16G dimensions + 16_UNORM 1/2 in both + (U->R16, V->G16) x and y + from the + Luma view +DXGI_FOR Plana 2 R16_UNIT NA Sampler, + Y= R16G16_U +MAT_P010 r HDC, PB + DXGI_FORMAT_R16_ INT + UINT + chomra + U/V = pixel + DXGI_FORMAT_R16G dimensions + 16_UINT 1/2 in both + (U->R16, V->G16) x and y + from the + Luma view +DXGI_FOR Pack 1 R16G16B16A16_UNOR NA NA Sampler, + DXGI_FORMAT_R16G +MAT_Y216 ed M + 16B16A16_UNORM + (Y0->R16, U->G16, Y1- + >B16, V->A16). +DXGI_FOR Pack 1 R16G16B16A16_UINT NA NA Sampler, + DXGI_FORMAT_R16G +MAT_Y216 ed HDC + 16B16A16_UINT + (Y0->R16, U->G16, Y1- + >B16, V->A16). + +DXGI_FOR Pack 1 R16G16B16A16_UNOR NA NA Sampler, + DXGI_FORMAT_R16G +MAT_Y210 ed M + 16B16A16_UNORM + (Y0->R16, U->G16, Y1- + >B16, V->A16). + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 100 + # + Pack Surfa + Dx YUV ed / ce + format Plana State Surface Surface + name DxRGB format name r s Surface Format #1 Format #2 Format #3 Support By +DXGI_FOR Pack 1 R16G16B16A16_UINT NA NA Sampler, + DXGI_FORMAT_R16G +MAT_Y210 ed HDC + 16B16A16_UINT + (Y0->R16, U->G16, Y1- + >B16, V->A16). +DXGI_FOR Pack 1 R16G16B16A16_UNOR NA NA Sampler, + DXGI_FORMAT_R16G +MAT_Y416 ed M HDC + 16B16A16_UNORM + (U->R16, Y->G16, V- + >B16, A->A16) + +DXGI_FOR Pack 1 R16G16B16A16_UINT NA NA Sampler, + DXGI_FORMAT_R16G +MAT_Y416 ed + 16B16A16_UINT + (U->R16, Y->G16, V- + >B16, A->A16) +DXGI_FOR Pack 1 R16G16B16A16_UNOR NA NA Sampler, + DXGI_FORMAT_R16G +MAT_Y410 ed M HDC + 16B16A16_UNORM + (U->R16, Y->G16, V- + >B16, A->A16) +DXGI_FOR Pack 1 R16G16B16A16_UINT NA NA Sampler, + DXGI_FORMAT_R16G +MAT_Y410 ed + 16B16A16_UINT + (U->R16, Y->G16, V- + >B16, A->A16) +NA NA Pack 1 R16G16_UINT NA NA Sampler, + ed HDC +NA NA Pack 1 R16G16_UINT NA NA Sampler, + ed HDC +NA NA Pack 1 R16G16_UINT NA NA Sampler, + ed HDC +NA NA Pack 1 R8G8_UINT NA NA Sampler, + ed HDC +NA NA Plana 2 R16_UNIT R16_UNIT NA Sampler, + r HDC +NA NA Plana 2 R16_UNIT R16_UNIT NA Sampler, + r HDC +NA NA Plana 2 R16_UNIT R16_UNIT NA Sampler, + r HDC +NA NA Plana 2 R8_UNIT R8_UNIT NA Sampler, + r HDC +NA NA Pack 1 R16_UNIT NA NA Sampler, + ed HDC +NA NA Pack 1 R16_UNIT NA NA Sampler, + ed HDC +NA NA Pack 1 R16_UNIT NA NA Sampler, + ed HDC +NA NA Pack 1 R8_UNIT NA NA Sampler, + ed HDC +NA NA Pack 1 R16_UNIT NA NA Sampler, + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 101 + # + Pack Surfa + Dx YUV ed / ce + format Plana State Surface Surface + name DxRGB format name r s Surface Format #1 Format #2 Format #3 Support By + ed HDC +NA NA Pack 1 R16_UNIT NA NA Sampler, + ed HDC +NA NA Pack 1 R16_UNIT NA NA Sampler, + ed HDC +NA NA Pack 1 R8_UNIT NA NA Sampler, + ed HDC +NA NA Pack 1 R16_UNIT NA NA Sampler, + ed HDC +NA NA Pack 1 R16_UNIT NA NA Sampler, + ed HDC +NA NA Pack 1 R16_UNIT NA NA Sampler, + ed HDC +NA NA Pack 1 R8_UNIT NA NA Sampler, + ed HDC + + + +6.6 Raw Format +A new surface format is added that is only supported with the untyped surface read/write and atomic +operation data port messages. This new format is called simply RAW. It means that the surface has no +inherent format. Surfaces of type RAW are addressed with byte-based offsets that must be DWord +aligned (multiple of 4). Data is returned in DWord quantities. The RAW surface format can be applied only +to surface types of BUFFER and STRBUF. + + +6.7 Surface Memory Organizations +See Memory Interface Functions chapter for a discussion of tiled vs. linear surface formats. + + +6.8 Graphics Translation Tables +The Graphics Translation Tables GTT (Graphics Translation Table, sometimes known as the global GTT) +and PPGTT (Per-Process Graphics Translation Table) are memory-resident page tables containing an +array of DWord Page Translation Entries (PTEs) used in mapping logical Graphics Memory addresses to +physical memory addresses, and sometimes snooped system memory “PCI” addresses. +The graphics translation tables must reside in (unsnooped) system memory. +The base address (MM offset) of the GTT and the PPGTT are programmed via the PGTBL_CTL and +PGTBL_CTL2 MI registers, respectively. The translation table base addresses must be 4KB aligned. The +GTT size can be either 128KB, 256KB or 512KB (mapping to 128MB, 256MB, and 512MB aperture sizes +respectively) and is physically contiguous. The global GTT should only be programmed via the range +defined by GTTADR. The PPGTT is programmed directly in memory. The per-process GTT (PPGTT) size +is controlled by the PGTBL_CTL2 register. The PPGTT can, in addition to the above sizes, also be 64KB +in size (corresponding to a 64MB aperture). Refer to the GTT Range chapter for a bit definition of the PTE +entries. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 102 + 6.9 Hardware Status Page +The hardware status page is a naturally-aligned 4KB page residing in snooped system memory. This +page exists primarily to allow the device to report status via PCI master writes – thereby allowing the +driver to read/poll WB memory instead of UC reads of device registers or UC memory. +The address of this page is programmed via the HWS_PGA MI register. The definition of that register (in +Memory Interface Registers) includes a description of the layout of the Hardware Status Page. + + +6.10 Instruction Ring Buffers +Instruction ring buffers are the memory areas used to pass instructions to the device. Refer to the +Programming Interface chapter for a description of how these buffers are used to transport instructions. +The RINGBUF register sets (defined in Memory Interface Registers) are used to specify the ring buffer +memory areas. The ring buffer must start on a 4KB boundary and be allocated in linear memory. The +length of any one ring buffer is limited to 2MB. +Note that “indirect” 3D primitive instructions (those that access vertex buffers) must reside in the same +memory space as the vertex buffers. + + +6.11 Instruction Batch Buffers +Instruction batch buffers are contiguous streams of instructions referenced via an +MI_BATCH_BUFFER_START and related instructions (see Memory Interface Instructions, Programming +Interface). They are used to transport instructions external to ring buffers. +Note that batch buffers should not be mapped to snooped SM (PCI) addresses. The device will treat +these as MainMemory (MM) address, and therefore not snoop the CPU cache. +The batch buffer must be QWord aligned and a multiple of QWords in length. The ending address is the +address of the last valid QWord in the buffer. The length of any single batch buffer is “virtually unlimited” +(i.e., could theoretically be 4GB in length). + + +6.12 2D Render Surfaces +These surfaces are used as general source and/or destination operands in 2D BLT operations. +Note that there is no coherency between 2D render surfaces and the texture cache. Software must +explicitly invalidate the texture cache before using a texture that has been modified via the BLT engine. +See the 2D Instruction and 2D Rendering chapters for specifics on how these surfaces are used, +restrictions on their size, placement, etc. + + +6.13 2D Monochrome Source +These 1 BPP (bit per pixel) surfaces are used as source operands to certain 2D BLT operations, where +the BLT engine expands the 1 BPP source to the required color depth. +The texture cache stores any monochrome sources. There is no mechanism to maintain coherency +between 2D render surfaces and texture-cached monochrome sources. Software must explicitly +invalidate the texture cache before using a memory-based monochrome source that has been modified + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 103 + via the BLT engine. (Here the assumption is that SW enforces memory-based monochrome source +surfaces as read-only surfaces.) +See the 2D Instruction and 2D Rendering chapters for specifics on how these surfaces are used, +restrictions on their size, placement, coherency rules, etc. + + +6.14 2D Color Pattern +Color pattern surfaces are used as special pattern operands in 2D BLT operations. +The device uses the texture cache to store color patterns. There is no mechanism to maintain coherency +between 2D render surfaces and (texture)-cached color patterns. Software is required to explicitly +invalidate the texture cache before using a memory-based color pattern that has been modified via the +BLT engine. (Here the assumption is that SW enforces memory-based color pattern surfaces as read-only +surfaces.) +See the 2D Instruction and 2D Rendering chapters for specifics on how these surfaces are used, +restrictions on their size, placement, etc. + + +6.15 3D Color Buffer (Destination) Surfaces +3D Color Buffer surfaces hold per-pixel color values for use in the 3D Pipeline. The 3D Pipeline always +requires a Color Buffer to be defined. +See the Non-Video Pixel/Texel Formats section in this chapter for details on the Color Buffer pixel +formats. See the 3D Instruction and 3D Rendering chapters for Color Buffer usage details. +The Color Buffer is defined as the BUFFERID_COLOR_BACK memory buffer via the +3DSTATE_BUFFER_INFO instruction. That buffer can be mapped to LM, SM (snooped or unsnooped) +and can be linear or tiled. When both the Depth and Color Buffers are tiled, the respective Tile Walk +directions must match. +When a linear Color Buffer and a linear Depth Buffer are used together: + +  The buffers may have different pitches, though both pitches must be a multiple of 32 bytes. +  The buffers must be co-aligned with a 32-byte region. + + +6.16 3D Depth Buffer Surfaces +Depth Buffer surfaces hold per-pixel depth values and per-pixel stencil values for use in the 3D Pipeline. +The 3D Pipeline does not require a Depth Buffer in general, though a Depth Buffer is required to perform +non-trivial Depth Test and Stencil Test operations. +The Depth Buffer is specified via the 3DSTATE_DEPTH_BUFFER command. See the description of that +instruction in Windower for restrictions. +See 7.17, 3D Depth Buffer Surfaces, for a summary of the possible Depth Buffer formats. See the Depth +Buffer Formats section in this chapter for details on the pixel formats. See the Windower and DataPort +chapters for details on the usage of the Depth Buffer. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 104 + Depth Buffer Formats + DepthBufferFormat / BPP (Bits Per + DepthComponent Pixel) Description +D32_FLOAT_S8X24_UINT 64 32-bit floating point Z depth value in first DWord, 8-bit stencil in + lower byte of second DWord +D32_FLOAT 32 32-bit floating point Z depth value +D24_UNORM_S8_UINT 32 24-bit fixed point Z depth value in lower 3 bytes, 8-bit stencil + value in upper byte +D16_UNORM 16 16-bit fixed point Z depth value + + + +6.17 3D Separate Stencil Buffer Surfaces +Separate Stencil Buffer surfaces hold per-pixel stencil values for use in the 3D Pipeline. Note that the 3D +Pipeline does not require a Stencil Buffer to be allocated, though a Stencil Buffer is required to perform +non-trivial Stencil Test operations. +UNRESOLVED CROSS REFERENCE, Depth Buffer Formats summarizes Stencil Buffer formats. Refer +to the Stencil Buffer Formats section in this chapter for details on the pixel formats. Refer to the Windower +chapters for Stencil Buffer usage details. +The Stencil buffer is specified via the 3DSTATE_STENCIL_BUFFER command. See that instruction +description in Windower for restrictions. + +Depth Buffer Formats + DepthBufferFormat / + DepthComponent BPP (bits per pixel) Description + S8_UINT/R8_ UNIT 8 8-bit stencil value in a byte + + + +6.18 Surface Layout +In addition to restrictions on maximum height, width, and depth, surfaces are also restricted to a +maximum size in bytes. This maximum is 2 GB for all products and all surface types. + + +6.18.1 Buffers +A buffer is an array of structures. Each structure contains up to 2048 bytes of elements. Each element is +a single surface format using one of the supported surface formats depending on how the surface is +being accessed. The surface pitch state for the surface specifies the size of each structure in bytes. +The buffer is stored in memory contiguously with each element in the structure packed together, and the +first element in the next structure immediately following the last element of the previous structure. Buffers +are supported only in linear memory. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 105 + 6.18.2 Structured Buffers +A structured buffer is a surface type that is accessed by a 2-dimensional coordinate. It can be thought of +as an array of structures, where each structure is a predefined number of DWords in size. The first +coordinate (U) defines the array index, and the second coordinate (V) is a byte offset into the structure +which must be a multiple of 4 (DWord aligned). A structured buffer must be defined with Surface Format +RAW. +The structured buffer has only one dimension programmed in SURFACE_STATE which indicates the +array size. The byte offset dimension (V) is assumed to be bounded only by the Surface Pitch. + + +6.18.3 1D Surfaces +One-dimensional surfaces are identical to 2D surfaces with height of one. Arrays of 1D surfaces are also +supported. Please refer to the 2D Surfaces section for details on how these surfaces are stored. + + + + +Surface Pitch is ignored for 1D surfaces. Surface QPitch specifies the distance in pixels between array +slices. QPitch should allow at least enough space for any mips that may be present. +A number of parameters are useful to determine where given pixels will be located on the 1D surface. +First, the width for each LOD “L” is computed: + + +Next, the aligned width parameter for each LOD “L” is computed. The “i” parameter is the horizontal +alignment parameter set by a state field or defined as a constant, depending on the surface. The + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 106 + alignment parameter may change at one point in the mip chain based on Mip Tail Start LOD. The +equation uses the I value that applies to the LOD being computed. + + + + +Based on the above parameters and the U and R (pixel address and array index, respectively), and the +bytes per pixel of the surface format (Bpp), the offset “u” in bytes from the base address of the surface is +given by: +u = [(R * QPitch) + LODUL + U] * Bpp + + +6.18.4 2D Surfaces +Surfaces that comprise texture mip-maps are stored in a fixed “monolithic” format and referenced by a +single base address. The base map and associated mipmaps are located within a single rectangular area +of memory identified by the base address of the upper left corner and a pitch. The base address +references the upper left corner of the base map. The pitch must be specified at least as large as the +widest mip-map. In some cases it must be wider; see the section on Minimum Pitch below. +These surfaces may be overlapped in memory and must adhere to the following memory organization +rules: + +  For non-compressed texture formats, each mipmap must start on an even row within the monolithic + rectangular area. For 1-texel-high mipmaps, this may require a row of padding below the previous + mipmap. This restriction does not apply to any compressed texture formats; each subsequent + (lower-res) compressed mipmap is positioned directly below the previous mipmap. +  Vertical alignment restrictions vary with memory tiling type: 1 DWord for linear, 16-byte (DQWord) for + tiled. (Note that tiled mipmaps are not required to start at the left edge of a tile row.) + +6.18.4.1 Computing MIP level sizes +Map width and height specify the size of the largest MIP level (LOD 0). Less detailed LOD level (i+1) +sizes are determined by dividing the width and height of the current (i) LOD level by 2 and truncating to +an integer (floor). This is equivalent to shifting the width/height by 1 bit to the right and discarding the bit +shifted off. The map height and width are clamped on the low side at 1. +In equations, the width and height of an LOD “L” can be expressed as: +WL = ((width >> L) > 0? width >> L:1) +HL = ((height >> L) > 0? height >> L:1) + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 107 + If the surface is multisampled and it is a depth or stencil surface or Multisampled Surface +StorageFormat in SURFACE_STATE is MSFMT_DEPTH_STENCIL, W L and HL must be adjusted as +follows before proceeding: + Number of Multisamples WL = HL = + 2 + ceiling(W L / 2) * 4 HL [no adjustment] + 4 + ceiling(W L / 2) * 4 ceiling(HL / 2) * 4 + + 8 + ceiling(W L / 2) * 8 ceiling(HL / 2) * 4d + 16 + ceiling(W L / 2) * 8 ceiling(HL / 2) * 8 + + +6.18.4.2 Base Address for LOD Calculation +It is conceptually easier to think of the space that the map uses in Cartesian space (x, y), where x and y +are in units of texels, with the upper left corner of the base map at (0, 0). The final step is to convert from +Cartesian coordinates to linear addresses as documented at the bottom of this section. +It is useful to think of the concept of “stepping” when considering where the next MIP level will be stored +in rectangular memory space. We either step down or step right when moving to the next higher LOD. + +  for MIPLAYOUT_RIGHT maps: + o step right when moving from LOD 0 to LOD 1 + o step down for all of the other MIPs + +  for MIPLAYOUT_BELOW maps: + o step down when moving from LOD 0 to LOD 1 + o step right when moving from LOD 1 to LOD 2 + o step down for all of the other MIPs + +To account for the cache line alignment required, we define i and j as the width and height, respectively, +of an alignment unit. This alignment unit is defined below. We then define lower-case wL and hL as the +padded width and height of LOD “L” as follows: + + + + +For separate stencil buffer, the width must be mutiplied by 2 and height divided by 2 as follows: + + + + +Equations to compute the upper left corner of each MIP level are then as follows: + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 108 + for MIPLAYOUT_RIGHT maps: + +LOD0 = (0,0) + +LOD1 = (w0,0 ) + +LOD2 = (w0,h1) + +LOD3 = (w0,h1 + h2) + +LOD4 = (w0,h1 + h2 + h3) +... +for MIPLAYOUT_BELOW maps: + +LOD0 = (0,0) + +LOD1 = (0,h0) + +LOD2 = (w1,h0) + +LOD3 = (w1,h0 + h2) + +LOD4 = (w1,h0 + h2 + h3) +... + + + + +6.18.4.3 Minimum Pitch for MIPLAYOUT_RIGHT and Other Maps +For MIPLAYOUT_RIGHT maps, the minimum pitch must be calculated before choosing a fence to place +the map within. This is approximately equal to 1.5x the pitch required by the base map, with possible + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 109 + adjustments made for cache line alignment. For MIPLAYOUT_BELOW and MIPLAYOUT_LEGACY +maps, the minimum pitch required is equal to that required by the base (LOD 0) map. +A safe but simple calculation of minimum pitch is equal to 2x the pitch required by the base map for +MIPLAYOUT_RIGHT maps. This ensures that enough pitch is available, and since it is restricted to +MIPLAYOUT_RIGHT maps, not much memory is wasted. It is up to the driver (hardware independent) +whether to use this simple determination of pitch or a more complex one. + +6.18.4.4 Alignment Unit Size +This section documents the alignment parameters i and j that are used depending on the surface. + + alignment unit width “i” alignment unit height “j” + surface defined by surface format +3DSTATE_DEPTH_BUFFER D16_UNORM 8 4 + not 4 4 + D16_UNORM +3DSTATE_STENCIL_BUFFER N/A 8 8 +SURFACE_STATE BC*, ETC*, 4 4 + EAC* + FXT1 8 4 + all others + set by Surface Horizontal set by Surface Vertical + Alignment Alignment + + + +6.18.4.5 Cartesian to Linear Address Conversion +A set of variables are defined in addition to the i and j defined above. + +  b = bytes per texel of the native map format (0.5 for DXT1, FXT1, and 4-bit surface format, 2.0 for + YUV 4:2:2, others aligned to surface format) +  t = texel rows / memory row (4 for DXT1-5 and FXT1, 1 for all other formats) +  p = pitch in bytes (equal to pitch in dwords * 4) +  B = base address in bytes (address of texel 0,0 of the base map) +  x, y = cartestian coordinates from the above calculations in units of texels (assumed that x is always + a multiple of i and y is a multiple of j) +  A = linear address in bytes + + + + +This calculation gives the linear address in bytes for a given MIP level (taking into account L1 cache line +alignment requirements). + +6.18.4.6 Compressed Mipmap Layout +Mipmaps of textures using compressed (DXTn, FXT) texel formats are also stored in a monolithic format. +The compressed mipmaps are stored in a similar fashion to uncompressed mipmaps, with each block of +source (uncompressed) texels represented by a 1 or 2 QWord compressed block. The compressed +blocks occupy the same logical positions as the texels they represent, where each row of compressed + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 110 + blocks represent a 4-high row of uncompressed texels. The format of the blocks is preserved, i.e., there is +no “intermediate” format as required on some other devices. +The following exceptions apply to the layout of compressed (vs. uncompressed) mipmaps: + +  Mipmaps are not required to start on even rows, therefore each successive mip level is located on + the texel row immediately below the last row of the previous mip level. Pad rows are neither required + nor allowed. +  The dimensions of the mip maps are first determined by applying the sizing algorithm presented in + Non-Power-of-Two Mipmaps above. Then, if necessary, they are padded out to compression block + boundaries. + +6.18.4.7 Surface Arrays + +6.18.4.7.1 For all surface other than separate stencil buffer +Both 1D and 2D surfaces can be specified as an array. The only difference in the surface state is the +presence of a depth value greater than one, indicating multiple array “slices”. +A value QPitch is defined which indicates the worst-case height for one slice in the texture array. This +QPitch is multiplied by the array index to and added to the vertical component of the address to determine +the vertical component of the address for that slice. Within the slice, the map is stored identically to a +MIPLAYOUT_BELOW 2D surface. MIPLAYOUT_BELOW is the only format supported by 1D non-arrays +and both 2D and 1D arrays, the programming of the MIP Map Layout Mode state variable is ignored when +using a TextureArray. +The following equation is used for surface formats other than compressed textures: +QPitch = (h0 + h1 + 11j) + + +The input variables in this equation are defined in sections above. +The equation for compressed textures (BC* and FXT1 surface formats) follows: + + + + +6.18.4.7.2 For all surfaces +A value QPitch is defined which indicates the worst-case height for one slice in the texture array. This +QPitch is multiplied by the array index to and added to the vertical component of the address to determine +the vertical component of the address for that slice. Within the slice, the map is stored identically to a 2D +surface. +The Surface Array Spacing field in SURFACE_STATE has two possible values, which affect the QPitch +formula. +If Surface Array Spacing is set to ARYSPC_FULL (note that the depth buffer and stencil buffer have an +implied value of ARYSPC_FULL): + + +QPitch = (h0 + 1h + 12j) + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 111 + Note that h0 and h1 have been halved as described earlier. + + +If Surface Array Spacing is set to ARYSPC_LOD0: + + +QPitch = h0 + + + + +6.18.4.8 Multisampled Surfaces +Starting with, multisampled render targets and sampling engine surfaces are supported. There are three +types of multisampled surface layouts designated as follows: + +  IMS Interleaved Multisampled Surface +  CMS Compressed Mulitsampled Surface +  UMS Uncompressed Multisampled Surface + +These surface layouts are described in the following sections. + +6.18.4.8.1 Interleaved Multisampled Surfaces +IMS surfaces are the only type supported on, and are supported on all products for depth and stencil +surfaces. These surfaces contain the samples in an interleaved fashion, with the underlying surface in +memory having a height and width that is larger than the non-multisampled surface as follows: +4x MSAA: 2x width and 2x height of non-multisampled surface +8x MSAA: 4x width and 2x height of non-multisampled surface + + +6.18.5 Cube Surfaces +The 3D Pipeline supports cubic environment maps, conceptually arranged as a cube surrounding the +origin of a 3D coordinate system aligned to the cube faces. These maps can be used to supply texel +(color/alpha) data of the environment in any direction from the enclosed origin, where the direction is +supplied as a 3D “vector” texture coordinate. These cube maps can also be mipmapped. +Each texture map level is represented as a group of six, square cube face texture surfaces. The faces are +identified by their relationship to the 3D texture coordinate system. The subsections below describe the +cube maps as described at the API as well as the memory layout dictated by the hardware. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 112 + 6.18.5.1 DirectX API Definition +The diagram below describes the cube map faces as they are defined at the DirectX API. It shows the +axes on the faces as they would be seen from the inside (at the origin). The origin of the U,V texel grid is +at the top left corner of each face. +This will be looking directly at face 4, the +z -face. Y is up by default. + +DirectX Cube Map Definition + + + + +6.18.5.2 Hardware Cube Map Layout +The cube face textures are stored in the same way as 2D array surfaces are stored (see section 2D +Surfaces for details). For cube surfaces, the depth (array instances) is equal to 6. The array index “q” +corresponds to the face according to the following table: + + “q” coordinate face + 0 +x + 1 -x + 2 +y + 3 -y + 4 +z + 5 -z + + +6.18.5.3 Restrictions +  The cube map memory layout is the same whether or not the cube map is mip-mapped, and whether + or not all six faces are “enabled”, though the memory backing disabled faces or non-supplied levels + can be used by software for other purposes. +  The cube map faces all share the same Surface Format + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 113 + 6.18.5.4 Cube Arrays +Cube arrays are stored identically to 2D surface arrays. A group of 6 consecutive array elements makes +up a single cube map. A cube array with N array elements is stored identically to a 2D array with 6N array +elements. + + +6.18.6 3D Surfaces +Multiple texture map surfaces (and their respective mipmap chains) can be arranged into a structure +known as a Texture3D (volume) texture. A volume texture map consists of many planes of 2D texture +maps. See Sampler for a description of how volume textures are used. + +Volume Texture Map + + + + +Note that the number of planes defined at each successive mip level is halved. Volumetric texture maps +are stored as follows. All of the LOD=0 q-planes are stacked vertically, then below that, the LOD=1 q- +planes are stacked two-wide, then the LOD=2 q-planes are stacked four-wide below that, and so on. +The width, height, and depth of LOD “L” are as follows: +WL = ((width >> L) > 0? width >> L:1) +HL = ((height >> L) > 0? height >> L:1) +This is the same as for a regular texture. For volume textures we add: +DL = ((depth >> L) > 0? depth >> L:1) +Cache-line aligned width and height are as follows, with i and j being a function of the map format as +shown in the table entitled 7.19.4.4, Alignment Unit Size. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 114 + Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 115 + Note that it is not necessary to cache-line align in the “depth” dimension (i.e. lowercase “d”). +The following equations for LODL,q give the base address Cartesian coordinates for the map at LOD L and +depth q. + + + + +These values are then used as “base addresses” and the 2D MIP Map equations are used to compute +the location within each LOD/q map. + +6.18.6.1 Minimum Pitch +The minimum pitch required to store the 3D map may in some cases be greater than the minimum pitch +required by the LOD=0 map. This is due to cache line alignment requirements that may impact some of +the MIP levels requiring additional spacing in the horizontal direction. + + +6.19 Surface Padding Requirements + +6.19.1 Sampling Engine Surfaces +The sampling engine accesses texels outside of the surface if they are contained in the same cache line +as texels that are within the surface. These texels will not participate in any calculation performed by the +sampling engine and will not affect the result of any sampling engine operation, however if these texels lie +outside of defined pages in the GTT, a GTT error will result when the cache line is accessed. In order to +avoid these GTT errors, “padding” at the bottom and right side of a sampling engine surface is sometimes +necessary. +It is possible that a cache line will straddle a page boundary if the base address or pitch is not aligned. All +pages included in the cache lines that are part of the surface must map to valid GTT entries to avoid +errors. To determine the necessary padding on the bottom and right side of the surface, refer to the table +in Section Alignment Unit Size for the i and j parameters for the surface format in use. The surface must +then be extended to the next multiple of the alignment unit size in each dimension, and all texels +contained in this extended surface must have valid GTT entries. +For example, suppose the surface size is 15 texels by 10 texels and the alignment parameters are i=4 +and j=2. In this case, the extended surface would be 16 by 10. Note that these calculations are done in +texels, and must be converted to bytes based on the surface format being used to determine whether +additional pages need to be defined. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 116 + For buffers, which have no inherent “height,” padding requirements are different. A buffer must be padded +to the next multiple of 256 array elements, with an additional 16 bytes added beyond that to account for +the L1 cache line. +For cube surfaces, an additional two rows of padding are required at the bottom of the surface. This must +be ensured regardless of whether the surface is stored tiled or linear. This is due to the potential rotation +of cache line orientation from memory to cache. +For compressed textures (BC* and FXT1 surface formats), padding at the bottom of the surface is to an +even compressed row, which is equal to a multiple of 8 uncompressed texel rows. Thus, for padding +purposes, these surfaces behave as if j = 8 only for surface padding purposes. The value of 4 for j still +applies for mip level alignment and QPitch calculation. +For YUV, 96 bpt, and 48 bpt surface formats, additional padding is required. These surfaces require an +extra row plus 16 bytes of padding at the bottom in addition to the general padding requirements. + + +6.19.2 Render Target and Media Surfaces +The data port accesses data (pixels) outside of the surface if they are contained in the same cache +request as pixels that are within the surface. These pixels will not be returned by the requesting message, +however if these pixels lie outside of defined pages in the GTT, a GTT error will result when the cache +request is processed. In order to avoid these GTT errors, “padding” at the bottom of the surface is +sometimes necessary. +If the surface contains an odd number of rows of data, a final row below the surface must be allocated. If +the surface will be accessed in field mode (Vertical Stride = 1), enough additional rows below the surface +must be allocated to make the extended surface height (including the padding) a multiple of 4. + + +6.20 BSD Logical Context Data (MFX) + +6.20.1 Register/State Context + Valid Only When PPGTT + Enabled + +DW DW State Field Restore PPGTTEnabled PPGTT Disabled Power Set Before +Range Count Inhibite s Context Submittin + d g + Context? + + 00h 1 R S/R X S/R Yes + Context Control + 01h 1 R S/R X S/R Yes + Ring Head Pointer Register + 02h 1 R R X S/R Yes + Ring Tail Pointer Register + 03h 1 NR S/R X S/R No + Batch Buffer Current Head + Register + + 04h 1 NR S/R X S/R No + Batch Buffer State Register + 05h 1 R R X S/R Yes + PPGTT Directory Cache Valid + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 117 + Valid Only When PPGTT + Enabled + Register + (Software always populates via + host) + 06h 1 X X X S/R X + Reserved + + 07h 1 R R X S/R Yes + PD Base Virtual Address + Register + 08h 1 NR S/R X S/R Yes + MFX_STATE_POINTER 0 + 09h 1 NR S/R X S/R Yes + MFX_STATE_POINTER 1 + 0Ah 1 NR S/R X S/R Yes + MFX_STATE_POINTER 2 + + 0Bh 1 NR S/R X S/R Yes + MFX_STATE_POINTER 3 + 0Ch 1 NR S/R X S/R No + VCS_CNTR— Media + Watchdog Counter Control + 0Dh 1 NR S/R X S/R No + VCS_THRSH— Media + Watchdog Counter Threshold + 0Eh 1 NR S/R X S/R No + Current Context ID Register + + 0Fh 1 X X X S/R X + Reserved + + + +6.20.2 The Per-Process Hardware Status Page +The following table defines the layout of the Per-process Hardware Status Page: + DWord Offset Description + (3FFh – 020h) These locations can be used for general purpose via + the MI_STORE_DATA_INDEX or + MI_STORE_DATA_IMM instructions. + 1F:5 + Reserved. + + 4 + Ring Head Pointer Storage: The contents of the + Ring Buffer Head Pointer register (register DWord 1) + are written to this location either as result of an + MI_REPORT_HEAD instruction or as the result of an + “automatic report” (see RINGBUF registers). + + 3:0 + Reserved. + +This page is designed to be read by SW in order to glean additional details about a context beyond what +it can get from the context status. +Accesses to this page will automatically be treated as cacheable and snooped. It is therefore illegal to +locate this page in any region where snooping is illegal (such as in stolen memory). + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 118 + 6.21 Copy Engine Logical Context Data + +6.21.1 Register/State Context + Valid Only When + PPGTT Enabled + +DW DW State Field Render PPGTTEnabled PPGTT Power Set Before +Range Count Restore Disabled Context Submittin + Inhibite g + d Context? + + 00h 1 NR X X X X + Reserved + 01h 1 R S/R X S/R Yes + Ring Head + Pointer Register + 02h 1 R R X S/R Yes + Ring Tail Pointer + Register + 03h 1 NR X X X X + Reserved + + 04h 1 NR X X X X + Reserved + 05h 1 R R X X Yes + PPGTT Directory + Cache Valid + Register + (Software always + populates via + host) + 06h 1 NR S/R X S/R Yes + BCS_SWCTRL + Register + 07h 1 R R X X Yes + PD Base Virtual + Address Register + + 08h 1 NR X X X X + Reserved + 09h 1 NR X X X X + Reserved + 0Ah 1 NR X X X X + Reserved + 0Bh 1 NR X X X X + Reserved + + 0Ch 1 NR X X X X + Reserved + 0Dh 1 NR X X X X + Reserved + 0Eh 1 NR X X X X + Reserved + 0Fh 1 NR X X X X + Reserved + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 119 + 6.21.2 The Per-Process Hardware Status Page +The following table defines the layout of the Per-process Hardware Status Page: + DWord Offset Description + (3FFh – 020h) These locations can be used for general purpose via + the MI_STORE_DATA_INDEX or + MI_STORE_DATA_IMM instructions. + 1F:5 + Reserved. + + 4 + Ring Head Pointer Storage: The contents of the + Ring Buffer Head Pointer register (register DWord 1) + are written to this location either as result of an + MI_REPORT_HEAD instruction or as the result of an + “automatic report” (see RINGBUF registers). + 3:0 + Reserved. + +This page is designed to be read by SW in order to glean additional details about a context beyond what +it can get from the context status. +Accesses to this page will automatically be treated as cacheable and snooped. It is therefore illegal to +locate this page in any region where snooping is illegal (such as in stolen memory). + + +6.22 Render Logical Context Data +Logical Contexts are memory images used to store copies of the device’s rendering and ring context. +Logical Contexts are aligned to 256-byte boundaries. +Logical contexts are referenced by their memory address. The format and contents of rendering contexts +are considered device-dependent and software must not access the memory contents directly. The +definition of the logical rendering and power context memory formats is included here primarily for internal +documentation purposes. + + +6.22.1 Overall Context Layout + +6.22.1.1 Register/State Context +POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + +Description # of DW + +NOOP CS + 1 +Load_Register_Immediate header 0x1100_105D CS + 1 +RING_BUFFER_START 0x2038 CS + 2 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 120 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + +Description # of DW + +RING_BUFFER_CONTROL 0x203C CS + 2 +RVSYNC 0x2040 CS + 2 + +RBSYNC 0x2044 CS + 2 +RC_PWRCTX_MAXCNT 0x2054 CS + 2 +CTX_WA_PTR 0x2058 CS + 2 +NOPID 0x2094 CS + 2 + +HWSTAM 0x2098 CS + 2 +FF_THREAD_MODE 0x20A0 CS + 2 +IMR 0x20A8 CS + 2 +EIR 0x20B0 CS + 2 + +EMR 0x20B4 CS + 2 +CMD_CCTL_0 0x20C4 CS + 2 +GAFS_Mode 0x212C CS + 2 +UHPTR 0x2134 CS + 2 + +BB_PREEMPT_ADDR 0x2148 CS + 2 +RING_BUFFER_HEAD_PREEMPT_REG 0x214C CS + 2 +CXT_SIZE 0x21A8 CS + 2 +CXT_OFFSET 0x21AC CS + 2 + +CXT_PIPESTATEBASE 0x21B0 CS + 2 +PREEMPT_DLY 0x2214 CS + 2 +GFX_MODE 0x229C CS + 2 +MTCH_CID_RST 0x222C CS + 2 +SYNC_FLIP_STATUS 0x22D0 CS + 2 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 121 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + + Description # of DW + +SYNC_FLIP_STATUS_1 0x22D4 CS + 2 +NOOP CS + 12 + +NOOP GPM + 1 +Load_Register_Immediate header 0x1100_10d5 GPM + 1 +GPM Data(Inc GAM) GPM + 214 +NOOP GPM + 1 + +Load_Register_Immediate header 0x1100_104b GPM + 1 +MBCunit GPM + 76 +NOOP GPM + 1 +Load_Register_Immediate header 0x1100_1013 GPM + 1 + +GCPunit GPM + 20 +NOOP GPM + 1 +Load_Register_Immediate header 0x1100_103f GPM + 1 +GDTunit GPM + 64 + +NOOP GPM + 1 +Load_Register_Immediate header 0x1100_1035 GPM + 1 +GAMunit GPM + 52 +NOOP GPM + 28 + +NOOP CS + 1 +Load_Register_Immediate header 0x1100_1017 CS + 1 +Context Control 0x2244 CS + 2 +Ring Head Pointer Register 0x2034 CS + 2 +Ring Tail Pointer Register 0x2030 CS + 2 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 122 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + +Description # of DW + +Batch Buffer Current Head Register 0x2140 CS + 2 +Batch Buffer State Register 0x2110 CS + 2 + +PPGTT Directory Cache Valid Register 0x2220 CS + 2 +PP_DIR_BASE 0x2228 CS + 2 +Read Offset in Piipelined State Page (8 CL aligned) 0x224C CS + 2 +Committed Vertex Number 0x21C4 CS + 2 + +Committed Instance ID 0x21C8 CS + 2 +Committed Primitive ID 0x21CC CS + 2 +CCID Register 0x2180 CS + 2 +NOOP CS + 6 + +NOOP CS + 1 +Load_Register_Immediate header 0x1100_105F CS + 1 +EXCC 0x2028 CS + 2 +MI_MODE 0x209C CS + 2 + +INSTPM 0x20C0 CS + 2 +PR_CTR_CTL 0x2178 CS + 2 +PR_CTR_THRSH 0x217C CS + 2 +IA_VERTICES_COUNT 0x2310 CS + 4 + +IA_PRIMITIVES_COUNT 0x2318 CS + 4 +VS_INVOCATION_COUNT 0x2320 CS + 4 +HS_INVOCATION_COUNT 0x2300 CS + 4 +DS_INVOCATION_COUNT 0x2308 CS + 4 +GS_INVOCATION_COUNT 0x2328 CS + 4 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 123 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + +Description # of DW + +GS_PRIMITIVES_COUNT 0x2330 CS + 4 +CL_INVOCATION_COUNT 0x2338 CS + 4 + +CL_PRIMITIVES_COUNT 0x2340 CS + 4 +PS_INVOCATION_COUNT 0x2348 CS + 4 +PS_DEPTH_COUNT 0x2350 CS + 4 +VFSKPD 0x2470 CS + 2 + +TIMESTAMP Register (LSB) 0x2358 CS + 2 +GPUGPU_DISPATCHDIMX 0x2500 CS + 2 +GPUGPU_DISPATCHDIMY 0x2504 CS + 2 +GPUGPU_DISPATCHDIMZ 0x2508 CS + 2 + +MI_PREDICATE_SRC0 0x2400 CS + 2 +MI_PREDICATE_SRC0 0x2404 CS + 2 +MI_PREDICATE_SRC1 0x2408 CS + 2 +MI_PREDICATE_SRC1 0x240C CS + 2 + +MI_PREDICATE_DATA 0x2410 CS + 2 +MI_PREDICATE_DATA 0x2414 CS + 2 +MI_PRED_RESULT 0x2418 CS + 2 +3DPRIM_END_OFFSET 0x2420 CS + 2 + +3DPRIM_START_VERTEX 0x2430 CS + 2 +3DPRIM_VERTEX_COUNT 0x2434 CS + 2 +3DPRIM_INSTANCE_COUNT 0x2438 CS + 2 +3DPRIM_START_INSTANCE 0x243C CS + 2 +3DPRIM_BASE_VERTEX 0x2440 CS + 2 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 124 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + +Description # of DW + +GPGPU_THREADS_DISPATCHED 0x2290 CS + 4 +MI_TOPOLOGY_FILTER CS + 1 + +MI_URB_CLEAR CS + 2 +MI_SET_APPID CS + 1 +PIPELINE_SELECT CS + 1 +STATE_BASE_ADDRESS CS + 10 + +3DSTATE_PUSH_CONSTANT_ALLOC_VS CS + 2 +3DSTATE_PUSH_CONSTANT_ALLOC_HS CS + 2 +3DSTATE_PUSH_CONSTANT_ALLOC_DS CS + 2 +3DSTATE_PUSH_CONSTANT_ALLOC_GS CS + 2 + +3DSTATE_PUSH_CONSTANT_ALLOC_PS CS + 2 +NOOP CS + 5 +NOOP SARB + 1 +Load_Register_Immediate header 0x1100_105B SARB + 1 + +SARB Error Status 0xB004 SARB + 2 +L3CD Error Status register 1 0xB008 SARB + 2 +L3CD Error Status register 2 0xB00C SARB + 2 +L3 SQC registers 1 0xB010 SARB + 2 + +L3 SQC registers 2 0xB014 SARB + 2 +L3 SQC registers 3 0xB018 SARB + 2 +L3 Control Register1 0xB01C SARB + 2 +L3 Control Register2 0xB020 SARB + 2 +L3 Control Register3 0xB024 SARB + 2 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 125 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + + Description # of DW + +L3 SLM Register 0xB028 SARB + 2 +Arbiter Control Register 0xB02C SARB + 2 + +L3 bank0 reg0 log error 0xB070 SARB + 2 +L3 bank0 reg1 log error 0xB074 SARB + 2 +L3 bank0 reg2 log error 0xB078 SARB + 2 +L3 bank0 reg3 log error 0xB07C SARB + 2 + +L3 bank0 reg4 log error 0xB080 SARB + 2 +L3 bank0 reg5 log error 0xB084 SARB + 2 +L3 bank0 reg6 log error 0xB088 SARB + 2 +L3 bank0 reg7 log error 0xB08C SARB + 2 + +L3 bank1 reg0 log error 0xB090 SARB + 2 +L3 bank1 reg1 log error 0xB094 SARB + 2 +L3 bank1 reg2 log error 0xB098 SARB + 2 +L3 bank1 reg3 log error 0xB09C SARB + 2 + +L3 bank1 reg4 log error 0xB0A0 SARB + 2 +L3 bank1 reg5 log error 0xB0A4 SARB + 2 +L3 bank1 reg6 log error 0xB0A8 SARB + 2 +L3 bank1 reg7 log error 0xB0AC SARB + 2 + +L3 bank2 reg0 log error 0xB0B0 SARB + 2 +L3 bank2 reg1 log error 0xB0B4 SARB + 2 +L3 bank2 reg2 log error 0xB0B8 SARB + 2 +L3 bank2 reg3 log error 0xB0BC SARB + 2 +L3 bank2 reg4 log error 0xB0C0 SARB + 2 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 126 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + +Description # of DW + +L3 bank2 reg5 log error 0xB0C4 SARB + 2 +L3 bank2 reg6 log error 0xB0C8 SARB + 2 + +L3 bank2 reg7 log error 0xB0CC SARB + 2 +L3 bank3 reg0 log error 0xB0D0 SARB + 2 +L3 bank3 reg1 log error 0xB0D4 SARB + 2 +L3 bank3 reg2 log error 0xB0D8 SARB + 2 + +L3 bank3 reg3 log error 0xB0DC SARB + 2 +L3 bank3 reg4 log error 0xB0E0 SARB + 2 +L3 bank3 reg5 log error 0xB0E4 SARB + 2 +L3 bank3 reg6 log error 0xB0E8 SARB + 2 + +L3 bank3 reg7 log error 0xB0EC SARB + 2 +L3 SQC register 4 0xB034 SARB + 2 +3DSTATE_VS SVG + 6 +3DSTATE_BINDING_TABLE_POINTERS_VS SVG + 2 + +3DSTATE_SAMPLER_STATE_POINTERS_VS SVG + 2 +3DSTATE_CONSTANT_VS SVG + 7 +3DSTATE_URB_VS SVG + 2 +3DSTATE_HS SVG + 7 + +3DSTATE_BINDING_TABLE_POINTERS_HS SVG + 2 +3DSTATE_SAMPLER_STATE_POINTERS_HS SVG + 2 +3DSTATE_CONSTANT_HS SVG + 7 +3DSTATE_URB_HS SVG + 2 +3DSTATE_TE SVG + 4 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 127 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + +Description # of DW + +3DSTATE_DS SVG + 6 +3DSTATE_BINDING_TABLE_POINTERS_DS SVG + 2 + +3DSTATE_SAMPLER_STATE_POINTERS_DS SVG + 2 +3DSTATE_CONSTANT_DS SVG + 7 +3DSTATE_URB_DS SVG + 2 +3DSTATE_GS SVG + 7 + +3DSTATE_BINDING_TABLE_POINTERS_GS SVG + 2 +3DSTATE_SAMPLER_STATE_POINTERS_GS SVG + 2 +3DSTATE_CONSTANT_GS SVG + 7 +3DSTATE_URB_GS SVG + 2 + +3DSTATE_STREAMOUT SVG + 3 +3DSTATE_CLIP SVG + 4 +3DSTATE_VIEWPORT_STATE_POINTERS_CL_SF SVG + 2 +3DSTATE_SF SVG + 7 + +3DSTATE_SCISSOR_STATE_POINTERS SVG + 2 +3DSTATE_MULTISAMPLE SVG + 4 +3DSTATE_DRAWING_RECTANGLE SVG + 4 +SWTESS_BASE_ADDRESS SVG + 2 + +NOOP SVG + 2 +3DSTATE_WM SVL + 3 +3DSTATE_VIEWPORT_STATE_POINTERS_CC SVL + 2 +3DSTATE_CC_STATE_POINTERS SVL + 2 +3DSTATE_DEPTHSTENCIL_STATE_POINTERS SVL + 2 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 128 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + +Description # of DW + +3DSTATE_SAMPLE_MASK SVL + 2 +3DSTATE_SBE SVL + 14 + +3DSTATE_CONSTANT_PS SVL + 7 +3DSTATE_PS SVL + 8 +3DSTATE_BINDING_TABLE_POINTERS_PS SVL + 2 +3DSTATE_SAMPLER_STATE_POINTERS_PS SVL + 2 + +3DSTATE_BLEND_STATE_POINTERS SVL + 2 +Load_Register_Immediate header 0x1100_100B SVL + 1 +Cache_Mode_0 0x7000 SVL + 2 +Cache_Mode_1 0x7004 SVL + 2 + +GT_MODE 0x7008 SVL + 2 +FBC_RT_BASE_ADDR_REGISTER 0x7020 SVL + 2 +STATE_SIP SVL + 2 +3DSTATE_DEPTH_BUFFER SVL + 7 + +3DSTATE_STENCIL_BUFFER SVL + 3 +3DSTATE_HIER_DEPTH_BUFFER SVL + 3 +3DSTATE_CLEAR_PARAMS SVL + 3 +NOOP SVL + 3 + +NOOP TDL0 + 1 +Load_Register_Immediate header 0x1100_1011 TDL0 + 1 +TD_CTL2 0xE404 TDL0 + 2 +TD_VF_VS_EMSK 0xE408 TDL0 + 2 +TD_GS_EMSK 0xE40C TDL0 + 2 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 129 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + +Description # of DW + +TD_WIZ_EMSK 0xE410 TDL0 + 2 +TD_TS_EMSK 0xE428 TDL0 + 2 + +TD_HS_EMSK 0xE4B0 TDL0 + 2 +TD_DS_EMSK 0xE4B4 TDL0 + 2 +NOOP TDL0 + 12 +NOOP TDL1 + 1 + +Load_Register_Immediate header 0x1100_1011 TDL1 + 1 +TD_CTL2 0xF404 TDL1 + 2 +TD_VF_VS_EMSK 0xF408 TDL1 + 2 +TD_GS_EMSK 0xF40C TDL1 + 2 + +TD_WIZ_EMSK 0xF410 TDL1 + 2 +TD_TS_EMSK 0xF428 TDL1 + 2 +TD_HS_EMSK 0xF4B0 TDL1 + 2 +TD_DS_EMSK 0xF4B4 TDL1 + 2 + +NOOP TDL1 + 12 +NOOP WM + 1 +Load_Register_Immediate header 0x1100_1003 WM + 1 +SuperSpan Count 0x5520 WM + 2 + +3DSTATE_POLY_STIPPLE_PATTERN WM + 33 +3DSTATE_AA_LINE_PARAMS WM + 3 +3DSTATE_POLY_STIPPLE_OFFSET WM + 2 +3DSTATE_LINE_STIPPLE WM + 3 +NOOP WM + 1 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 130 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + +Description # of DW + +NOOP SC0 + 1 +Load_Register_Immediate header 0x1100_1003 SC0 + 1 + +NOOP SC0 + 10 +NOOP SC1 + 1 +Load_Register_Immediate header 0x1100_1003 SC1 + 1 +NOOP SC1 + 10 + +3DSTATE_MONOFILTER_SIZE SC0/1 + 2 +3DSTATE_CHROMA_KEY SC0/1 + 16 +NOOP SC0/1 + 6 +MEDIA_VFE_STATE VFE + 8 + +MEDIA_CURBE_LOAD VFE + 4 +MEDIA_INTERFACE_DESCRIPTOR_LOAD VFE + 4 +MEDIA_OBJECT_PRT/GPGPU_WALKER VFE + 16 +MEDIA_STATE_FLUSH VFE + 2 + +NOOP VFE + 6 +3DSTATE_SAMPLER_PALETTE_LOAD0 DM0/1 + 257 +3DSTATE_SAMPLER_PALETTE_LOAD1 DM0/1 + 257 +NOOP DM0/1 + 14 + +NOOP SOL + 1 +Load_Register_Immediate header 0x1100_1027 SOL + 1 +SO_NUM_PRIMS_WRITTEN0 0x5200 SOL + 4 +SO_NUM_PRIMS_WRITTEN1 0x5208 SOL + 4 +SO_NUM_PRIMS_WRITTEN2 0x5210 SOL + 4 + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 131 + POWER CONTEXT + +MAIN CONTEXT +EXTENDED CONTEXT + + +Description # of DW + +SO_NUM_PRIMS_WRITTEN3 0x5218 SOL + 4 +SO_PRIM_STORAGE_NEEDED0 0x5240 SOL + 4 + +SO_PRIM_STORAGE_NEEDED1 0x5248 SOL + 4 +SO_PRIM_STORAGE_NEEDED2 0x5250 SOL + 4 +SO_PRIM_STORAGE_NEEDED3 0x5258 SOL + 4 +SO_WRITE_OFFSET0 0x5280 SOL + 2 + +SO_WRITE_OFFSET1 0x5284 SOL + 2 +SO_WRITE_OFFSET2 0x5288 SOL + 2 +SO_WRITE_OFFSET3 0x528C SOL + 2 +3DSTATE_SO_BUFFER SOL + 16 + +NOOP SOL + 3 +3DSTATE_SO_DECL_LIST SOL + 259 +3DSTATE_INDEX_BUFFER VF + 3 +3DSTATE_VERTEX_BUFFERS VF + 133 + +3DSTATE_VERTEX_ELEMENTS VF + 69 +3DSTATE_VF_STATISTICS VF + 1 +NOOP VF + 2 + + + +6.22.2 Pipelined State Page +This page is used a scratch area for the pipeline to store pipelined state that is not referenced indirectly. +Under no circumstances should SW read from or write to this page. + + +6.22.3 Ring Buffer +This page is used a scratch area for the pipeline to store ring buffer commands that need to be reissued. +Under no circumstances should SW read from or write to this page. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 132 + 6.22.4 The Per-Process Hardware Status Page +The following table defines the layout of the Per-process Hardware Status Page: +DWord + Offset Description +(3FFh – These locations can be used for general purpose via the MI_STORE_DATA_INDEX or + 020h) MI_STORE_DATA_IMM instructions. + 1F:1C Reserved. + + 1B Context Save Finished Timestamp + + 1A + Context Restore Complete Timestamp + + 19 + Pre-empt Request Received Timestamp + + 18 + Last Switch Timestamp + + 17:12 Reserved. + + F:5 + Reserved. + + 4 + Ring Head Pointer Storage: The contents of the Ring Buffer Head Pointer register (register DWord 1) + are written to this location either as result of an MI_REPORT_HEAD instruction or as the result of an + “automatic report” (see RINGBUF registers). + 3:0 + Reserved. + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 6/21/2012 133 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V1 Pt 1 – 05 12 5/29/2012 134 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol1_part2.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part2.txt new file mode 100644 index 0000000..0d0ca6a --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part2.txt @@ -0,0 +1,2349 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 1 Part 2: Graphics Core™ – MMIO, Media +Registers, and Programming Environment +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S +TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY +WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO +SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO +FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY +PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. + +A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly +or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + Contents + +1. Introduction............................................................................................................................................ 5 +2. Virtual Memory ...................................................................................................................................... 6 + 2.1 Global Virtual Memory.......................................................................................................................... 6 + 2.1.1 Graphics Translation Table (GTT) Range (GTTADR) .................................................................... 6 + 2.1.2 GTT Page Table Entries (PTEs)..................................................................................................... 6 + 2.2 Two-Level Per-Process Virtual Memory .............................................................................................. 8 + 2.2.1 PPGTT Directory Entries (PDEs) ................................................................................................. 10 + 2.2.2 PPGTT Table Entries (PTEs) ....................................................................................................... 10 +3. GFX MMIO – MCHBAR Aperture ........................................................................................................ 12 +4. Graphics Memory Interface Functions .............................................................................................. 13 + 4.1 Introduction ........................................................................................................................................ 13 + 4.2 Graphics Memory Clients ................................................................................................................... 13 + 4.3 Graphics Memory Addressing Overview ............................................................................................ 14 + 4.3.1 Graphics Address Path ................................................................................................................. 14 + 4.4 Graphics Memory Address Spaces ................................................................................................... 15 + 4.5 Address Tiling Function...................................................................................................................... 16 + 4.5.1 Linear vs. Tiled Storage ................................................................................................................ 16 + 4.5.2 Tile Formats .................................................................................................................................. 19 + 4.5.3 Tiling Algorithm ............................................................................................................................. 21 + 4.5.4 Tiled Channel Select Decision...................................................................................................... 23 + 4.5.5 Tiling Support................................................................................................................................ 25 + 4.5.6 Per-Stream Tile Format Support .................................................................................................. 28 + 4.6 Logical Memory Mapping ................................................................................................................... 28 + 4.6.1 Changes to GTT ........................................................................................................................... 29 + 4.6.2 Logical Memory Space Mappings ................................................................................................ 29 + 4.7 Physical Graphics Memory ................................................................................................................ 33 + 4.7.1 Physical Graphics Address Types ................................................................................................ 33 + 4.7.2 Main Memory ................................................................................................................................ 33 +5. Device Programming Environment ................................................................................................... 36 + 5.1 Programming Model ........................................................................................................................... 36 + 5.2 Graphics Device Register Programming............................................................................................ 36 + 5.3 Graphics Device Command Streams ................................................................................................. 36 + 5.3.1 Command Use .............................................................................................................................. 37 + 5.3.2 Command Transport Overview..................................................................................................... 37 + 5.3.3 Command Parser ......................................................................................................................... 37 + 5.3.4 The Ring Buffer ............................................................................................................................ 38 + 5.3.5 Batch Buffers ................................................................................................................................ 42 + 5.3.6 Indirect Data ................................................................................................................................. 42 + 5.3.7 Command Arbitration .................................................................................................................... 43 + 5.3.8 Graphics Engine Synchronization ................................................................................................ 45 + 5.3.9 Graphics Memory Coherency ....................................................................................................... 46 + 5.3.10 Graphics Cache Coherency ....................................................................................................... 46 + 5.3.11 Command Synchronization ........................................................................................................ 48 + 5.4 Hardware Status ................................................................................................................................ 50 + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 3 + 5.4.1 Hardware-Detected Errors (Master Error bit) ............................................................................... 50 + 5.4.2 Thermal Sensor Event .................................................................................................................. 50 + 5.4.3 Sync Status................................................................................................................................... 50 + 5.4.4 Display Plane A, B, (Sprite A, Sprite B) Flip Pending .................................................................. 50 + 5.4.5 Display Pipe A,B VBLANK ............................................................................................................ 50 + 5.4.6 User Interrupt ................................................................................................................................ 51 + 5.4.7 PIPE_CONTROL Notify Interrupt ................................................................................................. 51 + 5.4.8 Display Port Interrupt .................................................................................................................... 51 + 5.5 Hardware Status Writes ..................................................................................................................... 51 + 5.6 Interrupts ............................................................................................................................................ 51 + 5.7 Errors.................................................................................................................................................. 51 + 5.7.1 Error Reporting ............................................................................................................................. 51 + 5.7.2 Page Table Errors ........................................................................................................................ 52 + 5.7.3 Clearing Errors.............................................................................................................................. 57 + 5.8 Rendering Context Management ....................................................................................................... 57 + 5.8.1 Multiple Logical Rendering Contexts ............................................................................................ 58 + 5.9 Reset State ........................................................................................................................................ 59 + 5.10 Engine Idle ........................................................................................................................................ 60 + + + + +4 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 1. Introduction +The HW supports three engines.The render command streamer interfaces to 3D/IE and display streams. +The media command streamer interfaces to the fixed function media. The blitter command streamer +interfaces to the blit commands. Software interfaces of all 3 engines are very similar and should only +differ on engine-specific functionality. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 5 + 2. Virtual Memory +2.1 Global Virtual Memory +Global Virtual Memory is the default target memory if a PPGTT is not enabled. If a PPGTT is also +present, the method to choose which is targeted by memory and rendering operations varies by product. +See the sections on Per-Process Virtual Memory for more information. High priority graphics clients such +as Display and Cursor always access global virtual memory. + + + + +2.1.1 Graphics Translation Table (GTT) Range (GTTADR) +Address: GTTADR in CPU Physical Space +Access: Aligned DWord Read/Write +The GTTADR memory BAR defined in graphics device config space is an alias for the Global GTT. +Programming Notes: It is recommended that the driver map all graphics memory pages in the GGTT to +some physical page, if only a dummy page. + + +2.1.2 GTT Page Table Entries (PTEs) + +2.1.2.1 GTT Page Table Entries (PTEs) +Page Table Entry: 1 DWord per 4KB Graphics Memory page. + + + + +6 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + Bits Description + Physical Page Address 31:12: If the Valid bit is set, This field provides the page + number of the physical memory page backing the corresponding Graphics Memory + page. + 31: 12 + Physical Start Address Extension: This field specified Bits 39:32 of the page + table entry. This field must be zero for 32 bit addresses. + 11:4 + Graphics Data Type (GFDT) + This field contains the GFDT bit for this surface when writes occur. GFDT can also + be set by various state commands and indirect objects. The effective GFDT is the + logical OR of the GTT entry with this field. This field is ignored for reads. + Format = U1 + 0: No GFDT (default) + 1: GFDT + 3 + LLC Cacheability Control (LLCCC) + When GT is a caching agent: + This is the field used in GT interface block to determine what type of access need + to be generated to uncore. For the cases where the LLCCC is set, cacheable + transaction are generated to enable LLC usage for particular stream. + 0: use cacheability controls from GTT entry + 1: Data is cached in LLC + 2 + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 7 + L3 Cacheability Control (L3CC) + This field is used to control the L3 cacheability (allocation) of the stream. + 0: not cacheable within L3 + 1: cacheable in L3 + Note: even if the surface is not cacheable in L3, it is still kept coherent with L3 + content. + 1 + Valid PTE: This field indicates whether the mapping of the corresponding Graphics + Memory page is valid. + 1: Valid + 0: Invalid. An access (other than a CPU Read) through an invalid PTE will result in + Page Table Error (Invalid PTE). + 0 + + + +2.2 Two-Level Per-Process Virtual Memory + The motivation for the 2-level scheme is simple – it allows for the lookup table (the collection of page +tables) to exist in discontiguous memory, making allocation of memory for these structures less +problematic for the OS. The directory and each page table fit within a single 4K page of memory that can +be located anywhere in physical memory space. +If a PPGTT is enabled, all rendering operations (including blit commands) target Per-process virtual +memory. This means all commands except the Memory Interface Commands (MI_*). Certain Memory +Interface Commands have a specifier to choose global virtual memory (mapped via the GGTT) instead of +per-process memory. Global Virtual Memory can be thought of as “privileged” memory in this case. +Commands that elect to access privileged memory must have sufficient access rights to do so. +Commands executing directly from a ring buffer or from a “secure” batch buffer (see the +MI_BATCH_BUFFER_START command in Memory Interface Commands) have these access rights; +other commands do not and will not be permitted to access global virtual memory. See the Memory +Interface Commands chapters for details on command access of privileged memory. + + + + +8 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + The PPGTT is disabled by resetting the Per-Process GTT Enable + + + + +bit. +For SNB 32KB Big Pages, the non-big page client the access has no different view, similar to 4KB pages. +The page table is programmed similar to 4KB pages and h/w takes advantage of 32KBs for some +surfaces when it comes to TLB storage. +In case of a big page client, the following access path is used + + + + +The starting address of a 32KB page needs to be natively aligned to a 32KB boundary in memory. +Hardware uses certain bits (15 and up) to check for the TLB look-ups. +For Ivy Bridge, 32KB Big page implementation has been expanded to all surfaces and the restriction for +every pointer for 4KB does not need to be programmed: +If a PDE is marked 32KB, then . . . +(1) The entire PT pointed to by that PDE must use 32KB pages. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 9 + (2) PTE’s whose indexes are evenly divisible by 8 will be used (those not are ignored and need not be +populated). +(3) The phys addresses specified in each PTE must be 32KB aligned. + + + + +2.2.1 PPGTT Directory Entries (PDEs) +Directory Entry: 1 DWord per 4KB page table (4MB Graphics Memory). Page directories must be +located entirely within the GGTT (the table itself.) Directory entries should be updated only for non-active +contexts. If a directory entry update is done for a running context, it is unknown when that update will take +effect since the device caches directory entries. Directory entries can only be modified using GTTADDR +(see Memory Interface Commands for Rendering Engine). + 31 12 11 4 3 2 1 0 + Size ("0":4KB, "1":32KB) Valid +Physical Page Address 31:12 Physical Page Address 39:32 Reserved + + + +Bits Description + Physical Page Address 31:12: If the Valid bit is set, This field provides the page number of the physical + memory page backing the corresponding Graphics Memory page. +31:12 + Physical Page Address Extension: This field specifies bits 39:32 of the directory entry. +11:4 + 3:2 Reserved: MBZ + Page Size: Two page sizes are supported through PDE. + 0: 4KB pages + 1: 32KB pages + 1 + Valid PDE: This field indicates whether this directory entry is valid. + 1: Valid + 0: Invalid. An access through an invalid PDE will result in a page fault. + 0 + + +2.2.2 PPGTT Table Entries (PTEs) + +2.2.2.1 PPGTT Table Entries (PTEs) +Page Table Entry: 1 DWord per 4KB Graphics Memory page. Page Tables must be located in main +memory (not snooped). They can be updated directly in memory if proper precautions are taken, or from +the command stream by using the MI_UPDATE_GTT command (see Memory Interface Commands for +Rendering Engine). + + + + +10 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 31:12 11:4 3 2:1 0 +Physical Page Address 31:12 Physical Page Address 39:32 GFDT Cacheability Control Valid + + +Bits Description + Physical Page Address 31:12: If the Valid bit is set, This field provides the page number of the physical + memory page backing the corresponding Graphics Memory page. +31:12 + Physical Start Address Extension: This field specified Bits 39:32 of the page table entry. This field must be + zero for 32 bit addresses. +11:4 + Graphics Data Type (GFDT) + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by various state + commands and indirect objects. The effective GFDT is the logical OR of the GTT entry with this field. This field + is ignored for reads. + Format = U1 + 0: No GFDT (default) + 1: GFDT + 3 + Cacheability Control + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Format = U2 enumerated type + 00: Reserved + 01: data is not cached in LLC or MLC + 10: data is cached in LLC but not MLC + 11: data is cached in both LLC and MLC + Note for implementation: Bit 2 is already used to generate gam_ci_[r|ro|w]llc, so no GAM hardware changes + are required. + 2:1 + Valid PTE: This field indicates whether the mapping of the corresponding Graphics Memory page is valid. + 1: Valid + 0: Invalid. An access (other than a CPU Read) through an invalid PTE will result in Page Table Error (Invalid + PTE). + 0 + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 11 + 3. GFX MMIO – MCHBAR Aperture +Address: 140000h – 17FFFFh +Default Value: Same as MCHBAR +Access: Aligned Word, Dword or Qword Read/Write +This range defined in the graphics MMIO range is an alias with which graphics driver can read and write +registers defined in the MCHBAR MMIO space claimed through Device #0. Attributes for registers defined +within the MCHBAR space are preserved when the same registers are accessed via this space. Registers +that the graphics driver requires access to are Rank Throttling, GMCH Throttling, Thermal Sensor etc. +The Alias functions works for MMIO access from the CPU only. A command stream load register +immediate will drop the data and store register immediate will return all Zeros. +Graphics MMIO registers can be accessed through MMIO BARs in function #0 and function #1 in Device +#2. The aliasing mechanism is turned off if memory access to the corresponding function is turned off via +software or in certain power states. + + + + +12 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 4. Graphics Memory Interface Functions +4.1 Introduction +The major role of an integrated graphics device’s Memory Interface (MI) function is to provide various +client functions access to “graphics” memory used to store commands, surfaces, and other information +used by the graphics device. This chapter describes the basic mechanisms and paths by which graphics +memory is accessed. +Information not presented in this chapter includes: + +  Microarchitectural and implementation-dependent features (e.g., internal buffering, caching and + arbitration policies). +  MI functions and paths specific to the operation of external (discrete) devices attached via external + connections. +  MI functions essentially unrelated to the operation of the internal graphics devices, .e.g., traditional + “chipset functions”. + + +4.2 Graphics Memory Clients +The MI function provides memory access functionality to a number of external and internal graphics +memory clients, as described in the table below. + +Graphics Memory Clients + MI Client Access Modes +Host Processor Read/Write of Graphics Operands located in Main Memory. Graphics Memory is accessed + using Device 2 Graphics Memory Range Addresses +External PEG + Write-Only of Graphics Operands located in Main Memory via the Graphics Aperture. (This +Graphics Device + client is not described in this chapter). +Peer PCI Device + Write-Only of Graphics Operands located in Main Memory. Graphics Memory is accessed + using Device 2 Graphics Memory Range Addresses (i.e., mapped by GTT). Note that DMI + access to Graphics registers is not supported. + +Snooped Read/Write Internally-generated snooped reads/writes. +(internal) +Command Stream DMA Read of graphics commands and related graphics data. +(internal) +Vertex Stream DMA Read of indexed vertex data from Vertex Buffers by the 3D Vertex Fetch (VF) Fixed +(internal) Function. +Instruction/State Read of pipelined 3D rendering state used by the 3D/Media Functions and instructions +Cache (internal) executed by the EUs. +Render Cache Read/Write of graphics data operated upon by the graphics rendering engines (Blt, 3D, +(internal) MPEG, etc.) Read of render surface state. +Sampler Cache Read of texture (and other sampled surface) data stored in graphics memory. +(internal) +Display/Overlay Read of display, overlay, cursor and VGA data. +Engines (internal) + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 13 + 4.3 Graphics Memory Addressing Overview +The Memory Interface function provides access to graphics memory (GM) clients. It accepts memory +addresses of various types, performs a number of optional operations along address paths, and +eventually performs reads and writes of graphics memory data using the resultant addresses. The +remainder of this subsection will provide an overview of the graphics memory clients and address +operations. + + +4.3.1 Graphics Address Path +Graphics Address Path shows the internal graphics memory address path, connection points, and +optional operations performed on addresses. Externally-supplied addresses are normalized to zero-based +Graphics Memory (GM) addresses (GM_Address). If the GM address is determined to be a tiled address +(based on inclusion in a fenced region or via explicit surface parameters), address tiling is performed. At +this point the address is considered a Logical Memory address, and is translated into a Physical Memory +address via the GTT and associated TLBs. The physical memory location is then accessed. +CPU accesses to graphics memory are snooped post GTT translation. Hence pages that are mapped in +the GTT will be coherent with the CPU cache if accessed through graphics memory aperture. + + + + +14 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 4.3.1.1 Graphics Memory Paths + + + + +The remainder of this chapter describes the basic features of the graphics memory address pipeline, +namely Address Tiling, Logical Address Mapping, and Physical Memory types and allocation +considerations. + + +4.4 Graphics Memory Address Spaces +The Graphics Memory Address Spaces table lists the three supported Graphics Memory Address +Spaces. Note that the Graphics Memory Range Removal function is automatically performed to transform +system addresses to internal, zero-based Graphics Addresses. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 15 + Graphics Memory Address Types + Address Type Description Range +Dev2_GM_Addr Address range allocated via the Device 2 (integrated graphics + Some 64MB, 128MB, +ess device) GMADR register. The processor and other peer (DMI) + 256MB or 512MB + devices utilize this address space to read/write graphics data that + address range normally + resides in Main Memory. This address is internally converted to a + above TOM + GM_Address. +GM_Address Zero-based logical Graphics Address, utilized by internal device + [0, 64MB-1], + functions to access GTT-mapped graphics operands. + GM_Addresses are typically passed in commands and contained [0, 128MB-1], + in state to specify operand location. + [0, 256MB-1] or + [0, 512MB-1] +PGM_Address + Zero-based logical Per-Process Graphics Address, utilized by [0, 64MB-1], + internal device functions to access render GTT (PPGTT) mapped + [0,128MB-1], + graphics operands. Memory in this space is not accessible by the + processor and other peer (DMI) devices unless aliased to a [0,256MB-1], + GM_Address. + [0,512MB-1] or + [0, 1GB – 1] + + + +4.5 Address Tiling Function +When dealing with memory operands (e.g., graphics surfaces) that are inherently rectangular in nature, +certain functions within the graphics device support the storage/access of the operands using alternative +(tiled) memory formats in order to increase performance. This section describes these memory storage +formats, why/when they should be used, and the behavioral mechanisms within the device to support +them. + + +4.5.1 Linear vs. Tiled Storage +Regardless of the memory storage format, “rectangular” memory operands have a specific width and +height, and are considered as residing within an enclosing rectangular region whose width is considered +the pitch of the region and surfaces contained within. Surfaces stored within an enclosing region must +have widths less than or equal to the region pitch (indeed the enclosing region may coincide exactly with +the surface). Linear vs Tiled Storage shows these parameters. + + + + +16 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + Rectangular Memory Operand Parameters + + + + +The simplest storage format is the linear format (see Linear vs Tiled Storage), where each row of the +operand is stored in sequentially increasing memory locations. If the surface width is less than the +enclosing region’s pitch, there will be additional memory storage between rows to accommodate the +region’s pitch. The pitch of the enclosing region determines the distance (in the memory address space) +between vertically-adjacent operand elements (e.g., pixels, texels). + +Linear Surface Layout + + + + +The linear format is best suited for 1-dimensional row-sequential access patterns (e.g., a display surface +where each scanline is read sequentially). Here the fact that one object element may reside in a different + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 17 + memory page than its vertically-adjacent neighbors is not significant; all that matters is that horizontally- +adjacent elements are stored contiguously. However, when a device function needs to access a 2D +subregion within an operand (e.g., a read or write of a 4x4 pixel span by the 3D renderer, a read of a 2x2 +texel block for bilinear filtering), having vertically-adjacent elements fall within different memory pages is +to be avoided, as the page crossings required to complete the access typically incur increased memory +latencies (and therefore lower performance). +One solution to this problem is to divide the enclosing region into an array of smaller rectangular regions, +called memory tiles. Surface elements falling within a given tile will all be stored in the same physical +memory page, thus eliminating page-crossing penalties for 2D subregion accesses within a tile and +thereby increasing performance. +Tiles have a fixed 4KB size and are aligned to physical DRAM page boundaries. They are either 8 rows +high by 512 bytes wide or 32 rows high by 128 bytes wide (see Linear vs Tiled Storage). Note that the +dimensions of tiles are irrespective of the data contained within – e.g., a tile can hold twice as many 16-bit +pixels (256 pixels/row x 8 rows = 2K pixels) than 32-bit pixels (128 pixels/row x 8 rows = 1K pixels). + +Memory Tile Dimensions + + + + +The pitch of a tiled enclosing region must be an integral number of tile widths. The 4KB tiles within a tiled +region are stored sequentially in memory in row-major order. +The Linear vs Tiled Storage figure shows an example of a tiled surface located within a tiled region with a +pitch of 8 tile widths (512 bytes * 8 = 4KB). Note that it is the enclosing region that is divided into tiles – +the surface is not necessarily aligned or dimensioned to tile boundaries. + + + + +18 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + Tiled Surface Layout + + + + +4.5.2 Tile Formats +The device supports both X-Major (row-major) and Y-Major (column major) storage of tile data units, as +shown in the following figures. A 4KB tile is subdivided into an 8-high by 32-wide array of 16-byte OWords +for X-Major Tiles (X Tiles for short), and 32-high by 8-wide array of OWords for Y-Major Tiles (Y Tiles). +The selection of tile direction only impacts the internal organization of tile data, and does not affect how +surfaces map onto tiles. Note that the diagrams are not to scale – the first format defines the contents of +an 8-high by 512-byte wide tile, and the second a 32-high by 128-byte wide tile. The storage of tile data +units in X-Major or Y-Major fashion is sometimes refer to as the walk of the tiling. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 19 + X-Major Tile Layout + + + + +Note that an X-major tiled region with a tile pitch of 1 tile is actually stored in a linear fashion. + + + + +20 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + Y-Major Tile Layout + + + + +4.5.3 Tiling Algorithm +The following pseudocode describes the algorithm for translating a tiled memory surface in graphics +memory to an address in logical space. + Inputs: LinearAddress(offset into regular or LT aperture in terms of + bytes), + Pitch(in terms of tiles), + WalkY (1 for Y and 0 for X) + WalkW (1 for W and 0 for the rest) + Static Parameters: + TileH (Height of tile, 8 for X, 32 for Y and 64 for W), + TileW (Width of Tile in bytes, 512 for X, 128 for Y and 64 for W) + TileSize = TileH * TileW; + RowSize = Pitch * TileSize; + If (Fenced) { + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 21 + LinearAddress = LinearAddress – FenceBaseAddress + LinearAddrInTileW = LinearAddress div TileW; + Xoffset_inTile = LinearAddress mod TileW; + Y = LinearAddrInTileW div Pitch; + X = LinearAddrInTileW mod Pitch + Xoffset_inTile; + } + // Internal graphics clients that access tiled memory already have the + X, Y + // coordinates and can start here + YOff_Within_Tile = Y mod TileH; + XOff_Within_Tile = X mod TileW; + TileNumber_InY = Y div TileH; + TileNumber_InX = X div TileW; + TiledOffsetY = RowSize * TileNumber_InY + TileSize * + TileNumber_InX + TileH * 16 * (XOff_Within_Tile div 16) + + YOff_Within_Tile * 16 + (XOff_Within_Tile mod 16); + TiledOffsetW = RowSize * TileNumber_InY + TileSize * + TileNumber_InX + + TileH * 8 * (XOff_Within_Tile div 8) + + 64* (YOff_Within_Tile div 8)+ + 32*((YOff_Within_Tile div 4) mod 2) + + 16* ((XOff_Within_Tile div 4) mod 2) + + 8 * ((YOff_Within_Tile div 2) mod 2) + + 4* ((XOff_Within_Tile div 2) mod 2) + + 2 * (YOff_Within_Tile mod 2) + + (XOff_Within_Tile mod 2); + TiledOffsetX = RowSize * TileNumber_InY + TileSize * + TileNumber_InX + TileW * YOff_Within_Tile + + XOff_Within_Tile; + TiledOffset = WalkW? TiledOffsetW : (WalkY? TiledOffsetY : + TiledOffsetX); + TiledAddress = Tiled? (BaseAddress + TiledOffset): + (BaseAddress + Y*LinearPitch + X);TiledAddress = (Tiled && + (Address Swizzling for Tiled-Surfaces == 01)) ? + (WalkW || WalkY) ? + (TiledAddress div 128) * 128 + + (((TiledAddress div 64) mod 2) ^ + ((TiledAddress div 512) mod 2)) + + (TiledAddress mod 32) + : + + + + +22 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + (TiledAddress div 128) * 128 + + (((TiledAddress div 64) mod 2) ^ + ((TiledAddress div 512) mod 2) + ((TiledAddress Div 1024) mod2) + + (TiledAddress mod 32) + : + TiledAddress; + } +For Address Swizzling for Tiled-Surfaces see ARB_MODE – Arbiter Mode Control register, ARB_CTL— +Display Arbitration Control 1 and TILECTL - Tile Control register +The Y-Major tile formats have the characteristic that a surface element in an even row is located in the +same aligned 64-byte cacheline as the surface element immediately below it (in the odd row). This spatial +locality can be exploited to increase performance when reading 2x2 texel squares for bilinear texture +filtering, or reading and writing aligned 4x4 pixel spans from the 3D Render pipeline. +On the other hand, the X-Major tile format has the characteristic that horizontally-adjacent elements are +stored in sequential memory addresses. This spatial locality is advantageous when the surface is +scanned in row-major order for operations like display refresh. For this reason, the Display and Overlay +memory streams only support linear or X-Major tiled surfaces (Y-Major tiling is not supported by these +functions). This has the side effect that 2D- or 3D-rendered surfaces must be stored in linear or X-Major +tiled formats if they are to be displayed. Non-displayed surfaces, e.g., “rendered textures”, can also be +stored in Y-Major order. + + +4.5.4 Tiled Channel Select Decision +In order to spread DRAM accesses between multiple channels in the most efficient way, address bits are +used to select the channel. The most common DRAM configuration is 2-channels with 64B interleaving +where address bit[6] is used as channel select. However for tiled accesses, using bit[6] as is can be an +issue due to back to back accesses to have different patterns compared to liner streams. +For linear stream (no-X/Y tiling) address bit[6] has no modification. + +4.5.4.1 Address Swizzling for Tiled-Y Surfaces +The following board re-defines the address bit[6] after tiling. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 23 + As shown in the tiling algorithm, The new address bit[6] becomes : +Address bit[6] <= TiledAddr bit[6] XOR TiledAddr bit[9] + +4.5.4.2 Address Swizzling For Tiled-X Surfaces +Similar to Tiled-Y, we need to redefine the address bit[6] but for Tile-X, field mode needs to be taken into +account. + + + + +As shown in the tiling algorithm, the new address bit[6] should be: +Address bit[6] <= TiledAddr bit[6] XOR TiledAddr bit[9] XOR TiledAddr bit[10] + +4.5.4.3 When and Where to use the Tiled Address Swizzling +Address swizzling for tiled surfaces will be used for certain DRAM channel configurations with 64B (or +more) interleaving. However it is up to discretion of the GFX driver to set up the system to enable address +swizzling. +The need for address swizzling on Tiled Surfaces is communicated by GFX Driver to HW via MMIO +register updates. The following register present in 3 places of GFX MMIO region and driver is responsible +for consistent programming of all these values + + + +24 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + [1:0] R/W 00h + Address Swizzling for Tiled-Surfaces: This register location is updated via GFX Driver prior to enabling + DRAM accesses. Driver needs to obtain the need for memory address swizzling via DRAM + configuration registers and set the following bits (in Display Engine and Render/Media access streams) + 00: No address Swizzling + 01: Address bit[6] needs to be swizzled for tiled surfaces + 10: Reserved + 11: Reserved + +Note: the bit positions can vary due to assignments. +For GT => offset 0x0000_4030[5:4] ARB_MODE register +For DE => offset 0x0004_5000[14:13] Arbiter Control register + + + + +4.5.5 Tiling Support +The rearrangement of the surface elements in memory must be accounted for in device functions +operating upon tiled surfaces. (Note that not all device functions that access memory support tiled +formats). This requires either the modification of an element’s linear memory address or an alternate +formula to convert an element’s X,Y coordinates into a tiled memory address. +However, before tiled-address generation can take place, some mechanism must be used to determine +whether the surface elements accessed fall in a linear or tiled region of memory, and if tiled, what the tile +region pitch is, and whether the tiled region uses X-Major or Y-Major format. There are two mechanisms +by which this detection takes place: (a) an implicit method by detecting that the pre-tiled (linear) address +falls within a “fenced” tiled region, or (b) by an explicit specification of tiling parameters for surface +operands (i.e., parameters included in surface-defining instructions). +The following table identifies the tiling-detection mechanisms that are supported by the various memory +streams. + Access Path Tiling-Detection Mechanisms Supported +Processor access through the Graphics Memory Fenced Regions +Aperture +3D Render (Color/Depth Buffer access) Explicit Surface Parameters +Sampled Surfaces Explicit Surface Parameters +Blt operands Explicit Surface Parameters +Display and Overlay Surfaces Explicit Surface Parameters + + +4.5.5.1 Tiled (Fenced) Regions +The only mechanism to support the access of surfaces in tiled format by the host or external graphics +client is to place them within “fenced” tiled regions within Graphics Memory. A fenced region is a block of +Graphics Memory specified using one of the sixteen FENCE device registers. (See Memory Interface +Registers for details). Surfaces contained within a fenced region are considered tiled from an external +access point of view. Note that fences cannot be used to untile surfaces in the PGM_Address space +since external devices cannot access PGM_Address space. Even if these surfaces (or any surfaces +accessed by an internal graphics client) fall within a region covered by an enabled fence register, that +enable will be effectively masked during the internal graphics client access. Only the explicit surface +parameters described in the next section can be used to tile surfaces being accessed by the internal +graphics clients. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 25 + Each FENCE register (if its Fence Valid bit is set) defines a Graphics Memory region ranging from 4KB to +the aperture size. The region is considered rectangular, with a pitch in tile widths from 1 tile width (128B +or 512B) to 256 tile X widths (256 * 512B = 128KB) and 1024 tile Y widths (1024 * 128B = 128KB). Note +that fenced regions must not overlap, or operation is UNDEFINED. +Also included in the FENCE register is a Tile Walk field that specifies which tile format applies to the +fenced region. + +4.5.5.2 Tiled Surface Parameters +Internal device functions require explicit specification of surface tiling parameters via information passed +in commands and state. This capability is provided to limit the reliance on the fixed number of fence +regions. +The following table lists the surface tiling parameters that can be specified for 3D Render surfaces (Color +Buffer, Depth Buffer, Textures, etc.) via SURFACE_STATE. + Surface + Parameter Description +Tiled Surface If ENABLED, the surface is stored in a tiled format. If DISABLED, the surface is stored in a linear + format. +Tile Walk If Tiled Surface is ENABLED, this parameter specifies whether the tiled surface is stored in Y-Major + or X-Major tile format. +Base Address Additional restrictions apply to the base address of a Tiled Surface vs. that of a linear surface. +Pitch Pitch of the surface. Note that, if the surface is tiled, this pitch must be a multiple of the tile width. + + +4.5.5.3 Tiled Surface Restrictions +Additional restrictions apply to the Base Address and Pitch of a surface that is tiled. In addition, +restrictions for tiling via SURFACE_STATE are subtly different from those for tiling via fence regions. The +most restricted surfaces are those that will be accessed both by the host (via fence) and by internal +device functions. An example of such a surface is a tiled texture that is initialized by the CPU and then +sampled by the device. +The tiling algorithm for internal device functions is different from that of fence regions. Internal device +functions always specify tiling in terms of a surface. The surface must have a base address, and this base +address is not subject to the tiling algorithm. Only offsets from the base address (as calculated by X, Y +addressing within the surface) are transformed through tiling. The base address of the surface must +therefore be 4KB-aligned. This forces the 4KB tiles of the tiling algorithm to exactly align with 4KB device +pages once the tiling algorithm has been applied to the offset. The width of a surface must be less than or +equal to the surface pitch. There are additional considerations for surfaces that are also accessed by the +host (via a fence region). +Fence regions have no base address per se. Host linear addresses that fall in a fence region are +translated in their entirety by the tiling algorithm. It is as if the surface being tiled by the fence region has a +base address in graphics memory equal to the fence base address, and all accesses of the surfaces are +(possibly quite large) offsets from the fence base address. Fence regions have a virtual “left edge” +aligned with the fence base address, and a “right edge” that results from adding the fence pitch to the “left +edge”. Surfaces in the fence region must not straddle these boundaries. +Base addresses of surfaces that are to be accessed both by an internal graphics client and by the host +have the tightest restrictions. In order for the surface to be accessed without GTT re-mapping, the surface +base address (as set in SURFACE_STATE) must be a “Tile Row Start Address” (TRSA). The first +address in each tile row of the fence region is a Tile Row Start Address. The first TRSA is the fence base + + + + +26 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + address. Each TRSA can be generated by adding an integral multiple of the row size to the fence base +address. The row size is simply the fence pitch in tiles multiplied by 4KB (the size of a tile.) + +Tiled Surface Placement + + + + +The pitch in SURFACE_STATE must be set equal to the pitch of the fence that will be used by the host to +access the surface if the same GTT mapping will be used for each access. If the pitches differ, a different +GTT mapping must be used to eliminate the “extra” tiles (4KB memory pages) that exist in the excess +rows at the right side of the larger pitch. Obviously no part of the surface that will be accessed can lie in +pages that exist only in one mapping but not the other. The new GTT mapping can be done manually by +SW between the time the host writes the surface and the device reads it, or it can be accomplished by +arranging for the client to use a different GTT than the host (the PPGTT -- see Logical Memory Mapping +below). +The width of the surface (as set in SURFACE_STATE) must be less than or equal to both the surface +pitch and the fence pitch in any scenario where a surface will be accessed by both the host and an +internal graphics client. Changing the GTT mapping will not help if this restriction is violated. +Surface Access Base Address Pitch Width Tile “Walk” +Host only No restriction Integral multiple of tile size Must be <= Fence No restriction + <= 128KB Pitch +Client only 4KB-aligned Integral multiple of tile size Must be <= Surface + Restrictions imposed by + <= 256KB Pitch + the client (see Per Stream + Tile Format Support) + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 27 + Surface Access Base Address Pitch Width Tile “Walk” +Host and Client, Must be TRSA Fence Pitch = Surface Pitch Width <= Pitch Surface Walk must meet +No GTT = integral multiple of tile size client restriction, Fence +Remapping <= 256KB Walk = Surface Walk +Host and Client, 4KB-aligned for Both must be Integral Width <= Surface Walk must meet +GTT Remapping client (will be tile- multiple of tile size <=128KB, Min(Surface Pitch, client restriction, Fence + aligned for host) but not necessarily the same Fence Pitch) Walk = Surface Walk + + +4.5.6 Per-Stream Tile Format Support + MI Client Tile Formats Supported +CPU All +Read/Write +Display/Overlay + Y-Major not supported. + X-Major required for Async Flips +Blt + Linear and X-Major only + No Y-Major support +3D Sampler All Combinations of TileY, TileX and Linear are supported. TileY is the fastest, Linear is the + slowest. +3D Color,Depth Rendering Mode + Color-vs-Depth bpp Buffer Tiling Supported + Both Linear + Both TileX + Both TileY + Classical Linear & TileX + Same Bpp Linear & TileY + TileX & TileY + Both Linear + Both TileX + Both TileY + Classical Linear & TileX + Mixed Bpp Linear & TileY + TileX & TileY + NOTE: 128BPE Format Color buffer ( render target ) MUST be either TileX or Linear. + + + + +4.6 Logical Memory Mapping +In order to provide a contiguous address space for graphics operands (surfaces, etc.) yet allow this +address space to be mapped onto possibly discontiguous physical memory pages, the internal graphics +device supports a Logical Memory Space (see Logical Memory Space Mappings). A global Graphics +Translation Table (GTT) is provided to map zero-based (and post-tiled) Logical Memory Addresses into a +set of 4KB physical memory pages. (This mapping is also used for external PEG devices.) + +There is another logical mapping function available local to each graphics process; this works identically +to the global GTT with some additional restrictions. It is providing each graphics context with its own local +translation table(see Rendering Context Management later in this chapter). +The GTT and PPGTT are arrays of 4-byte Page Table Entries (PTEs) physically located in Main Memory. +The GTT and PPGTT are comprised of a number of locked (non-swappable) physically-contiguous 4KB + + + +28 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + memory pages, with a maximum size (each) of 128 4KB pages (128K DWords map 128K*4KB = 512MB +max) for Global GTT, and up to 512 4KB pages for PPGTT, for total up to 2GB max. GTT and PPGTT +base addresses must be 4KB-aligned. +Note that the PTEs within the global GTT must be written only through GTTADDR (see the Device #2 +Config registers for a description of this range), the invalidation of hardware TLBs need to be done +explicitly with a fence prior to enabling the new surface using updated PTEs. +The PPGTT base address is also 4KB aligned, but it is programmed directly in physical memory space +rather than through an alias mechanism like GTTADDR. Note that not all clients may use the PPGTT; +only the global GTT is available for processor accesses as well as graphics accesses from display +engines (including overlay and cursor). Any per-process access that occurs while the PPGTT is disabled +will default to a translation via the global GTT. + + +4.6.1 Changes to GTT +The GTT is constrained to be located at the beginning of a special section of stolen memory called the +GTT stolen memory (GSM). There is no longer an MMIO register containing the physical base address of +the GTT as on prior devices. Instead of using the PGTBL_CTL register to specify the base address of the +GTT, the GTT base is now defined to be at the bottom (offset 0) of GSM. +Since the graphics device (including the driver) knows nothing about the location of GSM, it does not +“know” where the GTT is located in memory. In fact, the CPU cannot directly access the GSM containing +the GTT. GTT entries therefore cannot be updated directly in memory as was possible on prior devices. +Instead, the driver must use GTTADR as it could before, or it must make use of a new command +(MI_UPDATE_GTT) to perform command-buffer-synchronized updates to the GTT. +The use by graphics of “physical” addressing is no longer be supported. Therefore all graphics +commands and registers that could, on prior devices, contain physical addresses must now use graphics +memory (virtual) addresses.Hardware definition is already updated to make sure all GFX base addresses +are in GFX virtual address space and mapped through page tables. + + +4.6.2 Logical Memory Space Mappings +Each valid PTE maps a 4KB page of Logical Memory to an independent 4KB page of: + +  MM: Main Memory (unsnooped), or +  SM: System Memory (snooped, therefore coherent with the processor cache, must not be accessed + through the Dev2_GM_Address range by the CPU) + +PTEs marked as invalid have no backing physical memory, and therefore the corresponding Logical +Memory Address pages must not be accessed in normal operation. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 29 + Global and Render GTT Mapping + + + + +The following table lists the memory space mappings valid for each MI client: + + + + +30 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + Logical Memory Space + MI Client Mappings Supported xGTT Usage + External Clients +Host Processor MM GTT only +External PEG Device None n/a +Snooped Read/Write None n/a + Internal GPU Clients +Render Command Ring Buffers MM GTT/PGTT, selected by PGTBL_STR2<2> +Render Command Batch Buffers MM GTT/PGTT, selected by PGTBL_STR2<5> +Indirect State Buffers MM GTT/PGTT, selected by PGTBL_STR2<4> +CURBE Constant Data MM Same xGTT used to fetch the + CONSTANT_BUFFER command. +Media Object Indirect Data MM Same xGTT used to fetch the + MEDIA_OBJECT command. +Vertex Fetch Data MM, SM GTT/PGTT, selected by PGTBL_STR2<3> +Sampler Cache (RO) MM, SM GTT/PGTT, selected by PGTBL_STR2<1> +DataPort Render Cache (R/W) MM, SM GTT/PGTT, selected by PGTBL_STR2<0> +Depth Buffer Cache (R/W) MM GTT/PGTT, selected by PGTBL_STR2<0> +Blit Engine MM, SM GTT/PGTT, selected by PGTBL_STR2<0> +MI_STORE_DATA_IMM Destination (if MM, SM Same xGTT used to fetch the command. +virtual addressed) +PIPE_CONTROL Write Destination MM, SM GTT/PGTT, selected by the command +Display/Overlay Engines (internal) MM GTT only + +Usage Note: Since the CPU cannot directly access memory pages mapped through a Graphics Process’ +local GTT (PPGTT), these pages must also be mapped though the global GTT (at least temporarily) in +order for the CPU to initialize graphics data for a Graphics Process. +The PPGTT mechanism can be used by a client to access a surface with a pitch that is smaller than that +of the fence region used by the host to initialize the surface, without having to physically move the data in +memory. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 31 + GTT Re-mapping to Handle Differing Pitches + + + + +Refer to the “Graphics Translation Table (GTT) Range (GTTADR) & PTE Description“ in Memory +Interface Registers for details on PTE formats and programming information. Refer to the Memory Data +Formats chapter for device-specific details/restrictions regarding the placement/storage of the various +data objects used by the graphics device. + +Logical-to-Physical Graphics Memory Mapping + + + + +32 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 4.7 Physical Graphics Memory +The integrated graphics device satisfies all of its memory requirements using portions of main system +memory. The integrated graphics device operates without any dedicated local memory, in a lower-cost +configuration typically (though not necessarily officially) known as Unified Graphics Memory (UMA). +The following figure shows how the Main Memory is interfaced to the device. + +Memory Interfaces + + + + +4.7.1 Physical Graphics Address Types +The Physical Graphics Address Types table lists the various physical address types supported by the +integrated graphics device. Physical Graphics Addresses are either generated by Logical Memory +mappings or are directly specified by graphics device functions. These physical addresses are not subject +to tiling or GTT re-mappings. + +Physical Memory Address Types + Address + Type Description Range +MM_Address [0,TopOfMemory- + Main Memory Address. Offset into physical, unsnooped Main + 1] + Memory. +SM_Address System Memory Address. Accesses are snooped in processor [0,4GB] + cache, allowing shared graphics/ processor access to (locked) + cacheable memory data. + + +4.7.2 Main Memory +The integrated graphics device is capable of using 4KB pages of physical main (system) memory for +graphics functions. Some of this main memory can be “stolen” from the top of system memory during + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 33 + initialization (e.g., for a VGA buffer). However, most graphics operands are dynamically allocated to +satisfy application demands. To this end the graphics driver will frequently need to allocate locked-down +(i.e., non-swappable) physical system memory pages – typically from a cacheable non-paged pool. The +locked pages required to back large surfaces are typically non-contiguous. Therefore a means to support +“logically-contiguous” surfaces backed by discontiguous physical pages is required. The Graphics +Translation Table (GTT) that was described in previous sections provides the means. + +4.7.2.1 Optimizing Main Memory Allocation +This section includes information for software developers on how to allocate SDRAM Main Memory (SM) +for optimal performance in certain configurations. The general idea is that these memories are divided +into some number of page types, and careful arrangement of page types both within and between +surfaces (e.g., between color and depth surfaces) will result in fewer page crossings and therefore yield +somewhat higher performance. +The algorithm for allocating physical SDRAM Main Memory pages to logical graphics surfaces is +somewhat complicated by (1) permutations of memory device technologies (which determine page sizes +and therefore the number of pages per device row), (2) memory device row population options, and (3) +limitations on the allocation of physical memory (as imposed by the OS). +However, the theory to optimize allocation by limiting page crossing penalties is simple: (a) switching +between open pages is optimal (again, the pages do not need to be sequential), (b) switching between +memory device rows does not in itself incur a penalty, and (c) switching between pages within a particular +bank of a row incurs a page miss and should therefore be avoided. + +4.7.2.2 Application of the Theory (Page Coloring) +This section provides some scenarios of how Main Memory page allocation can be optimized. + +4.7.2.2.1 3D Color and Depth Buffers +Here we want to minimize the impact of page crossings (a) between corresponding pages (1-4 tiles) in +the Color and Depth buffers, and (b) when moving from a page to a neighboring page within a Color or +Depth buffer. Therefore corresponding pages in the Color and Depth Buffers, and adjacent pages within a +Color or Depth Buffer should be mapped to different page types (where a page’s “type” or “color” refers to +the row and bank it’s in). + + + + +34 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + Memory Pages backing Color and Depth Buffers + + + + +For higher performance, the Color and Depth Buffers could be allocated from different memory device +rows. + +4.7.2.2.2 Media/Video +The Y surfaces can be allocated using 4 page types in a similar fashion to the Color Buffer diagram. The +U and V surfaces would split the same 4 page types as used in the Y surface. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 35 + 5. Device Programming Environment +The graphics device contains an extensive set of registers and commands (also referred to as +“commands” or “packets”) for controlling 2D, 3D, video I/O, and other operations. This chapter describes +the programming environment and software interface to these registers/commands. The registers and +commands themselves are described elsewhere in this document. + + +5.1 Programming Model +The graphics device is programmed via the following three basic mechanisms: +POST-Time Programming of Configuration Registers +These registers are the graphics device registers residing in PCI space. A majority of these registers are +programmed once during POST of the video device. Configuration registers are not covered in this +section. +Direct (Physical I/O and/or Memory-Mapped I/O) Access of Graphics Registers +Various graphics functions can only be controlled via direct register access. In addition, direct register +access is required to initiate the (asynchronous) execution of graphics command streams. This +programming mechanism is “direct” and synchronous with software execution on the CPU. +Command Stream DMA (via the Command Ring Buffer and Batch Buffers) +This programming mechanism utilizes the indirect and asynchronous execution of graphics command +streams to control certain graphics functions, e.g., all 2D, 3D drawing operations. Software writes +commands into a command buffer (either a Ring Buffer or Batch Buffer) and informs the graphics device +(using the Direct method above) that the commands are ready for execution. The graphics device’s +Command Parser (CP) will then, or at some point in the future, read the commands from the buffer via +DMA and execute them. + + +5.2 Graphics Device Register Programming +The graphics device registers (except for the Configuration registers) are memory mapped. The base +address of this 512 KB memory block is programmed in the MMADR Configuration register. For a detailed +description of the register map and register categories, refer to the Register Maps chapter. +Programming Note: + +  Software must only access GR06, MSR0, MSR1, and Paging registers (see Register Maps) via + Physical I/O, never via Memory Mapped I/O. + + +5.3 Graphics Device Command Streams +This section describes how command streams can be used to initiate and control graphics device +operations. + + + + +36 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 5.3.1 Command Use +Memory-resident commands are used to control drawing engines and other graphics device functional +units: + +  Memory Interface (MI) Commands. The MI commands can be used to control and synchronize the + command stream as well as perform various auxiliary functions (e.g., perform display/overlay flips, + etc.) +  2D Commands (BLT). These commands are used to perform various 2D (Blt) operations. +  3D Commands. 3D commands are used to program the 3D pipeline state and perform 3D rendering + operations. There are also a number of 3D commands that can be used to accelerate 2D and video + operations, e.g., “StretchBlt” operations, 2D line drawing, etc. +  Video Decode Commands (MPEG, etc.). A set of commands are supported to perform video decode + acceleration including Motion Compensation operations via the Sampling Engine of the 3D pipeline. + + +5.3.2 Command Transport Overview +Commands are not written directly to the graphics device – instead they are placed in memory by +software and later read via DMA by the graphics device’s Command Parser (CP) within the Memory +Interface function. The primary mechanism used to transport commands is through the use of a Ring +Buffer. +An additional, indirect mechanism for command transport is through the use of Batch Buffers initiated +from the Ring buffer. +The Command Parser uses a set of rules to determine the order in which commands are executed. +Following sections in this chapter provide descriptions of the Ring Buffer, Batch Buffers, and Command +Parser arbitration rules. + + +5.3.3 Command Parser +The graphics device’s Command Parser (CP) is responsible for: + +  Detecting the presence of commands (within the Ring Buffer). +  Reading commands from the Ring Buffer and Batch Buffers via DMA. This includes support of the + automatic head report function. +  Parsing the common "Command Type" (destination) field of commands. +  Execution of Memory Interface commands that control CP functionality, provide synchronization + functions, and provide display and overlay flips as well as other miscellaneous control functions. +  Redirection of 2D, 3D and Media commands to the appropriate destination (as qualified by the + INSTPM register) while enforcing drawing engine concurrency and coherency rules. +  Performing the “Sync Flush” mechanism +  Enforcing the Batch Buffer protection mechanism + +Below is a high-level diagram of the graphics device command interface. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 37 + Graphics Controller Command Interface + + + + +5.3.4 The Ring Buffer +The ring buffers are defined by a set of Ring Buffer registers and a memory area that is used to hold the +actual commands. The Ring Buffer registers (described in full below) define the start and length of the +memory area, and include two “offsets” (head and tail) into the memory area. Software uses the Tail +Offset to inform the CP of the presence of valid commands that must be executed. The Head Offset is +incremented by the CP as those commands are parsed and executed. The list of commands can wrap +from the bottom of the buffer back to the top. Also included in the Ring Buffer registers are control fields +that enable the ring and allow the head pointer to be reported to cacheable memory for more efficient flow +control algorithms. + + + + +38 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + Ring Buffer + + + + +5.3.4.1 The Ring Buffer (RB) +Ring Buffer support: + +  Batch Buffer initiation +  Indirect Data (operand access) + +5.3.4.2 Ring Buffer Registers +A Ring Buffer is defined by a set of 4 Ring Buffer registers. Before a Ring Buffer can be used for +command transport, software needs to program these registers. The fields contained within these +registers are as follows: + +  Ring Buffer Valid: This bit controls whether the Ring Buffer is included in the command arbitration + process. Software must program all other Ring Buffer parameters before enabling a Ring Buffer. + Although a Ring Buffer can be enabled in the non-empty state, it must not be disabled unless it is + empty. Attempting to disable a Ring Buffer in the non-empty state is UNDEFINED. Enabling or + disabling a Ring Buffer does not of itself change any other Ring Buffer register fields. +  Start Address: This field points to a contiguous, 4KB-aligned, linear (i.e., must not be tiled), mapped + graphics memory region which provides the actual command buffer area. +  Buffer Length: The size of the buffer, in 4KB increments, up to 2MB. +  Head Offset: This is the DWord offset (from Start Address) of the next command that the CP will + parse (i.e., it points one DWord past the last command parsed). The CP will update this field as + commands are parsed – the CP typically continues parsing new commands before the previous + command operations complete. (Note that, if commands are pending execution, the CP will likely + have prefetched commands past the Head Offset). As the graphics device does not "reset" the Head + Offset when a Ring Buffer is enabled, software must program the Head Offset field before enabling + the Ring Buffer. Software can enable a Ring Buffer with any legal values for Head/Tail (i.e., can + enable the Ring Buffer in an non-empty state). It is anticipated, but not required, that software enable + The Ring Buffer with Head and Tail Offsets of 0. Once the Head Offset reaches the QWord specified + by the Tail Offset (i.e., the offsets are equal), the CP considers the Ring Buffer "empty". + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 39 +  Head Wrap Count: This field is incremented by the CP every time the Head Offset wraps back to + the start of the buffer. As it is included in the DWord written in the "report head" process, software + can use this field to track CP progress as if the Ring Buffer had a "virtual" length of 2048 times the + size of the actual physical buffer (up to 4GB). +  Tail Offset: This is the offset (from Start Address) of the next QWord of command data that software + will request to be executed (i.e., it points one DWord past the last command DWord submitted for + execution). The Tail Offset can only point to an command boundary – submitting partial commands + is UNDEFINED. As the Tail Offset is a QWord offset, this requires software to submit commands in + multiples of QWords (both DWords of the last QWord submitted must contain valid command data). + Software may therefore need to insert a “pad” command to meet this restriction. After writing + commands into the Ring Buffer, software updates the Tail Offset field in order to submit the + commands for execution (by setting it to the QWord offset past the last command). The commands + submitted can wrap from the end of the buffer back to the top, in which case the Tail Offset written + will be less than the previous value. As the “empty” condition is defined as “Head Offset == Tail + Offset”, the largest amount of data that can be submitted at any one time is one QWord less than the + Ring Buffer length. +  IN USE Semaphore Bit: This bit (included in the Tail Pointer register) is used to provide a HW + semaphore that SW can use to manage access to the individual The Ring Buffer. See the Ring + Buffer Semaphore section below. +  Automatic Report Head Enable: Software can request to have the hardware Head Pointer register + contents written ("reported") to snooped system memory on a periodic basis. Auto-reports can be + programmed to occur whenever the Head Offset crosses either a 64KB or 128KB boundary. (Note + therefore that a Ring Buffer must be at least 64KB in length for the auto-report mechanism to be + useful). The complete Head Pointer register will be stored at a Ring Buffer-specific DWord offset into + the "hardware status page" (defined by the HWSTAM register). The auto-report mechanism is + desirable as software needs to use the Head Offset to determine the amount of free space in the + Ring Buffer -- and having the Head Pointer periodically reported to system memory provides a fairly + up-to-date Head Offset value automatically (i.e., without having to explicitly store a Head Pointer + value via the MI_REPORT_HEAD command). + +Ring Buffer Characteristics +Characteristic Description +Alignment 4 KB page aligned. +Max Size 2 MB +Length Programmable in numbers of 4 KB pages. +Start Pointer Programmable 4KB page-aligned address of the buffer +Head pointer + Hardware maintained DWord Offset into the ring buffer. Commands can wrap. + Programmable to initially set up ring. + +Tail pointer + Programmable QWord Offset into the ring buffer – indicating the next QWord + where software can insert new commands. + + +5.3.4.3 Ring Buffer Placement +Ring Buffer memory buffers are defined via a Graphics Address and must physically reside in (uncached) +Main Memory. There is no support for The Ring Buffer in cacheable system memory. + + + + +40 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 5.3.4.4 Ring Buffer Initialization +Before initializing a Ring Buffer, software must first allocate the desired number of 4KB pages for use as +buffer space. Then the Ring Buffer registers associated with the Ring Buffer can be programmed. Once +the Ring Buffer Valid bit is set, the Ring Buffer will be considered for command arbitration, and the Head +and Tail Offsets will either indicate an empty Ring Buffer (i.e., Head Offset == Tail Offset), or will define +some amount of command data to be executed. + +5.3.4.5 Ring Buffer Use +Software can write new commands into the "free space" of the Ring Buffer, starting at the Tail Offset +QWord and up to the QWord prior to the QWord indicated by the Head Offset. Note that this "free space" +may wrap from the end of the Ring Buffer back to the start (hence the “ring” in the name). +While the “free space” wrap may allow commands to be wrapped around the end of the Ring Buffer, the +wrap should only occur between commands. Padding (with NOP) may be required to follow this +restriction. +Software is required to use some mechanism to track command parsing progress in order to determine +the "free space" in the Ring Buffer. This can be accomplished in one of the following ways: + 1. A direct read (poll) of the Head Pointer register. This gives the most accurate indication but is + expensive due to the uncached read. + 2. The explicit reporting of the Head Pointer register via the MI_REPORT_HEAD command. This + allows for flexible and more accurate reporting but comes at the cost of command bandwidth + and execution time, in addition to the software overhead to determine how often to report the + head. + 3. Some other "implicit" means by which software can determine how far the CP has progressed + in retiring commands from a Ring Buffer. This could include the use of "Store DWORD" + commands to write sequencing data to system memory. This has similar characteristics to + using the MI_REPORT_HEAD mechanism. +Once the commands have been written and, if necessary, padded out to a QWord, software can write the +Tail Pointer register to submit the new commands for execution. The uncached write of the Tail Pointer +register will ensure that any pending command writes are flushed from the processor. +If the Ring Buffer Head Pointer and the Tail Pointer are on the same cacheline, the Head Pointer must not +be greater than the Tail Pointer. + +5.3.4.6 Ring Buffer Semaphore +When the Ring Buffer Mutex Enable (RBME) bit if the INSTPM MI register is clear, all Tail Pointer IN +USE bits are disabled (read as zero, writes ignored). When RBME is enabled, the IN USE bit acts as a +Ring Buffer semaphore. If the Tail Pointer is read, and IN USE is clear, it is immediately set after the read. +Subsequent Tail Pointer reads will return a set IN USE bit, until IN USE is cleared by a Tail Pointer write. +This allows SW to maintain exclusive ring access through the following protocol: A SW agent needing +exclusive ring access must read the Tail Pointer before accessing the Ring Buffer: if the IN USE bit is +clear, the agent gains access to the Ring Buffer; if the IN USE bit is set, the agent has to wait for access +to the Ring Buffer (as some other agent has control). The mechanism to inform pending agents upon +release of the IN USE semaphore is unspecified (i.e., left up to software). + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 41 + 5.3.5 Batch Buffers +The graphics device provides for the execution of command sequences external to the Ring buffer. These +sequences are called "Batch Buffers", and are initiated through the use of various Batch Buffer +commands described below. When a Batch Buffer command is executed, a batch buffer sequence is +initiated, where the graphics device fetches and executes the commands sequentially via DMA from the +batch buffer memory. + +5.3.5.1 Batch Buffer Chaining +What happens when the end of the Batch Buffer is reached depends on the final command in the buffer. +Normally, when a Batch Buffer is initiated from a Ring Buffer, the completion of the Batch Buffer will +cause control to pass back to the Ring Buffer at the command following the initiating Batch Buffer +command. +However, the final command of a Batch Buffer can be another Batch Buffer-initiating command +(MI_BATCH_BUFFER_START). In this case control will pass to the new Batch Buffer. This process, +called chaining, can continue indefinitely, terminating with a Batch Buffer that does not chain to another +Batch Buffer (ends with MI_BATCH_BUFFER_END) – at which point control will return to the Ring Buffer. + +Batch Buffer Chaining + + + + +5.3.5.2 Ending Batch Buffers +The end of the Batch Buffer is determined as the buffer is being executed: either by (a) an +MI_BATCH_BUFFER_END command, or (b) a “chaining” MI_BATCH_BUFFER_START command. +There is no explicit limit on the size of a Batch Buffer that uses GTT-mapped memory. Batch buffers in +physical space cannot exceed one physical page (4KB). + + +5.3.6 Indirect Data +In addition to Ring Buffer and Batch Buffers, the MI supports the access of indirect data for some specific +command types. (Normal read/write access to surfaces isn’t considered indirect access for this +discussion). + + + + +42 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 5.3.6.1 Logical Contexts +Logical Contexts, indirectly referenced via the MI_SET_CONTEXT command, must reside in (unsnooped) +Main Memory. + + +5.3.7 Command Arbitration +The command parser employs a set of rules to arbitrate among these command stream sources. This +section describes these rules and discusses the reasoning behind the algorithm. + +5.3.7.1 Arbitration Policies and Rationale +The Ring buffer (RB) is considered the primary mechanism by which drivers will pass commands to the +graphics device. +The insertion of command sequences into the Ring Buffer must be a "synchronous" operation, i.e., +software must guarantee mutually exclusive access to the Ring Buffer among contending sources +(drivers). This ensures that one driver does not corrupt another driver's partially-completed command +stream. There is currently no support for unsynchronized multi-threaded insertion of commands into ring +buffer. +Another requirement for asynchronous command generation arises from competing (and asynchronous) +drivers (e.g., "user-mode" driver libraries). In this case, the desire is to allow these entities to construct +command sequences in an asynchronous fashion, via batch buffers. Synchronization is then only +required to "dispatch" the batch buffers via insertion of Batch Buffer commands inserted into the Ring +Buffer. +Software retains some control over this arbitration process. The MI_ARB_ON_OFF command disables all +other sources of command arbitration until re-enabled by a subsequent MI_ARB_ON_OFF command +from the same command stream. This can be used to define uninterruptible "critical sections" in an +command stream (e.g., where some device operation needs to be protected from interruption). Disabling +arbitration from a batch buffer without re-enabling before the batch is complete is UNDEFINED. +Batch Buffers can be (a) interruptible at command boundaries, (b) interruptible only at chain points, or (c) +non-interruptible. See MI_BATCH_BUFFER_START in Memory Interface Commands for programming +details. + +5.3.7.2 Wait Commands +The MI_WAIT_EVENT command is provided to allow command streams to be held pending until an +asynchronous event occurs or condition exists. An event is defined as occurring at a specific point in time +(e.g., the leading edge of a signal, etc.) while a condition is defined as a finite period of time. A wait on an +event will (for all intents and purposes) take some non-zero period of time before the subsequent +command can be executed. A wait on a condition is effectively a noop if the condition exists when the +MI_WAIT_EVENT command is executed. +A Wait in the Ring Buffer or batch buffer will cause the CP to treat the Ring Buffer as if it were empty until +the specific event/condition occurs. This will temporarily stall the Ring Buffer. +While the Ring Buffer is waiting, the RB Wait bit of the corresponding RBn_CTL register will be set. +Software can cancel the wait by clearing this bit (along with setting the RB Wait Write Enable bit). This +will terminate the wait condition and the Ring Buffer will be re-enabled. This sequence can be included +when software is required to flush all pending device operations and pending Ring Buffer waits cannot be +tolerated. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 43 + 5.3.7.3 Wait Events/Conditions +This section describes the wait events and conditions supported by the MI_WAIT_EVENT command. +Only one event or condition can be specified in an MI_WAIT_EVENT, though different command streams +can be simultaneously waiting on different events. + +5.3.7.3.1 Display Pipe A,B Vertical Blank Event +The Vertical Blank event is defined as “shortly after” the leading edge of the next display VBLANK period +of the corresponding display pipe. The delay from the leading edge is provided to allow for internal device +operations to complete (including the update of display and overlay status bits, and the update of overlay +registers). + +5.3.7.3.2 Display Pipe A,B Horizontal Blank Event +The Horizontal Blank event is defined as “shortly after” the leading edge of the next display HBLANK +period of the corresponding display pipe. + +5.3.7.3.3 Display Plane A, B, Sprite A, Sprite B Flip Pending Condition +The Display Flip Pending condition is defined as the period starting with the execution of a “flip” +(MI_DISPLAY_BUFFER_INFO) command and ending with the completion of that flip request. Note that +the MI_DISPLAY_BUFFER_INFO command can specify whether the flip should be synchronized to +vertical refresh or completed “as soon as possible” (likely some number of horizontal refresh cycles later). + +5.3.7.3.4 Display Pipe A,B Scan Line Event +The Scan Line Event is defined as the start of a scan line specified in the Pipe A Display Scan Line Count +Range Compare Register. + +5.3.7.3.5 Semaphore Wait Condition +One of the 8 defined condition codes contained within the Execute Condition Code (EXCC) Register can +be selected as the source of a wait condition. While the selected condition code bit is set, the initiating +command stream will be removed from arbitration (i.e., paused). Arbitration of that command stream will +resume once the condition code bit is clear. If the selected condition code is clear when the +WAIT_ON_EVENT is executed, the command is effectively ignored. + +5.3.7.4 Command Arbitration Points +The CP performs arbitration for command execution at the following points: + +  Upon execution of an MI_ARB_CHECK command +  When the ring buffer becomes empty + +5.3.7.5 Command Arbitration Rules +At an arbitration point, the CP will switch to the new head pointer contained in the UHPTR register if it is +valid. Otherwise it will idle if empty, or continue execution in the current command flow if it arbitrated due +to an MI_ARB_CHECK command. + + + + +44 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 5.3.7.6 Batch Buffer Protection +The CP employs a protection mechanism to help prevent random writes to system memory from +occurring as a result of the execution of a batch buffer generated by a “non-secure” agent (e.g., client- +mode library). Commands executed directly from a ring buffer, along with batch buffers initiated from a +ring buffer and marked as “secure”, will not be subject to this protection mechanism as it is assumed they +can only be generated by “secure” driver components. +This protection mechanism is enabled via a field in a Batch Buffer command that indicates whether the +associated batch buffer is “secure” or “non-secure”. When the CP processes a non-secure batch buffer +from the ring buffer it does not allow any MI_STORE_DATA_IMM commands that reference physical +addresses, as that would allow the non-secure source to perform writes to any random DWord in the +system. (Note that graphics engines will only write to graphics memory ranges, which by definition are +virtual memory ranges mapped into physical memory pages by trusted driver components using the +GTT/TGTT hardware). Placing an MI_STORE_DATA in a non-secure batch buffer will instead cause a +Command Error. The CP will store the header of the command, the origin of the command, and an error +code. In addition, such a Command Error can generate an interrupt or a hardware write to system +memory (if these actions are enabled and unmasked in the IER and IMR registers respectively.) At this +point the CP can be reactivated only by a full reset. +The security indication field of Batch Buffer instructions placed in batch buffers (i.e., “chaining” batch +buffers) is ignored and the chained batch buffer will therefore inherit the security indication of the first +Batch Buffer in the chain (i.e. the batch buffer that was initiated by an MI_BATCH_BUFFER_START +command in the Ring Buffer). + + +5.3.8 Graphics Engine Synchronization +This table lists the cases where engine synchronization is required, and whether software needs to +ensure synchronization with an explicit MI_FLUSH command or whether the device performs an implicit +(automatic) flush instead. Note that a pipeline flush can be performed without flushing the render cache, +but not vice versa. + Implicit Flush or Requires Explicit + Event Flush? +PIPELINE_SELECT Requires explicit pipeline flush +Any Non-pipelined State Command Device implicitly stalls the command + until the pipeline has drained sufficiently + to allow the state update to be + performed without corrupting work-in- + progress +MI_SET_CONTEXT Device performs implicit flush + Requires explicit render cache flush + MI_DISPLAY_BUFFER_INFO + (“display flip”) +MI_OVERLAY_FLIP Requires explicit render cache flush +3D color destination buffer (render target) used as texture Requires explicit render cache flush +(i.e., “rendered texture”) +MEDIA_STATE_POINTERS Requires explicit pipeline flush +MEDIA_OBJECT Requires explicit pipeline flush +Media: Previous Destination Used as Source Requires explicit render cache flush + MI_SEMAPHORE_MBOX update to another pipe that Requires explicit pipe flush + requires output of current pipe to be in coherent memory. + Example is blitter/render pipe synchronization + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 45 + Workaround: Any time a pipeline flush is used it will need to follow by 8 separate storeDW commands. +This is done as a workaround to a known issue where the pipeline flush does not push all cycles to the +“GO” point. The store DWs will not accomplish this process but will create enough stall time to ensure all +cycles are at GO prior to execution of the next buffer or part of the buffer. This is required for +producer/consumer model. + + +5.3.9 Graphics Memory Coherency +vol1c Memory Interface and Command Stream2 lists the various types of graphics memory coherency +provided by the device, specifically where the CPU writes to a 64B cacheline, and the device then +accesses that same cacheline. Note that the coherency policy depends on the address type (GM or MM) +involved in the accesses. + +Graphics Memory Coherency + CPU Subsequent Example +Access Device Access Operand Coherency +Write GM Read GM +Write MM Read MM +Write GM Write GM Device ensures coherency following every Ring Buffer + Tail Pointer write. (This can be made optional via a bit in + the Tail Pointer data). +Write MM Write MM + +Write GM Read MM Device ensures coherency following every Ring Buffer + Tail Pointer write. (This can be made optional via a bit in + the Tail Pointer data). + + +5.3.10 Graphics Cache Coherency +There are several caches employed within the graphics device implementation. This section describes +the impact of these caches on the programming model (i.e., if/when does software need to be +concerned). + +5.3.10.1 Rendering Cache +The rendering (frame buffer) cache is used by the blit and 3D rendering engines and caches portions of +the frame buffer color and depth buffers. This cache is guaranteed to be flushed under the following +conditions (note that the implementation may flush the cache under additional, implementation-specific +conditions): + +  Execution of an MI_FLUSH command with the Render Flush Cache Inhibit bit clear +  Execution of a PIPE_CONTROL instruction with the Write Cache Flush Enable bit set (Depth Stall + must be clear). +  A SyncFlush handshake operation +  A change of rendering engines (e.g., going from 2D to 3D, 3D to 2D, etc.) +  Logical Context switch (via MI_SET_CONTEXT) + +The render cache must be explicitly flushed using one of these mechanisms under certain conditions. +See Graphics Engine Synchronization . + + + + +46 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 5.3.10.2 Sampler Cache +The read-only sampler cache is used to cache texels and other data read by the Sampling Engine in the +3D pipeline. This cache can be enabled or disabled via the Texture L2 Disable bit of the Cache_Mode_0 +register (see Memory Interface Registers). Note that, although there may be more than one level of +sampler cache within the implementation, the sampler cache is exposed as a single entity at the +programming interface. +The sampler cache is guaranteed to be invalidated under the following conditions (note that the +implementation may invalidate the cache under additional, implementation-specific conditions): + +  Execution of an MI_FLUSH command with the Map Cache Invalidate bit set +  Execution of PIPE_CONTROL with the Depth Stall Enable bit clear. +  A SyncFlush handshake operation + +The sampler cache must be invalidated prior to reallocation of physical texture memory (i.e., software +must guarantee that stale texture data is invalidated before reusing physical texture memory for a new or +modified texture). + +5.3.10.3 Instruction/State Cache +The read-only ISC is used to cache pipelined state and EU instructions read in from memory. It also +functions as a prefetch cache by reading in additional state information and instructions beyond those +immediately requested in order to decrease latency and improve performance. As with the sampler +cache, there may be more than one level of ISC within the implementation. The ISC is exposed as a +single entity at the programming interface. +The instruction/state cache is guaranteed to be invalidated under the following conditions (note that the +implementation may invalidate the cache under additional, implementation-specific conditions): + +  Execution of an MI_FLUSH command with the State/Instruction Cache Invalidate bit set +  Execution of PIPE_CONTROL with the Instruction/State Cache Flush Enable bit set. +  A SyncFlush handshake operation + +The instruction/state cache must be invalidated prior to reallocation of physical state/instruction memory +(i.e., software must guarantee that stale state/instruction data is invalidated before reusing physical +state/instruction memory for new or modified state or instructions). + +5.3.10.4 Vertex Cache +The vertex cache consists of 2 sub-caches: one that caches vertex buffer data based on address, and +another that caches (possibly shaded) vertex attribute data based on index (see the Vertex Fetch chapter +for vertex index details). The latter cache is always invalidated between primitive topologies. +Both vertex caches are guaranteed to be invalidated under the following conditions (note that the +implementation may invalidate the cache under additional, implementation-specific conditions): + +  Execution of an MI_FLUSH command +  Execution of a PIPE_CONTROL command +  A SyncFlush handshake operation +  Logical Context switch (via MI_SET_CONTEXT) + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 47 + 5.3.10.5 GTT TLBs +The following table summarizes when the various TLBs are invalidated. + TLB Normal Invalidation Mechanism +Display Refreshed on Vsync +Overlay Refreshed on Vsync +Render/Blit Internal Flush* +Host Through a Page Table PTE write +Sampler Cache Internal Flush* +Command Stream Through a Page Table PTE write + +* -- Includes MI_FLUSH, Engine switch, and Context switch. + + +5.3.11 Command Synchronization +This section describes the hardware mechanisms that can be used by software to provide +synchronization with command stream parsing and execution. +The key point here is distinguishing between command parsing and retirement – in that, for most +commands, there is some finite delay between the parsing of a command and the retirement (coherent +completion) of the operation it specifies. +Interrogation of the Ring Buffer Head Pointer only gives an indication of the progress of command +parsing. This information is required to discern the availability of command data within the Ring Buffer or +Batch Buffers. If the Head Pointer indicates the command data has been parsed, those locations can be +reused, otherwise the commands must be considered still pending parsing and left alone. +Given the CP rules for command execution, it is possible to use the indication of command parsing +progress to infer the retirement status of parsed commands. The only indication of instruction retirement +available from instruction parsing is that parsing of an MI instruction implies retirement of previous MI +instructions with the following exceptions: + +  The parsing of a Memory Interface (MI) command implies that all previously-parsed MI commands + have completed, with the following exceptions: + - Display and Overlay Flip commands: Only the submission of the flip request is guaranteed. The flip + operation will occur some time later. Mechanisms to detect the actual completion of a flip operation + are described below. + - “Store-Data” type commands: Only the submission of the store operation is guaranteed. The write + result will be complete (coherent) some time later (this is practically a finite period but there is no + guaranteed latency). + - Batch Buffer commands: There is no guarantee that the operations performed by the batch buffer + have completed. + +Other than the cases described above, additional measures must be taken to discern the progress of +command retirement. These measures are described in the following subsections. + +5.3.11.1 MI_FLUSH +The MI_FLUSH command pauses further command parsing until all drawing engines become idle and +any internal rendering cache is flushed and invalidated. All previous rendering commands can therefore +be considered retired. +This flush operation is considered complete once command parsing proceeds to the next command. +Software can, for example, follow an MI_FLUSH command with an MI_STORE_DATA_IMM or +MI_STORE_DATA_INDEX command – where the completion of the store operation implies that the flush + + + +48 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + operation has completed. (Note that if the last DWord in a ring buffer is an MI_FLUSH instruction, there is +no way by simply looking at the Ring Buffer registers to determine whether the flush operation is complete +or still pending.) +The successful completion of an MI_FLUSH command does not guarantee that all previous operations +have completed. Operations that may still be pending include: + +  Store Data type commands (MI_STORE_DATA_IMM, MI_STORE_DATA_INDEX, + MI_REPORT_HEAD) +  Display or Overlay Flip operations + +See Sampler Cache for more information on when the sampler cache should be invalidated. + +5.3.11.2 Sync flush +Inserting MI_FLUSH commands, while effective at determining or forcing the retirement of previous +rendering commands, may negatively impact performance if not absolutely required. For example, if the +knowledge of rendering command retirement is not known a priori, it is likely undesirable to insert +MI_FLUSH commands at intervals in the command stream. However, it may not be acceptable to insert +an MI_FLUSH command (and wait for its completion) at the point that rendering command retirement is +required – as there may be a large number of commands pending in ring/batch buffers at that point and +flushing the entire device (including waiting for completion of pending commands that have not yet been +parsed) may be prohibitive. There is a mechanism, however, where command stream synchronization +can be performed on demand, without requiring earlier submitted commands and batch buffers to +complete – it is called the “Sync Flush” mechanism. +Here’s how it works: + +  Software must (preferably at driver initialization time) unmask the Sync Status bit in the Hardware + Status Mask Register (HWSTAM). This should be done unconditionally (at least whenever HW + status writes are enabled), as any bandwidth increase due to Sync Status-initiated writes is + negligible. +  At the point that synchronization is required, software must guarantee that command parsing has + progressed past the point of interest in the command stream (i.e., past the last command whose + retirement is required). Note that this step is required in any scheme. +  Software then reads the location where the Interrupt Status is reported in the Hardware Status Page + (DWord offset 0) and saves that DWord in a temporary variable. +  Software then sets the Sync Enable bit of the Command Parser Mode Register (INSTPM) via an + uncached write. +  The Command Parser will detect the Sync Enable bit set before it proceeds to the very next + command (or immediately if the CP is idle). It will then perform an internal flush operation. This flush + is identical to that performed by an MI_FLUSH command with all flush types enabled. +  Once this flush operation is complete, the CP will clear the Sync Enable bit of the INSTPM register + and then toggle the Sync Status bit of the ISR register. This will initiate a write of the ISR register + contents (with the toggled Sync Status) to DWord 0 of the Hardware Status page (as part the normal + hardware status write mechanism). +  Software, following the write of the INSTPM register, should periodically poll the Hardware Status + location. By comparing the current versus saved value of the Sync Status bit, software can then + detect when the flush operation is complete. Note that the latency of this operation is typically small, + as it will be initiated either immediately or at least before the next command is parsed (regardless of + arbitration conditions). + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 49 + 5.4 Hardware Status +The graphics device supports a number of internal hardware status bits which can be used to detect and +monitor hardware status conditions via polling or interrupts. This section will describe each hardware +status bit. The following section describes the hardware status reporting (polling) mechanism. The +mechanism to allow these status bits to generate interrupts is described in the Interrupts section. Note +that the hardware status bits are actually reported in the Interrupt Status Register, so “hardware status” +and “interrupt status” are used interchangeably here (though many hardware status bits won’t necessarily +ever be used to generate interrupts). +The following subsections describe the various hardware (interrupt) status bits, as defined in the Interrupt +Status Register. + + +5.4.1 Hardware-Detected Errors (Master Error bit) +This interrupt status bit is generated whenever an “unmasked” hardware-detected error status is +detected. See Errors. + + +5.4.2 Thermal Sensor Event +This interrupt status bit is generated by “thermal events” detected by the Thermal Sensor logic. The bit +corresponding to this event in the HWSTAM register must always be masked (i.e., set to ‘1’) so that +thermal sensor events do not generate HW status DWord writes. See Hardware Status Writes. + + +5.4.3 Sync Status +This bit should only be used as described in Sync Flush, and should not be used to generate interrupts +(i.e., the corresponding interrupt should not be enabled in the IER). + + +5.4.4 Display Plane A, B, (Sprite A, Sprite B) Flip Pending +These bits are used to report the status of “flip” operations on the corresponding Display Plane. Display +Flip operations are requested via the MI_DISPLAY_BUFFER_INFO command. When that command is +executed, the corresponding Display Flip Pending status in the ISR register will be set to ‘1’ indicating that +a display flip has been requested but has not yet been performed. (Requesting a flip operation when one +is already pending is UNDEFINED). This indicates that a flip is “pending”. At the appropriate time during +the next vertical blank period (for that display stream), the flip operation will be performed (i.e., the display +will switch to refreshing from the new display buffer). This causes the Display Flip Pending status to reset +to ‘0’. When this occurs, and the Display Flip Pending status bit is unmasked by the Interrupt Mask +Register (IMR), the Display Flip Pending status bit of the Interrupt Identity Register (IIR) is set. Note that +this setting of an interrupt identity bit on the falling edge of the status bit is contrary to the general +definition of interrupt status bits. + + +5.4.5 Display Pipe A,B VBLANK +These bits are set on the leading edge of the selected Display Pipe’s VBLANK signal. + + + + +50 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 5.4.6 User Interrupt +This bit is set in response to the execution of an MI_USER_INTERRUPT command. The Command +Parser will continue parsing after processing that command. If a user interrupt is currently outstanding +(set in the ISR) this packet has no effect. +Programming Note: User interrupts can be used to notify software of the progress of instruction parsing +past the MI_USER_INTERRUPT instruction. Standard rules regarding instruction parsing versus +instruction retirement documented in the section of this chapter still apply. In particular, user interrupts +can be inserted into the command stream but effectively disabled for “normal operation” via the IMR and +HWSTAM registers. Whenever software requires the notification afforded by the user interrupts, it can +unmask this bit. + + +5.4.7 PIPE_CONTROL Notify Interrupt +This bit is set when a PIPE_CONTROL command with the Notify Enable bit set reaches the end of the +pipeline and all required cache flushes have occurred. + + +5.4.8 Display Port Interrupt +This bit is set on a hot plug event. See the Display Registers chapter for details. + + +5.5 Hardware Status Writes +The graphics device supports the writing of the hardware status (ISR) bits into memory for optimized +access from software. Software can select which (if any) status bits will trigger the write of the ISR +contents to memory using the Hardware Status Mask (HWSTAM) register. Writing a ‘0’ to a defined bit +position in the HWSTAM register will cause any change (0 => 1 or 1 => 0) in the corresponding ISR bit to +trigger the write. The complete ISR contents will be written to DWord offset 0 of the hardware status page, +located at the address programmed via the Hardware Status Page Address Register (HWS_PGA). + + +5.6 Interrupts +The graphics device supports the generation of an interrupt. This interrupt can be raised in response to +one or more internal interrupt status conditions. Which interrupt status conditions are allowed to raise an +interrupt is programmed via the Interrupt Mask Register (IMR) and Interrupt Enable Register (IER). The +IMR is used to selectively “unmask” hardware status bits as to allow them to be reported in the Interrupt +Identity Register (IIR). The IER holds a set of interrupt enable bits corresponding to each bit of the IIR – +setting bits in the IER will allow interrupts to be generated by the corresponding bits in the IIR. + + +5.7 Errors + +5.7.1 Error Reporting +Regardless of the error classification, all errors funnel through the Master Error bit of the Interrupt +Control Registers. This bit can be used to raise a device interrupt or trigger a hardware status write +operation. (Needless to say it can also be polled directly, though this is clearly discouraged). Refer to +Interrupt Control Registers in the Memory Interface Registers chapter for more information. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 51 + There are three registers dedicated to control, detect, and clear hardware error status conditions in a +similar fashion to the Interrupt Control Registers. All three error registers share a common error status bit +definition. +The Error Status Register (ESR) holds the actual error status bits (each of which may be the logical OR of +“source” error bits in various functional registers). The Error Mask Register (EMR) is used to select which +error status bit(s) are reported in the Error Identity Register (EIR). The EIR holds the “persistent” values of +the unmasked error status bits, and is also used to clear error status conditions. Any bits set in the EIR +will raise the Master Error interrupt status condition. +The error conditions corresponding to the error status bits include: + + +5.7.2 Page Table Errors +The following tables describe the various sources and types of Page Table Errors. Refer to the +description of the PGTBL_ERR register in Memory Interface Registers for more details. + +Page Table Error Types + Error Description Streams +Invalid GTT In the process of mapping an address, the MI encountered a GTT PTE + All (See +PTE that was marked “Invalid”. This would be the result of a programming + Graphics + error. + Memory + Clients) + +Invalid TLB An unexpected TLB miss (detected at GTT request time) was Display, +Miss encountered (e.g., during Display/Overlay/Sprite access). Overlay +Invalid PTE Mapping to the physical page specified in the PTE is not permitted (e.g., Host +Data a page in PAM, SMM or over the top of memory, etc.). This is the result + of a programming error. +Invalid Tiling A tiling parameter was found inconsistent with the current operation. This Blt, Display, + includes the use of Y-Major tiling in the Render/Display/Overlay streams. Overlay + This is the result of a programming error. This is detected during GTT + request. + +Note that Page Table Errors cannot be cleared. A device reset is required. + +5.7.2.1 Page Fault Handling +Register Recording +For each engine (Graphics, Media, and Blitter), there is a register that will be used for recording the first +page fault that occurs for that engine. Subsequent faults will be treated as described above, but will not +be recorded, until the valid bit of that register is cleared by Software (Valid bit is set when the first fault for +that engine happens). This will provide a lead to Software on when did things started going wrong. +(Page faults are presumed to be caused by a SW programming error) + + + + +52 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + GFX_ENG_FR - Graphics Engine Fault Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04094h-04097h + +Graphics Engine Fault Register + + +DWord Bit Description +0 31:12 Virtual Address of Fault + Default Value: 00000h + Access: R/W + + This is the original Address of the Page that generated the First fault for this engine. + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + + + + 11 GTTSEL + Default Value: 0b + Access: R/W + + This bit indicates if the valid bit happened while using PPGTT or GGTT: 0 - PPGTT, 1 - GGTT + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 10:3 SRCID of Fault + Default Value: 00h + Access: R/W + + This is the Source ID of the unit that requested the cycle that generated the First Page fault for this + engine. + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 2:1 Fault Type + Default Value: 00b + Access: R/W + + Type of Fault recorded: + + 00 - Page Fault. + + 01 - Invalid PD Fault + + 10 - Unloaded PD Fault + + 11 - Invalid and Unloaded PD fault + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 53 + GFX_ENG_FR - Graphics Engine Fault Register + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 0 Valid Bit + Default Value: 0b + Access: R/W + + This bit indicates that the first fault for this engine has been recorded. It can only be cleared by SW, + which will also clear the other fields. + + + + + MEDIA_ENG_FR - Media Engine Fault Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04194h-04197h + +Media Engine Fault Register + + +DWord Bit Description +0 31:12 Virtual Address of Fault + Default Value: 00000h + Access: R/W + + This is the original Address of the Page that generated the First fault for this engine. + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + + + + 11 GTTSEL + Default Value: 0b + Access: R/W + + This bit indicates if the valid bit happened while using PPGTT or GGTT: 0 - PPGTT, 1 - GGTT + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 10:3 SRCID of Fault + Default Value: 00h + Access: R/W + + + + +54 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + MEDIA_ENG_FR - Media Engine Fault Register + This is the Source ID of the unit that requested the cycle that generated the First Page fault for this + engine. + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 2:1 Fault Type + Default Value: 00b + Access: R/W + + Type of Fault recorded: + + 00 - Page Fault. + + 01 - Invalid PD Fault + + 10 - Unloaded PD Fault + + 11 - Invalid and Unloaded PD fault + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 0 Valid Bit + Default Value: 0b + Access: R/W + + This bit indicates that the first fault for this engine has been recorded. It can only be cleared by SW, + which will also clear the other fields. + + + + + BLT_ENG_FR - Blitter Engine Fault Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04294h-04297h + +Blitter Engine Fault Register + + +DWord Bit Description +0 31:12 Virtual Address of Page Fault + Default Value: 00000h + Access: R/W + + This is the original Address of the Page that generated the First fault for this engine. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 55 + BLT_ENG_FR - Blitter Engine Fault Register + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + + + + 11 Blitter GTTSEL + Default Value: 0b + Access: R/W + + This bit indicates if the valid bit happened while using PPGTT or GGTT: 0 - PPGTT, 1 - GGTT + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 10:3 SRCID of Fault + Default Value: 00h + Access: R/W + + This is the Source ID of the unit that requested the cycle that generated the First Page fault for this + engine. + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 2:1 Fault Type + Default Value: 00b + Access: R/W + + Type of Fault recorded: + + 00 - Page Fault. + + 01 - Invalid PD Fault + + 10 - Unloaded PD Fault + + 11 - Invalid and Unloaded PD fault + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 0 Valid Bit + Default Value: 0b + Access: R/W + + This bit indicates that the first fault for this engine has been recorded. It can only be cleared by SW, + which will also clear the other fields. + + + + +56 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 5.7.3 Clearing Errors +For operational errors, software is responsible for taking the proper steps to recover from the error and +then clearing the error indication. The actions required to recover from operational errors may be +discussed in the various functional areas (not here). See the Hardware-detected Error Bit Definitions in +Memory Interface Registers for more details. This subsection describes the actions required to clear the +error indication. +In order to clear operational errors, software is responsible for clearing the error condition from the +source, working back to the Master Error bit. Typically this will entail the following sequence. + +  First the primary source of the error must be cleared. This requires clearing the functional register(s) + containing the source error indication. +  Next, clear the particular error status bit by writing a ‘1’ to the appropriate bit of the Error Identity + Register (EIR). This will clear the error status bit in the Error Status Register (ESR). If multiple errors + are present, all error status bits should be cleared simultaneously. +  Next, clear the Master Error interrupt status bit by writing a ‘1’ to the Master Error bit of the Interrupt + Identity Register (IIR). + +Note: Page Table Errors cannot be cleared. + + +5.8 Rendering Context Management +The graphics device operation (rendering, etc.) is controlled via the settings of numerous hardware state +variables. These state variables are divided into global state and context state. +There is only one copy of global state variables, and changing the settings of these variables requires +explicit programming of the state variables. Examples of global state include: + +  MI registers (HWSTAM, Ring Buffer, etc.) with the exception of those listed in the next paragraph + (i.e, registers listed there are saved/restored) +  Configuration registers +  Display programming registers + +On the other hand, context state is associated with a specific context, where switching to that context +causes that context’s state to be restored. While the associated context is active, the state variables and +registers can be programmed via the command stream. Examples of context state include the +PIPELINE_STATE_POINTERS command and most non-pipelined state. The following MI registers are +considered part of context state and thus saved/restored with context: + +  INSTPM +  CACHE_MODE_0 +  CACHE_MODE_1 +  MI_ARB_STATE +  3D Pipeline Statistics Registers + +The graphics device supports both a hardware context and logical contexts. The multiple logical context +support provides robust rendering context support by swapping contexts to/from memory. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 57 + 5.8.1 Multiple Logical Rendering Contexts +The graphics device supports multiple logical renderingcontexts stored in Main Memory. Logical +rendering contexts are referenced via a 2KB-aligned LogicalContext Address. +The maximum size of a logical context entry (which is information required by the driver to allocate +contexts) is currently 2K bytes. For forward compatibility, the maximum size of a logical context entry +should be supplied to the drivers via a VBIOS mechanism as opposed to being hardcoded in the driver. +The actual size of a logical rendering context is the amount of data stored/restored during a context +switch and is measured in 64B cache lines. +The format of the logical rendering context in memory is considered device-dependent;software +must not attempt to modify the contents of a logical rendering context directly. This restriction is +motivated by forward compatibility concerns because the location and definition of fields may +change between implementations. + +5.8.1.1 Current Context IDs +The ring buffer has an associated Current Context ID (CCID) register. The CCID includes a Logical +Pipeline Context Address (LPCA). +The CCID for a ring buffer is set during the processing of the new MI_SET_CONTEXT command from +that ring. The MI_SET_CONTEXT command provides a new CCID value (LPCA) to be loaded into the +CCID register for the associated ring buffer. The MI_SET_CONTEXT command also contains a Restore +Inhibit bit used to optionally inhibit the restoration (loading) of the new rendering context. This bit must be +used during context initialization to avoid the loading of uninitialized (garbage) context data from memory. +Failure to do so leads to UNDEFINED operation. +The initial values of the CCIDs are UNDEFINED. The first time a valid CCID is set from a ring buffer, the +normal context save operation will be suppressed, as the previous CCID is invalid. + +5.8.1.2 Intra-Ring Context Switch +Within a specific ring buffer, a new logical rendering context is specified via the MI_SET_CONTEXT +command. Note that MI_SET_CONTEXT commands are permitted only within a ring buffer (not within a +batch buffer). +As part of the execution of the MI_SET_CONTEXT command from within a ring buffer, the Logical +Pipeline Context Address fields of the CCID register and MI_SET_CONTEXT command are compared. If +they differ (or the CCID register is uninitialized), a rendering context switch operation will be performed, +which includes: + 1. If the CCID contents are valid, a context save operation will be performed. The contents of the + HW context will be saved in memory starting at the Logical Pipeline Context Address specified + in the CCID. + 2. If the Restore Inhibit command field is not set, a context restore operation will be performed. + Here the logical context values are read starting from the Logical Pipeline Context Address field + of the command and used to set the internal HW context. + 3. The relevant contents of the command will be loaded into the appropriate CCID register. (This + occurs irrespective of the LPCA comparison result). At this point, the ring buffer has switched to + using the new logical rendering context. + + + + +58 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + 5.8.1.3 Logical Rendering Context Creation and Initialization + +5.8.1.3.1 Rendering Context Creation Rules + 1. Software only knows the size of the logical rendering context (2KB), for allocation purposes. + 2. Given (1), software does not know the format of the context, and therefore is not allowed to + write any portion of a logical rendering context. Software can, however, copy/move entire + logical context blocks. + 3. Given (2), software must never restore (load) a logical rendering context from memory that + has not been previously stored by HW. I.e., software must never attempt to initialize a context + itself and then cause it to be loaded. Breaking this rule causes UNDEFINED operation (as in + the hang seen in BDG validation). + 4. Initialization software must write all HW context variables with legal values before the first + rendering context can be saved (this must be done before you can perform any rendering + anyways). Given this, and the obvious rule that software must never program illegal state + values, guarantees that the HW context will forever remain valid (and therefore be available to + store into a logical rendering context). Note that software-visible context variables include 3D + state, Blt register state, etc. + +5.8.1.3.2 Context Initialization +Logical Rendering Contexts can be initialized (in memory) by software in the following way: + 1. Issue an MI_SET_CONTEXT command w/ the Restore Inhibit bit set and the about-to-be- + initialized logical pipeline context address. This will save the current rendering context and + then change the LPCA to the new context (without loading it). + 2. Use state commands to modify the context as desired. + 3. Issue another MI_SET_CONTEXT command specifying some other LPCA (e.g., the previous + one). This will cause the new context to be stored (initialized) in memory + +5.8.1.4 Context Save +A context save will occur anytime all of the following apply: + +  A rendering context switch occurs as a result of the execution of MI_SET_CONTEXT +  the CCID of the current context (CCID register of current ring) and the new CCID (the CCID register + of the newly selected ring or the new CCID in the MI_SET_CONTEXT command) differ OR an + MI_SET_CONTEXT with the “Force Restore” bit set initiated the context switch +  the current CCID is valid (has been previously set) + +The current rendering context will be written out to memory starting at the LPCA in the format described +by Logical Context Layout in Memory Data Formats. Note that this includes a limited number of Memory +Interface Registers whose values are saved by embedding them in an MI_LOAD_REGISTER_IMM +command that is written out to memory. +The Optional Extended Context will also be written if the Extended Save Enable bit is set in the current +CCID register. Context saves DO NOT modify pipelined state stored in memory. + + +5.9 Reset State +This section describes the state of the programming interface following a hardware reset. Refer to the +individual register definitions for details on reset (default) settings. + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 59 +  The settings of the hardware context state variables are UNDEFINED. Software must program all + state variables prior to their use in rendering. +  The ring buffer is disabled. +  All interrupts and error status bits are “masked” (disabled). All interrupts are disabled via IER. There + will be no HW activity to cause any hardware/interrupt status bits to be set. +  The Hardware Status Page is located at 1FFFF000h (though HW status writes are effectively + disabled) +  All FENCE registers are INVALID +  The GTT is disabled (accesses other than CPU reads, cursor and VGA reads will generate an error). +  All INSTDONE bits are set (“DONE”). +  The NOPID register is 0. +  All command groupings are enabled (via INSTPM) + + +5.10 Engine Idle +This section specifies when the command streamers specify to the Power Management function that the +command streamers and associated engines are IDLE. +A command streamer does not signal IDLE until the following conditions are true: + +  Any context that is not in the power context image has been saved, if the IDLE will enter the C6 + state. +  The associated engine is IDLE, which can be guaranteed by a flush of the engine. +  There is no pending work to be completed in the ring and the ring is enabled. +  There is an event that causes the engine to stall processing the next command in the ring, like + waiting for an event or for a semaphore (see the table below). + +Once all command streamers specify that their engines are IDLE, then Power Management may stop +clocks, lower voltages, or lower frequencies to save power. See the Power Management documentation +for more information. +The table below describes support for each type of wait by project: + +Wait Power Management Actions +Project Wait for Flip Wait for VBlank Wait for Scanline Wait for Semaphore + \ + Event Render Media/VE Blitter Render Media/VE Blitter Render Media/VE Blitter Render Media/VE Blitter + IVB RC6 NS RC6 RC6 NS NS RC6 NS NS BUSY RC6 RC6 +2 + Drivers can force engines to report IDLE through MMIO writes to Power Management. + + + + +60 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V1 Pt 2 – 05 12 6/12/2012 61 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol1_part3.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part3.txt new file mode 100644 index 0000000..9478779 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part3.txt @@ -0,0 +1,10018 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 1 Part 3: Graphics Core™ – Memory +Interface and Commands for the Render Engine +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 + Contents +1. Render Engine Command Streamer .................................................................................................... 4 + 1.1 Registers in Render Engine ................................................................................................................. 4 + 1.1.1 Introduction ..................................................................................................................................... 4 + 1.1.2 Outstanding Memory Requests Modulation Counters ................................................................... 6 + 1.1.3 Registers Used for Priority Field in Programmable Arbitration ....................................................... 9 + 1.1.4 Registers Used in Programmable Arbitration ............................................................................... 12 + 1.1.5 Virtual Memory Control ................................................................................................................. 29 + 1.1.6 GFX TLB In Use Virtual Address Registers ................................................................................. 34 + 1.1.7 GFX Pending TLB Cycles Information Registers ......................................................................... 39 + 1.1.8 Configuration Registers for Graphic Arbiter ................................................................................. 45 + 1.1.9 Context Save Registers ................................................................................................................ 47 + 1.1.10 Mode and Misc Ctrl Registers .................................................................................................... 54 + 1.1.11 RINGBUF — Ring Buffer Registers ........................................................................................... 75 + 1.1.12 Watchdog Timer Registers ......................................................................................................... 81 + 1.1.13 Interrupt Control Registers ......................................................................................................... 83 + 1.1.14 Logical Context Support ............................................................................................................. 89 + 1.1.15 Pipelines Statistics Counter Registers ..................................................................................... 101 + 1.1.16 Predicate Render Registers ..................................................................................................... 110 + 1.1.17 AUTO_DRAW Registers .......................................................................................................... 112 + 1.1.18 MMIO Registers for GPGPU Indirect Dispatch ........................................................................ 114 + 1.1.19 Memory Interface Registers ..................................................................................................... 117 + 1.2 Memory Interface Commands for Rendering Engine ...................................................................... 166 + 1.2.1 Introduction ................................................................................................................................. 166 + 1.2.2 Software Synchronization Commands ....................................................................................... 166 + 1.2.3 MI_ARB_CHECK ........................................................................................................................ 167 + 1.2.4 MI_ARB_ON_OFF ...................................................................................................................... 167 + 1.2.5 MI_BATCH_BUFFER_END ....................................................................................................... 168 + 1.2.6 MI_CONDITIONAL_BATCH_BUFFER_END ............................................................................. 168 + 1.2.7 MI_BATCH_BUFFER_START (Render) .................................................................................... 169 + 1.2.8 MI_CLFLUSH ............................................................................................................................. 173 + 1.2.9 MI_DISPLAY_FLIP ..................................................................................................................... 174 + 1.2.10 MI_FLUSH ................................................................................................................................ 176 + 1.2.11 MI_LOAD_REGISTER_IMM .................................................................................................... 178 + 1.2.12 MI_NOOP ................................................................................................................................. 180 + 1.2.13 Surface Probing ........................................................................................................................ 180 + 1.2.14 MI_REPORT_HEAD ................................................................................................................. 180 + 1.2.15 MI_SEMAPHORE_MBOX ........................................................................................................ 181 + 1.2.16 MI_SET_CONTEXT ................................................................................................................. 184 + 1.2.17 MI_STORE_DATA_IMM ........................................................................................................... 186 + 1.2.18 MI_STORE_DATA_INDEX ....................................................................................................... 187 + 1.2.19 MI_STORE_REGISTER_MEM ................................................................................................ 189 + 1.2.20 MI_SUSPEND_FLUSH ............................................................................................................ 190 + 1.2.21 MI_UPDATE_GTT .................................................................................................................... 191 + 1.2.22 MI_USER_INTERRUPT ........................................................................................................... 192 + 1.2.23 MI_WAIT_FOR_EVENT ........................................................................................................... 193 + 1.2.24 MI_LOAD_REGISTER_MEM ................................................................................................... 196 + 1.2.25 MI_URB_CLEAR ...................................................................................................................... 197 + 1.2.26 MI_PREDICATE ....................................................................................................................... 199 + 1.2.27 MI_TOPOLOGY_FILTER ......................................................................................................... 201 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 3 + 1. Render Engine Command Streamer +1.1 Registers in Render Engine + +1.1.1 Introduction +This chapter describes the memory-mapped registers associated with the Memory Interface, including +brief descriptions of their use. The functions performed by some of these registers are discussed in more +detail in the Memory Interface Functions, Memory Interface Instructions, and Programming Environment +chapters. +The registers detailed in this chapter are used across the family of products and are extentions to +previous projects. However, slight changes may be present in some registers (i.e., for features added or +removed), or some registers may be removed entirely. These changes are clearly marked within this +chapter. + +1.1.1.1 ARB_MODE – Arbiter Mode Control register + + ARB_MODE - Arbiter Mode Control register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Size (in bits): 32 +Trusted Type: 1 +Address: 04030h +DWord Bit Description +0 31:16 Mask Bits + Default Value: 00000000000000000b + Access: RO + Format: U16 + Mask bits act as write enables for the bits in the lower bits of this register + + 14 GAM to Bypass GTT Translation (GAM2BGTTT) + Default Value: 0b + Access: R/W + Format: MBZ + GAM to bypass GTT translation and pass logical addresses through with 0’s padded on the MSBs to + form the physical address. + + 13 DC GDR (DC_GDR) + Default Value: 0b + Access: R/W + DC GDR + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 4 + ARB_MODE - Arbiter Mode Control register + 12 HIZ GDR (HIZ_GDR) + Default Value: 0b + Access: R/W + HIZ GDR + + 11 STC GDR (STC_GDR) + Default Value: 0b + Access: R/W + Format: U1 + STC GDR + + 10 BLB GDR (STC_GDR) + Default Value: 0b + Access: R/W + BLB GDR + + 9 GAM PD GDR (GAMPD_GDR) + Default Value: 0b + Access: R/W + GAM PD GDR + + 8 Color/Depth Port Share Bit (CDPS) + Default Value: 00b + Access: R/W + Format: U1 + Color/Depth port share bit + This bit is used to force Color and Depth Caches to share an arbiter read request port. By default (Bit = + 0) the Color Cache will NOT share the read request port with the Depth Cache. + + 5 Address Swizzling for Tiled Surfaces (AS4TS) + Access: R/W + Format: U1 + Address Swizzling for Tiled-Surfaces. This register location is updated via GFX Driver prior to enabling + DRAM accesses. Driver needs to obtain the need for memory address swizzling via DRAM + configuration registers and set the following bits (in Display Engine and Render/Media access + streams). + Value Name + 0b No address Swizzling + 1b Address bit[6] needs to be swizzled for tiled surfaces + 4 VMC GDR Enable (VMC_GDR_EN) + Access: R/W + When this bit is set, Data requested from the VMC client will be generated by the GDR algorithm + + 3 Texture Cache GDR Enable bit (TCGDREN) + Access: R/W + Format: U1 + Texture Cache GDR enable bit When this bit is set, Data requested from the Texture Cache client will + be generated by the GDR algorithm (See GDR algorithm in xxx section) + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 5 + ARB_MODE - Arbiter Mode Control register + 2 Depth Cache GDR enable bit (DCGDREN) + Access: R/W + Format: U1 + When this bit is set, Data requested from the Depth Cache client will be generated by the GDR + algorithm (See GDR algorithm in xxx section) + + 1 Color Cache GDR enable bit(CCGDREN) + Access: R/W + Format: U1 + When this bit is set, Data requested from the Color Cache client will be generated by the GDR + algorithm (See GDR algorithm in xxx section) + + 0 GTT Accesses GDR (GTTAGDR ) + Default Value: 0b + Access: R/W + Format: U1 + When this bit is enabled along with the Client’s GDR bit, PPGTT and GGTT requests for this memory + access will also be tagged as GDR to SQ. + + + + +1.1.2 Outstanding Memory Requests Modulation Counters + +1.1.2.1 GFX_PEND_TLB_0 – Max Outstanding Pending TLB Requests 0 + + GFX_PEND_TLB_0 - Max Outstanding Pending TLB Requests 0 +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04034h-04037h + + +DWord Bit Description +0 31 TEX Limit Enable bit + Format: U1 + This bit is used to enable the pending TLB requests limitation function for the Texture Cache. When + set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + 30 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 6 + GFX_PEND_TLB_0 - Max Outstanding Pending TLB Requests 0 + 29:24 TEX TLB Limit Count + Format: U6 + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + 23 ISC Limit Enable bit + Format: U1 + This bit is used to enable the pending TLB requests limitation function for the Instruction Cache. When + set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + 22 Reserved + Format: MBZ + 21:16 ISC TLB Limit Count + Format: U6 + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + 15 VF Limit Enable bit + Format: U1 + This bit is used to enable the pending TLB requests limitation function for the Vertex Fetch. When set, + the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + 14 Reserved + Format: MBZ + 13:8 VF TLB Limit Count + Format: U6 + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + 7 CS Limit Enable bit + Format: U1 + This bit is used to enable the pending TLB requests limitation function for the Command Streamer. + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + 6 Reserved + Format: MBZ + 5:0 CS TLB Limit Count + Format: U6 + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 7 + 1.1.2.2 GFX_PEND_TLB_1 – Max Outstanding Pending TLB Requests 1 + + GFX_PEND_TLB_1 - Max Outstanding Pending TLB Requests 1 +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04038h-0403Bh + + +DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15 RCZ Limit Enable bit + Format: U1 + This bit is used to enable the pending TLB requests limitation function for the Render Depth Cache. + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + 14 Reserved + Format: MBZ + 13:8 RCZ TLB Limit Count + Format: U6 + This bit is used to enable the pending TLB requests limitation function for the Render Color Cache. + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + 7 RCC Limit Enable bit + Format: U1 + This bit is used to enable the pending TLB requests limitation function for the Render Color Cache. + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + 6 Reserved + Format: MBZ + 5:0 RCC TLB Limit Count + Format: U6 + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 8 + 1.1.3 Registers Used for Priority Field in Programmable Arbitration + +1.1.3.1 MIDARB_PRIO_HIT_REGISTER – Priority Field in Programmable + Arbitration for Hit + + MIDARB_PRIO_HIT_REGISTER - Priority Field in Programmable + Arbitration for Hit +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 16 +Trusted Type: 1 +Address: 043A0h + DWord Bit Description +0 31:12 Reserved + 11:9 Encoded Programmable Priority for MIDARB_GOTOFIELD_HIT3 Register + Encoding Priority 1 Priority 2 Priority 3 + 000 CS/VF/ISC MT/CTC RCC + 001 CS/VF/ISC RCC MT/CTC + 010 RCC CS/VF/ISC MT/CTC + 011 RCC MT/CTC CS/VF/ISC + 100 MT/CTC CS/VF/ISC RCC + 101 MT/CTC RCC CS/VF/ISC + 110 Reserved Reserved Reserved + 111 Reserved Reserved Reserved + 8:6 Encoded Programmable Priority for MIDARB_GOTOFIELD_HIT2 Register + 5:3 Encoded Programmable Priority for MIDARB_GOTOFIELD_HIT1 Register + 2:0 Encoded Programmable Priority for MIDARB_GOTOFIELD_HIT0 Register + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 9 + 1.1.3.2 MIDARB_PRIO_MISS_REGISTER – Priority Field in Programmable + Arbitration for Miss + + MIDARB_PRIO_MISS_REGISTER - Priority Field in Programmable + Arbitration for Miss +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04204h + DWord Bit Description +0 31:20 Reserved + 19:15 Encoded Programmable Priority for MIDARB_GOTOFIELD_MISS3 Register + 14:10 Encoded Programmable Priority for MIDARB_GOTOFIELD_MISS2 Register + 9:5 Encoded Programmable Priority for MIDARB_GOTOFIELD_MISS1 Register + 4:0 Encoded Programmable Priority for MIDARB_GOTOFIELD_MISS0 Register + + + +1.1.3.3 MIDARB_PRIO_NP_REGISTER – Priority Field in Programmable + Arbitration for Hit-NP + + MIDARB_PRIO_NP_REGISTER - Priority Field in Programmable + Arbitration for Hit-NP +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043A4h + + +Address: 04208h + + + DWord Bit Description +0 31:20 Reserved + 19:15 Encoded Programmable Priority for MIDARB_GOTOFIELD_MISS3 Register + Encoding Priority 1 Priority 2 Priority 3 Priority 4 + 00000 CS/VF/ISC MT_CTC RCC RCZ_HiZ_Stnc + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 10 + MIDARB_PRIO_NP_REGISTER - Priority Field in Programmable + Arbitration for Hit-NP + 00001 CS/VF/ISC RCC MT_CTC RCZ_HiZ_Stnc + 00010 RCC CS/VF/ISC MT_CTC RCZ_HiZ_Stnc + 00011 RCC MT_CTC CS/VF/ISC RCZ_HiZ_Stnc + 00100 MT_CTC CS/VF/ISC RCC RCZ_HiZ_Stnc + 00101 MT_CTC RCC CS/VF/ISC RCZ_HiZ_Stnc + 01000 CS/VF/ISC MT_CTC RCZ_HiZ_Stnc RCC + 01001 CS/VF/ISC RCC RCZ_HiZ_Stnc MT_CTC + 01010 RCC CS/VF/ISC RCZ_HiZ_Stnc MT_CTC + 01011 RCC MT_CTC RCZ_HiZ_Stnc CS/VF/ISC + 01100 MT_CTC CS/VF/ISC RCZ_HiZ_Stnc RCC + 01101 MT_CTC RCC RCZ_HiZ_Stnc CS/VF/ISC + 10000 CS/VF/ISC RCZ_HiZ_Stnc MT_CTC RCC + 10001 CS/VF/ISC RCZ_HiZ_Stnc RCC MT_CTC + 10010 RCC RCZ_HiZ_Stnc CS/VF/ISC MT_CTC + 10011 RCC RCZ_HiZ_Stnc MT_CTC CS/VF/ISC + 10100 MT_CTC RCZ_HiZ_Stnc CS/VF/ISC RCC + 10101 MT_CTC RCZ_HiZ_Stnc RCC CS/VF/ISC + 11000 RCZ_HiZ_Stnc CS/VF/ISC MT_CTC RCC + 11001 RCZ_HiZ_Stnc CS/VF/ISC RCC MT_CTC + 11010 RCZ_HiZ_Stnc RCC CS/VF/ISC MT_CTC + 11011 RCZ_HiZ_Stnc RCC MT_CTC CS/VF/ISC + 11100 RCZ_HiZ_Stnc MT_CTC CS/VF/ISC RCC + 11101 RCZ_HiZ_Stnc MT_CTC RCC CS/VF/ISC + Other values Reserved + 14:10 Encoded Programmable Priority for MIDARB_GOTOFIELD_NP2 Register + 9:5 Encoded Programmable Priority for MIDARB_GOTOFIELD_NP1 Register + 4:0 Encoded Programmable Priority for MIDARB_GOTOFIELD_NP0 Register + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 11 + 1.1.4 Registers Used in Programmable Arbitration + +1.1.4.1 MIDARB_GOTOFIELD_HIT0_REGISTER – Goto Field in Programmable + Arbitration for Hit0 + +MIDARB_GOTOFIELD_HIT0 - Goto Field in Programmable Arbitration + for Hit0 +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 16 +Trusted Type: 1 +Address: 043B0h + DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15:14 Goto field when request vector is 111 + Determines the GOTO and priority register to be used next: + Value Name Description + 00b Use MIDARB_GOTOFIELD_HIT0 and MIDARB_PRIO_HIT_REGISTER[2:0] + 01b Use MIDARB_GOTOFIELD_HIT1 and MIDARB_PRIO_HIT_REGISTER[5:3] + 10b Use MIDARB_GOTOFIELD_HIT2 and MIDARB_PRIO_HIT_REGISTER[8:6] + 11b Use MIDARB_GOTOFIELD_HIT3 and MIDARB_PRIO_HIT_REGISTER[11:9] + 13:12 Goto field when request vector is 110b. + 11:10 Goto field when request vector is 101b. + 9:8 Goto field when request vector is 100b. + 7:6 Goto field when request vector is 011b. + 5:4 Goto field when request vector is 010b. + 3:2 Goto field when request vector is 001b. + 1:0 Goto field when request vector is 000b. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 12 + 1.1.4.2 MIDARB_GOTOFIELD_HIT1_REGISTER – Goto Field in Programmable + Arbitration for Hit1 + +MIDARB_GOTOFIELD_HIT1 - Goto Field in Programmable Arbitration + for Hit1 +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 16 +Trusted Type: 1 +Address: 043B4h + DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15:14 Goto field when request vector is 111 + Determines the GOTO and priority register to be used next + Value Name Description + 00b Use MIDARB_GOTOFIELD_HIT0 and MIDARB_PRIO_HIT_REGISTER[2:0] + 01b Use MIDARB_GOTOFIELD_HIT1 and MIDARB_PRIO_HIT_REGISTER[5:3] + 10b Use MIDARB_GOTOFIELD_HIT2 and MIDARB_PRIO_HIT_REGISTER[8:6] + 11b Use MIDARB_GOTOFIELD_HIT3 and MIDARB_PRIO_HIT_REGISTER[11:9] + 13:12 Goto field when request vector is 110b. + 11:10 Goto field when request vector is 101b. + 9:8 Goto field when request vector is 100b. + 7:6 Goto field when request vector is 011b. + 5:4 Goto field when request vector is 010b. + 3:2 Goto field when request vector is 001b. + 1:0 Goto field when request vector is 000b. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 13 + 1.1.4.3 MIDARB_GOTOFIELD_HIT2_REGISTER – Goto Field in Programmable + Arbitration for Hit2 + +MIDARB_GOTOFIELD_HIT2 - Goto Field in Programmable Arbitration + for Hit2 +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 16 +Trusted Type: 1 +Address: 043B8h + DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15:14 Goto field when request vector is 111. + Determines the GOTO and priority register to be used next + Value Name Description + 00b Use MIDARB_GOTOFIELD_HIT0 and MIDARB_PRIO_HIT_REGISTER[2:0] + 01b Use MIDARB_GOTOFIELD_HIT1 and MIDARB_PRIO_HIT_REGISTER[5:3] + 10b Use MIDARB_GOTOFIELD_HIT2 and MIDARB_PRIO_HIT_REGISTER[8:6] + 11b Use MIDARB_GOTOFIELD_HIT3 and MIDARB_PRIO_HIT_REGISTER[11:9] + 13:12 Goto field when request vector is 110b. + 11:10 Goto field when request vector is 101b. + 9:8 Goto field when request vector is 100b. + 7:6 Goto field when request vector is 011b. + 5:4 Goto field when request vector is 010b. + 3:2 Goto field when request vector is 001b. + 1:0 Goto field when request vector is 000b. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 14 + 1.1.4.4 MIDARB_GOTOFIELD_HIT3_REGISTER – Goto Field in Programmable + Arbitration for Hit3 + +MIDARB_GOTOFIELD_HIT3 - Goto Field in Programmable Arbitration + for Hit3 +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 16 +Trusted Type: 1 +Address: 043BCh + DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15:14 Goto field when request vector is 111. + Determines the GOTO and priority register to be used next. + Field for arbitration on next clock cycle for request entries of 111 corresponding to arbitration + action field entry of MIDARB_PRIO_HIT_REGISTER[11:9] + Value Name Description + 00b Use MIDARB_GOTOFIELD_HIT0 and MIDARB_PRIO_HIT_REGISTER[2:0] + 01b Use MIDARB_GOTOFIELD_HIT1 and MIDARB_PRIO_HIT_REGISTER[5:3] + 10b Use MIDARB_GOTOFIELD_HIT2 and MIDARB_PRIO_HIT_REGISTER[8:6] + 11b Use MIDARB_GOTOFIELD_HIT3 and MIDARB_PRIO_HIT_REGISTER[11:9] + 13:12 Goto field when request vector is 110. + Field for arbitration on next clock cycle for request entries of 110 corresponding to arbitration + action field entry of MIDARB_PRIO_HIT_REGISTER[11:9] + 11:10 Goto field when request vector is 101. + Field for arbitration on next clock cycle for request entries of 101 corresponding to arbitration + action field entry of MIDARB_PRIO_HIT_REGISTER[11:9] + 9:8 Goto field when request vector is 100. + Field for arbitration on next clock cycle for request entries of 100 corresponding to arbitration + action field entry of MIDARB_PRIO_HIT_REGISTER[11:9] + 7:6 Goto field when request vector is 011. + Field for arbitration on next clock cycle for request entries of 011 corresponding to arbitration + action field entry of MIDARB_PRIO_HIT_REGISTER[11:9] + 5:4 Goto field when request vector is 010. + Field for arbitration on next clock cycle for request entries of 010 corresponding to arbitration + action field entry of MIDARB_PRIO_HIT_REGISTER[11:9] + 3:2 Goto field when request vector is 001. + Field for arbitration on next clock cycle for request entries of 001 corresponding to arbitration + action field entry of MIDARB_PRIO_HIT_REGISTER[11:9] + 1:0 Goto field when request vector is 000. + Field for arbitration on next clock cycle for request entries of 000 corresponding to arbitration + action field entry of MIDARB_PRIO_HIT_REGISTER[11:9] + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 15 + 1.1.4.5 MIDARB_GOTOFIELD_NP0_REGISTER – Goto Field in Programmable + Arbitration for Hit-NP0 + +MIDARB_GOTOFIELD_NP0 - Goto Field in Programmable Arbitration + for Hit-NP0 +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043C0h + DWord Bit Description +0 31:30 Goto field when request vector is 1111. + Determines the GOTO and priority register to be used next. + Value Name Description + 00b Use MIDARB_GOTOFIELD_NP0 and MIDARB_PRIO_NP_REGISTER[4:0] + 01b Use MIDARB_GOTOFIELD_NP1 and MIDARB_PRIO_NP_REGISTER[9:5] + 10b Use MIDARB_GOTOFIELD_NP2 and MIDARB_PRIO_NP_REGISTER[14:10] + 11b Use MIDARB_GOTOFIELD_NP3 and MIDARB_PRIO_NP_REGISTER[19:15] + 29:28 Goto field when request vector is 1110b. + 27:26 Goto field when request vector is 1101b. + 25:24 Goto field when request vector is 1100b. + 23:22 Goto field when request vector is 1011b. + 21:20 Goto field when request vector is 1010b. + 19:18 Goto field when request vector is 1001b. + 17:16 Goto field when request vector is 1000b. + 15:14 Goto field when request vector is 0111b. + 13:12 Goto field when request vector is 0110b. + 11:10 Goto field when request vector is 0101b. + 9:8 Goto field when request vector is 0100b. + 7:6 Goto field when request vector is 0011b. + 5:4 Goto field when request vector is 0010b. + 3:2 Goto field when request vector is 0001b. + 1:0 Goto field when request vector is 0000b. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 16 + 1.1.4.6 MIDARB_GOTOFIELD_NP1_REGISTER – Goto Field in Programmable + Arbitration for Hit-NP1 + +MIDARB_GOTOFIELD_NP1 - Goto Field in Programmable Arbitration + for Hit-NP1 +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043C4h + DWord Bit Description +0 31:30 Goto field when request vector is 1111. + Determines the GOTO and priority register to be used next. + Value Name Description + 00b Use MIDARB_GOTOFIELD_NP0 and MIDARB_PRIO_NP_REGISTER[4:0] + 01b Use MIDARB_GOTOFIELD_NP1 and MIDARB_PRIO_NP_REGISTER[9:5] + 10b Use MIDARB_GOTOFIELD_NP2 and MIDARB_PRIO_NP_REGISTER[14:10] + 11b Use MIDARB_GOTOFIELD_NP3 and MIDARB_PRIO_NP_REGISTER[19:15] + 29:28 Goto field when request vector is 1110b. + 27:26 Goto field when request vector is 1101b. + 25:24 Goto field when request vector is 1100b. + 23:22 Goto field when request vector is 1011b. + 21:20 Goto field when request vector is 1010b. + 19:18 Goto field when request vector is 1001b. + 17:16 Goto field when request vector is 1000b. + 15:14 Goto field when request vector is 0111b. + 13:12 Goto field when request vector is 0110b. + 11:10 Goto field when request vector is 0101b. + 9:8 Goto field when request vector is 0100b. + 7:6 Goto field when request vector is 0011b. + 5:4 Goto field when request vector is 0010b. + 3:2 Goto field when request vector is 0001b. + 1:0 Goto field when request vector is 0000b. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 17 + 1.1.4.7 MIDARB_GOTOFIELD_NP2_REGISTER – Goto Field in Programmable + Arbitration for Hit-NP2 + +MIDARB_GOTOFIELD_NP2 - Goto Field in Programmable Arbitration + for Hit-NP2 +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043C8h + DWord Bit Description +0 31:30 Goto field when request vector is 1111. + Determines the GOTO and priority register to be used next. + Value Name Description + 00b Use MIDARB_GOTOFIELD_NP0 and MIDARB_PRIO_NP_REGISTER[4:0] + 01b Use MIDARB_GOTOFIELD_NP1 and MIDARB_PRIO_NP_REGISTER[9:5] + 10b Use MIDARB_GOTOFIELD_NP2 and MIDARB_PRIO_NP_REGISTER[14:10] + 11b Use MIDARB_GOTOFIELD_NP3 and MIDARB_PRIO_NP_REGISTER[19:15] + 29:28 Goto field when request vector is 1110b. + 27:26 Goto field when request vector is 1101b. + 25:24 Goto field when request vector is 1100b. + 23:22 Goto field when request vector is 1011b. + 21:20 Goto field when request vector is 1010b. + 19:18 Goto field when request vector is 1001b. + 17:16 Goto field when request vector is 1000b. + 15:14 Goto field when request vector is 0111b. + 13:12 Goto field when request vector is 0110b. + 11:10 Goto field when request vector is 0101b. + 9:8 Goto field when request vector is 0100b. + 7:6 Goto field when request vector is 0011b. + 5:4 Goto field when request vector is 0010b. + 3:2 Goto field when request vector is 0001b. + 1:0 Goto field when request vector is 0000b. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 18 + 1.1.4.8 MIDARB_GOTOFIELD_NP3_REGISTER – Goto Field in Programmable + Arbitration for Hit-NP3 + +MIDARB_GOTOFIELD_NP3 - Goto Field in Programmable Arbitration + for Hit-NP3 +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043CCh + DWord Bit Description +0 31:30 Goto field when request vector is 1111. + Determines the GOTO and priority register to be used next. + Value Name Description + 00b Use MIDARB_GOTOFIELD_NP0 and MIDARB_PRIO_NP_REGISTER[4:0] + 01b Use MIDARB_GOTOFIELD_NP1 and MIDARB_PRIO_NP_REGISTER[9:5] + 10b Use MIDARB_GOTOFIELD_NP2 and MIDARB_PRIO_NP_REGISTER[14:10] + 11b Use MIDARB_GOTOFIELD_NP3 and MIDARB_PRIO_NP_REGISTER[19:15] + 29:28 Goto field when request vector is 1110b. + 27:26 Goto field when request vector is 1101b. + 25:24 Goto field when request vector is 1100b. + 23:22 Goto field when request vector is 1011b. + 21:20 Goto field when request vector is 1010b. + 19:18 Goto field when request vector is 1001b. + 17:16 Goto field when request vector is 1000b. + 15:14 Goto field when request vector is 0111b. + 13:12 Goto field when request vector is 0110b. + 11:10 Goto field when request vector is 0101b. + 9:8 Goto field when request vector is 0100b. + 7:6 Goto field when request vector is 0011b. + 5:4 Goto field when request vector is 0010b. + 3:2 Goto field when request vector is 0001b. + 1:0 Goto field when request vector is 0000b. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 19 + 1.1.4.9 ARB_GAC_GAM_REQCNTS0 – GAC_GAM Arbitration Counters + Register 0 + + ARB_GAC_GAM_REQCNTS0 - GAC_GAM Arbitration Counters + Register 0 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043A8h + DWord Bit Description +0 31:22 Reserved + 21:16 Number of GAC WR requests to be accumulated before applying the arbitration + 15:14 Reserved + 13:8 Number of GAC R requests to be accumulated before applying the arbitration + 7:6 Reserved + 5:0 Number of GAC RO requests to be accumulated before applying the arbitration + + + +1.1.4.10 ARB_GAC_GAM_REQCNTS1 – GAC_GAM Arbitration Counters + Register 1 + + ARB_GAC_GAM_REQCNTS1 - GAC_GAM Arbitration Counters + Register 1 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043ACh + DWord Bit Description +0 31:22 Reserved + 21:16 Number of GAC WR requests to be accumulated before applying the arbitration + 15:14 Reserved + 13:8 Number of GAC R requests to be accumulated before applying the arbitration + 7:6 Reserved + 5:0 Number of GAC RO requests to be accumulated before applying the arbitration + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 20 + 1.1.4.11 ARB_RO_GAC_GAM0 – GAC_GAM RO Arbitration Register 0 + + ARB_RO_GAC_GAM0 - GAC_GAM RO Arbitration Register 0 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043D0h + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 1 + 26:24 Goto field for entry 1 when request vector is 11b + 23:21 Goto field for entry 1 when request vector is 10b + 20:18 Goto field for entry 1 when request vector is 01b + 17:15 Goto field for entry 1 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 01 + 11:9 Goto field for entry 01 when request vector is 11b + 8:6 Goto field for entry 01 when request vector is 10b + 5:3 Goto field for entry 01 when request vector is 01b + 2:0 Goto field for entry 01 when request vector is 00b + + + +1.1.4.12 ARB_RO_GAC_GAM1 – GAC_GAM RO Arbitration Register 1 + + ARB_RO_GAC_GAM1 - GAC_GAM RO Arbitration Register 1 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043D4h + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 3 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 21 + ARB_RO_GAC_GAM1 - GAC_GAM RO Arbitration Register 1 + 26:24 Goto field for entry 3 when request vector is 11b + 23:21 Goto field for entry 3 when request vector is 10b + 20:18 Goto field for entry 3 when request vector is 01b + 17:15 Goto field for entry 3 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 2 + 11:9 Goto field for entry 2 when request vector is 11b + 8:6 Goto field for entry 2 when request vector is 10b + 5:3 Goto field for entry 2 when request vector is 01b + 2:0 Goto field for entry 2 when request vector is 00b + + + +1.1.4.13 ARB_RO_GAC_GAM2 – GAC_GAM RO Arbitration Register 2 + + ARB_RO_GAC_GAM2 - GAC_GAM RO Arbitration Register 2 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043D8h + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 5 + 26:24 Goto field for entry 5 when request vector is 11b + 23:21 Goto field for entry 5 when request vector is 10b + 20:18 Goto field for entry 5 when request vector is 01b + 17:15 Goto field for entry 5 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 4 + 11:9 Goto field for entry 4 when request vector is 11b + 8:6 Goto field for entry 4 when request vector is 10b + 5:3 Goto field for entry 4 when request vector is 01b + 2:0 Goto field for entry 4 when request vector is 00b + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 22 + 1.1.4.14 ARB_RO_GAC_GAM3 – GAC_GAM RO Arbitration Register 3 + + ARB_RO_GAC_GAM3 - GAC_GAM RO Arbitration Register 3 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043DCh + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 7 + 26:24 Goto field for entry 7 when request vector is 11b + 23:21 Goto field for entry 7 when request vector is 10b + 20:18 Goto field for entry 7 when request vector is 01b + 17:15 Goto field for entry 7 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 6 + 11:9 Goto field for entry 6 when request vector is 11b + 8:6 Goto field for entry 6 when request vector is 10b + 5:3 Goto field for entry 6 when request vector is 01b + 2:0 Goto field for entry 6 when request vector is 00b + + + +1.1.4.15 ARB_R_GAC_GAM0 – GAC_GAM R Arbitration Register 0 + + ARB_R_GAC_GAM0 - GAC_GAM R Arbitration Register 0 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043E0h + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 1 + 26:24 Goto field for entry 1 when request vector is 11b + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 23 + ARB_R_GAC_GAM0 - GAC_GAM R Arbitration Register 0 + 23:21 Goto field for entry 1 when request vector is 10b + 20:18 Goto field for entry 1 when request vector is 01b + 17:15 Goto field for entry 1 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 0 + 11:9 Goto field for entry 0 when request vector is 11b + 8:6 Goto field for entry 0 when request vector is 10b + 5:3 Goto field for entry 0 when request vector is 01b + 2:0 Goto field for entry 0 when request vector is 00b + + + +1.1.4.16 ARB_R_GAC_GAM1 – GAC_GAM R Arbitration Register 1 + + ARB_R_GAC_GAM1 - GAC_GAM R Arbitration Register 1 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043E4h + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 3 + 26:24 Goto field for entry 3 when request vector is 11b + 23:21 Goto field for entry 3 when request vector is 10b + 20:18 Goto field for entry 3 when request vector is 01b + 17:15 Goto field for entry 3 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 2 + 11:9 Goto field for entry 2 when request vector is 11b + 8:6 Goto field for entry 2 when request vector is 10b + 5:3 Goto field for entry 2 when request vector is 01b + 2:0 Goto field for entry 2 when request vector is 00b + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 24 + 1.1.4.17 ARB_R_GAC_GAM2 – GAC_GAM R Arbitration Register 2 + + ARB_R_GAC_GAM2 - GAC_GAM R Arbitration Register 2 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043E8h + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 5 + 26:24 Goto field for entry 5 when request vector is 11b + 23:21 Goto field for entry 5 when request vector is 10b + 20:18 Goto field for entry 5 when request vector is 01b + 17:15 Goto field for entry 5 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 4 + 11:9 Goto field for entry 4 when request vector is 11b + 8:6 Goto field for entry 4 when request vector is 10b + 5:3 Goto field for entry 4 when request vector is 01b + 2:0 Goto field for entry 4 when request vector is 00b + + + +1.1.4.18 ARB_R_GAC_GAM3 – GAC_GAM R Arbitration Register 3 + + ARB_R_GAC_GAM3 - GAC_GAM R Arbitration Register 3 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043ECh + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 7 + 26:24 Goto field for entry 7 when request vector is 11b + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 25 + ARB_R_GAC_GAM3 - GAC_GAM R Arbitration Register 3 + 23:21 Goto field for entry 7 when request vector is 10b + 20:18 Goto field for entry 7 when request vector is 01b + 17:15 Goto field for entry 7 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 6 + 11:9 Goto field for entry 6 when request vector is 11b + 8:6 Goto field for entry 6 when request vector is 10b + 5:3 Goto field for entry 6 when request vector is 01b + 2:0 Goto field for entry 6 when request vector is 00b + + + +1.1.4.19 ARB_WR_GAC_GAM0 – GAC_GAM WR Arbitration Register 0 + + ARB_WR_GAC_GAM0 - GAC_GAM WR Arbitration Register 0 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043F0h + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 1 + 26:24 Goto field for entry 1 when request vector is 11b + 23:21 Goto field for entry 1 when request vector is 10b + 20:18 Goto field for entry 1 when request vector is 01b + 17:15 Goto field for entry 1 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 0 + 11:9 Goto field for entry 0 when request vector is 11b + 8:6 Goto field for entry 0 when request vector is 10b + 5:3 Goto field for entry 0 when request vector is 01b + 2:0 Goto field for entry 0 when request vector is 00b + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 26 + 1.1.4.20 ARB_WR_GAC_GAM1 – GAC_GAM WR Arbitration Register 1 + + ARB_WR_GAC_GAM1 - GAC_GAM WR Arbitration Register 1 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043F4h + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 3 + 26:24 Goto field for entry 3 when request vector is 11b + 23:21 Goto field for entry 3 when request vector is 10b + 20:18 Goto field for entry 3 when request vector is 01b + 17:15 Goto field for entry 3 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 2 + 11:9 Goto field for entry 2 when request vector is 11b + 8:6 Goto field for entry 2 when request vector is 10b + 5:3 Goto field for entry 2 when request vector is 01b + 2:0 Goto field for entry 2 when request vector is 00b + + + +1.1.4.21 ARB_WR_GAC_GAM2 – GAC_GAM WR Arbitration Register 2 + + ARB_WR_GAC_GAM2 - GAC_GAM WR Arbitration Register 2 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043F8h + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 5 + 26:24 Goto field for entry 5 when request vector is 11b + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 27 + ARB_WR_GAC_GAM2 - GAC_GAM WR Arbitration Register 2 + 23:21 Goto field for entry 5 when request vector is 10b + 20:18 Goto field for entry 5 when request vector is 01b + 17:15 Goto field for entry 5 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 4 + 11:9 Goto field for entry 4 when request vector is 11b + 8:6 Goto field for entry 4 when request vector is 10b + 5:3 Goto field for entry 4 when request vector is 01b + 2:0 Goto field for entry 4 when request vector is 00b + + + +1.1.4.22 ARB_WR_GAC_GAM3 – GAC_GAM WR Arbitration Register 3 + + ARB_WR_GAC_GAM3 - GAC_GAM WR Arbitration Register 3 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 043FCh + DWord Bit Description +0 31:28 Reserved + 27 Priority for entry 7 + 26:24 Goto field for entry 7 when request vector is 11b + 23:21 Goto field for entry 7 when request vector is 10b + 20:18 Goto field for entry 7 when request vector is 01b + 17:15 Goto field for entry 7 when request vector is 00b + 14:13 Reserved + 12 Priority for entry 6 + 11:9 Goto field for entry 6 when request vector is 11b + 8:6 Goto field for entry 6 when request vector is 10b + 5:3 Goto field for entry 6 when request vector is 01b + 2:0 Goto field for entry 6 when request vector is 00b + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 28 + 1.1.5 Virtual Memory Control + +1.1.5.1 HWS_PGA — Hardware Status Page Address Register +Programming Note: If this register is written, a workload must subsequently be dispatched to the render +command streamer. + + HWS_PGA - Hardware Status Page Address Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04080h + + + + This register is used to program the 4 KB-aligned System Memory address of the Hardware Status Page used to + report hardware status into (typically cacheable) System Memory. + Programming Notes Project +If this register is written, a workload must subsequently be dispatched to the Render command streamer. +DWord Bit Description +0 31:12 Address + Format: GraphicsAddress[31:12] + This field is used by SW to specify Bits 31:12 of the 4 KB-aligned System Memory address of the 4 KB + page known as the Hardware Status Page. The Global GTT is used to map this page from the graphics + virtual address to physical address. + Programming Notes + If the Per-Process Virtual Address Space and Exec List Enable bit is set, HW requires that the status + page is programmed to allow for the context switch status to be reported. + 11:0 Reserved + Format: MBZ + + + +The following table defines the layout of the Hardware Status Page: + + Hardware Status Page Layout + +Source: RenderCS +Default 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 29 + Hardware Status Page Layout + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 30 + Hardware Status Page Layout + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 31 + Hardware Status Page Layout + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000 + DWord Bit Description +0 31:0 Interrupt Status Register Storage + Project: All + The content of the ISR register is written to this location whenever an “unmasked” bit of the ISR (as + determined by the HWSTAM register) changes state. + +1..3 31:0 Reserved + Project: All + Must not be used. + +4 31:0 Ring Head Pointer Storage + Project: All + The contents of the Ring Buffer Head Pointer register (register DWord 1) are written to this location + either as result of an MI_REPORT_HEAD instruction or as the result of an “automatic report” (see + RINGBUF registers). + +5..15 31:0 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 32 + Hardware Status Page Layout + Must not be used. + +16..27 31:0 Context Status DWords + Project: All +28..30 31:0 Reserved + Project: All + Must not be used. + +31 31:0 Last Written Status Offset + Project: All +32..1023 31:0 General Purpose + Project: All + These locations can be used for general purpose via the MI_STORE_DATA_INDEX or + MI_STORE_DATA_IMM instructions. + + + + +1.1.5.2 PP_DCLV – PPGTT Directory Cacheline Valid Register + + PP_DCLV - PPGTT Directory Cacheline Valid Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Size (in bits): 64 +Address: 02220h + Description Project +Access: R/W + + This register controls update of the on-chip PPGTT Directory Cache during a context restore. Bits that are + set will trigger the load of the corresponding 16 directory entry group. This register is restored with context + (prior to restoring the on-chip directory cache itself). This register is also restored when switching to a + context whose LRCA matches the current CCID if the Force PD Restore bit is set in the context descriptor. + + The context image of this register must be updated and maintained by SW; SW should not normally need to + read this register. + + This register can also effectively be used to limit the size of a process's virtual address space. Any access + by a process that requires a PD entry in a set that is not enabled in this register will cause a fatal error, and + no fetch of the PD entry will be attempted. + Programming Notes Project +Page Directory Base Register is a Global Context Register (power context) and not maintained per context in +ring buffer mode of submission. One should explicitly load PP_DCLV followed by PP_DIR_BASE register +through Load Register Immediate commands in Ring Buffer before submitting a context. One should +program these registers after ensuring the pipe is completely flushed with TLB’s invalidated. + DWord Bit Description +0 63:32 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 33 + PP_DCLV - PPGTT Directory Cacheline Valid Register + Format: MBZ + 31:0 PPGTT Directory Cache Restore [1..32] 16 entries + Project: All + Format: BitMask[Enable] + If set, the [1st..32nd] 16 entries of the directory cache are considered valid and will be brought in on + context restore. If clear, these entries are considered invalid and fetch of these entries will not be + attempted. + + + + +1.1.6 GFX TLB In Use Virtual Address Registers + +1.1.6.1 MTTLB_VA — MT Virtual Page Address Registers + + MTTLB_VA - MT Virtual Page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 04800h-048FCh + DWord Bit Description +0 31:12 Address + Format: GraphicsAddress[31:12] + Page virtual address. + + 11:0 Reserved + + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 34 + 1.1.6.2 MTTLB_VLD — Valid Bit Vector 0 for MTTLB + + MTTLB_VLD0 - Valid Bit Vector 0 for MTTLB +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 04780h-04783h +This register contains the valid bits for entries 0-31 of MTTLB (Texture and constant cache TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + +1.1.6.3 MTTLB_VLD — Valid Bit Vector 1 for MTTLB + + MTTLB_VLD1 - Valid Bit Vector 1 for MTTLB +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 04784h-04787h +This register contains the valid bits for entries 0-31 of MTTLB (Texture and constant cache TLBVertex Fetch, +Instruction Cache, and Command Streamer TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 35 + 1.1.6.4 VICTLB_VA — VIC Virtual page Address Registers + + VICTLB_VA - VIC Virtual page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 04900h-049FCh +These registers are directly mapped to the current Virtual Addresses in the VICTLB (Vertex Fetch, Instruction Cache, +and Command Streamer TLB.) + DWord Bit Description +0 31:12 Address + Format: GraphicsAddress[31:12] + Page virtual address. + + 11:0 Reserved + Format: MBZ + + + +1.1.6.5 VICTLB_VLD — Valid Bit Vector 0 for MTVICTLB + + VICTLB_VLD0 - Valid Bit Vector 0 for MTVICTLB +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 04788h-0478Bh +This register contains the valid bits for entries 0-31 of VICTLB (Vertex Fetch, Instruction Cache, and Command +Streamer TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 36 + 1.1.6.6 VICTLB_VLD — Valid Bit Vector 1 for MTVICTLB + + MTVICTLB_VLD1 - Valid Bit Vector 1 for MTVICTLB +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 0478Ch-0478Fh +This register contains the valid bits for entries 0-31 of VICTLB (Vertex Fetch, Instruction Cache, and Command +Streamer TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + +1.1.6.7 RCCTLB_VA — Virtual page Address Registers + + RCCTLB_VA - RCC Virtual page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 04A00h-04AFCh +These registers are directly mapped to the current Virtual Addresses in the RCCTLB (Render Cache for Color TLB). + DWord Bit Description +0 31:12 Address + Project: All + Format: GraphicsAddress[31:12] + Page virtual address. + + 11:0 Reserved + + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 37 + 1.1.6.8 RCCTLB_VLD — Valid Bit Vector 0 for RCCTLB + + RCCTLB_VLD0 - Valid Bit Vector 0 for RCCTLB +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 04790h-04793h +This register contains the valid bits for entries 0-31 of RCCTLB (Render Cache for Color TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + +1.1.6.9 RCZTLB_VA — RCZ Virtual Page Address Registers + + RCZTLB_VA - RCZ Virtual Page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 04B00h-04BFCh +These registers are directly mapped to the current Virtual Addresses in the RCZTLB (Render Cache for Z (Depth), Hi +Z, and Stencil TLB). + DWord Bit Description +0 31:12 Address + Format: GraphicsAddress[31:12] + Page virtual address. + + 11:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 38 + 1.1.6.10 RCZTLB_VLD0 — Valid Bit Vector 0 for RCZTLB + + RCZTLB_VLD0 - Valid Bit Vector 0 for RCZTLB +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 04798h-0479Bh +This register contains the valid bits for entries 0-31 of RCZTLB (Render Cache for Z (Depth), Hi Z, and Stencil TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + +1.1.6.11 RCZTLB_VLD1 — Valid Bit Vector 1 for RCZTLB + + RCZTLB_VLD1 - Valid Bit Vector 1 for RCZTLB +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 0479Ch-0479Fh +This register contains the valid bits for entries 0-31 of RCZTLB (Render Cache for Z (Depth), Hi Z, and Stencil TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + + +1.1.7 GFX Pending TLB Cycles Information Registers +The following registers contain information about cycles that did not complete their TLB translation. +Information is organized as 64 entries, where each entry has a valid and ready bit, collapsed into +separate registers. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 39 + 1.1.7.1 TLBPEND_VLD0 - Valid Bit Vector 0 for TLBPEND Registers + + TLBPEND_VLD0 - Valid Bit Vector 0 for TLBPEND registers +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04700h-04703h +This register contains the valid bits for entries 0-31 of TLBPEND structure (Cycles pending TLB translation). + DWord Bit Description +0 31:0 Valid bits per entry + + + +1.1.7.2 TLBPEND_VLD1 - Valid Bit Vector 1 for TLBPEND Registers + + TLBPEND_VLD1 - Valid Bit Vector 1 for TLBPEND registers +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04704h-04707h +This register contains the valid bits for entries 32-63 of TLBPEND structure (Cycles pending TLB translation). + DWord Bit Description +0 31:0 Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 40 + 1.1.7.3 TLBPEND_RDY0 - Ready Bit Vector 0 for TLBPEND Registers + + TLBPEND_RDY0 - Ready Bit Vector 0 for TLBPEND registers +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04708h-0470Bh +This register contains the ready bits for entries 0-31 of TLBPEND structure (Cycles pending TLB translation). + DWord Bit Description +0 31:0 Ready bits per entry + + + +1.1.7.4 TLBPEND_RDY1 - Ready Bit Vector 1 for TLBPEND Registers + + TLBPEND_RDY1 - Ready Bit Vector 1 for TLBPEND registers +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 0470Ch-0470Fh +This register contains the ready bits for entries 32-63 of TLBPEND structure (Cycles pending TLB translation). + DWord Bit Description +0 31:0 Ready bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 41 + 1.1.7.5 TLBPEND_SEC0 — Section 0 of TLBPEND Entry + + TLBPEND_SEC0 - Section 0 of TLBPEND Entry +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04400h-044FCh +This register is directly mapped to the TLBPEND Array in the Graphic Arbiter. +DWord Bit Description +0 31 vtstatus + This bit will be used in conjunction with the ready bit to determine the stage of the translation. See table + below. + 30:28 GTT bits + Bits 3:1 of the GTT entry used to translate the Virtual Address. 000 if translation is pending. + 27:0 Current address + The value of this field depends on the stage of the TLB translation for this entry: VA – bits 27:20 = 00, + bits 19:0 = Bits 31:12 of the Virtual Address of the cycle. + + + +VTDMODE Valid Ready Vtstatus + Meaning + +DC 0 DC + DC Entry is invalid +0 1 0 0 Entry was a TLB miss. Waiting for TLB translation. +0 1 0 1 + Entry was a Hit not present. Waiting for TLB translation from a previous miss. + +0 1 1 0 Not possible +0 1 1 1 TLB translation complete. Entry ready +1 1 0 0 Entry was a TLB miss. Waiting for TLB translation. +1 1 0 1 + Entry was a Hit not present. Waiting for TLB translation from a previous miss. +1 1 1 0 GPA translation complete. Entry ready for VTD translation. +1 1 1 1 TLB translation complete. Entry ready + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 42 + 1.1.7.6 TLBPEND_SEC1 — Section 1 of TLBPEND entry + + TLBPEND_SEC1 - Section 1 of TLBPEND Entry +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04500h-045FCh +This register is directly mapped to the current Virtual Addresses in the MTTLB (Texture and constant cache +TLBRender Cache for Z (Depth), Hi Z, and Stencil TLB). +DWord Bit Description +0 31:28 Current address + Bits 9:6 of the Virtual Address of the cycle. + 27:24 Cacheability Control Bits + + Bits 3:1 of the GTT entry used to translate the Virtual Address. 000 if translation is pending. + + 3 + + 2 Graphics Data Type (GFDT). This field contains the GFDT bit for this surface when writes occur. + GFDT can also be set by the GTT. The effective GFDT is the logical OR of this field with the GFDT + from the GTT entry. This field is ignored for reads. + + 1:0 Cacheability Control. This field controls cacheability in the mid-level cache (MLC) and last-level + cache (LLC). + + 00: use cacheability control bits from GTT entry + + 01: data is not cached in LLC or MLC + + 10: data is cached in LLC but not MLC + + 11: data is cached in both LLC and MLC + 23 ZLR bit + Flag to indicate this is a zero length read, a read used to calculate a physical address for a write. + 22:4 TAG + Cycle identification TAG. + 3:0 SRC ID + Encoding of unit generating this cycle . + Value Name + 0000b CS_RD_SRCID + 0001b VF_RD_SRCID + 0010b ISC_SRCID + 0011b MT_SRCID + 0100b RCC_SRCID + 0101b HZARB_SRCID + 0110b RCZ_SRCID + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 43 + TLBPEND_SEC1 - Section 1 of TLBPEND Entry + 0111b CTC_SRCID + 1000b CS_WR_SRCID + 1001b MBC_SRCID + 1010b Reserved + 1011b CS_RD_PWRCTX + 1100b RC_R4WRCMP + 1101b RESRVD2_SRCID + 1110b RESRVD1_SRCID + 1111b RESRVD0_SRCID + + + +1.1.7.7 TLBPEND_SEC2 — Section 2 of TLBPEND entry + + TLBPEND_SEC2 - Section 2 of TLBPEND Entry +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04600h-046FCh +This register is directly mapped to the current Virtual Addresses in the MTTLB (Texture and constant cache TLB). + DWord Bit Description +0 31:14 Reserved + 13 Big Page Attribute + This entry is using a 32K page. + 12:8 Current Address + Format: GraphicsAddress[14:10] + Bits 14:10 of the Virtual Address of the cycle. + + 7:0 PAT Entry + Location of Physical Address in Physical Address Table. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 44 + 1.1.8 Configuration Registers for Graphic Arbiter + +1.1.8.1 ZSHR — Depth/Early Depth TLB Partitioning Register + + ZSHR - Depth/Early Depth TLB Partitioning Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000020 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04050h +This register is used to determine the number of TLB entries from the total of 64 available to be used by the Depth +partition of the TLB. The rest of the entries are used for the Early Depth/Stencil TLB. + DWord Bit Description +0 31:6 Reserved + Format: MBZ + 5:0 Number of TLB Entries Out of 64 used for Depth TLB + Default Value: 32 + The rest are be used for Early Depth/Stencil TLB. Default value is 32. + + + + +1.1.8.2 Color/Depth Write FIFO Watermarks + + CZWMRK - Color/Depth Write FIFO Watermarks +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04060h +This register is directly mapped to the current Virtual Addresses in the MTTLB (Texture and constant cache TLB). +DWord Bit Description +0 31:24 Reserved + Format: MBZ + 23:18 Color Wr Burst Size + This is the maximum size of the requests burst, from the last High Watermark trip, before reevaluating + the High Watermark again. + 17:16 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 45 + CZWMRK - Color/Depth Write FIFO Watermarks + 15:12 Color Wr FIFO High Watermark + This is the number of accumulated Color writes that will trigger a Burst of Z Writes. + 11:6 Z Wr Burst Size + This is the maximum size of the requests burst, from the last High Watermark trip, before reevaluating + the High Watermark again. + 5:4 Reserved + Format: MBZ + 3:0 Z Wr FIFO High Watermark + This is the number of accumulated Depth writes that will trigger a Burst of Z Writes. + + + +1.1.8.3 PP_PFD[0:31] – PPGTT Page Fault Data Registers + + PP_PFD[0:31] - PPGTT Page Fault Data Registers +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 04580h + + The GTT Page Fault Log entries can be read from these registers. + + 4580h-4583h: Fault Entry 0 + + ... + + 45FCh-45FFh: Fault Entry 31 +DWord Bit Description +0 31:12 Fault Entry Page Address + Format: GraphicsAddress[31:12] + This RO field contains the faulting page address for this Fault Log entry. This field will contain a valid + fault address only if the bit in the GTT Page Fault Indication Register corresponding with the address + offset of this entry is set. + + 11:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 46 + 1.1.9 Context Save Registers + +1.1.9.1 SVG_CTX — SVG Context Save Register + + SVG_CTX - SVG Context Save Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: WO +Size (in bits): 32 +Address: 06FFCh +This register is used to send messages to enable context saving. This register may not be written from CPU. +DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0 + + 15:1 Reserved + Format: MBZ + 0 Context Save Start + Default Value: 0h + Format: Enable + When a 1 is written to this bit with the mask bit set, it will kick off a context save. Once the save is + complete the bit will be cleared. + + + + +1.1.9.2 SVL_CTX— SVL Context Save Register + + SVL_CTX - SVL Context Save Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 07FFCh +This register is used to send messages to enable context saving. This register may not be written from CPU. +DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0 + + 15:1 Reserved + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 47 + SVL_CTX - SVL Context Save Register + Format: MBZ + 0 Context Save Start + Default Value: 0h + Format: Enable + When a 1 is written to this bit with the mask bit set, it will initiate a context save. Once the save is + complete the bit will be cleared. + + + + +1.1.9.3 WM_CTX— WM Context Save Register + + WM_CTX - WM Context Save Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 05FFCh +This register is used to send messages to enable context saving. This register may not be written from CPU. +DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0 + + 15:1 Reserved + Format: MBZ + 0 Context Save Start + Default Value: 0h + Format: Enable + When a 1 is written to this bit with the mask bit set, it will kick off a context save. Once the save is + complete the bit will be cleared. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 48 + 1.1.9.4 SC_CTX— SC Context Save Register + + SC_CTX - SC Context Save Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 0E1FCh +Address: 0F1FCh +Name: SC_CTX_SLICE1 + + +This register is used to send messages to enable context saving. This register may not be written from CPU. +DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0 + + 15:5 Reserved + Format: MBZ + 4 Context Save Start(MMIO and NP State) + Format: Enable + When a 1 is written to this bit with the mask bit set, it will kick off a context save. Once the save is + complete the bit will be cleared. + + 3:1 Reserved + Format: MBZ + 0 Context Save Start(MMIO Only) + Format: Enable + When a 1 is written to this bit with the mask bit set, it will kick off a context save. Once the save is + complete the bit will be cleared. + + + + +1.1.9.5 DM_CTX — DM Context Save Register + + DM_CTX - DM Context Save Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 49 + DM_CTX - DM Context Save Register +Address: 0E0FCh +Address: 0F0FCh +Name: DM_CTX_SLICE1 + + +This register is used to send messages to enable context saving. This register may not be written from CPU. +DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0. + + 15:1 Reserved + Format: MBZ + 0 Context Save Start + Default Value: 0h + Format: Enable + When a 1 is written to this bit with the mask bit set, it will initiate a context save. Once the save is + complete the bit will be cleared. + + + + +1.1.9.6 SARB_CTX— SARB Context Save Register + + SARB_CTX - SARB Context Save Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 0B1FCh +This register is used to send messages to enable context saving. This register may not be written from CPU. +DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0 + + 15:1 Reserved + Format: MBZ + 0 Context Save Start + Default Value: 0h + Format: Enable + When a 1 is written to this bit with the mask bit set, it will kick off a context save. Once the save is + complete the bit will be cleared. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 50 + 1.1.9.7 VSC_CTX— VSC Context Save Register + + VSC_CTX - VSC Context Save Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 051FCh +This register is used to send messages to enable context saving. This register may not be written from CPU. +DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0 + + 15:1 Reserved + Format: MBZ + 0 Context Save Start + Default Value: 0h + Format: Enable + When a 1 is written to this bit with the mask bit set, it will kick off a context save. Once the save is + complete, the bit will be cleared. + + + + +1.1.9.8 GPM_CTX— GPM Context Save Register + + GPM_CTX - GPM Context Save Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 080FCh +This register is used to send messages to enable context saving. This register may not be written from CPU. +DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0 + + 15:1 Reserved + Format: MBZ + 0 Context Save Start + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 51 + GPM_CTX - GPM Context Save Register + Default Value: 0h + Format: Enable + When a 1 is written to this bit with the mask bit set, it will initiate a context save. Once the save is + complete the bit will be cleared. + + + + +1.1.9.9 SOL_CTX— SOL Context Save Register + + SOL_CTX - SOL Context Save Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 052FCh +This register is used to send messages to enable context saving. This register may not be written from CPU. +DWord Bit Description +0 31:6 Context Save Address/Offset + Default Value: 0h + Format: Address + + This field specifies where the SOL context is to be saved. + + If Power Context Save Mode is disabled, then the value of this field is the virtual address of the + location for SOL context to be saved. + + If Power Context Save Mode is enabled, then the value of this field is the offset into the power context + image for SOL context to be saved. + + 5:2 Reserved + Format: MBZ + 1 Power Context Save Mode + Default Value: 0h + Format: Enable + If set, then the save from SOL is for Power Context Save. If clear, then the save is for Ring Context + Save. + + 0 Context Save Start + Default Value: 0h + Format: Enable + When a 1 is written to this bit with the mask bit set, it will kick off a context save. Once the save is + complete, the bit will be cleared. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 52 + 1.1.9.10 1.1.9.11 RING_BUFFER_HEAD_PREEMPT_REG + + RING_BUFFER_HEAD_PREEMPT_REG - + RING_BUFFER_HEAD_PREEMPT_REG +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 0214Ch +Name: RCS RING_BUFFER_HEAD_PREEMPT_REG +ShortName: RCS_RING_BUFFER_HEAD_PREEMPT_REG + +This register contains the Head pointer offset in the ring when the last PREEMPTABLE command was executed +and caused the head pointer to move due to the UHPTR register being valid. If the PREEMPTABLE command is +executed as part of the batch buffer then the value of the register will be the offset in the ring of the command past +the batch buffer start that contained the preemptable command. + +This is a global register and context save restored as part of power context image. + + Programming Notes + + Programming Restriction: + + This register should NEVER be programmed by driver. This is for HW internal use only. +DWord Bit Description +0 31:21 Reserved + Format: MBZ + 20:2 Preempted Head Offset + Format: U19 + This field contains the Head pointer offset in the ring when the last MI_ARB_CHECK command was + executed and caused the head pointer to move due to the UHPTR register being valid. + + 1:0 Ring/Batch Indicator + Format: Enabled + + + Value Name Description + 0h Ring Preemptable command was executed in ring and caused head pointer to be updated. + 1h Batch Preemptable command was executed in batch and caused head pointer to be updated. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 53 + 1.1.9.11 BB_ADDR_DIFF—Batch Buffer Address Difference Register + + BB_ADDR_DIFF - Batch Address Difference Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02154h + + This register contains the difference between the start of the last batch and where the last initiated Batch Buffer is + currently fetching commands. + Programming Notes +Programming Restriction: + + + This register should NEVER be programmed by driver, this is for HW internal use only. +DWord Bit Description +0 31:2 Batch Buffer Address Difference + Format: GraphicsAddress[31:2] + This field specifies the DWord-aligned difference between the starting address of the batch buffer and + where the last initiated Batch Buffer is currently fetching commands. + + 1:0 Reserved + Format: MBZ + + + + +1.1.10 Mode and Misc Ctrl Registers + +1.1.10.1 GT4 Mode Control Register +B/D/F/Type:MBCunit +Address Offset:9038-903Bh +Default Value:0h +Access: RW; RO; +Size:32 bits + Bit Access Default Value RST/PWR Description + 1:0 R/W 00b Core + GT4 Usage mode: + 00: Non-GT4 + 01: GT4 is used in Alternate Frame rendering Mode (AFR) + 10: Basic Split Frame rendering Mode (SFR) + 11: Complex Split Frame rendering Mode (SFR w/ CBR) + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 54 + Basic Split Frame Rendering is like CBR for all units except Windower. Windower should not be doing +any checker boarding in basic SFR. The split programming should be done scissor range programming. + +Complex Split Frame Rendering (aka CBR) is already defined in many DCNs + +1.1.10.2 MI_MODE — Render Mode Register for Software Interface + + MI_MODE - Render Mode Register for Software Interface +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 0209Ch +The MI_MODE register contains information that controls software interface aspects of the Memory Interface +function. +DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0 + + 14 Async Flip Performance mode + + Format: U1 + + + Value Name Description + 0h Performance mode enabled [Default] The stall of the flip event is in the windower + 1h Performance mode disabled The stall of the flip event is in the command stream + + + Programming Notes + This bit should be set to '1' on all projects disabling Async Flip Performance mode. + + When Async Flip Performance mode is enabled stall is in the Windower allowing the commands + following the MI_WAIT_FOR_EVENT to be parsed by command streamer, this breaks the usage + model of controlling the display message generation in display engine using + MI_LOAD_REGISTER_IMMEDIATE commands from ring buffer. + 13 Flush Performance mode + + Format: U1 + + + Value Name Description + 0h run fast restore [Default] No NonPipelined SV flush. + 1h run slow legacy restore With NonPipelined SV flush. + 11 Invalidate UHPTR enable + Format: Enable + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 55 + MI_MODE - Render Mode Register for Software Interface + If bit set H/W clears the valid bit of UHPTR (2134h, bit 0) when current active head pointer is equal to + UHPTR. + + 10 Reserved + + Format: MBZ + 9 Rings Idle + Format: U1 + Read Only Status bit + Value Name Description + 0h Not Idle [Default] Parser not Idle or Ring Arbiter not Idle. + 1h Idle Parser Idle and Ring Arbiter Idle. + + + Programming Notes + Writes to this bit are not allowed. + 8 Stop Rings + Format: U1 + + + Value Name Description + 0h [Default] Normal Operation. + 1h Parser is turned off and Ring arbitration is turned off. + + + Programming Notes + Software must set this bit to force the Rings and Command Parser to Idle. Software must read a 1 in + the Ring Idle bit after setting this bit to ensure that the hardware is idle. + Software must clear this bit for Rings to resume normal operation. + 6 Vertex Shader Timer Dispatch Enable + Format: Enable + + + Value Name Description + 0h Disable Disable the timer for dispatch of single vertices from the vertex shader. Vertex + [Default] shader will try to collect 2 vertices before a dispatch + 1h Enable Enable the timer for dispatch of single vertices. Dispatch a single vertex shader + thread after the timer expires. + 5 Reserved + Format: MBZ + 4 Reserved + + Format: MBZ + 3:1 Reserved + + Format: MBZ + 0 Mask IIR disable + Format: Disable + Mask IIR disable. Nominally the Interrupt controller masks interrupts in the IIR register if an interrupt + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 56 + MI_MODE - Render Mode Register for Software Interface + acknowledge from the 3gio interface is pending. Setting this bit to a 1 allows interrupts to be visible to + the interrupt controller while an interrupt acknowledge is pending. + + + + +1.1.10.3 FF_Mode - Thread Mode Register + + FF_Mode - Thread Mode Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS + 0x28A01010 +Access: R/W +Size (in bits): 32 +Address: 020A0h +This register is used to program the FF shader Mode. +DWord Bit Description +0 31 Reserved + + Format: MBZ + 30 Reserved + + Format: MBZ + 29:26 DS Hit Max Value + Format: U4 + + + Description Project + If the number of hits reaches the DS Hit Max Value and there is a pending miss to be + dispatched, the DS will dispatch the pending miss vertex as a single dispatch. + Programming the value beyond the range will have undefined behavior. + + + Value Name Project + 10 [Default] + [1,11] + 25:20 VS Hit Max Value + Format: U6 + + + Description Project + If the number of hits reaches the VS Hit Max Value and there is a pending miss to be + dispatched, the VS will dispatch the pending miss vertex as a single dispatch. + Programming the value beyond the range will have undefined behavior. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 57 + FF_Mode - Thread Mode Register + Value Name Project + 10 [Default] + [1,58] + 19 DS Reference Count Full Force Miss Enable + Project: + Format: Enable + + + Value Name Description + 0b [Default] On a hit to the DS cache and the associated handle’s reference count is full then stall + until a derefernce. + 1b On a hit to the DS cache and the associated handle’s reference count is full then force + the cycle as a miss and allocate a new handle. + 18:17 TS Thread Dispatch Mode + + Format: U2 + + + Value Name Description + 0h Load Balanced Thread Dispatch will load balance the half slices of the threads. Note: this will + [Default] cause possible corruption if input handles are reused due to instancing or + topologies that reuse vertices(i.e. strips and fans) + 1h Half Slice 0 All threads will be dispatched to Half Slice 0. + 2h Half Slice 1 All threads will be dispatched to Half Slice 1. + 3h Reserved + 16 TS Thread Dispatch Override Enable + + Format: Enable + + + Value Name Description + 0h Disable [Default] Hardware will decide which half slice the thread will dispatch. + 1h Enable The value in the TS Thread Dispatch Mode will be used for dispatch. + 15 VS Reference Count Full Force Miss Enable + + Format: U1 + + + Value Name Description + [0,1] + 0b [Default] On a hit to the VS cache and the associated handle's reference count is full then stall + until a derefernce. + 1b On a hit to the VS cache and the associated handle's reference count is full then force + the cycle as a miss and allocate a new handle. + 14:13 VS Thread Dispatch Mode + + Format: U2 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 58 + FF_Mode - Thread Mode Register + Value Name Description + 0h Load Balanced Thread Dispatch will load balance the half slices of the threads. Note: this will + [Default] cause possible corruption if input handles are reused due to instancing or + topologies that reuse vertices (i.e. strips and fans) + 1h Half Slice 0 All threads will be dispatched to Half Slice 0. + 2h Half Slice 1 All threads will be dispatched to Half Slice 1. + 3h Reserved + 12 VS Thread Dispatch Override Enable + + Format: Enable + + + Value Name Description + 0h Disable Hardware will decide which half slice the thread will dispatch. + 1h Enable [Default] The value in the VS Thread Dispatch Mode will be used for dispatch. + 11:7 Reserved + Format: MBZ + 6:5 DS Thread Dispatch Mode + + Format: U2 + + + Value Name Description + 0h Load Balanced Thread Dispatch will load balance the half slices of the threads. Note: this will + [Default] cause possible corruption if input handles are reused due to instancing or + topologies that reuse vertices (i.e., strips and fans). + 1h Half Slice 0 All threads will be dispatched to Half Slice 0. + 2h Half Slice 1 All threads will be dispatched to Half Slice 1. + 3h Reserved + 4 DS Thread Dispatch Override Enable + + Format: Enable + + + Value Name Description + 0h Disable Hardware will decide which half slice the thread will dispatch. + 1h Enable [Default] The value in the DS Thread Dispatch Mode will be used for dispatch. + 3:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 59 + 1.1.10.4 GFX_MODE – Graphics Mode Register + + GFX_MODE - Graphics Mode Register +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000800 +Size (in bits): 32 +Trusted Type: 1 +Address: 0229Ch + + + Description Project +This register contains a control bit for the new 2-level PPGTT functions. +DefaultValue = 00002800h +DWord Bit Description +0 31:16 Mask Bits + Format: Mask[15:0] + Must be set to modify corresponding bit in Bits 15:0. (All implemented bits) + + 14 Reserved + Project: + Format: MBZ + 13 Flush TLB invalidation Mode + + Format: U1 + This field controls the invalidation if the TLB cache inside the hardware. When enabled this bit limits the + invalidation of the TLB only to batch buffer boundaries, to pipe_control commands which have the TLB + invalidation bit set and sync flushes. If disabled, the TLB caches are flushed for every full flush of the + pipeline. + + 12 Reserved + Project: All + Format: MBZ + 11 Replay Mode + + Format: U1 Context Switch Granularity + + + This field controls the granularity of the replay mechanism when coming back into a previously + preempted context. + Value Name Description Project + 0h mid-triangle Super span Level. Pipeline is not flushed. This implies commands + preemption parsed are executed speculatively and may not complete before a + context switch. + 1h mid-cmdbuffer Drawcall Level. Pipeline is flushed before switching to the next + preemption [Default] context. Commands parsed are commited to completing before a + context switch + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 60 + GFX_MODE - Graphics Mode Register + Programming Notes + A fixed function pipe flush is required before modifying this fieldUnless pre-emption at a mid-triangle is + required the bit must be set. + 10 Reserved + Project: All + Format: MBZ + 9 Per-Process GTT Enable + + Format: Enabled + Per-Process GTT Enable + Value Name Description + 0h PPGTT When clear, the Global GTT will be used to translate memory access from + Disable designated commands and for commands that select the PPGTT as their + [Default] translation space. + 1h PPGTT When set, the PPGTT will be used to translate memory access from designated + Enable commands and for commands that select the PPGTT as their translation space. + The PD Offset and PD Cacheline Valid registers must be set in all pipes (blitter, + MFX, render) before any workload is submitted to hardware. This mode enables + support for big pages (32k) + 8 Reserved + + Format: MBZ + 7 Reserved + + Format: MBZ + 6:1 Reserved + + Format: MBZ + 0 Reserved + + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 61 + 1.1.10.5 GT_MODE – GT Mode Register + + GT_MODE - GT Mode Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000200 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 07008h + + + + This Register is used to control the 6EU and 12EU configuration for GT. + + Write 0x01FF01FF to this register enables the 6EU mode. + + RegisterType = MMIO_SVL +DWord Bit Description +0 31:16 Mask Bits + Format: Mask[15:0] + Must be set to modify corresponding bit in Bits 15:0. (All implemented bits) + + 15 Reserved + + Format: MBZ + 14:11 Reserved + + Format: MBZ + 10 Reserved + + Format: MBZ + 9 WIZ Hashing Mode High Bit + + Format: U1 + + This field adds additional hashing modes in combination with the WIZ Hashing Mode field. The Value + column in the table below refers to this field (high bit) and the WIZ Hashing Mode field (low bit). + + This field is don’t care if the Hashing Disable bit is set. + Value Name Description + 0h 8x8 Checkerboard hashing + 1h [Default] 8x4 Checkerboard hashing + 2h 16x4 Checkerboard hashing + 3h Reserved + 7 WIZ Hashing Mode + Project: + Format: U1 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 62 + GT_MODE - GT Mode Register + + Description Project + This field configures the Hashing mode in Windower. This field is don’t care if the + Hashing Disable bit is set. + The WIZ Hashing Mode High Bit field is combined with this field to enable additional + modes. + 2 Reserved + Format: MBZ + 0 Reserved + + + +1.1.10.6 Cache_Mode_0— Cache Mode Register 0 + + Cache_Mode_0 - Cache Mode Register 0 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS + 0x00000004 +Access: R/W +Size (in bits): 32 +Address: 07000h + + + + This register is used to control the operation of the Render and Sampler L2 Caches. All reserved bits are + implemented as read/write. + + Before changing the value of this register, GFX pipeline must be idle i.e. full flush is required. + + This Register is saved and restored as part of Context. + + RegisterType = MMIO_SVL +DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0. + + 15 Sampler L2 Disable + Format: Disable + + + Value Name Description + 0h [Default] Sampler L2 Cache Enabled. + 1h Sampler L2 Cache Disabled all accesses are treated as misses. + 14:12 Reserved + + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 63 + Cache_Mode_0 - Cache Mode Register 0 + 11 Reserved + + Format: MBZ + 10 Reserved + Format: MBZ + 9 Sampler L2 TLB Prefetch Enable + Value Name Description + 0h [Default] TLB Prefetch Disabled + 1h TLB Prefetch Enabled + 7:6 Sampler L2 Request Arbitration + Format: U2 + + + Value Name Description + 00b Round Robin + 01b Fetch are Highest Priority + 10b Constants are Highest Priority + 11b Reserved + 5 STC Eviction Policy + Format: Disable + + If this bit is set, RCCunit will have LRA as replacement policy. The default value i.e. ( when this bit is + reset ) indicates that non-LRA eviction policy. This bit must be reset. LRA replacement policy is not + supported. + + Note: If this bit is set to "1", bit 7 of 0x7010h must also be set to "1" + + 4 RCC Eviction Policy + + Format: Disable + + If this bit is set, RCCunit will have LRA as replacement policy. The default value i.e. ( when this bit is + reset ) indicates that non-LRA eviction policy. This bit must be reset. LRA replacement policy is not + supported. + + Note: If this bit is set to "1", bit 7 of 0x7010h must also be set to "1" + + 3 Hierarchical Z Disable + Mask: MMIO(0x2120)#19 + Format: U1 + + + Value Name + 0h Enable + 1h Disable + 2 Hierarchical Z RAW Stall Optimization Disable + + Format: U1 + The Hierarchical Z RAW Stall Optimization allows non-overlapping polygons in the same 8x4 + pixel/sample area to be processed without stalling waiting for the earlier ones to write to Hierarchical Z + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 64 + Cache_Mode_0 - Cache Mode Register 0 + buffer. + Value Name Description + 0h Enable Enables the hierarchical Z RAW Stall Optimization. + 1h Disable [Default] Disables the hierarchical Z RAW Stall Optimization. + 1 Disable clock gating in the pixel backend + Format: Disable + 0 Render Cache Operational Flush Enable + + Format: Enable + + + Value Name Description + 0h Disable Operational Flush Disabled (recommended for performance when not rendering + [Default] to the front buffer) + 1h Enable Operational Flush Enabled (required when rendering to the front buffer) + + + Errata Description Project + Erratum This bit must be set to ‘0’ (Disable) + + + +1.1.10.7 Cache_Mode_1— Cache Mode Register 1 + + Cache_Mode_1 - Cache Mode Register 1 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000180 +Access: Read/32 bit Write Only +Size (in bits): 32 +Address: 07004h + + + Description Project +RegisterType: MMIO_SVL +Before changing the value of this register, GFX pipeline must be idle; i.e., full flush is required. This Register +is saved and restored as part of Context. +DWord Bit Description +0 31:16 Mask Bits for 15:0 + Format: Mask[15:0] + Must be set to modify corresponding data bit. Reads to this field returns zero. + + 15 Reserved + Project: All + Format: MBZ + 14 Reserved + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 65 + Cache_Mode_1 - Cache Mode Register 1 + + Format: MBZ + 12 HIZ Eviction Policy + Project: All + Format: U1 + If this bit is set, Hizunit will have LRA as replacement policy. The default value i.e. (when this bit is + reset) indicates the non-LRA eviction policy. For performance reasons, this bit must be reset. + Value Name Description Project + 0h [Default] Non-LRA eviction Policy All + 1h LRA eviction Policy All + + + Programming Notes Project + If this bit is set to "1", bit 3 of 0x7010h must also be set to "1" + 11 Reserved + + Format: MBZ + 8:7 Sampler Cache Set XOR selection + Project: All + Format: U2 + These bits have an impact only when the Sampler cache is configured in 16 way set associative mode. + If the cache is being used for immediate data or for blitter data these bits have no effect. + Value Name Description Project + 00b None No XOR. All + 01b Scheme 1 All + New_set_mask[3:0] = Tiled_address[16:13]. + + + + New_set[3:0] less than or = New_set_mask[3:0] ^Old_set[3:0]. + + + + Rationale: These bits can distinguish among 16 different equivalent + classes of virtual pages. These bits also represent the lsb for tile rows + ranging from a pitch of 1 tile to 16 tiles. + 10b Scheme 2 All + New_set_mask[3] = Tiled_address[17] ^ Tiled_address[16]. + + + + New_set_mask[2] = Tiled_address[16] ^ Tiled_address[15]. + + + + New_set_mask[1] = Tiled_address[15] ^ Tiled_address[14]. + + + + New_set_mask[0] = Tiled_address[14] ^ Tiled_address[13]. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 66 + Cache_Mode_1 - Cache Mode Register 1 + + New_set[3:0] less than or = New_set_mask[3:0] ^ Old_set[3:0]. + + + + Rationale: More bits on each XOR can give better statistical uniformity on + sets and since two lsbs are taken for each tile row size, it reduces the + chance of aliasing on sets. + 11b Scheme 3 + [Default] New_set_mask[3] = Tiled_address[22] ^ Tiled_address[21] ^ + Tiled_address[20] ^ Tiled_address[19]. + + + + New_set_mask[2] = Tiled_address[18] ^ Tiled_address[17] ^ + Tiled_address[16]. + + + + New_set_mask[1] = Tiled_address[15] ^ Tiled_address[14]. + + + + New_set_mask[0] = Tiled_address[13]. + + + + New_set[3:0] less than or = New_set_mask[3:0] ^ Old_set[3:0]. + + + + Rationale: More bits on each XOR can give better statistical uniformity on + sets and since each XOR has different bits, it reduces the chance of + aliasing on sets even more. + 6 Pixel Backend sub-span collection Optimization Disable + + Format: Disable + + + Value Name Description + 0h [Default] Enables two contiguous quads to be collected as 4X2 access for RCZ interface. This + allows for less bank collision and less RAM power on RCZ. + 1h Disables this optimization and therefore only one valid sub-span is sent to RCZ on the + 4X2 interface. + + + Programming Notes Project + This bit must be set. + 5 MCS Cache Disable + + Format: Disable + For Programming restrictions please refer to the 3D Pipeline. + Value Name Description + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 67 + Cache_Mode_1 - Cache Mode Register 1 + 0h [Default] MCS cache enabled. It allows RTs with MCS buffer enabled to be rendered using + either MSAA compression for MSRT OR with color clear feature for non MSRT. + 1h MCS cache is disabled. Hence no MSAA compression for MSRT and no color clear for + non-MSRT. + 4 Reserved + + Format: MBZ + 3 Depth Read Hit Write-Only Optimization Disable + + Format: Disable + + + Description Project + This bit must always be reset to "0". + + + Value Name Description Project + 0h [Default] Read Hit Write-only optimization is enabled in the Depth cache (RCZ). + 1h Read Hit Write-only optimization is disabled in the Depth cache (RCZ). + 2:1 Reserved + + + + +1.1.10.8 GAFS_MODE — Mode Register for GAFS + + GAFS_MODE - Mode Register for GAFS +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 0212Ch +DWord Bit Description +0 31:16 Mask Bits + Format: Mask[15:0] + Masks: These bits serve as write enables for bits 15:0. If this register is written with any of these bits + clear the corresponding bit in the field 15:0 will not be modified. Reading these bits always returns 0s. + + 15:10 Reserved + Format: MBZ + 8:2 Reserved + Format: MBZ + 0 Selection of Arbitration for GAFS + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 68 + GAFS_MODE - Mode Register for GAFS + + Format: MBZ + GAFS data return policy from FFROB is a round-robin. This bit freezes the round robin to FF pipeline + order. + + + + + 1.1.10.9 INSTPM—Instruction Parser Mode Register + + INSTPM - Instruction Parser Mode Register + Register Space: MMIO: 0/2/0 + Project: All + Source: RenderCS + Default Value: 0x00000000 + Access: R/W + Size (in bits): 32 + Trusted Type: 1 + Address: 020C0h + The INSTPM register is used to control the operation of the Instruction Parser. Certain classes of instructions can be + disabled (ignored) – often useful for detecting performance bottlenecks. Also, Synchronizing Flush operations can be + initiated – useful for ensuring the completion (vs. only parsing) of rendering instructions. + Programming Notes +  If an instruction type is disabled, the parser will read those instructions but not process them. + + Error checking will be performed even if the instruction is ignored. + + All Reserved bits are implemented. + + This Register is saved and restored as part of Context. + + + DWor + d Bit Description + 0 31:1 Mask Bits + 6 Format: Mask[15:0] + Masks: These bits serve as write enables for bits 15:0. If this register is written with any of these bits clear + the corresponding bit in the field 15:0 will not be modified. Reading these bits always returns 0s. + + 14:1 Reserved + 3 + Format: MBZ + 11 CLFLUSH Toggle + + Format: U1 + This bit changes polarity each time the MI_CLFLUSH command completes. + + + + + Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 69 + INSTPM - Instruction Parser Mode Register + + 10 Reserved + + Format: MBZ + 9 TLB Invalidate + + Format: U1 + If set, this bit allows the command stream engine to invalidate the 3D render TLBs. This bit is valid only + with the Sync flush enable. Note: GFX soft resets do not invalidate TLBs, it is up to GFX driver to explicitly + invalidate TLBs post reset. + + 8 Memory Sync Enable + + Format: U1 + If set, this bit allows the command stream engine to write out the data from the local caches to memory. + This bit is valid only with the Sync flush enable + + 7 Force Sync Command Ordering + + Format: Enable + + + Description Project + By default, driver/OS synchronization commands (MI_STORE_DATA_IMM, for instance) can + execute out of order with respect to 3D state and 3D primitive commands. When set, this bit forces + ordering of these commands. See section 3.2.2 for a list of these commands. + [This bit should be programmed to 1. + + + Value Name + 0b [Default] + 1b + 6 CONSTANT_BUFFER Address Offset Disable + + Format: Disable + When this bit is clear, the 3DSTATE_CONSTANT_* Buffers’ Starting Address is used as a + DynamicStateOffset. That is, it serves as an offset from the Dynamic State Base Address. Accesses will be + subject to Dynamic State bounds checking. + When this bit is set, the 3DSTATE_CONSTANT_* Buffers’ Starting Address is used as a true + GraphicsAddress (not an offset). No bounds checking will be performed during access. + + 5 Sync Flush Enable + + Format: U1 + This field is used to request a Sync Flush operation. The device will automatically clear this bit before + completing the operation. See Sync Flush (Programming Environment). + Programming Notes Project +  The command parser must be stopped prior to issuing this command by setting + the Stop Rings bit in register MI_MODE. Only after observing Rings Idle set in + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 70 + INSTPM - Instruction Parser Mode Register + MI_MODE can a Sync Flush be issued by setting this bit. Once this bit becomes + clear again, indicating flush complete, the command parser is re-enabled by + clearing Stop Rings. + + Workaround : + + Write 0x2050[31:0] = 0x00010001 (disable sequence) + + + Write 0x2700[31:0] = 0x00000000 (Wake up CS but don't do anything) + + Poll 0x22AC[3:0] = 0 (Guarantees render pipe is awake) + + VT-d request(Sync Flush) (Normal VT-d cycles(Replace with Sync Flush Steps) + + Write 0x2050[31:0] = 0x00010000 ( Enable sequence (to enter RC6) ) + 3 Media Instruction Disable + + Format: U1 + This bit instructs the Renderer instruction parser to parse and error-check Media instructions, but not + execute them. Format = Disable + + 2 3D Rendering Instruction Disable + + Format: U1 + + This bit instructs the Renderer instruction parser to parse and error-check 3D Rendering instructions, but + not execute them. This bit must always be set by software if 3D State Instruction Disable is set. Setting + this bit without setting 3D State Instruction Disable is allowed. + + Format = Disable + + 1 3D State Instruction Disable + + Format: Disable + 0 Texture Palette Load Instruction Disable + + Format: U1 + This bit instructs the Renderer instruction parser to parse and error-check Texture Palette Load + instructions, but not execute them. Format = Disable + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 71 + 1.1.10.10 EXCC—Execute Condition Code Register + + EXCC - Execute Condition Code Register +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W,RO +Size (in bits): 32 +Trusted Type: 1 +Address: 02028h + + This register contains user defined and hardware generated conditions that are used by MI_WAIT_FOR_EVENT + commands. An MI_WAIT_FOR_EVENT instruction excludes the executing ring from arbitration if the selected event + evaluates to a 1, while instruction is discarded if the condition evaluates to a 0. Once excluded a ring is enabled into + arbitration when the selected condition evaluates to a 0. + + This register also contains control for the invalidation of indirect state pointers on context restore. + DWord Bit Description +0 31:16 Mask Bits + Format: Mask[15:0] + These bits serves as a write enable for bits 15:0. If this register is written with any of these bits clear + the corresponding bit in the field 15:0 will not be modified. Reading these bits always returns 0s. + + 15:12 Reserved + + Format: MBZ + 11 Pending Indirect State Dirty Bit + + This field keeps track of whether or not an indirect state pointer command has been parsed in the + current context. Clears either on a context save or explicitly through a flush command. + + 10:7 Pending Indirect State Counter + + This field keeps track of the maximum number of indirect state pointers pending in the system. + When the register is saved/restored, it saves either a value of 1 or 0. This field is Read-Only. + + 6:5 Reserved + Format: MBZ + 4:0 User Defined Condition Codes + The software may signal a Stream Semaphore by setting the Mask bit and Signal Bit together to + match the bit field specified in a WAIT_FOR_EVENT (Semaphore). + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 72 + 1.1.10.11 NOPID — NOP Identification Register + + NOPID - NOP Identification Register +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Size (in bits): 32 +Trusted Type: 1 +Address: 02094h + Description Project +Access: RW +The NOPID register contains the Noop Identification value specified by the last MI_NOOP instruction that +enabled this register to be updated. + DWord Bit Description +0 31:22 Reserved + Format: MBZ + + + +1.1.10.12 FBC RT BASE ADDRESS REGISTER + + FBC_RT_BASE_ADDR_REGISTER - + FBC_RT_BASE_ADDR_REGISTER +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: Read/32 bit Write Only +Size (in bits): 32 +Address: 07020h + + +This Register is saved and restored as part of Context. +DWord Bit Description +0 31:12 FBC RT Base Address + Format: PPGraphicsAddress[31:12] + 4KB aligned Base Address as mapped in the PPGTT or in the GGTT for the render target. + Must be set to modify corresponding data bit. Reads to this field returns zero. This base address must + be the one that is either front buffer or the back-buffer (a flip target). It can be only programmed once + per context. It must be programmed before any draw call binding that render target base address. + + 11:2 Reserved + Format: MBZ + 1 FBC Front Buffer Target + + Format: Enable + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 73 + FBC_RT_BASE_ADDR_REGISTER - + FBC_RT_BASE_ADDR_REGISTER + + Value Name Description Project + 0h [Default] FBC is targeting the Back Buffer for compression. This buffer can be cached in + the MLC/LLC, so a GFDT flush is required before FBC can begin compression. + 1h FBC is targeting the Font Buffer for compression. This buffer cannot be cached + in the MLC/LLC. FBC compression can begin after any RC flush. + 0 PPGTT Render Target Base Address Valid for FBC + + Access: None + Exists If: Always + Format: Enable + Format: GraphicsAddress[31:0]U32 + + + Value Name Description + 0h [Default] Base address in this register [31:12] is not valid and therefore FBC will not get + any modifications from rendering. + 1h Base address in this register [31:12] is valid and HW needs to compare the + current render target base address with this base address to provide + modifications to FBC. + + + Programming Notes + Workaround : Do not enable Render Command Streamer tracking for FBC. + Instead insert a LRI to address 0x50380 with data 0x00000004 after the + PIPE_CONTROL that follows each render submission. + + + +1.1.10.13 RVSYNC – Render/Video Semaphore Sync Register + + RVSYNC - Render/Video Semaphore Sync Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 02040h +This register is written by VCS, read by CS. + DWord Bit Description +0 31:0 Semaphore Data + Semaphore data for synchronization between render engine and blitter engine. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 74 + 1.1.10.14 RBSYNC – Render/Blitter Semaphore Sync Register + + RBSYNC - Render/Blitter Semaphore Sync Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 02044h +This register is written by BCS, read by CS. + DWord Bit Description +0 31:0 Semaphore Data + Semaphore data for synchronization between render engine and blitter engine. + + + + +1.1.11 RINGBUF — Ring Buffer Registers +See the “Device Programming Environment” chapter for detailed information on these registers + +1.1.11.1 RING_BUFFER_TAIL + + RING_BUFFER_TAIL - Ring Buffer Tail +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02030h +Name: RCS Ring Buffer Tail +ShortName: RCS_RING_BUFFER_TAIL +Address: 12030h +Name: VCS Ring Buffer Tail +ShortName: VCS_RING_BUFFER_TAIL +Address: 22030h +Name: BCS Ring Buffer Tail +ShortName: BCS_RING_BUFFER_TAIL +These registers are used to define and operate the “ring buffer” mechanism which can be used to pass instructions +to the command interface. The buffer itself is located in a linear memory region. The ring buffer is defined by a 4 +Dword register set that includes starting address, length, head offset, tail offset, and control information. + Refer to the Programming Interface chapter for a detailed description of the parameters specified in this ring buffer +register set, restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be +used to pass instructions. + Ring Buffer Tail Offsets must be properly programmed before ring is enabled. A Ring Buffer can be enabled when + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 75 + RING_BUFFER_TAIL - Ring Buffer Tail +empty. +DWord Bit Description +0 31:21 Reserved + Format: MBZ + 20:3 Tail Offset + Format: GraphicsAddress[20:3] + This field is written by software to specify where the valid instructions placed in the ring buffer end. The + value written points to the QWord past the last valid QWord of instructions. In other words, it can be + defined as the next QWord that software will write instructions into. + Software must write subsequent instructions to QWords following the Tail Offset, possibly wrapping + around to the top of the buffer (i.e., software can’t skip around within the buffer). + Note that all DWords prior to the location indicated by the Tail Offset must contain valid instruction + data – which may require instruction padding by software. See Head Offset for more information. + + 2:0 Reserved + Format: MBZ + + + +1.1.11.2 RING_BUFFER_HEAD + + RING_BUFFER_HEAD - Ring Buffer Head +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02034h +Name: RCS Ring Buffer Head +ShortName: RCS_RING_BUFFER_HEAD +Address: 12034h +Name: VCS Ring Buffer Head +ShortName: VCS_RING_BUFFER_HEAD +Address: 22034h +Name: BCS Ring Buffer Head +ShortName: BCS_RING_BUFFER_HEAD +This register is used to define and operate the ring buffer mechanism which can be used to pass instructions to the +command interface. The buffer itself is located in a physical memory region. The ring buffer is defined by a 4 Dword +register set that includes starting address, length, head offset, tail offset, and control information. Refer to the +Programming Interface chapter for a detailed description of the parameters specified in this ring buffer register set, +restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be used to pass +instructions. +Ring Buffer Head Offsets must be properly programmed before ring is enabled. A Ring Buffer can be +enabled when empty. +DWord Bit Description +0 31:21 Wrap Count + Format: U11 count of ring buffer wraps + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 76 + RING_BUFFER_HEAD - Ring Buffer Head + + This field is incremented by 1 whenever the Head Offset wraps from the end of the buffer back to the + start (i.e., whenever it wraps back to 0). Appending this field to the Head Offset field effectively creates + a virtual 4GB Head “Pointer” which can be used as a tag associated with instructions placed in a ring + buffer. The Wrap Count itself will wrap to 0 upon overflow. + + 20:2 Head Offset + Format: GraphicsAddress[20:2] DWord Offset + + + This field indicates the offset of the next instruction DWord to be parsed. Software will initialize this field + to select the first DWord to be parsed once the RB is enabled. (Writing the Head Offset while the RB is + enabled is UNDEFINED). Subsequently, the device will increment this offset as it executes instructions + – until it reaches the QWord specified by the Tail Offset. At this point the ring buffer is considered + “empty”. + Programming Notes + A RB can be enabled empty or containing some number of valid instructions. + 1 Reserved + Format: MBZ + 0 Wait for Condition Indicator + Source: RenderCS + This is a read only value used to indicate whether or not the command streamer is currently waiting for + a conditional code to be cleared from 0x2028 + + 0 Reserved + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + Format: MBZ + + + +1.1.11.3 RING_BUFFER_START + + RING_BUFFER_START - Ring Buffer Start +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02038h +Name: RCS Ring Buffer Start +ShortName: RCS_RING_BUFFER_START +Address: 12038h +Name: VCS Ring Buffer Start +ShortName: VCS_RING_BUFFER_START +Address: 22038h +Name: BCS Ring Buffer Start + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 77 + RING_BUFFER_START - Ring Buffer Start +ShortName: BCS_RING_BUFFER_START +These registers are used to define and operate the “ring buffer” mechanism which can be used to pass instructions +to the command interface. The buffer itself is located in a physical memory region. The ring buffer is defined by a 4 +Dword register set that includes starting address, length, head offset, tail offset, and control information. Refer to the +Programming Interface chapter for a detailed description of the parameters specified in this ring buffer register set, +restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be used to pass +instructions. + DWord Bit Description +0 31:12 Starting Address + Format: GraphicsAddress[31:12]RingBuffer + This field specifies Bits 31:12 of the 4KB-aligned starting Graphics Address of the ring buffer. + Address bits 31 down to 29 must be zero. + All ring buffer pages must map to Main Memory (uncached) pages. Ring Buffer addresses are + always translated through the global GTT. + + 11:0 Reserved + Format: MBZ + + + +1.1.11.4 RING_BUFFER_CONTROL + + RING_BUFFER_CTL - Ring Buffer Control +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 0203Ch +Name: RCS Ring Buffer Control +ShortName: RCS_RING_BUFFER_CTL +Address: 1203Ch +Name: VCS Ring Buffer Control +ShortName: VCS_RING_BUFFER_CTL +Address: 2203Ch +Name: BCS Ring Buffer Control +ShortName: BCS_RING_BUFFER_CTL +These registers are used to define and operate the ring buffer mechanism which can be used to pass instructions to +the command interface. The buffer itself is located in a physical memory region. The ring buffer is defined by a 4 +Dword register set that includes starting address, length, head offset, tail offset, and control information. Refer to the +Programming Interface chapter for a detailed description of the parameters specified in this ring buffer register set, +restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be used to pass +instructions. +Ring Buffer Head and Tail Offsets must be properly programmed before it is enabled. A Ring Buffer can be +enabled when empty. +DWord Bit Description +0 31:21 Reserved + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 78 + RING_BUFFER_CTL - Ring Buffer Control + Format: MBZ + 20:12 Buffer Length + Format: U9-1 in 4 KB pages – 1 + + + This field is written by SW to specify the length of the ring buffer in 4 KB Pages.Range = [0 = 1 page = + 4 KB, 1FFh = 512 pages = 2 MB] + Value Name Description + 0 1 page = 4 KB + 1FFh 512 pages = 2 MB + 11 RBWait + Indicates that this ring has executed a WAIT_FOR_EVENT instruction and is currently waiting. + Software can write a “1” to clear this bit, write of “0” has no effect. When the RB is waiting for an event + and this bit is cleared, the wait will be terminated and the RB will be returned to arbitration. + 10 Semaphore Wait + Description Project + Indicates that this ring has executed a MI_SEMAPHORE_MBOX instruction with register + compare and is currently waiting. + 9 Reserved + Format: MBZ + 8 Reserved + Source: RenderCS, BlitterCS + Format: MBZ + 8 Disable Register Accesses + Source: VideoCS, VideoCS2, VideoEnhancementCS + + + Value Name Description + 0 R/W Ring is allowed to access (read or write) MMIO space. + 1 Read Only Ring is not allowed to write MMIO space. Ring is allowed to read registers. + 7:3 Reserved + Format: MBZ + 2:1 Automatic Report Head Pointer + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + + + Description Project + This field is written by software to control the automatic “reporting” (write) of this ring buffer’s + “Head Pointer” register (register DWord 1) to the corresponding location within the Hardware + Status Page. Automatic reporting can either be disabled or enabled at 4KB, 64KB or 128KB + boundaries within the ring buffer. + The head pointer will be reported to the head pointer location in the Per-Process Hardware + Status Page when it passes each 4KB page boundary. When the above-mentioned bit is set, + reporting will behave just as on the prior devices (as documented above), and option 2 is not + legal. + + + Value Name Description + 0 MI_AUTOREPORT_OFF Automatic reporting disabled + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 79 + RING_BUFFER_CTL - Ring Buffer Control + 1 MI_AUTOREPORT_64KB Report every 16 pages (64KB) + 2 MI_AUTOREPORT_4KB Report every page (4KB)This mode must not be enabled in Ring + Buffer mode of scheduling to minimize the auto reports. + 3 MI_AUTOREPORT_128KB Report every 32 pages (128KB) + 2:1 Reserved + + Source: RenderCS + Format: MBZ + 0 Ring Buffer Enable + Format: Enable + This field is used to enable or disable this ring buffer. It can be enabled or disabled regardless of + whether there are valid instructions pending. If disabled and the ring head equals ring tail, all state + currently loaded in hardware is considered invalid. + Programming Notes Project + SW should follow the below programming notes while enabling render engine's ring buffer for + the first time, this would be coming out of boot, standby, hibernate or reset. + + SW should set the Force Wakeup bit to prevent GT from entering C6. + + SW should dispatch workload (dummy) to initialize render engine with default state such that + any context switches that occur subsequently (Power Save) will save and restore coherent + device state. Indirect pointers used in 3D states should point to valid graphics surface existing + in memory. PP_DCLV followed by PP_DIR_BASE register should be programmed as part of + initialization workload if PPGTT is enabled in GFX_MODE register. + Once the render engine is programmed with valid state and the configuration, Force Wakeup + bit should be reset to enable C6 entry. + + + + +1.1.11.5 UHPTR — Pending Head Pointer Register + + UHPTR - Pending Head Pointer Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02134h +Name: RCS Pending Head Pointer Register +ShortName: RCS_UHPTR +Address: 12134h +Name: VCS Pending Head Pointer Register +ShortName: VCS_UHPTR +Address: 22134h +Name: BCS Pending Head Pointer Register + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 80 + UHPTR - Pending Head Pointer Register +ShortName: BCS_UHPTR + Programming Notes +Once SW uses UHPTR to preempt the existing workload, should explicitly program MI_SET_CONTEXT to save the +preempted context status before submitting the new workload. In case SW doesn’t want to save the state of the +preempted context, it should at the minimum program RS_PREEMPT_STATUS to 0x0 so that the register status +doesn’t interfere with the new workloads. + DWord Bit Description +0 31:3 Head Pointer Address + Format: GraphicsAddress[31:3] + This register represents the GFX address offset where execution should continue in the ring buffer + following execution of an MI_ARB_CHECK command. + + 2:1 Reserved + Format: MBZ + 0 Head Pointer Valid + This bit is set by the software to request a pre-emption. + It is reset by hardware when an MI_ARB_CHECK command is parsed by the command streamer. + The hardware uses the head pointer programmed in this register at the time the reset is generated. + Value Name Description + 0 InValid No valid updated head pointer register, resume execution at the current location in the + ring buffer + 1 Valid Indicates that there is an updated head pointer programmed in this register + + + + +1.1.12 Watchdog Timer Registers +These 2 registers together implement a watchdog timer. Writing ones to the control register enables the +counter, and writing zeroes disables the counter. The 2nd register is programmed with a threshold value +which, when reached, signals an interrupt then resets the counter to 0. Program the threshold value +before enabling the counter or extremely frequent interrupts may result. +Note that the counter itself is not observable. It increments with the main render clock. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 81 + 1.1.12.1 PR_CTR_CTL—Render Watchdog Counter Control + + PR_CTR_CTL - Render Watchdog Counter Control +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02178h +DWord Bit Description +0 31 Count Select + + Format: select + 0 – Use the timestamp to increment the watchdog count (every 640ns)1 – Use the fixed function clock + (csclk) to increment the watchdog count + + 30:0 Counter Logic Op + This field specifies the action to be taken by the clock counter to generate interrupts. Writing 0 into this + register causes a core render clock counter to be kicked off. Writing 1 into this register causes a core + render clock counter to be stopped and reset to 0. + + + +1.1.12.2 PR_CTR_THRSH—Render Watchdog Counter Threshold + + PR_CTR_THRSH - Render Watchdog Counter Threshold +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00150000 +Access: R/W +Size (in bits): 32 +Address: 0217Ch +DWord Bit Description +0 31:0 Counter logic Threshold + Default Value: 00150000h + Format: U32 + This field specifies the threshold that the hardware checks against for the value of the render clock + counter before generating an interrupt. The counter in hardware generates an interrupt when the + threshold is reached, rolls over and starts counting again. The interrupt generated is the “Media Hang + Notify” interrupt since this watchdog timer is intended primarily to remedy VLD hangs on the main + pipeline. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 82 + 1.1.12.3 PR_CTR—Render Watchdog Counter + + PR_CTR - Render Watchdog Counter +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 02190h + + DWord Bit Description +0 31:0 Counter Value + Format: U32 + This register reflects the render watchdog counter value itself. It cannot be written to. + + + + +1.1.13 Interrupt Control Registers +The Interrupt Control Registers described in this section all share the same bit definition. The bit definition +is as follows: + + Bit Definition for Interrupt Control Registers + +Source: RenderCS +Default Value: 0x00000000 +DWord Bit Description +0 31:12 Reserved + + Format: MBZ + Reserved for other command streamers - can not be allocated by main command streamer. + + 11:10 Reserved + + Format: MBZ + These bits may be assigned to interrupts on future products/steppings. + + 9 Performance Monitoring Buffer Half-Full Interrupt + + For internal trigger (timerbased) based reporting, if the report buffer crosses half full limit, this interrupt + is generated. + + 8 Context Switch Interrupt + 7 Page Fault + Project: All + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 83 + Bit Definition for Interrupt Control Registers + + Description Project + This bit is set whenever there is a pending GGTT/PPGTT (page or directory) fault in Render + command streamer. + 6 Timeout Counter Expired + Set when the render pipe timeout counter (0x02190) has reached the timeout thresh-hold value + (0x0217c). + 5 Reserved + + Format: MBZ + 4 PIPE_CONTROL Notify Interrupt + The Pipe Control packet (Fences) specified in 3D pipeline document may optionally generate an + Interrupt. The Store QW associated with a fence is completed ahead of the interrupt. + 3 Render Command Parser Master Error + + When this status bit is set, it indicates that the hardware has detected an error. It is set by the device + upon an error condition and cleared by a CPU write of a one to the appropriate bit contained in the + Error ID register followed by a write of a one to this bit in the IIR. Further information on the source of + the error comes from the "Error Status Register" which along with the "Error Mask Register" determine + which error conditions will cause the error status bit to be set and the interrupt to occur. + + Page Table Error: Indicates a page table error. + + Instruction Parser Error: The Render Instruction Parser encounters an error while parsing an + instruction. + 2 Sync Status + + + This bit is set in the Hardware Status Page DW offset 0 when the Instruction Parser completes a flush + with the sync enable bit active in the INSTPM register. The toggle event will happen after the render + engine is flushed. The HW Status DWord write resulting from this toggle will cause the CPU’s view of + graphics memory to be coherent as well (flush and invalidate the render cache). It is the driver's + responsibility to clear this bit before the next sync flush with HWSP write enabled. + + 0 Render Command Parser User Interrupt + This status bit is set when an MI_USER_INTERRUPT instruction is executed on the Render Command + Parser. Note that instruction execution is not halted and proceeds normally. A mechanism such as an + MI_STORE_DATA instruction is required to associate a particular meaning to a user interrupt. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 84 + The following table specifies the settings of interrupt bits stored upon a “Hardware Status Write” due to +ISR changes: + ISR bit Reporting via Hardware + Status Write (when unmasked + Bit Interrupt Bit via HWSTAM) + Set when event occurs, cleared + 9 Performance Monitoring Buffer Half-Full Interrupt + when event cleared + Not supported to be unmasked + 8 Context Switch Interrupt: Set when a context switch has just occurred. + + 7 Page Fault: This bit is set whenever there is a pending PPGTT (page or Set when event occurs, cleared + directory) fault. when event cleared + Not supported to be unmasked + 6 Media Decode Pipeline Counter Exceeded Notify Interrupt: The + counter threshold for the execution of the media pipeline is exceeded. + Driver needs to attempt hang recovery. + + 5 L3 Parity interrupt + + PIPE_CONTROL packet - Notify Enable 0 + 4 + Master Error Set when error occurs, cleared + 3 + when error cleared + Sync Status Toggled every SyncFlush Event + 2 + + 1 Reserved + User Interrupt 0 + 0 + + +1.1.13.1 HWSTAM — Hardware Status Mask Register + + HWSTAM - Hardware Status Mask Register +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0xFFFFFFFF +Access: R/W,RO +Size (in bits): 32 +Trusted Type: 1 +Address: 02098h +The HWSTAM register has the same format as the Interrupt Control Registers. The bits in this register are mask bits +that prevent the corresponding bits in the Interrupt Status Register from generating a Hardware Status Write (PCI +write cycle). Any unmasked interrupt bit (HWSTAM bit set to 0) will allow the Interrupt Status Register to be written to +the ISR location (within the memory page specified by the Hardware Status Page Address Register) when that +Interrupt Status Register bit changes state. + Programming Notes +  To write the interrupt to the HWSP, the corresponding IMR bit must also be clear (enabled). +  At most 1 bit can be unmasked at any given time. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 85 + DWord Bit Description +0 31:0 Hardware Status Mask Register + Default Value: FFFFFFFFh + Format: Array of Masks + Refer to the Interrupt Control Register section for bit definitions. Reserved bits are RO. + + + + +1.1.13.2 IMR—Interrupt Mask Register + + IMR - Interrupt Mask Register +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0xFFFFFFFF +Access: R/W,RO +Size (in bits): 32 +Address: 020A8h +The IMR register is used by software to control which Interrupt Status Register bits are masked or unmasked. +Unmasked bits will be reported in the IIR, possibly triggering a CPU interrupt, and will persist in the IIR until cleared +by software. Masked bits will not be reported in the IIR and therefore cannot generate CPU interrupts. + DWord Bit Description +0 31:0 Interrupt Mask Bits + Format: InterruptMask[32] Refer to the Interrupt Control Register section for bit definitions. + + + This field contains a bit mask which selects which interrupt bits (from the ISR) are reported in the IIR. + Reserved bits in the Interrupt Control Register are RO. + Value Name Description + FFFF FFFFh [Default] + 0h Not Masked Will be reported in the IIR + 1h Masked Will not be reported in the IIR + + + +1.1.13.3 Hardware-Detected Error Bit Definitions (for EIR, EMR, ESR) +This section defines the Hardware-Detected Error bit definitions and ordering that is common to the EIR, +EMR and ESR registers. The EMR selects which error conditions (bits) in the ESR are reported in the +EIR. Any bit set in the EIR will cause the Master Error bit in the ISR to be set. EIR bits will remain set until +the appropriate bit(s) in the EIR is cleared by writing the appropriate EIR bits with ‘1’ (except for the +unrecoverable bits described below). +The following table describes the Hardware-Detected Error bits: + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 86 + Hardware-Detected Error Bit Definitions + +Source: RenderCS +Default Value: 0x00000000 +DWord Bit Description +0 31:3 Reserved + Format: MBZ + 2 Reserved + + Format: MBZ + 1 Reserved + Format: MBZ + 0 Instruction Error + This bit is set when the Renderer Instruction Parser detects an error while parsing an instruction. + Instruction errors include: + + Client ID value (Bits 31:29 of the Header) is not supported (only MI, 2D and 3D are supported). + Defeatured MI Instruction Opcodes: + Value Name Description + 1 Instruction Error detected + + + Programming Notes + This error indications cannot be cleared except by reset (i.e., it is a fatal error). + + +1.1.13.3.1 EIR — Error Identity Register + + EIR - Error Identity Register +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W,RO +Size (in bits): 32 +Address: 020B0h +The EIR register contains the persistent values of Hardware-Detected Error Condition bits. Any bit set in this register +will cause the Master Error bit in the ISR to be set. The EIR register is also used by software to clear detected errors +(by writing a 1 to the appropriate bit(s)), except for the unrecoverable bits described.) +DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15:0 Error Identity Bits + Format: Array of Error condition bits See the table titled Hardware-Detected Error Bits. + + + This register contains the persistent values of ESR error status bits that are unmasked via the EMR + register. (See Table Table 3-3. Hardware-Detected Error Bits). The logical OR of all (defined) bits in + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 87 + EIR - Error Identity Register + this register is reported in the Master Error bit of the Interrupt Status Register. In order to clear an error + condition, software must first clear the error by writing a 1 to the appropriate bit(s) in this field. If + required, software should then proceed to clear the Master Error bit of the IIR. Reserved bits are RO. + Value Name + 1h Error occurred + + + Programming Notes + Writing a 1 to a set bit will cause that error condition to be cleared. However, neither the Page Table + Error bit (Bit 4) nor the Instruction Error bit (Bit 0) can be cleared except by reset (i.e., it is a fatal error). + + + +1.1.13.3.2 EMR—Error Mask Register + + EMR - Error Mask Register +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x000000FF +Access: R/W,RO +Size (in bits): 32 +Address: 020B4h +The EMR register is used by software to control which Error Status Register bits are masked or unmasked. +Unmasked bits will be reported in the EIR, thus setting the Master Error ISR bit and possibly triggering a CPU +interrupt, and will persist in the EIR until cleared by software. Masked bits will not be reported in the EIR and +therefore cannot generate Master Error conditions or CPU interrupts. Reserved bits are RO. + DWord Bit Description +0 31:8 Reserved + Format: Must Be One + + + Programming Notes + These bits are not implemented in HW and must be set to ’1’ + 7:0 Error Mask Bits + Format: Array of error condition mask bits See the table titled Hardware-Detected Error Bits. + + + This register contains a bit mask that selects which error condition bits (from the ESR) are + reported in the EIR. + Value Name Description + FFh [Default] + 0h Not Masked Will be reported in the EIR + 1h Masked Will not be reported in the EIR + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 88 + 1.1.13.3.3 ESR—Error Status Register + + ESR - Error Status Register +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 020B8h +The ESR register contains the current values of all Hardware-Detected Error condition bits (these are all by definition +persistent). The EMR register selects which of these error conditions are reported in the persistent EIR (i.e., set bits +must be cleared by software) and thereby causing a Master Error interrupt condition to be reported in the ISR. + DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15:0 Error Status Bits + Format: Array of error condition bits See the table titled Hardware-Detected Error Bits. + + + This register contains the non-persistent values of all hardware-detected error condition bits. + Value Name + 1h Error Condition Detected + + + + +1.1.14 Logical Context Support + +1.1.14.1 BB_ADDR — Batch Buffer Head Pointer + + BB_ADDR - Batch Buffer Head Pointer Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 02140h +Name: RCS Batch Buffer Head Pointer Register +ShortName: RCS_BB_ADDR +Address: 12140h +Name: VCS Batch Buffer Head Pointer Register +ShortName: VCS_BB_ADDR + + +Address: 1A140h + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 89 + BB_ADDR - Batch Buffer Head Pointer Register +Name: VECS Batch Buffer Head Pointer Register +ShortName: VECS_BB_ADDR +Address: 22140h +Name: BCS Batch Buffer Head Pointer Register +ShortName: BCS_BB_ADDR +This register contains the current DWord Graphics Memory Address of the last-initiated batch buffer. + Programming Notes +Programming Restriction: This register should NEVER be programmed by driver. This is for HW internal use only. +DWord Bit Description +0 31:3 Batch Buffer Head Pointer + + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + Format: GraphicsAddress[31:3] + This field specifies the DWord-aligned Graphics Memory Address where the last initiated Batch Buffer is + currently fetching commands. If no batch buffer is currently active, the Valid bit will be 0 and this field will + be meaningless. + + 31:2 Batch Buffer Head Pointer + + Source: RenderCS + Format: GraphicsAddress[31:2] + This field specifies the DWord-aligned Graphics Memory Address where the last initiated Batch Buffer is + currently fetching commands. If no batch buffer is currently active, the Valid bit will be 0 and this field will + be meaningless. + + 2 Reserved + + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + Format: MBZ + 1 Reserved + Format: MBZ + 0 Valid + Format: U1 + + + Value Name Description + 0h Invalid [Default] Batch buffer Invalid + 1h Valid Batch buffer Valid + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 90 + 1.1.14.2 BB_STATE – Batch Buffer State Register + + BB_STATE - Batch Buffer State Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 02110h +Name: RCS Batch Buffer State Register +ShortName: RCS_BB_STATE + + This register contains the attributes of the current batch buffer initiated from the Ring Buffer. These include the + security indicator. + + This register should not be written by software. These fields should only get written by a context restore. Software + should always set these fields via the MI_BATCH_BUFFER_START command when initiating a batch buffer. + + This register is saved and restored with context. + DWord Bit Description +0 31:9 Reserved + Format: MBZ + 8 Reserved + + Format: MBZ + 7 Reserved + + Format: MBZ + 5 Address Space Indicator + + + + + Value Name Description + 0h GGTT [Default] This batch buffer is located in GGTT memory + 1h PPGTT This batch buffer is located in PPGTT memory. + 3:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 91 + 1.1.14.3 CCID—Current Context Register + + CCID - Current Context Register +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02180h +This register contains the current logical rendering context address associated with the ring buffer in ring buffer mode +of scheduling. This register contents are not valid in Exec-List mode of scheduling. + Programming Notes +The CCID register must not be written directly (via MMIO) unless the Command Streamer is completely idle (i.e., the +Ring Buffer is empty and the pipeline is idle). Note that, under normal conditions, the CCID register should only be +updated from the command stream using the MI_SET_CONTEXT command. + DWord Bit Description +0 31:12 Logical Render Context Address (LRCA) + Default Value: 0h + Format: GraphicsAddress[31:11] + This field contains the 4 KB-aligned Graphics Memory Address of the current Logical Rendering + Context. Bit 11 MBZ. + + 11:10 Reserved + Format: MBZ + 8 Reserved + Format: Must Be One + 7:4 Reserved + Format: MBZ + 3 Extended State Save Enable + Format: Enable + If set, the extended state identified in the Logical Context Data section of the Memory Data Formats + chapter, is saved as part of switching away from this logical context. + + 2 Extended State Restore Enable + Format: Enable + If set, the extended state identified in the Logical Context Data section of the Memory Data Formats + chapter, was loaded (or restored) as part of switching to this logical context. + + 1 Reserved + Format: MBZ + 0 Valid + Format: U1 + + + Value Name Description + 0h Invalid The other fields of this register are invalid. A switch away from the context will + [Default] not invoke a context save operation. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 92 + CCID - Current Context Register + 1h Valid The other fields of this register are valid, and a switch from the context will + invoke the normal context save/restore operations. + + + +1.1.14.4 CXT_SIZE—Context Sizes + + CXT_SIZE - Context Sizes +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x48A7B8CD +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 021A8h +The actual size of a logical rendering context is the amount of data stored/restored during a context switch and is +measured in 64B cache lines. This register will be power context save/restored. Note that this register will default to +the correct value, so software should not have to modify it. + DWord Bit Description +0 31:25 Power Context Size + Default Value: 24h + This field indicates the Power context data that need to be save restored. + + 24:22 Ring Context Size + Default Value: 2h + This field indicates the Ring context data that need to be save restored. + + 21:16 Render Context Size + Default Value: 27h + This field indicates the render context data that need to be save restored when extended mode is not + enabled for a context. + + 15:9 Extended Context Size + Default Value: 5Ch + This field indicates the render context data that need to be save restored when extended mode is + enabled for a context. Note: Render context is subset of this context. + + 8:6 GT1 Mode + Default Value: 3h + This field indicates the amount of data that need not be save/restored from render context in GT1 + mode. Note: This is the amount of data not save/restored from TDL and SC in GT1 mode. + + 5:0 VF State Context Size + Default Value: Dh + This field indicates the amount of VF unit data context save/restored in cachelines. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 93 + 1.1.14.5 MTCH_CID_RST – Matched Context ID Reset Register + + MTCH_CID_RST - Matched Context ID Reset Register +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 0222Ch + + +This register is used to generate a Context ID specific reset (Render Only). To initiate a reset, the register is written +with the pending bit set. Hardware compares the current context ID with the register and on match generates a +Render Only reset. After reset is complete, HW clears the pending bit and can be programmed to generate an +interrupt. The match bit is set. If the current context ID does not match this register, the pending bit is reset and an +interrupt is generated. The match bit is reset.The match indicates the result of the last comparison, and its valid only +when pending bit is zero.Please see MCIDRST interrupt bit assignment in the Interrupt Control Registers. + DWord Bit Description +0 31:12 Match Context ID + Format: U20 + Contains the context ID to be compared with the currently running context ID. + + 11:2 Reserved + Format: MBZ + 1 Match + Format: U20 + This bit indicates the result of the match operation; 1 means the Current Context ID matches the + Match Context ID field. + + 0 Pending + Format: U20 + This bit indicates that a matched context ID reset is pending. The bit should be set when the register + is written (in order to have a pending MTCH_CID_RST request), and will be reset by hardware to + indicate that the operation is completed (Either with a match or mismatch) + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 94 + 1.1.14.6 SYNC_FLIP_STATUS – Wait for Event and Display Flip Flags Register + + SYNC_FLIP_STATUS - Wait For Event and Display Flip Flags + Register +Register Space: MMIO: 0/2/0 +Project: All +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 022D0h +Name: RCS Wait For Event and Display Flip Flags Register +ShortName: RCS_SYNC_FLIP_STATUS + + +This register is the saved value of what wait for events are still valid. This register is part of context save and restore +for RC6 feature. + Programming Notes +Programming Restriction: + This register should NEVER be programmed by SW, this is for HW internal use only. +DWord Bit Description +0 31 Reserved + Format: MBZ + 30 Display Plane A Asyncronous Display Flip Pending + Format: Enable + This field enables a wait for the duration of a Display Plane A “Flip Pending” condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the Device + Programming Interface chapter of MI Functions. + + 29 Display Plane A Syncronous Flip Display Pending + Format: Enable + This field enables a wait for the duration of a Display Plane A “Flip Pending” condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the Device + Programming Interface chapter of MI Functions. + + 28 Display Sprite A Syncronous Flip Display Pending + Format: Enable + This field enables a wait for the duration of a Display Sprite A “Flip Pending” condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition in the Device + Programming Interface chapter of MI Functions. + + 27 Reserved + Format: MBZ + 26 Display Plane B Asyncronous Display Flip Pending + Format: Enable + This field enables a wait for the duration of a Display Plane B “Flip Pending” condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 95 + SYNC_FLIP_STATUS - Wait For Event and Display Flip Flags + Register + now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the Device + Programming Interface chapter of MI Functions. + + 25 Display Plane B Syncronous Flip Display Pending + Format: Enable + This field enables a wait for the duration of a Display Plane B Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the Device + Programming Interface chapter of MI Functions. + + 24 Display Sprite B Syncronous Flip Display Pending + Format: Enable + This field enables a wait for the duration of a Display Sprite B Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition in the Device + Programming Interface chapter of MI Functions. + + 23 Display Plane A Asyncronous Performance Flip Pending Wait Enable + Source: RenderCS + Format: Enable + This field enables a wait for the duration of a Display Plane A Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the Device + Programming Interface chapter of MI Functions. + + 22 Display Plane A Asyncronous Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Plane A Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the Device + Programming Interface chapter of MI Functions. + + 21 Display Plane A Syncronous Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Plane A Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the Device + Programming Interface chapter of MI Functions. + + 20 Display Sprite A Syncronous Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Sprite A Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition in the Device + Programming Interface chapter of MI Functions. + + 19 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 96 + SYNC_FLIP_STATUS - Wait For Event and Display Flip Flags + Register + 18 Display Pipe A Scan Line Wait Enable + Format: Enable + This field enables a wait while a Display Pipe A Scan Line condition exists. This condition is defined as + the the start of the scan line specified in the Pipe A Display Scan Line Count Range Compare Register. + See Scan Line Event in the Device Programming Interface chapter of MI Functions. + + 17 Display Pipe A Vertical Blank Wait Enable + Format: Enable + This field enables a wait until the next Display Pipe A Vertical Blank event occurs. This event is defined as + the start of the next Display Pipe A vertical blank period. Note that this can cause a wait for up to an entire + refresh period. See Vertical Blank Event (See Programming Interface). + + 16 Display Pipe A H Blank Wait Enable + + Format: Enable + This field enables a wait until the start of next Display Pipe A Horizontal Blank event occurs. This event is + defined as the start of the next Display A Horizontal blank period. Note that this can cause a wait for up to + a line. See Horizontal Blank Event in the Device Programming Interface chapter of MI Functions. + + 15 Display Plane B Asyncronous Performance Flip Pending Wait Enable + Source: RenderCS + Format: Enable + This field enables a wait for the duration of a Display Plane B Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the Device + Programming Interface chapter of MI Functions. + + 14 Display Plane B Asyncronous Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Plane B Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the Device + Programming Interface chapter of MI Functions. + + 13 Display Plane B Syncronous Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Plane B Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the Device + Programming Interface chapter of MI Functions. + + 12 Display Sprite B Syncronous Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Sprite B Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address has + now been loaded into the active front buffer registers). See Display Flip Pending Condition in the Device + Programming Interface chapter of MI Functions. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 97 + SYNC_FLIP_STATUS - Wait For Event and Display Flip Flags + Register + 11 Reserved + Format: MBZ + 10 Display Pipe B Scan Line Wait Enable + Format: Enable + This field enables a wait while a Display Pipe B Scan Line condition exists. This condition is defined as + the the start of the scan line specified in the Pipe B Display Scan Line Count Range Compare Register. + See Scan Line Event in the Device Programming Interface chapter of MI Functions. + + 9 Display Pipe B Vertical Blank Wait Enable + Format: Enable + This field enables a wait until the next Display Pipe B Vertical Blank event occurs. This event is defined as + the start of the next Display Pipe B vertical blank period. Note that this can cause a wait for up to an entire + refresh period. See Vertical Blank Event (See Programming Interface). + + 8 Display Pipe B H Blank Wait Enable + + Format: Enable + This field enables a wait until the start of next Display Pipe B Horizontal Blank event occurs. This event is + defined as the start of the next Display B Horizontal blank period. Note that this can cause a wait for up to + a line. See Horizontal Blank Event in the Device Programming Interface chapter of MI Functions. + + 7:5 Reserved + Format: MBZ + 4:0 Condition Code Wait Select + + This field enables a wait for the duration that the corresponding condition code is active. These enable + select one of 15 condition codes in the EXCC register, that cause the parser to wait until that condition- + code in the EXCC is cleared. + Value Name Description + 0h Not Enabled Condition Code Wait not enabled + 1h-5h Enabled Condition Code select enabled; selects one of 5 codes, 0 – 4 + 6h-15h Reserved + + + Programming Notes + Note that not all condition codes are implemented. The parser operation is UNDEFINED if an + unimplemented condition code is selected by this field. The description of the EXCC register (Memory + Interface Registers) lists the codes that are implemented. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 98 + 1.1.14.7 SYNC_FLIP_STATUS_1 – Wait for Event and Display Flip Flags Register + 1 + + SYNC_FLIP_STATUS_1 - Wait For Event and Display Flip Flags + Register 1 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 022D4h +Name: RCS Wait For Event and Display Flip Flags Register 1 +ShortName: RCS_SYNC_FLIP_STATUS_1 +This register is the saved value of what wait for events are still valid. This register is part of context save and restore +for RC6 feature. +DWord Bit Description +0 31:27 Reserved + Format: MBZ + 26:15 Reserved + + Format: MBZ + 11 SyncFlush Status + + Format: Enable + This field toggles on completion of sync flush. This bit toggle generates Interrupt and also reports + interrupt status to HWSP on sync flush done. + + 10 Display Plane C Asyncronous Display Flip Pending + Format: Enable + This field enables a wait for the duration of a Display Plane C Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 9 Display Plane C Syncronous Flip Display Pending + Format: Enable + This field enables a wait for the duration of a Display Plane C Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 8 Display Sprite C Syncronous Flip Display Pending + Format: Enable + This field enables a wait for the duration of a Display Sprite C Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition in the + Device Programming Interface chapter of MI Functions. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 99 + SYNC_FLIP_STATUS_1 - Wait For Event and Display Flip Flags + Register 1 + 7 Display Plane C Asyncronous Performance Flip Pending Wait Enable + Source: RenderCS + Format: Enable + This field enables a wait for the duration of a Display Plane C Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 6 Display Plane C Asyncronous Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Plane C “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 5 Display Plane C Syncronous Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Plane C Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 4 Display Sprite C Syncronous Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Sprite C Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition in the + Device Programming Interface chapter of MI Functions. + + 3 Reserved + Format: MBZ + 2 Display Pipe C Scan Line Wait Enable + Format: Enable + This field enables a wait while a Display Pipe C Scan Line condition exists. This condition is defined as + the the start of the scan line specified in the Pipe C Display Scan Line Count Range Compare Register. + See Scan Line Event in the Device Programming Interface chapter of MI Functions. + + 1 Display Pipe C Vertical Blank Wait Enable + Format: Enable + This field enables a wait until the next Display Pipe C Vertical Blank event occurs. This event is defined + as the start of the next Display Pipe C vertical blank period. Note that this can cause a wait for up to an + entire refresh period. See Vertical Blank Event (See Programming Interface). + + 0 Display Pipe C H Blank Wait Enable + + Format: Enable + This field enables a wait until the start of next Display Pipe C Horizontal Blank event occurs. This event + is defined as the start of the next Display C Horizontal blank period. Note that this can cause a wait for + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 100 + SYNC_FLIP_STATUS_1 - Wait For Event and Display Flip Flags + Register 1 + up to a line. See Horizontal Blank Event in the Device Programming Interface chapter of MI Functions. + + + + +1.1.15 Pipelines Statistics Counter Registers +These registers keep continuous count of statistics regarding the 3D pipeline. They are saved and +restored with context but should not be changed by software except to reset them to 0 at context creation +time. These registers may be read at any time; however, to obtain a meaningful result, a pipeline flush +just prior to reading the registers is necessary in order to synchronize the counts with the primitive stream. + +1.1.15.1 IA_VERTICES_COUNT — Reported Vertices Counter + + IA_VERTICES_COUNT +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02310h +This register stores the count of vertices processed by VF. This register is part of the context save and restore. +DWord Bit Description +0 63:0 IA Vertices Count Report + Total number of vertices fetched by the VF stage. This count is updated for every input vertex as long as + Statistics Enable is set in VF_STATE (see the Vertex Fetch Chapter in the 3D Volume.) + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 101 + 1.1.15.2 IA_PRIMITIVES_COUNT — Reported Vertex Fetch Output Primitives + Counter + + IA_PRIMITIVES_COUNT +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02318h +This register stores the count of primitives generated by VF. This register is part of the context save and restore. +DWord Bit Description +0 63:0 IA Primitives Count Report + Total number of primitives output by the Vertex Fetch (IA) stage. This count is updated for every + primitive output by the VF stage, as long as Statistics Enable is set in VF_STATE (see the Vertex Fetch + Chapter in the 3D Volume.) + + + +1.1.15.3 VS_INVOCATION_COUNT— Reported Vertex Shader Invocation + Counter + + VS_INVOCATION_COUNT +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02320h +This register stores the value of the vertex count shaded by VS. This register is part of the context save and restore. +DWord Bit Description +0 63:0 VS Invocation Count Report + Number of vertices that are dispatched as threads by the VS stage. Updated only when Statistics + Enable is set in VS_STATE (see the Vertex Shader Chapter in the 3D Volume.) + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 102 + 1.1.15.4 HS_INVOCATION_COUNT— Reported Hull Shader Invocation Counter + + HS_INVOCATION_COUNT +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02300h +This register stores the number of patch objects processed by the HS unit. E.g., A PATCHLIST_2 topology with 6 +vertices would cause this counter to increment by 3 (there are 3 2-vertex patch objects in that topology).This register +is part of the context save and restore. + DWord Bit Description +0 63:0 HS Invocation Count + Number of patch objects processed by the HS stage. Updated only when HS Enable and HS + Statistics Enable are set in 3DSTATE_HS + + + +1.1.15.5 DS_INVOCATION_COUNT— Reported Domain Shader Invocation + Counter + + DS_INVOCATION_COUNT +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02308h +This register stores the number of domain points shaded by the DS threads. Domain points which hit in the DS cache +will not cause this register to increment. Note that the spawning of a DS thread which shades two domain points will +cause this counter to increment by two.This register is part of the context save and restore. + DWord Bit Description +0 63:0 DS Invocation Count + Number of domain points shaded by the DS threads. Updated only when DS Function Enable and + Statistics Enable are set in 3DSTATE_DS + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 103 + 1.1.15.6 GS_INVOCATION_COUNT — Reported Geometry Shader Thread + Invocation Counter + + GS_INVOCATION_COUNT +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02328h +This register stores the number of objects that are part of geometry shader threads. This register is part of the +context save and restore. +DWord Bit Description +0 63:0 GS Invocation Count + Number of objects that are dispatched as a geometry shader threads invoked by the GS stage. Updated + only when Statistics Enable is set in GS_STATE (see the Geometry Shader Chapter in the 3D + Volume.) + + + +1.1.15.7 GS_PRIMITIVES_COUNT — Reported Geometry Shader Output + Primitives Counter + + GS_PRIMITIVES_COUNT +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02330h +This register reflects the total number of primitives that have been output by the Geometry Shader stage. This +register is part of the context save and restore. +DWord Bit Description +0 63:0 GS Primitives Count + Total number of primitives output by the geometry stage. Updated only when Statistics Enable is set in + GS_STATE (see the Geometry Shader Chapter in the 3D Volume.) + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 104 + 1.1.15.8 CL_INVOCATION_COUNT— Reported Clipper Thread Invocation + Counter + + CL_INVOCATION_COUNT +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02338h +This register stores the count of objects entering the Clipper stage. This register is part of the context save and +restore. +DWord Bit Description +0 63:0 CL Invocation Count Report + Number of objects entering the clipper stage. Updated only when Statistics Enable is set in + CLIP_STATE (see the Clipper Chapter in the 3D Volume.) + + + +1.1.15.9 CL_PRIMITIVES_COUNT— Reported Clipper Output Primitives Counter + + CL_PRIMITIVES_COUNT +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02340h +This register reflects the total number of primitives that have been output by the clipper. This register is part of the +context save and restore. +DWord Bit Description +0 63:0 Clipped Primitives Output Count + Total number of primitives output by the clipper stage. This count is updated for every primitive output by + the clipper stage, as long as Statistics Enable is set in SF_STATE (see the Clipper and SF Chapters in + the 3D Volume.) + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 105 + 1.1.15.10 PS_INVOCATION_COUNT— Reported Pixels Shaded Counter + + PS_INVOCATION_COUNT +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02348h +DWord Bit Description +0 63:0 PS Invocation Count + Reflects a count of the total number of pixels (including unlit “helper pixels” within a subspan that need to + go through the PS shader to provide 2x2 gradients) that are dispatched to pixel shader invocations while + Statistics Enable is set in the Windower. See the Windower chapter of the 3D volume for details. This + count will generally be much greater than the actual count of PS threads since a single thread may + process up to 32 pixels. + + + +1.1.15.11 PS_DEPTH_COUNT — Reported Pixels Passing Depth Test Counter + + PS_DEPTH_COUNT +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02350h +This register stores the value of the count of pixels that have passed the depth test. This register is part of the +context save and restore. Note that the value of this register can be obtained in a pipeline-synchronous fashion +without a pipeline flush by using the 3DCONTROL command. See 3D Overview in the 3D volume. +DWord Bit Description +0 63:0 Depth Count + This register reflects the total number of pixels that have passed the depth test (i.e., will be visible). All + pixels are counted when Statistics Enable is set in the Windower State. See the Windower chapter of the + 3D volume for details. Pixels that pass the depth test but fail the stencil test will not be counted. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 106 + 1.1.15.12 TIMESTAMP — Reported Timestamp Count + + TIMESTAMP - Reported Timestamp Count +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: RO. This register is not set by the context restore. +Size (in bits): 64 +Address: 02358h +This register provides an elapsed real-time value that can be used as a timestamp for GPU events over short periods +of time. Note that the value of this register can be obtained in a 3D pipeline-synchronous fashion without a pipeline +flush by using the PIPE_CONTROL command. See 3D Geometry Pipeline in the “3D and Media” volume.This +register (effectively) counts at a constant frequency by adjusting the increment amount according to the actual +reference clock frequency. SW therefore does not need to know the reference clock frequency.This register is not +reset by a graphics reset. It will maintain its value unless a full chipset reset is performed. + Note: This timestamp register reflects the value of the PCU TSC. The PCU TSC counts 10ns increments; this +timestamp reflects bits 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5 hours). + DWord Bit Description +0 63:36 Reserved + Format: MBZ + 35:0 Timestamp Value + Format: U32 + This register toggles every 80 ns. The upper 28 bits are zero. + + + + +1.1.15.13 SO_NUM_PRIMS_WRITTEN[0:3]— Stream Output Num Primitives + Written Counters + + SO_NUM_PRIMS_WRITTEN[0:3] - Stream Output Num Primitives + Written Counter +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Address: 05200h-0521Fh +There is one 64-bit register for each of the 4 supported streams:5200h-5207h SO_NUM_PRIMS_WRITTEN0 (for +Stream Out Stream #0)5208h-520Fh SO_NUM_PRIMS_WRITTEN1 (for Stream Out Stream #1)5210h-5217h +SO_NUM_PRIMS_WRITTEN2 (for Stream Out Stream #2)5218h-521Fh SO_NUM_PRIMS_WRITTEN3 (for Stream +Out Stream #3)These registers are used to count the number of primitives (aka objects: points, lines, triangles) which +the SO stage has successfully written to a particular “stream’s” Streamed Vertex Output buffers, subject to buffer +overflow detection. (See the Stream Output section of the 3D pipeline volume).These registers are part of the context +save and restore. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 107 + DWord Bit Description +0 63:0 Num Prims Written Count + Format: U64 + This count is incremented (by one) every time a GS thread outputs a DataPort Streamed Vertex Buffer + Write message with the Increment Num Prims Written bit set in the message header (see the Geometry + Shader and Data Port chapters in the 3D Volume.) + + + + +1.1.15.14 SO_PRIM_STORAGE_NEEDED[0:3] —Stream Output Primitive Storage + Needed Counters + + SO_PRIM_STORAGE_NEEDED[0:3] - Stream Output Primitive + Storage Needed Counters +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: RO. This register is set by the context restore. +Size (in bits): 64 +Address: 05240h-0525Fh +There is one 64-bit register for each of the 4 supported streams: + +5240h-5247h SO_PRIM_STORAGE_NEEDED0 (for Stream Out Stream #0) +5248h-524Fh SO_PRIM_STORAGE_NEEDED1 (for Stream Out Stream #1) +5250h-5257h SO_PRIM_STORAGE_NEEDED2 (for Stream Out Stream #2) +5258h-525Fh SO_PRIM_STORAGE_NEEDED3 (for Stream Out Stream #3) + +These registers are used to count the number of primitives (aka objects: points, lines, triangles) which the SO stage +has or would have written to a particular “stream’s” Streamed Vertex Output buffers if all buffers had been large +enough to accommodate the writes. (See the Stream Output section of the 3D pipeline volume). + +These registers are part of the context save and restore. +DWord Bit Description +0 63:0 Prim Storage Needed Count + + Format: U64 + This count is incremented (by one) by the SOL stage for each object (point, line, triangle) it writes or + attempts to write to the corresponding stream’s output buffers. The count is not affected by the actual + number of buffers bound to the stream. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 108 + 1.1.15.15 SO_WRITE_OFFSET[0:3] —Stream Output Write Offsets + + SO_WRITE_OFFSET[0:3] - Stream Output Write Offsets +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: RW. This register is set by the context restore. +Size (in bits): 32 +Address: 05280h-0528Fh + +There is one R/W 32-bit register for each of the 4 supported stream output buffer slots: + +5280h-5283h SO_WRITE_OFFSET0 (for Stream Out Buffer #0) + +5284h-5287h SO_ WRITE_OFFSET1 (for Stream Out Buffer #1) + +5288h-528Bh SO_ WRITE_OFFSET2 (for Stream Out Buffer #2) + +528Ch-528Fh SO_ WRITE_OFFSET3 (for Stream Out Buffer #3) + + These registers are used to set and track a DWord-granular Write Offset for each of the 4 Stream Output Buffer + slots. Software can directly write them via MI_LOAD_REGxxx commands. The SOL stage will increment them as + part of stream output processing. Software can cause them to be written to memory via MI_STORE_REGxxx + commands. (See the Stream Output section of the 3D pipeline volume). +These registers are part of the context save and restore. + Programming Notes +  Software must ensure that no HW stream output operations can be in process or otherwise pending at the + point that the MI_LOAD/STORE commands are processed. This will likely require a pipeline flush. +  The SOL stage will effectively advance the write offset by the buffer’s Surface Pitch after each vertex is written + (assuming no overflow is detected in any targetted SO buffer). Under “normal” conditions one would expect + software to initialize the WriteOffset to some (possibly zero) multiple of Surface Pitch in order to align vertex + writes to the buffer’s Base Address, though it is not required to do so. + + +DWord Bit Description +0 31:2 Write Offset + + Format: U30 + This field contains a DWord offset from the corresponding SO buffer’s Base Address value. The SOL + stage uses this value as a write offset when performing writes to the buffer. The SOL stage will + increment this value as a part of performing stream output to the buffer. Note that the SOL stage uses + the buffer’s Surface Pitch to advance the Write Offset, without regard to the buffer’s Base Address (see + Programming Notes above). + + 1:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 109 + 1.1.16 Predicate Render Registers + +1.1.16.1 MI_PREDICATE_SRC0 - Predicate Rendering Temporary Register0 + + MI_PREDICATE_SRC0 - Predicate Rendering Temporary Register0 +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Address: 02400h-02407h + +DWord Bit Description +0 63:0 MI_PREDICATE_SRC0 + This register is a temporary register for Predicate Rendering. See Predicate Rendering section for more + details. + + + +1.1.16.2 1.1.16.2 MI_PREDICATE_SRC1– Predicate Rendering Temporary + Register1 + + MI_PREDICATE_SRC1 - Predicate Rendering Temporary Register1 +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Address: 02408h-0240Fh +DWord Bit Description +0 63:0 MI_PREDICATE_SRC1 + This register is a temporary register for Predicate Rendering. See Predicate Rendering section for more + details. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 110 + 1.1.16.3 MI_PREDICATE_DATA– Predicate Rendering Data Storage + + MI_PREDICATE_DATA - Predicate Rendering Data Storage +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Address: 02410h-02417h + +DWord Bit Description +0 63:0 MI_PREDICATE_DATA + This register is used either as computed value based off the MI_PREDICATE_SRC0 and + MI_PREDICATE_SRC1 or a temporary register. See Predicate Rendering section for more details. + + + +1.1.16.4 MI_PREDICATE_RESULT – Predicate Rendering Data Result + + MI_PREDICATE_RESULT - Predicate Rendering Data Result +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02418h + DWord Bit Description +0 31:1 Reserved + Format: MBZ + 0 MI_PREDICATE_RESULT + This bit is the result of the last MI_PREDICATE. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 111 + 1.1.17 AUTO_DRAW Registers + +1.1.17.1 3DPRIM_END_OFFSET – Auto Draw End Offset + + 3DPRIM_END_OFFSET - Auto Draw End Offset +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02420h-02423h + +DWord Bit Description +0 31:0 End Offset + Format: U32 + This register is used to store the end offset value used by the Vertex Fetch to determine when to stop + processing the 3D_PRIMITIVE command. This register is valid when the End Offset Enable is set in the + 3D_PRIMITIVE command. + + + + +1.1.17.2 3DPRIM_START_VERTEX – Load Indirect Start Vertex + + 3DPRIM_START_VERTEX - Load Indirect Start Vertex +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02430h-02433h + +DWord Bit Description +0 31:0 Start Vertex + Format: U32 + This register is used to store the Start Vertex of the 3D_PRIMITIVE command when Load Indirect + Enable is set. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 112 + 1.1.17.3 3DPRIM_VERTEX_COUNT – Load Indirect Vertex Count + + 3DPRIM_VERTEX_COUNT - Load Indirect Vertex Count +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02434h-02437h + +DWord Bit Description +0 31:0 Vertex Count + Format: U32 + This register is used to store the Vertex Count of the 3D_PRIMITIVE command when Load Indirect + Enable is set. + + + + +1.1.17.4 3DPRIM_INSTANCE_COUNT – Load Indirect Instance Count + + 3DPRIM_INSTANCE_COUNT - Load Indirect Instance Count +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02438h-0243Bh + +DWord Bit Description +0 31:0 Instance Count + This register is used to store the Instance Count of the 3D_PRIMITIVE command when Load Indirect + Enable is set. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 113 + 1.1.17.5 3DPRIM_START_INSTANCE – Load Indirect Start Instance + + 3DPRIM_START_INSTANCE - Load Indirect Start Instance +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 0243Ch-0243Fh + +DWord Bit Description +0 31:0 Start Vertex + Format: U32 + This register is used to store the Start Instance of the 3D_PRIMITIVE command when Load Indirect + Enable is set. + + + + +1.1.17.6 3DPRIM_BASE_VERTEX – Load Indirect Base Vertex + + 3DPRIM_BASE_VERTEX - Load Indirect Base Vertex +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02440h-02443h + +DWord Bit Description +0 31:0 Base Vertex + Format: S31 + This register is used to store the Base Vertex of the 3D_PRIMITIVE command when Load Indirect + Enable is set. + + + + +1.1.18 MMIO Registers for GPGPU Indirect Dispatch +This register is normally written with the MI_LOAD_REGISTER_MEMORY command rather than from the +CPU. +These registers should not be written with 0 for these projects. To avoid this, the +MI_LOAD_REGISTER_MEMORY command which writes them from an address in memory which was + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 114 + written by a previous GPGPU_WALKER command will need to be checked with the following command +sequence. The commands in red are the additional commands to implement the workaround: +MI_LOAD_REGISTER_MEMORY Xaddress, GPGPU_DISPATCHDIMX +MI_CONDITIONAL_BATCH_BUFFER_END Xaddress, 0 // Compare X dimension to 0, end batch buffer if +0 +MI_LOAD_REGISTER_MEMORY GPGPU_DISPATCHDIMY +MI_CONDITIONAL_BATCH_BUFFER_END Yaddress, 0 // Compare Y dimension to 0, end batch buffer if +0 +MI_LOAD_REGISTER_MEMORY GPGPU_DISPATCHDIMZ +MI_CONDITIONAL_BATCH_BUFFER_END Zaddress, 0 // Compare Z dimension to 0, end batch buffer if +0 +GPGPU_WALKER // Walker with indirect dispatch +This way, if any dimension is 0 we would not execute the GPGPU_WALKER. This has the limitation that +the indirect GPGPU_WALKER has to be the last WALKER of the batch buffer. + +1.1.18.1 GPGPU_DISPATCHDIM(X/Y/Z) - GPGPU Dispatch Dimension (X/Y/Z) +These registers are normally written with the MI_LOAD_REGISTER_MEMORY command rather than +from the CPU. + + GPGPU_DISPATCHDIMX - GPGPU Dispatch Dimension X +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02500h + DWord Bit Description +0 31:0 Dispatch Dimension X + Format: U32 + The number of thread groups to be dispatched in the X dimension (max x + 1). + Value Name Project + 1,FFFFFFFFh + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 115 + GPGPU_DISPATCHDIMY - GPGPU Dispatch Dimension Y +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02504h + DWord Bit Description +0 31:0 Dispatch Dimension Y + Format: U32 + The number of thread groups to be dispatched in the Y dimension (max y + 1 + Value Name Project + 1,FFFFFFFFh + + + + + GPGPU_DISPATCHDIMZ - GPGPU Dispatch Dimension Z +Register Space: MMIO: 0/2/0 + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 02508h + DWord Bit Description +0 31:0 Dispatch Dimension Z + Format: U32 + The number of thread groups to be dispatched in the Zdimension (max Z + 1) + Value Name Project + 1,FFFFFFFFh + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 116 + 1.1.18.2 TS_GPGPU_THREADS_DISPATCHED – Count Active Channels + Dispatched + + TS_GPGPU_THREADS_DISPATCHED - Count Active Channels + Dispatched +Register Space: MMIO: 0/2/0 +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Trusted Type: 1 +Address: 02290h +This register is used to count the number of active channels that TS sends for dispatch. For each dispatch the active +bits in the execution mask are summed and added to this register. This register is reset when a write occurs to 2290h + DWord Bit Description +0 63:0 GPGPU_THREADS_DISPATCHED + Format: U64 + This count is increased by the number of active bits in the execution mask each time the TS sends a + GPGPU dispatch. + + + + +1.1.19 Memory Interface Registers + +1.1.19.1 PWRCTX_REST_DONE - Power Context Restore Done + + PWRCTX_REST_DONE - Power Context Restore Done +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04000h-04003h + + Power Context Restore Done + DWord Bit Description +0 31:16 Mask Bits + Default Value: 0000h + Access: RO + + Mask Bits + + 15:1 Extra Mask Bits + Default Value: 000000000000000b + Access: R/W + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 117 + PWRCTX_REST_DONE - Power Context Restore Done + Extra Mask Bits + + 0 Restore Done + Default Value: 0b + Access: R/W + + GAM - CS will write to indicate ‘restore done’ + + It is a config message register between CS & GAM + + + + +1.1.19.2 WR_WATERMARK - Write Watermark + + WR_WATERMARK - Write Watermark +Register Space: MMIO: 0/2/0 + + +Default Value: 0x000FFEA4 +Address: 04028h-0402Bh + + Write Watermark +DWord Bit Description +0 31:20 Counter Extra Bits + Default Value: 000000000000b + Access: R/W + + Counter Extra Bits + + 19 Watermark Timeout Enable + Default Value: 1b + Access: R/W + + Watermark timeout enable. + + + + + 18:8 Watermark Timeout + Default Value: 11111111110b + Access: R/W + + Number of clocks that the write pipe queue is allowed to keep a ready write cycle, without reads or + writes to the queue. Once this value is met, and if the feature is enabled, the watermark will be + considered reach, and all pending write requests will be issued. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 118 + WR_WATERMARK - Write Watermark + 7 Watermark En + Default Value: 1b + Access: R/W + + Enable write request grouping + + + + + 6:0 High Watermark + Default Value: 0100100b + Access: R/W + + This is the number of write requests to be collected before initiating a write burst. Once a burst is + initiated, it will continue until all the available writes are requested. + + + + +1.1.19.3 GFX_PRIO_CTRL - GFX Arbiter Client Priority Control + + GFX_PRIO_CTRL - GFX Arbiter Client Priority Control +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00011D10 +Address: 0402Ch-0402Fh + + GFX Arbiter Client Priority Control + DWord Bit Description +0 31:17 Extra 402C Register + Default Value: 000000000000000b + Access: R/W + + Extra 402C Register + + 16:12 Read Rstrm Max Reject + Default Value: 10001b + Access: R/W + + Read Rstrm Max Reject + + + + + 11:9 gapc_gam_c_priority + Default Value: 110b + Access: R/W + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 119 + GFX_PRIO_CTRL - GFX Arbiter Client Priority Control + gapc_gam_c_priority - Lowest Bit [9] is not used + + + + + 8:6 gapc_gam_z_priority + Default Value: 100b + Access: R/W + + gapc_gam_z_priority - Lowest Bit [6] is not used + + + + + 5:3 gapc_gam_l3_priority + Default Value: 010b + Access: R/W + + gapc_gam_l3_priority - Lowest Bit [3] is not used + + + + + 2:0 gafm_gam_priority + Default Value: 000b + Access: R/W + + Client Priority control bitss + + gafm_gam_priority - Lowest Bit [0] is not used + + + + +1.1.19.4 1.1.19.4 GFX_PEND_TLB_0 - Max Outstanding Pending TLB Requests + 0 + + GFX_PEND_TLB_0 - Max Outstanding Pending TLB Requests 0 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04034h-04037h + +GFX_PEND_TLB_0 - Max Outstanding Pending TLB Requests 0 + + +DWord Bit Description +0 31 TEX Limit Enable Bit + Default Value: 0b + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 120 + GFX_PEND_TLB_0 - Max Outstanding Pending TLB Requests 0 + Access: R/W + + TEX Limit Enable bit Project: All Format: U1 + + This bit is used to enable the pending TLB requests limitation function for the Texture Cache + + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + + + + 30 Reserved Bit + Default Value: 0b + Access: RO + + Reserved Project: All Format: MBZ + + + + + 29:24 TEX TLB Limit Count + Default Value: 000000b + Access: R/W + + TEX TLB Limit Count Project: All Format: U6 + + This is the MAX number of Allowed internal pending read requests which require a TLB read + + + + + 23 DC Limit Enable bit + Default Value: 0b + Access: R/W + + DC Limit Enable bit Project: All Format: U1 + + This bit is used to enable the pending TLB requests limitation function for the Instruction Cache. + + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + + + + 22 Reserved Bit + Default Value: 0b + Access: RO + + Reserved Project: All Format: MBZ + + + + + 21:16 DC TLB Limit Count + Default Value: 000000b + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 121 + GFX_PEND_TLB_0 - Max Outstanding Pending TLB Requests 0 + Access: R/W + + DC TLB Limit Count Project:All Format:U6 + + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + + + + 15 VF Limit Enable bit + Default Value: 0b + Access: R/W + + VF Limit Enable bit Project: All Format: U1 + + This bit is used to enable the pending TLB requests limitation function for the Vertex Fetch + + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + + + + 14 Reserved Bit + Default Value: 0b + Access: RO + + Reserved Project: All Format: MBZ + + 13:8 VF TLB Limit Count + Default Value: 000000b + Access: R/W + + VF TLB Limit Count Project: All Format: U6 + + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + + + + 7 VMC Limit Enable bit + Default Value: 0b + Access: R/W + + VMC Limit Enable bit Project: All Format: U1 + + This bit is used to enable the pending TLB requests limitation function for the Video Motion + Compensation . When set, the number of internal pending read requests which require a TLB read will + not exceed the programmed counter value. + + + + + 6 Reserved Bit + Default Value: 0b + Access: RO + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 122 + GFX_PEND_TLB_0 - Max Outstanding Pending TLB Requests 0 + Reserved Project: All Format: MBZ + + 5:0 VMC TLB Limit Count + Default Value: 000000b + Access: R/W + + VMC TLB Limit Count Project: All Format: U6 + + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + + + +B/D/F/Type:0/0/0/GAMunit_Config +Address Offset:4034-4037h +Default Value:00000000h +Access: RO; RW; +Size:32 bits +GFX_PEND_TLB_0 - Max Outstanding Pending TLB Requests 0 + + + Default + Bit Access Value RST/PWR Description + 31 RW 0b Core + TEX Limit Enable Bit (TEXLEN): + TEX Limit Enable bit Project: All Format: U1 + This bit is used to enable the pending TLB requests limitation function for the + Texture Cache + When set, the number of internal pending read requests which require a TLB + read will not exceed the programmed counter value. + + + 30 RO 0b Core + Reserved Bit (RSVD): + Reserved Project: All Format: MBZ + + +29:24 RW 000000b Core + TEX TLB Limit Count (TEXTLBLCNT): + TEX TLB Limit Count Project: All Format: U6 + This is the MAX number of Allowed internal pending read requests which require + a TLB read + + + 23 RW 0b Core + DC Limit Enable bit (DCLEN): + DC Limit Enable bit Project: All Format: U1 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 123 + Default + Bit Access Value RST/PWR Description + This bit is used to enable the pending TLB requests limitation function for the + Instruction Cache. + When set, the number of internal pending read requests which require a TLB + read will not exceed the programmed counter value. + + + 22 RO 0b Core + Reserved Bit (RSVD): + Reserved Project: All Format: MBZ + + +21:16 RW 000000b Core + DC TLB Limit Count (DCTLBLCNT): + DC TLB Limit Count Project:All Format:U6 + This is the MAX number of Allowed internal pending read requests which require + a TLB read. + + + 15 RW 0b Core + VF Limit Enable bit (VFLEN): + VF Limit Enable bit Project: All Format: U1 + This bit is used to enable the pending TLB requests limitation function for the + Vertex Fetch + When set, the number of internal pending read requests which require a TLB + read will not exceed the programmed counter value. + + + 14 RO 0b Core + Reserved Bit (RSVD): + Reserved Project: All Format: MBZ + +13:8 RW 000000b Core + VF TLB Limit Count (VFTLBLCNT): + VF TLB Limit Count Project: All Format: U6 + This is the MAX number of Allowed internal pending read requests which require + a TLB read. + + + 7 RW 0b Core + VMC Limit Enable bit (VMCLEN): + VMC Limit Enable bit Project: All Format: U1 + This bit is used to enable the pending TLB requests limitation function for the + Video Motion Compensation. When set, the number of internal pending read + requests which require a TLB read will not exceed the programmed counter + value. + + + 6 RO 0b Core + Reserved Bit (RSVD): + Reserved Project: All Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 124 + Default + Bit Access Value RST/PWR Description + 5:0 RW 000000b Core + VMC TLB Limit Count (VMCTLBLCNT): + VMC TLB Limit Count Project: All Format: U6 + This is the MAX number of Allowed internal pending read requests which require + a TLB read. + + + + +1.1.19.5 GFX_PEND_TLB_1 - Max Outstanding Pending TLB Requests 1 + + GFX_PEND_TLB_1 - Max Outstanding Pending TLB Requests 1 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04038h-0403Bh + +GFX_PEND_TLB_1 - Max Outstanding pending TLB requests 1 + + +DWord Bit Description +0 31 SOL Limit Enable bit + Default Value: 0b + Access: R/W + + SOL Limit Enable bit Project: All Format: U1 + + This bit is used to enable the pending TLB requests limitation function for the SOL. When set, the + number of internal pending read requests which require a TLB read will not exceed the programmed + counter value. + + 30 Reserved Bits + Default Value: 0b + Access: RO + + Reserved Project: All Format: MBZ + + + + + 29:24 SOL TLB Limit Count + Default Value: 000000b + Access: R/W + + SOL TLB Limit Count Project: All Format: U6 + + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + 23 L3 Limit Enable bit + Default Value: 0b + Access: R/W + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 125 + GFX_PEND_TLB_1 - Max Outstanding Pending TLB Requests 1 + L3 Limit Enable bit Project: All Format: U1 + + This bit is used to enable the pending TLB requests limitation function for the L3. When set, the + number of internal pending read requests which require a TLB read will not exceed the programmed + counter value. + + 22 Reserved Bit + Default Value: 0b + Access: RO + + Reserved Project: All Format: MBZ + + 21:16 L3 TLB Limit Count + Default Value: 000000b + Access: R/W + + L3 TLB Limit Count Project: All Format: U6 + + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + 15 RCZ Limit Enable bit + Default Value: 0b + Access: R/W + + RCZ Limit Enable bit Project: All Format: U1 + + + + This bit is used to enable the pending TLB requests limitation function for the Render Depth Cache + + + + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + + + + 14 Reserved Bit + Default Value: 0b + Access: RO + + Reserved Project: All Format: MBZ + Programming Notes + "" + 13:8 RCZ TLB Limit Count + Default Value: 000000b + Access: R/W + + RCZ TLB Limit Count Project: All Format: U6 + + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 126 + GFX_PEND_TLB_1 - Max Outstanding Pending TLB Requests 1 + + + 7 RCC Limit Enable bit + Default Value: 0b + Access: R/W + + RCC Limit Enable bit Project: All Format: U1 + + This bit is used to enable the pending TLB requests limitation function for the Render Color Cache. + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + 6 Reserved Bit + Default Value: 0b + Access: RO + + Reserved Project: All Format: MBZ + + 5:0 RCC TLB Limit Count + Default Value: 000000b + Access: R/W + + RCC TLB Limit Count Project: All Format: U6 + + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + + + +1.1.19.6 L3_LRA_0 - L3 LRA 0 + + L3_LRA_0 - L3 LRA 0 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x3F201F00 +Address: 0403Ch-0403Fh + + L3 LRA 0 + DWord Bit Description +0 31:24 L3 LRA1 Max + Default Value: 00111111b + Access: R/W + + L3 LRA1 Max Project: All Format: U6 + + Maximum value of programmable LRA1 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 127 + L3_LRA_0 - L3 LRA 0 + 23:16 L3 LRA1 Min + Default Value: 00100000b + Access: R/W + + L3 LRA1 Min Project: All Format: U6 + + Minimum value of programmable LRA1 + + 15:8 L3 LRA0 Max + Default Value: 00011111b + Access: R/W + + L3 LRA0 Max Project: All Format: U6 + + Maximum value of programmable LRA0 + + 7:0 L3 LRA0 Min + Default Value: 00000000b + Access: R/W + + L3 LRA0 Min Project: All Format: U6 + + Minimum value of programmable LRA1 + + + + +1.1.19.7 L3_LRA_1 - L3 LRA 1 + + L3_LRA_1 - L3 LRA 1 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x0900FF40 +Address: 04040h-04043h + + L3 LRA 1 + DWord Bit Description +0 31:30 Reserved Bits + Default Value: 00b + Access: RO + + Reserved Bits + + 29:28 DC + Default Value: 00b + Access: R/W + + Which LRA should DC use + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 128 + L3_LRA_1 - L3 LRA 1 + + 27:26 TEXTURE + Default Value: 10b + Access: R/W + + Which LRA should TEXTURE use + + + + + 25:24 L3 + Default Value: 01b + Access: R/W + + Which LRA should L3 use + + + + + 23:16 Reserved Bits + Default Value: 00000000b + Access: RO + + Reserved Bits + + 15:8 L3 LRA2 Max + Default Value: 11111111b + Access: R/W + + L3 LRA2 Max Project: All Format: U6 + + Maximum value of programmable LRA2 + + 7:0 L3 LRA2 Min + Default Value: 01000000b + Access: R/W + + L3 LRA2 Min Project: All Format: U6 + + Minimum value of programmable LRA2 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 129 + 1.1.19.8 CVS_TLB_LRA_0 - CVS TLB LRA 0 + + CVS_TLB_LRA_0 - CVS TLB LRA 0 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x1F080700 +Address: 04044h-04047h + + CVS TLB LRA 0 + DWord Bit Description +0 31:29 Reserved Bits + Default Value: 000b + Access: RO + + Reserved Project: All Format: MBZ + + 28:24 CVS LRA1 Max + Default Value: 11111b + Access: R/W + + CVS LRA1 Max Project: All Format: MBZ + + Maximum value of programmable LRA1 + + 23:21 Reserved Bits + Default Value: 000b + Access: RO + + Reserved Project: All Format: MBZ + + 20:16 CVS LRA1 Min + Default Value: 01000b + Access: R/W + + CVS LRA1 Min Project: All Format: U6 + + Minimum value of programmable LRA1 + + 15:13 Reserved Bits + Default Value: 000b + Access: RO + + Reserved Project: All Format: MBZ + + 12:8 CVS LRA0 Max + Default Value: 00111b + Access: R/W + + CVS LRA0 Max Project: All Format: MBZ + + Maximum value of programmable LRA0 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 130 + CVS_TLB_LRA_0 - CVS TLB LRA 0 + + 7:5 Reserved Bits + Default Value: 000b + Access: RO + + Reserved Project: All Format: MBZ + + 4:0 CVS LRA0 Min + Default Value: 00000b + Access: R/W + + CVS LRA0 Min Project: All Format: U6 + + Minimum value of programmable LRA0 + + + + +1.1.19.9 _TLB_LRA_1 - CVS TLB LRA 1 + + CVS_TLB_LRA_1 - CVS TLB LRA 1 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00001F18 +Address: 04048h-0404Bh + + CVS TLB LRA 1 + DWord Bit Description +0 31:13 Reserved Bits + Default Value: 0000000000000000000b + Access: RO + + Reserved Project: All Format: MBZ + + 12:8 CVS LRA2 Max + Default Value: 11111b + Access: R/W + + CVS LRA2 Max Project: All Format: MBZ + + Maximum value of programmable LRA2 + + 7:5 Reserved Bits + Default Value: 000b + Access: RO + + Reserved Project: All Format: MBZ + + 4:0 CVS LRA2 Min + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 131 + CVS_TLB_LRA_1 - CVS TLB LRA 1 + Default Value: 11000b + Access: R/W + + CVS LRA2 Min Project: All Format: U6 + + Minimum value of programmable LRA2 + + + + +1.1.19.10 CVS_TLB_LRA_2 - CVS TLB LRA 2 + + CVS_TLB_LRA_2 - CVS TLB LRA 2 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000005 +Address: 0404Ch-0404Fh + + CVS TLB LRA 2 + DWord Bit Description +0 31:6 Reserved Bits + Default Value: 00000000000000000000000000b + Access: RO + + Reserved Project: All Format: MBZ + + 5:4 CS LRA + Default Value: 00b + Access: R/W + + CS LRA Project: All Format: U6 + + Which LRA should CS use + + 3:2 VF LRA + Default Value: 01b + Access: R/W + + VF LRA Project: All Format: U1 + + Which LRA should VF use + + 1:0 SO LRA + Default Value: 01b + Access: R/W + + SO LRA Project: All Format: MBZ + + Which LRA should SO use + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 132 + 1.1.19.11 ZTLB_LRA_0 - ZTLB LRA 0 + + ZTLB_LRA_0 - ZTLB LRA 0 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x1F107F00 +Address: 04050h-04053h + + ZTLB TLB LRA 0 + DWord Bit Description +0 31 Reserved Bits + Default Value: 0b + Access: RO + + Reserved Bits + + 30:24 ZTLB LRA1 Max + Default Value: 0011111b + Access: R/W + + ZTLB LRA1 Max Project: All Format: U6 + + Maximum value of programmable LRA1 + + 23 Reserved Bit + Default Value: 0b + Access: RO + + Reserved Project: All Format: U1 + + 22:16 ZTLB LRA1 Min + Default Value: 0010000b + Access: R/W + + ZTLB LRA1 Min Project: All Format: MBZ + + Minimum value of programmable LRA1 + + 15 Reserved Bits + Default Value: 0b + Access: RO + + Reserved Bits + + 14:8 ZTLB LRA0 Max + Default Value: 1111111b + Access: R/W + + ZTLB LRA0 Max Project: All Format: U1 + + Maximum value of programmable LRA0 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 133 + ZTLB_LRA_0 - ZTLB LRA 0 + + 7 Reserved Bit + Default Value: 0b + Access: RO + + Reserved Project: All Format: U1 + + 6:0 ZTLB LRA0 Min + Default Value: 0000000b + Access: R/W + + ZTLB LRA0 Min Project: All Format: U6 + + Minimum value of programmable LRA0 + + + + +1.1.19.12 ZTLB_LRA_1 - ZTLB LRA 1 + + ZTLB_LRA_1 - ZTLB LRA 1 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00002F20 +Address: 04054h-04057h + + ZTLB TLB LRA 1 + DWord Bit Description +0 31:22 Reserved Bits + Default Value: 0000000000b + Access: RO + + Reserved Project: All Format: MBZ + + 21:20 STC LRA + Default Value: 00b + Access: R/W + + STC LRA Project: All Format: U6 + + Which LRA should STC use + + 19:18 HIZ LRA + Default Value: 00b + Access: R/W + + HIZ LRA Project: All Format: U1 + + Which LRA should HIZ use + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 134 + ZTLB_LRA_1 - ZTLB LRA 1 + 17:16 RCZ LRA + Default Value: 00b + Access: R/W + + RCZ LRA Project: All Format: MBZ + + + + Which LRA should RCZ use + + + + + 15 Reserved Bits + Default Value: 0b + Access: RO + + Reserved Bits + + 14:8 ZTLB LRA2 Max + Default Value: 0101111b + Access: R/W + + ZTLB LRA2 Max Project: All Format: U1 + + Maximum value of programmable LRA2 + + 7 Reserved Bits + Default Value: 0b + Access: RO + + Reserved Project: All Format: MBZ + + 6:0 ZTLB LRA2 Min + Default Value: 0100000b + Access: R/W + + ZTLB LRA2 Min Project: All Format: U6 + + Minimum value of programmable LRA2 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 135 + 1.1.19.13 RCC_LRA_0 - RCC LRA 0 + + RCC_LRA_0 - RCC LRA 0 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x3F100F00 +Address: 04058h-0405Bh + + RCC LRA 0 + DWord Bit Description +0 31:30 Reserved Bit + Default Value: 00b + Access: RO + + Reserved Project: All Format: U1 + + 29:24 RCC LRA1 Max + Default Value: 111111b + Access: R/W + + RCC LRA1 Max Project: All Format: U6 + + Maximum value of programmable LRA1 + + 23:22 Reserved Bit + Default Value: 00b + Access: RO + + Reserved Project: All Format: U1 + + 21:16 RCC LRA1 Min + Default Value: 010000b + Access: R/W + + RCC LRA1 Min Project: All Format: MBZ + + Minimum value of programmable LRA1 + + 15:14 Reserved Bit + Default Value: 00b + Access: RO + + Reserved Project: All Format: U1 + + 13:8 RCC LRA0 Max + Default Value: 001111b + Access: R/W + + RCC LRA0 Max Project: All Format: U1 + + Maximum value of programmable LRA0 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 136 + RCC_LRA_0 - RCC LRA 0 + + 7:6 Reserved Bit + Default Value: 00b + Access: RO + + Reserved Project: All Format: U1 + + 5:0 RCC LRA0 Min + Default Value: 000000b + Access: R/W + + RCC LRA0 Min Project: All Format: U6 + + Minimum value of programmable LRA0 + + + + +1.1.19.14 RCC_LRA_1 - RCC LRA 1 + + RCC_LRA_1 - RCC LRA 1 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00010000 +Address: 0405Ch-0405Fh + + RCC LRA 1 + DWord Bit Description +0 31:20 Reserved Bits + Default Value: 000000000000b + Access: RO + + Reserved Project: All Format: MBZ + + 19:18 MSC LRA + Default Value: 00b + Access: R/W + + MSC LRA Project: All Format: U1 + + Which LRA should MSC use + + 17:16 RCC LRA + Default Value: 01b + Access: R/W + + RCC LRA Project: All Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 137 + RCC_LRA_1 - RCC LRA 1 + Which LRA should RCC use + + + + + 15:0 Reserved Bits + Default Value: 0000000000000000b + Access: RO + + Reserved Project: All Format: MBZ + + + + +1.1.19.15 CASC_LRA_0 - CASC LRA 0 + + CASC_LRA_0 - CASC LRA 0 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x1F100F00 +Address: 04060h-04063h + + CASC LRA 0 + DWord Bit Description +0 31:24 CASC LRA1 Max + Default Value: 00011111b + Access: R/W + + CASC LRA1 Max Project: All Format: U6 + + Maximum value of programmable LRA1 + + Maximum Allow Value: 159 + + 23:16 CASC LRA1 Min + Default Value: 00010000b + Access: R/W + + CASC LRA1 Min Project: All Format: U6 + + Minimum value of programmable LRA1 + + 15:8 CASC LRA0 Max + Default Value: 00001111b + Access: R/W + + CASC LRA0 Max Project: All Format: U6 + + Maximum value of programmable LRA0 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 138 + CASC_LRA_0 - CASC LRA 0 + Maximum Allow Value: 159 + + 7:0 CASC LRA0 Min + Default Value: 00000000b + Access: R/W + + CASC LRA0 Min Project: All Format: U6 + + Minimum value of programmable LRA1 + + + + +1.1.19.16 CASC_LRA_1 - CASC LRA 1 + + CASC_LRA_1 - CASC LRA 1 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x3F302F20 +Address: 04064h-04067h + + CASC LRA 1 + DWord Bit Description +0 31:24 CASC LRA3 Max + Default Value: 00111111b + Access: R/W + + CASC LRA3 Max Project: All Format: U6 + + Maximum value of programmable LRA3 + + 23:16 CASC LRA3 Min + Default Value: 00110000b + Access: R/W + + CASC LRA3 Min Project: All Format: U6 + + Minimum value of programmable LRA3 + + 15:8 CASC LRA2 Max + Default Value: 00101111b + Access: R/W + + CASC LRA2 Max Project: All Format: U6 + + Maximum value of programmable LRA2 + + 7:0 CASC LRA2 Min + Default Value: 00100000b + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 139 + CASC_LRA_1 - CASC LRA 1 + Access: R/W + + CASC LRA2 Min Project: All Format: U6 + + Minimum value of programmable LRA2 + + + + +1.1.19.17 CASC_LRA_2 - CASC LRA 2 + + CASC_LRA_2 - CASC LRA 2 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00009F40 +Address: 04068h-0406Bh + + CASC LRA 2 + DWord Bit Description +0 31:16 Reserved Bits + Default Value: 0000h + Access: RO + + Reserved Project: All Format: MBZ + + 15:8 CASC LRA4 Max + Default Value: 10011111b + Access: R/W + + CASC LRA4 Max Project: All Format: U6 + + Maximum value of programmable LRA4 + + Maximum Allow Value: 159 + + 7:0 CASC LRA4 Min + Default Value: 01000000b + Access: R/W + + CASC LRA4 Min Project: All Format: U6 + + Minimum value of programmable LRA4 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 140 + 1.1.19.18 CASC_LRA_3 - CASC LRA 3 + + CASC_LRA_3 - CASC LRA 3 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x000014E4 +Address: 0406Ch-0406Fh + + CASC LRA 3 + DWord Bit Description +0 31:18 Reserved Bits + Default Value: 00000000000000b + Access: RO + + Reserved Project: All Format: MBZ + + 17:15 BCS LRA + Default Value: 000b + Access: R/W + + BCS LRA Project: All Format: U6 + + Which LRA should use + + 14:12 BLB LRA + Default Value: 001b + Access: R/W + + BLB LRA Project: All Format: U6 + + Which LRA should use + + 11:9 VCS LRA + Default Value: 010b + Access: R/W + + VCS LRA Project: All Format: U6 + + Which LRA should use + + 8:6 VMX LRA + Default Value: 011b + Access: R/W + + VMX LRA Project: All Format: U6 + + Which LRA should use + + 5:3 VMC LRA + Default Value: 100b + Access: R/W + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 141 + CASC_LRA_3 - CASC LRA 3 + VMC LRA Project: All Format: U6 + + Which LRA should use + + 2:0 VCR LRA + Default Value: 100b + Access: R/W + + VCR LRA Project: All Format: U6 + + Which LRA should use + + + + +1.1.19.19 MEDIA_MAX_REQ_COUNT - MAX Requests Allowed - CASC + + MEDIA_MAX_REQ_COUNT - MAX Requests Allowed - CASC +Register Space: MMIO: 0/2/0 + + +Default Value: 0x10202020 +Address: 04070h-04073h + + Programmable Request Count - CASC +DWord Bit Description +0 31:24 GFX Max Request Limit Count + Default Value: 00010000b + Access: R/W + + This is the MAX number of Allowed Requests Count - These counters keep track of the accepted + requests from each engine . Requests are counted, regardless of kind of cycle (Miss/Hit/Present) + + Minimum count value must be = 1 + + + + + 23:16 MFX/BLT Max Request Limit Count + Default Value: 00100000b + Access: R/W + + This is the MAX number of Allowed Requests Count - These counters keep track of the accepted + requests from each engine . Requests are counted, regardless of kind of cycle (Miss/Hit/Present) + + Minimum count value must be = 1 + + + + + 15:14 Reserved Bits + Default Value: 00b + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 142 + MEDIA_MAX_REQ_COUNT - MAX Requests Allowed - CASC + Access: RO + + Reserved Bits + + 13:8 VLF Max Request Limit Count + Default Value: 100000b + Access: R/W + + This is the MAX number of Allowed Requests Count - These counters keep track of the accepted + requests from each client. Requests are counted, regardless of kind of cycle (Miss/Hit/Present ) + + Minimum count value must be = 1 + + 7:6 Reserved Bits + Default Value: 00b + Access: RO + + Reserved Project: All Format: MBZ + + 5:0 CASC Max Request Limit Count + Default Value: 100000b + Access: R/W + + This is the MAX number of Allowed Requests Count - These counters keep track of the accepted + requests from each client. Requests are counted, regardless of kind of cycle (Miss/Hit/Present ) + + Minimum count value must be = 1 + + + + +1.1.19.20 GFX_MAX_REQ_COUNT - MAX Requests Allowed - GAM + + GFX_MAX_REQ_COUNT - MAX Requests Allowed - GAM +Register Space: MMIO: 0/2/0 + + +Default Value: 0x43F20101 +Address: 04074h-04077h + + Programmable Request Count - GAM +DWord Bit Description +0 31:26 GAP Writes Max Request Limit Count + Default Value: 010000b + Access: R/W + + This is the MAX number of Allowed Write Requests Count - These counters keep track of the + accepted write requests from all GAP clients (RCZ, HiZ,Stc, RCC, L3). + + Minimum count value must be = 1 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 143 + GFX_MAX_REQ_COUNT - MAX Requests Allowed - GAM + 25:20 CVS Max Request Limit Count + Default Value: 111111b + Access: R/W + + This is the MAX number of Allowed Requests Count - These counters keep track of the accepted + requests from each client. Requests are counted, regardless of kind of cycle (Miss/Hit/Present ) + + Minimum count value must be = 1 + + 19 Reserved Bits + Default Value: 0b + Access: RO + + Reserved Project: All Format: MBZ + + 18:13 L3 Max Request Limit Count + Default Value: 010000b + Access: R/W + + This is the MAX number of Allowed Requests Count - These counters keep track of the accepted + requests from each client. Requests are counted, regardless of kind of cycle (Miss/Hit/Present) + + Minimum count value must be = 1 + + 12 Reserved Bits + Default Value: 0b + Access: RO + + Reserved Project: All Format: MBZ + + 11:6 Z Request Limit Count + Default Value: 000100b + Access: R/W + + This is the MAX number of Allowed Requests Count - These counters keep track of the accepted + requests from each client. Requests are counted, regardless of kind of cycle (Miss/Hit/Present) + + Minimum count value must be = 1 + + 5:0 RCC Request Limit Count + Default Value: 000001b + Access: R/W + + This is the MAX number of Allowed Requests Count - These counters keep track of the accepted + requests from each client. Requests are counted, regardless of kind of cycle (Miss/Hit/Present) + + Minimum count value must be = 1 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 144 + 1.1.19.21 GAM_HWSP_REG - GAM Hardware Status Page Address Register + + GAM_HWSP_REG - GAM Hardware Status Page Address Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04080h-04083h + + This register is used to program the 4 KB-aligned System Memory address of the Hardware Status Page used to + report hardware status into (typically cacheable) System Memory. This address in this register is translated using + the Global GTT in memory. The mapping type of the GTT entry determines the snoop nature of the transaction to + memory. + DWord Bit Description +0 31:12 GAM HWSP Register + Default Value: 00000h + Access: R/W + + + + + 11:0 Reserved Bits + Default Value: 000h + Access: RO + + + + +1.1.19.22 GFX_ENG_FR - Graphics Engine Fault Register + + GFX_ENG_FR - Graphics Engine Fault Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04094h-04097h + + Graphics Engine Fault Register + + +DWord Bit Description +0 31:12 Virtual Address of Fault + Default Value: 00000h + Access: R/W + + This is the original Address of the Page that generated the First fault for this engine. + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 145 + GFX_ENG_FR - Graphics Engine Fault Register + + + 11 GTTSEL + Default Value: 0b + Access: R/W + + This bit indicates if the valid bit happened while using PPGTT or GGTT: 0 - PPGTT, 1 - GGTT + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 10:3 SRCID of Fault + Default Value: 00h + Access: R/W + + This is the Source ID of the unit that requested the cycle that generated the First Page fault for this + engine. + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 2:1 Fault Type + Default Value: 00b + Access: R/W + + Type of Fault recorded: + + 00 - Page Fault. + + 01 - Invalid PD Fault + + 10 - Unloaded PD Fault + + 11 - Invalid and Unloaded PD fault + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 0 Valid Bit + Default Value: 0b + Access: R/W + + This bit indicates that the first fault for this engine has been recorded. It can only be cleared by SW, + which will also clear the other fields. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 146 + 1.1.19.23 ERROR - Main Graphic Arbiter Error Report + + ERROR - Main Graphic Arbiter Error Report +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 040A0h-040A3h + +This register is used to report differet error conditions. Error bits are writable. + + +DWord Bit Description +0 31:16 Reserved Bits + Default Value: 0000h + Access: RO + + Reserved Bits + + + + + 15 Reserved Error Bits 15 + Default Value: 0b + Access: R/W + + Reserved Error bits (Future expansion) + + 14 Reserved Error Bits 14 + Default Value: 0b + Access: R/W + + Reserved Error bits (Future expansion) + + 13 Reserved Error Bits 13 + Default Value: 0b + Access: R/W + + Reserved Error bits (Future expansion) + + 12 Reserved Error Bits 12 + Default Value: 0b + Access: R/W + + Reserved Error bits (Future expansion) + + 11 Reserved Error Bits 11 + Default Value: 0b + Access: R/W + + Reserved Error bits (Future expansion) + + 10 Reserved Error Bits 10 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 147 + ERROR - Main Graphic Arbiter Error Report + Default Value: 0b + Access: R/W + + Reserved Error bits (Future expansion) + + 9 Reserved Error Bits 9 + Default Value: 0b + Access: R/W + + Reserved Error bits (Future expansion) + + + + + 8 Unloaded PD Error + Default Value: 0b + Access: R/W + + Unloaded PD error + + The Cache Line containing a PD entry being accessed, was marked as invalid in the last PD load + cycle. + + + + + 7 Reserved Error Bits 7 + Default Value: 0b + Access: R/W + + Reserved Error bits (Future expansion) + + + + + 6 Page Directory Entry VTD Translation Error + Default Value: 0b + Access: R/W + + Page Directory entry VTD translation error + + PD entry’s VTD translation generated an error (HPA is not accessible for DMA read or write) + + + + + 4 TLB Page VTD Translation Error + Default Value: 0b + Access: R/W + + TLB Page VTD translation error + + A TLB Page’s VTD translation generated an error (HPA is not accessible for DMA read or write) + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 148 + ERROR - Main Graphic Arbiter Error Report + + 2 Invalid Page Directory Entry Error + Default Value: 0b + Access: R/W + + Invalid Page Directory entry error + + PD entry’s valid bit is 0 + + + + + 0 TLB Page Fault Error + Default Value: 0b + Access: R/W + + TLB Page Fault error + + A TLB Page’s GTT translation generated a page fault (GTT entry not valid) + + + + +1.1.19.24 DONE_REG - Gam Fub Done Lookup Register + + DONE_REG - Gam Fub Done Lookup Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 040B0h-040B3h + + Gam Fub Done Lookup Register + DWord Bit Description +0 31:0 Gam Fub Done Lookup Reg + Default Value: 00000000h + Access: RO + + 31 CVS Credit Fifo is Empty + + 30 CVS TLB Don’t have any Cycles + + 29 Z Credit fifo is empty + + 28 ZTLB Don’t have any cycles + + 27 RCC Credit Fifo is empty + + 26 RCC TLB Don’t have any cycles + + 25 L3 Credit fifo is empty + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 149 + DONE_REG - Gam Fub Done Lookup Register + 24 L3 TLB is don’t have any Cycles + + 23 VLF Credit fifo is empty + + 22 VLF TLB don’t have any cycles + + 21 CASC Credit fifo empty + + 20 CASC TLB don’t have any Cycles + + 19 Miss Fub Done + + 18 Read Stream Done + + 17 Read Steam Fifo is empty + + 16 Recycle Fifo in rstrm is empty + + 15 TLB Pend Done + + 14 TLB Pend PQ Array Is done + + 13 TLB pend PB Array is done + + 12 Read route fub is done + + 11 Gafm Data fifo is empty + + 10 GAP data fifo is empty + + 9 GAC data fifo is empty + + 8 Wrdp is done with all the cycles + + 7 Wrdp RID fifo is empty + + 6 No hold from midarb to RTSTRM + + 5 No hold from TLBPEND to MIDARB + + 4 VTD Mode + + 3 Tied to "1" - to be defined + + 2 Fence FSM are IDLE + + 1 Non PD Load Done + + 0 Tied to "1" - to be defined + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 150 + 1.1.19.25 GAC_HWSP_REG - GAC Hardware Status Page Address Register + + GAC_HWSP_REG - GAC Hardware Status Page Address Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04180h-04183h + + This register is used to program the 4 KB-aligned System Memory address of the Hardware Status Page used to + report hardware status into (typically cacheable) System Memory. The address in this register is translated using the + Global GTT in memory. The mapping type of the GTT entry determines the snoop nature of the transaction to + memory. + DWord Bit Description +0 31:12 GAC HWSP Register + Default Value: 00000h + Access: R/W + + + + + 11:0 Reserved Bits + Default Value: 000h + Access: RO + + + + +1.1.19.26 MEDIA_ENG_FR - Media Engine Fault Register + + MEDIA_ENG_FR - Media Engine Fault Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04194h-04197h + + Media Engine Fault Register + + +DWord Bit Description +0 31:12 Virtual Address of Fault + Default Value: 00000h + Access: R/W + + This is the original Address of the Page that generated the First fault for this engine. + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 151 + MEDIA_ENG_FR - Media Engine Fault Register + + + 11 GTTSEL + Default Value: 0b + Access: R/W + + This bit indicates if the valid bit happened while using PPGTT or GGTT: 0 - PPGTT, 1 - GGTT + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 10:3 SRCID of Fault + Default Value: 00h + Access: R/W + + This is the Source ID of the unit that requested the cycle that generated the First Page fault for this + engine. + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 2:1 Fault Type + Default Value: 00b + Access: R/W + + Type of Fault recorded: + + 00 - Page Fault. + + 01 - Invalid PD Fault + + 10 - Unloaded PD Fault + + 11 - Invalid and Unloaded PD fault + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 0 Valid Bit + Default Value: 0b + Access: R/W + + This bit indicates that the first fault for this engine has been recorded. It can only be cleared by SW, + which will also clear the other fields. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 152 + 1.1.19.27 GAB_HWSP_REG - GAB Hardware Status Page Address Register + + GAB_HWSP_REG - GAB Hardware Status Page Address Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04280h-04283h + + This register is used to program the 4 KB-aligned System Memory address of the Hardware Status Page used to + report hardware status into (typically cacheable) System Memory. The address in this register is translated using + the Global GTT in memory. The mapping type of the GTT entry determines the snoop nature of the transaction to + memory. + DWord Bit Description +0 31:12 GAB HWSP Register + Default Value: 00000h + Access: R/W + + + + + 11:0 Reserved Bits + Default Value: 000h + Access: RO + + + + +1.1.19.28 BLT_ENG_FR - Blitter Engine Fault Register + + BLT_ENG_FR - Blitter Engine Fault Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04294h-04297h + +Blitter Engine Fault Register + + +DWord Bit Description +0 31:12 Virtual Address of Page Fault + Default Value: 00000h + Access: R/W + + This is the original Address of the Page that generated the First fault for this engine. + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 153 + BLT_ENG_FR - Blitter Engine Fault Register + + + 11 Blitter GTTSEL + Default Value: 0b + Access: R/W + + This bit indicates if the valid bit happened while using PPGTT or GGTT: 0 - PPGTT, 1 - GGTT + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 10:3 SRCID of Fault + Default Value: 00h + Access: R/W + + This is the Source ID of the unit that requested the cycle that generated the First Page fault for this + engine. + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 2:1 Fault Type + Default Value: 00b + Access: R/W + + Type of Fault recorded: + + 00 - Page Fault. + + 01 - Invalid PD Fault + + 10 - Unloaded PD Fault + + 11 - Invalid and Unloaded PD fault + + This value is locked and not updated on subsequent faults, until the valid bit of this register is cleared + by SW + + 0 Valid Bit + Default Value: 0b + Access: R/W + + This bit indicates that the first fault for this engine has been recorded. It can only be cleared by SW, + which will also clear the other fields. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 154 + 1.1.19.29 TLB_RD_ADDR - TLB_RD_ADDRESS Register + + TLB_RD_ADDR - TLB_RD_ADDRESS Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04700h-04703h + +TLB Read Address + + + DWord Bit Description +0 31:10 Reserved Bits + Default Value: 0000000000000000000000b + Access: RO + + Reserved Bits + + 9:0 TLB Read Address + Default Value: 0000000000b + Access: R/W + + TLB Read Address + + MSB<9:X> : + TLB Select <9:X> PAT MSB: Section of the PAT used. + PAT_MSB_VLFTLB 00000 32 entries - 32 + PAT_MSB_CVSTLB 00001 32 entries - 32 + PAT_MSB_RCCTLB 0001 64 entries - 64 + PAT_MSB_ZTLB 001 128 entries - 128 + PAT_MSB_L3TLB 01 160 entries - 256 + PAT_MSB_CASCTLB 10 140 entries - 256 + + LSB : + + GEN RAM ADDRES in Selected TLB + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 155 + 1.1.19.30 TLB_RD_DATA - TLB_RD_DATA Register + + TLB_RD_DATA - TLB_RD_DATA Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04704h-04707h + + TLB_READ_DATA Register + + + DWord Bit Description +0 31:0 TLB_READ_DATA Register + Default Value: 00000000h + Access: RO + + Return data + + + + +1.1.19.31 VLFTLB_VLD_0 - Valid Bit Vector 0 for VLF + + VLFTLB_VLD_0 - Valid Bit Vector 0 for VLF +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04720h-04723h + + This register contains the valid bits for entries 0-31 of VLFTLB + DWord Bit Description +0 31:0 Valid Bit Vector 0 for VLF + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.1.19.32 CVSTLB_VLD_0 - Valid Bit Vector 0 for CVS + + CVSTLB_VLD_0 - Valid Bit Vector 0 for CVS +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 156 + CVSTLB_VLD_0 - Valid Bit Vector 0 for CVS +Address: 04724h-04727h + + This register contains the valid bits for entries 0-31 of CVSTLB + DWord Bit Description +0 31:0 Valid Bit Vector 0 for CVS + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.1.19.33 RCCTLB_VLD_0 - Valid Bit Vector 0 for RCC + + RCCTLB_VLD_0 - Valid Bit Vector 0 for RCC +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04728h-0472Bh + + This register contains the valid bits for entries 0-31 of RCCTLB + DWord Bit Description +0 31:0 Valid Bit Vector 0 for RCC + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.1.19.34 RCCTLB_VLD_1 - Valid Bit Vector 1 for RCC + + RCCTLB_VLD_1 - Valid Bit Vector 1 for RCC +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 0472Ch-0472Fh + + This register contains the valid bits for entries 0-31 of RCCTLB + DWord Bit Description +0 31:0 Valid Bit Vector 1 for RCC + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 157 + 1.1.19.35 ZTLB_VLD_0 - Valid Bit Vector 0 for Z + + ZTLB_VLD_0 - Valid Bit Vector 0 for Z +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04730h-04733h + + This register contains the valid bits for entries 0-31 of ZTLB + DWord Bit Description +0 31:0 Valid Bit Vector 0 for Z + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.1.19.36 ZTLB_VLD_1 - Valid Bit Vector 1 for Z + + ZTLB_VLD_1 - Valid Bit Vector 1 for Z +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04734h-04737h + + This register contains the valid bits for entries 0-31 of ZTLB + DWord Bit Description +0 31:0 Valid Bit Vector 1 for Z + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 158 + 1.1.19.37 ZTLB_VLD_2 - Valid Bit Vector 2 for Z + + ZTLB_VLD_2 - Valid Bit Vector 2 for Z +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04738h-0473Bh + + This register contains the valid bits for entries 0-31 of ZTLB + DWord Bit Description +0 31:0 Valid Bit Vector 2 for Z + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.1.19.38 ZTLB_VLD_3 - Valid Bit Vector 3 for Z + + ZTLB_VLD_3 - Valid Bit Vector 3 for Z +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 0473Ch-0473Fh + + This register contains the valid bits for entries 0-31 of ZTLB + DWord Bit Description +0 31:0 Valid Bit Vector 3 for Z + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 159 + 1.1.19.39 L3TLB_VLD_0 - Valid Bit Vector 0 for L3 + + L3TLB_VLD_0 - Valid Bit Vector 0 for L3 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04740h-04743h + + This register contains the valid bits for entries 0-31 of L3TLB + DWord Bit Description +0 31:0 Valid Bit Vector 0 for L3 + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.1.19.40 L3TLB_VLD_1 - Valid Bit Vector 1 for L3 + + L3TLB_VLD_1 - Valid Bit Vector 1 for L3 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04744h-04747h + + This register contains the valid bits for entries 0-31 of L3TLB + DWord Bit Description +0 31:0 Valid Bit Vector 1 for L3 + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 160 + 1.1.19.41 L3TLB_VLD_2 - Valid Bit Vector 2 for L3 + + L3TLB_VLD_2 - Valid Bit Vector 2 for L3 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04748h-0474Bh + + This register contains the valid bits for entries 0-31 of L3TLB + DWord Bit Description +0 31:0 Valid Bit Vector 2 for L3 + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.1.19.42 L3TLB_VLD_3 - Valid Bit Vector 3 for L3 + + L3TLB_VLD_3 - Valid Bit Vector 3 for L3 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 0474Ch-0474Fh + + This register contains the valid bits for entries 0-31 of L3TLB + DWord Bit Description +0 31:0 Valid Bit Vector 3 for L3 + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 161 + 1.1.19.43 L3TLB_VLD_4 - Valid Bit Vector 4 for L3 + + L3TLB_VLD_4 - Valid Bit Vector 4 for L3 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04750h-04753h + + This register contains the valid bits for entries 0-31 of L3TLB + DWord Bit Description +0 31:0 Valid Bit Vector 4 for L3 + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.1.19.44 L3TLB_VLD_5 - Valid Bit Vector 5 for L3 + + L3TLB_VLD_5 - Valid Bit Vector 5 for L3 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04754h-04757h + + This register contains the valid bits for entries 0-31 of L3TLB + DWord Bit Description +0 31:0 Valid Bit Vector 5 for L3 + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 162 + 1.1.19.45 L3TLB_VLD_6 - Valid Bit Vector 6 for L3 + + L3TLB_VLD_6 - Valid Bit Vector 6 for L3 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04758h-0475Bh + + This register contains the valid bits for entries 0-31 of L3TLB + DWord Bit Description +0 31:0 Valid Bit Vector 6 for L3 + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.1.19.46 L3TLB_VLD_7 - Valid Bit Vector 7 for L3 + + L3TLB_VLD_7 - Valid Bit Vector 7 for L3 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 0475Ch-0475Fh + + This register contains the valid bits for entries 0-31 of L3TLB + DWord Bit Description +0 31:0 Valid Bit Vector 7 for L3 + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 163 + 1.1.19.47 CASCTLB_VLD_0 - Valid Bit Vector 0 for CASC + + CASCTLB_VLD_0 - Valid Bit Vector 0 for CASC +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04760h-04763h + + This register contains the valid bits for entries 0-31 of CASCTLB + DWord Bit Description +0 31:0 Valid Bit Vector 0 for CASC + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.1.19.48 CASCTLB_VLD_1 - Valid Bit Vector 1 for CASC + + CASCTLB_VLD_1 - Valid Bit Vector 1 for CASC +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04764h-04767h + + This register contains the valid bits for entries 0-31 of CASCTLB + DWord Bit Description +0 31:0 Valid Bit Vector 1 for CASC + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 164 + 1.1.19.49 CASCTLB_VLD_2 - Valid Bit Vector 2 for CASC + + CASCTLB_VLD_2 - Valid Bit Vector 2 for CASC +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04768h-0476Bh + + This register contains the valid bits for entries 0-31 of CASCTLB + DWord Bit Description +0 31:0 Valid Bit Vector 2 for CASC + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.1.19.50 CASCTLB_VLD_3 - Valid Bit Vector 3 for CASC + + L3TLB_VLD_3 - Valid Bit Vector 3 for L3 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 0474Ch-0474Fh + + This register contains the valid bits for entries 0-31 of L3TLB + DWord Bit Description +0 31:0 Valid Bit Vector 3 for L3 + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 165 + 1.1.19.51 CASCTLB_VLD_4 - Valid Bit Vector 4 for CASC + + CASCTLB_VLD_4 - Valid Bit Vector 4 for CASC +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Address: 04770h-04773h + + This register contains the valid bits for entries 0-31 of CASCTLB + DWord Bit Description +0 31:0 Valid Bit Vector 4 for CASC + Default Value: 00000000h + Access: RO + + Valid bits per entry + + + + +1.2 Memory Interface Commands for Rendering Engine + +1.2.1 Introduction +This chapter describes the formats of the “Memory Interface” commands, including brief descriptions of +their use. The functions performed by these commands are discussed fully in the Memory Interface +Functions Device Programming Environment chapter. +This chapter describes MI Commands for the original graphics processing engine. The term “for +Rendering Engine” in the title has been added to differentiate this chapter from a similar one describing +the MI commands for the Media Decode Engine. +The commands detailed in this chapter are used across products within the Ivy Bridge family. However, +slight changes may be present in some commands (i.e., for features added or removed), or some +commands may be removed entirely. Refer to the Preface chapter for product specific summary. + + +1.2.2 Software Synchronization Commands +To support mid-triangle interruption, certain commands need to be placed in a temporary location in +hardware until primitive commands are complete. This introduces out-of-order command execution. +Below show the commands that are affected. Note that the INSTPM register has a bit that is used to force +in-order execution. If set, however, mid-triangle modes like PSMI cannot be enabled. + Command Qualifications + MI_NOOP When writing to the NOOPID register + MI_USER_INTERRUPT Always + MI_SEMAPHORE_MBOX Memory write + MI_STORE_DATA_IMM Always + MI_STORE_DATA_INDEX Always + MI_LOAD_REGISTER_IMM Always + MI_UPDATE_GTT Always + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 166 + Command Qualifications + MI_STORE_REGISTER_MEM Register read is done in-order, register write done out-of-order + + +1.2.3 MI_ARB_CHECK + + MI_ARB_CHECK + +Source: RenderCS +Length Bias: 1 +The MI_ARB_CHECK instruction is used to check the ring buffer double buffered head pointer (register UHPTR). +This instruction can be used to pre-empt the current execution of the ring buffer. Note that the valid bit in the updated +head pointer register needs to be set for the command streamer to be pre-empted. + Programming Notes +  The current head pointer is loaded with the updated head pointer register independent of the location of the + updated head +  If the current head pointer and the updated head pointer register are equal, hardware will automatically reset + the valid bit corresponding to the UHPTR +  This instruction can be in either a ring buffer or batch buffer. +  For pre-emption, the wrap count in the ring buffer head register is no longer maintained by hardware. The + hardware updates the wrap count to the value in the UHPTR register. + + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 05h MI_ARB_CHECK + Format: OpCode + 22:0 Reserved + Format: MBZ + + + + +1.2.4 MI_ARB_ON_OFF + + MI_ARB_ON_OFF + +Source: RenderCS +Length Bias: 1 +The MI_ARB_ON_OFF instruction is used to disable/enable context switching. Note that context switching will +remain disabled until re-enabled through use of this command. + This command will also prevent a switch in the case of waiting on events, running out of commands. These will +effectively hang the device if allowed to occur while arbitration is off (context switching is disabled.) This command +should always be used as an off-on pair with the sequence of instructions to be protected from context switch +between MI_ARB_OFF and MI_ARB_ON. Software must use this arbitration control with caution since it has the +potential to increase the response time of the Render Engine to pre-emption requests. This is a privileged command; +it will not be effective (will be converted to a no-op) if executed from within a non-privileged batch buffer. + DWord Bit Description + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 167 + MI_ARB_ON_OFF +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 08h MI_ARB_ON_OFF + Format: OpCode + 22:1 Reserved + Format: MBZ + 0 Arbitration Enable + Format: Enable + This field enables or disables context switches due to pre-emption . + + + + +1.2.5 MI_BATCH_BUFFER_END + + MI_BATCH_BUFFER_END + +Source: RenderCS +Length Bias: 1 +The MI_BATCH_BUFFER_END command is used to terminate the execution of commands stored in a batch buffer +initiated using a MI_BATCH_BUFFER_START command. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 0Ah MI_ BATCH_BUFFER_END + Format: OpCode + 22:0 Reserved + Format: MBZ + + + + +1.2.6 MI_CONDITIONAL_BATCH_BUFFER_END + + MI_CONDITIONAL_BATCH_BUFFER_END + +Source: RenderCS +Length Bias: 2 +The MI_BATCH_BUFFER_END command is used to conditionally terminate the execution of commands stored in a +batch buffer initiated using a MI_BATCH_BUFFER_START command. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 168 + MI_CONDITIONAL_BATCH_BUFFER_END + Format: OpCode + 28:23 MI Command Opcode + Default Value: 36h MI_CONDITIONAL_BATCH_BUFFER_END + Format: OpCode + 22 Use Global GTT + Default Value: 0h + Format: U1 + If set, this command will use the global GTT to translate the Compare Address and this command + must be executing from a privileged (secure) batch buffer. If clear, the PPGTT will be used to translate + the Compare Address. + + 21 Compare Semaphore + Default Value: 0h + Format: U1 + If set, the value from the Compare Data Dword is compared to the value from the Compare Address in + memory. If the value at Compare Address is greater than the Compare Data Dword, execution of + current command buffer should continue. If clear, no comparison takes place. + + 19:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 0h + Format: =n Total Length - 2. Excludes DWord (0,1). + + + +1 31:0 Compare Data Dword + Data dword to compare memory. The Data dword is supplied by software to control execution of the + command buffer. If the compare is enabled and the data at Compare Address is greater than this + dword, the execution of the command buffer should continue. +2 31:3 Compare Address + + Qword address to fetch Data Dword(DW0) from memory. + + HW will compare the Data Dword(DW0) with Compare Data Dword + 2:0 Reserved + Format: MBZ + + + + +1.2.7 MI_BATCH_BUFFER_START (Render) + + MI_BATCH_BUFFER_START + +Source: RenderCS +Length Bias: 2 +The MI_BATCH_BUFFER_START command is used to initiate the execution of commands stored in a batch buffer. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 169 + MI_BATCH_BUFFER_START +For restrictions on the location of batch buffers, see Batch Buffers in the Device Programming Interface chapter of MI +Functions. + Programming Notes +It is essential that the address location beyond the current page be populated inside the GTT. HW performs over-fetch +of the command addresses and any over-fetch requires a valid TLB entry. A single extra page beyond the batch buffer +is sufficient. Prior to sending batch buffer start command with clear command buffer enable set, software has to +ensure pipe is flushed explicitly by sending MI_FLUSH. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 31h MI_BATCH_BUFFER_START + Format: OpCode + 22 Reserved + + Format: MBZ + 21:17 Reserved + Format: MBZ + 16 Reserved + + Format: MBZ + 15 Reserved + + Format: MBZ + 14 Reserved + Format: MBZ + 13 Reserved + + Format: MBZ + 11 Clear Command Buffer Enable + Format: Enable + The address of the batch buffer is an offset into the WOPCM area. This batch buffer needs to be + preceded by a MI_FLUSH command or PIPE_CONTROL with CS Stall set. + + 10 Reserved + + Format: MBZ + 8 Address Space Indicator + Description Project + SW must ensure the "Address Space Indicator" of the chained batch buffer to be same as the + initial batch buffer. Ex: If the MI_BATCH_BUFFER_START executed from Ring Buffer has + "Address Space Indicator" as "PPGTT" then all subsequent chained batch buffers (not second + level Batch Buffers) must be in "PPGTT". + Not complying to above programming will result in unknown behavior of HW. + Second level batch buffer can select its "Address space Indicator" independent of the parent + batch buffer. + This field must be '0' unless the Per-Process GTT Enable is '1' + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 170 + MI_BATCH_BUFFER_START + + Value Name Description + 0h GGTT This batch buffer will be accessed via the GGTT. + 1h PPGTT This batch buffer will be accessed via the PPGTT. + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Format: =n Total - Bias + + + +1 31:2 Batch Buffer Start Address + Format: GraphicsAddress[31:2]BatchBuffer + This field specifies Bits 31:2 of the starting address of the batch buffer. + + 1:0 Reserved + Format: MBZ + + + +1.2.7.1 Command Access of Privileged Memory +Memory space mapped through the global GTT is considered “privileged” memory. Commands that have +the capability of accessing both privileged and unprivileged (PPGTT space) memory will contain a bit that, +if set, will attempt a “privileged” access through the GGTT rather than an unprivileged access through the +context-local PPGTT. +“User mode” command buffers should not be able to access privileged memory under any circumstances. +These command buffers will be issued by the kernel mode driver with the batch buffer’s Buffer Security +Indicator set to “non-secure”. Commands in such a batch buffer are not allowed to access privileged +memory. +“Kernel mode” command buffers are allowed to access privileged memory. The batch buffers Buffer +Security indicator is set to “secure” in this case. In some of the commands that access memory in a +secure batch buffer, a bit is provided in the command to steer the access to Per process or Global virtual +space. Secure batch buffers are executed from the global GTT. +Commands in ring buffers and commands in batch buffers that are marked as secure (by the kernel mode +driver) are allowed to access both privileged and unprivileged memory and may choose on a command- +by-command basis. + +GGTT and PPGTT Usage by Command + Command Address Allowed Access + MI_BATCH_BUFFER_START* Command Address Selectable + MI_DISPLAY_FLIP Display Buffer Base GGTT Only + MI_STORE_DATA_IMM* Storage Address Selectable + MI_STORE_DATA_INDEX** Storage Offset Selectable + MI_STORE_REGISTER_MEM* Storage Address Selectable + MI_SEMAPHORE_MBOX Semaphore Address Selectable + PIPE_CONTROL STDW Address Selectable + +*Command has a GGTT/PPGTT selector added to it vs. previous products. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 171 + **Added bit allows offset to apply to global HW Status Page or PP HW Status Page found in context +image. + +2.1.7.2 Privileged Commands +A subset of the commands are privileged. These commands may be issued only from a secure batch +buffer or directly from a ring. If one of these commands is parsed in a non-secure batch buffer, an error is +flagged and the command is dropped. For commands that generates a write, the hardware will complete +the transaction but the byte enables are turned off. Batch buffers from the User mode driver are passed +directly to the kernel mode driver which does not validate them but issues them with the Security Indicator +set to ‘non-secure’ to protect the system from an attack using these privileged commands. + +Privileged Commands + + Function in non-privileged batch buffers + Privileged Command +MI_LOAD_REGISTER_IMM Byte enables are turned off +MI_UPDATE_GTT Byte enabled are turned off +MI_STORE_DATA_IMM + Command is translated using the Per-process GTT if Per-Process Virtual Address + Space is set + +MI_STORE_DATA_INDEX +MI_STORE_REGISTER_MEM Command is translated and completed with byte enables turned off +MI_DISPLAY_FLIP Command is ignored by the hardware + +Parsing one of the commands in the table above from a non-secure batch buffer will flag an error and +convert the command to a NOOP. + +1.2.7.2 User Mode Privileged Commands +A subset of the commands are privileged. These commands may be issued only from a secure batch +buffer or directly from a ring. If one of these commands is parsed in a non-secure batch buffer, an error is +flagged and the command is dropped. For commands that generates a write, the hardware will complete +the transaction but the byte enables are turned off. Batch buffers from the User mode driver are passed +directly to the kernel mode driver which does not validate them but issues them with the Security Indicator +set to ‘non-secure’ to protect the system from an attack using these privileged commands. + +User Mode Privileged Commands +User Mode Privileged Command Function in non-privileged batch buffers +MI_LOAD_REGISTER_IMM Command is converted to NOOP +MI_UPDATE_GTT Command is converted to NOOP +MI_STORE_DATA_IMM + Command is converted to NOOP if Use Global GTT is enabled. + +MI_STORE_DATA_INDEX + Command is converted to NOOP if Use Global GTT is enabled. + +MI_STORE_REGISTER_MEM Command is converted to NOOP +MI_DISPLAY_FLIP Command is converted to NOOP +MI_ARB_ON_OFF Command is converted to NOOP +MI_ARB_CHECK Command is converted to NOOP +MI_WAIT_FOR_EVENT Command is converted to NOOP + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 172 + 1.2.8 MI_CLFLUSH + + MI_CLFLUSH + +Source: RenderCS +Length Bias: 2 + + Flushes out the page given in the command out to system memory. This command is specific to the render engine. + This command is not privileged. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 27h Store DW MI_CLFLUSH + Format: OpCode + 22 Use Global GTT + This bit will be ignored and treated as if clear when executing from a non-privileged batch buffer. It is + allowed for this bit to be clear when executing this command from a privileged (secure) batch buffer. + This bit must be 1 if the Per Process GTT Enable bit is clear. + Value Name Description + 0h Per Process + Graphics Address + 1h Global Graphics This command will use the global GTT to translate the Address and this + Address command must be executing from a privileged (secure) batch buffer. + 21:10 Reserved + Format: MBZ + 9:0 DWord Length + Default Value: 0h + Format: =n Total Length - 2. Excludes DWord (0,1). + + + +1 31:12 Page Base Address + Format: GraphicsAddress[31:12] + 4KB aligned Page Address which software requires hardware to flush to DRAM. + + 11:6 Starting Cacheline Offset + Format: U6 Zero based starting cacheline offset to the Page Base Address. + + + + 5:0 Reserved + Format: MBZ +2 31:16 Address + 15:0 Page Base Address + Format: GraphicsAddress[47:32] + This field specifies the 4GB aligned base address of gfx 4GB virtual address space within the host’s + 64-bit virtual address space. + +3..n 31:0 DW Representing ½ Cache Line + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 173 + MI_CLFLUSH + Format: MBZ + + The information given to hardware is the DW itself, not the contents. Hardware uses the DW count of + the command to determine the offset from the base to flush out. The offset is ½ cache line (8 DW = + 1HW) granular so for a full page, the command will need 4096 bytes / 4 bytes per DW / 8 DW per HW + = 128 DW. + Programming Notes + Always even number of "DW Representing 1/2 cacheline" terms must be programmed. + + + + +1.2.9 MI_DISPLAY_FLIP + + MI_DISPLAY_FLIP + +Source: RenderCS +Length Bias: 2 +The MI_DISPLAY_FLIP command is used to request a specific display plane to switch (flip) to display a new buffer. +The buffer is specified with a starting address and pitch. The tiled attribute of the buffer start address is programmed +as part of the packet. The operation this command performs is also known as a “display flip request” operation – in +that the flip operation itself will occur at some point in the future. This command specifies when the flip operation is to +occur: either synchronously with vertical retrace to avoid tearing artifacts (possibly on a future frame), or +asynchronously (as soon as possible) to minimize rendering stalls at the cost of tearing artifacts. + Programming Notes + + This command simply requests a display flip operation -- command execution then continues normally. There is no + guarantee that the flip (even if asynchronous) will occur prior to subsequent commands being executed. (Note that + completion of the PIPE_CONTROL command does not guarantee that outstanding flip operations have completed). + The MI_WAIT_FOR_EVENT command must be used to provide this synchronization to avoid back to back + MI_DISPLAY_FLIP commands to the same display plane – by pausing command execution until a pending flip has + actually completed. This synchronization can also be performed by use of the Display Flip Pending hardware + status. + + After a display flip operation is requested, software is responsible for initiating any required synchronization with + subsequent buffer clear or rendering operations. For multi-buffering (e.g., double buffering) operations, this will + typically require updating SURFACE_STATE or the binding table to change the rendering (back) buffer. In addition, + prior to any subsequent clear or rendering operations, software must typically ensure that the new rendering buffer + is not actively being displayed. Again, the MI_WAIT_FOR_EVENT command or Display Flip Pending hardware + status can be used to provide this synchronization. See Display Flip Synchronization in the Device Programming + Interface chapter of MI Functions. + + The display buffer command uses the X and Y offset for the tiled buffers from the Display Interface registers. + Software is allowed to change the offset via the MMIO interface irrespective of the flip commands enqueued in the + command stream. For tiled buffers, the display subsystem uses the X and Y offset in generation of the final request + to memory. The offset is always updated on the next vblank for both Synchronous and Asynch Flips. It is not + necessary to have a flip enqueued to update the X and Y offset The display buffer command uses the linear dword + offset for the linear buffers from the Display Interface registers. Software is allowed to change the offset via the + MMIO interface irrespective of the flip commands enqueued in the command stream. For linear buffers, the display + subsystem uses the dword offset in generation of the final request to memory. For synchronous flips the offset is + updated on the next vblank. It is not necessary to have a sync flip enqueued to update the dword offset. Linear + memory does not support asynchronous flips DWord 3 (Left Eye Display Buffer Base Address) must not be set with + synchronous flips or asynchronous flips. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 174 + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 14h MI_DISPLAY_FLIP + Format: OpCode + 22 Async Flip Indicator + Format: Enable + This bit should always be set if DW2 [1:0] == ‘01’ (async flip). This field is required due to HW + limitations. This bit is used by the render pipe while DW2 is used by the display hardware. + + 21:19 Display (Plane) Select + + Format: U3 + This field selects which display plane is to perform the flip operation. + Value Name Project + 0h Display Plane A + 1h Display Plane B + 2h Display Sprite A + 3h Display Sprite B + 4h Display Plane C + 5h Display Sprite C + 18:8 Reserved + + Format: MBZ + 7:0 DWord Length + Format: =n + + + Total Length - 2. Excludes DWord (0,1). + For Synchronous Flips and Asynchronous Flips, this field must be programmed to 1h for a total length + of 3. + + + Value Name + 0h [Default] + 1h For Synchronous Flips and Asynchronous Flips +1 31 Reserved + + Format: MBZ + 30:16 Reserved + Format: MBZ + 15:6 Display Buffer Pitch + Default Value: 0h + Format: U10 + For Synchronous Flips, this field specifies the 64-byte aligned pitch of the new display buffer. For + Asynchronous Flips, this parameter is programmed so that all the flips in a flip chain should maintain + the same pitch as programmed with the last synchronous flip or direct through MMIO. + + 5:1 Reserved + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 175 + MI_DISPLAY_FLIP + Format: MBZ + 0 Tile Parameter + + Format: Enable + For Asynchronous Flips, this parameter cannot be changed. All the flips in a flip chain should maintain + the same tile parameter as programmed with the last synchronous flip or direct thru mmio. + Value Name Description + 0h Linear [Default] For Syncronous Flips Only + 1h Tiled X + 2 31:12 Display Buffer Base Address + Format: GraphicsAddress[31:12] + This field specifies Bits 31:12 of the Graphics Address of the new display buffer. + Programming Notes + + The Display buffer must reside completely in Main Memory + + This address is always translated via the global (rather than per-process) GTT + 11:3 Reserved + Format: MBZ + 1:0 Flip Type + + This field specifies whether the flip operation should be performed asynchronously to vertical retrace. + Value Name Description + 00b Sync Flip The flip will occur during the vertical blanking interval – thus avoiding any + [Default] tearing artifacts. + 01b Async Flip The flip will occur "as soon as possible" – and may exhibit tearing artifacts + 11b Reserved + + + Programming Notes + Asynch flips are Supported on X-Tiled Frame buffers only. + For Asynch Flips the Buffers used must be 32KB aligned. + + + + + 1.2.10 MI_FLUSH + + MI_FLUSH + + Source: RenderCS + Length Bias: 1 + Description Project + The MI_FLUSH command is used to perform an internal flush operation. The parser pauses on an internal + flush until all drawing engines have completed any pending operations and the read caches are invalidated + including the texture cache accessed via the Sampler or the data port. In addition, this command can also be + used to: + +2. + + + + + Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 176 + MI_FLUSH + Flush any dirty data in the Render Cache to memory. This is done by default, however this can be + inhibited. +3. + Invalidate the state and command cache. + + Usage note: After this command is completed and followed by a Store DWord-type command, CPU access + to graphics memory will be coherent (assuming the Render Cache flush is not inhibited). This command is + specific to the render engine. Other engines use MI_FLUSH_DW. + + In order to use this command, bit 12 in the MI_MODE(0x209c) must be enabled. + + If GFX_MODE(0x229C) bit 13, this command will cause a config write to MMIO register space with the + address 0x4f100. + MI_FLUSH command is no longer validated or supported. Use at your own risk. + DWord Bit Description + 0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 04h MI_FLUSH + Format: OpCode + 22:7 Reserved + Format: MBZ + 5 Indirect State Pointers Disable + Format: Disable + At the completion of the flush, the indirect state pointers in the hardware will be considered as invalid ie + the indirect pointers will not be restored for the context. + + 4 Generic Media State Clear + + Format: Disable + If set, all generic media state context information will not be included with the next context save, + assuming no new state is initiated after the flush. If clear, the generic media state context save state + will not be affected. An MI_FLUSH with this bit set should be issued once all the Media Objects that will + be processed by a given persistent root thread have been issued or when an MI_SET_CONTEXT + switching from a generic media context to a 3D context completes. When using MI_SET_CONTEXT, + once state is programmed, it will be saved and restarted as part of any context each time that context is + saved/restored until an MI_FLUSH with this bit set is issued in that context. + + 3 Global Snapshot Count Reset + Format: Boolean + The Statistics Counters are also reset; SW should never set this bit during normal operation since the + Statistics Counters are intended to be free running. + Value Name Description + 0h Don’t Do not reset the snapshot counts or Statistics Counters. + Reset + 1h Reset Reset the snapshot count for all the units and reset the Statistics Counters except as + noted above. + + + + + Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 177 + MI_FLUSH + Programming Notes + TIMESTAMP are not reset by MI_FLUSH with this bit set. TIMESTAMP and PS_DEPTH_COUNT can + be reset by writing 0 to them + 2 Render Cache Flush Inhibit + Format: Boolean + If set, the Render Cache is not flushed as part of the processing of this command. + Value Name Description + 0h Flush Flush the Render Cache + 1h Don’t Flush Do not flush the Render Cache + 1 State/Instruction Cache Invalidate + Format: Boolean + If set, Invalidates the State and Instruction Cache + Value Name Description + 0h Don’t Invalidate Leave State/Instruction Cache unaffected + 1h Invalidate Invalidate State/Instruction Cache + 0 Reserved + Format: MBZ + + + + +1.2.11 MI_LOAD_REGISTER_IMM + + MI_LOAD_REGISTER_IMM + +Source: RenderCS +Length Bias: 2 +The MI_LOAD_REGISTER_IMM command requests a write of up to a DWord constant supplied in the command to +the specified Register Offset (i.e., offset into Memory-Mapped Register Range). + Programming Notes Project + + A stalling flush must be sent down pipeline before issuing this command. The behavior of this command is + controlled by Dword 3, Bit 8 (Disable Register Access) of the RINGBUF register. If this command is + disallowed then the command stream converts it to a NOOP. + + If this command is executed from a BB then the behavior of this command is controlled by Dword 0, Bit 8 + (Security Indicator) of the BATCH_BUFFER_START Command. If the batch buffer is insecure then the + command stream converts this command to a NOOP. Note that the corresponding ring buffer must allow a + register update for this command to execute. + + To ensure this command gets executed before upcoming commands in the ring, either a stalling + pipeControl should be sent after this command, or MMIO 0x20C0 bit 7 should be set to 1. + + When base address of 0x180000 is added to the Register Offset, when executed will result in updating of + the register in the other GT in GTB mode of operation then the GT from which this instruction is executed. + When this instruction is executed by Command Streamer with COREID-0 will result in updating the register + in GT with COREID-1 and vice versa, when base address of 0x180000 is added to the register offset. + + The following addresses should NOT be used for LRIs: + 1. 0x8800 - 0x88FF + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 178 + MI_LOAD_REGISTER_IMM + 2. >= 0xC0000 + + Limited LRI cycles to the Display Engine 0x40000-0xBFFFF) are allowed, but must be spaced to allow only + one pending at a time. This can be done by issuing an SRM to the same address immediately after each + LRI. +MI_LOAD_REGISTER_IMM command to program Scanline Register followed by Wait For Event command +with Scanline Wait, should always be programmed in the same cacheline together without any commands +(including pipe control) in between and also should be submitted in the same ring dispatch. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 22h MI_LOAD_REGISTER_IMM + Format: OpCode + 22:12 Reserved + Format: MBZ + 11:8 Byte Write Disables + Format: Enable[4] Bit 8 corresponds to Data DWord [7:0] + + + + + Range: Must specify a valid register write operation + If [11:8] is '1111b', then this command will behave as a NOOP. + Otherwise, the value is forwarded to the destination register. + 7:0 DWord Length + Default Value: 1h + Format: =n Total Length - 2. Excludes DWord (0,1). + + + +1 31:2 Register Offset + Format: MmioAddress[31:2] + This field specifies bits [31:2] of the offset into the Memory Mapped Register Range (i.e., this field + specifies a DWord offset). When the base address of 0x180000 is added to the Register Offset, when + executed will result in updating of the register in the other GT in GTB mode of operation then the GT + from which this instruction is executed. When this instruction is executed by Command Streamer with + COREID-0 will result in updating the register in GT with COREID-1 and vice versa, when base address + of 0x180000 is added to the register offset. + + 1:0 Reserved + Format: MBZ +2 31:0 Data DWord + Mask: Bytes Write Disables + Format: U32 + This field specifies the DWord value to be written to the targeted location. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 179 + 1.2.12 MI_NOOP + + MI_NOOP + +Source: RenderCS +Length Bias: 1 +The MI_NOOP command basically performs a “no operation” in the command stream and is typically used to pad the +command stream (e.g., in order to pad out a batch buffer to a QWord boundary). However, there is one minor +(optional) function this command can perform – a 22-bit value can be loaded into the MI NOPID register. This +provides a general-purpose command stream tagging (“breadcrumb”) mechanism (e.g., to provide sequencing +information for a subsequent breakpoint interrupt). + Programming Notes Project +Performance : The MI_NOOP process time is reduced to 1 clock. An example use of the improved NOOP +throughput is for some multi-pass media applications where some unwanted media object commands are +replaced by MI_NOOP commands without repacking the commands in a batch buffer. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 0h MI_NOOP + 22 Identification Number Register Write Enable + Format: Enable + This field enables the value in the Identification Number field to be written into the MI NOPID + register. If disabled, that register is unmodified, making this command an effective "no operation" + function. + Value Name Description + 0h Disable Do not write the NOP_ID register. + 1h Enable Write the NOP_ID register. + 21:0 Identification Number + Format: U22 + This field contains a 22-bit number which can be written to the MI NOPID register. + + + + +1.2.13 Surface Probing +These commands are only valid when the “Surface Fault Enable” bit is set in the GFX_MODE register. + + +1.2.14 MI_REPORT_HEAD + + MI_REPORT_HEAD + +Source: RenderCS +Length Bias: 1 +The MI_REPORT_HEAD command causes the Head Pointer value of the active ring buffer to be written to a +cacheable (snooped) system memory location. The location written is relative to the address programmed in the +Hardware Status Page Address Register. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 180 + MI_REPORT_HEAD + Programming Notes +This command must not be executed from a Batch Buffer. (Refer to the description of the HWS_PGA register.) + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 07h MI_REPORT_HEAD + Format: OpCode + 22:0 Reserved + Format: MBZ + + + + +1.2.15 MI_SEMAPHORE_MBOX + + MI_SEMAPHORE_MBOX + +Source: RenderCS +Length Bias: 2 + +This command is provided as alternative to MI_SEMAPHORE to provide mailbox-type semaphores where there is +no update of the semaphore by the checking process (the consumer). Single-bit compare-and-update semantics are +also provided. In either case, atomic access of semaphores need not be guaranteed by hardware as with the +previous command. This command should eventually supersede the previous command. + +Synchronization between contexts (especially between contexts running on two different engines) is provided by the +MI_SEMAPHORE_MBOX command. Note that contexts attempting to synchronize in this fashion must be able to +access a common_sli memory location. This means the contexts must share the same virtual address space (have +the same page directory), must have a common physical page mapped into both of their respective address spaces, +or the semaphore commands must be executing from a secure batch buffer or directly from a ring with the Use +Global GTT bit set such that they are privileged and will use the (always shared) global GTT. + + MI_SEMAPHORE with the Update Semaphore bit set (and the Compare Semaphore bit clear) implements the + Signal command, while the Wait command is indicated by Compare Semaphore being set. Note that Wait can + cause a context switch. Signal increments unconditionally. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 16h MI_SEMAPHORE_MBOX + Format: OpCode + 22 Use Global GTT + + If set, this command will use the global GTT to translate the Semaphore Address and this command + must be executing from a privileged (secure) batch buffer. If clear, the PPGTT will be used to translate + the Semaphore Address. + + This bit will be ignored (and treated as if clear) if this command is executed from a non-privileged + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 181 + MI_SEMAPHORE_MBOX + batch buffer. It is allowed for this bit to be clear when executing this command from a privileged + (secure) batch buffer or directly from a ring buffer. + Programming Notes + This field is only valid when Compare Register Field is reset. + 21 Update Semaphore + If set, the value from the Semaphore Data Dword is written to memory. If Compare Semaphore is + also set, the semaphore is not updated if the semaphore comparison fails. If clear, the data at + Semaphore Address is not changed. + Programming Notes + This field should be always clear when Compare Register Field is set. + 20 Compare Semaphore + If set, the value from the Semaphore Data Dword is compared to the value from the Semaphore + Address in memory when Compare Register is clear. If set, the value from the Semaphore Data + Dword is compared to the value from MMIO Register selected by Register Select field when + Compare Register is set. If the value at Semaphore Address/MMIO Register is greater than the + Semaphore Data Dword, execution is continued from the current command buffer. If clear, no + comparison takes place. Update Semaphoremust be set in this case. + 19 Reserved + Format: MBZ + 18 Compare Register + If set, data in MMIO register will be used for compare. If clear, data in memory will be used for + compare. + Programming Notes + Compare Register field should be always set. + 17:16 Register Select + Format: Register Select + If Compare Register is set in bit[18], this field indicates which register will be used. + Value Name Description + 0h RVSYNC VCS Register + 2h RBSYNC BCS Register + 3h Use General Register Select + 15:14 Reserved + Format: MBZ + 13:8 Reserved + + Format: MBZ + 7:0 DWord Length + Default Value: 0h + Format: =n Total Length - 2. Excludes DWord (0,1). + + + +1 31:0 Semaphore Data Dword + Format: U32 + Data dword to compare/update memory. The Data dword is supplied by software to control execution + of the command buffer. If the compare is enabled and the data at Semaphore Address is greater than + this dword, the execution of the command buffer continues. + +2 31:2 PointerBitFieldName/MMIO Register Address + Format: GraphicsVirtualAddress[31:2]Semaphore + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 182 + MI_SEMAPHORE_MBOX + If Compare Register bit[18] is cleared, this field is the Graphics Memory Address of the 32-bit value for + the semaphore. If Compare Register bit[18] is set, this field is the MMIO address of the register for the + semaphore. + + 1:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 183 + 1.2.16 MI_SET_CONTEXT + + MI_SET_CONTEXT + +Source: RenderCS +Length Bias: 2 + +The MI_SET_CONTEXT command is used to specify the logical context associated with the hardware context. A +logical context is an area in memory used to store hardware context information, and the context is referenced via a +2KB-aligned pointer. If the (new) logical context is different (i.e., at a different memory address), the device saves +the current HW context values to the current logical context address, and then restores (loads) the new logical +context by reading the context from the new address and loading it into the hardware context state. If the logical +context address specified in this command matches the current logical context address, this command is effectively +treated as a NOOP. Specific to the Render command stream only. + +This command also includes some controls over the context save/restore process. +  The Force Restore bit can be used to refresh the on-chip device state from the same memory address if the + indirect state buffers have been modified. +  The Restore Inhibit bit can be used to prevent the new context from being loaded at all. This must be used to + prevent an uninitialized context from being loaded. Once software has initialized a context (by setting all state + variables to initial values via commands), the context can then be stored and restored normally. +  This command needs to be always followed by a single MI_NOOP instruction to workaround a silicon issue. +  When switching from a generic media context to a 3D context, the generic media state must be cleared via the + Generic Media State Clear bit 16 in PIPE_CONTROL (or bit 4 in MI_FLUSH) before saving 3D context. +  MI_SET_CONTEXT commands are permitted only within a ring buffer (not within a batch buffer). + + + Programming Notes Project +Workaround : If Flush TLB Invalidation Mode is enabled it is the driver’s responsibility to invalidate the +TLBs at least once after the previous context switch after any GTT mappings changed (including new GTT +entries). This can be done by a pipelined PIPE_CONTROL with TLB inv bit set immediately before +MI_SET_CONTEXT. +MI_ARB_ON_OFF with 'Arbitration Enable Reset' set should be programmed before an MI_SET_CONTEXT +command. MI_ARB_ON_OFF with 'Arbitration Enable' set should be programmed after an +MI_SET_CONTEXT command. This programming ensures that PSMI context switch flows do not conflict +with MI_SET_CONTEXT flows. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 18h MI_SET_CONTEXT + Format: OpCode + 22:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 0h + Format: =n Total Length - 2. Excludes DWord (0,1). + + + +1 31:12 Logical Context Address + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 184 + MI_SET_CONTEXT + + Format: GraphicsAddress[31:12]LogicalContext + + + Description Project + + This field contains the 4KB-aligned graphics memory address of the Logical Context that is to + be loaded into the hardware context. If this address is equal to the CCID register associated + with the current ring, no load will occur. Prior to loading this new context, the device will save + the existing context as required. After the context switch operation completes, this address will + be loaded into the associated CCID register. + This field needs to be 4KB aligned virtual address. + 11:10 Reserved + Format: MBZ + 9 Reserved + + Format: MBZ + 8 Reserved, Must be 1 + Format: Must Be One + 7:5 Reserved + Format: MBZ + 4 Reserved + + Format: MBZ + 3 Extended State Save Enable + + Format: Enable + If set, the extended state identified in the Logical Context Data section of the Memory Data Formats + chapter is saved as part of switching away from this logical context. This bit will be stored in the + associated CCID register to control the context save operation when switching away from this context + (as part of a subsequent MI_SET_CONTEXT command). This bit must be 1 when RS2 power state is + enabled (via MCHBAR, offset 0x11B8) + + 2 Extended State Restore Enable + + Format: Enable + If set, the extended state identified in the Logical Context Data section of the Memory Data Formats + chapter is loaded (or restored) as part of switching to this logical context. This method can be used to + restore things such as filter coefficients using the indirect state restore followed by a restore of the + extended logical context data. This bit affects the switch (if required) to the context specified in Logical + Context Address. This bit will also be stored in the associated CCID register to control a subsequent + context save operation when switching to this context (as part of a subsequent ring buffer switch). This + bit must be 1 when RS2 power state is enabled (via MCHBAR, offset 0x11B8) + + 1 Force Restore + When switching to this logical context a comparison between Logical Context Address and the contests + of the CCID register is performed. Normally, matching addresses prevent a context restore from + occurring; however, when this bit is set a context restore is forced to occur. This bit cannot be set with + Restore Inhibit. Note: This bit is not saved in the associated CCID register. It only affects the + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 185 + MI_SET_CONTEXT + processing of this command. + 0 Restore Inhibit + If set, the restore of the HW context from the logical context specified by Logical Context Address is + inhibited (i.e., the existing HW context values are maintained). This bit must be used to prevent the + loading of an uninitialized logical context. If clear, the context switch proceeds normally. This bit cannot + be set with Force Restore. Note: This bit is not saved in the associated CCID register. It only affects the + processing of this command. + + + + + 1.2.17 MI_STORE_DATA_IMM + + MI_STORE_DATA_IMM + Project: All + Source: RenderCS + Length Bias: 2 + The MI_STORE_DATA_IMM command requests a write of the QWord constant supplied in the packet to the + specified Memory Address. As the write targets a System Memory Address, the write operation is coherent with the + CPU cache (i.e., the processor cache is snooped). + Programming Notes + + + This command should not be used within a "non-privilege" batch buffer to access global virtual space, doing so will + be treated as privilege access violation. Refer “User Mode Privilege Command” in MI_BATCH_BUFFER_START + command section to know HW behavior on encountering privilege access violation. This command can be used + within ring buffers and/or privilege batch buffers to access global virtual space. + + This command can be used for general software synchronization through variables in cacheable memory (i.e., + where software does not need to poll un-cached memory or device registers). + + This command simply initiates the write operation with command execution proceeding normally. Although the + write operation is guaranteed to complete eventually, there is no mechanism to synchronize command execution + with the completion (or even initiation) of these operations. + + + DWord Bit Description + 0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 20h MI_STORE_DATA_IMM + Format: OpCode + 22 Use Global GTT + Project: All + Format: Boolean + If set, this command will use the global GTT to translate the Address and this command must be + executing from a privileged (secure) batch buffer. If clear, the PPGTT will be used. It is allowed for this + bit to be clear when executing this command from a privileged (secure) batch buffer. This bit must be + ‘1’ if the Per Process GTT Enable bit is clear. + + + + + Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 186 + MI_STORE_DATA_IMM + + 21 Reserved + + Format: MBZ + 20:10 Reserved + Format: MBZ + 9:0 DWord Length + Default Value: 2h + Format: =n Total Length - 2. Excludes DWord (0,1) + + + + + Programming Notes + DWord Length programmed must not exceed 0x3FE +1 31:0 Reserved + + Format: MBZ +2 31:2 Address + + Format: GraphicsAddress[31:2]U32(2) + This field specifies Bits 31:2 of the Address where the DWord will be stored. As the store address must + be DWord-aligned, Bits 1:0 of that address MBZ. This address must be 8B aligned for a store "QW" + command. + + 1:0 Reserved + + Format: MBZ +3 31:0 Data DWord 0 + Format: U32 + This field specifies the DWord value to be written to the targeted location.For a QWord write this + DWord is the lower DWord of the QWord to be reported (DW 0). + +4 31:0 Data DWord 1 + Format: U32 + This field specifies the upper DWord value to be written to the targeted QWord location (DW 1). + + + + +1.2.18 MI_STORE_DATA_INDEX + + MI_STORE_DATA_INDEX + +Source: RenderCS +Length Bias: 2 +The MI_STORE_DATA_INDEX command requests a write of the data constant supplied in the packet to the +specified offset from the System Address defined by the Hardware Status Page Address Register. As the write + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 187 + MI_STORE_DATA_INDEX +targets a System Address, the write operation is coherent with the CPU cache (i.e., the processor cache is snooped). + Programming Notes +- +  Use of this command with an invalid or uninitialized value in the Hardware Status Page Address Register is + UNDEFINED. +  This command can be used for general software synchronization through variables in cacheable memory (i.e., + where software does not need to poll uncached memory or device registers). +  This command simply initiates the write operation with command execution proceeding normally. Although the + write operation is guaranteed to complete eventually, there is no mechanism to synchronize command + execution with the completion (or even initiation) of these operations. + + +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 21h MI_STORE_DATA_INDEX + Format: OpCode + 22 Reserved + + + 21 Reserved + + Format: MBZ + 20:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 1h + Format: =n Total Length - 2. Excludes DWord (0,1 ) = 1 for DWord, 2 for QWord. + + + +1 31:12 Reserved + Format: MBZ + 11:2 Offset + Format: U10 zero-based DWord offset into the HW status page. + + + Format: HardwareStatusPageOffset[11:2]U32 + This field specifies the offset (into the hardware status page) to which the data will be written. Note that + the first few DWords of this status page are reserved for special-purpose data storage – targeting these + reserved locations via this command is UNDEFINED. This address must be 8B aligned for a store QW + command. + Value Name + [16, 1023] + 1:0 Reserved + Format: MBZ +2 31:0 Data DWord 0 + Format: U32 + This field specifies the DWord value to be written to the targeted location.For a QWord write this + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 188 + MI_STORE_DATA_INDEX + DWord is the lower DWord of the QWord to be reported (DW 0). + + 3 31:0 Data DWord 1 + Format: U32 + This field specifies the upper DWord value to be written to the targeted QWord location (DW 1). + + + + + 1.2.19 MI_STORE_REGISTER_MEM + + MI_STORE_REGISTER_MEM + Project: All + Source: RenderCS + Length Bias: 2 + The MI_STORE_REGISTER_MEM command requests a register read from a specified memory mapped register + location in the device and store of that DWord to memory. The register address is specified along with the command + to perform the read. + Programming Notes + + + The command temporarily halts command execution. + + The memory address for the write is snooped on the host bus. + + This command should not be used from within a "non-privilege" batch buffer to access global virtual space. doing + so will be treated as privilege access violation. Refer "User Mode Privilege Command" in + MI_BATCH_BUFFER_START command section to know HW behavior on encountering privilege access violation. + This command can be used within ring buffers and/or "privilege" batch buffers to access global virtual space. + + This command will cause undefined data to be written to memory if given register addresses for the + PGTBL_CTL_0 or FENCE registers. + + + DWord Bit Description + 0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 24h MI_STORE_REGISTER_MEM + Format: OpCode + 22 Use Global GTT + It is allowed for this bit to be set when executing this command from a privileged (secure) batch or ring + buffer. This bit must be clear when programmed from within a non-privileged batch buffer. This bit + must be 1 if the Per Process GTT Enable bit is clear. + Value Name Description Project + 0h Per Process + Graphics Address + 1h Global Graphics This command will use the global GTT to translate the Address and + + + + + Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 189 + MI_STORE_REGISTER_MEM + Address this command must be executing from a privileged (secure) batch + buffer. + 21 Reserved + + Format: MBZ + 20:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 1h Excludes DWord (0,1) + Format: =n Total Length - 2 + + + +1 31:26 Reserved + Format: MBZ + 25:2 Register Address + Format: MMIOAddress[25:2]MMIO_Register + This field specifies Bits 25:2 of the Register offset the DWord will be read from. As the register + address must be DWord-aligned, Bits 1:0 of that address MBZ. + Programming Notes +  Storing a VGA register is not permitted and will store an UNDEFINED value. +  The values of PGTBL_CTL0 or any of the FENCE registers cannot be stored to memory; + UNDEFINED values will be written to memory if the addresses of these registers are specified. + + 1:0 Reserved + Format: MBZ +2 31:2 Memory Address + Format: GraphicsAddress[31:2]MMIO_Register + This field specifies the address of the memory location where the register value specified in the + DWord above will be written. The address specifies the DWord location of the data.Range = + GraphicsVirtualAddress[31:2] for a DWord register + + 1:0 Reserved + Format: MBZ + + + + +1.2.20 MI_SUSPEND_FLUSH + + MI_SUSPEND_FLUSH + +Source: RenderCS +Length Bias: 1 + Description Project +Blocks MMIO sync flush or any flushes related to VT-d while enabled. + Programming Notes Project +SW must ensure MI_SUSPEND_FLUSH with "Suspend Flush" enabled have a corresponding +MI_SUSPEND_FLUSH with "Suspend Flush" disabled in the same ring dispatch. SW must also ensure not + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 190 + MI_SUSPEND_FLUSH +to program MI_WAIT_FOR_EVENT command when "Suspend Flush" is enabled. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 0Bh MI_SUSPEND_FLUSH + Format: OpCode + 22:1 Reserved + Format: MBZ + 0 Suspend Flush + Format: Enable + + + Description Project + This field suspends flush due and IOTLB invalidation. + + + Programming Notes Project + Workaround: Make sure that Suspend Flush Enabled and Suspend Flush Disabled are in + the same tail update. + + + + +1.2.21 MI_UPDATE_GTT + + MI_UPDATE_GTT + +Source: RenderCS +Length Bias: 2 + +The MI_UPDATE_GTT command is used to update GTT page table entries in a coherent manner and at a +predictable place in the command flow. + +An MI_FLUSH should be placed before this command, since work associated with preceding commands that are +still in the pipeline may be referencing GTT entries that will be changed by its execution. The flush also invalidates +TLBs and read caches that may become invalid as a result of the changed GTT entries. MI_FLUSH is not required if +it can be guaranteed that the pipeline is free of any work that relies on changing GTT entries (such as +MI_UPDATE_GTT contained in a paging DMA buffer that is doing only update/mapping activities and no rendering). + +This is a privileged command. + +Note that MI_UPDATE_GTT is mainly for the pages that are strictly used by GT. If driver chooses to update the +CPU used pages thru MI_UPDATE_GTT, it needs to write any value to MMIO address 0x101008 to ensure system +agent TLBs are invalidated before the new pages can be used. + + PPGTT updates cannot be done via MI_UPDATE_GTT; gfx driver will have to use MI_STORE_DATA_IMM for + PPGTT inline updates. + DWord Bit Description +0 31:29 Command Type + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 191 + MI_UPDATE_GTT + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 23h MI_UPDATE_GTT + Format: OpCode + 22 Use Global GTT + Reserved: Must be 1h. Updating Per Process Graphics Address is not supported. + Value Name Description + 0h Per Process Graphics Address + 1h Global Graphics Address + 21:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 0h + Format: =n Total Length - 2. Excludes DWord (0,1). + + + +1 31:12 Entry Address + Format: GraphicsAddress[31:12] + This field simply holds the DW offset of the first table entry to be modified. Note that one or more of + the upper bits may need to be 0, i.e., for a 2G aperture, bit 31 MBZ. + + 11:0 Reserved + Format: MBZ +2..n 31:0 Entry Data + Format: Table Entry + This Dword becomes the new page table entry. See PPGTT/Global GTT Table Entries (PTEs) in + Memory Interface Registers. + + + + +1.2.22 MI_USER_INTERRUPT + + MI_USER_INTERRUPT + +Source: RenderCS +Length Bias: 1 +The MI_USER_INTERRUPT command is used to generate a User Interrupt condition. The parser will continue +parsing after processing this command. See User Interrupt. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 02h MI_USER_INTERRUPT + Format: OpCode + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 192 + MI_USER_INTERRUPT + 22:0 Reserved + Format: MBZ + + + + +1.2.23 MI_WAIT_FOR_EVENT + + MI_WAIT_FOR_EVENT + +Source: RenderCS +Length Bias: 1 + Description Project + + The MI_WAIT_FOR_EVENT command is used to pause command stream processing of this pipe only + until a specific event occurs or while a specific condition exists. See Wait Events/Conditions, Device + Programming Interface in MI Functions. Only one event/condition can be specified. Specifying multiple + events is UNDEFINED. + + Once parsed, the parser will halt (and suspend command arbitration) until the event/condition occurs. Note + that if a specified condition does not exist (the condition code is inactive) at the time the parser executes + this command, the parser proceeds, treating this command as a no-operation. + + If CSunit is waiting for V-blank or flip done, HW can go into RC1/RC6 state. + + MI_NOOP setting NOP register (or any other benign command) must be set after MI_WAIT_FOR_EVENT + under the following conditions: +  Back-to-back MI_WAIT_FOR_EVENT commands +  MI_WAIT_FOR_EVENT is the last command before head = tail + +Events must be unmasked in the Display Engine Render Response Mask Register + (DE RRMR 0x44050) prior to waiting for them with a MI_WAIT_FOR_EVENT command, or in the case of +flips + or scanlines, prior to starting the flip or loading the scanline. Unmasked events will wake command + streamer as they occur, so for improved power savings it is recommended to only unmask events that are + required. Programming the DE RRMR register can be done through MMIO or a +LOAD_REGISTER_IMMEDIATE + command. + + Programming Notes Project +Software must always program MI_NOOP command with “Identification Number Register Write Enable” set +following MI_WAIT_FOR_EVENT command to avoid know HW issue. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 03h MI_WAIT_FOR_EVENT + Format: OpCode + 22 Display Pipe C Horizontal Blank Wait Enable + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 193 + MI_WAIT_FOR_EVENT + Format: Enable + This field enables a wait until the start of next Display Pipe C Horizontal Blank event occurs. This + event is described as the start of the next Display C Horizontal blank period. Note that this can cause + a wait for up to a line. + + 21 Display Pipe C Vertical Blank Wait Enable + + Format: Enable + This field enables a wait until the next Display Pipe C Vertical Blank event occurs. This event is + described as the start of the next Display C vertical blank period. Note that this can cause a wait for up + to an entire refresh period. + + 20 Display Sprite C Flip Pending Wait Enable + + Format: Enable + This field enables a wait for the duration of a Display Sprite C Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). + + 19:16 Condition Code Wait Select + + This field enables a wait for the duration that the corresponding condition code is active. These enable + select one of 15 condition codes in the EXCC register, that cause the parser to wait until that + condition-code in the EXCC is cleared. + Value Name Description + 0h Not enabled Condition Code Wait Not Enabled + 1h-5h Enable Condition Code Select Enabled; selects one of 5 codes, 0 – 4 + 6h-15h Reserved + + + Programming Notes + Note that not all condition codes are implemented. The parser operation is UNDEFINED if an + unimplemented condition code is selected by this field. The description of the EXCC register (Memory + Interface Registers) lists the codes that are implemented. + 15 Display Plane C Flip Pending Wait Enable + + Format: Enable + This field enables a wait for the duration of a Display Plane C “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). + + 14 Display Pipe C Scan Line Wait Enable + + Format: Enable + This field enables a wait while a Display Pipe C Scan Line condition exists. This condition is defined as + the start of the scan line specified in the Pipe C Display Scan Line Count Range Compare Register. + + 13 Display Pipe B Horizontal Blank Wait Enable + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 194 + MI_WAIT_FOR_EVENT + Format: Enable + This field enables a wait until the start of next Display Pipe B “Horizontal Blank” event occurs. This + event is described as the start of the next Display B Horizontal blank period. Note that this can cause a + wait for up to a line. + + 12 Reserved + Format: MBZ + 11 Display Pipe B Vertical Blank Wait Enable + Format: U32 + This field enables a wait until the next Display Pipe B “Vertical Blank” event occurs. This event is + described as the start of the next Display Pipe B vertical blank period. Note that this can cause a wait + for up to an entire refresh period. + + 10 Display Sprite B Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Sprite B “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). + + 9 Display Plane B Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Plane B Flip Pending condition. If a flip request is + pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers. + + 8 Display Pipe B Scan Line Wait Enable + Format: Enable + This field enables a wait while a Display Pipe B Scan Line condition exists. This condition is defined as + the start of the scan line specified in the Pipe B Display Scan Line Count Range Compare Register. + + 7:6 Reserved + + Format: MBZ + 5 Display Pipe A Horizontal Blank Wait Enable + + Format: U32 + This field enables a wait until the start of next Display Pipe A Horizontal Blank event occurs. This + event is described as the start of the next Display A Horizontal blank period. Note that this can cause a + wait for up to a line. + + 4 Reserved + Format: MBZ + 3 Display Pipe A Vertical Blank Wait Enable + Format: U32 + This field enables a wait until the next Display Pipe A “Vertical Blank” event occurs. This event is + described as the start of the next Display Pipe A vertical blank period. Note that this can cause a wait + for up to an entire refresh period. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 195 + MI_WAIT_FOR_EVENT + 2 Display Sprite A Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Sprite A “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). + + 1 Display Plane A Flip Pending Wait Enable + Format: Enable + This field enables a wait for the duration of a Display Plane A “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). + + 0 Display Pipe A Scan Line Wait Enable + Format: Enable + This field enables a wait while a Display Pipe A “Scan Line” condition exists. This condition is defined + as the start of the scan line specified in the Pipe A Display Scan Line Count Range Compare Register. + + + + + 1.2.24 MI_LOAD_REGISTER_MEM + + MI_LOAD_REGISTER_MEM + + Source: RenderCS + Length Bias: 2 + The MI_LOAD_REGISTER_MEM command requests from a memory location and stores that DWord to a register. + Programming Notes + + The command temporarily halts commands that will cause cycles down the 3D pipeline. + + This command should not be used within a non-privilege batch buffer to access global virtual space, doing so will + be treated as privilege access violation. Refer "User Mode Privilege Command" in MI_BATCH_BUFFER_START + command section to know HW behavior on encountering privilege access violation. + + This command is not allowed to update the privilege register range when executed from a non-privilege batch + buffer. + + + DWord Bit Description + 0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 29h MI_LOAD_REGISTER_MEM + Format: OpCode + 22 Use Global GTT + This bit if set when executing from a non-privileged batch buffer will be treated as privilege access + + + + + Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 196 + MI_LOAD_REGISTER_MEM + violation. It is allowed for this bit to be clear when executing this command from a privileged (secure) + batch buffer or ring buffer. + Value Name Description + 0h Per Process + Graphics Address + 1h Global Graphics This command will use the global GTT to translate the Address and this + Address command must be executing from a privileged (secure) batch buffer. + 21 Async Mode Enable + Description Project + If this bit is set then the command stream will not wait for completion of this command before + executing the next command. Please refer to the LOAD_INDIRECT and Predicate registers + for usage of this bit. + + + 20:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 1h + Format: =n Total Length - 2. Excludes DWord (0,1). + + + +1 31:26 Reserved + Format: MBZ + 25:2 Register Address + Format: MMIOAddress[22:2]MMIO_Register + This field specifies Bits 25:2 of the Register offset the DWord will be written to. As the register address + must be DWord-aligned, Bits 1:0 of that address MBZ. + + 1:0 Reserved + Format: MBZ +2 31:2 Memory Address + Format: GraphicsAddress[31:2]MMIO_Register + + This field specifies the address of the memory location where the register value specified in the + DWord above will read from. The address specifies the DWord location of the data. + + Range = GraphicsVirtualAddress[31:2] for a DWord register + + 1:0 Reserved + Format: MBZ + + + + +1.2.25 MI_URB_CLEAR + + MI_URB_CLEAR + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 197 + MI_URB_CLEAR +Source: RenderCS +Length Bias: 2 +The MI_URB_CLEAR command allows SW to clear (write zero) to a section in the URB. + Programming Notes +  The command temporarily halts command execution. +  This command is part of context save/restore. Only the last instance will be part of context. +  This command requires the 3D pipeline to be flushed before execution. + + + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 19h MI_URB_CLEAR + Format: OpCode + 22:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 0h + Format: =n Total Length - 2. Excludes DWord (0,1). + + + +1 31:30 Reserved + + Format: MBZ + 29 Reserved + + Format: MBZ + 28:16 URB Clear Length + + This field specifies the number of 256b entries in the URB to be cleared to zero. + Value Name + [0,8191] + 15 Reserved + + Format: MBZ + 14 Reserved + + Format: MBZ + 13:0 URB Address + + Format: URBAddress[18:5] 256b aligned + + + This field specifies Bits 18:5 of the URB Address + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 198 + 1.2.26 MI_PREDICATE +The MI_PREDICATE command is used to control the Predicate state bit, which in turn can be used to +enable/disable the processing of 3DPRIMITIVE commands. + + MI_PREDICATE + +Source: RenderCS +Length Bias: 1 + +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 0Ch MI_PREDICATE + Format: OpCode + 22:8 Reserved + Format: MBZ + 7:6 Load Operation + This field controls if/how the Predicate state bit is modified. + Value Name Description + 0h LOADOP_KEEP The Predicate state bit is unmodified. + 1h Reserved + 2h LOADOP_LOAD The Predicate state bit is loaded with the combine operation result. + 3h LOADOP_LOADINV The Predicate state bit is loaded with the inverted combine operation result. + 5 Reserved + Format: MBZ + 4:3 Combine Operation + This field controls if/how the result of the compare operation is combined with the current Predicate + state bit. + Value Name Description + 0h COMBINEOP_SET The combine operation output the compare result unmodified. + 1h COMBINEOP_AND The combine operation outputs the AND of the compare result and the + current Predicate state bit. + 2h COMBINEOP_OR The combine operation outputs the OR of the compare result and the + current Predicate state bit. + 3h COMBINEOP_XOR The combine operation outputs the XOR of the compare result and the + current Predicate state bit. + 2 Reserved + Format: MBZ + 1:0 Compare Operation + This field controls how Data DWord 0 and Data DWord 1 fields are used to generate a compare + operation result and possibly modify the PredicateData register. + Value Name Description + 0h COMPAREOP_TRUE The compare operation outputs TRUE. The PredicateData + register is unmodified. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 199 + MI_PREDICATE + 1h COMPAREOP_FALSE The compare operation outputs FALSE. The PredicateData + register is unmodified. + 2h COMPAREOP_SRCS_EQUAL (MItemp0 – MItemp1) is computed and loaded into the + PredicateData register. The compare operation outputs + (MItemp0 == MItemp1). + 3h COMPAREOP_DELTAS_EQUAL (MItemp0 – MItemp1) is computed and compared to the + PredicateData register. If the values are equal, the compare + operation outputs TRUE, otherwise it outputs FALSE. The + PredicateData register is unmodified. + + + +1.2.26.1 Predicated Rendering Support in HW +DX10 defines predicated rendering, where sequences of rendering commands can be discarded based +on the result of a previous predicate test. A new state bit, Predicate, has been added to the command +stream. In addition, a PredicateEnable bit is added to 3DPRIMITIVE. When the PredicateEnable bit is set, +the command is ignored if the Predicate state bit is set. +A new command, MI_PREDICATE, is added. It contains several control fields which specify how the +Predicate bit is generated. +Refer to the diagram below and the command description for details. + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 200 + MI_PREDICATE Function + + + + +MI_LOAD_REGISTER_MEM commands can be used to load the MItemp0, MItemp1 and PredicateData +registers prior to MI_PREDIATE. In order to ensure the memory sources of the +MI_LOAD_REGISTER_MEM commands are coherent with previous 3D_PIPECONTROL store-dword +operations, software can use the new Pipe Control Flush Enable bit in the PIPE_CONTROL command. + + +1.2.27 MI_TOPOLOGY_FILTER + + MI_TOPOLOGY_FILTER + +Source: RenderCS +Length Bias: 1 +This command is used to specify a specific 3DPrimType value, where the CS will ignore all 3DPRIMITIVE commands +that do no have a matching 3DPrimType. This primitive culling is optional (turned off by using this command with a +Topology Filter Value of 0). This command is specific to the Render command stream only. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 201 + MI_TOPOLOGY_FILTER + Format: OpCode + 28:23 MI Command Opcode + Default Value: 0Dh MI_TOPOLOGY_FILTER + Format: OpCode + 22:6 Reserved + Format: MBZ + 5:0 Topology Filter Value + Format: 3D_PrimTopoType + When non-zero, the CS will discard all 3DPRIMITIVE commands which do not match the specified + 3DPrimTopologyType. When zero, no filtering is performed (normal operation). + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 202 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V1 Pt 3 – 05 12 5/31/2012 203 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol1_part4.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part4.txt new file mode 100644 index 0000000..a48d8b3 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part4.txt @@ -0,0 +1,7337 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 1 Part 4: Graphics Core™ – Blitter +Engine +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + Contents +1. BLT Engine ........................................................................................................................... 6 + 1.1 Introduction .................................................................................................................... 6 + 1.2 Classical BLT Engine Functional Description ................................................................. 6 + 1.2.1 Basic BLT Functional Considerations..................................................................... 7 + 1.2.2 Basic Graphics Data Considerations .................................................................... 19 + 1.2.3 BLT Programming Examples ............................................................................... 24 + 1.3 BLT Instruction Overview ............................................................................................. 29 + 1.4 BLT Engine State ......................................................................................................... 29 + 1.5 Cacheable Memory Support......................................................................................... 30 + 1.6 Device Cache Coherency: Render & Texture Caches ................................................. 30 + 1.7 BLT Engine Instructions ............................................................................................... 30 + 1.7.1 BLT Programming Restrictions............................................................................. 30 + 1.8 Fill/Move Instructions.................................................................................................... 31 + 1.8.1 COLOR_BLT (Fill) ................................................................................................ 31 + 1.8.2 SRC_COPY_BLT (Move) ..................................................................................... 32 + 1.9 2D (X,Y) BLT Instructions ............................................................................................. 33 + 1.9.1 XY_SETUP_BLT .................................................................................................. 36 + 1.9.2 XY_SETUP_MONO_PATTERN_SL_BLT ............................................................ 38 + 1.9.3 XY_SETUP_CLIP_ BLT ....................................................................................... 40 + 1.9.4 XY_PIXEL_BLT .................................................................................................... 41 + 1.9.5 XY_SCANLINES_BLT .......................................................................................... 42 + 1.9.6 XY_TEXT_BLT ..................................................................................................... 43 + 1.9.7 XY_TEXT_IMMEDIATE_BLT ............................................................................... 44 + 1.9.8 XY_COLOR_BLT ................................................................................................. 45 + 1.9.9 XY_PAT_BLT ....................................................................................................... 47 + 1.9.10 XY_PAT_CHROMA_BLT ..................................................................................... 48 + 1.9.11 XY_PAT_BLT_IMMEDIATE ................................................................................. 50 + 1.9.12 XY_PAT_CHROMA_BLT_IMMEDIATE ............................................................... 52 + 1.9.13 XY_MONO_PAT_BLT .......................................................................................... 54 + 1.9.14 XY_SRC_COPY_BLT .......................................................................................... 62 + 1.9.15 XY_SRC_COPY_CHROMA_BLT ........................................................................ 64 + 1.9.16 XY_MONO_SRC_COPY_BLT ............................................................................. 66 + 1.9.17 XY_MONO_SRC_COPY_ IMMEDIATE_BLT ...................................................... 68 + 1.9.18 XY_FULL_BLT ..................................................................................................... 70 + 1.9.19 XY_FULL_IMMEDIATE_PATTERN_BLT ............................................................. 72 + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 3 + 1.9.20 XY_FULL_MONO_SRC_BLT .............................................................................. 74 + 1.9.21 XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT ...................................... 77 + 1.9.22 XY_FULL_MONO_PATTERN_BLT ..................................................................... 79 + 1.9.23 XY_FULL_MONO_PATTERN_MONO_SRC_BLT ............................................... 82 + 1.10 BLT Engine Instruction Field Definitions....................................................................... 84 + 1.10.1 BR00—BLT Opcode & Control ............................................................................. 85 + 1.10.2 BR01—Setup BLT Raster OP, Control, and Destination Offset ........................... 87 + 1.10.3 BR05—Setup Expansion Background Color ........................................................ 89 + 1.10.4 BR06—Setup Expansion Foreground Color ......................................................... 90 + 1.10.5 BR07— Setup Blit Color Pattern Address ............................................................ 90 + 1.10.6 BR09—Destination Address ................................................................................. 91 + 1.10.7 BR11—BLT Source Pitch (Offset) ........................................................................ 91 + 1.10.8 BR12—Source Address ....................................................................................... 92 + 1.10.9 BR13—BLT Raster OP, Control, and Destination Pitch ....................................... 92 + 1.10.10 BR14—Destination Width & Height .................................................................. 94 + 1.10.11 BR15—Color Pattern Address.......................................................................... 94 + 1.10.12 BR16—Pattern Expansion Background & Solid Pattern Color ......................... 95 + 1.10.13 BR17—Pattern Expansion Foreground Color................................................... 95 + 1.10.14 BR18—Source Expansion Background, and Destination Color ....................... 95 + 1.10.15 BR19—Source Expansion Foreground Color ................................................... 96 +2. Blitter (Blt) Engine Command Streamer ........................................................................... 97 + 2.1 Registers for Blitter Engine ........................................................................................... 97 + 2.1.1 Introduction .......................................................................................................... 97 + 2.1.2 GAB PWR CTX STORAGE REGISTERS ............................................................ 97 + 2.1.3 GFX TLB In Use Virtual Address Registers. ......................................................... 98 + 2.1.4 GFX Pending TLB cycles information registers. ................................................. 102 + 2.1.5 GAB Error Reporting Register ............................................................................ 105 + 2.1.6 Virtual Memory Control ....................................................................................... 106 + 2.1.7 Mode and Misc Ctrl Registers ............................................................................ 108 + 2.1.8 BCS_EXCC — BCS Execute Condition Code Register ..................................... 112 + 2.1.9 BCS_RINGBUF—Ring Buffer Registers ............................................................ 115 + 2.1.10 Interrupt Control Registers ................................................................................. 122 + 2.1.11 Logical Context Support ..................................................................................... 127 + 2.1.12 Software Control Bit Definitions .......................................................................... 133 + 2.2 Memory Interface Commands for Blitter Engine ......................................................... 134 + 2.2.1 Introduction ........................................................................................................ 134 + 2.2.2 MI_ARB_CHECK ............................................................................................... 135 + + + + +4 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.2.3 I_BATCH_BUFFER_END .................................................................................. 135 + 2.2.4 MI_BATCH_BUFFER_START ........................................................................... 136 + 2.2.5 MI_FLUSH_DW.................................................................................................. 137 + 2.2.6 MI_LOAD_REGISTER_IMM .............................................................................. 140 + 2.2.7 MI_NOOP ........................................................................................................... 141 + 2.2.8 MI_REPORT_HEAD .......................................................................................... 142 + 2.2.9 MI_SEMAPHORE_MBOX .................................................................................. 142 + 2.2.10 MI_STORE_REGISTER_MEM .......................................................................... 144 + 2.2.11 MI_STORE_DATA_IMM .................................................................................... 146 + 2.2.12 MI_STORE_DATA_INDEX ................................................................................ 147 + 2.2.13 MI_SUSPEND_FLUSH ...................................................................................... 149 + 2.2.14 MI_UPDATE_GTT.............................................................................................. 149 + 2.2.15 MI_USER_INTERRUPT ..................................................................................... 150 + 2.2.16 MI_WAIT_FOR_EVENT ..................................................................................... 151 + 2.2.17 MI_LOAD_REGISTER_MEM ............................................................................. 153 + 2.2.18 MI_DISPLAY_FLIP............................................................................................. 155 + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 5 + 1. BLT Engine +1.1 Introduction +2D Rendering can be divided into 2 categories: classical BLTs, described here, and 3D BLTs. 3D BLTs +are operations which can take advantage of the 3D drawing engine’s functionality and access patterns. +Functions such as Alpha BLTs, arithmetic (bilinear) stretch BLTs, rotations, transposing pixel maps, color +space conversion, and DIBs are all considered 3D BLTs and are covered in the 3D rendering section. +DIBs can be thought of as an indexed texture which uses the texture palette for performing the data +translation. All drawing engines have swappable context. The same hardware can be used by multiple +driver threads where the current state of the hardware is saved to memory and the appropriate state is +loaded from memory on thread switches. +All operands for both 3D and classical BLTs can be in graphics aperture or cacheable system memory. +Some operands can be immediates which are sent through the command stream. Immediate operands +are: patterns, monochrome sources, DIB palettes, and DIB source operands. All non-monochrome +operands which are not tiled have a stride granularity of a double-word (4 bytes). +The classical BLT commands support both linear addressing and X, Y coordinates with and without +clipping. All X1 and Y1 destination and clipping coordinates are inclusive, while X2 and Y2 are exclusive. +Currently, only destination coordinates can be negative. The source and clipping coordinates must be +positive. If clipping is disabled, but a negative destination coordinate is specified, the negative coordinate +is clipped to 0. Linear address BLT commands must supply a non-zero height and width. If either height +or width = 0, then no accesses occur. + + +1.2 Classical BLT Engine Functional Description +The graphics controller provides a hardware-based BLT engine to off load the work of moving blocks of +graphics data from the host CPU. Although the BLT engine is often used simply to copy a block of +graphics data from the source to the destination, it also has the ability to perform more complex functions. +The BLT engine is capable of receiving three different blocks of graphics data as input as shown in the +figure below. The source data may exist in the frame buffer or the Graphics aperture. The pattern data +always represents an 8x8 block of pixels that can be located in the frame buffer, Graphics aperture, or +passed through a command packet. The pattern data must be located in linear memory. The data already +residing at the destination may also be used as an input. The destination data can also be located in the +frame buffer or graphics aperture. + + + + +6 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + Block Diagram and Data Paths of the BLT Engine +The BLT engine may use any combination of these three different blocks of graphics data as operands, in +both bit-wise logical operations to generate the actual data to be written to the destination, and in per- +pixel write-masking to control the writing of data to the destination. It is intended that the BLT engine will +perform these bit-wise and per-pixel operations on color graphics data that is at the same color depth that +the rest of the graphics system has been set. However, if either the source or pattern data is +monochrome, the BLT engine has the ability to put either block of graphics data through a process called +“color expansion” that converts monochrome graphics data to color. Since the destination is often a +location in the on-screen portion of the frame buffer, it is assumed that any data already at the destination +will be of the appropriate color depth. + + +1.2.1 Basic BLT Functional Considerations + +1.2.1.1 Color Depth Configuration and Color Expansion +The graphics system and BLT engine can be configured for color depths of 8, 16, and 32 bits per pixel. +The configuration of the BLT engine for a given color depth dictates the number of bytes of graphics data +that the BLT engine will read and write for each pixel while performing a BLT operation. It is assumed that +any graphics data already residing at the destination which is used as an input is already at the color +depth to which the BLT engine is configured. Similarly, it is assumed that any source or pattern data used +as an input has this same color depth, unless one or both is monochrome. If either the source or pattern + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 7 + data is monochrome, the BLT engine performs a process called “color expansion” to convert such +monochrome data to color at the color depth to which the BLT engine has been set. +During “color expansion” the individual bits of monochrome source or pattern data that correspond to +individual pixels are converted into 1, 2, or 4 bytes (which ever is appropriate for the color depth to which +the BLT engine has been set). If a given bit of monochrome source or pattern data carries a value of 1, +then the byte(s) of color data resulting from the conversion process are set to carry the value of a +specified foreground color. If a given bit of monochrome source or pattern data carries a value of 0, the +resulting byte(s) are set to the value of a specified background color or not written if transparency is +selected. +The BLT engine is set to a default configuration color depth of 8, 16, or 32 bits per pixel through BLT +command packets. Whether the source and pattern data are color or monochrome must be specified +using command packets. Foreground and background colors for the color expansion of both monochrome +source and pattern data are also specified through the command packets. The source foreground and +background colors used in the color expansion of monochrome source data are specified independently +of those used for the color expansion of monochrome pattern data. + +1.2.1.2 Graphics Data Size Limitations +The BLT engine is capable of transferring very large quantities of graphics data. Any graphics data read +from and written to the destination is permitted to represent a number of pixels that occupies up to 65,536 +scan lines and up to 32,768 bytes per scan line at the destination. The maximum number of pixels that +may be represented per scan line’s worth of graphics data depends on the color depth. +Any source data used as an input must represent the same number of pixels as is represented by any +data read from or written to the destination, and it must be organized so as to occupy the same number of +scan lines and pixels per scan line. +The actual number of scan lines and bytes per scan line required to accommodate data read from or +written to the destination are set in the destination width & height registers or using X and Y coordinates +within the command packets. These two values are essential in the programming of the BLT engine, +because the engine uses these two values to determine when a given BLT operation has been +completed. + +1.2.1.3 Bit-Wise Operations +The BLT engine can perform any one of 256 possible bit-wise operations using various combinations of +the three previously described blocks of graphics data that the BLT engine can receive as input. +The choice of bit-wise operation selects which of the three inputs will be used, as well as the particular +logical operation to be performed on corresponding bits from each of the selected inputs. The BLT engine +automatically foregoes reading any form of graphics data that has not been specified as an input by the +choice of bit-wise operation. An 8-bit code written to the raster operation field of the command packets +chooses the bit-wise operation. The following table lists the available bit-wise operations and their +corresponding 8-bit codes. + +Bit-Wise Operations and 8-Bit Codes (00-3F) + + Value Written to Bits at Value Written to Bits at + Code Destination Code Destination + +00 writes all 0’s 20 D and ( P and ( notS )) +01 not( D or ( P or S ))) 21 not( S or( D xor P )) +02 D and ( not( P or S )) 22 D and ( notS ) + + + + +8 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + Value Written to Bits at Value Written to Bits at + Code Destination Code Destination + +03 not( P or S ) 23 not( S or ( P and ( notD ))) +04 S and ( not( D or P )) 24 ( S xor P ) and ( D xor S ) +05 not( D or P ) 25 not( P xor ( D and ( not( S and P )))) +06 not( P or ( not( D xor S ))) 26 S xor ( D or ( P and S )) +07 not( P or ( D and S )) 27 S xor ( D or ( not( P xor S ))) +08 S and ( D and ( notP )) 28 D and ( P xor S ) +09 not( P or ( D xor S )) 29 not( P xor ( S xor ( D or ( P and S )))) +0A D and ( notP ) 2A D and ( not( P and S )) +0B not( P or ( S and ( notD ))) 2B not( S xor (( S xor P ) and ( P xor D + ))) +0C S and ( notP ) 2C S xor ( P and ( D or S )) +0D not( P or ( D and ( notS ))) 2D P xor ( S or ( notD )) +0E not( P or ( not( D or S ))) 2E P xor ( S or ( D xor P )) +0F notP 2F not( P and ( S or ( notD ))) +10 P and ( not( D or S )) 30 P and ( notS ) +11 not( D or S ) 31 not( S or ( D and ( notP ))) +12 not( S or ( not( D xor P ))) 32 S xor ( D or ( P or S )) +13 not( S or ( D and P )) 33 notS +14 not( D or ( not( P xor S ))) 34 S xor ( P or ( D and S )) +15 not( D or ( P and S )) 35 S xor ( P or ( not( D xor S ))) +16 P xor ( S xor (D and ( not( P and S )))) 36 S xor ( D or P ) +17 not( S xor (( S xor P ) and ( D xor S ))) 37 not( S and ( D or P )) +18 ( S xor P ) and ( P xor D ) 38 P xor ( S and ( D or P )) +19 not( S xor ( D and ( not( P and S )))) 39 S xor ( P or ( notD )) +1A P xor ( D or ( S and P )) 3A S xor ( P or ( D xor S )) +1B not( S xor ( D and ( P xor S ))) 3B not( S and ( P or ( notD ))) +1C P xor ( S or ( D and P )) 3C P xor S +1D not( D xor ( S and ( P xor D ))) 3D S xor ( P or ( not( D or S ))) +1E P xor ( D or S ) 3E S xor ( P or ( D and ( notS ))) +1F not( P and ( D or S )) 3F not( P and S ) + +Notes: +S = Source Data +P = Pattern Data +D = Data Already Existing at the Destination + +Bit-Wise Operations and 8-bit Codes (40 - 7F) + + Value Written to Bits at + Code Destination Code Value Written to Bits at Destination + +40 P and ( S and ( notD )) 60 P and ( D xor S ) +41 not( D or ( P xor S )) 61 not( D xor ( S xor ( P or ( D and S )))) +42 ( S xor D ) and ( P xor D ) 62 D xor ( S and ( P or D )) +43 not( S xor ( P and ( not( D and S )))) 63 S xor ( D or ( notP )) +44 S and ( notD ) 64 S xor ( D and ( P or S )) +45 not( D or ( P and ( notS ))) 65 D xor ( S or ( notP )) +46 D xor ( S or ( P and D )) 66 D xor S +47 not( P xor ( S and ( D xor P ))) 67 S xor ( D or ( not( P or S ))) +48 S and ( D xor P ) 68 not( D xor ( S xor ( P or ( not( D or S + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 9 + Value Written to Bits at + Code Destination Code Value Written to Bits at Destination + + ))))) +49 not( P xor ( D xor ( S or ( P and D )))) 69 not( P xor ( D xor S )) +4A D xor ( P and ( S or D )) 6A D xor ( P and S ) +4B P xor ( D or ( notS )) 6B not( P xor ( S xor ( D and ( P or S )))) +4C S and ( not( D and P )) 6C S xor ( D and P ) +4D not( S xor (( S xor P ) or ( D xor S ))) 6D not( P xor ( D xor ( S and ( P or D )))) +4E P xor ( D or ( S xor P )) 6E S xor ( D and ( P or ( notS ))) +4F not( P and ( D or ( notS ))) 6F not( P and ( not( D xor S ))) +50 P and ( notD ) 70 P and ( not( D and S )) +51 not( D or ( S and ( notP ))) 71 not( S xor (( S xor D ) and ( P xor D ))) +52 D xor (P or ( S and D )) 72 S xor ( D or ( P xor S )) +53 not( S xor ( P and ( D xor S ))) 73 not( S and ( D or ( notP ))) +54 not( D or ( not( P or S ))) 74 D xor ( S or ( P xor D )) +55 notD 75 not( D and ( S or ( notP ))) +56 D xor ( P or S ) 76 S xor ( D or ( P and ( notS ))) +57 not( D and ( P or S )) 77 not( D and S ) +58 P xor ( D and ( S or P )) 78 P xor ( D and S ) +59 D xor ( P or ( notS )) 79 not( D xor ( S xor ( P and ( D or S )))) +5A D xor P 7A D xor ( P and ( S or ( notD ))) +5B D xor ( P or ( not( S or D ))) 7B not( S and ( not( D xor P ))) +5C D xor ( P or ( S xor D )) 7C S xor ( P and ( D or ( notS ))) +5D not( D and ( P or ( notS ))) 7D not( D and ( not( P xor S ))) +5E D xor ( P or ( S and ( notD ))) 7E ( S xor P ) or ( D xor S ) +5F not( D and P ) 7F not( D and ( P and S )) + +Notes: +S = Source Data +P = Pattern Data +D = Data Already Existing at the Destination + +Bit-Wise Operations and 8-bit Codes (80 - BF) + + Value Written to Bits at Value Written to Bits at + Code Destination Code Destination + +80 D and ( P and S ) A0 D and P +81 not(( S xor P ) or ( D xor S )) A1 not( P xor ( D or ( S and ( notP )))) +82 D and ( not( P xor S )) A2 D and ( P or ( notS )) +83 not( S xor ( P and ( D or ( notS )))) A3 not( D xor ( P or ( S xor D ))) +84 S and ( not( D xor P )) A4 not( P xor ( D or ( not( S or P )))) +85 not( P xor ( D and ( S or ( notP )))) A5 not( P xor D ) +86 D xor ( S xor ( P and ( D or S ))) A6 D xor ( S and ( notP )) +87 not( P xor ( D and S )) A7 not( P xor ( D and ( S or P ))) +88 D and S A8 D and ( P or S ) +89 not( S xor ( D or ( P and ( notS )))) A9 not( D xor ( P or S )) +8A D and ( S or ( notP )) AA D +8B not( D xor ( S or ( P xor D ))) AB D or ( not( P or S)) +8C S and ( D or ( notP )) AC S xor (P and ( D xor S )) +8D not( S xor ( D or ( P xor S ))) AD not( D xor ( P or ( S and D ))) +8E S xor (( S xor D ) and ( P xor D )) AE D or ( S and ( notP )) + + + +10 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + Value Written to Bits at Value Written to Bits at + Code Destination Code Destination + +8F not( P and ( not( D and S ))) AF D or ( notP ) +90 P and ( not( D xor S )) B0 P and ( D or ( notS )) +91 not( S xor ( D and ( P or ( notS )))) B1 not( P xor ( D or ( S xor P ))) +92 D xor ( P xor ( S and ( D or P ))) B2 S xor (( S xor P ) or ( D xor S )) +93 not( S xor ( P and D )) B3 not( S and ( not( D and P ))) +94 P xor ( S xor ( D and ( P or S ))) B4 P xor ( S and ( notD )) +95 not( D xor ( P and S )) B5 not( D xor ( P and ( S or D ))) +96 D xor ( P xor S ) B6 D xor ( P xor ( S or ( D and P ))) +97 P xor ( S xor ( D or ( not( P or S )))) B7 not( S and ( D xor P )) +98 not( S xor ( D or ( not( P or S )))) B8 P xor ( S and ( D xor P )) +99 not( D xor S ) B9 not( D xor ( S or ( P and D ))) +9A D xor ( P and ( notS )) BA D or ( P and ( notS )) +9B not( S xor ( D and ( P or S ))) BB D or ( notS ) +9C S xor ( P and ( notD )) BC S xor ( P and ( not( D and S ))) +9D not( D xor ( S and ( P or D ))) BD not(( S xor D ) and ( P xor D )) +9E D xor ( S xor ( P or ( D and S ))) BE D or ( P xor S ) +9F not( P and ( D xor S )) BF D or ( not( P and S )) + +Notes: +S = Source Data +P = Pattern Data +D = Data Already Existing at the Destination + +Bit-Wise Operations and 8-bit Codes (C0 - FF) + + Code Value Written to Bits at Destination Code Value Written to Bits at Destination + +C0 P and S E0 P and ( D or S ) +C1 not( S xor ( P or ( D and ( notS )))) E1 not( P xor ( D or S )) +C2 not( S xor ( P or ( not( D or S )))) E2 D xor ( S and ( P xor D )) +C3 not( P xor S ) E3 not( P xor ( S or ( D and P ))) +C4 S and ( P or ( notD )) E4 S xor ( D and ( P xor S )) +C5 not( S xor ( P or ( D xor S ))) E5 not( P xor ( D or ( S and P ))) +C6 S xor ( D and ( notP )) E6 S xor ( D and ( not( P and S ))) +C7 not( P xor ( S and ( D or P ))) E7 not(( S xor P ) and ( P xor D )) +C8 S and ( D or P ) E8 S xor (( S xor P ) and ( D xor S )) +C9 not( S xor ( P or D )) E9 not( D xor ( S xor ( P and ( not( D and S ))))) +CA D xor ( P and ( S xor D )) EA D or ( P and S ) +CB not( S xor ( P or ( D and S ))) EB D or ( not( P xor S )) +CC S EC S or ( D and P ) +CD S or ( not( D or P )) ED S or ( not( D xor P )) +CE S or ( D and ( notP )) EE D or S +CF S or ( notP ) EF S or ( D or ( notP )) +D0 P and ( S or ( notD )) F0 P +D1 not( P xor ( S or ( D xor P ))) F1 P or ( not( D or S )) +D2 P xor ( D and ( notS )) F2 P or ( D and ( notS )) +D3 not( S xor ( P and ( D or S ))) F3 P or ( notS ) +D4 S xor (( S xor P ) and ( P xor D )) F4 P or ( S and ( notD )) +D5 not( D and ( not( P and S ))) F5 P or ( notD ) +D6 P xor ( S xor ( D or ( P and S ))) F6 P or ( D xor S ) + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 11 + Code Value Written to Bits at Destination Code Value Written to Bits at Destination + +D7 not( D and ( P xor S )) F7 P or ( not( D and S )) +D8 P xor ( D and ( S xor P )) F8 P or ( D and S ) +D9 not( S xor ( D or ( P and S ))) F9 P or ( not( D xor S )) +DA D xor ( P and ( not( S and D ))) FA D or P +DB not(( S xor P ) and ( D xor S )) FB D or ( P or ( notS )) +DC S or ( P and ( notD )) FC P or S +DD S or ( notD ) FD P or ( S or ( notD )) +DE S or ( D xor P ) FE D or ( P or S ) +DF S or ( not( D and P )) FF writes all 1’s + +Notes: +S = Source Data +P = Pattern Data +D = Data Already Existing at the Destination + + + +1.2.1.4 Per-Pixel Write-Masking Operations +The BLT engine is able to perform per-pixel write-masking with various data sources used as pixel masks +to constrain which pixels at the destination are to be written to by the BLT engine. As shown in the figure +below, either monochrome source or monochrome pattern data may be used as pixel masks. Color +pattern data cannot be used. Another available pixel mask is derived by comparing a particular color +range per color channel to either the color already specified for a given pixel at the destination or source. + + + + +12 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + Block Diagram and Data Paths of the BLT Engine +The command packets can specify the monochrome source or the monochrome pattern data as a pixel +mask. When this feature is used, the bits that carry a value of 0 cause the bytes of the corresponding +pixel at the destination to not be written to by the BLT engine, thereby preserving whatever data was +originally carried within those bytes. This feature can be used in writing characters to the display, while +also preserving the pre-existing backgrounds behind those characters. When both operands are in the +transparent mode, the logical AND of the 2 operands are used for the write enables per pixel. +The 3-bit field, destination transparency mode, within the command packets can select per-pixel write- +masking with a mask based on the results of color comparisons. The monochrome source background +and foreground are range compared with either the bytes for the pixels at the destination or the source +operand. This operation is described in the BLT command packet and register descriptions. + +1.2.1.5 When the Source and Destination Locations Overlap +It is possible to have BLT operations in which the locations of the source and destination data overlap. +This frequently occurs in BLT operations where a user is shifting the position of a graphical item on the +display by only a few pixels. In these situations, the BLT engine must be programmed so that destination +data is not written into destination locations that overlap with source locations before the source data at +those locations has been read. Otherwise, the source data will become corrupted. The XY commands +determine whether there is an overlap and perform the accesses in the proper direction to avoid data +corruption. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 13 + The following figure shows how the source data can be corrupted when a rectangular block is copied from +a source location to an overlapping destination location. The BLT engine typically reads from the source +location and writes to the destination location starting with the left-most pixel in the top-most line of both, +as shown in step (a). As shown in step (b), corruption of the source data has already started with the +copying of the top-most line in step (a) — part of the source that originally contained lighter-colored pixels +has now been overwritten with darker-colored pixels. More source data corruption occurs as steps (b) +through (d) are performed. At step (e), another line of the source data is read, but the two right-most +pixels of this line are in the region where the source and destination locations overlap, and where the +source has already been overwritten as a result of the copying of the top-most line in step (a). Starting in +step (f), darker-colored pixels can be seen in the destination where lighter-colored pixels should be. This +errant effect occurs repeatedly throughout the remaining steps in this BLT operation. As more lines are +copied from the source location to the destination location, it becomes clear that the end result is not what +was originally intended. + + + + +14 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + Source Corruption in BLT with Overlapping Source and Destination Locations +The BLT engine can alter the order in which source data is read and destination data is written when +necessary to avoid source data corruption problems when the source and destination locations overlap. +The command packets provide the ability to change the point at which the BLT engine begins reading and + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 15 + writing data from the upper left-hand corner (the usual starting point) to one of the other three corners. +The BLT engine may be set to read data from the source and write it to the destination starting at any of +the four corners of the panel. +The XY command packets perform the necessary comparisons and start at the proper corner of each +operand which avoids data corruption. + + + + +16 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + Correctly Performed BLT with Overlapping Source and Destination Locations +The following figure illustrates how this feature of the BLT engine can be used to perform the same BLT +operation as was illustrated in the figure above, while avoiding the corruption of source data. As shown in +the figure below, the BLT engine reads the source data and writes the data to the destination starting with + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 17 + the right-most pixel of the bottom-most line. By doing this, no pixel existing where the source and +destination locations overlap will ever be written to before it is read from by the BLT engine. By the time +the BLT operation has reached step (e) where two pixels existing where the source and destination +locations overlap are about to be over written, the source data for those two pixels has already been read. + + + + +Suggested Starting Points for Possible Source and Destination Overlap Situations +The figure above shows the recommended lines and pixels to be used as starting points in each of 8 +possible ways in which the source and destination locations may overlap. In general, the starting point +should be within the area in which the source and destination overlap. + + + + +18 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 1.2.2 Basic Graphics Data Considerations + +1.2.2.1 Contiguous vs. Discontinuous Graphics Data +Graphics data stored in memory, particularly in the frame buffer of a graphics system, has organizational +characteristics that often distinguish it from other varieties of data. The main distinctive feature is the +tendency for graphics data to be organized in a discontinuous block of graphics data made up of multiple +sub-blocks of bytes, instead of a single contiguous block of bytes. + +Representation of On-Screen Single 6-Pixel Line in the Frame Buffer + + + + +The figure above shows an example of contiguous graphics data — a horizontal line made up of six +adjacent pixels within a single scan line on a display with a resolution of 640x480. Presuming that the +graphics system driving this display has been set to 8 bits per pixel and that the frame buffer’s starting +address of 0h corresponds to the upper left-most pixel of this display, then the six pixels that make this +horizontal line starting at coordinates (256, 256) occupies the six bytes starting at frame buffer address +28100h, and ending at address 28105h. +In this case, there is only one scan line’s worth of graphics data in this single horizontal line, so the block +of graphics data for all six of these pixels exists as a single, contiguous block comprised of only these six +bytes. The starting address and the number of bytes are the only pieces of information that a BLT engine +would require to read this block of data. +The simplicity of the above example of a single horizontal line contrasts sharply to the example of +discontinuous graphics data depicted in the figure below. The simple six-pixel line of the figure above is +now accompanied by three more six-pixel lines placed on subsequent scan lines, resulting in the 6x4 +block of pixels shown. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 19 + Representation of On-Screen 6x4 Array of Pixels in the Frame Buffer + + + + +Since there are other pixels on each of the scan lines on which this 6x4 block exists that are not part of +this 6x4 block, what appears to be a single 6x4 block of pixels on the display must be represented by a +discontinuous block of graphics data made up of 4 separate sub-blocks of six bytes apiece in the frame +buffer at addresses 28100h, 28380h, 28600h, and 28880h. This situation makes the task of reading what +appears to be a simple 6x4 block of pixels more complex. However, there are two characteristics of this +6x4 block of pixels that help simplify the task of specifying the locations of all 24 bytes of this +discontinuous block of graphics data: all four of the sub-blocks are of the same length, and the four sub- +blocks are separated from each other at equal intervals. +The BLT engine is designed to make use of these characteristics of graphics data to simplify the +programming required to handle discontinuous blocks of graphics data. For such a situation, the BLT +engine requires only four pieces of information: the starting address of the first sub-block, the length of a +sub-block, the offset (in bytes), pitch, of the starting address of each subsequent sub-block, and the +quantity of sub-blocks. + +1.2.2.2 Source Data +The source data may exist in the frame buffer or elsewhere in the graphics aperture where the BLT +engine may read it directly, or it may be provided to the BLT engine by the host CPU through the +command packets. The block of source graphics data may be either contiguous or discontinuous, and +may be either in color (with a color depth that matches that to which the BLT engine has been set) or +monochrome. +The source select bit in the command packets specifies whether the source data exists in the frame buffer +or is provided through the command packets. Monochrome source data is always specified as being +supplied through an immediate command packet. + + + + +20 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + If the color source data resides within the frame buffer or elsewhere in the graphics aperture, then the +Source Address Register, specified in the command packets is used to specify the address of the source. +In cases where the host CPU provides the source data, it does so by writing the source data to ring buffer +directly after the BLT command that requires the data or uses an IMMEDIATE_INDIRECT_BLT command +packet which has a size and pointer to the operand in Graphics aperture. +The block of bytes sent by the host CPU through the command packets must be quadword-aligned and +the source data contained within the block of bytes must also be aligned. +To accommodate discontinuous source data, the source and destination pitch registers can be used to +specify the offset in bytes from the beginning of one scan line’s worth source data to the next. Otherwise, +if the source data is contiguous, then an offset equal to the length of a scan line’s worth of source data +should be specified. + +1.2.2.3 Monochrome Source Data +The opcode of the command packet specifies whether the source data is color or monochrome. Since +monochrome graphics data only uses one bit per pixel, each byte of monochrome source data typically +carries data for 8 pixels which hinders the use of byte-oriented parameters when specifying the location +and size of valid source data. Some additional parameters must be specified to ensure the proper reading +and use of monochrome source data by the BLT engine. The BLT engine also provides additional options +for the manipulation of monochrome source data versus color source data. +The various bit-wise logical operations and per-pixel write-masking operations were designed to work with +color data. In order to use monochrome data, the BLT engine converts it into color through a process +called color expansion, which takes place as a BLT operation is performed. In color expansion the single +bits of monochrome source data are converted into one, two, or four bytes (depending on the color depth) +of color data that are set to carry value corresponding to either the foreground or background color that +have been specified for use in this conversion process. If a given bit of monochrome source data carries +a value of 1, then the byte(s) of color data resulting from the conversion process will be set to carry the +value of the foreground color. If a given bit of monochrome source data carries a value of 0, then the +resulting byte(s) will be set to the value of the background color. The foreground and background colors +used in the color expansion of monochrome source data can be set in the source expansion foreground +color register and the source expansion background color register. +The BLT Engine requires that the bit alignment of each scan line’s worth of monochrome source data be +specified. Each scan line’s worth of monochrome source data is word aligned but can actually start on +any bit boundary of the first byte. Monochrome text is special cased and it is bit or byte packed, where in +bit packed there are no invalid pixels (bits) between scan lines. There is a 3 bit field which indicates the +starting pixel position within the first byte for each scan line, Mono Source Start. +The BLT engine also provides various clipping options for use with specific BLT commands (BLT_TEXT) +with a monochrome source. Clipping is supported through: Clip rectangle Y addresses or coordinates and +X coordinates along with scan line starting and ending addresses (with Y addresses) along with X starting +and ending coordinates. +The maximum immediate source size is 128 bytes. + +1.2.2.4 Pattern Data +The color pattern data must exist within the frame buffer or Graphics aperture where the BLT engine may +read it directly or it can be sent through the command stream. The pattern data must be located in linear +memory. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 21 + Monochrome pattern data is supplied by the command packet when it is to be used. As shown in figure +below, the block of pattern graphics data always represents a block of 8x8 pixels. The bits or bytes of a +block of pattern data may be organized in the frame buffer memory in only one of three ways, depending +upon its color depth which may be 8, 16, or 32 bits per pixel (whichever matches the color depth to which +the BLT engine has been set), or monochrome. +The maximum color pattern size is 256 bytes. + +Pattern Data -- Always an 8x8 Array of Pixels + + + + +The Pattern Address Register is used to specify the address of the color pattern data at which the block +of pattern data begins. The three least significant bits of the address written to this register are ignored, +because the address must be in terms of quadwords. This is because the pattern must always be located +on an address boundary equal to its size. Monochrome patterns take up 8 bytes, or a single quadword of +space, and are loaded through the command packet that uses it. Similarly, color patterns with color +depths of 8, 16, and 32 bits per pixel must start on 64-byte, 128-byte and 256-byte boundaries, +respectively. The next 3 figures show how monochrome, 8bpp, 16bpp, and 32bpp pattern data , +respectively, is organized in memory. + +8bpp Pattern Data -- Occupies 64 Bytes (8 quadwords) + + + + +22 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 16bpp Pattern Data -- Occupies 128 Bytes (16 quadwords) + + + + +32bpp Pattern Data -- Occupies 256 Bytes (32 quadwords) + + + + +The opcode of the command packet specifies whether the pattern data is color or monochrome. The +various bit-wise logical operations and per-pixel write-masking operations were designed to work with +color data. In order to use monochrome pattern data, the BLT engine is designed to convert it into color +through a process called “color expansion” which takes place as a BLT operation is performed. In color +expansion, the single bits of monochrome pattern data are converted into one, two, or four bytes +(depending on the color depth) of color data that are set to carry values corresponding to either the +foreground or background color that have been specified for use in this process. The foreground color is +used for pixels corresponding to a bit of monochrome pattern data that carry the value of 1, while the +background color is used where the corresponding bit of monochrome pattern data carries the value of 0. +The foreground and background colors used in the color expansion of monochrome pattern data can be +set in the Pattern Expansion Foreground Color Register and Pattern Expansion Background Color +Register. + +1.2.2.5 Destination Data +There are actually two different types of “destination data”: the graphics data already residing at the +location that is designated as the destination, and the data that is to be written into that very same +location as a result of a BLT operation. +The location designated as the destination must be within the frame buffer or Graphics aperture where +the BLT engine can read from it and write to it directly. The blocks of destination data to be read from and +written to the destination may be either contiguous or discontinuous. All data written to the destination will +have the color depth to which the BLT engine has been set. It is presumed that any data already existing + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 23 + at the destination which will be read by the BLT engine will also be of this same color depth — the BLT +engine neither reads nor writes monochrome destination data. +The Destination Address Register is used to specify the address of the destination. +To accommodate discontinuous destination data, the Source and Destination Pitch Registers can be +used to specify the offset in bytes from the beginning of one scan line’s worth of destination data to the +next. Otherwise, if the destination data is contiguous, then an offset equal to the length of a scan line’s +worth of destination data should be specified. + + +1.2.3 BLT Programming Examples + +1.2.3.1 Pattern Fill — A Very Simple BLT +In this example, a rectangular area on the screen is to be filled with a color pattern stored as pattern data +in off-screen memory. The screen has a resolution of 1024x768 and the graphics system has been set to +a color depth of 8 bits per pixel. + +On-Screen Destination for Example Pattern Fill BLT + + + + +As shown in the figure above, the rectangular area to be filled has its upper left-hand corner at +coordinates (128, 128) and its lower right-hand corner at coordinates (191, 191). These coordinates +define a rectangle covering 64 scan lines, each scan line’s worth of which is 64 pixels in length — in other +words, an array of 64x64 pixels. Presuming that the pixel at coordinates (0, 0) corresponds to the byte at + + + + +24 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + address 00h in the frame buffer memory, the pixel at (128, 128) corresponds to the byte at address +20080h. + +Pattern Data for Example Pattern Fill BLT + + + + +As shown in figure above, the pattern data occupies 64 bytes starting at address 100000h. As always, the +pattern data represents an 8x8 array of pixels. +The BLT command packet is used to select the features to be used in this BLT operation, and must be +programmed carefully. The vertical alignment field should be set to 0 to select the top-most horizontal row +of the pattern as the starting row used in drawing the pattern starting with the top-most scan line covered +by the destination. The pattern data is in color with a color depth of 8 bits per pixel, so the dynamic color +enable should be asserted with the dynamic color depth field should be set to 0. Since this BLT operation +does not use per-pixel write-masking (destination transparency mode), this field should be set to 0. +Finally, the raster operation field should be programmed with the 8-bit value of F0h to select the bit-wise +logical operation in which a simple copy of the pattern data to the destination takes place. Selecting this +bit-wise operation in which no source data is used as an input causes the BLT engine to automatically +forego either reading source data from the frame buffer. +The Destination Pitch Register must be programmed with number of bytes in the interval from the start of +one scan line’s worth of destination data to the next. Since the color depth is 8 bits per pixel and the +horizontal resolution of the display is 1024, the value to be programmed into these bits is 400h, which is +equal to the decimal value of 1024. +Bits [31:3] of the Pattern Address Register must be programmed with the address of the pattern data. +Similarly, bits [31:0] of the Destination Address Register must be programmed with the byte address at +the destination that will be written to first. In this case, the address is 20080h, which corresponds to the +byte representing the pixel at coordinates (128, 128). +This BLT operation does not use the values in the Source Address Register or the Source Expansion +Background or Foreground Color Registers. +The Destination Width and Height Registers (or the Destination X and Y Coordinates) must be +programmed with values that describe to the BLT engine the 64x64 pixel size of the destination location. +The height should be set to carry the value of 40h, indicating that the destination location covers 64 scan +lines. The width should be set to carry the value of 40h, indicating that each scan line’s worth of +destination data occupies 64 bytes. All of this information is written to the ring buffer using the PAT_BLT +(or XY_PAT_BLT) command packet. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 25 + Results of Example Pattern Fill BLT + + + + +The figure above shows the end result of performing this BLT operation. The 8x8 pattern has been +repeatedly copied (“tiled”) into the entire 64x64 area at the destination. + +1.2.3.2 Drawing Characters Using a Font Stored in System Memory +In this example BLT operation, a lowercase letter “f” is to be drawn in black on a display with a gray +background. The resolution of the display is 1024x768, and the graphics system has been set to a color +depth of 8 bits per pixel. + + + + +26 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + On-Screen Destination for Example Character Drawing BLT + + + + +The figure above shows the display on which this letter “f” is to be drawn. As shown in this figure, the +entire display has been filled with a gray color. The letter “f” is to be drawn into an 8x8 region on the +display with the upper left-hand corner at the coordinates (128, 128). + +Source Data in System Memory for Example Character Drawing BLT + + + + +The figure above shows both the 8x8 pattern making up the letter “f” and how it is represented +somewhere in the host’s system memory — the actual address in system memory is not important. The +letter “f” is represented in system memory by a block of monochrome graphics data that occupies 8 bytes. +Each byte carries the 8 bits needed to represent the 8 pixels in each scan line’s worth of this graphics +data. This type of pattern is often used to store character fonts in system memory. +During this BLT operation, the host CPU will read this representation of the letter “f” from system memory, +and write it to the BLT engine by performing memory writes to the ring buffer as an immediate +monochrome BLT operand following the BLT_TEXT command. The BLT engine will receive this data +through the command stream and use it as the source data for this BLT operation. The BLT engine will be +set to the same color depth as the graphics system — 8 bits per pixel, in this case. Since the source data +in this BLT operation is monochrome, color expansion must be used to convert it to an 8 bpp color depth. +To ensure that the gray background behind this letter “f” is preserved, per-pixel write masking will be +performed, using the monochrome source data as the pixel mask. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 27 + The BLT Setup and Text_immediate command packets are used to select the features to be used in this +BLT operation. Only the fields required by these two command packets must be programmed carefully. +The BLT engine ignores all other registers and fields. The source select field in the Text_immediate +command must be set to 1, to indicate that the source data is provided by the host CPU through the +command packet. Finally, the raster operation field should be programmed with the 8-bit value CCh to +select the bit-wise logical operation that simply copies the source data to the destination. Selecting this +bit-wise operation in which no pattern data is used as an input, causes the BLT engine to automatically +forego reading pattern data from the frame buffer. +The Setup Pattern/Source Expansion Foreground Color Register to specify the color with which the letter +“f” will be drawn. There is no Source address. All scan lines of the glyph are bit packed and the clipping is +controlled by the ClipRect registers from the SETUP_BLT command and the Destination Y1, Y2, X1, and +X2 registers in the TEXT_BLT command. Only the pixels that are within (inclusive comparisons) the clip +rectangle are written to the destination surface. +The Destination Pitch Register must be programmed with a value equal to the number of bytes in the +interval between the first bytes of each adjacent scan line’s worth of destination data. Since the color +depth is 8 bits per pixel and the horizontal resolution of the display is 1024 pixels, the value to be +programmed into these bits is 400h, which is equal to the decimal value of 1024. Since the source data +used in this BLT operation is monochrome, the BLT engine will not use a byte-oriented pitch value for the +source data. +Since the source data is monochrome, color expansion is required to convert it to color with a color depth +of 8 bits per pixel. Since the Setup Pattern/Source Expansion Foreground Color Register is selected to +specify the foreground color of black to be used in drawing the letter “f”, this register must be programmed +with the value for that color. With the graphics system set for a color depth of 8 bits per pixel, the actual +colors are specified in the RAMDAC palette, and the 8 bits stored in the frame buffer for each pixel +actually specify the index used to select a color from that palette. This example assumes that the color +specified at index 00h in the palette is black, and therefore bits [7:0] of this register should be set to 00h +to select black as the foreground color. The BLT engine ignores bits [31:8] of this register because the +selected color depth is 8 bits per pixel. Even though the color expansion being performed on the source +data normally requires that both the foreground and background colors be specified, the value used to +specify the background color is not important in this example. Per-pixel write-masking is being performed +with the monochrome source data as the pixel mask, which means that none of the pixels in the source +data that will be converted to the background color will ever be written to the destination. Since these +pixels will never be seen, the value programmed into the Pattern/Source Expansion Background Color +Register to specify a background color is not important. +The Destination Width and Height Registers are not used. The Y1, Y2, X1, and X2 are used to describe +to the BLT engine the 8x8 pixel size of the destination location. The Destination Y1 and Y2 address (or +coordinate) registers must be programmed with the starting and ending scan line address (or Y +coordinates) of the destination data. This address is specified as an offset from the start of the frame +buffer of the scan line at the destination that will be written to first. The destination X1 and X2 registers +must be programmed with the starting and ending pixel offsets from the beginning of the scan line. +This BLT operation does not use the values in the Pattern Address Register, the Source Expansion +Background Color Register, or the Source Expansion Foreground Color Register. + + + + +28 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + Results of Example Character Drawing BLT + + + + +The preceding shows the end result of performing this BLT operation. Only the pixels that form part of the +actual letter “f” have been drawn into the 8x8 destination location on the display, leaving the other pixels +within the destination with their original gray color. + + +1.3 BLT Instruction Overview +This chapter defines the instructions used to control the 2D (BLT) rendering function. +The instructions detailed in this chapter are used across devices. However, slight changes may be +present in some instructions (i.e., for features added or removed), or some instructions may be removed +entirely. Refer to the Device Dependencies chapter for summary information regarding device-specific +behaviors/interfaces/features. +The XY instructions offload the drivers by providing X and Y coordinates and taking care of the access +directions for overlapping BLTs without fields specified by the driver. +Color pixel sizes supported are 8, 16, and 32 bits per pixel (bpp). All pixels are naturally aligned. + + +1.4 BLT Engine State +Most of the BLT instructions are state-free, which means that all states required to execute the command +is within the instruction. If clipping is not used, then there is no shared state for many of the BLT +instructions. This allows the BLT Engine to be shared by many drivers with minimal synchronization +between the drivers. +Instructions which share state are: + All instructions that are X,Y commands and use the Clipping Rectangle by asserting the Clip + Enable field + All XY_Setup Commands (XY_SETUP_BLT and XY_SETUP_MONO_PATTERN_SL_BLT, + XY_SETUP_CLIP_BLT) load the shared state for the following commands: +XY_PIXEL_BLT (Negative Stride (=Pitch) Not Allowed) + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 29 + XY_SCANLINES_BLT +XY_TEXT_BLT (Negative Stride (=Pitch) Not Allowed) +XY_TEXT_IMMEDIATE_BLT (Negative Stride (=Pitch) Not Allowed) +State registers that are saved & restored in the Logical Context: +BR1+ Setup Control (Solid Pattern Select, Clipping Enable, Mono Source Transparency Mode, Mono Pattern Transparency + Mode, Color Depth[1:0], Raster Operation[7:0], & Destination Pitch[15:0]) + 32bpp Channel Mask[1:0], Mono / Color + Pattern +BR05 Setup Background Color +BR06 Setup Foreground Color +BR07 Setup Pattern Base Address +BR09 Setup Destination Base Address +BR20 DW0 for a Monochrome Pattern +BR21 DW1 for a Monochrome Pattern +BR24 ClipRectY1’X1 +BR25 ClipRectY2’X2 + + + +1.5 Cacheable Memory Support +The BLT Engine can be used to transfer data between cacheable (“system”) memory and uncached +(“main”, or “UC”) graphics memory using the BLT instructions. The GTT must be properly programmed to +map memory pages as cacheable or UC. Only linear-mapped (not tiled) surfaces can be mapped as +cacheable. +Transfers between cacheable sources and cacheable destinations are not supported. Patterns and +monochrome sources can not be located in cacheable memory. +Cacheable write operands do not snoop the processor’s cache nor update memory until evicted from the +render cache. Cacheable read or write operands are not snooped (nor invalidated) from either internal +cache by external (processor, hublink,…) accesses. + + +1.6 Device Cache Coherency: Render & Texture Caches +Software must initiate cache flushes to enforce coherency between the render and texture caches, i.e., +both the render and texture caches must be flushed before a BLT destination surface can be reused as a +texture source. Color sources and destinations use the render cache, while patterns and monochrome +sources use the texture cache. + + +1.7 BLT Engine Instructions +The Instruction Target field is used as an opcode by the BLT Engine state machine to qualify the control +bits that are relevant for executing the instruction. The descriptions for each DWord and bit field are +contained in the BLT Engine Instruction Field Definition section. Each DWord field is described as a +register, but none of these registers can be written of read through a memory mapped location – they are +internal state only. + + +1.7.1 BLT Programming Restrictions +Overlapping Source/Destination BLTs: The following condition must be avoided when programming +the Blt engine: Linear surfaces with a cache line in scan line Y for the source stream overlapping with a +cache line in scan line Y-1 for the dest stream (=> non-aligned surface pitches). The cache coherency + + + + +30 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + rules combined with the Blitter data consumption rules result in UNDEFINED operation. (Note that this +restriction will likely follow forward to future products due to architectural complexities.) There are two +suggested software workarounds: +In order to perform coherent overlapping Blts, (a) the Source and Destination Base Address registers +must hold the same value (without alignment restriction), and (b) the Source and Destination Pitch +registers (BR11,BR13) must both be a multiple of 64 bytes. +If (a) isn’t possible, do overlapping source copy BLTs as two blits, using a separate intermediate surface. +All reserved fields must be programmed to 0s. +When using monosource or text data (bit/byte/word aligned): do not program pixel widths greater than +32,745 pixels. +The other way to do this is driver should always program a dummy 3D + NON-PIPELINE state following the BLT commands. +Immediate Commands: There must be at least 1 command after any immediate blitter commands before +head == tail. This can be a simple MI_NOOP. + + +1.8 Fill/Move Instructions +These instructions use linear addresses with width and height. BLT clipping is not supported. + + +1.8.1 COLOR_BLT (Fill) + + COLOR_BLT + +Length Bias: 2 + +COLOR_BLT is the simplest BLT operation. It performs a color fill to the destination (with a possible ROP). The only +operand is the destination operand which is written dependent on the raster operation. The solid pattern color is +stored in the pattern background register. + + + +This instruction is optimized to run at the maximum memory write bandwidth. + + + + The typical Raster operation code = F0 which performs a copy of the pattern background register to the destination. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 40h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 31 + COLOR_BLT + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:5 Reserved + Format: MBZ + 5:0 DWord Length + Default Value: 03h +1 31:26 Reserved + Format: MBZ +BR13 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch (Signed) + Destination pitch in bytes (Same as before). +2 31:16 Destination Height (in scan lines) + 15:0 Destination Byte Width (in bytes) +BR14 +3 31:0 Destination Address + Address of the first byte to be written. +BR09 +4 31:0 Solid Pattern Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR16 + + + + +1.8.2 SRC_COPY_BLT (Move) + + SRC_COPY_BLT + +Length Bias: 2 + + This BLT instruction performs a color source copy where the only operands involved is a color source and + destination of the same bit width. + + + + The source and destination operands may overlap. The command must indicate the horizontal and vertical + directions: either forward or backwards to avoid data corruption. The X direction (horizontal) field applies to both the + destination and source operands. The source and destination pitches (stride) are signed. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + + + + +32 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + SRC_COPY_BLT + Default Value: 43h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:5 Reserved + Format: MBZ + 5:0 DWord Length + Default Value: 04h +1 31 Reserved + Format: MBZ +BR13 30 X Direction + (1 = written from right to left (decrementing = backwards); 0 = incrementing) + 29:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch (signed) + Destination pitch in bytes (Same as before). +2 31:16 Destination Height (in scan lines) + 15:0 Destination Byte Width (in bytes) +BR14 +3 31:0 Destination Address + Address of the first byte to be written. +BR09 +4 31:16 Reserved + Format: MBZ +BR11 15:0 Source Pitch + (double word aligned and signed) +5 31:0 Source Address + Address of the first byte to be read. +BR12 + + + + +1.9 2D (X,Y) BLT Instructions +Most BLT instructions (prefixed with “XY_”) use 2D X,Y coordinate specifications vs. lower-level linear +addresses. These instructions also support simple 2D clipping against a clip rectangle. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 33 + The top and left Clipping coordinates are inclusive. The bottom and right coordinates are exclusive. The +BLT Engine performs a trivial reject for all CLIP BLT instructions before performing any accesses. +Negative destination and source coordinates are supported. In the case of negative source coordinates, +the destination X1 and Y1 are modified by the absolute value of the negative source coordinate before +the destination clip checking and final drawing coordinates are calculated. The absolute value of the +source negative coordinate is added to the corresponding destination coordinate. The BLT engine +clipping also checks for (DX2 [ or = DX1) or (DY2 [ or = DY1) after this calculation and if true, then the +BLT is totally rejected. + + + + +DX1, DY1, CX1, and CY1 are inclusive, while DX2, DY2, CX2, and CY2 are exclusive. +Destination pixel address = (Destination Base Address + (Destination Y coordinate * Destination pitch) + +(Destination X coordinate * bytes per pixel)). +Source pixel address = (Source Base Address + (Source Y coordinate * Source pitch) + (Source X +coordinate * bytes per pixel)). +Since there is 1 set of Clip Rectangle registers, the Interrupt Ring BLT commands either MUST NEVER +enable clipping with these command and never use the XY_Pixel_BLT, XY_Scanline_BLT, nor +XY_Text_BLT commands or it must use context switching. The Interrupt rings can also use the non- +clipped, linear address commands specified before this section. +The base addresses plus the X and Y coordinates determine if there is an overlap between the source +and destination operands. If the base addresses of the source and destination are the same and the +Source X1 is less than Destination X1, then the BLT Engine performs the accesses in the X-backwards + + + + +34 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + access pattern. There is no need to look for an actual overlap. If the base addresses are the same and +Source Y1 is less than Destination Y1, then the scan line accesses are performed backwards. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 35 + 1.9.1 XY_SETUP_BLT + + XY_SETUP_BLT + +Length Bias: 2 + +This setup instruction supplies common setup information including clipping coordinates used by the XY commands: +XY_PIXEL_BLT, XY_SCANLINE_BLT, XY_TEXT_BLT, and XY_TEXT_BLT_IMMEDIATE. + + + + These are the only instructions that require that state be saved between instructions other than the Clipping + parameters. There are 5 dedicated registers to contain the state for the 3 setup BLT instructions (XY_SETUP_BLT, + XY_SETUP_MONO_PATTERN_SL_BLT, and XY_SETUP_CLIP_BLT. All other BLTs use a temporary version of + these. The 5 double word registers are: DW1 (Setup Control), DW6 (Setup Foreground color), DW5 (Setup + Background color), DW7 (Setup Pattern address), and DW4 (Setup Destination Base Address). +DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 01h + Format: Opcode + 21:20 32 bpp Byte Mask + Value Name + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:12 Reserved + Format: MBZ + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 06h +1 31 Reserved + Format: MBZ +BR01 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29 Mono Source Transparency Mode + Value Name + 0b Use Background + 1b Transparency Enabled + 28:26 Reserved + + + + +36 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_SETUP_BLT + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement (Negative Pitch Not allowed for Pixel nor Text) For Tiled surfaces (bit_11 enabled) + this pitch is of 512Byte granularity for Tile-X, 128B granularity for Tile-Y and can be upto 128Kbytes + (or 32KDwords). +2 31:16 ClipRect Y1 Coordinate (Top) + (30:16 = 15 bit positive number) +BR24 15:0 ClipRect X1 Coordinate (Left) + (14:00 = 15 bit positive number) +3 31:16 ClipRect Y2 Coordinate (Bottom) + (30:16 = 15 bit positive number) +BR25 15:0 ClipRect X2 Coordinate (Right) + (14:00 = 15 bit positive number) +4 31:0 Setup Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Setup Background Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] All +BR05 +6 31:0 Setup Foreground Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] (SLB and TB only) +BR06 +7 31:0 Setup Pattern Base Address for Color Pattern + (26:06 are implemented) (SLB only) (Note no NPO2 change here). The pattern data must be located +BR07 in linear memory. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 37 + 1.9.2 XY_SETUP_MONO_PATTERN_SL_BLT + + XY_SETUP_MONO_PATTERN_SL_BLT + +Length Bias: 2 +This setup instruction supplies common setup information including clipping coordinates used exclusively with the +following instruction: XY_SCANLINE_BLT (SLB) - 1 scan line of monochrome pattern and destination are the only +operands allowed. +DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 11h + Format: Opcode + 21:20 32 bpp Byte Mask + Value Name + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:12 Reserved + Format: MBZ + 11 Tiling Enable + Value Name + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y + 10:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 07h +1 31 Solid Pattern Select + (SLB and Pixel only) +BR01 Value Name + 0 No Solid Pattern + 1 Solid Pattern + 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29 Reserved + Format: MBZ + 28 Mono Pattern Transparency Mode + Value Name + 0b Use Background + 1b Transparency Enabled + 27:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + + + + +38 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_SETUP_MONO_PATTERN_SL_BLT + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement (Negative Pitch Not allowed for Pixel nor Text) For Tiled surfaces (bit_11 enabled) this + pitch is of 512Byte granularity for Tile-X, 128B granularity for Tile-Y and can be upto 128Kbytes (or + 32KDwords). +2 31:16 ClipRect Y1 Coordinate (Top) + (30:16 = 15 bit positive number) +BR24 15:0 ClipRect X1 Coordinate (Left) + (14:00 = 15 bit positive number) +3 31:16 ClipRect Y2 Coordinate (Bottom) + (30:16 = 15 bit positive number) +BR25 15:0 ClipRect X2 Coordinate (Right) + (14:00 = 15 bit positive number) +4 31:0 Setup Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Setup Background Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] All +BR05 +6 31:0 Setup Foreground Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] (SLB and TB only) +BR06 +7 31:0 DW0 (least significant) for a Monochrome Pattern + +BR20 +8 31:0 DW1 (most significant) for a Monochrome Pattern + +BR21 + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 39 + 1.9.3 XY_SETUP_CLIP_ BLT + + XY_SETUP_CLIP_BLT + +Length Bias: 2 +This command is used to only change the clip coordinate registers. These are the same clipping registers as the +Setup clipping registers above. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 03h + Format: Opcode + 21:12 Reserved + Format: MBZ + 11 Tiling Enable + Value Name + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y + 10:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 01h +1 31:16 ClipRect Y1 Coordinate (Top) + (30:16 = 15 bit positive number) +BR24 15:0 ClipRect X1 Coordinate (Left) + (14:00 = 15 bit positive number) +2 31:16 ClipRect Y2 Coordinate (Bottom) + (30:16 = 15 bit positive number) +BR25 15:0 ClipRect X2 Coordinate (Right) + (14:00 = 15 bit positive number) + + + + +40 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 1.9.4 XY_PIXEL_BLT + + XY_PIXEL_BLT + +Length Bias: 2 + +The Destination X coordinate and Destination Y coordinate is compared with the ClipRect registers. If it is within all +4 comparisons, then the pixel supplied in the XY_SETUP_BLT instruction is written with the raster operation to +(Destination Y Address + (Destination Y coordinate * Destination pitch) + (Destination X coordinate * bytes per +pixel)). + + + +ROP field must specify pattern or fill with 0’s or 1’s. There is no source operand. + + + + Negative Stride (= Pitch) specified in the Setup command is Not Allowed + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 24h + Format: Opcode + 21:12 Reserved + Format: MBZ + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 00h +1 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 41 + 1.9.5 XY_SCANLINES_BLT + + XY_SCANLINES_BLT + +Length Bias: 2 + + All scan lines and pixels that fall within the ClipRect Y and X coordinates are written. Only pixels within the + ClipRectX coordinates and the Destination X coordinates are written using the raster operation. + + + + The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the + destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) + modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. + + + + Solid pattern should use the XY_SETUP_MONO_PATTERN_SL_BLT instruction. + + + + ROP field must specify pattern or fill with 0's or 1's. There is no source operand. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 25h + Format: Opcode + 21:15 Reserved + Format: MBZ + 14:12 Pattern Horizontal Seed + Pixel of the scan line to start on corresponding to DST X=0. + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Pattern Vertical Seed + Scan line of the 8x8 pattern to start on corresponding to DST Y=0. + 7:0 DWord Length + Default Value: 01h +1 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +2 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. + + + + +42 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 1.9.6 XY_TEXT_BLT + + XY_TEXT_BLT + +Length Bias: 2 + +All source scan lines and pixels that fall within the ClipRect Y and X coordinates are written. The source address +corresponds to Destination X1 and Y1 coordinate. + + + +Text is either bit or byte packed. Bit packed means that the next scan line starts 1 pixel after the end of the current +scan line with no bit padding. Byte packed means that the next scan line starts on the first bit of the next byte +boundary after the last bit of the current line. + + + +Source expansion color registers are always in the SETUP_BLT. + + + + Negative Stride (= Pitch) is NOT ALLOWED. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 26h + Format: Opcode + 21:17 Reserved + Format: MBZ + 16 Bit / Byte Packed + Byte packed is for the NT driver. + Value Name + 0 Bit + 1 Byte + 15:12 Reserved + Format: MBZ + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 02h +1 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 43 + XY_TEXT_BLT +2 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +3 31:0 Source Address + (address of the first byte on scan line corresponding to Dst X1,Y1). (Note no NPO2 change here) +BR12 + + + + +1.9.7 XY_TEXT_IMMEDIATE_BLT + + XY_TEXT_IMMEDIATE_BLT +Project: +Length Bias: 2 + +This instruction allows the Driver to send data through the instruction stream that eliminates the read latency of +reading a source from memory. + + + +If an operand is in system cacheable memory and either small or only accessed once, it can be copied directly to +the instruction stream versus to graphics accessible memory. The IMMEDIATE_BLT data MUST transfer an even +number of doublewords. + + + +The BLT engine will hang if it does not get an even number of doublewords. All source scan lines and pixels that fall +within the ClipRect X and Y coordinates are written. The source data corresponds to Destination X1 and Y1 +coordinate. + + + + Source expansion color registers are always in the SETUP_BLT. NEGATIVE STRIDE (= PITCH) IS NOT + ALLOWED. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 31h + Format: Opcode + 21:17 Reserved + Format: MBZ + 16 Bit / Byte Packed + Byte packed is for the NT driver. + Value Name + 0 Bit + 1 Byte + + + + +44 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_TEXT_IMMEDIATE_BLT + 15:12 Reserved + Format: MBZ + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Reserved + Format: MBZ + 7:0 DWord Length + 01 + DWL = (Number of Immediate double words)h +1 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +2 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +3 31:0 Immediate Data DW 0 +4 31:0 Immediate Data DW 1 +5..n 31:0 Immediate Data DWs 2 through DWORD_LENGTH (DWL-1) + + + + +1.9.8 XY_COLOR_BLT + + XY_COLOR_BLT + +Length Bias: 2 + + COLOR_BLT is the simplest BLT operation. It performs a color fill to the destination (with a possible ROP). The only + operand is the destination operand which is written dependent on the raster operation. The solid pattern color is + stored in the pattern background register. + + + This instruction is optimized to run at the maximum memory write bandwidth. + + + The typical (and fastest) Raster operation code = F0 which performs a copy of the pattern background register to + the destination. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 50h + Format: Opcode + 21:20 32bpp Byte Mask + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 45 + XY_COLOR_BLT + This field is only used for 32bpp. + Value Name + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:12 Reserved + Format: MBZ + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 04h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement + For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, 128B granularity for + Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Setup Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Solid Pattern Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR16 + + + + +46 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 1.9.9 XY_PAT_BLT + + XY_PAT_BLT + +Length Bias: 2 + + PAT_BLT is used when there is no source and the color pattern is not trivial (is not a solid color only). + + + If clipping is enabled, all scan lines and pixels that fall within the ClipRect Y and X coordinates are written. Only + pixels within the ClipRectX coordinates and the Destination X coordinates are written using the raster operation. + + + + The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the + destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) + modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. +DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 51h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:15 Reserved + Format: MBZ + 14:12 Pattern Horizontal Seed + Pixel of the scan line to start on corresponding to DST X=0. + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Pattern Vertical Seed + Scan line of the 8x8 pattern to start on corresponding to DST Y=0. + 7:0 DWord Length + Default Value: 04h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29:26 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 47 + XY_PAT_BLT + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement (Negative Pitch Not allowed for Pixel nor Text) For Tiled surfaces (bit_11 enabled) + this pitch is of 512Byte granularity for Tile-X, 128B granularity for Tile-Y and can be upto 128Kbytes + (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Pattern Base Address + (28:06 are implemented) (Note no NPO2 change here) . The pattern data must be located in linear +BR15 memory. + + + + +1.9.10 XY_PAT_CHROMA_BLT + + XY_PAT_CHROMA_BLT + +Length Bias: 2 + + PAT_BLT is used when there is no source and the color pattern is not trivial (is not a solid color only). + + + + All scan lines and pixels that fall within the ClipRect Y and X coordinates are written. Only pixels within the + ClipRectX coordinates and the Destination X coordinates are written using the raster operation. + + + + The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the + destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) + modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. +DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + + + +48 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_PAT_CHROMA_BLT + 28:22 Instruction Target(Opcode) + Default Value: 76h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:17 Transparency Range Mode + (chroma-key) – Dst Chroma-key modes ONLY (SRC ILLEGAL) + 16:15 Reserved + Format: MBZ + 14:12 Pattern Horizontal Seed + Pixel of the scan line to start on corresponding to DST X=0. + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Pattern Vertical Seed + Scan line of the 8x8 pattern to start on corresponding to DST Y=0. + 7:0 DWord Length + Default Value: 06h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement (Negative Pitch Not allowed for Pixel nor Text) For Tiled surfaces (bit_11 enabled) + this pitch is of 512Byte granularity for Tile-X, 128B granularity for Tile-Y and can be upto 128Kbytes + (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 49 + XY_PAT_CHROMA_BLT + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit 11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Pattern Base Address + (26:06 are used, other bits are ignored) (Note no NPO2 change here). The pattern data must be +BR15 located in linear memory. +6 31:0 Transparency Color Low + (Chroma-key Low = Pixel Greater or Equal) +BR18 +7 31:0 Transparency Color High + (Chroma-key High = Pixel Less or Equal) +BR19 + + + + +1.9.11 XY_PAT_BLT_IMMEDIATE + + XY_PAT_BLT_IMMEDIATE + +Length Bias: 2 + + PAT_BLT_IMMEDIATE is used when there is no source and the color pattern is not trivial (is not a solid color only) + and the pattern is pulled through the command stream. The immediate data sizes are 64 bytes (16 DWs), 128 bytes + (32 DWs), or 256 (64DWs) for 8, 16, and 32 bpp color patterns. + + + + DWL indicates the total number of Dwords of immediate data. All scan lines and pixels that fall within the ClipRect Y + and X coordinates are written. Only pixels within the ClipRectX coordinates and the Destination X coordinates are + written using the raster operation. + + + + The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the + destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) + modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. +DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 72h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + + + + +50 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_PAT_BLT_IMMEDIATE + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:15 Reserved + Format: MBZ + 14:12 Pattern Horizontal Seed + Pixel of the scan line to start on corresponding to DST X=0. + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Pattern Vertical Seed + Scan line of the 8x8 pattern to start on corresponding to DST Y=0. + 7:0 DWord Length + 03 + DWL = (Number of Immediate double)h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement (Negative Pitch Not allowed for Pixel nor Text) For Tiled surfaces (bit_11 enabled) + this pitch is of 512Byte granularity for Tile-X, 128B granularity for Tile-Y and can be upto 128Kbytes + (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Immediate Data 0 +6 31:0 Immediate Data 1 +7..n 31:0 Immediate Data DWs 2 through DWORD_LENGTH (DWL-1): + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 51 + 1.9.12 XY_PAT_CHROMA_BLT_IMMEDIATE + + XY_PAT_CHROMA_BLT_IMMEDIATE + +Length Bias: 2 + + PAT_BLT_IMMEDIATE is used when there is no source and the color pattern is not trivial (is not a solid color only) + and the pattern is pulled through the command stream. The immediate data sizes are 64 bytes (16 DWs), 128 bytes + (32 DWs), or 256 (64DWs) for 8, 16, and 32 bpp color patterns. + + + + DWL indicates the total number of Dwords of immediate data. All scan lines and pixels that fall within the ClipRect Y + and X coordinates are written. Only pixels within the ClipRectX coordinates and the Destination X coordinates are + written using the raster operation. + + + + The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the + destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) + modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 77h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:17 Transparency Range Mode + (chroma-key) – Dst Chroma-key modes ONLY (SRC ILLEGAL) + 16:15 Reserved + Format: MBZ + 14:12 Pattern Horizontal Seed + Pixel of the scan line to start on corresponding to DST X=0. + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Pattern Vertical Seed + Scan line of the 8x8 pattern to start on corresponding to DST Y=0. + 7:0 DWord Length + 05 + DWL = (Number of Immediate double)h +1 31 Reserved + Format: MBZ + + + + +52 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_PAT_CHROMA_BLT_IMMEDIATE +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Transparency Color Low + (Chroma-key Low = Pixel Greater or Equal) +BR18 +6 31:0 Transparency Color High + (Chroma-key High = Pixel Less or Equal) +BR19 +7 31:0 Immediate Data 0 +8 31:0 Immediate Data 1 +9..n 31:0 Immediate Data DWs 2 through DWORD_LENGTH (DWL-1): + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 53 + 1.9.13 XY_MONO_PAT_BLT + + XY_MONO_PAT_BLT + +Length Bias: 2 + + MONO_PAT_BLT is used when we have no source and the monochrome pattern is not trivial (is not a solid color + only). The monochrome pattern is loaded from the instruction stream. + + + + All scan lines and pixels that fall within the ClipRect Y and X coordinates are written. Only pixels within the + ClipRectX coordinates and the Destination X coordinates are written using the raster operation. + + + + The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the + destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) + modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. + + + + The monochrome pattern transparency mode indicates whether to use the pattern background color or de-assert + the write enables when the bit in the pattern is 0. When the pattern bit is 1, then the pattern foreground color is used + in the ROP operation. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 52h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:15 Reserved + Format: MBZ + 14:12 Pattern Horizontal Seed + Pixel of the scan line to start on corresponding to DST X=0. + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Pattern Vertical Seed + Scan line of the 8x8 pattern to start on corresponding to DST Y=0. + 7:0 DWord Length + Value Name + 07h + + + + +54 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_MONO_PAT_BLT +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29 Reserved + Format: MBZ + 28 Mono Pattern Transparency Mode + Value Name + 0 Use Background + 1 Transparency Enabled + 27:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit 11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Pattern Background Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR16 +6 31:0 Pattern Foreground Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR17 +7 31:0 Pattern Data 0 + +BR20 +8 31:0 Pattern Data 1 + +BR21 + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 55 + 1.9.13.1 XY_MONO_PAT_FIXED_BLT + + XY_MONO_PAT_FIXED_BLT + +Length Bias: 2 + + MONO_PAT_FIXED_BLT is used when we have no source and the monochrome pattern is not trivial (is not a solid + color only). The monochrome pattern is one of 10 fixed patterns described below. The pattern seeds can still be + used with the fixed patterns, creating even more fixed patterns. This eliminates 2 doublewords compared to the + XY_MONO_PAT_BLT command packet. + + + + All scan lines and pixels that fall within the ClipRect Y and X coordinates are written. Only pixels within the + ClipRectX coordinates and the Destination X coordinates are written using the raster operation. + + + + The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the + destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) + modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. + + + + The monochrome pattern transparency mode indicates whether to use the pattern background color or de-assert + the write enables when the bit in the pattern is 0. When the pattern bit is 1, then the pattern foreground color is used + in the ROP operation. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 59h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19 Reserved + Format: MBZ + 18:15 Fixed Pattern + Value Name + 0000b HS_HORIZONTAL + 0001b HS_VERTICAL + 0010b HS_FDIAGONAL + 0011b HS_BDIAGONAL + 0100b HS_CROSS + 0101b HS_DIAGCROSS + 0110b Reserved + 0111b Reserved + + + + +56 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_MONO_PAT_FIXED_BLT + 1000b Screen Door + 1001b SD Wide + 1010b Walking Bit (one) + 1011b Walking Zero + 1100b Reserved + 1101b Reserved + 1110b Reserved + 1111b Reserved + 14:12 Pattern Horizontal Seed + Pixel of the scan line to start on corresponding to DST X=0. + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Pattern Vertical Seed + Scan line of the 8x8 pattern to start on corresponding to DST Y=0. + 7:0 DWord Length + Value Name + 05h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29 Reserved + Format: MBZ + 28 Mono Pattern Transparency Mode + Value Name + 0 Use Background + 1 Transparency Enabled + 27:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 57 + XY_MONO_PAT_FIXED_BLT +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Pattern Background Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR16 +6 31:0 Pattern Foreground Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR17 + + + +1.9.13.2 Monochrome Pattern Memory Format +The monochrome pattern is made of 8 bytes that correspond to the 8 pixels per scan line and 8 scan +lines. Byte 0 corresponds to scan line 0, byte 1 corresponds to scan line 1,…, and byte 7 corresponds to +scan line 7. The bits within each byte are transposed. Pixel 0 is bit 7, pixel 1 is bit 6,…, pixel 7 is bit 0. +The diagram below illustrates the byte and bit relationship to the pixels of the pattern. + + + + +1.9.13.3 HS_HORIZONTAL 0 + + Bit 7 0 + + 0,0 7,0 + + 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 + 1 1 1 1 1 1 1 1 + 0 0 0 0 0 0 0 0 + + + + +58 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 + + +1.9.13.4 HS_VERTICAL 1 + + Bit 7 0 + + 0,0 7,0 + + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + + +1.9.13.5 HS_FDIAGONAL 2 + + Bit 7 0 + + 0,0 7,0 + + 1 0 0 0 0 0 0 0 + 0 1 0 0 0 0 0 0 + 0 0 1 0 0 0 0 0 + 0 0 0 1 0 0 0 0 + 0 0 0 0 1 0 0 0 + 0 0 0 0 0 1 0 0 + 0 0 0 0 0 0 1 0 + 0 0 0 0 0 0 0 1 + + +1.9.13.6 HS_BDIAGONAL 3 + + Bit 7 0 + + 0,0 7,0 + + 0 0 0 0 0 0 0 1 + 0 0 0 0 0 0 1 0 + 0 0 0 0 0 1 0 0 + 0 0 0 0 1 0 0 0 + 0 0 0 1 0 0 0 0 + 0 0 1 0 0 0 0 0 + 0 1 0 0 0 0 0 0 + 1 0 0 0 0 0 0 0 + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 59 + 1.9.13.7 HS_CROSS 4 + + Bit 7 0 + + 0,0 7,0 + + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + 1 1 1 1 1 1 1 1 + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + 0 0 0 0 1 0 0 0 + + +1.9.13.8 HS_DIAGCROSS 5 + + Bit 7 0 + + 0,0 7,0 + + 1 0 0 0 0 0 0 1 + 0 1 0 0 0 0 1 0 + 0 0 1 0 0 1 0 0 + 0 0 0 1 1 0 0 0 + 0 0 0 1 1 0 0 0 + 0 0 1 0 0 1 0 0 + 0 1 0 0 0 0 1 0 + 1 0 0 0 0 0 0 1 + + +1.9.13.9 Screen Door 8 + + Bit 7 0 + + 0,0 7,0 + + 0 1 0 1 0 1 0 1 + 1 0 1 0 1 0 1 0 + 0 1 0 1 0 1 0 1 + 1 0 1 0 1 0 1 0 + 0 1 0 1 0 1 0 1 + 1 0 1 0 1 0 1 0 + 0 1 0 1 0 1 0 1 + 1 0 1 0 1 0 1 0 + + +1.9.13.10 SD Wide 9 + + Bit 7 0 + + 0,0 7,0 + + 1 1 0 0 1 1 0 0 + + + + +60 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 0 0 1 1 0 0 1 1 + 1 1 0 0 1 1 0 0 + 0 0 1 1 0 0 1 1 + 1 1 0 0 1 1 0 0 + 0 0 1 1 0 0 1 1 + 1 1 0 0 1 1 0 0 + 0 0 1 1 0 0 1 1 + + +1.9.13.11 Walking Bit (One) A + + Bit 7 0 + + 0,0 7,0 + + 1 0 0 0 1 0 0 0 + 0 1 0 0 0 1 0 0 + 0 0 1 0 0 0 1 0 + 0 0 0 1 0 0 0 1 + 1 0 0 0 1 0 0 0 + 0 1 0 0 0 1 0 0 + 0 0 1 0 0 0 1 0 + 0 0 0 1 0 0 0 1 + + +1.9.13.12 Walking Zero B + + Bit 7 0 + + 0,0 7,0 + + 0 1 1 1 0 1 1 1 + 1 0 1 1 1 0 1 1 + 1 1 0 1 1 1 0 1 + 1 1 1 0 1 1 1 0 + 0 1 1 1 0 1 1 1 + 1 0 1 1 1 0 1 1 + 1 1 0 1 1 1 0 1 + 1 1 1 0 1 1 1 0 + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 61 + 1.9.14 XY_SRC_COPY_BLT + + XY_SRC_COPY_BLT + +Length Bias: 2 + +This BLT instruction performs a color source copy where the only operands involved is a color source and +destination of the same bit width. + + + +The source and destination operands may overlap, which means that the X and Y directions can be either forward +or backwards. The BLT Engine takes care of all situations. The base addresses plus the X and Y coordinates +determine if there is an overlap between the source and destination operands. If the base addresses of the source +and destination are the same and the Source X1 is less than Destination X1, then the BLT Engine performs the +accesses in the X-backwards access pattern. There is no need to look for an actual overlap. If the base addresses +are the same and Source Y1 is less than Destination Y1, then the scan line accesses start at Destination Y2 with +the corresponding source scan line and the strides are subtracted for every scan line access. + + + + The ROP value chosen must involve source and no pattern data in the ROP operation. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 53h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:16 Reserved + Format: MBZ + 15 Src Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear) + 1b Tiling Enabled (Tile-X or Tile-Y) + 14:12 Reserved + Format: MBZ + 11 Dest Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Reserved + Format: MBZ + + + + +62 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_SRC_COPY_BLT + 7:0 DWord Length + Value Name + 06h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Dest Tiling is enabled (Bit_11 enabled), +BR09 this address is limited to 4Kbytes. +5 31:16 Source Y1 Coordinate (Top) + 16 bit signed number. +BR26 15:0 Source X1 Coordinate (Left) + 16 bit signed number. +6 31:16 Reserved + Format: MBZ +BR11 15:0 Source Pitch (double word aligned) and in DWords + 2's complement. For Tiled Src (bit 15 enabled) this pitch is of 512Byte granularity for Tile-X, 128B + granularity for Tile-Yand can be upto 128Kbytes (or 32KDwords). +7 31:0 Source Base Address + Base address of the destination surface: X=0, Y=0. When Src Tiling is enabled (Bit_15 enabled), +BR12 this address is limited to 4Kbytes. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 63 + 1.9.15 XY_SRC_COPY_CHROMA_BLT + + XY_SRC_COPY_CHROMA_BLT + +Length Bias: 2 + +This BLT instruction performs a color source copy with chroma-keying where the only operands involved is a color +source and destination of the same bit width. + + + +The source and destination operands may overlap, which means that the X and Y directions can be either forward +or backwards. The BLT Engine takes care of all situations. The base addresses plus the X and Y coordinates +determine if there is an overlap between the source and destination operands. If the base addresses of the source +and destination are the same and the Source X1 is less than Destination X1, then the BLT Engine performs the +accesses in the X-backwards access pattern. There is no need to look for an actual overlap. If the base addresses +are the same and Source Y1 is less than Destination Y1, then the scan line accesses start at Destination Y2 with +the corresponding source scan line and the strides are subtracted for every scan line access. + + + + The ROP value chosen must involve source and no pattern data in the ROP operation. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 73h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:17 Transparency Range Mode + (chroma-key) + 16 Reserved + Format: MBZ + 15 Src Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear) + 1b Tiling Enabled (Tile-X or Tile-Y) + 14:12 Reserved + Format: MBZ + 11 Dest Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Reserved + + + + +64 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_SRC_COPY_CHROMA_BLT + Format: MBZ + 7:0 DWord Length + Value Name + 08h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:16 Source Y1 Coordinate (Top) + 16 bit signed number. +BR26 15:0 Source X1 Coordinate (Left) + 16 bit signed number. +6 31:16 Reserved + Format: MBZ +BR11 15:0 Source Pitch (double word aligned) and in DWords + 2's complement. For Tiled Src (bit 15 enabled) this pitch is of 512Byte granularity for Tile-X, 128B + granularity for Tile-Yand can be upto 128Kbytes (or 32KDwords). +7 31:0 Source Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_15 enabled), this +BR12 address is limited to 4Kbytes. +8 31:0 Transparency Color Low + (Chroma-key Low = Pixel Greater or Equal) +BR18 + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 65 + XY_SRC_COPY_CHROMA_BLT +9 31:0 Transparency Color High + (Chroma-key High = Pixel Less or Equal) +BR19 + + + + +1.9.16 XY_MONO_SRC_COPY_BLT + + XY_MONO_SRC_COPY_BLT + +Length Bias: 2 + +This BLT instruction performs a monochrome source copy where the only operands involved is a monochrome +source and destination. The source and destination operands cannot overlap therefore the X and Y directions are +always forward. + + + +All non-text monochrome sources are word aligned. At the end of a scan line of monochrome source, all bits until +the next word boundary are ignored. The monochrome source data bit position field [2:0] indicates the bit position +within the first byte of the scan line that should be used as the first source pixel which corresponds to the destination +X1 coordinate. + + + + The monochrome source transparency mode indicates whether to use the source background color or de-assert the + write enables when the bit in the source is 0. When the source bit is 1, then the source foreground color is used in + the ROP operation. The ROP value chosen must involve source and no pattern data in the ROP operation. + Negative Stride (= Pitch) is NOT ALLOWED. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 54h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:17 Monochrome source data bit position of the first pixel within a byte per scan line. + 16:12 Reserved + Format: MBZ + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + + + + +66 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_MONO_SRC_COPY_BLT + 10:8 Reserved + Format: MBZ + 7:0 DWord Length + Value Name + 06h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29 Mono Source Transparency Mode + Value Name + 0 Use Background + 1 Transparency Enabled + 28:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Source Address + (address corresponding to DST X1,Y1) (Note no NPO2 change here). +BR12 +6 31:0 Source Background Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR18 +7 31:0 Source Foreground Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR19 + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 67 + 1.9.17 XY_MONO_SRC_COPY_ IMMEDIATE_BLT + + XY_MONO_SRC_COPY_IMMEDIATE_BLT + +Length Bias: 2 + +This instruction allows the Driver to send monochrome data through the instruction stream, eliminating the read +latency of the source during command execution. + + + +The IMMEDIATE_BLT data MUST transfer an even number of doublewords and the exact number of quadwords. +DWL indicates the total number of Dwords of immediate data. + + + +All non-text monochrome sources are word aligned. At the end of a scan line of monochrome source, all bits until +the next word boundary are ignored. The Monochrome source data bit position field [2:0] indicates the bit position +within the first byte of the scan line that should be used as the first source pixel which corresponds to the destination +X1 coordinate. + + + +The monochrome source transparency mode indicates whether to use the source background color or de-assert the +write enables when the bit in the source is 0. When the source bit is 1, then the source foreground color is used in +the ROP operation. The ROP value chosen must involve source and no pattern data in the ROP operation. + + + +The monochrome source data supplied corresponds to the Destination X1 and Y1 coordinates. + + + + Negative Stride (= Pitch) is NOT ALLOWED. +DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 71h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:17 Monochrome source data bit position of the first pixel within a byte per scan line. + 16:12 Reserved + Format: MBZ + 11 Dest Tiling Enable + Value Name Description + + + + +68 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_MONO_SRC_COPY_IMMEDIATE_BLT + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 11 Src Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Reserved + Format: MBZ + 7:0 DWord Length + 05 + DWL = (Number of Immediate double words)h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29 Mono Source Transparency Mode + Value Name + 0b Transparency Enabled + 1b Use Background + 28:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Source Background Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR18 +6 31:0 Source Foreground Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 69 + XY_MONO_SRC_COPY_IMMEDIATE_BLT +BR19 +7 31:0 Immediate Data 0 +8 31:0 Immediate Data 1 +9..n 31:0 Immediate Data DWs 2 through DWORD_LENGTH (DWL-1) + + + + +1.9.18 XY_FULL_BLT + + XY_FULL_BLT + +Length Bias: 2 + + The full BLT is the most comprehensive BLT instruction. It provides the ability to specify all 3 operands: destination, + source, and pattern. The source and pattern operands are the same bit width as the destination operand. + + + + The source and destination operands may overlap, which means that the X and Y directions can be either forward + or backwards. The BLT Engine takes care of all situations. The base addresses plus the X and Y coordinates + determine if there is an overlap between the source and destination operands. If the base addresses of the source + and destination are the same and the Source X1 is less than Destination X1, then the BLT Engine performs the + accesses in the X-backwards access pattern. There is no need to look for an actual overlap. If the base addresses + are the same and Source Y1 is less than Destination Y1, then the scan line accesses start at Destination Y2 with + the corresponding source scan line and the strides are subtracted for every scan line access. + + + + All scan lines and pixels that fall within the ClipRect Y and X coordinates are written. Only pixels within the + ClipRectX coordinates and the Destination X coordinates are written using the raster operation. + + + + The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the + destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) + modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 55h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:16 Reserved + + + + +70 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_FULL_BLT + Format: MBZ + 15 Src Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 14:12 Pattern Horizontal Seed + Pixel of the scan line to start on corresponding to DST X=0. + 11 Dest Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (-X or Tile-Y) + 10:8 Pattern Vertical Seed + Starting scan line of the 8x8 pattern corresponding to DST Y=0. + 7:0 DWord Length + Default Value: 07h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:16 Reserved + Format: MBZ +BR11 Should be programmed all 0's for 48bit addressing. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 71 + XY_FULL_BLT + 15:0 Source Pitch (double word aligned and signed) and in DWords + 2's complement. For Tiled Src (bit 15 enabled) this pitch is of 512Byte granularity for Tile-X, 128B + granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +6 31:16 Source Y1 Coordinate (Top) + 16 bit signed number. +BR26 15:0 Source X1 Coordinate (Left) + 16 bit signed number. +7 31:0 Source Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_15 enabled), this +BR12 address is limited to 4Kbytes. +8 31:0 Pattern Base + (28:06 are implemented ) (Note no NPO2 change here). The pattern data must be located in linear +BR15 memory. + + + + +1.9.19 XY_FULL_IMMEDIATE_PATTERN_BLT + + XY_FULL_IMMEDIATE_PATTERN_BLT + +Length Bias: 2 + + The full BLT is the most comprehensive BLT instruction. It provides the ability to specify all 3 operands: destination, + source, and pattern. The source and immediate pattern operands are the same bit width as the destination operand. + The immediate data sizes are 64 bytes (16 DWs), 128 bytes (32 DWs), or 256 (64 DWs) for 8, 16, and 32 bpp color + patterns. DWL indicates the total number of Dwords of immediate data. + + + + The source and destination operands may overlap, which means that the X and Y directions can be either forward + or backwards. The BLT Engine takes care of all situations. The base addresses plus the X and Y coordinates + determine if there is an overlap between the source and destination operands. If the base addresses of the source + and destination are the same and the Source X1 is less than Destination X1, then the BLT Engine performs the + accesses in the X-backwards access pattern. There is no need to look for an actual overlap. If the base addresses + are the same and Source Y1 is less than Destination Y1, then the scan line accesses start at Destination Y2 with + the corresponding source scan line and the strides are subtracted for every scan line access. + + + + All scan lines and pixels that fall within the ClipRect Y and X coordinates are written. Only pixels within the + ClipRectX coordinates and the Destination X coordinates are written using the raster operation. + + + + The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the + destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) + modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + + + + +72 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_FULL_IMMEDIATE_PATTERN_BLT + 28:22 Instruction Target(Opcode) + Default Value: 74h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:16 Reserved + Format: MBZ + 15 Src Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear) + 1b Tiling Enabled (Tile-X or Tile-Y) + 14:12 Pattern Horizontal Seed + (pixel of the scan line to start on corresponding to DST X=0) + 11 Dest Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Reserved + Format: MBZ + 7:0 DWord Length + 06 + DWL = (Number of Immediate double words)h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 73 + XY_FULL_IMMEDIATE_PATTERN_BLT +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Src Tiling is enabled (Bit_15 enabled), this +BR09 address is limited to 4Kbytes. +5 31:16 Reserved + Format: MBZ +BR11 Should be programmed all 0's for 48bit addressing. + + 15:0 Source Pitch (double word aligned and signed) and in DWords + 2's complement. For Tiled Src (bit 11 enabled) this pitch is of 512Byte granularity for Tile-X, 128B + granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +6 31:16 Source Y1 Coordinate (Top) + 16 bit signed number. +BR26 15:0 Source X1 Coordinate (Left) + 16 bit signed number. +7 31:0 Source Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit 15 enabled), this +BR12 address is limited to 4Kbytes. +8 31:0 Immediate Data 0 +9 31:0 Immediate Data 1 +10..n 31:0 Immediate Data DWs 2 through DWORD_LENGTH (DWL-1) + + + + +1.9.20 XY_FULL_MONO_SRC_BLT + + XY_FULL_MONO_SRC_BLT + +Length Bias: 2 + +The full BLT is the most comprehensive BLT instruction. It provides the ability to specify all 3 operands: destination, +source, and pattern. The source operand is monochrome and the pattern operand is the same bit width as the +destination. + + + +The monochrome source transparency mode indicates whether to use the source background color or de-assert the +write enables when the bit in the source is 0. When the source bit is 1, then the source foreground color is used in +the ROP operation. + + + +All non-text and non-immediate monochrome sources are word aligned. At the end of a scan line the monochrome +source, the remaining bits until the next word boundary are ignored. The Monochrome source data bit position field +[2:0] indicates which bit position within the first byte should be used as the first source pixel which corresponds to +the Destination X1 coordinate. + + + + +74 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_FULL_MONO_SRC_BLT + +All scan lines and pixels that fall within the ClipRect Y and X coordinates are written. Only pixels within the +ClipRectX coordinates and the Destination X coordinates are written using the raster operation. + + + +The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the +destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) +modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. + + + + Negative Stride (= Pitch) is NOT ALLOWED + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 56h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:17 Monochrome source data bit position of the first pixel within a byte per scan line. + 16:15 Reserved + Format: MBZ + 14:12 Pattern Horizontal Seed + (pixel of the scan line to start on corresponding to DST X=0) + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Pattern Vertical Seed + Starting scan line of the 8x8 pattern corresponding to DST Y = 0. + 7:0 DWord Length + Value Name + 07h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29 Mono Source Transparency Mode + Value Name + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 75 + XY_FULL_MONO_SRC_BLT + 0 Use Background + 1 Transparency Enabled + 28:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Mono Source Address + (address corresponds to DST X1, Y1) (Note no NPO2 change here). +BR12 +6 31:0 Source Background Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR18 +7 31:0 Source Foreground Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR19 +8 31:0 Pattern Base Address + (28:06 are implemented ) (Note no NPO2 change here). The pattern data must be located in linear +BR15 memory. + + + + +76 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 1.9.21 XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT + + + XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT + +Length Bias: 2 + +The full BLT is the most comprehensive BLT instruction. It provides the ability to specify all 3 operands: destination, +source, and pattern. The source operand is a monochrome and the immediate pattern operand is the same bit width +as the destination. The immediate data sizes are 64 bytes (16 DWs), 128 bytes (32 DWs), or 256 (64DWs) for 8, 16, +and 32 bpp color patterns. + + + +The monochrome source transparency mode indicates whether to use the source background color or de-assert the +write enables when the bit in the source is 0. When the source bit is 1, then the source foreground color is used in +the ROP operation. + + + +All non-text monochrome sources are word aligned. At the end of a scan line the monochrome source, the +remaining bits until the next word boundary are ignored. The Monochrome source data bit position field [2:0] +indicates which bit position within the first byte should be used as the first source pixel which corresponds to the +destination X1 coordinate. + + + +All scan lines and pixels that fall within the ClipRect Y and X coordinates are written. Only pixels within the +ClipRectX coordinates and the Destination X coordinates are written using the raster operation. + + + +The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the +destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) +modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. + + + + Negative Stride (= Pitch) is NOT ALLOWED. +DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 75h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 77 + XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT + 19:17 Monochrome source data bit position of the first pixel within a byte per scan line. + 16:15 Reserved + Format: MBZ + 14:12 Pattern Horizontal Seed + (pixel of the scan line to start on corresponding to DST X=0) + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Reserved + Format: MBZ + 7:0 DWord Length + 06 + DWL = (Number of Immediate double words)h +1 31 Reserved + Format: MBZ +BR13 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29 Mono Source Transparency Mode + Value Name + 0 Use Background + 1 Transparency Enabled + 28:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Mono Source Address + (address corresponds to DST X1, Y1) (Note no NPO2 change here). + + + +78 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT +BR12 +6 31:0 Source Background Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR18 +7 31:0 Source Foreground Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR19 +8 31:0 Immediate Data DW 0 +9 31:0 Immediate Data DW 1 +10..n 31:0 Immediate Data DWs 2 through DWORD_LENGTH (DWL-1) + + + + +1.9.22 XY_FULL_MONO_PATTERN_BLT + + XY_FULL_MONO_PATTERN_BLT + +Length Bias: 2 + +The full BLT is the most comprehensive BLT instruction. It provides the ability to specify all 3 operands: destination, +source, and pattern. The pattern operand is monochrome and the source operand is the same bit width as the +destination operand. + + + +The source and destination operands may overlap, which means that the X and Y directions can be either forward +or backwards. The BLT Engine takes care of all situations. The base addresses plus the X and Y coordinates +determine if there is an overlap between the source and destination operands. If the base addresses of the source +and destination are the same and the Source X1 is less than Destination X1, then the BLT Engine performs the +accesses in the X-backwards access pattern. There is no need to look for an actual overlap. If the base addresses +are the same and Source Y1 is less than Destination Y1, then the scan line accesses start at Destination Y2 with +the corresponding source scan line and the strides are subtracted for every scan line access. + + + +The monochrome pattern transparency mode indicates whether to use the pattern background color or de-assert +the write enables when the bit in the source is 0. When the source bit is 1, then the pattern foreground color is used +in the ROP operation. + + + +All scan lines and pixels that fall within the ClipRect Y and X coordinates are written. Only pixels within the +ClipRectX coordinates and the Destination X coordinates are written using the raster operation. + + + +The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the +destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) +modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 79 + XY_FULL_MONO_PATTERN_BLT + Setting both Solid Pattern Select =1 and Mono Pattern Transparency = 1 is mutually exclusive. The device + implementation results in NO PIXELs DRAWN. + DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 57h + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:16 Reserved + 15 Src Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 14:12 Pattern Horizontal Seed + (pixel of the scan line to start on corresponding to DST X=0) + 11 Dest Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Pattern Vectical Seed + Starting scan line of the 8x8 pattern corresponding to DST Y=0. + 7:0 DWord Length + Value Name + 0Ah +1 31 Solid Pattern Select + Value Name +BR13 0 No Solid Pattern + 1 Solid Pattern + 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29 Reserved + Format: MBZ + 28:27 Mono Source Transparency Mode + Value Name + 0 Use Background + 1 Transparency Enabled + 26 Reserved + Format: MBZ + + + + +80 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_FULL_MONO_PATTERN_BLT + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:16 Reserved + Format: MBZ +BR11 15:0 Source Pitch (double word aligned and signed) and in DWords + 2's complement. For Tiled Src (bit 15 enabled) this pitch is of 512Byte granularity for Tile-X, 128B + granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +6 31:16 Source Y1 Coordinate (Top) + 16 bit signed number. +BR26 15:0 Source X1 Coordinate (Left) + 16 bit signed number. +7 31:0 Source Base Address + (base address of the source surface: X=0, Y=0). When Src Tiling is enabled (Bit 15 enabled), this +BR12 address is limited to 4Kbytes. +8 31:0 Pattern Background Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR16 +9 31:0 Pattern Foreground Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR17 +10 31:0 Pattern Data 0 + (least significant DW) +BR20 +11 31:0 Pattern Data 1 + (most significant DW) +BR21 + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 81 + 1.9.23 XY_FULL_MONO_PATTERN_MONO_SRC_BLT + + XY_FULL_MONO_PATTERN_MONO_SRC_BLT + +Length Bias: 2 + +The full BLT provides the ability to specify all 3 operands: destination, source, and pattern. The pattern and source +operands are monochrome. + + + +The monochrome source transparency mode indicates whether to use the source background color or de-assert the +write enables when the bit in the source is 0. When the source bit is 1, then the source foreground color is used in +the ROP operation. + + + +All non-text monochrome sources are word aligned. At the end of a scan line the monochrome source, the +remaining bits until the next word boundary are ignored. The Monochrome source data bit position field [2:0] +indicates which bit position within the first byte should be used as the first source pixel which corresponds to the +destination X1 coordinate. + + + +The monochrome pattern transparency mode indicates whether to use the pattern background color or de-assert +the write enables when the bit in the pattern is 0. When the source bit is 1, then the pattern foreground color is used +in the ROP operation. The monochrome source transparency mode works identical to the pattern transparency +mode. + + + +All scan lines and pixels that fall within the ClipRect Y and X coordinates are written. Only pixels within the +ClipRectX coordinates and the Destination X coordinates are written using the raster operation. + + + +The Pattern Seeds correspond to Destination X = 0 (horizontal) and Y = 0 (vertical). The alignment is relative to the +destination coordinates. The pixel of the pattern used / scan line is the (destination X coordinate + horizontal seed) +modulo 8. The scan line of the pattern used is the (destination Y coordinate + vertical seed) modulo 8. + + + +Setting both Solid Pattern Select =1 and Mono Pattern Transparency = 1 is mutually exclusive. The device +implementation results in NO PIXELs DRAWN. + + + + Negative Stride (= Pitch) is NOT ALLOWED. +DWord Bit Description +0 31:29 Client + Default Value: 02h 2D Processor +BR00 Format: Opcode + 28:22 Instruction Target(Opcode) + Default Value: 58h + + + + +82 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + XY_FULL_MONO_PATTERN_MONO_SRC_BLT + Format: Opcode + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:17 Monochrome source data bit position of the first pixel within a byte per scan line. + 16:15 Reserved + Format: MBZ + 14:12 Pattern Horizontal Seed + (pixel of the scan line to start on corresponding to DST X=0) + 11 Tiling Enable + Value Name Description + 0b Tiling Disabled (Linear Blit) + 1b Tiling Enabled (Tile-X or Tile-Y) + 10:8 Pattern Vertical Seed + Starting scan line of the 8x8 pattern corresponding to DST Y = 0. + 7:0 DWord Length + Value Name + 0Ah +1 31 Solid Pattern Select + Value Name +BR13 0 No Solid Pattern + 1 Solid Pattern + 30 Clipping Enabled + Value Name + 0b Disabled + 1b Enabled + 29 Mono Source Transparency Mode + Value Name + 0 Use Background + 1 Transparency Enabled + 28 Mono Pattern Transparency Mode + Value Name + 0 Use Background + 1 Transparency Enabled + 27:26 Reserved + Format: MBZ + 25:24 Color Depth + Value Name + 00b 8 Bit Color + 01b 16 Bit Color(565) + 10b 16 Bit Color(1555) + 11b 32 Bit Color + 23:16 Raster Operation + 15:0 Destination Pitch in DWords + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 83 + XY_FULL_MONO_PATTERN_MONO_SRC_BLT + 2's complement For Tiled surfaces (bit_11 enabled) this pitch is of 512Byte granularity for Tile-X, + 128B granularity for Tile-Y and can be upto 128Kbytes (or 32KDwords). +2 31:16 Destination Y1 Coordinate (Top) + 16 bit signed number. +BR22 15:0 Destination X1 Coordinate (Left) + 16 bit signed number. +3 31:16 Destination Y2 Coordinate (Bottom) + 16 bit signed number. +BR23 15:0 Destination X2 Coordinate (Right) + 16 bit signed number. +4 31:0 Destination Base Address + Base address of the destination surface: X=0, Y=0. When Tiling is enabled (Bit_11 enabled), this +BR09 address is limited to 4Kbytes. +5 31:0 Mono Source Address + (address corresponds to DST X1, Y1) (Note no NPO2 change here). +BR12 +6 31:0 Source Background Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR18 +7 31:0 Source Foreground Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR19 +8 31:0 Pattern Background Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR16 +9 31:0 Pattern Foreground Color + 8 bit = [7:0], 16 bit = [15:0], 32 bit = [31:0] +BR17 +10 31:0 Pattern Data 0 + (least significant DW) +BR20 +11 31:0 Pattern Data 1 + (most significant DW) +BR21 + + + + +1.10 BLT Engine Instruction Field Definitions +This section describes the BLT Engine instruction fields. These descriptions are in the format of register +descriptions. These registers are internal and are not readable. Some of these registers are state that is +saved and restored for supporting separate software threads. + + + + +84 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 1.10.1 BR00—BLT Opcode & Control + + BR00 - BLT Opcode and Control +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31 BLT Engine Busy + This bit indicates whether the BLT Engine is busy (1) or idle (0). This bit is replicated in the SETUP BLT + Opcode and Control register. + Value Name + 0 Idle [Default] + 1 Busy + 30 Setup Instruction Instruction + Default Value: 0 + The current instruction performs clipping (1). + + 29 Setup Monochrome Pattern + This bit is decoded from the Setup instruction opcode to identify whether a color (0) or monochrome (1) + pattern is used with the SCANLINE_BLT instruction. + Value Name + 0 Color [Default] + 1 Monochrome + 28:22 Instruction Target (Opcode) + Default Value: 0000000b + This is the contents of the Instruction Target field from the last BLT instruction. This field is used by the + BLT Engine state machine to identify the BLT instruction it is to perform. The opcode specifies whether + the source and pattern operands are color or monochrome. + + 21:20 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 19:17 Monochrome Source Start + Default Value: 000b + This field indicates the starting monochrome pixel bit position within a byte per scan line of the source + operand. The monochrome source is word aligned which means that at the end of the scan line all bits + should be discarded until the next word boundary. + + 16 Bit/Byte Packed + Byte packed is for the NT driver. + Value Name + 0b Bit [Default] + 1b Byte + 15 Src Tiling Enable + Value Name Project + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 85 + BR00 - BLT Opcode and Control + 0b Tiling Disabled (Linear) [Default] + 1b Tiling enabled: Tile-X or Tile-Y + 14:12 Horizontal Pattern Seed + Default Value: 0b + This field indicates the pattern pixel position which corresponds to X = 0. + + 11 Dest Tiling Enable + When set to '1', this means that Blitter is executing in Tiled mode. If '0' it means that Blitter is in Linear + mode. Blitter supports both Tile-X and Tile-Y modes. On reset, this bit will be '0'. This definition applies + to only X,Y Blits. + Value Name Project + 0b Tiling Disabled (Linear blit) [Default] + 1b Tiling enabled: Tile-X or Tile-Y + 10:8 Transparency Range Mode + These bits control whether or not the byte(s) at the destination corresponding to a given pixel will be + conditionally written, and what those conditions are. This feature can make it possible to perform + various masking functions in order to selectively write or preserve graphics data already at the + destination. + Value Name Description + xx0b [Default] No color transparency mode enabled. This causes normal operation with regard to + writing data to the destination. + 001b [Source color transparency] The Transparency Color Low: (Pixel Greater or Equal) + (source background register) and the Transparency Color High: (Pixel Less or Equal) + (source foreground register) are compared to the source pixels. The range + comparisons are done on each component (R,G,B) and then logically ANDed. If the + source pixel components are not within the range defined by the Transparency Color + registers, then the byte(s) at the destination corresponding to the current pixel are + written with the result of the bit-wise operation. + 011b [Source and Alpha color transparency] The Transparency Color Low: (Pixel Greater or + Equal) (source background register) and the Transparency Color High: (Pixel Less or + Equal) (source foreground register) are compared to the source pixels. The range + comparisons are done on each component (A,R,G,B) and then logically ANDed. If the + source pixel components are not within the range defined by the Transparency Color + registers, then the byte(s) at the destination corresponding to the current pixel are + written with the result of the bit-wise operation." + 101b [Destination and Alpha color transparency] The Transparency Color Low: (Pixel + Greater or Equal) (source background register) and the Transparency Color High: + (Pixel Less or Equal) (source foreground register) are compared to the destination + pixels. The range comparisons are done on each component (A,R,G,B) and then + logically ANDed. If the destination pixels are within the range, then the byte(s) at the + destination corresponding to the current pixel are written with the result of the bit-wise + operation. + 111b [Destination color transparency] The Transparency Color Low: (Pixel Greater or Equal) + (source background register) and the Transparency Color High: (Pixel Less or Equal) + (source foreground register) are compared to the destination pixels. The range + comparisons are done on each component (R,G,B) and then logically ANDed. If the + destination pixels are within the range, then the byte(s) at the destination + corresponding to the current pixel are written with the result of the bit-wise operation. + 7:5 Pattern Vertical Seed + Default Value: 000b + + + + +86 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + BR00 - BLT Opcode and Control + This field specifies the pattern scan line which corresponds to Y=0. + + 4 Destination Read Modify Write + Default Value: 0b + This bit is decoded from the last instruction's opcode field and Destination Transparency Mode to + identify whether a Destination read is needed. + + 3 Color Source + Default Value: 0b + This bit is decoded from the last instructions opcode field to identify whether a color (1) source is used. + + 2 Monochrome Source + Default Value: 0b + This bit is decoded from the last instructions opcode field to identify whether a monochrome (1) source + is used. + + 1 Color Pattern + Default Value: 0b + This bit is decoded from the last instructions opcode field to identify whether a color (1) pattern is used. + + 0 Monochrome Pattern + Default Value: 0b + This bit is decoded from the last instructions opcode field to identify whether a monochrome (1) pattern + is used. + + + + +1.10.2 BR01—Setup BLT Raster OP, Control, and Destination Offset + + BR01 - Setup BLT Raster OP, Control, and Destination Offset +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31 Solid Pattern Select + This bit applies only when the pattern data is monochrome. This bit determines whether or not the BLT + Engine actually performs read operations from the frame buffer in order to load the pattern data. Use of + this feature to prevent these read operations can increase BLT Engine performance, if use of the + pattern data is indeed not necessary. The BLT Engine is configured to accept either monochrome or + color pattern data via the opcode field. + Value Name Description + 0b [Default] This causes normal operation with regard to the use of the pattern data. The BLT + Engine proceeds with the process of reading the pattern data, and the pattern data is + used as the pattern operand for all bit-wise operations. + 1b The BLT Engine forgoes the process of reading the pattern data, the presumption is + made that all of the bits of the pattern data are set to 0, and the pattern operand for all + bit-wise operations is forced to the background color specified in the Color Expansion + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 87 + BR01 - Setup BLT Raster OP, Control, and Destination Offset + Background Color Register. + 30 Clipping Enabled + Value Name + 0b [Default] + 1b + 29 Monochrome Source Transparency Mode + This bit applies only when the source data is in monochrome. This bit determines whether or not the + byte(s) at the destination corresponding to the pixel to which a given bit of the source data also + corresponds will actually be written if that source data bit has the value of 0. This feature can make it + possible to use the source as a transparency mask. The BLT Engine is configured to accepted either + monochrome or color source data via the opcode field. + Value Name Description + 0b [Default] This causes normal operation with regard to the use of the source data. Wherever a bit + in the source data has the value of 0, the color specified in the background color + register is used as the source operand in the bit-wise operation for the pixel + corresponding to the source data bit, and the bytes at the destination corresponding to + that pixel are written with the result. + 1b Wherever a bit in the source data has the value of 0, the byte(s) at the destination + corresponding to the pixel to which the source data bit also corresponds are simply not + written, and the data at those byte(s) at the destination are allowed to remain + unchanged. + 28 Monochrome Pattern Transparency Mode + This bit applies only when the pattern data is monochrome. This bit determines whether or not the + byte(s) at the destination corresponding to the pixel to which a given bit of the pattern data also + corresponds will actually be written if that pattern data bit has the value of 1. This feature can make it + possible to use the pattern as a transparency mask. The BLT Engine is configured to accepted either + monochrome or color pattern data via the opcode field. + Value Name Description + 0b [Default] This causes normal operation with regard to the use of the pattern data. Wherever a bit + in the pattern data has the value of 0, the color specified in the background color + register is used as the pattern operand in the bit-wise operation for the pixel + corresponding to the pattern data bit, and the bytes at the destination corresponding to + that pixel are written with the result. + 1b Wherever a bit in the pattern data has the value of 0, the byte(s) at the destination + corresponding to the pixel to which the pattern data bit also corresponds are simply not + written, and the data at those byte(s) at the destination are allowed to remain + unchanged. + 27:26 32bpp Byte Mask + This bit applies only when the pattern data is monochrome. This bit determines whether or not the + byte(s) at the destination corresponding to the pixel to which a given bit of the pattern data also + corresponds will actually be written if that pattern data bit has the value of 1. This feature can make it + possible to use the pattern as a transparency mask. The BLT Engine is configured to accepted either + monochrome or color pattern data via the opcode field. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 25:24 Color Depth + Value Name + 00b 8 Bit Color Depth [Default] + + + + +88 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + BR01 - Setup BLT Raster OP, Control, and Destination Offset + 01b 16 Bit Color Depth + 10b 16 Bit Color Depth + 11b 32 Bit Color Depth + 23:16 Raster Operation Select + These 8 bits are used to select which one of 256 possible raster operations is to be performed by the + BLT Engine. The opcode field must indicate a monochrome source if ROP = F0. + 15:0 Destination Pitch (Offset) + For non-XY Blits, the signed 16bit field allows for specifying upto + 32Kbytes signed pitches in bytes + (same as before). For X, Y Blits with tiled-X surfaces, the pitch for Destination will be 512Byte aligned + and should be programmable upto + 128Kbytes. For X, Y Blits with tiled-Y surfaces, the pitch for + Destination will be 128Byte aligned and should be programmable upto + 128Kbytes. In this case, this + 16bit signed pitch field is used to specify upto + 32KDWords. For X, Y blits with nontiled surfaces + (linear surfaces), this 16bit field can be programmed to byte specification of upto + 32Kbytes (same as + before). These 16 bits store the signed memory address offset value by which the destination address + originally specified in the Destination Address Register is incremented or decremented as each scan + line's worth of destination data is written into the frame buffer by the BLT Engine, so that the destination + address will point to the next memory address to + which the next scan line's worth of destination data is to be written. If the intended destination of a BLT + operation is within on-screen frame buffer memory, this offset is normally set so that each subsequent + scan line's worth of destination data lines up vertically with the destination data in the scan line, above. + However, if the intended destination of a BLT operation is within off-screen memory, this offset can be + set so that each subsequent scan line's worth of destination data is stored at a location immediately + after the location where the destination data for the last scan line ended, in order to create a single + contiguous block of bytes of destination data at the destination. + + + + +1.10.3 BR05—Setup Expansion Background Color + + BR05 - Setup Expansion Background Color +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31:0 Setup Expansion Background Color Bits + These bits provide the one, two, or four bytes worth of color data that select the background color to be + used in the color expansion of monochrome pattern or source data for either the SCANLINE_BLT or + TEXT_BLT instructions. BR05 is also used as the solid pattern for the PIXEL_BLT instruction. Whether + one, two, or three bytes worth of color data is needed depends upon the color depth to which the BLT + Engine has been set. For a color depth of 32bpp, 16bpp and 8bpp, bits [31:0], [15:0] and [7:0], + respectively, are used. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 89 + 1.10.4 BR06—Setup Expansion Foreground Color + + + BR06 - Setup Expansion Foreground Color +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31:0 Setup Expansion Foreground Color Bits + These bits provide the one, two, or four bytes worth of color data that select the foreground color to be + used in the color expansion of monochrome pattern or source data for either the SCANLINE_BLT or + TEXT_BLT instructions. Whether one, two, or three bytes worth of color data is needed depends upon + the color depth to which the BLT Engine has been set. For a color depth of 32bpp, 16bpp and 8bpp, bits + [31:0], [15:0] and [7:0], respectively, are used. + + + + +1.10.5 BR07— Setup Blit Color Pattern Address + + BR07 - Setup Blit Color Pattern Address +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31:29 Reserved + Format: MBZ + 28:6 Setup Blit Color Pattern Address + These 26 bits specify the starting address of the (8X8) pixel color pattern from the SETUP_BLT + instruction. This register works identically to the Pattern Address register (BR15), but this version is + only used with the SCANLINE_BLT instruction execution (the actual programming for this, is done in + XY_SETUP_BLT command). The pattern data must be located in linear memory. The pattern data + must be located on a pattern-size boundary. The pattern is always of 8x8 pixels, and therefore, its size + is dependent upon its pixel depth. The pixel depth may be 8, 16, or 32 bits per pixel if the pattern is in + color (the pixel depth of a color pattern must match the pixel depth to which the graphics system has + been set). Monochrome patterns require 8 bytes and is supplied through the instruction. Color patterns + of 8, 16, and 32 bits per pixel color depth must start on 64-byte, 128-byte and 256-byte boundaries, + respectively. + 5:0 Reserved + Format: MBZ + + + + +90 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 1.10.6 BR09—Destination Address + + + BR09 - Destination Address +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31:0 Destination Address Bits + When tiling is enabled for XY-blits, this base address should be limited to 4KB. Otherwise for XY blits, + there is no restriction and it is same as before. These specify the starting pixel address of the destination + data. This register is also the working destination address register and changes as the BLT Engine + performs the accesses. Used as the scan line address (Destination Y Address and Destination Y1 + Address) for BLT instructions: PIXEL_BLT, SCANLINE_BLT, and TEXT_BLT. In this case the address + points to the first pixel in a scan line and is compared with the ClipRect Y1 and Y2 address registers to + determine whether the scan line should be written or not. The Destination Y1 address is the top scan + line to be written for text. Note that for non-XY blits (COLOR_BLT, SRC_COPY_BLT), this address + points to the first byte to be written. Note: Some instructions affect only one scan line (requiring only one + coordinate); other instructions affect multiple scan lines and need both coordinates. + + + + +1.10.7 BR11—BLT Source Pitch (Offset) + + BR11 - BLT Source Pitch (Offset) +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 15:0 Source Pitch (Offset) + For non-XY Blits with color source operand (SRC_COPY_BLT), the signed 16bit field allows for + specifying upto + 32Kbytes signed pitch in bytes (same as before). For X, Y Blits with tiled-X surfaces, + the pitch for Color Source will be 512Byte aligned and should be programmable upto + 128Kbytes. For + X, Y Blits with tiled-Y surfaces, the pitch for Color Source will be 128Byte aligned and should be + programmable upto + 128Kbytes. In this case, this 16bit signed pitch field is used to specify upto + + 32KDWords. For X, Y blits with nontiled color source surfaces (linear surfaces), this 16bit field can be + programmed to byte specification of upto + 32Kbytes (same as before). When the color source data is + located within the frame buffer or AGP aperture, these signed 16 bits store the memory address offset + (pitch) value by which the source address originally specified in the Source Address Register is + incremented or decremented as each scan line's worth of source data + is read from the frame buffer by the BLT Engine, so that the source address will point to the next + memory address from which the next scan line's worth of source data is to be read. Note that if the + intended source of a BLT operation is within on-screen frame buffer memory, this offset is normally set + to accommodate the fact that each subsequent scan line's worth of source data lines up vertically with + the source data in the scan line, above. However, if the intended source of a BLT operation is within off- + screen memory, this offset can be set to accommodate a situation in which the source data exists as a + single contiguous block of bytes where in each subsequent scan line's worth of source data is stored at + a location immediately after the location where the source data for the last scan line ended. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 91 + 1.10.8 BR12—Source Address + + BR12 - Source Address +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31:0 Source Address Bits + When tiling is enabled for XY-blits with Color source surfaces, this base address should be limited to + 4KB. Otherwise for XY blits, there is no restriction and it is same as before, including for monosource + and text blits. Note that for non-XY blit with Color Source (SRC_COPY_BLT), this address points to the + first byte to be read. These specify the starting pixel address of the color source data. The lower 3 bits + are used to indicate the position of the first valid byte within the first Quadword of the source data. + + + + +1.10.9 BR13—BLT Raster OP, Control, and Destination Pitch + + BR13 - BLT Raster OP, Control, and Destination Pitch +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31 Solid Pattern Select + This bit applies only when the pattern data is monochrome. This bit determines whether or not the BLT + Engine actually performs read operations from the frame buffer in order to load the pattern data. Use of + this feature to prevent these read operations can increase BLT Engine performance, if use of the + pattern data is indeed not necessary. The BLT Engine is configured to accept either monochrome or + color pattern data via the opcode field. + Value Name Description + 0 [Default] This causes normal operation with regard to the use of the pattern data. The BLT + Engine proceeds with the process of reading the pattern data, and the pattern data is + used as the pattern operand for all bit-wise operations. + 1 The BLT Engine forgoes the process of reading the pattern data, the presumption is + made that all of the bits of the pattern data are set to 0, and the pattern operand for all + bit-wise operations is forced to the background color specified in the Color Expansion + Background Color Register. + 30 Clipping Enabled + Default Value: 0 + 29 Monochrome Source Transparency Mode + This bit applies only when the source data is in monochrome. This bit determines whether or not the + byte(s) at the destination corresponding to the pixel to which a given bit of the source data also + corresponds will actually be written if that source data bit has the value of 0. This feature can make it + possible to use the source as a transparency mask. The BLT Engine is configured to accepted either + monochrome or color source data via the opcode field. + Value Name Description + 0 [Default] This causes normal operation with regard to the use of the source data. Wherever a bit + in the source data has the value of 0, the color specified in the background color + register is used as the source operand in the bit-wise operation for the pixel + + + + +92 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + BR13 - BLT Raster OP, Control, and Destination Pitch + corresponding to the source data bit, and the bytes at the destination corresponding to + that pixel are written with the result. + 1 Where a bit in the source data has the value of 0, the byte(s) at the destination + corresponding to the pixel to which the source data bit also corresponds are simply not + written, and the data at those byte(s) at the destination are allowed to remain + unchanged. + 28 Monochrome Pattern Transparency Mode + This bit applies only when the pattern data is monochrome. This bit determines whether or not the + byte(s) at the destination corresponding to the pixel to which a given bit of the pattern data also + corresponds will actually be written if that pattern data bit has the value of 1. This feature can make it + possible to use the pattern as a transparency mask. The BLT Engine is configured to accepted either + monochrome or color pattern data via the opcode in the Opcode and Control register. + Value Name Description + 0 [Default] This causes normal operation with regard to the use of the pattern data. Where a bit in + the pattern data has the value of 0, the color specified in the background color register + is used as the pattern operand in the bit-wise operation for the pixel corresponding to + the pattern data bit, and the bytes at the destination corresponding to that pixel are + written with the result. + 1 Wherever a bit in the pattern data has the value of 0, the byte(s) at the destination + corresponding to the pixel to which the pattern data bit also corresponds are simply not + written, and the data at those byte(s) at the destination are allowed to remain + unchanged. + 27:26 32bpp Byte Mask + This field is only used for 32bpp. + Value Name + 00b [Default] + 1xb Write Alpha Channel + x1b Write RGB Channel + 25:24 Color Depth + Value Name + 00b 8 Bit Color Depth [Default] + 01b 16 Bit Color Depth + 10b 24 Bit Color Depth + 11b Reserved + 23:16 Raster Operation Select + Default Value: 00000000b + These 8 bits are used to select which one of 256 possible raster operations is to be performed by the + BLT Engine. The opcode must indicate a monochrome source operand if ROP = F0. + + 15:0 Destination Pitch(Offset) + These 16 bits store the signed memory address offset value by which the destination address originally + specified in the Destination Address Register is incremented or decremented as each scan line's worth + of destination data is written into the frame buffer by the BLT Engine, so that the destination address + will point to the next memory address to which the next scan line's worth of destination data is to be + written. If the intended destination of a BLT operation is within on-screen frame buffer memory, this + offset is normally set so that each subsequent scan line's worth of destination data lines up vertically + with the destination data in the scan line, above. However, if the intended destination of a BLT + operation is within off-screen memory, this offset can be set so that each subsequent scan line's worth + of destination data is stored at a location immediately after the location where the destination data for + the last scan line ended, in order to create + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 93 + BR13 - BLT Raster OP, Control, and Destination Pitch + a single contiguous block of bytes of destination data at the destination. + + + + +1.10.10 BR14—Destination Width & Height + + BR14 - Destination Width and Height +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +BR14 contains the values for the height and width of the data to be BLT. If these values are not correct, such that the +BLT Engine is either expecting data it does not receive or receives data it did not expect, the system can hang. +DWord Bit Description +0 31:29 Reserved + 28:16 Destination Height + These 13 bits specify the height of the destination data in terms of the number of scan lines. This is a + working register. + 15:13 Reserved + 12:0 Destination Byte Width + These 13 bits specify the width of the destination data in terms of the number of bytes per scan line. + The number of pixels per scan line into which this value translates depends upon the color depth to + which the graphics system has been set. + + + + +1.10.11 BR15—Color Pattern Address + + BR15 - Color Pattern Address +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31:29 Reserved + Format: MBZ + 28:6 Color Pattern Address + There is no change to the Color Pattern address specification due to Non-Power-of-2 change. It + remains the same as before. The pattern data must be located in linear memory. These 26 bits specify + the starting address of the (8X8) pixel color pattern. The pattern data must be located on a pattern-size + boundary. The pattern is always of 8x8 pixels, and therefore, its size is dependent upon its pixel depth. + The pixel depth may be 8, 16, or 32 bits per pixel if the pattern is in color (the pixel depth of a color + pattern must match the pixel depth to which the graphics system has been set). Monochrome patterns + require 8 bytes and are applied through the instruction. Color patterns of 8, 16, and 32 bits per pixel + color depth must start on 64-byte, 128-byte and 256-byte boundaries, respectively. + 5:0 Reserved + Format: MBZ + + + + +94 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 1.10.12 BR16—Pattern Expansion Background & Solid Pattern Color + + BR16 - Pattern Expansion Background and Solid Pattern Color +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31:0 Pattern Expansion Background Color Bits + These bits provide the one, two, or four bytes worth of color data that select the background color to be + used in the color expansion of monochrome pattern data during BLT operations. Whether one, two, or + four bytes worth of color data is needed depends upon the color depth to which the BLT Engine has + been set. For a color depth of 32bpp, 16bpp and 8bpp, bits [31:0], [15:0] and [7:0], respectively, are + used. + + + + +1.10.13 BR17—Pattern Expansion Foreground Color + + BR17 - Pattern Expansion Foreground Color +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31:0 Pattern Expansion Background Color Bits + These bits provide the one, two, or four bytes worth of color data that select the foreground color to be + used in the color expansion of monochrome pattern data during BLT operations. Whether one, two, or + four bytes worth of color data is needed depends upon the color depth to which the BLT Engine has + been set. For a color depth of 32bpp, 16bpp and 8bpp, bits [31:0], [15:0] and [7:0], respectively, are + used. + + + + +1.10.14 BR18—Source Expansion Background, and Destination + Color + + BR18 - Source Expansion Background and Destination Color +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31:0 Source Expansion Background Color Bits + These bits provide the one, two, or four bytes worth of color data that select the background color to be + used in the color expansion of monochrome source data during BLT operations. This register is also + used to support destination transparency mode and Solid color fill. Whether one, two, three, or four + bytes worth of color data is needed depends upon the color depth to which the BLT Engine has been + set. For a color depth of 32bpp, 16bpp and 8bpp, bits [31:0], [15:0] and [7:0], respectively, are used. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 95 + 1.10.15 BR19—Source Expansion Foreground Color + + BR19 - Source Expansion Foreground Color +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +DWord Bit Description +0 31:0 Pattern/Source Expansion Foreground Color Bits + These bits provide the one, two, or four bytes worth of color data that select the foreground color to be + used in the color expansion of monochrome source data during BLT operations. Whether one, two, or + four bytes worth of color data is needed depends upon the color depth to which the BLT Engine has + been set. For a color depth of 32bpp, 16bpp and 8bpp, bits [31:0], [15:0] and [7:0], respectively, are + used. + + + + +96 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2. Blitter (Blt) Engine Command + Streamer +The blitter pipeline has its own command streamer and operates completely independently of the other +command streamers. This command streamer supports a separate set of registers starting at offset +20000h. + + +2.1 Registers for Blitter Engine + +2.1.1 Introduction +Each register is at the same offset from 020000h as its primary counterpart is offset from 02000h. + + +2.1.2 GAB PWR CTX STORAGE REGISTERS + +2.1.2.1 GAB_CTL_REG – GAB unit Control Register + + GAB_CTL_REG - GAB unit Control Register + + +Source: BlitterCS +Default Value: 0x000000BF +Access: R/W +Size (in bits): 32 +Address: 24000h +DefaultValue=FF0000BFh Trusted Type = 1 +DWord Bit Description +0 31:9 Reserved + 8 Continue after Page Fault + If set to 1: upon receiving a page fault when requesting an address translation, GAB will set address bit + 39 to 1 and continue. If set to 0: GAB will hang on a page fault. Default = b0. + 7:6 PPGTT BCS TLB LRA MIN + Default Value: 10b + TLB Depth Partitioning Register In PP GTT Mode. + + 5:4 GAB write request priority signal value used in GAC arbitration + Default Value: 11b + 3:2 GAB read only request priority signal value used in GAC arbitration + Default Value: 11b + 1:0 GAB read request priority signal value used in GAC arbitration + Default Value: 11b + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 97 + 2.1.3 GFX TLB In Use Virtual Address Registers. +2.1.3.1 BCSTLB_VA — BCS TLB Virtual Page Address Registers + + BCSTLB_VA - BCS TLB Virtual Page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 24800h-248FCh + +This register is directly mapped to the current Virtual Addresses in the BCS TLB. + DWord Bit Description +0 31:12 ADDRESS + + Format: GraphicsAddress[31:12] + PAGE VIRTUAL ADDRESS. + + 11:0 RESERVED + + Format: MBZ + + + + +98 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.1.3.2 BLBTLB_VA — Virtual page Address Registers + + BLBTLB_VA - BLBTLB_VA Virtual page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 24900h-249FCh + +This register is directly mapped to the current Virtual Addresses in the BLB TLB. + DWord Bit Description +0 31:12 ADDRESS + + Format: GraphicsAddress[31:12] + PAGE VIRTUAL ADDRESS + + 11:0 RESERVED + Format: MBZ + + + +2.1.3.3 CTXTLB_VA — Virtual page Address Registers + + CTXTLB_VA - CTXTLB_VA Virtual page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 24A00h-24AFCh + +This register is directly mapped to the current Virtual Addresses in the CTX TLB. + DWord Bit Description +0 31:12 ADDRESS + + Format: GraphicsAddress[31:12] + PAGE VIRTUAL ADDRESS + + 11:0 RESERVED + + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 99 + 2.1.3.4 PDTLB_VA — Virtual page Address Registers + + PDTLB_VA - PDTLB_VA Virtual page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 24B00h-24BFCh + +This register is directly mapped to the current Virtual Addresses in the PD TLB. + DWord Bit Description +0 31:12 ADDRESS + + Format: GraphicsAddress[31:12] + PAGE VIRTUAL ADDRESS + + 11:0 RESERVED + + Format: MBZ + + + +2.1.3.5 BCSTLB_VLD — Valid Bit Vector for BCS TLB + + BCSTLB_VLD - Valid Bit Vector for BCS TLB +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 24780h-24783h + +This register contains the valid bits for entries 0-31 of BCS TLB. + DWord Bit Description +0 31:4 Reserved + 3:0 Valid bits per entry + + + + +100 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.1.3.6 BLBTLB_VLD — Valid Bit Vector for BLB TLB + + BLBTLB_VLD - Valid Bit Vector for BLB TLB +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 24784h-24787h + + This register contains the valid bits for entries 0-31 of BLB TLB. + DWord Bit Description +0 31:8 Reserved + 7:0 Valid bits per entry + + + +2.1.3.7 CTXTLB_VLD — Valid Bit Vector for CTX TLB + + CTX_TLB_VLD - Valid Bit Vector for CTX TLB +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 24788h-2478Bh +This register contains the valid bits for entries 0-31 of CTX TLB. + DWord Bit Description +0 31:1 Reserved + 0 Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 101 + 2.1.3.8 PDTLB_VLD — Valid Bit Vector for PD TLB + + PDTLB_VLD - Valid Bit Vector for PD TLB +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 2478Ch-2478Fh +This register contains the valid bits for entries 0-31 of PD TLB. + DWord Bit Description +0 31:8 Reserved + 7:0 Valid bits per entry + + + + +2.1.4 GFX Pending TLB cycles information registers. +The following registers contain information about cycles that did not complete their TLB translation. +Information is organized as 64 entries, where each entry has a valid and ready bit, collapsed into +separate registers. + +2.1.4.1 BCS_TLBPEND_VLD0 - BCS Valid Bit Vector for TLBPEND registers + + BCS_TLBPEND_VLD0 - BCS Valid Bit Vector for TLBPEND registers +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 24700h-24703h +This register contains the valid bits for entries 0-31 of TLBPEND structure(Cycles pending TLB translation). + DWord Bit Description +0 31:0 Valid bits per entry + + + + +102 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.1.4.2 BCS_TLBPEND_RDY0 - BCS Ready Bit Vector for TLBPEND registers + + BCS_TLBPEND_RDY0 - BCS Ready Bit Vector for TLBPEND + Registers +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 24708h-2470Bh + + This register contains the ready bits for entries 0-31 of TLBPEND structure (Cycles pending TLB + translation). + DWord Bit Description +0 31:0 Ready bits per entry + + + +2.1.4.3 TLBPEND_SEC0 — Section 0 of TLBPEND entry + + TLBPEND_SEC0 - Section 0 of TLBPEND Entry +Register Space: MMIO: 0/2/0 + + +Source: RenderCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04400h-044FCh +This register is directly mapped to the TLBPEND Array in the Graphic Arbiter. +DWord Bit Description +0 31 vtstatus + This bit will be used in conjunction with the ready bit to determine the stage of the translation. See table + below. + 30:28 GTT bits + Bits 3:1 of the GTT entry used to translate the Virtual Address. 000 if translation is pending. + 27:0 Current address + The value of this field depends on the stage of the TLB translation for this entry: VA – bits 27:20 = 00, + bits 19:0 = Bits 31:12 of the Virtual Address of the cycle. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 103 + 2.1.4.4 BCS_TLBPEND_SEC1 — BCS Section 1 of TLBPEND entry + + BCS_TLBPEND_SEC1 - BCS Section 1 of TLBPEND entry +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 24500h-245FCh + + This register is directly mapped to the current Virtual Addresses in the MTTLB (Texture and constant cache + TLB) +DWord Bit Description +0 31 vtstatus + This bit will be used in conjunction with the ready bit to determine the stage of the translation. See table + in section 0 register. + 30:28 Reserved + 27:24 PAT entry + Location of Physical Address in Physical Address Table. + 23:22 Reserved + 21:20 Surface format + Value Name + 0xb Linear + 10b Tile X + 11b Tile Y + 19:14 Cache line offset in page + 13:10 Cacheability Control Bits + 9 ZLR bit + indicates a zero length read + 8:2 TAG + 1:0 SRC ID + 00/01=BCS; 10/11= BLB + + + + +104 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.1.5 GAB Error Reporting Register + + GAB Error Reporting Register +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 24094h + +This register is directly mapped for the Error Reporting Register + DWord Bit Description +0 31:8 Reserved + 7 HWSP GGTT fetch yields an invalid entry + 6 VTD fetch yields an invalid entry + 5 PD VTD HPA fetch yields an invalid entry + 4 PD fetch yields an invalid entry + 3 PD fetch for entry marked as invalid by BCS + 2 GTT fetch yields an invalid entry + Page Fault occurred in one of the GTT translations. + 1 CTXTLB VTD fetch yields an invalid entry + 0 CTXTLB fetch yields an invalid entry + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 105 + 2.1.6 Virtual Memory Control + +2.1.6.1 BCS_HWS_PGA — BCS Hardware Status Page Address Register + + BCS_HWS_PGA - BCS Hardware Status Page Address Register +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 04280h + + +This register is used to program the 4 KB-aligned System Memory address of the Hardware Status Page used to +report hardware status into (typically cacheable) System Memory. + Programming Notes Project +If this register is written, a workload must subsequently be dispatched to the Blitter command streamer. + DWord Bit Description +0 11:1 Reserved + Format: MBZ + +The following table defines the layout of the Hardware Status Page: + DWord Offset Description + 3:0 Reserved. Must not be used. + 4 + Head Pointer Storage: The contents of the Ring Buffer Head + Pointer register (register DWord 1) are written to this location + either as result of an MI_REPORT_HEAD instruction or as the + result of an “automatic report” (see RINGBUF registers). + 0Fh:05h + Reserved. Must not be used. + 3FFh:010h These locations can be used for general purpose via the + MI_STORE_DATA_INDEX or MI_STORE_DATA_IMM instructions. + + + + +106 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.1.6.2 BCS_PP_DCLV – PPGTT Directory Cacheline Valid Register + + BCS_PP_DCLV - BCS PPGTT Directory Cacheline Valid Register +Register Space: MMIO: 0/2/0 +Project: All +Source: BlitterCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Address: 22220h + +Default Value = 0h +This register controls update of the on-chip PPGTT Directory Cache during a context restore. Bits that are +set will trigger the load of the corresponding 16 directory entry group. This register is restored with context +(prior to restoring the on-chip directory cache itself). This register is also restored when switching to a +context whose LRCA matches the current CCID if the Force PD Restore bit is set in the context descriptor. +The context image of this register must be updated and maintained by SW; SW should not normally need to +read this register. +This register can also effectively be used to limit the size of a processes’ virtual address space. Any access +by a process that requires a PD entry in a set that is not enabled in this register will cause a fatal error, and +no fetch of the PD entry will be attempted. +DWord Bit Description +0 63:32 Reserved + Format: MBZ + 31:0 PPGTT Directory Cache Restore + Format: Enable[32] + [1..32] 16 entries + If set, the [1st..32nd] 16 entries of the directory cache are considered valid and will be + brought in on context restore. If clear, these entries are considered invalid and fetch of these + entries will not be attempted. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 107 + 2.1.7 Mode and Misc Ctrl Registers + +2.1.7.1 BCS_CXT_SIZE—BCS Context Sizes + + BCS_CXT_SIZE - BCS Context Sizes +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000400 +Access: Read/32 bit Write Only +Size (in bits): 32 +Address: 221A8h + + DWord Bit Description +0 31:13 Reserved + Project: All + Format: MBZ + 12:8 BCS Context Size + Project: All + Format: U5 + + Value Name Project + 4h [Default] + 7:5 Reserved + Project: All + Format: MBZ + + + +2.1.7.2 BCS_MI_MODE — Mode Register for Software Interface + + BCS_MI_MODE - BCS Mode Register for Software Interface +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 2209Ch-2209Fh +The MI_MODE register contains information that + controls software interface aspects of the command parser. +DWord Bit Description +0 31:16 Masks + A 1 in a bit in this field allows + the modification of the corresponding bit in Bits 15:0 + + + + +108 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + BCS_MI_MODE - BCS Mode Register for Software Interface + 15 Suspend Flush + Project: All + Mask: MMIO(0x209c)#31 + Value Name Description + 0h No Delay HW will not delay flush, this bit + will get cleared by MI_SUSPEND_FLUSH as well + 1h Delay Flush Suspend flush is active + 14:12 Reserved + Read/Write + 11 Invalidate UHPTR enable + If bit set H/W clears the valid bit of + BCS_UHPTR (4134h, bit 0) when current active head + pointer is equal to UHPTR. + 10 Reserved + + Format: MBZ + 9 Ring Idle (Read Only Status Bit) + Writes to this bit are not allowed. + Value Name + 0 Parser not Idle + 1 Parser Idle + 8 Stop Ring + Software must set this bit to force the Ring and Command Parser to Idle. Software must read a + 1 in Ring Idle bit after setting this bit to ensure that the hardware is idle. + Software must clear this bit for Ring to resume normal operation. + Value Name + 0 Normal Operation + 1 Parser is turned off + 7:2 Reserved + Read/Write + 0 Reserved + Read/Write + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 109 + 2.1.7.3 BLT_MODE – Blitter Mode Register + + BLT_MODE - Blitter Mode Register +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 2229Ch +This register contains a control bit for the new 2-level PPGTT functions. This register is not saved/restored with +context. +DWord Bit Description +0 31:16 Mask Bits + Format: Mask[15:0] + Must be set to modify corresponding bit in Bits 15:0. (All implemented bits) + + 14 Reserved + + Format: MBZ + 13:10 Reserved + Project: All + Format: MBZ + 9 Per-Process GTT Enable + Project: All + Format: Enable Per-Process GTT BS Mode Enable + + + + + Value Name Description Project + 0h PPGTT Disable When clear, the Global GTT will be used to translate memory access All + [Default] from designated commands and for commands that select the PPGTT + as their translation space. + 1h PPGTT Enable When set, the PPGTT will be used to translate memory access from All + designated commands and for commands that select the PPGTT as + their translation space. + 7:5 Reserved + + Format: MBZ + 0 Reserved + + Format: MBZ + + + + +110 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.1.7.4 BCS_INSTPM—BCS Instruction Parser Mode Register +The BCS_INSTPM register is used to control the operation of the BCS Instruction Parser. Certain classes +of instructions can be disabled (ignored) – often useful for detecting performance bottlenecks. Also, +“Synchronizing Flush” operations can be initiated – useful for ensuring the completion (vs. only parsing) of +rendering instructions. +Programming Notes: + +  All Reserved bits are implemented. + + + BCS_INSTPM - BCS Instruction Parser Mode Register +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 220C0h +Desc +DWord Bit Description +0 31:16 Mask Bits + Format: Mask[15:0] + Must be set to modify corresponding bit in Bits 15:0. (All implemented bits) + + 15:11 Reserved + Project: All + Format: MBZ + 10 Reserved + + Format: MBZ + 9 TLB Invalidate + + Format: U1 + If set, this bit allows the command stream engine to invalidate the blitter TLBs. This bit is valid + only with the Sync flush enable + Note: GFX soft resets do not invalidate TLBs, it is up to GFX driver to explicitly + invalidate TLBs post reset. + + 8:7 Reserved + Project: All + Format: MBZ + 6 Memory Sync Enable + + Format: U1 + This set, this bit allows the blitter decode engine to write out the data from the local caches to + memory.This bit is not persistent. S/W must define this bit each time a sync flush is requested + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 111 + BCS_INSTPM - BCS Instruction Parser Mode Register + + 5 Sync Flush Enable + + Format: U1 + Format: Enable Cleared by HW + + + This field is used to request a Sync Flush operation. The device will automatically clear this bit before + completing the operation. See Sync Flush (Programming Environment). + + 4:0 Reserved + Project: All + Format: MBZ + + + + +2.1.8 BCS_EXCC — BCS Execute Condition Code Register + + BCS_EXCC - BCS Execute Condition Code Register +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: R/W,RO +Size (in bits): 32 +Trusted Type: 1 +Address: 22028h + +This register contains user defined and hardware generated conditions that are used by +MI_WAIT_FOR_EVENT commands. An MI_WAIT_FOR_EVENT instruction excludes the executing ring from +arbitration if the selected event evaluates to a 1, while instruction is discarded if the condition evaluates to +a 0. Once excluded, a ring is enabled into arbitration when the selected condition evaluates to a 0. This +register also contains control for the invalidation of indirect state pointers on context restore. + DWord Bit Description +0 31:16 Mask Bits + Format: Mask[15:0] + These bits serves as a write enable for bits 15:0. + If this register is written with any of these bits clear the + corresponding bit in the field 15:0 will not be modified. + Reading these bits always returns 0s. + + 15 Reserved + Format: MBZ + 14:12 Reserved + + Format: MBZ + + + + +112 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + BCS_EXCC - BCS Execute Condition Code Register + 11:5 Reserved + Format: MBZ + 4:0 User Defined Condition Codes + + Format: U5 + The software may signal a Stream Semaphore by setting the Mask bit and Signal Bit together to + match the bit field specified in a WAIT_FOR_EVENT (Semaphore). + + + + +2.1.8.1 BRSYNC – Blitter/Render Semaphore Sync Register + + BRSYNC - Blitter/Render Semaphore Sync Register +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 22040h + +This register is written by CS, read by BCS. + DWord Bit Description +0 31:0 Semaphore Data + Semaphore data for synchronization between + blitter engine and render engine. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 113 + 2.1.8.2 BVSYNC – Blitter/Video Semaphore Sync Register + + BVSYNC - Blitter/Video Semaphore Sync Register +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 22044h +This register is written by VCS, read by BCS. + DWord Bit Description +0 31:0 Semaphore Data + Semaphore data for synchronization between blitter engine and video codec engine. + + + +2.1.8.3 GAB_MODE — Mode Register for GAB + + GAB_MODE - Mode Register for GAB +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 220A0h-220A3h +The GAB_MODE register + contains information that controls configurations in the GAB. + DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this + field allows the modification of the + corresponding bit in Bits 15:0. + + 15:0 Reserved + Read/Write + + + + +114 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.1.9 BCS_RINGBUF—Ring Buffer Registers + + RING_BUFFER_TAIL - Ring Buffer Tail +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02030h +Name: RCS Ring Buffer Tail +ShortName: RCS_RING_BUFFER_TAIL +Address: 12030h +Name: VCS Ring Buffer Tail +ShortName: VCS_RING_BUFFER_TAIL +Address: 22030h +Name: BCS Ring Buffer Tail +ShortName: BCS_RING_BUFFER_TAIL +These registers are used to define and operate the “ring buffer” mechanism which can be used to pass instructions +to the command interface. The buffer itself is located in a linear memory region. The ring buffer is defined by a 4 +Dword register set that includes starting address, length, head offset, tail offset, and control information. + Refer to the Programming Interface chapter for a detailed description of the parameters specified in this ring buffer +register set, restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be +used to pass instructions. + Ring Buffer Tail Offsets must be properly programmed before ring is enabled. A Ring Buffer can be enabled when +empty. +DWord Bit Description +0 31:21 Reserved + Format: MBZ + 20:3 Tail Offset + Format: GraphicsAddress[20:3] + This field is written by software to specify where the valid instructions placed in the ring buffer end. The + value written points to the QWord past the last valid QWord of instructions. In other words, it can be + defined as the next QWord that software will write instructions into. + Software must write subsequent instructions to QWords following the Tail Offset, possibly wrapping + around to the top of the buffer (i.e., software can’t skip around within the buffer). + Note that all DWords prior to the location indicated by the Tail Offset must contain valid instruction + data – which may require instruction padding by software. See Head Offset for more information. + + 2:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 115 + RING_BUFFER_HEAD - Ring Buffer Head +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02034h +Name: RCS Ring Buffer Head +ShortName: RCS_RING_BUFFER_HEAD +Address: 12034h +Name: VCS Ring Buffer Head +ShortName: VCS_RING_BUFFER_HEAD +Address: 22034h +Name: BCS Ring Buffer Head +ShortName: BCS_RING_BUFFER_HEAD +This register is used to define and operate the ring buffer mechanism which can be used to pass instructions to the +command interface. The buffer itself is located in a physical memory region. The ring buffer is defined by a 4 Dword +register set that includes starting address, length, head offset, tail offset, and control information. Refer to the +Programming Interface chapter for a detailed description of the parameters specified in this ring buffer register set, +restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be used to pass +instructions. +Ring Buffer Head Offsets must be properly programmed before ring is enabled. A Ring Buffer can +be enabled when empty. +DWord Bit Description +0 31:21 Wrap Count + Format: U11 count of ring buffer wraps + + + This field is incremented by 1 whenever the Head Offset wraps from the end of the buffer back to the + start (i.e., whenever it wraps back to 0). Appending this field to the Head Offset field effectively + creates a virtual 4GB Head “Pointer” which can be used as a tag associated with instructions placed in + a ring buffer. The Wrap Count itself will wrap to 0 upon overflow. + + 20:2 Head Offset + Format: GraphicsAddress[20:2] DWord Offset + + + This field indicates the offset of the next instruction DWord to be parsed. Software will initialize this field + to select the first DWord to be parsed once the RB is enabled. (Writing the Head Offset while the RB is + enabled is UNDEFINED). Subsequently, the device will increment this offset as it executes instructions + – until it reaches the QWord specified by the Tail Offset. At this point the ring buffer is considered + “empty”. + Programming Notes + A RB can be enabled empty or containing some number of valid instructions. + 1 Reserved + Format: MBZ + + + + +116 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + RING_BUFFER_HEAD - Ring Buffer Head + 0 Wait for Condition Indicator + Source: RenderCS + This is a read only value used to indicate whether or not the command streamer is currently waiting for + a conditional code to be cleared from 0x2028 + + 0 Reserved + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + Format: MBZ + + + + + RING_BUFFER_START - Ring Buffer Start +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02038h +Name: RCS Ring Buffer Start +ShortName: RCS_RING_BUFFER_START +Address: 12038h +Name: VCS Ring Buffer Start +ShortName: VCS_RING_BUFFER_START +Address: 22038h +Name: BCS Ring Buffer Start +ShortName: BCS_RING_BUFFER_START +These registers are used to define and operate the “ring buffer” mechanism which can be used to pass instructions +to the command interface. The buffer itself is located in a physical memory region. The ring buffer is defined by a 4 +Dword register set that includes starting address, length, head offset, tail offset, and control information. Refer to the +Programming Interface chapter for a detailed description of the parameters specified in this ring buffer register set, +restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be used to pass +instructions. + DWord Bit Description +0 31:12 Starting Address + Format: GraphicsAddress[31:12]RingBuffer + This field specifies Bits 31:12 of the 4KB-aligned starting Graphics Address of the ring buffer. + Address bits 31 down to 29 must be zero. + All ring buffer pages must map to Main Memory (uncached) pages. Ring Buffer addresses are + always translated through the global GTT. + + 11:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 117 + RING_BUFFER_CTL - Ring Buffer Control +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 0203Ch +Name: RCS Ring Buffer Control +ShortName: RCS_RING_BUFFER_CTL +Address: 1203Ch +Name: VCS Ring Buffer Control +ShortName: VCS_RING_BUFFER_CTL +Address: 2203Ch +Name: BCS Ring Buffer Control +ShortName: BCS_RING_BUFFER_CTL +These registers are used to define and operate the ring buffer mechanism which can be used to pass instructions to +the command interface. The buffer itself is located in a physical memory region. The ring buffer is defined by a 4 +Dword register set that includes starting address, length, head offset, tail offset, and control information. Refer to the +Programming Interface chapter for a detailed description of the parameters specified in this ring buffer register set, +restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be used to pass +instructions. +Ring Buffer Head and Tail Offsets must be properly programmed before it is enabled. A Ring +Buffer can be enabled when empty. +DWord Bit Description +0 31:21 Reserved + Format: MBZ + 20:12 Buffer Length + Format: U9-1 in 4 KB pages – 1 + + + This field is written by SW to specify the length of the ring buffer in 4 KB Pages.Range = [0 = 1 page = + 4 KB, 1FFh = 512 pages = 2 MB] + Value Name Description + 0 1 page = 4 KB + 1FFh 512 pages = 2 MB + 11 RBWait + Indicates that this ring has executed a WAIT_FOR_EVENT instruction and is currently waiting. + Software can write a “1” to clear this bit, write of “0” has no effect. When the RB is waiting for an event + and this bit is cleared, the wait will be terminated and the RB will be returned to arbitration. + 10 Semaphore Wait + Description Project + Indicates that this ring has executed a MI_SEMAPHORE_MBOX instruction with register + compare and is currently waiting. + 9 Reserved + Format: MBZ + 8 Reserved + Source: RenderCS, BlitterCS + + + + +118 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + RING_BUFFER_CTL - Ring Buffer Control + Format: MBZ + 8 Disable Register Accesses + Source: VideoCS, VideoCS2, VideoEnhancementCS + + Value Name Description + 0 R/W Ring is allowed to access (read or write) MMIO space. + 1 Read Only Ring is not allowed to write MMIO space. Ring is allowed to read registers. + 7:3 Reserved + Format: MBZ + 2:1 Automatic Report Head Pointer + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + + Description Project + This field is written by software to control the automatic “reporting” (write) of this ring buffer’s + “Head Pointer” register (register DWord 1) to the corresponding location within the Hardware + Status Page. Automatic reporting can either be disabled or enabled at 4KB, 64KB or 128KB + boundaries within the ring buffer. + The head pointer will be reported to the head pointer location in the Per-Process Hardware + Status Page when it passes each 4KB page boundary. When the above-mentioned bit is set, + reporting will behave just as on the prior devices (as documented above), and option 2 is not + legal. + + Value Name Description + 0 MI_AUTOREPORT_OFF Automatic reporting disabled + 1 MI_AUTOREPORT_64KB Report every 16 pages (64KB) + 2 MI_AUTOREPORT_4KB Report every page (4KB)This mode must not be enabled in Ring + Buffer mode of scheduling to minimize the auto reports. + 3 MI_AUTOREPORT_128KB Report every 32 pages (128KB) + 2:1 Reserved + + Source: RenderCS + Format: MBZ + 0 Ring Buffer Enable + Format: Enable + This field is used to enable or disable this ring buffer. It can be enabled or disabled regardless of + whether there are valid instructions pending. If disabled and the ring head equals ring tail, all state + currently loaded in hardware is considered invalid. + Programming Notes Project + SW should follow the below programming notes while enabling render engine's ring buffer for + the first time, this would be coming out of boot, standby, hibernate or reset. +  + SW should set the Force Wakeup bit to prevent GT from entering C6. +  + SW should dispatch workload (dummy) to initialize render engine with default state such that + any context switches that occur subsequently (Power Save) will save and restore coherent + device state. Indirect pointers used in 3D states should point to valid graphics surface + existing in memory. PP_DCLV followed by PP_DIR_BASE register should be programmed + as part of initialization workload if PPGTT is enabled in GFX_MODE register. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 119 + RING_BUFFER_CTL - Ring Buffer Control +  + Once the render engine is programmed with valid state and the configuration, Force Wakeup + bit should be reset to enable C6 entry. + + + + +120 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.1.9.1 BCS_UHPTR — BCS Pending Head Pointer Register + + UHPTR - Pending Head Pointer Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02134h +Name: RCS Pending Head Pointer Register +ShortName: RCS_UHPTR +Address: 12134h +Name: VCS Pending Head Pointer Register +ShortName: VCS_UHPTR +Address: 22134h +Name: BCS Pending Head Pointer Register +ShortName: BCS_UHPTR + Programming Notes +Once SW uses UHPTR to preempt the existing workload, should explicitly program MI_SET_CONTEXT to save the +preempted context status before submitting the new workload. In case SW doesn’t want to save the state of the +preempted context, it should at the minimum program RS_PREEMPT_STATUS to 0x0 so that the register status +doesn’t interfere with the new workloads. + DWord Bit Description +0 31:3 Head Pointer Address + Format: GraphicsAddress[31:3] + This register represents the GFX address offset where execution should continue in the ring buffer + following execution of an MI_ARB_CHECK command. + + 2:1 Reserved + Format: MBZ + 0 Head Pointer Valid + This bit is set by the software to request a pre-emption. + It is reset by hardware when an MI_ARB_CHECK command is parsed by the command streamer. + The hardware uses the head pointer programmed in this register at the time the reset is generated. + Value Name Description + 0 InValid No valid updated head pointer register, resume execution at the current location in the + ring buffer + 1 Valid Indicates that there is an updated head pointer programmed in this register + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 121 + 2.1.9.2 BCS_CTR_THRSH – BCS Watchdog Counter Threshold + + BCS_CTR_THRSH - BCS Watchdog Counter Threshold +Register Space: MMIO: 0/2/0 +Project: All +Source: BlitterCS +Default Value: 0x00150000 +Access: R/W +Size (in bits): 32 +Address: 2217Ch +DWord Bit Description +0 31:0 Counter logic Threshold + Default Value: 00150000h + Format: U32 + This field specifies the threshold that the hardware checks against for the value of the blitter clock + counter before generating an interrupt. The counter in hardware generates an interrupt when the + threshold is reached, rolls over and starts counting again. The interrupt generated is the "Media Hang + Notify" interrupt since this watchdog timer is intended primarily to remedy VLD hangs on the main + pipeline. + + + + +2.1.10 Interrupt Control Registers +The Interrupt Control Registers described below all share the same bit definition. The bit definition is as +follows: + +Bit Definition for Interrupt Control Registers + Bit Description +31:30 + Reserved. MBZ: These bits may be assigned to interrupts on future products/steppings. + 29 + Page Fault: + This bit is set whenever there is a pending page or directory fault in blitter command + streamer. +28:27 + Reserved. MBZ + + 26 + MI_FLUSH_DW Notify Interrupt: The Pipe Control packet (Fences) specified in 3D pipeline + document may optionally generate an Interrupt. The Store QW associated with a fence is + completed ahead of the interrupt. + 25 + Blitter Command Parser Master Error: When this status bit is set, it indicates that the hardware has + detected an error. It is set by the device upon an error condition and cleared by a CPU write of a one to + the appropriate bit contained in the Error ID register followed by a write of a one to this bit in the IIR. + Further information on the source of the error comes from the “Error Status Register” which along + with the “Error Mask Register” determine which error conditions will cause the error status bit to be + set and the interrupt to occur. + + + + +122 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + Bit Description + Page Table Error: Indicates a page table error. + Instruction Parser Error: The Blitter Instruction Parser encounters an error while parsing an + instruction. + + 24 Sync Status: This bit is set when the Instruction Parser completes a flush with the sync enable bit active in the + INSTPM register. The event will happen after all the blitter engines are flushed. The HW Status DWord write + resulting from this event will cause the CPU’s view of graphics memory to be coherent as well (flush and + invalidate the blitter cache). It is the driver’s responsibility to clear this bit before the next sync flush with HWSP + write enabled. + 23 + Reserved. MBZ + + 22 Blitter Command Parser User Interrupt: This status bit is set when an MI_USER_INTERRUPT instruction is + executed on the Render Command Parser. Note that instruction execution is not halted and proceeds normally. + A mechanism such as an MI_STORE_DATA instruction is required to associate a particular meaning to a user + interrupt. + 21:0 + Reserved. MBZ + + + +2.1.10.1 BCS_HWSTAM - BCS Hardware Status Mask Register + + BCS_HWSTAM - BCS Hardware Status Mask Register +Register Space: MMIO: 0/2/0 +Project: All +Source: BlitterCS +Default Value: 0xFFFFFFFF +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 22098h +Access: RO for Reserved Control bits +The HWSTAM register has the same format as the Interrupt Control Registers. The bits in this register are “mask” +bits that prevent the corresponding bits in the Interrupt Status Register from generating a “Hardware Status Write” +(PCI write cycle). Any unmasked interrupt bit (HWSTAM bit set to 0) will allow the Interrupt Status Register to be +written to the ISR location (within the memory page specified by the Hardware Status Page Address Register) when +that Interrupt Status Register bit changes state. + Programming Notes +To write the interrupt to the HWSP, the corresponding IMR bit must also be clear (enabled). At most 1 bit can be +unmasked at any given time. + DWord Bit Description +0 31:0 Hardware Status Mask Register + Default Value: FFFFFFFFh + Project: All + Format: Array of Masks + refer to Table 5-1 in Interrupt Control Register section for bit definitions + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 123 + 2.1.10.2 IMR—BCS Interrupt Mask Register + + BCS_IMR - BCS Interrupt Mask Register +Register Space: MMIO: 0/2/0 +Project: All +Source: BlitterCS +Default Value: 0xFFFFFFFF +Access: R/W +Size (in bits): 32 +Address: 220A8h +The IMR register is used by software to control which Interrupt Status Register bits are “masked” or “unmasked”. +“Unmasked” bits will be reported in the IIR, possibly triggering a CPU interrupt, and will persist in the IIR until cleared +by software. “Masked” bits will not be reported in the IIR and therefore cannot generate CPU interrupts. + DWord Bit Description +0 31:0 Interrupt Mask Bits + Project: All + Format: Array of interrupt mask bits Refer to Table 5-1 in Interrupt Control Register section for bit + definitions + + + This field contains a bit mask which selects which interrupt bits (from the ISR) are reported in the + IIR. + Value Name Description Project + FFFF FFFFh [Default] + 0h Not Masked Will be reported in the IIR All + 1h Masked Will not be reported in the IIR All + + + +2.1.10.3 Hardware-Detected Error Bit Definitions (for EIR, EMR, ESR) +This section defines the Hardware-Detected Error bit definitions and ordering that is common to the EIR, +EMR and ESR registers. The EMR selects which error conditions (bits) in the ESR are reported in the +EIR. Any bit set in the EIR will cause the Master Error bit in the ISR to be set. EIR bits will remain set until +the appropriate bit(s) in the EIR is cleared by writing the appropriate EIR bits with ‘1’ (except for the +unrecoverable bits described below). +The following table describes the Hardware-Detected Error bits: + + BCS Hardware-Detected Error Bit Definitions + +Source: BlitterCS +Default Value: 0x00000000 +DWord Bit Description +0 15:3 Reserved + Format: MBZ + 2 Reserved + + Format: MBZ + + + + +124 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + BCS Hardware-Detected Error Bit Definitions + 1 Reserved + Format: MBZ + 0 Instruction Error + This bit is set when the Renderer Instruction Parser detects an error while parsing an instruction. + Instruction errors include: + + +  + Client ID value (Bits 31:29 of the Header) is not supported (only MI, 2D and 3D are supported). +  + Defeatured MI Instruction Opcodes: + + Value Name Description + 1 Instruction Error detected + + Programming Notes + This error indications cannot be cleared except by reset (i.e., it is a fatal error). + + + + +2.1.10.3.1 EIR — BCS Error Identity Register + + BCS_EIR - BCS Error Identity Register +Register Space: MMIO: 0/2/0 +Project: All +Source: BlitterCS +Default Value: 0x00000000 +Access: R/WC +Size (in bits): 32 +Address: 220B0h +The EIR register contains the persistent values of Hardware-Detected Error Condition bits. Any bit set in this register +will cause the Master Error bit in the ISR to be set. The EIR register is also used by software to clear detected errors +(by writing a ‘1’ to the appropriate bit(s) except for the unrecoverable bits described).). +DWord Bit Description +0 31:16 Reserved + Project: All + Format: MBZ + 15:0 Error Identity Bits + Project: All + Format: Array of Error condition bits See Table 1 5. Hardware-Detected Error Bits + + + This register contains the persistent values of ESR error status bits that are unmasked via the EMR + register. The logical OR of all (defined) bits in this register is reported in the Master Error bit of the + Interrupt Status Register. In order to clear an error condition, software must first clear the error by + writing a ‘1’ to the appropriate bit(s) in this field. If required, software should then proceed to clear the + Master Error bit of the IIR. + Value Name Description Project + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 125 + BCS_EIR - BCS Error Identity Register + 0h [Default] + 1h Error occurred Error occurred All + + Programming Notes + Writing a ‘1’ to a set bit will cause that error condition to be cleared. However, the Instruction Error bit + (Bit 0) cannot be cleared except by reset (i.e., it is a fatal error). + + + +2.1.10.3.2 EMR—BCS Error Mask Register + + BCS_EMR - BCS Error Mask Register +Register Space: MMIO: 0/2/0 +Project: All +Source: BlitterCS +Default Value: 0x0000FFFF +Access: R/W +Size (in bits): 32 +Address: 220B4h +The EMR register is used by software to control which Error Status Register bits are “masked” or “unmasked”. +“Unmasked” bits will be reported in the EIR, thus setting the Master Error ISR bit and possibly triggering a CPU +interrupt, and will persist in the EIR until cleared by software. “Masked” bits will not be reported in the EIR and +therefore cannot generate Master Error conditions or CPU interrupts. + DWord Bit Description +0 31:16 Reserved + Project: All + Format: MBZ + 15:0 Error Mask Bits + Project: All + Format: Array of error condition mask bits See Table 1 5. Hardware-Detected Error Bits + + + This register contains a bit mask that selects which error condition bits (from the ESR) are + reported in the EIR. + Value Name Description Project + FFFF FFFFh [Default] + 0h Not Masked Will be reported in the EIR All + 1h Masked Will not be reported in the EIR All + + + + +126 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.1.10.3.3 ESR—Error Status Register + + BCS_ESR - BCS Error Status Register +Register Space: MMIO: 0/2/0 +Project: All +Source: BlitterCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 220B8h +The ESR register contains the current values of all Hardware-Detected Error condition bits (these are all by definition +“persistent”). The EMR register selects which of these error conditions are reported in the persistent EIR (i.e., set bits +must be cleared by software) and thereby causing a Master Error interrupt condition to be reported in the ISR. + DWord Bit Description +0 31:16 Reserved + Project: All + Format: MBZ + 15:0 Error Status Bits + Project: All + Format: Array of error condition bits See Table 1 5. Hardware-Detected Error Bits + + + This register contains the non-persistent values of all hardware-detected error condition bits. + Value Name Description Project + 0h [Default] + 1h Error Condition Detected Error Condition detected All + + + + +2.1.11 Logical Context Support + +2.1.11.1 BB_ADDR — Batch Buffer Head Pointer Register + + BB_ADDR - Batch Buffer Head Pointer Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 02140h +Name: RCS Batch Buffer Head Pointer Register +ShortName: RCS_BB_ADDR +Address: 12140h +Name: VCS Batch Buffer Head Pointer Register +ShortName: VCS_BB_ADDR + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 127 + BB_ADDR - Batch Buffer Head Pointer Register + +Address: 1A140h +Name: VECS Batch Buffer Head Pointer Register +ShortName: VECS_BB_ADDR +Address: 22140h +Name: BCS Batch Buffer Head Pointer Register +ShortName: BCS_BB_ADDR +This register contains the current DWord Graphics Memory Address of the last-initiated batch buffer. + Programming Notes +Programming Restriction: This register should NEVER be programmed by driver. This is for HW internal use +only. +DWord Bit Description +0 31:3 Batch Buffer Head Pointer + + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + Format: GraphicsAddress[31:3] + This field specifies the DWord-aligned Graphics Memory Address where the last initiated Batch Buffer is + currently fetching commands. If no batch buffer is currently active, the Valid bit will be 0 and this field will + be meaningless. + + 31:2 Batch Buffer Head Pointer + + Source: RenderCS + Format: GraphicsAddress[31:2] + This field specifies the DWord-aligned Graphics Memory Address where the last initiated Batch Buffer is + currently fetching commands. If no batch buffer is currently active, the Valid bit will be 0 and this field will + be meaningless. + + 2 Reserved + + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + Format: MBZ + 1 Reserved + Format: MBZ + 0 Valid + Format: U1 + + Value Name Description + 0h Invalid [Default] Batch buffer Invalid + 1h Valid Batch buffer Valid + + + + +128 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.1.11.2 BCS_SYNC_FLIP_STATUS – Wait for event and Display flip flags + Register + + BCS_SYNC_FLIP_STATUS - BCS Wait for event and Display flip + flags Register +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 222D0h + + +This register is the saved value of what wait for events are still valid. This register is part of context save and restore +for RC6 feature. +DWord Bit Description +0 31 Reserved + Project: All + Format: MBZ + 30 Display Plane A Asyncronous Display Flip Pending + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane A “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 29 Display Plane A Syncronous Flip Display Pending + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane A “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 28 Display Sprite A Syncronous Flip Display Pending + Project: All + Format: Enable + This field enables a wait for the duration of a Display Sprite A “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition in the + Device Programming Interface chapter of MI Functions. + + 27 Reserved + Project: All + Format: MBZ + 26 Display Plane B Asyncronous Display Flip Pending + Project: All + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 129 + BCS_SYNC_FLIP_STATUS - BCS Wait for event and Display flip + flags Register + Format: Enable + This field enables a wait for the duration of a Display Plane B “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 25 Display Plane B Syncronous Flip Display Pending + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane B “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 24 Display Sprite B Syncronous Flip Display Pending + Project: All + Format: Enable + This field enables a wait for the duration of a Display Sprite B “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition in the + Device Programming Interface chapter of MI Functions. + + 23 Reserved + Project: All + Format: MBZ + 22 Display Plane A Asyncronous Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane A “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 21 Display Plane A Syncronous Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane A “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 20 Display Sprite A Syncronous Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Sprite A “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition in the + Device Programming Interface chapter of MI Functions. + + + + +130 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + BCS_SYNC_FLIP_STATUS - BCS Wait for event and Display flip + flags Register + + 19:15 Reserved + Project: All + Format: MBZ + 14 Display Plane B Asyncronous Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane B “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 13 Display Plane B Syncronous Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane B “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 12 Display Sprite B Syncronous Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Sprite B “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition in the + Device Programming Interface chapter of MI Functions. + + 11 Display Plane C Asynchronous Display Flip Pending + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane C “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 10 Display Plane C Synchronous Display Flip Pending + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane C “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 9 Display Sprite C Syncronous Flip Display Pending + Project: All + Format: Enable + This field enables a wait for the duration of a Display Sprite C “Flip Pending” condition. If a flip request + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 131 + BCS_SYNC_FLIP_STATUS - BCS Wait for event and Display flip + flags Register + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition in the + Device Programming Interface chapter of MI Functions. + + 8 Display Plane C Asyncronous Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane C “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 7 Display Plane C Syncronous Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane C “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition (in the + Device Programming Interface chapter of MI Functions. + + 6 Display Sprite C Syncronous Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Sprite C “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). See Display Flip Pending Condition in the + Device Programming Interface chapter of MI Functions.. + + 5 Reserved + Project: All + Format: MBZ + 4:0 Condition Code Wait Select + Project: All + This field enables a wait for the duration that the corresponding condition code is active. These enable + select one of 15 condition codes in the EXCC register, that cause the parser to wait until that condition- + code in the EXCC is cleared. + Value Name Description Project + 0h Not Enabled Condition Code Wait not enabled All + 1h-5h Enabled Condition Code select enabled; selects one of 5 codes, 0 – 4 All + 6h-15h Reserved All + + Programming Notes + Note that not all condition codes are implemented. The parser operation is UNDEFINED if an + unimplemented condition code is selected by this field. The description of the EXCC register (Memory + Interface Registers) lists the codes that are implemented. + + + + +132 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.1.12 Software Control Bit Definitions +Registers in the range 22XX are not protected from the load register immediate instruction if the +command is executed in the non-secure batch buffer. + +2.1.12.1 BCS_TILE—Software Tile Register + + BCS_SWCTRL +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 22200h +DWord Bit Description +0 31:16 Masks + + Format: U16 + A “1” in a bit in this field allows the modification of the corresponding bit in bits 15:0. + + 15:2 Reserved + + Format: MBZ + 1 Tile Y Destination + + Format: U1 + Programming this bit makes the HW treat all destination surfaces as Tile Y. This bit over-rides the + setting of the destination format in the packet provided to the blitter command streamer. SW is required + to flush the HW before changing the polarity of this bit. This bit is part of the context save/restore. + + 0 Tile Y Source + + Format: U1 + Programming this bit makes the HW treat all source surfaces as Tile Y. This bit over-rides the setting of + the source format in the packet provided to the blitter command streamer. SW is required to flush the + HW before changing the polarity of this bit. This bit is part of the context save/restore. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 133 + 2.1.12.2 TIMESTAMP — BCS Reported Timestamp Count + + BCS_TIMESTAMP - BCS Reported Timestamp Count +Register Space: MMIO: 0/2/0 +Project: All +Source: BlitterCS +Default Value: 0x00000000, 0x00000000 +Access: RO. This register is not set by the context restore. +Size (in bits): 64 +Address: 22358h +This register provides an elapsed real-time value that can be used as a timestamp.This register is not reset by a +graphics reset. It will maintain its value unless a full chipset reset is performed. + Note: This timestamp register reflects the value of the PCU TSC. The PCU TSC counts 10ns increments; this +timestamp reflects bits 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5 hours). + DWord Bit Description +0 63:36 Reserved + Project: All + Format: MBZ + 35:0 Timestamp Value + Project: All + Format: U36 + + This register toggles every 80 ns. The upper 28 bits are zero. + + + + +2.2 Memory Interface Commands for Blitter Engine + +2.2.1 Introduction +This chapter describes the formats of the “Memory Interface” commands, including brief descriptions of +their use. The functions performed by these commands are discussed fully in the Memory Interface +Functions Device Programming Environment chapter. +This chapter describes MI Commands for the blitter graphics processing engine. The term “for Blitter +Engine” in the title has been added to differentiate this chapter from a similar one describing the MI +commands for the Media Decode Engine and the Rendering Engine. +The commands detailed in this chapter are used across products within the subsystem. However, slight +changes may be present in some commands (i.e., for features added or removed), or some commands +may be removed entirely. Refer to the Preface chapter for product specific summary. + + + + +134 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.2.2 MI_ARB_CHECK +The instruction format is: + + MI_ARB_CHECK + +Source: BlitterCS +Length Bias: 1 +The MI_ARB_CHECK is used to check for a change in arbitration. If executed as part of a Ring Buffer the command +checks the UHPTR valid bit and if set the head of the ring will jump to the value of the head pointer programmed in +the UHPTR. + Programming Notes +This instruction cannot be placed in a batch buffer. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_INSTRUCTION + Format: OpCode + 28:23 MI Command Opcode + Default Value: 05h MI_ARB_CHECK + Format: OpCode + 22:0 Reserved + Format: MBZ + + + + +2.2.3 I_BATCH_BUFFER_END + + MI_BATCH_BUFFER_END + +Source: BlitterCS +Length Bias: 1 +The MI_BATCH_BUFFER_END command is used to terminate the execution of commands stored in a batch buffer +initiated using a MI_BATCH_BUFFER_START command. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 0Ah MI_ BATCH_BUFFER_END + 22:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 135 + 2.2.4 MI_BATCH_BUFFER_START + + MI_BATCH_BUFFER_START + +Source: BlitterCS +Length Bias: 2 +The MI_BATCH_BUFFER_START command is used to initiate the execution of commands stored in a batch buffer. +For restrictions on the location of batch buffers, see Batch Buffers in the Device Programming Interface chapter of MI +Functions.The batch buffer can be specified as secure or non-secure, determining the operations considered valid +when initiated from within the buffer and any attached (chained) batch buffers. See Batch Buffer Protection in the +Device Programming Interface chapter of MI Functions. + Programming Notes +  Batch buffers referenced with physical addresses must not extend beyond the end of the starting physical page + (can’t span physical pages). However, a batch buffer initiated using a physical address can chain to another + buffer in another physical page. +  A batch buffer initiated with this command must end either with a MI_BATCH_BUFFER_END command or by + chaining to another batch buffer with an MI_BATCH_BUFFER_START command. + + +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 31h MI_BATCH_BUFFER_START + Format: OpCode + 22 Reserved + + Format: MBZ + 21:9 Reserved + Project: All + Format: MBZ + 8 Address Space Indicator + + Format: MI_BufferSecurityType + Certain operations (e.g., MI_STORE_DATA_IMM commands to privileged memory) are prohibited + within non-secure buffers. See Batch Buffer Protection in the Device Programming Interface chapter of + MI Functions. The command streamer will not allow a batch buffer in PPGTT to call a batch buffer in + GGTT space by retaining the PPGTT value. It is illegal for the driver to program the value of this field to + a different value than the current batch buffer executing this command. + Value Name Description Project + 0h GGTT This batch buffer is secure and will be accessed via the GGTT. All + + Programming Notes + This field must be ‘0’ unless the Per-Process GTT Enable is ‘1’ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Format: =n + Total - Bias + + + + +136 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + MI_BATCH_BUFFER_START +1 31:2 Batch Buffer Start Address + Project: All + Format: GraphicsAddress[31:2]BatchBuffer + This field specifies Bits 31:2 of the starting address of the batch buffer. + + 1:0 Reserved + Project: All + Format: MBZ + + + + +2.2.5 MI_FLUSH_DW + + MI_FLUSH_DW + +Source: BlitterCS +Length Bias: 2 + +The MI_FLUSH_DW command is used to perform an internal “flush” operation. The parser pauses on an +internal flush until all drawing engines have completed any pending operations. In addition, this command +can also be used to: Flush any dirty data to memory. Invalidate the TLB cache inside the hardware +Usage note: After this command is completed with a Store DWord enabled, CPU access to graphics +memory will be coherent (assuming the Render Cache flush is not inhibited). +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 26h MI_FLUSH_DW + 22 Reserved + Project: All + Format: U1 + 21 Store Data Index + + Format: U1 + This field is valid only if the post-sync operation is not 0. If this bit is set, the store data + address is actually an index into the hardware status page. If this bit is set, this command will + index into the per-process hardware status page if executed from within a non-secure batch + buffer and if the Per-Process Virtual Address Space is set. Else the Global HW status page is + used. + + + 20:19 Reserved + Project: All + Format: MBZ + 18 TLB Invalidate + + Format: U1 + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 137 + MI_FLUSH_DW + + Description Project + If ENABLED, all TLBs will be invalidated once the flush operation is complete. This bit is only + valid when the Post-Sync Operation field is a value of 1h or 3h. + If GFX_MODE (0x229c) bit 13, this command will cause a config write to MMIO register space + with the address 0x4f100. + 17 Synchronize GFDT surface + + Format: U1 + If enabled, at the end of the current flush the last level cache is cleared of all the cachelines which have + been marked with the special GFDT flags. Store DW must be enabled + + 16 Reserved + Project: All + Format: MBZ + 15:14 Post-Sync Operation + + BitFieldDesc + Value Name Description + 0h No write occurs as a result of this instruction. This can be used to implement a + “trap” operation, etc. + 1h Write the QWord containing Immediate Data Low, High DWs to the Destination + Address + 2h Reserved + 3h Write the TIMESTAMP register to the Destination Address with a granularity of + 80ns. + The upper 28 bits of the TIMESTAMP register are tied to ‘0’. + + Programming Notes + If executed in a non-secure batch buffer, the address given is in a PPGTT address space. If in a + secure ring or batch, the address given is in GGTT space. + + 13:9 Reserved + Project: All + Format: MBZ + 8 Notify Enable + + Format: U1 + If ENABLED, a Sync Completion Interrupt will be generated (if enabled by the MI Interrupt Control + registers) once the sync operation is complete. See Interrupt Control Registers in Memory Interface + Registers for details. + + 7:6 Reserved + Project: All + Format: MBZ + 5:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + +138 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + MI_FLUSH_DW + + + Value Name Project + 2h Excludes DWord (0,1) = 1 for DWord, 2 for QWord [Default] +1 31:3 Address + + Format: GraphicsAddress[31:3]U28 + This field specifies Bits 31:3 of the Address where the DWord or QWord will be stored. Note that the + address can only be QWord aligned, irrespective of data size. + + 2 Destination Address Type + Project: All + Defines address space of Destination Address + Value Name Description Project + 0h PPGTT Use PPGTT address space for DW write All + 1h GGTT Use GGTT address space for DW write All + + Programming Notes + Ignored if “No write” is the selected in Operation. + 1:0 Reserved + Project: All + Format: MBZ +2..3 31:0 Immediate Data + + Format: U64 + + This field specifies the DWord value to be written to the targeted location. DW2 is the lower DW if QW + is desired. Only valid when 15:14 in header is set to 1h + To avoid hitting a known hardware bug, drivers cannot send a QW write when bit 5 of the address is ‘1’ + + Value Name + [0,FFFFFFFFh] + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 139 + 2.2.6 MI_LOAD_REGISTER_IMM + + MI_LOAD_REGISTER_IMM + +Source: BlitterCS +Length Bias: 2 +The MI_LOAD_REGISTER_IMM command requests a write of up to a DWord constant supplied in the command to +the specified Register Offset (i.e., offset into Memory-Mapped Register Range). The register is loaded before the +next command is executed. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 22h MI_ + 22:12 Reserved + Project: All + Format: MBZ + 11:8 Byte Write Disables + Format: Enable[4] Bit 8 corresponds to Data DWord [7:0] + + + + + Range: Must specify a valid register write operation + If [11:8] is '1111b', then the register write will not occur. + If [11:8] is '0000b', then the register DW will be updated. + Any other value, the behavior will be specifically specified by the register or the behavior is + undefined. + 7:0 DWord Length + Default Value: 1h Excludes DWord (0,1) + Format: =n Total Length - 2 + + + +1 31:2 Register Offset + Format: U30 + Format: MmioAddress[31:2] + This field specifies bits [31:2] of the offset into the Memory Mapped Register Range (i.e., this field + specifies a DWord offset). + + 1:0 Reserved + Project: All + Format: MBZ +2 31:0 Data DWord + Mask: Bytes Write Disables + Format: U32 + This field specifies the DWord value to be written to the targeted location. + + + + +140 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.2.7 MI_NOOP + + MI_NOOP + +Source: BlitterCS +Length Bias: 1 +The MI_NOOP command basically performs a “no operation” in the command stream and is typically used to pad the +command stream (e.g., in order to pad out a batch buffer to a QWord boundary). However, there is one minor +(optional) function this command can perform – a 22-bit value can be loaded into the MI NOPID register. This +provides a general-purpose command stream tagging ("breadcrumb") mechanism (e.g., to provide sequencing +information for a subsequent breakpoint interrupt). + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 0h MI_NOOP + 22 Identification Number Register Write Enable + Project: All + Format: Enable + This field enables the value in the Identification Number field to be written into the MI NOPID register. + If disabled, that register is unmodified – making this command an effective “no operation” function. + Value Name Description Project + 0h Disable Do not write the NOP_ID register. All + 1h Enable Write the NOP_ID register. All + 21:0 Identification Number + Project: All + Format: U22 + This field contains a 22-bit number which can be written to the MI NOPID register. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 141 + 2.2.8 MI_REPORT_HEAD + + MI_REPORT_HEAD + +Source: BlitterCS +Length Bias: 1 + +The MI_REPORT_HEAD command causes the Head Pointer value of the active ring buffer to be written to a +cacheable (snooped) system memory location. + Programming Notes +This command must not be executed from a Batch Buffer (Refer to the +description of the HWS_PGA register). + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 07h MI_REPORT_HEAD + 22:0 Reserved + Project: All + Format: MBZ + + + + +2.2.9 MI_SEMAPHORE_MBOX + + MI_SEMAPHORE_MBOX + +Source: BlitterCS +Length Bias: 2 + +This command is provided as alternative to MI_SEMAPHORE to provide mailbox-type semaphores where +there is no update of the semaphore by the checking process (the consumer). Single-bit compare-and- +update semantics are also provided. In either case, atomic access of semaphores need not be guaranteed +by hardware as with the previous command. This command should eventually supersede the previous +command. +Synchronization between contexts (especially between contexts running on 2 different engines) is provided +by the MI_SEMAPHORE_MBOX command. Note that contexts attempting to synchronize in this fashion +must be able to access a common memory location. This means the contexts must share the same virtual +address space (have the same page directory), must have a common physical page mapped into both of +their respective address spaces or the semaphore commands must be executing from a secure batch buffer +or directly from a ring with the Use Global GTT bit set such that they are “privileged” and will use the +(always shared) global GTT. +MI_SEMAPHORE with the Update Semaphore bit set (and the Compare Semaphore bit clear) +implements the Signal command, while the Wait command is indicated by Compare Semaphore being set. +Note that Wait can cause a context switch. Signal increments unconditionally. +If execution is stalled due to this command, the engine signals IDLE to Power Management. +DWord Bit Description + + + + +142 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + MI_SEMAPHORE_MBOX +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 16h MI_SEMAPHORE_MBOX + 22 Use Global GTT + Project: All + Format: U1 + If set, this command will use the global GTT to translate the Semaphore Address and this command + must be executing from a privileged (secure) batch buffer. If clear, the PPGTT will be used to translate + the Semaphore Address.This bit will be ignored (and treated as if clear) if this command is executed + from a non-privileged batch buffer. It is allowed for this bit to be clear when executing this command + from a privileged (secure) batch buffer or directly from a ring buffer. + Programming Notes + This field is only valid when Compare Register Field is reset. + 21 Update Semaphore + Project: All + Format: U1 + If set, the value from the Semaphore Data Dword is written to memory. If Compare Semaphore is also + set, the semaphore is not updated if the semaphore comparison fails.If clear, the data at Semaphore + Address is not changed. + Programming Notes + This field should be always clear when Compare Register Field is set. + 20 Compare Semaphore + Project: All + Format: U1 + If set, the value from the Semaphore Data Dword is compared to the value from the Semaphore + Address in memory when Compare Register is clear. If set, the value from the Semaphore Data + Dword is compared to the value from MMIO Register selected by Register Select field when + Compare Register is set. If the value at Semaphore Address/MMIO Register is greater than + the Semaphore Data Dword, execution is continued from the current command buffer. If clear, no + comparison takes place. Update Semaphoremust be set in this case. + + 19 Reserved + Project: All + Format: MBZ + 18 Compare Register + + Format: Compare Type + If set, data in MMIO register will be used for compare. If clear, data in memory will be used for + compare. + Programming Notes + Compare Register field should be always set. + 17:16 Register Select + + Format: Register Select + If compare register is set in bit[18], this field indicates which register will be used. + Value Name + 0 CS register (BRSYNC) + 2 VCS regiser (BVSYNC) + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 143 + MI_SEMAPHORE_MBOX + 3 Reserved + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Format: =n Total Length - 2 + + + +1 31:0 Semaphore Data Dword + Project: All + Format: U32 + Data dword to compare/update memory. The Data dword is supplied by software to control execution + of the command buffer. If the compare is enabled and the data at Semaphore Address is greater than + this dword, the execution of the command buffer continues. + +2 31:2 PointerBitFieldName/MMIO Register Address + Project: All + Format: GraphicsVirtualAddress[31:2]Semaphore + if Compare Register bit[18] is cleared, this field if the Graphics Memory Address of the 32 bit value for + the semaphore.If Compare Register bit[18] is set, this field is the MMIO address of the register for the + semaphore. + + 1:0 Reserved + Project: All + Format: MBZ + + + + +2.2.10 MI_STORE_REGISTER_MEM + + MI_STORE_REGISTER_MEM +Project: All +Source: BlitterCS +Length Bias: 2 + +The MI_STORE_REGISTER_MEM command requests a register read from a specified memory mapped +register location in the device and store of that DWord to memory. The register address is specified along +with the command to perform the read. + Programming Notes +The command temporarily halts command execution.The memory address for the write is snooped on the +host bus. +This command will cause undefined data to be written to memory if given register addresses for the +PGTBL_CTL_0 or FENCE registers + +DWord Bit Description +0 31:29 Command Type + + + + +144 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + MI_STORE_REGISTER_MEM + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 24h MI_STORE_REGISTER_MEM + Format: OpCode + 22 Use Global GTT + Project: All + This bit must be ‘1’ if the Per Process GTT Enable bit is clear + Value Name Description Project + 0h Per Process All + Graphics Address + 1h Global Graphics This command will use the global GTT to translate the Address and All + Address this command must be executing from a privileged (secure) batch + buffer. + + Programming Notes Project + This will not be ignored when in a PPGTT batch buffer. + 21:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 1h Excludes DWord (0,1) + Format: =n Total Length - 2 + + + +1 31:23 Reserved + + Format: MBZ + 22:2 Register Address + Project: All + Format: MMIOAddress[22:2]MMIO_Register + This field specifies Bits 22:2 of the Register offset the DWord will be read from. As the register + address must be DWord-aligned, Bits 1:0 of that address MBZ. + Programming Notes +  Storing a VGA register is not permitted and will store an UNDEFINED value. +  The values of PGTBL_CTL0 or any of the FENCE registers cannot be stored to memory; + UNDEFINED values will be written to memory if the addresses of these registers are specified. + + 1:0 Reserved + Project: All + Format: MBZ +2 31:2 Memory Address + + Format: GraphicsAddress[31:2]MMIO_Register + This field specifies the address of the memory location where the register value specified in the + DWord above will be written. The address specifies the DWord location of the data. + + 1:0 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 145 + MI_STORE_REGISTER_MEM + Format: MBZ + + + + +2.2.11 MI_STORE_DATA_IMM + + MI_STORE_DATA_IMM +Project: All +Source: BlitterCS +Length Bias: 2 +The MI_STORE_DATA_IMM command requests a write of the QWord constant supplied in the packet to the +specified Memory Address. As the write targets a System Memory Address, the write operation is coherent with the +CPU cache (i.e., the processor cache is snooped). + Programming Notes +This command can be used for general software synchronization through variables in cacheable memory (i.e., where +software does not need to poll un-cached memory or device registers). However, the cacheable nature of the +transaction is determined by the setting of the “mapping type” in the GTT entry. This command simply initiates the +write operation with command execution proceeding normally. Although the write operation is guaranteed to +complete “eventually”, there is no mechanism to synchronize command execution with the completion (or even +initiation) of these operations. All writes to memory generated using this command are expected to finish in order. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 20h MI_STORE_DATA_IMM + 22 Use Global GTT + Project: All + This bit must be ‘1’ if the Per Process GTT Enable bit is clear. + Value Name Description Project + 0h Per Process All + Graphics Address + 1h Global Graphics This command will use the global GTT to translate the Address and All + Address this command must be executing from a privileged (secure) batch + buffer. + + Programming Notes Project + This will not be ignored when in a PPGTT batch buffer. + 21 Reserved + + Format: MBZ + 20:10 Reserved + Project: All + Format: MBZ + 9:0 DWord Length + Default Value: 2h Excludes DWord (0,1) = 2 for DWord, 3 for QWord + + + + +146 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + MI_STORE_DATA_IMM + Format: =n Total Length - 2 + + + +1 31:0 Reserved + Project: All + Format: MBZ +2 31:2 Address + Project: All + Format: GraphicsAddress[31:2]U32(2) + This field specifies Bits 31:2 of the Address where the DWord will be stored. As the store address + must be DWord-aligned, Bits 1:0 of that address MBZ. This address must be 8B aligned for a store + “QW” command. + + 1:0 Reserved + Project: All + Format: MBZ +3 31:0 Data DWord 0 + Project: All + Format: U32 + This field specifies the DWord value to be written to the targeted location.For a QWord write this + DWord is the lower DWord of the QWord to be reported (DW 0). + +4 31:0 Data DWord 1 + Project: All + Format: U32 + This field specifies the upper DWord value to be written to the targeted QWord location (DW 1). + + + + +2.2.12 MI_STORE_DATA_INDEX + + MI_STORE_DATA_INDEX + +Source: BlitterCS +Length Bias: 2 +The MI_STORE_DATA_INDEX command requests a write of the data constant supplied in the packet to the +specified offset from the System Address defined by the Hardware Status Page Address Register. As the write +targets a System Address, the write operation is coherent with the CPU cache (i.e., the processor cache is snooped). + Programming Notes +Use of this command with an invalid or uninitialized value in the Hardware Status Page Address Register is +UNDEFINED. This command can be used for general software synchronization through variables in cacheable +memory (i.e., where software does not need to poll uncached memory or device registers). This command simply +initiates the write operation with command execution proceeding normally. Although the write operation is +guaranteed to complete “eventually”, there is no mechanism to synchronize command execution with the completion +(or even initiation) of these operations. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 147 + MI_STORE_DATA_INDEX + 28:23 MI Command Opcode + Default Value: 21h MI_STORE_DATA_INDEX + 22 Reserved + Project: All + Format: MBZ + 21 Reserved + + Format: MBZ + 20:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 1h Excludes DWord (0,1 ) = 1 for DWord, 2 for QWord + Format: =n Total Length - 2 + + + +1 31:12 Reserved + Project: All + Format: MBZ + 11:2 Offset + Project: All + Format: U10 zero-based DWord offset into the HW status page. + + + Format: HardwareStatusPageOffset[11:2]U32 + This field specifies the offset (into the hardware status page) to which the data will be written. Note that + the first few DWords of this status page are reserved for special-purpose data storage – targeting + these reserved locations via this command is UNDEFINED.This address must be 8B aligned for a + store “QW” command. + Value Name + [16, 1023] + 1:0 Reserved + Project: All + Format: MBZ +2 31:0 Data DWord 0 + Project: All + Format: U32 + This field specifies the DWord value to be written to the targeted location.For a QWord write this + DWord is the lower DWord of the QWord to be reported (DW 0). + +3 31:0 Data DWord 1 + Project: All + Format: U32 + This field specifies the upper DWord value to be written to the targeted QWord location (DW 1). + + + + +148 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.2.13 MI_SUSPEND_FLUSH + + MI_SUSPEND_FLUSH +Project: All +Source: BlitterCS +Length Bias: 1 + Description Project +Blocks MMIO sync flush or any flushes related to VT-d while enabled. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 0Bh MI_SUSPEND_FLUSH + 22:1 Reserved + Project: All + Format: MBZ + 0 Suspend Flush + Project: All + Format: Enable + + Description Project + This field suspends flush due and IOTLB invalidation. + + + + +2.2.14 MI_UPDATE_GTT + + MI_UPDATE_GTT + +Source: BlitterCS +Length Bias: 2 + +The MI_UPDATE_GTT command is used to update GTT page table entries in a coherent manner and at a +predictable place in the command flow. An MI_FLUSH should be placed before this command, because +work associated with preceding commands that are still in the pipeline may be referencing GTT entries that +will be changed by its execution. The flush will also invalidate TLBs and read caches that may become +invalid as a result of the changed GTT entries. MI_FLUSH is not required if it can be guaranteed that the +pipeline is free of any work that relies on changing GTT entries (such as MI_UPDATE_GTT contained in a +paging DMA buffer that is doing only update/mapping activities and no rendering). This is a privileged +command. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 23h MI_UPDATE_GTT + Format: OpCode + 22 Use Global GTT + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 149 + MI_UPDATE_GTT + Project: All + Reserved: Must be 1h. Updating Per Process Graphics Address is not supported + Value Name Description Project + 0h Per Process Graphics Address All + 1h Global Graphics Address All + 21:6 Reserved + Project: All + Format: MBZ + 5:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Format: =n + Total Length - 2 + +1 31:12 Entry Address + Project: All + Format: GraphicsAddress[31:12] + This field simply holds the DW offset of the first table entry to be modified. Note that one or more of + the upper bits may need to be 0, i.e., for a 2G aperture, bit 31 MBZ. + + 11:0 Reserved + Project: All + Format: MBZ +2..n 31:0 Entry Data + Project: All + Format: Table Entry + This Dword becomes the new page table entry. See PPGTT/Global GTT Table Entries (PTEs) in + Memory Interface Registers. + + + + +2.2.15 MI_USER_INTERRUPT + + MI_USER_INTERRUPT + +Source: BlitterCS +Length Bias: 1 +The MI_USER_INTERRUPT command is used to generate a User Interrupt condition. The parser will continue +parsing after processing this command. See User Interrupt. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 02h MI_USER_INTERRUPT + 22:0 Reserved + Project: All + Format: MBZ + + + + +150 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.2.16 MI_WAIT_FOR_EVENT + + MI_WAIT_FOR_EVENT + +Source: BlitterCS +Length Bias: 1 +The MI_WAIT_FOR_EVENT command is used to pause command stream processing until a specific event occurs or +while a specific condition exists. Only one event/condition can be specified -- specifying multiple events is +UNDEFINED.The effect of the wait operation depends on the source of the command. If executed from a batch +buffer, the parser will halt (and suspend command arbitration) until the event/condition occurs. If executed from a ring +buffer, further processing of that ring will be suspended, although command arbitration (from other rings) will +continue. Note that if a specified condition does not exist (the condition code is inactive) at the time the parser +executes this command, the parser proceeds, treating this command as a no-operation.If execution of this command +from a primary ring buffer causes a wait to occur, the active ring buffer will effectively give up the remainder of its +time slice (required in order to enable arbitration from other primary ring buffers). + Programming Notes Project + Driver must ensure blitter command stream is not waiting for an event with the following code: +  MI_LOAD_REGISTER_IMM with 0x22050[31:0] = 0x00010001 +  WAIT_FOR_EVENT +  MI_LOAD_REGISTER_IMM with 0x22050[31:0] = 0x00010000 + + RC6 entry must be disabled during a MI_WAIT_FOR_EVENT command with a Flip Pending Wait + Enable bit set if this command is in a batch buffer. If RC6 entry is required with a + MI_WAIT_FOR_EVENT command with a Flip Pending Wait Enable bit set then it needs to be + executed in the ring. + +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 03h MI_WAIT_FOR_EVENT + 22 Reserved + Project: All + Format: MBZ + 21 Reserved + + Format: MBZ + 20 Display Sprite C Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Sprite C “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). + + 19:16 Condition Code Wait Select + Project: All + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 151 + MI_WAIT_FOR_EVENT + This field enables a wait for the duration that the corresponding condition code is active. These enable + select one of 15 condition codes in the EXCC register, that cause the parser to wait until that + condition-code in the EXCC is cleared. + Value Name Description Project + 0h Not Enabled Condition Code Wait not enabled All + 1h-5h Enabled Condition Code select enabled; selects one of 5 codes, 0 – 4 All + 6h-15h Reserved All + + Programming Notes + Note that not all condition codes are implemented. The parser operation is UNDEFINED if an + unimplemented condition code is selected by this field. The description of the EXCC register (Memory + Interface Registers) lists the codes that are implemented. + 15 Display Plane C Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane C “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). + + 14 Reserved + + Format: MBZ + 13:12 Reserved + Project: All + Format: MBZ + 11 Reserved + + Format: MBZ + 10 Display Sprite B Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Sprite B “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). + + 9 Display Plane B Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane B “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). + + 8 Reserved + + Format: MBZ + 7:4 Reserved + Project: All + Format: MBZ + + + + +152 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + MI_WAIT_FOR_EVENT + 3 Reserved + + Format: MBZ + 2 Display Sprite A Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Sprite A “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). + + 1 Display Plane A Flip Pending Wait Enable + Project: All + Format: Enable + This field enables a wait for the duration of a Display Plane A “Flip Pending” condition. If a flip request + is pending, the parser will wait until the flip operation has completed (i.e., the new front buffer address + has now been loaded into the active front buffer registers). + + 0 Reserved + + Format: MBZ + + + + +2.2.17 MI_LOAD_REGISTER_MEM + + MI_LOAD_REGISTER_MEM + +Source: BlitterCS +Length Bias: 2 +The MI_LOAD_REGISTER_MEM command requests from a memory location and stores that DWord to a register. + Programming Notes + The following addresses should NOT be used for LRIs +  0x8800 - 0x88FF +  >= 0xC0000 + + Limited LRI cycles to the Display Engine 0x40000-0xBFFFF) are allowed, but must be spaced to allow only + one pending at a time. This can be done by issuing an SRM to the same address immediately after each + LRI. + +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 29h MI_LOAD_REGISTER_MEM + Format: OpCode + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 153 + MI_LOAD_REGISTER_MEM + 22 Use Global GTT + Project: All + This bit must be ‘1’ if the Per-Process GTT Enable bit is clear. + Value Name Description Project + 0h Per Process All + Graphics Address + 1h Global Graphics This command will use the global GTT to translate the Address and All + Address this command must be executing from a privileged (secure) batch + buffer. + 21 Async Mode Enable + Project: All + If this bit is set then the command stream will not wait for completion of this command before + executing the next command. + + 20:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 1h Excludes DWord (0,1) + Format: =n Total Length - 2 + + + +1 31:26 Reserved + Format: MBZ + 22:2 Register Address + Project: All + Format: MMIOAddress[22:2]MMIO_Register + This field specifies Bits 25:2 of the Register offset the DWord will be written to. As the register address + must be DWord-aligned, Bits 1:0 of that address MBZ. + + 1:0 Reserved + Format: MBZ +2 31:2 Memory Address + Project: All + Format: GraphicsAddress[31:2]MMIO_Register + This field specifies the address of the memory location where the register value specified in the DWord + above will read from. The address specifies the DWord location of the data. + + 1:0 Reserved + Project: All + Format: MBZ + + + + +154 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + 2.2.18 MI_DISPLAY_FLIP + + MI_DISPLAY_FLIP + +Source: BlitterCS +Length Bias: 2 +The MI_DISPLAY_FLIP command is used to request a specific display plane to switch (flip) to display a new buffer. +The buffer is specified with a starting address and pitch. The tiled attribute of the buffer start address is programmed +as part of the packet. +The operation this command performs is also known as a “display flip request” operation – in that the flip operation +itself will occur at some point in the future. This command specifies when the flip operation is to occur: either +synchronously with vertical retrace to avoid tearing artifacts + Programming Notes Project +This command simply requests a display flip operation -- command execution then continues normally. +There is no guarantee that the flip (even if asynchronous) will occur prior to subsequent commands being +executed. (Note that completion of the MI_FLUSH_DW command does not guarantee that outstanding flip +operations have completed). The MI_WAIT_FOR_EVENT command must be used to provide this +synchronization to avoid back to back MI_DISPLAY_FLIP commands to the same display plane – by +pausing command execution until a pending flip has actually completed. This synchronization can also be +performed by use of the Display Flip Pending hardware status. See Display Flip Synchronization in the +Device Programming Interface chapter of MI Functions. +After a display flip operation is requested, software is responsible for initiating any required synchronization +with subsequent buffer clear or blitter operations. For multi-buffering (e.g., double buffering) operations, this +will typically require updating SURFACE_STATE or the binding table to change the blitter (back) buffer. In +addition, prior to any subsequent clear or blitter operations, software must typically ensure that the new +blitter buffer is not actively being displayed. Again, the MI_WAIT_FOR_EVENT command or Display Flip +Pending hardware status can be used to provide this synchronization. See Display Flip Synchronization in +the Device Programming Interface chapter of MI Functions. +The display buffer command uses the X and Y offset for the tiled buffers from the Display Interface registers. +Software is allowed to change the offset via the MMIO interface irrespective of the flip commands enqueued +in the command stream. For tiled buffers, the display subsystem uses the X and Y offset in generation of the +final request to memory. The offset is always updated on the next vblank for both Synchronous and Asynch +Flips. It is not necessary to have a flip enqueued to update the X and Y offset +The display buffer command uses the linear dword offset for the linear buffers from the Display Interface +registers. Software is allowed to change the offset via the MMIO interface irrespective of the flip commands +enqueued in the command stream. For linear buffers, the display subsystem uses the dword offset in +generation of the final request to memory. +  For synchronous flips the offset is updated on the next vblank. It is not necessary to have a sync flip + enqueued to update the dword offset. +  Linear memory does not support asynchronous flips + +DWord 3 (Left Eye Display Buffer Base Address) must not be set with synchronous flips or asynchronous +flips. +The full packet must be contained within the same cache line. +There must be at least one valid command following this packet. +Events must be unmasked in the Display Engine Render Response Mask Register + (DE RRMR 0x44050) prior to waiting for them with a MI_WAIT_FOR_EVENT command, + or in the case of flips or scanlines, prior to starting the flip or loading the + scanline. Unmasked events will wake command streamer as they occur, so for improved + power savings it is recommended to only unmask events that are required. + Programming the DE RRMR register can be done through MMIO or a + LOAD_REGISTER_IMMEDIATE command. + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 155 + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 14h MI_DISPLAY_FLIP + Format: OpCode + 22 Async Flip Indicator + Project: All + Format: Enable + This bit should always be set if DW2 [1:0] == ‘01’ (async flip). This field is required due to HW + limitations. This bit is used by the blitter pipe while DW2 is used by the display hardware. + + 21:19 Display (Plane) Select + Project: All + Format: U3 + This field selects which display plane is to perform the flip operation. + Value Name Project + 0h Display Plane A All + 1h Display Plane B All + 2h Display Sprite A All + 3h Display Sprite B All + 4h Display Plane C + 5h Display Sprite C + 18:8 Reserved + Project: + Format: MBZ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Format: =n Total Length - 2 + + + For Synchronous Flips and Asynchronous Flips, this field must be programmed to 1h for a total length + of 3. + +1 31 Reserved + Project: + Format: MBZ + 30:16 Reserved + Project: All + Format: MBZ + 15:6 Display Buffer Pitch + Default Value: 0h DefaultVaueDesc + Project: All + Format: U10 + For Synchronous Flips only, this field specifies the 64-byte aligned pitch of the new display buffer. For + Asynchronous Flips, this parameter is programmed so that all the flips in a flip chain should maintain + the same pitch as programmed with the last synchronous or direct thru mmio + + 5:1 Reserved + + + + +156 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + MI_DISPLAY_FLIP + Project: All + Format: MBZ + 0 Tile Parameter + + Format: Enable + For Asynchronous Flips, this parameter cannot be changed. All the flips in a flip chain should maintain + the same tile parameter as programmed with the last synchronous flip or direct thru mmio. + Value Name Description + 0h Linear [Default] For Syncronous Flips Only + 1h Tiled X + + Programming Notes + Performing a synchronous or asynchronous flip will drop any previous synchronous flip that has not + yet completed. +2 31:12 Display Buffer Base Address + Project: All + Format: GraphicsAddress[31:12] + This field specifies Bits 31:12 of the Graphics Address of the new display buffer. + Programming Notes + The Display buffer must reside completely in Main Memory + This address is always translated via the global (rather than per-process) GTT + 11:3 Reserved + Project: All + Format: MBZ + 1:0 Flip Type + + This field specifies whether the flip operation should be performed asynchronously to vertical retrace. + Value Name Description Project + 00b Synchronous flip + [Default] + 00b Sync Flip [Default] The flip will occur during the vertical blanking interval – thus All + avoiding any tearing artifacts. + 01b Async Flip The flip will occur “as soon as possible” – and may exhibit All + tearing artifacts + 1b Reserved All + + + + +Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 5/31/2012 157 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +158 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 4 – 05 12 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol1_part5.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part5.txt new file mode 100644 index 0000000..df808e4 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part5.txt @@ -0,0 +1,3281 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 1 Part 5: Graphics Core™ – Video Codec +Engine Command Streamer (Ivy Bridge) + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + Contents +1. Video Codec Engine Command Streamer .......................................................................................... 4 + 1.1 Registers for Video Codec ................................................................................................................... 4 + 1.1.1 Introduction ..................................................................................................................................... 4 + 1.1.2 Virtual Memory Control ................................................................................................................... 4 + 1.1.3 Mode and Misc Ctrl Registers ........................................................................................................ 8 + 1.1.4 VCS_RINGBUF—Ring Buffer Registers ...................................................................................... 16 + 1.1.5 Watchdog Timer Registers ........................................................................................................... 22 + 1.1.6 Interrupt Control Registers ........................................................................................................... 23 + 1.1.7 Logical Context Support ............................................................................................................... 30 + 1.1.8 Image Enhancement Registers .................................................................................................... 32 + 1.1.9 Registers in Media Engine ............................................................................................................ 35 + 1.2 Memory Interface Commands for Video Codec Engine .................................................................... 50 + 1.2.1 Introduction ................................................................................................................................... 50 + 1.2.2 MI_ARB_CHECK .......................................................................................................................... 51 + 1.2.3 MI_ARB_ON_OFF ........................................................................................................................ 51 + 1.2.4 MI_BATCH_BUFFER_END ......................................................................................................... 52 + 1.2.5 MI_CONDITIONAL_BATCH_BUFFER_END ............................................................................... 52 + 1.2.6 MI_BATCH_BUFFER_START ..................................................................................................... 53 + 1.2.7 MI_FLUSH_DW ............................................................................................................................ 55 + 1.2.8 MI_LOAD_REGISTER_IMM ........................................................................................................ 57 + 1.2.9 MI_NOOP ..................................................................................................................................... 59 + 1.2.10 MI_SEMAPHORE_MBOX .......................................................................................................... 60 + 1.2.11 MI_STORE_REGISTER_MEM .................................................................................................. 62 + 1.2.12 MI_STORE_DATA_IMM ............................................................................................................. 63 + 1.2.13 MI_STORE_DATA_INDEX ......................................................................................................... 65 + 1.2.14 MI_SUSPEND_FLUSH .............................................................................................................. 66 + 1.2.15 MI_USER_INTERRUPT ............................................................................................................. 67 + 1.2.16 MI_UPDATE_GTT ...................................................................................................................... 67 + 1.2.17 MI_WAIT_FOR_EVENT ............................................................................................................. 68 + 1.2.18 MI_LOAD_REGISTER_MEM ..................................................................................................... 69 + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/29/12 3 + 1. Video Codec Engine Command + Streamer +Full decode pipeline as well as encode pipeline are implemented in VCE. +VCE has its own command streamer and operates completely independently of the render (3D/Media) +pipeline command streamer. + + +1.1 Registers for Video Codec + +1.1.1 Introduction +This command streamer supports a completely independent set of registers. Only a subset of the MI +Registers is supported for this 2nd command streamer. The effort is to keep the registers at the same +offset as the render command streamer registers. The base of the registers for the video decode engine +will be defined per project, the offsets will be maintained. + Base Address Value for the memory interface register offset for the Bit + Project Stream Command Stream + 0x10000 + eg: The Ring buffer tail pointer will be 0x10000 + 0x2030 + + + +1.1.2 Virtual Memory Control +MFX engine Supports a 2-level mapping scheme for PPGTT, consisting of a first-level page directory +containing page table base addresses, and the page tables themselves on the 2 nd level, consisting of +page addresses. + +1.1.2.1 VCS_PP_DCLV – VCS PPGTT Directory Cacheline Valid Register + + VCS_PP_DCLV - VCS PPGTT Directory Cacheline Valid Register +Register Space: MMIO: 0/2/0 + +Source: VideoCS +Default Value: 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 64 +Address: 12220h + +This register controls update of the on-chip PPGTT Directory Cache during a context restore. Bits that are set will +trigger the load of the corresponding 16 directory entry group. + +This register is restored with context (prior to restoring the on-chip directory cache itself). This register is also +restored when switching to a context whose LRCA matches the current CCID if the Force PD Restore bit is set in +the context descriptor. The context image of this register must be updated and maintained by SW; SW should not + + + +4 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + VCS_PP_DCLV - VCS PPGTT Directory Cacheline Valid Register + normally need to read this register. + + This register can also effectively be used to limit the size of a processes’ virtual address space. Any access by a + process that requires a PD entry in a set that is not enabled in this register will cause a fatal error, and no fetch of + the PD entry will be attempted. + DWord Bit Description +0 63:32 Reserved + Format: MBZ + 31:0 PPGTT Directory Cache Restore [1..32] 16 entries + Format: Enable[32] + If set, the [1st..32nd] 16 entries of the directory cache are considered valid and will be brought in on + context restore. If clear, these entries are considered invalid and fetch of these entries will not be + attempted. + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 5 + 1.1.2.2 VCS_EXCC—Execute Condition Code Register + + VCS_EXCC - VCS Execute Condition Code Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W,RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12028h + + + + This register contains user defined and hardware generated conditions that are used by MI_WAIT_FOR_EVENT + commands. An MI_WAIT_FOR_EVENT instruction excludes the executing ring from arbitration if the selected event + evaluates to a 1, while instruction is discarded if the condition evaluates to a 0. Once excluded, a ring is enabled + into arbitration when the selected condition evaluates to a 0. + + This register also contains control for the invalidation of indirect state pointers on context restore. + DWord Bit Description +0 31:16 Mask Bits + Format: Mask[15:0] + + These bits serve as a write enable for bits 15:0. If this register is written with any of these bits clear + the corresponding bit in the field 15:0 will not be modified. + + Reading these bits always returns 0s. + + 15:8 Reserved + Format: MBZ + 4:0 User Defined Condition Codes + The software may signal a Stream Semaphore by setting the Mask bit and Signal Bit together to + match the bit field specified in a WAIT_FOR_EVENT (Semaphore). + + + + +6 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.2.2.1 VCS_HWS_PGA — VCS Hardware Status Page Address Register + + VCS_HWS_PGA - VCS Hardware Status Page Address Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 04180h + + +This register is used to program the 4 KB-aligned System Memory address of the Hardware Status Page used to +report hardware status into (typically cacheable) System Memory. + Programming Notes Project +If this register is written, a workload must subsequently be dispatched to the video command streamer. +DWord Bit Description +0 31:12 Address + Format: GraphicsAddress[31:12] + This field is used by SW to specify Bits 31:12 of the 4 KB-aligned System Memory address of the 4 KB + page known as the Hardware Status Page. The Global GTT is used to map this page from the graphics + virtual address to physical address. + Programming Notes + If the Per-Process Virtual Address Space bit is set, HW requires that the status page is programmed + to allow for the context switch status to be reported. + 11:1 Reserved + Format: MBZ + 0 Translation In Progress + Format: U1 + This field indicates that the translation for the hardware status page from the graphics virtual address to + the physical address is pending. Software can use this indicator to prevent updating the status page + when there is a pending cycle for translation. + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 7 + 1.1.3 Mode and Misc Ctrl Registers + +1.1.3.1 2nd Level Batch Buffer Address + + 2nd Level Batch Buffer Address +Register Space: MMIO: 0/2/0 +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 12144h + + +This register is to read the current value of the 2nd level batch buffer address. Since the 2nd level batch buffer logic +is shared with the C6 work-around batch buffer, this also shows the work-around address when it is active. + DWord Bit Description +0 31:2 WA Batch Buffer Address + Format: U30 + Pointer to the WA Batch Buffer Address. + + 1:0 Reserved + Format: MBZ + + + + +8 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.3.2 VCS_CXT_SIZE - VCS Context Sizes + + VCS_CXT_SIZE - VCS Context Sizes +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00040D00 +Access: Read/32 bit Write Only +Size (in bits): 32 +Address: 121A8h + + + DWord Bit Description +0 31:21 Reserved + Format: MBZ + 20:16 VCS Context Size + Format: U5 + + + Value Name Project + 4h [Default] + 15:13 Reserved + Format: MBZ + 12:8 VCR Context Size + Format: U3 + + + Value Name Project + Dh [Default] + 7:5 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 9 + 1.1.3.3 VCS_MI_MODE — VCS Mode Register for Software Interface + + VCS_MI_MODE - VCS Mode Register for Software Interface +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 1209Ch-1209Fh + + +The MI_MODE register contains information that controls software interface aspects of the command parser. +DWord Bit Description +0 31:16 Masks + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0. + 15 Suspend Flush + Mask: MMIO(0x209c)#31 + + + Value Name Description + 0h No Delay HW will not delay flush, this bit will get cleared by MI_SUSPEND_FLUSH as well + 1h DelayFlush Suspend flush is active + 14:12 Reserved + Access: R/W + 11 Invalidate UHPTR enable + If bit set H/W clears the valid bit of BCS_UHPTR (4134h, bit 0) when current active head pointer is + equal to UHPTR. + 10 Reserved + + Format: MBZ + 9 Ring Idle (Read Only Status bit) + Access: RO + Writes to this bit are not allowed. + Value Name + 0 Parser not idle + 1 Parser idle + 8 Stop Ring + + Software must set this bit to force the Ring and Command Parser to Idle. Software must read a “1” in + Ring Idle bit after setting this bit to ensure that the hardware is idle. + + Software must clear this bit for Ring to resume normal operation. + Value Name + 0 Normal Operation + 1 Parser is turned off + 7:0 Reserved + Access: R/W + + + + +10 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.3.4 MFX_MODE – Video Mode Register + + MFX_MODE - Video Mode Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 1229Ch + + +This register contains a control bit for the 2-level PPGTT functions. +DWord Bit Description +0 31:16 Mask Bits + Format: Mask[15:0] + Must be set to modify corresponding bit in Bits 15:0. (All implemented bits) + + 14 Reserved + + Format: MBZ + 13:10 Reserved + Project: All + Format: MBZ + 9 Per-Process GTT Enable + Format: Enable Per-Process GTT BS Mode Enable + + + + + Value Name Description + 0h PPGTT Disable When clear, the Global GTT will be used to translate memory access from + [Default] designated commands and for commands that select the PPGTT as their + translation space. + 1h PPGTT Enable When set, the PPGTT will be used to translate memory access from designated + commands and for commands that select the PPGTT as their translation space. + 7 Reserved + + Format: MBZ + 6:5 Reserved + Project: All + Format: MBZ + 4:0 Reserved + + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 11 + 1.1.3.5 VCS_INSTPM—VCS Instruction Parser Mode Register + + VCS_INSTPM - VCS Instruction Parser Mode Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 120C0h-120C3h + + + + The VCS_INSTPM register is used to control the operation of the VCS Instruction Parser. Certain classes of + instructions can be disabled (ignored) – often useful for detecting performance bottlenecks. Also, “Synchronizing + Flush” operations can be initiated – useful for ensuring the completion (vs. only parsing) of rendering instructions. + DefaultValue=0000 0000h + Programming Notes +All reserved bits are implemented. +DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + These bits serve as write enables for bits 15:0. If this register is written with any of these bits clear the + corresponding bit in the field 15:0 will not be modified. Reading these bits always returns 0s. + + 15:11 Reserved + Project: All + Format: MBZ + 10 Reserved + + Format: MBZ + 9 TLB Invalidate + + Format: U1 + + If set, this bit allows the command stream engine to invalidate the MFX TLBs. This bit is valid only with + the Sync flush enable. + + Note: GFX soft resets do not invalidate TLBs, it is up to GFX driver to explicitly invalidate TLBs post + reset./ + + 8:7 Reserved + Format: MBZ + 6 Memory Sync Enable + + If set, this bit allows the video decode engine to write out the data from the local caches to memory. + + 5 Sync Flush Enable + + Format: Enable (Cleared by HW) + + + + +12 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + VCS_INSTPM - VCS Instruction Parser Mode Register + + + This field is used to request a Sync Flush operation. The device will automatically clear this bit before + completing the operation. See Sync Flush (Programming Environment). + + Setting the Sync Flush Enable will cause a config write to MMIO register space with the address + 0x4f100. + Programming Notes + The command parser must be stopped prior to issuing this command by setting the Stop Ring bit in + register BCS_MI_MODE. Only after observing Ring Idleset in BCS_MI_MODE can a Sync Flush be + issued by setting this bit. Once this bit becomes clear again, indicating flush complete, the command + parser is re-enabled by clearing Stop Ring. + 4:0 Reserved + Access: R/W + Format: MBZ + + + +1.1.3.6 VCS_NOPID — NOP Identification Register + + VCS_NOPID - VCS NOP Identification Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 12094h-12097h + + +The VCS_NOPID register contains the Noop Identification value specified by the last MI_NOOP instruction that +enabled this register to be updated. +DWord Bit Description +0 31:22 Reserved + Format: MBZ + 21:0 Identification Number + This field contains the 22-bit Noop Identification value specified by the last MI_NOOP instruction that + enabled this field to be updated. + Programming Notes +  +  Although this is a R/W register, it should only be written to by the MI_NOOP command. Write + access is needed for power management support. + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 13 + 1.1.3.7 VBSYNC – Video/Blitter Semaphore Sync Register + + VBSYNC - Video/Blitter Semaphore Sync Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 12040h +This register is written by BCS, read by VCS. + DWord Bit Description +0 31:0 Semaphore Data + Semaphore data for synchronization between video codec engine and blitter engine. + + + +1.1.3.8 VRSYNC – Video/Render Semaphore Sync Register + + VRSYNC - Video/Render Semaphore Sync Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 12044h +This register is written by CS, read by VCS. + DWord Bit Description +0 31:0 Semaphore Data + Semaphore data for synchronization between video codec engine and render engine. + + + + +14 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.3.9 GAC_MODE — Mode Register for GAC + + GAC_MODE - Mode Register for GAC +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 120A0h-120A3h + + +The GAC_MODE register contains information that controls configurations in the GAC. + DWord Bit Description +0 31:16 Masks + Format: Mask[15:0] + A 1 in a bit in this field allows the modification of the corresponding bit in Bits 15:0. + + 15:0 Reserved + Access: R/W + + + +1.1.3.10 VCS_PREEMPTION_HINT_UDW + + VCS_PREEMPTION_HINT_UDW - VCS_PREEMPTION_HINT_UDW +Register Space: MMIO: 0/2/0 +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 124C8h + + +This register contains the 4GB aligned base address of gfx 4GB virtual address space within the host’s 64-bit virtual +address space of the Batch Buffer corresponding to MI_ARB_CHECK command called Preemption Hint Address. + Programming Notes +Programming Restriction: +This register should NEVER be programmed in functional mode, this should be used only in validation mode +to achieve deterministic behavior of UHPTR being sampled by a given MI_ARB_CHK in command stream. +DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15:0 Preempted Hint Address + Format: GraphicsAddress[47:32] + This field contains the 4GB aligned base address of gfx 4GB virtual address space within the host's 64- + bit virtual address space of the batch buffer when Preemption Hint is set to Batch Buffer. This field is + not valid when Preemption Hint is set to Ring Buffer. + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 15 + 1.1.4 VCS_RINGBUF—Ring Buffer Registers + + RING_BUFFER_TAIL - Ring Buffer Tail +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02030h +Name: RCS Ring Buffer Tail +ShortName: RCS_RING_BUFFER_TAIL +Address: 12030h +Name: VCS Ring Buffer Tail +ShortName: VCS_RING_BUFFER_TAIL +Address: 22030h +Name: BCS Ring Buffer Tail +ShortName: BCS_RING_BUFFER_TAIL +These registers are used to define and operate the “ring buffer” mechanism which can be used to pass instructions +to the command interface. The buffer itself is located in a linear memory region. The ring buffer is defined by a 4 +Dword register set that includes starting address, length, head offset, tail offset, and control information. + Refer to the Programming Interface chapter for a detailed description of the parameters specified in this ring buffer +register set, restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be +used to pass instructions. + Ring Buffer Tail Offsets must be properly programmed before ring is enabled. A Ring Buffer can be enabled when +empty. +DWord Bit Description +0 31:21 Reserved + Format: MBZ + 20:3 Tail Offset + Format: GraphicsAddress[20:3] + This field is written by software to specify where the valid instructions placed in the ring buffer end. The + value written points to the QWord past the last valid QWord of instructions. In other words, it can be + defined as the next QWord that software will write instructions into. + Software must write subsequent instructions to QWords following the Tail Offset, possibly wrapping + around to the top of the buffer (i.e., software can’t skip around within the buffer). + Note that all DWords prior to the location indicated by the Tail Offset must contain valid instruction + data – which may require instruction padding by software. See Head Offset for more information. + + 2:0 Reserved + Format: MBZ + + + + +16 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + RING_BUFFER_HEAD - Ring Buffer Head +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02034h +Name: RCS Ring Buffer Head +ShortName: RCS_RING_BUFFER_HEAD +Address: 12034h +Name: VCS Ring Buffer Head +ShortName: VCS_RING_BUFFER_HEAD +Address: 22034h +Name: BCS Ring Buffer Head +ShortName: BCS_RING_BUFFER_HEAD +This register is used to define and operate the ring buffer mechanism which can be used to pass instructions to the +command interface. The buffer itself is located in a physical memory region. The ring buffer is defined by a 4 Dword +register set that includes starting address, length, head offset, tail offset, and control information. Refer to the +Programming Interface chapter for a detailed description of the parameters specified in this ring buffer register set, +restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be used to pass +instructions. +Ring Buffer Head Offsets must be properly programmed before ring is enabled. A Ring Buffer can be +enabled when empty. +DWord Bit Description +0 31:21 Wrap Count + Format: U11 count of ring buffer wraps + + + This field is incremented by 1 whenever the Head Offset wraps from the end of the buffer back to the + start (i.e., whenever it wraps back to 0). Appending this field to the Head Offset field effectively creates + a virtual 4GB Head “Pointer” which can be used as a tag associated with instructions placed in a ring + buffer. The Wrap Count itself will wrap to 0 upon overflow. + + 20:2 Head Offset + Format: GraphicsAddress[20:2] DWord Offset + + + This field indicates the offset of the next instruction DWord to be parsed. Software will initialize this field + to select the first DWord to be parsed once the RB is enabled. (Writing the Head Offset while the RB is + enabled is UNDEFINED). Subsequently, the device will increment this offset as it executes instructions + – until it reaches the QWord specified by the Tail Offset. At this point the ring buffer is considered + “empty”. + Programming Notes + A RB can be enabled empty or containing some number of valid instructions. + 1 Reserved + Format: MBZ + 0 Wait for Condition Indicator + Source: RenderCS + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 17 + RING_BUFFER_HEAD - Ring Buffer Head + This is a read only value used to indicate whether or not the command streamer is currently waiting for + a conditional code to be cleared from 0x2028 + + 0 Reserved + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + Format: MBZ + + + + + RING_BUFFER_START - Ring Buffer Start +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02038h +Name: RCS Ring Buffer Start +ShortName: RCS_RING_BUFFER_START +Address: 12038h +Name: VCS Ring Buffer Start +ShortName: VCS_RING_BUFFER_START +Address: 22038h +Name: BCS Ring Buffer Start +ShortName: BCS_RING_BUFFER_START +These registers are used to define and operate the “ring buffer” mechanism which can be used to pass instructions +to the command interface. The buffer itself is located in a physical memory region. The ring buffer is defined by a 4 +Dword register set that includes starting address, length, head offset, tail offset, and control information. Refer to the +Programming Interface chapter for a detailed description of the parameters specified in this ring buffer register set, +restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be used to pass +instructions. + DWord Bit Description +0 31:12 Starting Address + Format: GraphicsAddress[31:12]RingBuffer + This field specifies Bits 31:12 of the 4KB-aligned starting Graphics Address of the ring buffer. + Address bits 31 down to 29 must be zero. + All ring buffer pages must map to Main Memory (uncached) pages. Ring Buffer addresses are + always translated through the global GTT. + + 11:0 Reserved + Format: MBZ + + + + +18 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + RING_BUFFER_CTL - Ring Buffer Control +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 0203Ch +Name: RCS Ring Buffer Control +ShortName: RCS_RING_BUFFER_CTL +Address: 1203Ch +Name: VCS Ring Buffer Control +ShortName: VCS_RING_BUFFER_CTL +Address: 2203Ch +Name: BCS Ring Buffer Control +ShortName: BCS_RING_BUFFER_CTL +These registers are used to define and operate the ring buffer mechanism which can be used to pass instructions to +the command interface. The buffer itself is located in a physical memory region. The ring buffer is defined by a 4 +Dword register set that includes starting address, length, head offset, tail offset, and control information. Refer to the +Programming Interface chapter for a detailed description of the parameters specified in this ring buffer register set, +restrictions on the placement of ring buffer memory, arbitration rules, and in how the ring buffer can be used to pass +instructions. +Ring Buffer Head and Tail Offsets must be properly programmed before it is enabled. A Ring Buffer can be +enabled when empty. +DWord Bit Description +0 31:21 Reserved + Format: MBZ + 20:12 Buffer Length + Format: U9-1 in 4 KB pages – 1 + + + This field is written by SW to specify the length of the ring buffer in 4 KB Pages.Range = [0 = 1 page = + 4 KB, 1FFh = 512 pages = 2 MB] + Value Name Description + 0 1 page = 4 KB + 1FFh 512 pages = 2 MB + 11 RBWait + Indicates that this ring has executed a WAIT_FOR_EVENT instruction and is currently waiting. + Software can write a “1” to clear this bit, write of “0” has no effect. When the RB is waiting for an event + and this bit is cleared, the wait will be terminated and the RB will be returned to arbitration. + 10 Semaphore Wait + Description Project + Indicates that this ring has executed a MI_SEMAPHORE_MBOX instruction with register + compare and is currently waiting. + 9 Reserved + Format: MBZ + 8 Reserved + Source: RenderCS, BlitterCS + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 19 + RING_BUFFER_CTL - Ring Buffer Control + Format: MBZ + 8 Disable Register Accesses + Source: VideoCS, VideoCS2, VideoEnhancementCS + + + Value Name Description + 0 R/W Ring is allowed to access (read or write) MMIO space. + 1 Read Only Ring is not allowed to write MMIO space. Ring is allowed to read registers. + 7:3 Reserved + Format: MBZ + 2:1 Automatic Report Head Pointer + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + + + Description Project + This field is written by software to control the automatic “reporting” (write) of this ring buffer’s + “Head Pointer” register (register DWord 1) to the corresponding location within the Hardware + Status Page. Automatic reporting can either be disabled or enabled at 4KB, 64KB or 128KB + boundaries within the ring buffer. + The head pointer will be reported to the head pointer location in the Per-Process Hardware + Status Page when it passes each 4KB page boundary. When the above-mentioned bit is set, + reporting will behave just as on the prior devices (as documented above), and option 2 is not + legal. + + + Value Name Description + 0 MI_AUTOREPORT_OFF Automatic reporting disabled + 1 MI_AUTOREPORT_64KB Report every 16 pages (64KB) + 2 MI_AUTOREPORT_4KB Report every page (4KB)This mode must not be enabled in Ring + Buffer mode of scheduling to minimize the auto reports. + 3 MI_AUTOREPORT_128KB Report every 32 pages (128KB) + 2:1 Reserved + + Source: RenderCS + Format: MBZ + 0 Ring Buffer Enable + Format: Enable + This field is used to enable or disable this ring buffer. It can be enabled or disabled regardless of + whether there are valid instructions pending. If disabled and the ring head equals ring tail, all state + currently loaded in hardware is considered invalid. + Programming Notes Project + SW should follow the below programming notes while enabling render engine's ring buffer for + the first time, this would be coming out of boot, standby, hibernate or reset. + + +  + SW should set the Force Wakeup bit to prevent GT from entering C6. +  + SW should dispatch workload (dummy) to initialize render engine with default state such that + any context switches that occur subsequently (Power Save) will save and restore coherent + + + + +20 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + RING_BUFFER_CTL - Ring Buffer Control + device state. Indirect pointers used in 3D states should point to valid graphics surface + existing in memory. PP_DCLV followed by PP_DIR_BASE register should be programmed + as part of initialization workload if PPGTT is enabled in GFX_MODE register. +  + Once the render engine is programmed with valid state and the configuration, Force Wakeup + bit should be reset to enable C6 entry. + + + + +1.1.4.1 VCS_UHPTR — Pending Head Pointer Register + + UHPTR - Pending Head Pointer Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Address: 02134h +Name: RCS Pending Head Pointer Register +ShortName: RCS_UHPTR +Address: 12134h +Name: VCS Pending Head Pointer Register +ShortName: VCS_UHPTR +Address: 22134h +Name: BCS Pending Head Pointer Register +ShortName: BCS_UHPTR + Programming Notes +Once SW uses UHPTR to preempt the existing workload, should explicitly program MI_SET_CONTEXT to save the +preempted context status before submitting the new workload. In case SW doesn’t want to save the state of the +preempted context, it should at the minimum program RS_PREEMPT_STATUS to 0x0 so that the register status +doesn’t interfere with the new workloads. + DWord Bit Description +0 31:3 Head Pointer Address + Format: GraphicsAddress[31:3] + This register represents the GFX address offset where execution should continue in the ring buffer + following execution of an MI_ARB_CHECK command. + + 2:1 Reserved + Format: MBZ + 0 Head Pointer Valid + This bit is set by the software to request a pre-emption. + It is reset by hardware when an MI_ARB_CHECK command is parsed by the command streamer. + The hardware uses the head pointer programmed in this register at the time the reset is generated. + Value Name Description + 0 InValid No valid updated head pointer register, resume execution at the current location in the + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 21 + UHPTR - Pending Head Pointer Register + ring buffer + 1 Valid Indicates that there is an updated head pointer programmed in this register + + + + +1.1.5 Watchdog Timer Registers + +1.1.5.1 VCS_CNTR—Counter for the bit stream decode engine + + VCS_CNTR - VCS Counter for the bit stream decode engine +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0xFFFFFFFF +Access: R/W +Size (in bits): 32 +Address: 12178h-1217Bh + + + DWord Bit Description +0 31:0 Count Value + Default Value: ffffffffh + + Writing a Zero value to this register starts the counting. + + Writing a Value of FFFF FFFF to this counter stops the counter. + + + + +22 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.5.2 VCS_THRSH—VCS Threshold for the counter of bit stream decode + engine + + VCS_THRSH - VCS Threshold for the counter of bit stream decode + engine +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00150000 +Access: R/W +Size (in bits): 32 +Address: 1217Ch-1217Fh + + +DWord Bit Description +0 31:0 Threshold Value + Default Value: 00150000h + The value in this register reflects the number of clocks the bit stream decode engine is expected to run. + If the value is exceeded the counter is reset and an interrupt may be enabled in the device. + + + + +1.1.6 Interrupt Control Registers +The Interrupt Control Registers described below all share the same bit definition. The bit definition is as +follows: + +Bit Definition for Interrupt Control Registers + Bit Description + 31:21 + Reserved. MBZ: These bits may be assigned to interrupts on future products/steppings. + + 20 + Context Switch Interrupt: Set when a context switch has just occurred. + + 19 + Page Fault: This bit is set whenever there is a pending page or directory fault. + This bit is set whenever there is a pending page or directory fault in Video command streamer. + 18 + Timeout Counter Expired: Set when the VCS timeout counter has reached the timeout thresh-hold + value. + 17 Reserved + 16 + MI_FLUSH_DW Notify Interrupt: The Pipe Control packet (Fences) specified in 3D pipeline + document may optionally generate an Interrupt. The Store QW associated with a fence is completed + ahead of the interrupt. + 15 + Video Command Parser Master Error: When this status bit is set, it indicates that the hardware has + detected an error. It is set by the device upon an error condition and cleared by a CPU write of a one + to the appropriate bit contained in the Error ID register followed by a write of a one to this bit in the IIR. + Further information on the source of the error comes from the “Error Status Register” which along with + the “Error Mask Register” determine which error conditions will cause the error status bit to be set and + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 23 + Bit Description + the interrupt to occur. + Page Table Error: Indicates a page table error. + Instruction Parser Error: The Video Instruction Parser encounters an error while parsing an + instruction. + 14 + Sync Status: This bit is set when the Instruction Parser completes a flush with the sync enable bit + active in the INSTPM register. The event will happen after all the MFX engines are flushed. The HW + Status DWord write resulting from this event will cause the CPU’s view of graphics memory to be + coherent as well (flush and invalidate the MFX cache).It is the driver’s responsibility to clear this bit + before the next sync flush with HWSP write enabled + + 13 + Reserved: MBZ + + 12 + Video Command Parser User Interrupt: This status bit is set when an MI_USER_INTERRUPT + instruction is executed on the Video Command Parser. Note that instruction execution is not halted + and proceeds normally. A mechanism such as an MI_STORE_DATA instruction is required to + associate a particular meaning to a user interrupt. + 11:0 + Reserved: MBZ + +The following table specifies the settings of interrupt bits stored upon a “Hardware Status Write” due to +ISR changes: + ISR bit Reporting via + Hardware Status Write (when + Bit Interrupt Bit unmasked via HWSTAM) + Not supported to be unmasked + Context Switch Interrupt: Set when a context switch has just occurred. + 8 + Set when event occurs, cleared + Page Fault: This bit is set whenever there is a pending PPGTT (page or + when event cleared + directory) fault. + 7 + Not supported to be unmasked + Media Decode Pipeline Counter Exceeded Notify Interrupt: The + counter threshold for the execution of the media pipeline is exceeded. + Driver needs to attempt hang recovery. + 6 + Reserved + 5 + 4 MI_FLUSH_DW packet - Notify Enable 0 + 3 Master Error Set when error occurs, cleared + when error cleared + 2 Sync Status Set every SyncFlush Event + 0 User Interrupt 0 + + + + +24 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.6.1 VCS_HWSTAM - VCS Hardware Status Mask Register + + VCS_HWSTAM - VCS Hardware Status Mask Register +Register Space: MMIO: 0/2/0 +Project: All +Source: VideoCS +Default Value: 0xFFFFFFFF +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 12098h + + +Access: RO for Reserved Control bits +The HWSTAM register has the same format as the Interrupt Control Registers. The bits in this register are “mask” +bits that prevent the corresponding bits in the Interrupt Status Register from generating a “Hardware Status Write” +(PCI write cycle). Any unmasked interrupt bit (HWSTAM bit set to 0) will allow the Interrupt Status Register to be +written to the ISR location (within the memory page specified by the Hardware Status Page Address Register) when +that Interrupt Status Register bit changes state. + Programming Notes +  To write the interrupt to the HWSP, the corresponding IMR bit must also be clear (enabled). +  At most 1 bit can be unmasked at any given time. + + + DWord Bit Description +0 31:0 Hardware Status Mask Register + Default Value: FFFFFFFFh + Format: Array of Masks + Refer to the table in the Interrupt Control Register section for bit definitions. + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 25 + 1.1.6.2 VCS_IMR - VCS Interrupt Mask Register + + VCS_IMR - VCS Interrupt Mask Register +Register Space: MMIO: 0/2/0 +Project: All +Source: VideoCS +Default Value: 0xFFFFFFFF +Access: R/W +Size (in bits): 32 +Address: 120A8h + + +The IMR register is used by software to control which Interrupt Status Register bits are masked or unmasked. +Unmasked bits will be reported in the IIR, possibly triggering a CPU interrupt, and will persist in the IIR until cleared +by software. Masked bits will not be reported in the IIR and therefore cannot generate CPU interrupts. + DWord Bit Description +0 31:0 Interrupt Mask Bits + Format: Array of interrupt mask bits Refer to the Interrupt Control Register section for bit + definitions. + + + This field contains a bit mask which selects which interrupt bits (from the ISR) are reported in the + IIR. + Value Name Description + FFFF FFFFh [Default] + 0h Not Masked Will be reported in the IIR + 1h Masked Will not be reported in the IIR + + + +1.1.6.3 VCS Hardware - Detected Error Bit Definitions (for EIR, EMR, ESR) +This section defines the Hardware-Detected Error bit definitions and ordering that is common to the EIR, +EMR and ESR registers. The EMR selects which error conditions (bits) in the ESR are reported in the +EIR. Any bit set in the EIR will cause the Master Error bit in the ISR to be set. EIR bits will remain set until +the appropriate bit(s) in the EIR is cleared by writing the appropriate EIR bits with ‘1’(except for the +unrecoverable bits described below). +The following table describes the Hardware-Detected Error bits: + + VCS Hardware-Detected Error Bit Definitions + +Source: VideoCS +Default Value: 0x00000000 +DWord Bit Description +0 15:3 Reserved + Format: MBZ + 2 Reserved + + Format: MBZ + + + + +26 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + VCS Hardware-Detected Error Bit Definitions + 1 Reserved + Format: MBZ + 0 Instruction Error + This bit is set when the Renderer Instruction Parser detects an error while parsing an instruction. + Instruction errors include: + + +  + Client ID value (Bits 31:29 of the Header) is not supported (only MI, 2D and 3D are supported). +  + Defeatured MI Instruction Opcodes: + + Value Name Description + 1 Instruction Error detected + + + Programming Notes + This error indications cannot be cleared except by reset (i.e., it is a fatal error). + + + + +1.1.6.3.1 VCS_EIR — Error Identity Register + + VCS_EIR - VCS Error Identity Register +Register Space: MMIO: 0/2/0 +Project: All +Source: VideoCS +Default Value: 0x00000000 +Access: R/WC +Size (in bits): 32 +Address: 120B0h + + +The EIR register contains the persistent values of Hardware-Detected Error Condition bits. Any bit set in this register +will cause the Master Error bit in the ISR to be set. The EIR register is also used by software to clear detected errors +(by writing a 1 to the appropriate bit(s) except for the unrecoverable bits described). +DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15:0 Error Identity Bits + Format: Array of Error condition bits ee the table titled Hardware-Detected Error Bits + + + This register contains the persistent values of ESR error status bits that are unmasked via the EMR + register. The logical OR of all (defined) bits in this register is reported in the Master Error bit of the + Interrupt Status Register. In order to clear an error condition, software must first clear the error by + writing a 1 to the appropriate bit(s) in this field. If required, software should then proceed to clear the + Master Error bit of the IIR. + Value Name Description + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 27 + VCS_EIR - VCS Error Identity Register + 0h [Default] + 1h Error occurred Error occurred + + + Programming Notes + Writing a 1 to a set bit will cause that error condition to be cleared. However, the Page Table Error bit + (Bit 4) cannot be cleared except by reset (i.e., it is a fatal error). + + + +1.1.6.3.2 VCS_EMR - VCS Error Mask Register + + VCS_EMR - VCS Error Mask Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x0000FFFF +Access: R/W +Size (in bits): 32 +Address: 120B4h + + +The EMR register is used by software to control which Error Status Register bits are “masked” or “unmasked”. +“Unmasked” bits will be reported in the EIR, thus setting the Master Error ISR bit and possibly triggering a CPU +interrupt, and will persist in the EIR until cleared by software. “Masked” bits will not be reported in the EIR and +therefore cannot generate Master Error conditions or CPU interrupts. + DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15:0 Error Mask Bits + Format: Array of error condition mask bits See the table titled Hardware-Detected Error Bits. + + + This register contains a bit mask that selects which error condition bits (from the ESR) are + reported in the EIR. + Value Name Description + FFFF FFFFh [Default] + 0h Not Masked Will be reported in the EIR + 1h Masked Will not be reported in the EIR + + + + +28 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.6.3.3 VCS_ESR - VCS Error Status Register + + VCS_ESR - VCS Error Status Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 120B8h + + +The ESR register contains the current values of all Hardware-Detected Error condition bits (these are all by definition +persistent). The EMR register selects which of these error conditions are reported in the persistent EIR (i.e., set bits +must be cleared by software) and thereby causing a Master Error interrupt condition to be reported in the ISR. + DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15:0 Error Status Bits + Format: Array of error condition bits See the table titled Hardware-Detected Error Bits. + + + This register contains the non-persistent values of all hardware-detected error condition bits. + Value Name Description + 0h [Default] + 1h Error Condition Detected Error Condition detected + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 29 + 1.1.7 Logical Context Support + +1.1.7.1 BB_ADDR—Batch Buffer Head Pointer Register + + BB_ADDR - Batch Buffer Head Pointer Register +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 02140h +Name: RCS Batch Buffer Head Pointer Register +ShortName: RCS_BB_ADDR +Address: 12140h +Name: VCS Batch Buffer Head Pointer Register +ShortName: VCS_BB_ADDR + + +Address: 1A140h +Name: VECS Batch Buffer Head Pointer Register +ShortName: VECS_BB_ADDR +Address: 22140h +Name: BCS Batch Buffer Head Pointer Register +ShortName: BCS_BB_ADDR +This register contains the current DWord Graphics Memory Address of the last-initiated batch buffer. + Programming Notes +Programming Restriction: This register should NEVER be programmed by driver. This is for HW internal use only. +DWord Bit Description +0 31:3 Batch Buffer Head Pointer + + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + Format: GraphicsAddress[31:3] + This field specifies the DWord-aligned Graphics Memory Address where the last initiated Batch Buffer is + currently fetching commands. If no batch buffer is currently active, the Valid bit will be 0 and this field will + be meaningless. + + 31:2 Batch Buffer Head Pointer + + Source: RenderCS + Format: GraphicsAddress[31:2] + This field specifies the DWord-aligned Graphics Memory Address where the last initiated Batch Buffer is + currently fetching commands. If no batch buffer is currently active, the Valid bit will be 0 and this field will + be meaningless. + + 2 Reserved + + + + +30 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + BB_ADDR - Batch Buffer Head Pointer Register + Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS + Format: MBZ + 1 Reserved + Format: MBZ + 0 Valid + Format: U1 + + + Value Name Description + 0h Invalid [Default] Batch buffer Invalid + 1h Valid Batch buffer Valid + + + +1.1.7.2 BB_STATE - Batch Buffer State Register + + BB_STATE - Batch Buffer State Register +Register Space: MMIO: 0/2/0 + + +Source: BlitterCS, VideoCS, VideoCS2, VideoEnhancementCS +Default Value: 0x00000000 [IVB:GT1] +Access: RO +Size (in bits): 32 +Address: 12110h +Name: VCS Batch Buffer State Register +ShortName: VCS_BB_STATE +Address: 1A110h +Name: VECS Batch Buffer State Register +ShortName: VECS_BB_STATE +Address: 22110h +Name: BCS Batch Buffer State Register +ShortName: BCS_BB_STATE + +This register contains the attributes of the current batch buffer initiated from the Ring Buffer. These include the +security indicator. + +This register should not be written by software. These fields should only get written by a context restore. Software +should always set these fields via the MI_BATCH_BUFFER_START command when initiating a batch buffer. + + This register is saved and restored with context. +DWord Bit Description +0 31:7 Reserved + Project: All + Format: MBZ + 6 2nd Level Buffer Security Indicator + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 31 + BB_STATE - Batch Buffer State Register + + Source: VideoCS, VideoCS2 + If set, VCS is fetching 2nd level batch commands from a PPGTT address space. If clear, GGTT. If clear, + this batch buffer is secure and will be accessed via the GGTT. + Value Name Description + 0h [Default] + 0h MIBUFFER_SECURE [Default] Located in GGTT memory + 1h MIBUFFER_NONSECURE Located in PPGTT memory + 6 Reserved + + Source: VideoCS, VideoCS2 + Format: MBZ + 6 Reserved + + Source: BlitterCS, VideoEnhancementCS + Format: MBZ + 5 1st Level Buffer Security Indicator + + Format: MI_1stBufferSecurityType + + If set, BCS is fetching 1st level batch commands from a PPGTT address space. If clear, GGTT. + It will be accessed via the PPGTT. If clear, + this batch buffer is secure and will be accessed via the GGTT. + Value Name Description + 0h MIBUFFER_SECURE [Default] Located in GGTT memory + 1h MIBUFFER_NONSECURE Located in PPGTT memory + 4 Reserved + Project: All + Source: BlitterCS + Format: MBZ + 3:0 Reserved + Project: All + Format: MBZ + + + + +1.1.8 Image Enhancement Registers +These registers contain the statistical data collected by Image Enhancement filters in Sampler (The +denoise, deinterlace and film mode detection filter block) and Render Cache (The color enhancement +filter block). + + + + +32 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.8.1 Denoise, Deinterlace and FMD Registers + + Image Enhancement MMIO Registers +Register MMIO: 0/2/0 +Space: + + +Source: VideoCS +Default 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +Access: RO +Size (in 26x32 +bits): +Trusted 1 +Type: +Address: 05000h + +Address Offset: + +05000h – 05028h: FMD Variances for Video Stream 0 + +0502Ch: GNE for Video Stream 0 + +05030h: Number of Valid GNE Blocks for Stream 0 + +05034h – 0505Ch: FMD Variances for Video Stream 1 + +05060h: GNE for Video Stream 1 + +05064h: Number of Valid GNE Blocks for Stream 1 + +The Denoise and Deinterlace features of Image Enhancement produce statistics across entire video frames for +driver control of these features. Each of the supported video streams has a separate set of registers. The registers' +contents are described in detail in Volume 5c Shared Functions, in the Deinterlacer and Denoise Filter section. + + These registers are reset to zero when the read completes. + DWord Bit Description +0 31:0 FMD Variance[0] for Video Stream 0 + (For details, refer to the Simple Differences section in Volume 5c Shared Functions.) +1 31:0 FMD Variance[1] for Video Stream 0 +2 31:0 FMD Variance[2] for Video Stream 0 +3 31:0 FMD Variance[3] for Video Stream 0 +4 31:0 FMD Variance[4] for Video Stream 0 +5 31:0 FMD Variance[5] for Video Stream 0 +6 31:0 FMD Variance[6] for Video Stream 0 +7 31:0 FMD Variance[7] for Video Stream 0 +8 31:0 FMD Variance[8] for Video Stream 0 +9 31:0 FMD Variance[9] for Video Stream 0 +10 31:0 FMD Variance[10] for Video Stream 0 +11 31:0 GNE Sum for Video Stream 0 + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 33 + Image Enhancement MMIO Registers + (For details, refer to the Block Noise Estimate section in Volume 5c Shared Functions.) +12 31:0 GNE Count for Video Stream 0 +13 31:0 FMD Variance[0] for Video Stream 1 + (For details, refer to the Simple Differences section in Volume 5c Shared Functions.) +14 31:0 FMD Variance[1] for Video Stream 1 +15 31:0 FMD Variance[2] for Video Stream 1 +16 31:0 FMD Variance[3] for Video Stream 1 +17 31:0 FMD Variance[4] for Video Stream 1 +18 31:0 FMD Variance[5] for Video Stream 1 +19 31:0 FMD Variance[6] for Video Stream 1 +20 31:0 FMD Variance[7] for Video Stream 1 +21 31:0 FMD Variance[8] for Video Stream 1 +22 31:0 FMD Variance[9] for Video Stream 1 +23 31:0 FMD Variance[10] for Video Stream 1 +24 31:0 GNE Sum for Video Stream 1 + (For details, refer to the Block Noise Estimate section in Volume 5c Shared Functions.) +25 31:0 GNE Count for Video Stream 1 + + + +1.1.8.2 Color Enhancement Registers + + Color Enhancement Registers +Register MMIO: 0/2/0 +Space: + + +Source: VideoCS +Default 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000 +Access: RO +Size (in 48x32 +bits): +Trusted 1 +Type: +Address: 05000h + +Address Offset: + +05080h: ACE Histogram Bin 0 (bits 15:0), Bin 1 (bits 31:16) + +05084h to 517c: ACE Histogram Bins 2 through 127 (even bins in bits 15:0, odd bins in bits 31:16) + + + +34 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + Color Enhancement Registers +05070h: Skin Data Ymax (bits 25:16), Ymin (bits 9:0), other bits zero + +05074h: Number of skin pixels (bits 20:0, other bits zero) + + These registers are reset to zero when the read completes. + DWord Bit Description +0 31:16 ACE Histogram Bin 1 + 15:0 ACE Histogram Bin 0 +1..63 31:0 ACE Histogram Bins 2 through 127 + (even bins in bits 15:0, odd in 31:16) +64 31:26 Reserved + Format: MBZ + 25:16 Skin Data Ymax + 15:10 Reserved + Format: MBZ + 9:0 Skin Data Ymin + + + + +1.1.9 Registers in Media Engine + +1.1.9.1 Introduction +This chapter describes the memory-mapped registers associated with the Memory Interface, including +brief descriptions of their use. The functions performed by some of these registers are discussed in more +detail in the Memory Interface Functions, Memory Interface Instructions, and Programming Environment +chapters. + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 35 + 1.1.9.2 GAC PWR CTX STORAGE REGISTERS + +1.1.9.2.1 GFX_PEND_TLB – Max Outstanding Media pending TLB requests + + GFX_PEND_TLB - TLBPEND Control Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 14040h +Max Outstanding Media pending TLB requests +DWord Bit Description +0 30 Reserved + Format: MBZ + 29:24 VMX BS Limit Count + Format: U6 + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + 23 VMC Limit Enable bit + Format: U1 + + This bit is used to enable the pending TLB requests limitation function for the VMC. + + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + 22 Reserved + Format: MBZ + 21:16 VMC TLB Limit Count + Format: U6 + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + 15 VMXRS Limit Enable bit + Format: U1 + + This bit is used to enable the pending TLB requests limitation function for the VMX Row store. + + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + 14 Reserved + Format: MBZ + 13:8 VMX RS Random Accsess TLB Limit Count + Format: U6 + + + + +36 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + GFX_PEND_TLB - TLBPEND Control Register + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + 7 VCS Limit Enable bit + Format: U1 + + This bit is used to enable the pending TLB requests limitation function for the Command Streamer. + + When set, the number of internal pending read requests which require a TLB read will not exceed the + programmed counter value. + + 6 Reserved + Format: MBZ + 5:0 VCS TLB Limit Count + Format: U6 + This is the MAX number of Allowed internal pending read requests which require a TLB read. + + + + +1.1.9.2.2 GAC_ARB_CTL_REG - GAC_GAB Arbitration Counters Register 1 + + GAC_ARB_CTL_REG - GAC_GAB Arbitration Counters Register 1 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00400002 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 14050h +GAC_GAB R/RO/W Arbitration Control Register +DWord Bit Description +0 31 GAC write request Limit Enable + Format: U1 + As long As there is no conflict between GAC and GAB ,GAC will alow whoever shows up (if media + present and no GAB, let meda and vice versa). If both are present, start counting and switch when + programmable no of request is expired. Allow only One GAB request and reset the counter. Counter + only counts while we service a particular client and another client is present, else counter will reset. + + 30 VLF Final write Limit Enable + Format: MBZ + As long as there is no conflict Between VCS MFD and VLF Final Write, GAC will allow whoever shows + up (if VLF present and no VCSMFD, Let VLF and vice versa). If both are present, Start counting and + when programmable no of request is expired. Allow only One VCSMFD request And counter will reset. + Counter only counts while we service a particular client and another client is present, else counter will + reset. + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 37 + GAC_ARB_CTL_REG - GAC_GAB Arbitration Counters Register 1 + 29:24 Write Req Limit Count + Format: U6 + The value programmed determines the number of GAC/VLF Writes will allow for Each time. + + 23 GAC/GAB Cascaded Read Only Limit Enable + Format: U1 + As long as there is no conflict between GAC and GAB Read Requests, GAC will allow whoever shows + up (if GAC present and no GAB, Let GAC and vice versa). If both are present, Start counting and + switch when programmable no of request from either side is expired (reset the counter when switch). + Counter only counts while we service a particular client and other client is present, else counter will + reset. + + 22 Fixed Priority Setting + Format: MBZ + Once programmable counter is disabled, GAC uses the fixed arbitration setting given in this register + setting. + Value Name + 0 GAC + 1 GAB [Default] + 21 Reserved + Format: MBZ + 20:16 GAC/GAB Read Only Limit Counter Value + Format: U6 + This is the Maximum number of Read requests Allowed from Each Cascaded Agent. Default 0 + + 15 GAC/GAB Cascaded Read Limit Enable + Format: U1 + + + As long as there is no conflict Between GAC and GAB Read Only Requests, GAC will allow whoever + shows up (if GAC present and no GAB, Let GAC and vice versa). If both are present, Start counting + and switch when programmable no of request from either side is expired (reset the counter when + switch). Counter only counts while we service a particular client and other client is present, else + counter will reset. + Default 0 + 14 Default priority 0-GAC, 1-GAB + Format: MBZ + Default 0 + + 13 Reserved + Format: MBZ + 12:8 GAC/GAB Read Limit Counter Value + Format: U6 + This is the Maximum number of Read requests allowed from Each Cascaded Agent. + + 7:6 Reserved + Format: MBZ + 5:0 No of Global GTT Entries Valid in PPGTT mode in TLB064 + + + + +38 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + GAC_ARB_CTL_REG - GAC_GAB Arbitration Counters Register 1 + Default Value: 000010b + Format: U6 + Minimum value the PPGGTT LRA can have (effectively partitioning the TLB between PPGTT and + GGTT). Currently, only 2 entries are allocated to GGTT in ASmodel. TLB64 is shared by GGTT and + PPGTT entries, are 2 LRAs, the GGTT one running from 0 up to PPGTT_MIN -1 (which is 2, but could + be changed if needed), and the PPGTT one running from PPGTT_MIN up to 63. + + + + +1.1.9.3 GFX TLB In Use Virtual Address Registers + +1.1.9.3.1 TLB064_VA — Virtual Page Address Registers + + TLB064_VA - TLB064_VA Virtual Page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 14800h-148FCh +This register is directly mapped to the current Virtual Addresses in the TLB064 (VCS and VMC TLB). + DWord Bit Description +0 31:12 Address + Format: GraphicsAddress[31:12] + Page virtual address. + + 11:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 39 + 1.1.9.3.2 TLB132_VA — Virtual Page Address Registers + + TLB132_VA - TLB132_VA Virtual Page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 14900h-149FCh +These registers are directly mapped to the current Virtual Addresses in the TLB132 (All The Media Clients TLB). +Default Value = UUUUUUUUh Trusted Type = 1 + DWord Bit Description +0 31:12 Address + Format: GraphicsAddress[31:12] + Page virtual address. + + 11:0 Reserved + Format: MBZ + + + +1.1.9.3.3 TLB232_VA — Virtual Page Address Registers + + TLB232_VA - TLB232_VA Virtual Page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 14A00h-14AFCh +This register is directly mapped to the current Virtual Addresses in the TLB232 (VDS and VLF FW TLB). + DWord Bit Description +0 31:12 Address + Format: GraphicsAddress[31:12] + Page virtual address. + + 11:0 Reserved + Format: MBZ + + + + +40 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.9.3.4 TLB304_VA — Virtual Page Address Registers + + TLB304_VA - TLB304_VA Virtual Page Address Registers +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 14B00h-14BFCh +This register is directly mapped to the current Virtual Addresses in the TLB304 (VCR TLB). + DWord Bit Description +0 31:12 Address + Format: GraphicsAddress[31:12] + Page virtual address. + + 11:0 Reserved + Format: MBZ + + + +1.1.9.3.5 TLB064_VLD — Valid Bit Vector 0 for TLB + + MTTLB064_VLD0 - Valid Bit Vector 0 for TLB064 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 14780h-14783h +This register contains the valid bits for entries 0-31 of MTTLB (Texture and constant cache TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 41 + 1.1.9.3.6 TLB064_VLD — Valid Bit Vector 1 for TLB + + MTTLB064_VLD1 - Valid Bit Vector 1 for TLB064 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 14784h-14787h +This register contains the valid bits for entries 0-31 of MTTLB (Texture and constant cache TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + +1.1.9.3.7 TLB132_VLD — Valid Bit Vector 0 for TLB + + MTTLB132_VLD0 - Valid Bit Vector 0 for TLB132 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 14788h-1478Bh +This register contains the valid bits for entries 0-31 of MTTLB (Texture and constant cache TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + + +42 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.9.3.8 TLB132_VLD — Valid Bit Vector 1 for MTTLB + + MTTLB132_VLD1 - Valid Bit Vector 1 for TLB132 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 1478Ch-1478Fh +This register contains the valid bits for entries 0-31 of MTTLB (Texture and constant cache TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + +1.1.9.3.9 TLB232_VLD — Valid Bit Vector 0 for TLB + + MTTLB232_VLD0 - Valid Bit Vector 0 for TLB232 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 14790h-14793h +This register contains the valid bits for entries 0-31 of MTTLB (Texture and constant cache TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 43 + 1.1.9.3.10 TLB232_VLD — Valid Bit Vector 1 for MTTLB + + MTTLB232_VLD1 - Valid Bit Vector 1 for TLB232 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 14794h-14797h +This register contains the valid bits for entries 0-31 of MTTLB (Texture and constant cache TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + +1.1.9.3.11 TLB304_VLD — Valid Bit Vector 0 for TLB304 + + MTTLB304_VLD0 - Valid Bit Vector 0 for TLB304 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 14798h-1479Bh +This register contains the valid bits for entries 0-31 of MTTLB (Texture and constant cache TLB). + DWord Bit Description +0 31:0 Valid bits per entry + + + + +44 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.9.3.12 TLB304_VLD — Valid Bit Vector 1 for TLB304 + + MTTLB304_VLD1 - Valid Bit Vector 1 for TLB304 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 1479Ch-1479Fh +This register contains the valid bits for entries 0-31 of MTTLB (Texture and constant cache TLB). Default Value = +00000000h Trusted Type = 1 + DWord Bit Description +0 31:0 Valid bits per entry + + + +1.1.9.4 GFX Pending TLB Cycles Information Registers +The following registers contain information about cycles that did not complete their TLB translation. +Information is organized as 64 entries, where each entry has a valid and ready bit, collapsed into +separate registers. + +1.1.9.4.1 VCS_TLBPEND_VLD0 - VCS Valid Bit Vector 0 for TLBPEND Registers + + VCS_TLBPEND_VLD0 - VCS Valid Bit Vector 0 for TLBPEND + Registers +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 14700h-14703h +This register contains the valid bits for entries 0-31 of TLBPEND structure (Cycles pending TLB translation). + DWord Bit Description +0 31:0 Valid bits per entry + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 45 + 1.1.9.4.2 VCS_TLBPEND_VLD1 - VCS Valid Bit Vector 1 for TLBPEND Registers + + VCS_TLBPEND_VLD1 - VCS Valid Bit Vector 1 for TLBPEND + Registers +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 14704h-14707h +This register contains the valid bits for entries 32-63 of TLBPEND structure (Cycles pending TLB translation). + DWord Bit Description +0 31:0 Valid bits per entry + + + +1.1.9.4.3 VCS_TLBPEND_RDY0 - VCS Ready Bit Vector 0 for TLBPEND Registers + + VCS_TLBPEND_RDY0 - VCS Ready Bit Vector 0 for TLBPEND + Registers +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 14708h-1470Bh +This register contains the ready bits for entries 0-31 of TLBPEND structure (Cycles pending TLB translation). + DWord Bit Description +0 31:0 Ready bits per entry + + + + +46 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.1.9.4.4 VCS_TLBPEND_RDY1 - VCS Ready Bit Vector 1 for TLBPEND Registers + + VCS_TLBPEND_RDY1 - VCS Ready Bit Vector 1 for TLBPEND + Registers +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 1470Ch-1470Fh +This register contains the ready bits for entries 32-63 of TLBPEND structure (Cycles pending TLB translation). + DWord Bit Description +0 31:0 Ready bits per entry + + + +1.1.9.4.5 VCS_TLBPEND_SEC0 - VCS Section 0 of TLBPEND Entry + + VCS_TLBPEND_SEC0 - VCS Section 0 of TLBPEND Entry +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 14400h-144FCh +This register is directly mapped to the TLBPEND Array in the Graphic Arbiter. +DWord Bit Description +0 31 vtstatus + This bit will be used in conjunction with the ready bit to determine the stage of the translation. See table + below. + 30:28 GTT bits + Bits 3:1 of the GTT entry used to translate the Virtual Address. 000 if translation is pending. + 27:0 Current address + + The value of this field depends on the stage of the TLB translation for this entry: + + VA – bits 27:20 = 00, bits 19:0 = Bits 31:12 of the Virtual Address of the cycle. + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 47 + VTDMODE Meaning + Val Ready Vtstatus + id + +DC 0 DC DC Entry is invalid +0 1 0 0 Entry was a TLB miss. Waiting for TLB translation. +0 1 0 1 Entry was a Hit not present. Waiting for TLB translation from a previous + miss. +0 1 1 0 Not possible +0 1 1 1 TLB translation complete. Entry ready +1 1 0 0 Entry was a TLB miss. Waiting for TLB translation. +1 1 0 1 Entry was a Hit not present. Waiting for TLB translation from a previous + miss. +1 1 1 0 GPA translation complete. Entry ready for VTD translation. +1 1 1 1 TLB translation complete. Entry ready + + +1.1.9.4.6 TLBPEND_SEC1 — Section 1 of TLBPEND Entry + + VCS_TLBPEND_SEC1 - VCS Section 1 of TLBPEND Entry +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 14500h-145FCh +This register is directly mapped to the current Virtual Addresses in the MTTLB (Texture and constant cache TLB). +DWord Bit Description +0 31:28 Current address + Bits 9:6 of the Virtual Address of the cycle. + 27:24 Cacheability Control Bits + 2 Graphics Data + Type (GFDT) + This field contains the GFDT bit for this surface when writes occur. GFDT can also + be set by the GTT. The effective GFDT is the logical OR of this field with the GFDT + from the GTT entry. This field is ignored for reads. + 1:0 Cacheability + Control + This field controls cacheability in the mid-level cache (MLC) and last-level cache + (LLC). + 00: use cacheability control bits from GTT entry + 01: data is not cached in LLC or MLC + 10: data is cached in LLC but not MLC + 11: data is cached in both LLC and MLC + 23 ZLR bit + Flag to indicate this is a zero length read (A read used to calculate a Physical Address for a write). + 22:4 TAG + Cycle identification TAG. + 3:0 SRC ID + + + +48 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + VCS_TLBPEND_SEC1 - VCS Section 1 of TLBPEND Entry + Encoding of unit generating this cycle + Constant Value + SRCID + VCS_RD_SRCID “00000” + VMC_RD_SRCID “00001” + VMX_RARD_SRCID “00010” + VMX_BSRD_SRCID “00011” + VMX_RSRD_SRCID “00100” + VIP_RD_SRCID “00101” + VLF_RD_SRCID “00110” + VDS_ZLRD_SRCID “00111” + VCS_WR_SRCID “01000” + VMX_BSWR_SRCID “01001” + VDS_WR_SRCID “01010” + VOP_WR_SRCID “01011” + VLF_RSWR_SRCID “01100” + VLF_FDWR_SRCID “01101” + VMX_RSWR_SRCID “01110” + BSP_WR_SRCID “01111” + VCR_RD_SRCID “10001” + VCR_WR_SRCID “10010” + VCS_RD_PROBE “10011” + + + +1.1.9.4.7 VCS_TLBPEND_SEC2 - VCS Section 2 of TLBPEND Entry + + VCS_TLBPEND_SEC2 - VCS Section 2 of TLBPEND Entry +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 14600h-146FCh +This register is directly mapped to the current Virtual Addresses in the MTTLB (Texture and constant cache TLB). + DWord Bit Description +0 31:11 Reserved + 10:8 Current address + Bits 11:9 of the Virtual Address of the cycle. + 7:0 PAT entry + Location of Physical Address in Physical Address Table. + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 49 + 1.1.9.5 VCS_TIMESTAMP - VCS Reported Timestamp Count + + VCS_TIMESTAMP - VCS Reported Timestamp Count +Register Space: MMIO: 0/2/0 +Project: All +Source: VideoCS +Default Value: 0x00000000, 0x00000000 +Access: RO. This register is not set by the context restore. +Size (in bits): 64 +Address: 12358h + + +This register provides an elapsed real-time value that can be used as a timestamp. This register is not reset by a +graphics reset. It will maintain its value unless a full chipset reset is performed. + Note: This timestamp register reflects the value of the PCU TSC. The PCU TSC counts 10ns increments; this +timestamp reflects bits 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5 hours). + DWord Bit Description +0 63:36 Reserved + Format: MBZ + 35:0 Timestamp Value + Format: U32 + + This register toggles every 80 ns. The upper 28 bits are zero. + + + + +1.2 Memory Interface Commands for Video Codec Engine + +1.2.1 Introduction +This chapter describes the formats of the “Memory Interface” commands, including brief descriptions of +their use. The functions performed by these commands are discussed fully in the Memory Interface +Functions Device Programming Environment chapter. +This chapter describes MI Commands for the Video Codec Engine. +The commands detailed in this chapter are used across the later products within the architecture. +However, slight changes may be present in some commands (i.e., for features added or removed), or +some commands may be removed entirely. Refer to the Preface chapter for details. + + + + +50 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.2.2 MI_ARB_CHECK + + MI_ARB_CHECK +Project: All +Source: VideoCS +Length Bias: 1 +The MI_ARB_CHECK is used to check for a change in arbitration. If executed as part of a Ring Buffer the command +checks the UHPTR valid bit and if set the head of the ring will jump to the value of the head pointer programmed in +the UHPTR. + Programming Notes +This instruction cannot be placed in a batch buffer. + DWord Bit Description +0 31:29 MI Instruction Type + Default Value: 0h MI_INSTRUCTION + Format: OpCode + 28:23 MI Instruction Opcode + Default Value: 05h MI_ARB_CHECK + Format: OpCode + 22:0 Reserved + Format: MBZ + + + + +1.2.3 MI_ARB_ON_OFF + + MI_ARB_ON_OFF + +Source: VideoCS +Length Bias: 1 +The MI_ARB_ON_OFF instruction is used to disable/enable context switching. Note that context switching will +remain disabled until re-enabled through use of this command. This command will also prevent a switch in the case +of running out of commands. This will effectively hang the device if allowed to occur while arbitration is off (context +switching is disabled.) This command should always be used as an off-on pair with the sequence of instructions to be +protected from context switch between MI_ARB_OFF and MI_ARB_ON. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 08h MI_ARB_ON_OFF + 22:1 Reserved + Format: MBZ + 0 Arbitration Enable + Format: Enable + This field enables or disables context switches due to pre-emption. + Value Name + 0h Disabled + 1h Enabled + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 51 + 1.2.4 MI_BATCH_BUFFER_END +The MI_BATCH_BUFFER_END command format follows: + + MI_BATCH_BUFFER_END +Project: All +Source: VideoCS +Length Bias: 1 +The MI_BATCH_BUFFER_END command is used to terminate the execution of commands stored in a batch buffer +initiated using a MI_BATCH_BUFFER_START command. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 0Ah MI_BATCH+_BUFFER_END + Format: OpCode + 22:0 Reserved + Format: MBZ + + + + +1.2.5 MI_CONDITIONAL_BATCH_BUFFER_END + + MI_CONDITIONAL_BATCH_BUFFER_END + +Source: VideoCS +Length Bias: 2 +The MI_BATCH_BUFFER_END command is used to conditionally terminate the execution of commands stored in a +batch buffer initiated using a MI_BATCH_BUFFER_START command. + Programming Notes +This command is only valid with a 1st level batch buffer (bit 22 in MI_BATCH_BUFFER_START is set to 0). +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 36h MI_CONDITIONAL_BATCH_BUFFER_END + 22 Use Global GTT + Default Value: 0h DefaultVaueDesc + Format: U1 + Format: U1 FormatDesc + + + If set, this command will use the global GTT to translate the Compare Address and this command must + be executing from a privileged (secure) batch buffer. If clear, the PPGTT will be used to translate the + Compare Address. + + + + +52 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + MI_CONDITIONAL_BATCH_BUFFER_END + + 21 Compare Semaphore + Default Value: 0h DefaultVaueDesc + Format: U1 + If set, the value from the Compare Data Dword is compared to the value from the Compare Address in + memory. If the value at Compare Address is greater than the Compare Data Dword, execution of + current command buffer should continue.If clear, no comparison takes place. + + 19:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Format: =n Total Length - 2 + + + +1 31:0 Compare Data Dword + Data dword to compare memory. The Data dword is supplied by software to control execution of the + command buffer. If the compare is enabled and the data at Semaphore Address is greater than this + dword, the execution of the command buffer should continue. +2 31:3 Compare Address + Qword address to fetch compare Mask (DW0) and Data Dword(DW1) from memory. HW will do AND + operation on Mask(DW0) with Data Dword(DW1) and then compare the result against Semaphore Data + Dword + 2:0 Reserved + Format: MBZ + + + + +1.2.6 MI_BATCH_BUFFER_START +The MI_BATCH_BUFFER_START command format follows: + + MI_BATCH_BUFFER_START + +Source: VideoCS +Length Bias: 2 +The MI_BATCH_BUFFER_START command is used to initiate the execution of commands stored in a batch buffer. +For restrictions on the location of batch buffers, see Batch Buffers in the Device Programming Interface chapter of MI +Functions.The batch buffer can be specified as secure or non-secure, determining the operations considered valid +when initiated from within the buffer and any attached (chained) batch buffers. See Batch Buffer Protection in the +Device Programming Interface chapter of MI Functions. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 31h MI_BATCH_BUFFER_START + Format: OpCode + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 53 + MI_BATCH_BUFFER_START + 22 2nd Level Batch Buffer + + The command streamer contains 3 storage elements; 1 for the ring head address, 1 for the batch head + address, and 1 for the 2nd level batch head address. When performing batch buffer chaining, hardware + simply updates the head pointer of the 1st level batch address storage. There is no stack in hardware. + When this bit is set, hardware uses the 2nd level batch head address storage element. Upon + MI_BATCH_BUFFER_END, it will automatically return to the 1st (traditional) level batch buffer address. + this allows hardware to mimic a simple 3 level stack. + Value Name Description + 0h 1st level Place the batch buffer address in the 1st (traditional) level batch address storage + batch element + 1h 2nd level Place the batch buffer address in the 2nd level batch address storage element + batch + + + Programming Notes +  A non-secure 2nd level batch buffer cannot be called from a non-secure 1st(traditional) level + batch buffer. +  2nd level batch buffer chaining is not supported. + + 21:10 Reserved + Format: MBZ + 8 Address Space Indicator + + Format: U32 + Format: MI_BufferSecurityType + + + Certain operations (e.g., MI_STORE_DATA_IMM commands to privileged memory) are prohibited + within non-secure buffers. See Batch Buffer Protection in the Device Programming Interface chapter of + MI Functions. The command streamer will not allow a batch buffer in PPGTT to call a batch buffer in + GGTT space by retaining the PPGTT value. It is illegal for the driver to program the value of this field + to a different value than the current batch buffer executing this command. + This field must be 0 unless the Per-Process GTT Enable is 1. + + + Value Name + 0 MIBUFFER_SECURE (GGTT space) + 1 MIBUFFER_NONSECURE (PPGTT space) + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Format: =n Total Length - 2 + + + +1 31:2 Buffer Start Address + Format: GraphicsAddress[31:2] + + + Programming Notes +  A batch buffer initiated with this command must end either with a MI_BATCH_BUFFER_END + + + + +54 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + MI_BATCH_BUFFER_START + command or by chaining to another batch buffer with an MI_BATCH_BUFFER_START + command. +  The selection of PPGTT vs. GGTT for the batch buffer is determined by the Buffer Security + Indicator (bit8). + + 1:0 Reserved + Format: MBZ + + + + +1.2.7 MI_FLUSH_DW + + MI_FLUSH_DW +Project: All +Source: VideoCS +Length Bias: 2 +The MI_FLUSH_DW command is used to perform an internal “flush” operation. The parser pauses on an internal +flush until all drawing engines have completed any pending operations. In addition, this command can also be used +to:Flush any dirty data to memory. Invalidate the TLB cache inside the hardware Usage note: After this command is +completed with a Store DWord enabled, CPU access to graphics memory will be coherent (assuming the Render +Cache flush is not inhibited). + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 26h MI_FLUSH_DW + 21 Store Data Index + + Format: U1 + This field is valid only if the post-sync operation is not 0. If this bit is set, the store data address is + actually an index into the hardware status page. + If this bit is set, this command will index into the per-process hardware status page if executed from + within a non-secure batch buffer and if the Per-Process Virtual Address Space is set. Else the Global + HW status page is used. + + 20:19 Reserved + Format: MBZ + 18 TLB Invalidate + + Format: U1 + + + Description Project + If ENABLED, all TLBs will be invalidated once the flush operation is complete. This bit is only + valid when the Post-Sync Operation field is a value of 1h or 3h. + If GFX_MODE(0x229c) bit 13, this command will cause a config write to MMIO register space + with the address 0x4f100. + 17 Synchronize GFDT surface + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 55 + MI_FLUSH_DW + + Format: U1 + If enabled, at the end of the current flush the last level cache is cleared of all the cachelines which + have been marked with the special GFDT flags. Store DW must be enabled + + 16 Reserved + Format: MBZ + 15:14 Post-Sync Operation + + BitFieldDesc + Value Name Description Project + 0h No write occurs as a result of this instruction. This can be used to implement a + “trap” operation, etc. + 1h Write the QWord containing Immediate Data Low, High DWs to the Destination + Address + 2h Reserved + 3h Write the TIMESTAMP register to the Destination Address with a granularity of + 80ns. + The upper 28 bits of the TIMESTAMP register are tied to ‘0’. + + + Programming Notes + + + 13:9 Reserved + Format: MBZ + 8 Notify Enable + Project: + Format: U1 + If ENABLED, a Sync Completion Interrupt will be generated (if enabled by the MI Interrupt Control + registers) once the sync operation is complete. See Interrupt Control Registers in Memory Interface + Registers for details. + + 7 Video Pipeline Cache invalidate + + Format: U1 + Enable the invalidation of the video cache at the end of this flush + + 5:0 DWord Length + Format: =n Total Length - 2 + + + + + Value Name Project + 2h Excludes DWord (0,1) = 1 for DWord, 2 for QWord [Default] +1 31:3 Address + Format: GraphicsAddress[31:3]U28 + This field specifies Bits 31:3 of the Address where the DWord or QWord will be stored. Note that the + address can only be QWord aligned, irrespective of data size. + + + + +56 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + MI_FLUSH_DW + + 2 Destination Address Type + Defines address space of Destination Address + Value Name Description + 0h PPGTT Use PPGTT address space for DW write + 1h GGTT Use GGTT address space for DW write + + + Programming Notes + Ignored if “No write” is the selected in Operation. + 1:0 Reserved + Format: MBZ +2..3 31:0 Immediate Data + + Format: U64 + + + This field specifies the DWord value to be written to the targeted location. DW2 is the lower DW if + QW is desired. Only valid when 15:14 in header is set to 1h + To avoid hitting a known hardware bug, drivers cannot send a QW write when bit 5 of the address is + ‘1’ + + + Value Name + [0,FFFFFFFFh] + + + + +1.2.8 MI_LOAD_REGISTER_IMM +The MI_LOAD_REGISTER_IMM command format is: + + MI_LOAD_REGISTER_IMM +Project: All +Source: VideoCS +Length Bias: 2 +The MI_LOAD_REGISTER_IMM command requests a write of up to a DWord constant supplied in the command to +the specified Register Offset (i.e., offset into Memory-Mapped Register Range). The register is loaded before the +next command is executed. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 22h MI_LOAD_REGISTER_IMM + Format: OpCode + 22:12 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 57 + MI_LOAD_REGISTER_IMM + 11:8 Byte Write Disables + Format: Enable[4] (bit 8 corresponds to Data DWord [7:0]). + + + + + Range: Must specify a valid register write operation + If [11:8] is '1111b', then the register write will not occur. + If [11:8] is '0000b', then the register DW will be updated. + Any other value, the behavior will be specifically specified by the register or the behavior is + undefined. + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Format: =n Total Length - 2 + + + +1 31:23 Reserved + Format: MBZ + 22:2 Register Offset + Format: MmioAddress[22:2] + This field specifies bits [22:2] of the offset into the Memory Mapped Register Range (i.e., this field + specifies a DWord offset).Mapped + + 1:0 Reserved + Format: MBZ +2 31:0 Data DWord + Format: U32 FormatDesc + + + This field specifies the DWord value to be written to the targeted location. + + + + +58 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.2.9 MI_NOOP +The MI_NOOP command format is: + + MI_NOOP +Project: All +Source: VideoCS +Length Bias: 1 +The MI_NOOP command basically performs a “no operation” in the command stream and is typically used to pad the +command stream (e.g., in order to pad out a batch buffer to a QWord boundary). However, there is one minor +(optional) function this command can perform – a 22-bit value can be loaded into the MI NOPID register. This +provides a general-purpose command stream tagging ("breadcrumb") mechanism (e.g., to provide sequencing +information for a subsequent breakpoint interrupt). + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 00h MI_NOOP + Format: OpCode + 22 Identification Number Register Write Enable + Format: Enable + This field enables the value in the Identification Number field to be written into the MI NOPID + register. If disabled, that register is unmodified – making this command an effective “no operation” + function. + Value Name + 1 Write the NOP_ID register. + 21:0 Identification Number + Format: U22 + This field contains a 22-bit number which can be written to the MI NOPID register. + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 59 + 1.2.10 MI_SEMAPHORE_MBOX + + MI_SEMAPHORE_MBOX + +Source: VideoCS +Length Bias: 2 + Description Project + + This command is provided as alternative to MI_SEMAPHORE to provide mailbox-type semaphores where + there is no update of the semaphore by the checking process (the consumer). Single-bit compare-and- + update semantics are also provided. In either case, atomic access of semaphores need not be guaranteed + by hardware as with the previous command. This command should eventually supersede the previous + command. + + Synchronization between contexts (especially between contexts running on 2 different engines) is provided + by the MI_SEMAPHORE_MBOX command. Note that contexts attempting to synchronize in this fashion + must be able to access a common memory location. This means the contexts must share the same virtual + address space (have the same page directory), must have a common physical page mapped into both of + their respective address spaces, or the semaphore commands must be executing from a secure batch + buffer or directly from a ring with the Use Global GTT bit set such that they are “privileged” and will use the + (always shared) global GTT.MI_SEMAPHORE with the Update Semaphore bit set (and the Compare + Semaphore bit clear) implements the Signal command, while the Wait command is indicated by Compare + Semaphore being set. Note that Wait can cause a context switch. Signal increments unconditionally. + + If execution is stalled due to this command, the engine will specify that the engine is IDLE to the power + management engine. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 16h MI_SEMAPHORE_MBOX + 22 Use Global GTT + Format: U1 + If set, this command will use the global GTT to translate the Semaphore Address and this command + must be executing from a privileged (secure) batch buffer. If clear, the PPGTT will be used to translate + the Semaphore Address. This bit will be ignored (and treated as if clear) if this command is executed + from a non-privileged batch buffer. It is allowed for this bit to be clear when executing this command + from a privileged (secure) batch buffer or directly from a ring buffer. + Programming Notes + This field is only valid when Compare Register Field is reset. + 21 Update Semaphore + Format: U1 + If set, the value from the Semaphore Data Dword is written to memory. If Compare Semaphore is also + set, the semaphore is not updated if the semaphore comparison fails. If clear, the data at Semaphore + Address is not changed. + Programming Notes + This field should be always clear when Compare Register Field is set. + 20 Compare Semaphore + Format: U1 + If set, the value from the Semaphore Data Dword is compared to the value from the Semaphore + Address in memory when Compare Register is clear. If set, the value from the Semaphore Data + + + + +60 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + MI_SEMAPHORE_MBOX + Dword is compared to the value from MMIO Register selected by Register Select field when + Compare Register is set. If the value at Semaphore Address/MMIO Register is greater than the + Semaphore Data Dword, execution is continued from the current command buffer. If clear, no + comparison takes place. Update Semaphoremust be set in this case. + + 19 Reserved + Format: MBZ + 18 Compare Register + + Format: Compare Type + If set, data in MMIO register will be used for compare. If clear, data in memory will be used for + compare. + Programming Notes + Compare Register field should be always set. + 17:16 Register Select + + Format: Register Select + If compare register is set in bit[18], this field indicates which register will be used. + Value Name + 0 BCS register (VBSYNC) + 2 CS register (VRSYNC) + 3 Reserved + 15:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Format: =n Total Length - 2 + + + +1 31:0 Semaphore Data Dword + Format: U32 + Data dword to compare/update memory. The Data dword is supplied by software to control execution + of the command buffer. If the compare is enabled and the data at Semaphore Address is greater than + this dword, the execution of the command buffer continues. + +2 31:2 PointerBitFieldName/MMIO Register Address + Format: GraphicsVirtualAddress[31:2]Semaphore + if Compare Register bit[18] is cleared, this field if the Graphics Memory Address of the 32 bit value for + the semaphore. If Compare Register bit[18] is set, this field is the MMIO address of the register for the + semaphore. + + 1:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 61 + 1.2.11 MI_STORE_REGISTER_MEM + + MI_STORE_REGISTER_MEM +Project: All +Source: VideoCS +Length Bias: 2 +The MI_STORE_REGISTER_MEM command requests a register read from a specified memory mapped register +location in the device and store of that DWord to memory. The register address is specified along with the command +to perform the read. + Programming Notes +  The command temporarily halts command execution. +  The memory address for the write is snooped on the host bus. +  This command will cause undefined data to be written to memory if given register addresses for the + PGTBL_CTL_0 or FENCE registers + +The following addresses should NOT be used for SRMs + 1. 0x8800 - 0x88FF + 2. >= 0x40000 +The only exception is an SRM cycle to 0x40000-0xBFFFF when used as part of the LRI read-after-write requirement. + +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 24h MI_STORE_REGISTER_MEM + 22 Use Global GTT + This bit must be ‘1’ if the Per Process GTT Enable bit is clear. + Value Name Description + 0h Per Process + Graphics Address + 1h Global Graphics This command will use the global GTT to translate the Address and this + Address command must be executing from a privileged (secure) batch buffer. + + + Programming Notes Project + This will not be ignored when in a PPGTT batch buffer. + 21:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 1h Excludes DWord (0,1) + Format: =n Total Length - 2 + + + +1 31:23 Reserved + + Format: MBZ + 22:2 Register Address + Format: MMIOAddress[22:2]MMIO_Register + This field specifies Bits 22:2 of the Register offset the DWord will be read from. As the register address + + + + +62 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + MI_STORE_REGISTER_MEM + must be DWord-aligned, Bits 1:0 of that address MBZ. + Programming Notes + Storing a VGA register is not permitted and will store an UNDEFINED value. + The values of PGTBL_CTL0 or any of the FENCE registers cannot be stored to memory; UNDEFINED + values will be written to memory if the addresses of these registers are specified. + 1:0 Reserved + Format: MBZ +2 31:2 Memory Address + + Format: GraphicsAddress[31:2]MMIO_Register + This field specifies the address of the memory location where the register value specified in the DWord + above will be written. The address specifies the DWord location of the data.Range = + GraphicsVirtualAddress[31:2] for a DWord register + + 1:0 Reserved + Format: MBZ + + + + +1.2.12 MI_STORE_DATA_IMM +The MI_STORE_DATA_IMM command format is: + + MI_STORE_DATA_IMM + +Source: VideoCS +Length Bias: 2 +The MI_STORE_DATA_IMM command requests a write of the QWord or DWord constant supplied in the packet to +the specified Memory Address. As the write targets a System Memory Address, the write operation is coherent with +the CPU cache (i.e., the processor cache is snooped). + Programming Notes Project +This command should not be used within a “non-secure” batch buffer to access global virtual space. Doing +so will cause the command parser to perform the write with byte enables turned off. This command can be +used within ring buffers and/or “secure” batch buffers. +Use Global GTT will not be ignored when in a PPGTT batch buffer. +This command can be used for general software synchronization through variables in cacheable memory +(i.e., where software does not need to poll un-cached memory or device registers). +This command simply initiates the write operation with command execution proceeding normally. Although +the write operation is guaranteed to complete “eventually”, there is no mechanism to synchronize command +execution with the completion (or even initiation) of these operations. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 20h MI_STORE_DATA_IMM + Format: OpCode + 22 Use Global GTT + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 63 + MI_STORE_DATA_IMM + Format: U32 + If set, this command will use the global GTT to translate the Address and this command must be + executing from a privileged (secure) batch buffer. If clear, the PPGTT will be used. It is allowed for this + bit to be clear when executing this command from a privileged (secure) batch buffer. This bit must be + ‘1’ if the Per Process GTT Enable bit is clear. + + 21:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) = 3 for QWord, 2 for DWord + Format: =n Total Length - 2 + + + +1 31:0 Reserved + Format: MBZ +2 31:2 Address + Format: GraphicsAddress[31:2] + This field specifies Bits 31:2 of the Address where the DWord will be stored. As the store address must + be DWord-aligned, Bits 1:0 of that address MBZ. This address must be 8B aligned for a store “QW” + command. + + 1:0 Reserved + Format: MBZ +3 31:0 Data DWord 0 + Format: U32 FormatDesc + + + This field specifies the DWord value to be written to the targeted location.For a QWord write this DWord + is the lower DWord of the QWord to be reported (DW 0). + +4 31:0 Data DWord 1 + Format: U32 FormatDesc + + + This field specifies the upper DWord value to be written to the targeted QWord location (DW 1). + + + + +64 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.2.13 MI_STORE_DATA_INDEX +The MI_STORE_DATA_INDEX command format is: + + MI_STORE_DATA_INDEX +Project: All +Source: VideoCS +Length Bias: 2 +The MI_STORE_DATA_INDEX command requests a write of the data constant supplied in the packet to the +specified offset from the System Address defined by the Hardware Status Page Address Register. As the write +targets a System Address, the write operation is coherent with the CPU cache (i.e., the processor cache is snooped). + Programming Notes +  Use of this command with an invalid or uninitialized value in the Hardware Status Page Address Register is + UNDEFINED. +  This command can be used for general software synchronization through variables in cacheable memory (i.e., + where software does not need to poll uncached memory or device registers). +  This command simply initiates the write operation with command execution proceeding normally. Although the + write operation is guaranteed to complete “eventually”, there is no mechanism to synchronize command + execution with the completion (or even initiation) of these operations. + + +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 21h MI_STORE_DATA_INDEX + Format: OpCode + 22 Reserved + Format: MBZ + 21 Reserved + + Format: MBZ + 20:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) = 2 for QWord + Format: =n Total Length - 2 + + + +1 31:12 Reserved + Format: MBZ + 11:2 Offset + Format: U10 FormatDesc; zero-based DWord offset into the HW status page + + + Format: GraphicsAddress[31:0]U32 + This field specifies the offset (into the hardware status page) to which the data will be written. Note that + the first few DWords of this status page are reserved for special-purpose data storage – targeting these + reserved locations via this command is UNDEFINED.For a QWord write, the offset is valid down to bit 3 + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 65 + MI_STORE_DATA_INDEX + only. + Value Name + [16, 1023] + 1:0 Reserved + Format: MBZ +2 31:0 Data DWord 0 + Format: U32 FormatDesc + + + This field specifies the upper DWord value to be written to the targeted QWord location (DW 1). + +3 31:0 Data Word 1 + Format: U32 FormatDesc + + + This field specifies the upper DWord value to be written to the targeted QWord location (DW 1). + + + + +1.2.14 MI_SUSPEND_FLUSH + + MI_SUSPEND_FLUSH +Project: All +Source: VideoCS +Length Bias: 1 + Description Project +Blocks MMIO sync flush or any flushes related to VT-d while enabled. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 0Bh MI_SUSPEND_FLUSH + 22:1 Reserved + Format: MBZ + 0 Suspend Flush + Format: Enable + + + Description Project + This field suspends flush due and IOTLB invalidation. + + + + +66 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + 1.2.15 MI_USER_INTERRUPT + + MI_USER_INTERRUPT +Project: All +Source: VideoCS +Length Bias: 1 +The MI_USER_INTERRUPT command is used to generate a User Interrupt condition. The parser will continue +parsing after processing this command. See User Interrupt. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 02h MI_USER_INTERRUPT + Format: OpCode + 22:0 Reserved + Format: MBZ + + + + +1.2.16 MI_UPDATE_GTT + +1.2.16.1 MI_UPDATE_GTT + + MI_UPDATE_GTT + +Source: VideoCS +Length Bias: 2 +The MI_UPDATE_GTT command is used to update GTT page table entries in a coherent manner and at a +predictable place in the command flow. An MI_FLUSH should be placed before this command, because work +associated with preceding commands that are still in the pipeline may be referencing GTT entries that will be +changed by its execution. The flush will also invalidate TLBs and read caches that may become invalid as a result of +the changed GTT entries. MI_FLUSH is not required if it can be guaranteed that the pipeline is free of any work that +relies on changing GTT entries (such as MI_UPDATE_GTT contained in a paging DMA buffer that is doing only +update/mapping activities and no rendering). This is a privileged command. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 23h MI_UPDATE_GTT + Format: OpCode + 22 Use Global GTT + Reserved: Must be 1h. Updating Per Process Graphics Address is not supported + Value Name Description + 0h Per Process Graphics Address + 1h Global Graphics Address + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 67 + MI_UPDATE_GTT + 21:6 Reserved + Format: MBZ + 5:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Format: =n + Total Length - 2 + +1 31:12 Entry Address + Format: GraphicsAddress[31:12] + This field simply holds the DW offset of the first table entry to be modified. Note that one or more of + the upper bits may need to be 0, i.e., for a 2G aperture, bit 31 MBZ. + + 11:0 Reserved + Format: MBZ +2..n 31:0 Entry Data + Format: Page Table Entry + This Dword becomes the new page table entry. See PPGTT/Global GTT Table Entries (PTEs) in + Memory Interface Registers. + + + + +1.2.17 MI_WAIT_FOR_EVENT + + MI_WAIT_FOR_EVENT + +Source: VideoCS +Length Bias: 1 +The MI_WAIT_FOR_EVENT command is used to pause command stream processing of this pipe only until a +specific event occurs or while a specific condition exists. See Wait Events/Conditions, Device Programming Interface +in MI Functions. Only one event/condition can be specified -- specifying multiple events is UNDEFINED.Note that if a +specified condition does not exist (the condition code is inactive) at the time the parser executes this command, the +parser proceeds, treating this command as a no-operation. + DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + 28:23 MI Command Opcode + Default Value: 03h MI_WAIT_FOR_EVENT + 22:20 Reserved + Project: All + Format: MBZ + 19:16 Condition Code Wait Select + This field enables a wait for the duration that the corresponding condition code is active. These + enable select one of 15 condition codes in the EXCC register, that cause the parser to wait until that + condition-code in the EXCC is cleared. + + + + +68 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + MI_WAIT_FOR_EVENT + Value Name Description + 0h Not enabled Condition Code Wait Not Enabled + 1h-5h Enable Condition Code select enabled; selects one of 5 codes, 0 – 4 + 6h-15h Reserved + + + Programming Notes + Note that not all condition codes are implemented. The parser operation is UNDEFINED if an + unimplemented condition code is selected by this field. The description of the EXCC register (Memory + Interface Registers) lists the codes that are implemented. + 15:0 Reserved + Format: MBZ + + + + +1.2.18 MI_LOAD_REGISTER_MEM + + MI_LOAD_REGISTER_MEM + +Source: VideoCS +Length Bias: 2 +The MI_LOAD_REGISTER_MEM command requests from a memory location and stores that DWord to a register. +DWord Bit Description +0 31:29 Command Type + Default Value: 0h MI_COMMAND + Format: OpCode + 28:23 MI Command Opcode + Default Value: 29h MI_LOAD_REGISTER_MEM + Format: OpCode + 22 Use Global GTT + This bit must be 1 if the Per-Process GTT Enable bit is clear. + Value Name Description + 0h Per Process + Graphics Address + 1h Global Graphics This command will use the global GTT to translate the Address and this + Address command must be executing from a privileged (secure) batch buffer. + 21 Async Mode Enable + If this bit is set then the command stream will not wait for completion of this command before executing + the next command. + 20:8 Reserved + Format: MBZ + 7:0 DWord Length + Format: =n + + + Value Name Description + 01h Excludes DWord (0,1) [Default] Total Length - 2 + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 69 + MI_LOAD_REGISTER_MEM +1 31:26 Reserved + Format: MBZ + 22:2 Register Address + Format: MMIOAddress[22:2]MMIO_Register + This field specifies Bits 25:2 of the Register offset the DWord will be written to. As the register address + must be DWord-aligned, Bits 1:0 of that address MBZ. + + 1:0 Reserved + Format: MBZ +2 31:2 Memory Address + Format: GraphicsAddress[31:2]MMIO_Register + This field specifies the address of the memory location where the register value specified in the DWord + above will read from. The address specifies the DWord location of the data. + + 1:0 Reserved + Format: MBZ + + + + +70 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V1 Pt 5 – 05 12 5/31/2012 71 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol1_part6.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part6.txt new file mode 100644 index 0000000..f3b7b08 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part6.txt @@ -0,0 +1,3732 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 1 Part 6: GT Interface Register +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 + Contents +1. GT Interface Registers .......................................................................................................................... 4 + 1.1 MBCunit Config Space ......................................................................................................................... 4 + 1.1.1 IDICR - IDI Control register ............................................................................................................ 4 + 1.1.2 SNPCR - Snoop control register..................................................................................................... 5 + 1.1.3 IDICA - IDI Cacheable Register...................................................................................................... 8 + 1.1.4 IDISLFSNP - IDI Self Snoop Register .......................................................................................... 10 + 1.1.5 SQCNT1 - Super Queue Internal Cnt Register I .......................................................................... 12 + 1.1.6 SQCNT2 - Super Queue Internal Counters Register II ................................................................ 14 + 1.1.7 SQCFG - Super Queue GFX cycle Options register .................................................................... 17 + 1.1.8 SQERR - SQ Error Status ............................................................................................................ 18 + 1.1.9 MFCR - Fence Control Register ................................................................................................... 18 + 1.1.10 MBCTL - MBC Control Register ................................................................................................. 19 + 1.1.11 TOLUD - Mirror of TOLUD.......................................................................................................... 20 + 1.1.12 MGGC - Mirror of GMCH Graphics Control Register ................................................................. 21 + 1.1.13 TOUUD - Mirror of TOUUD ........................................................................................................ 23 + 1.1.14 DSMB - Mirror of DSMBASE ...................................................................................................... 23 + 1.1.15 GSMB - Mirror of GSMBASE ...................................................................................................... 24 + 1.1.16 GCMD - Mirror of Global Command Register ............................................................................ 24 + 1.1.17 GTTMMADR - Mirror of Graphics Translation Table and Memory Mapped Range Address..... 28 + 1.1.18 PCICMD - Mirror of PCICMD MAE/BME .................................................................................... 29 + 1.1.19 PERFCNT1 - Performance Counter 1 ........................................................................................ 31 + 1.1.20 PERFCNT2 - Performance Counter 2 ........................................................................................ 32 + 1.1.21 PERFMATRIX - Performance Matrix Events .............................................................................. 33 + 1.2 MBCunit Message .............................................................................................................................. 36 + 1.2.1 IDIMSG - IDI MESSAGES ............................................................................................................ 36 + 1.2.2 BOOTMSG - BOOT VECTOR ...................................................................................................... 38 + 1.2.3 GFXPMRDPR - GFX/DPR Update Message Bits ........................................................................ 38 + 1.2.4 IDILK1 - IDI Lookup Register 1..................................................................................................... 39 + 1.2.5 IDILK2 - IDI Lookup Register 2..................................................................................................... 40 + 1.3 GDTunit Config Space ....................................................................................................................... 44 + 1.3.1 PSMIBase - PSMI Base Register ................................................................................................. 44 + 1.3.2 PSMICtrl - PSMI Control ............................................................................................................... 44 + 1.3.3 PSMIStatus - PSMI Status ........................................................................................................... 45 + 1.4 GCPunit Config Register Space ........................................................................................................ 45 + 1.4.1 UCGCTL1 - Unit Level Clock Gating Control 1 ............................................................................ 46 + 1.4.2 UCGCTL2 - Unit Level Clock Gating Control 2 ............................................................................ 49 + 1.4.3 UCGCTL3 - Unit Level Clock Gating Control 3 ............................................................................ 55 + 1.4.4 UCGCTL4 - Unit Level Clock Gating Control 4 ............................................................................ 59 + 1.4.5 RCGCTL1 - RAM Clock Gating Control 1 .................................................................................... 60 + 1.4.6 RCGCTL2 - RAM Clock Gating Control 2 .................................................................................... 65 + 1.4.7 IFDIMCTL - Integrated Power Supply Frequency Domain Impedance Meter Controls ............... 68 + 1.4.8 GDRST - Graphics Device Reset Control .................................................................................... 69 + 1.4.9 RSTCTL - Misc. Reset Control Register ...................................................................................... 70 + 1.4.10 MISCCPCTL - Misc. Clocking/Reset Control Register ............................................................... 71 + 1.5 GCPunit Message Register Space .................................................................................................... 71 + 1.5.1 FLRCTLMSG - GT Function Level Reset Control Message ........................................................ 72 + 1.5.2 CGMSG - Glock Gating Messages .............................................................................................. 72 + 1.5.3 RSTFCTLMSG - Reset Flow Control Messages .......................................................................... 73 + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 3 + 1. GT Interface Registers +1.1 MBCunit Config Space + Register Register Register + Register Name Symbol Start End Default Value Access +IDI Control Register IDICR 9008h 900Bh 00000005h RW +Snoop Control Register SNPCR 900Ch 900Fh 00001B40h RW, + RO +IDI Cacheable Register IDICA 9014h 9017h 00000000h RW +IDI Self Snoop Register IDISLFSNP 9018h 901Bh 00000000h RW +Super Queue Internal Counters Register 1 SQCNT1 9024h 9027h 00000000h RW, + RO +Super Queue Internal Counters Register 2 SQCNT2 9028h 902Bh 00000F00h RO, + RW +Super Queue GFX Cycle Options Register SQCFG 902Ch 902Fh 00000000h RO, + RW +Fence Control Register MFCR 9070h 9073h 00000000h RO, + RW +MBC Control Register MBCTL 907Ch 907Fh 00000000h RW, + RO +Mirror of TOLUD TOLUD 9090h 9093h 00100000h RO +Mirror of GMCH Graphics Control Register MGGC 9094h 9097h 00000030h RO +Mirror of TOUUD TOUUD 9098h 909Fh 0000000000000000h RO +Mirror of DSMBASE DSMB 90A0h 90A3h 00000000h RO +Mirror of GSMBASE GSMB 90A4h 90A7h 00000000h RO +Mirror of DPRBASE DPRB 90A8h 90ABh 00000000h RO +Mirror of Global Command Register GCMD 90CCh 90CFh 00000000h RO +Mirror of Graphics Translation Table and GTTMMADR 9124h 912Bh 0000000000000000h RO +Memory Mapped Range Address +Mirror of PCICMD MAE/BME PCICMD 912Ch 912Fh 00000000h RW + +Workaround: Accesses to the MMIO range from 0x9500-0x97ff can prevent GT from entering RC6 after +the read or write. There are no registers in this range, thus no reason for software to read or write this +range. + + +1.1.1 IDICR - IDI Control register +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 9008-900Bh +Default Value: 00000005h +Access: RW +Size: 32 bits + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 4 + Default + Bits Access Value RST/PWR Description +31:15 RW 00000h Core + ECORSVD (ECORSVD): + ECO purposes and Reserved. + 6:4 RW 000b Core + LRUHint (LRU): + 000b: No LRUHint command sent to uncore. It’s reserved. + 001b: If LRUHint is asserted from SQ with a read or write command, IDI + dispatcher chooses to send an LlcPrefData. + 101b: If LRUHint is asserted from SQ with a read or write command, IDI + dispatcher chooses to send an LLCPrefCode command on the C2U request + channel. + 010b: If LRUHint is asserted from SQ with a read/write command, IDI dispatcher + chooses to send an LlcPrefRFO command on the C2U request channel. + 011b: If LRUHint is asserted from SQ with a read, IDI dispatcher chooses to send + an LlcPrefData command on the C2U request channel. If LRUHint is asserted + from SQ with a write, IDI dispatcher chooses to send LlcPrefRFO command on + the C2U request channel. + 111b: If LRUHint is asserted from SQ with a read, IDI dispatcher chooses to send + an LLCPrefCode command on the C2U request channel. If LRUHint is asserted + from SQ with a write, IDI dispatcher chooses to send LlcPrefRFO command on + the C2U request channel. + + 3 RO 0b Core Reserved. + 2 RW 0b Core + Rsp Port1 Disable: + 0 - Default value - Both the Response ports on the BGF side are enabled. + 1 - Rsp Port1 Disable - Response Port1 is disable on the BGF Side + 1:0 RW 01b Core + SQ Grant Counter (SQGNT): + SQ grant counter - 2-bit grant counter for SQ requests: + 00b - 1 grant + 01b - 2 grants + 10b - 4 grants + 11b - 8 grants + + + +1.1.2 SNPCR - Snoop control register +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 900C-900Fh +Default Value: 00001B40h +Access: RW, RO +Size: 32 bits +Snoop control register + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 5 + Default + Bits Access Value RST/PWR Description +31:23 RO 000000000b Core + Reserved (RSVD): + RSVD +22:21 RW 00b Core + IDICOS (IDICOS): + 00 => MAX uncore resources (default) + 01 => Medium uncore resources + 10 => LOW uncore resources + 11 => MIN uncore resources + SNPCR - Snoop control register, IDICOS values explanation + Bits COS Value Description (from BSpec) GT GT + + Mobile 8MB Total Cache Size CPUs (4+2, ie 3820QM) + 22:21 00 6 3MB + 01 16 8MB + 10 12 6MB + 11 1 512KB + Mobile 6MB Cache Size CPUs (4+2, ie 3615QM) + 22:21 00 5 2.5MB + 01 12 6MB + 10 9 4.5MB + 11 1 512KB + IVB Mobile 4MB Cache Size CPUs (2+?, like 3520M) + 22:21 00 6 1.5MB + 01 16 4MB + 10 12 3MB + 11 1 256KB + Mobile 3MB Cache Size CPUs (2+?, like 3320M) + 22:21 00 5 1.25MB + 01 12 6MB + 10 9 2.25MB + 11 1 256KB + 20 RW 0b Core + Non Temporal (NONTMP): + Indication to uncore that - Request is of the type that should get minimal + cache resources in the uncore +19:16 RO 0000b Core + RSVD (RSVD): + Reserved + 15 RW 0b Core + Thread ID (THDID): + 1 bit Thread ID for GT + + 14 RW 0b Core + Force Invalidate (FINV): + Force Invalidate - Forces the invalidate flag to be set with snoop lookups all + the time. + 0 - normal invalidation (based on req) - Default + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 6 + Default +Bits Access Value RST/PWR Description + 1 - Forced invalidation +13:11 RW 011b Core + IDI Pend Timer (IDITIMER): + IDIpend timer - Time to wait before monitoring the sq_snpc_idipend signal. + 000=> 0 clocks + 001 => 1 clock + 010 => 2 clocks + 011 => 4 clocks (default) + 100 => 8 + 101 => 16 + 110 => 32 + 111 => 64 +10:8 RW 011b Core + Retry Limi (RTRYLMT): + Retry Limit - Number of times to retry before switching to the freeze + mechanism + 000=> Always freeze (first shot) + 001=> 1 retry + 010 => 2 retry + 011 => 4 retry (default) + 100 => 8 retry + 101 => 16 retry + 110 => 32 retry + 111 => infinite (no freeze) + + 7:3 RW 01000b Core + Retry Timer (RTRYTIMER): + Retry Timer - Time between receiving a reject from SQ and repeating the + monitor sequence. + 00000=> 0 clocks + 00001 => 1 clock + 00010 => 2 clocks + 00011 => 3 clocks + 00111 => 7 clocks + 01000 => 8 clocks (Default) + . + . + . + 11111 => 32 clocks + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 7 + Default +Bits Access Value RST/PWR Description +2:0 RW 000b Core + MLCSQ Timer (MSTIMER): + MLC-SQ Timer - Time between doing an MLC lookup and SQ lookup + 000=> 0 clocks (default) + 001 => 1 clock + 010 => 2 clocks + 011 => 4 clocks + 100 => 8 + 101 => 16 + 110 => 32 + 111 => 64 + + + +1.1.3 IDICA - IDI Cacheable Register +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 9014-9017h +Default Value: 00000000h +Access: RW +Size: 32 bits +Cacheable: + Default + Bits Access Value RST/PWR Description +31:30 RW 00b Core + LLCWBCA (LLCWBCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. +29:28 RW 00b Core + LLCPRFOCA (LLCPRFOCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. + +27:26 RW 00b Core + LLCPCCA (LLCPCCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. +25:24 RW 00b Core + LLCPDCA (LLCPDCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. +23:22 RW 00b Core + CLFCA (CLFCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. +21:20 RW 00b Core + POCA (POCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. + +19:18 RW 00b Core + ITMCA (ITMCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 8 + Default + Bits Access Value RST/PWR Description +17:16 RW 00b Core + WCILFCA (WCILFCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. +15:14 RW 00b Core + WILCA (WILCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. +13:12 RW 00b Core + WCILCA (WCILCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. + +11:10 RW 00b Core + WBMCA (WBMCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. + 9:8 RW 00b Core + RFOCA (RFOCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. + 7:6 RW 00b Core + PORINCA (PORINCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. + 5:4 RW 00b Core + PRDCA (PRDCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. + + 3:2 RW 00b Core + DRDCA (DRDCA): + 00b: What ever the logic decides (so force feature is disabled) - Default. + 01b: Always drive “0”. + 10b: Always drive “1”. + 11b: Reserved. + 1:0 RW 00b Core + CRDCA (CRDCA): + 00b: What ever the logic decides (so force feature is disabled) - Default. + 01b: Always drive “0”. + 10b: Always drive “1”. + 11b: Reserved. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 9 + 1.1.4 IDISLFSNP - IDI Self Snoop Register +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset:9018-901Bh +Default Value: 00000000h +Access: RW +Size: 32 bits +IDI Self Snoop Register: + Default + Bits Access Value RST/PWR Description +31:30 RW 00b Core + LLCWBSNP (LLCWBSNP): + 00b: Whatever the logic decides (so force feature is disabled) - Default. + 01b: Always drive “0”. + 10b: Always drive “1”. + 11b: Reserved. + +29:28 RW 00b Core + LLCPRFOSNP (LLCPRFOSNP): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. +27:26 RW 00b Core + LLCPCSNP (LLCPCSNP): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. +25:24 RW 00b Core + LLCPDSNP (LLCPDSNP): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. +23:22 RW 00b Core + CLFCA (CLFCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. +21:20 RW 00b Core + POCA (POCA): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. +19:18 RW 00b Core + ITMSNP (ITMSNP): + 00b: Whatever the logic decides (so force feature is disabled) - Default. + 01b: Always drive “0”. + 10b: Always drive “1”. + 11b: Reserved. +17:16 RW 00b Core + WCILFSNP (WCILFSNP): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 10 + Default + Bits Access Value RST/PWR Description +15:14 RW 00b Core + WILSNP (WILSNP): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. +13:12 RW 00b Core + WCILSNP (WCILSNP): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. +11:10 RW 00b Core + WBMSNP (WBMSNP): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. + + 9:8 RW 00b Core + RFOSNP (RFOSNP): + 00b: What ever the logic decides (so force feature is disabled) - Default. + 01b: Always drive “0”. + 10b: Always drive “1”. + 11b: Reserved. + 7:6 RW 00b Core + PORINSNP (PORINSNP): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. + 5:4 RW 00b Core + PRDSNP (PRDSNP): + NOTE - THIS SHOULD ALWAYS BE PROGRAMMED TO “00”. CANNOT BE + FLEXED. + 3:2 RW 00b Core + DRDSNP (DRDSNP): + 00b: Whatever the logic decides (so force feature is disabled) - Default. + 01b: Always drive “0”. + 10b: Always drive “1”. + 11b: Reserved. + + 1:0 RW 00b Core + CRDSP (CRDSP): + 00b: Whatever the logic decides (so force feature is disabled) - Default. + 01b: Always drive “0”. + 10b: Always drive “1”. + 11b: Reserved. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 11 + 1.1.5 SQCNT1 - Super Queue Internal Cnt Register I +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 9024-9027h +Default Value: 00000000h +Access: RW, RO +Size: 32 bits +SQ Internal Counter Register + Default RST/PW + Bits Access Value R Description + 31:24 RO 0000000 Core + RSVD (RSVD): + 0b + RSVD + 23:20 RW 0000b Core + SQRWCQD (SQRWCQD): + Read-Write Request Queue Command Get Delay: + This indicates the number of clocks that are inserted between + each GFX cycle being accepted on the GFX Read or GFX Write + ports. By default, this is disabled, which means that the RWRQ is + able to accept one cycle per clock. By any other value, the + RWRQ will insert the number of idle clocks listed in this register + before accepting another cycle from GFX, essentially throttling + the bandwidth. During each idle clock, RWRQ is guaranteed not + to assert its command get to either read or write port. + 0000 = disabled (no additional clocks added) + 0001 = one idle clock inserted between command gets + 0010 = two idle clocks inserted between command gets + ... + 1111 = fifteen idle clocks inserted between command gets + 19:16 RW 0000b Core + SQCQD (SQCQD): + Read-Only Request Queue Command Get Delay: + This indicates the number of clocks that are inserted between + each GFX cycle being accepted on the GFX Read-Only port. By + default, this is disabled, which means that the RORQ is able to + accept one cycle per clock. By any other value, the RORQ will + insert the number of idle clocks listed in this register before + accepting another cycle from GFX, essentially throttling the + bandwidth. During each idle clock, RORQ is guaranteed not to + assert its command get. + 0000 = disabled (no additional clocks added) + 0001 = one idle clock inserted between command gets + 0010 = two idle clocks inserted between command gets + ... + 1111 = fifteen idle clocks inserted between command gets + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 12 + Default RST/PW + Bits Access Value R Description + 15:13 RW 000b Core + SQDPTH (SQDPTH): + Super Queue Depth: + This indicates the maximum number of cycles that are supported + at any given time by Super Queue. By default, this is 48, which is + the maximum size of the Super Queue, but can be throttled back + to support fewer GFX cycles. + Note: By limiting the depth of the super queue, effectively the + recycle queue limits the SQIDs that are allowed to be used. + 000 = disabled (48 deep) + 001 = Rsvd. + 010 = 2 deep + 011 = 4 deep + 100 = 8 deep + 101 = 16 deep + 110 = 24 deep + 111 = 32 deep + 12:9 RW 0000b Core + SQMQCNT (SQMQCNT): + Outstanding MQ IDI Cycle Counter: + Note: This register Bits (SQMQCNT) should not be programmed. + The default value "0" ( 16 entries) is the POR. + This indicates the maximum number of outstanding cycles that + are presented to IDI/uncore at any given time by Maintenance + Queue. By default, this is 16, but can be throttled back to support + fewer IDI cycles. + 0 = disabled (16) + 1-15 = max number of outstanding IDI cycles + 8:6 RW 000b Core + SQVTDCNT (SQVTDCNT): + Outstanding VTD read Counter: + This indicates the maximum number of outstanding VTD read + cycles that are presented to IDI/uncore at any given time by + Super Queue. By default, this is 4, but can be throttled back to + support fewer VTD read cycles. + 000 = 1 max outstanding VTD read cycle + 001 = 2 max outstanding VTD read cycles + 010 = 3 max outstanding VTD read cycles + 011 = 4 max outstanding VTD read cycles (Default value) + 100 = 5 max outstanding VTD read cycles + 101 = 6 max outstanding VTD read cycles + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 13 + Default RST/PW + Bits Access Value R Description + 110 = 7 max outstanding VTD read cycles + 111 = 8 max outstanding VTD read cycles + 5:0 RW 000000b Core + SQIDICNT (SQIDICNT): + Outstanding SQ IDI Cycle Counter: + This indicates the maximum number of outstanding cycles that + are presented to IDI/uncore at any given time by Super Queue. + By default, this is 48, but can be throttled back to support fewer + IDI cycles. + 0 = disabled (48) + 1-47 = max number of outstanding IDI cycles + 48+ = reserved + + + +1.1.6 SQCNT2 - Super Queue Internal Counters Register II +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 9028-902Bh +Default Value: 00000F00h +Access: RO, RW +Size: 32 bits +Super Queue Internal Counter register + Default + Bits Access Value RST/PWR Description +31:30 RO 00b Core + Reserved (RSVD): + Reserved + + 29 RW 0b Core + Enable Promotion on Read (ENPROM): + Enable Promotion on Read Match: Enable the promotion of write request if + matched with a Read request. + 28 RW 0b Core + Priority 3 Pool Count Disable (PRIO3PCDIS): + Priority3 Pool Count Disable: When set, priority3 pool becomes unlimited. And + priority3 pool count value should not be used in reset of the remaining counters. +27:25 RW 000b Core + Priority3 Pool Count: (PRIO3PC): + Priority3 Pool Count: + The count of cycles is selected from priority3 pool before switching to lower + priority pools. Count is used as the power of 2. + 000: 1 request + 001: 2 requests + 010: 4 requests + 011: 8 requests + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 14 + Default +Bits Access Value RST/PWR Description + ….. + 111: 128 requests + 24 RW 0b Core + Priority2 Pool Count Disable (PRIO2PCDIS): + Priority2 Pool Count Disable: When set, priority2 pool becomes unlimited. And + priority2 pool count value should not be used in reset of the remaining counters. +23:21 RW 000b Core + Priority2 Pool count (PRIO2PC): + Priority2 Pool Count: + The count of cycles is selected from priority2 pool before switching to lower + priority pools. Count is used as the power of 2. + 000: 1 request + 001: 2 requests + 010: 4 requests + 011: 8 requests + ….. + 111: 128 requests + + 20 RW 0b Core + Priority1 Pool Count Disable (PRIO1PCDIS): + Priority1 Pool Count Disable: When set, priority1 pool becomes unlimited. And + priority1 pool count value should not be used in reset of the remaining counters. +19:17 RW 000b Core + Priority1 Pool Count (PRIO1PC): + Priority1 Pool Count: + The count of cycles is selected from priority1 pool before switching to lower + priority pools. Count is used as the power of 2. + 000: 1 request + 001: 2 requests + 010: 4 requests + 011: 8 requests + ….. + 111: 128 requests + 16 RW 0b Core + Priority0 Pool Count Disable (PRIO0PCDIS): + Priority0 Pool Count Disable: When set, priority0 pool becomes unlimited. And + priority0 pool count value should not be used in reset of the remaining counters. +15:13 RW 000b Core + Priority0 Pool Count (PRIO0PC): + Priority0 Pool Count: + The count of cycles is selected from priority0 pool before switching to lower + priority pools. Count is used as the power of 2. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 15 + Default +Bits Access Value RST/PWR Description + 000: 1 request + 001: 2 requests + 010: 4 requests + 011: 8 requests + ….. + 111: 128 requests + 12 RW 0b Core + Enable Priority Selection (PRIOEN): + Enable Priority Selection: + Enables the use of priority bits coming from GFX core. If disabled, all slots in SQ + is treated as same peiority + 0 (default) : Disabled + 1: Enable +11:8 RW 1111b Core + Super Queue Internal Register count (VTD): + SQ Mas VTD Cycles + This is the binary value of the maximum number of VTd cycles that GTI Super + Queue will accept from graphics before new VTd requests are throttled. In + essence, this determines the depth of the VTd queue within the Super Queue. + 0000 = 1 VTd cycle + 0001 = 2 VTd cycles + 0010 = 3 VTd cycles + ... + 1110 = 15 VTd cycles + 1111 = 16 VTd cycles + + 7:0 RO 00h Core + LRU Hint counter (LRU): + Reserved + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 16 + 1.1.7 SQCFG - Super Queue GFX cycle Options register +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 902C-902Fh +Default Value: 00000000h +Access: RO, RW +Size: 32 bits +Super Queue GFX Cycle Options register. + Default +Bits Access Value RST/PWR Description +31:3 RO 00000000h Core + Reserved (RSVD): + Reserved + + 2 RW 0b Core + SQ Read-Only Port Reject Disable (SQRORD): + SQ Read-Only Port Reject Disable + This indicates whether rejections can be issued from the Super Queue to GFX + for read cycles on the Read Only port. Rejected cycles are retried at a later time + by GFX. + By default, read cycles that have a matching address elsewhere in the Super + Queue are rejected, and GFX is notified of the rejection. + If this bit is set, no rejections will ever occur on the SQ-GFX interface. SQ will + accept all requests, but in the case of a matching address, the SQ will stall the + Read-Only port until the address match disappears (matching entry is retired by + SQ). + 1 = Rejections are disabled, SQ will stall if needed + 0 = Rejections are enabled + 1 RW 0b Core + SQ ReadPort GFX Read Ownership (SQRWO): + SQ Read Port GFX Read Ownership (SQRWO): + SQ Read-Only Port GFX Read Ownership Indication This indicates the type of + request that is issued to uncore for each read cycle from the GFX Read-Only + port which produces a miss in the MLC. By default, read cycles that have no + matching MLC entry will produce a regular read request from uncore through the + IDI. If this bit is set, the request is changed from a regular read to a request for + ownership (RFO) of the cacheline. This applies for all read requests from the + GFX Read-Only port ONLY. 1 = All GFX reads from RO port require ownership + of the cacheline 0 = GFX reads from RO port do + 0 RW 0b Core + SQ Read-Only Port GFX Read (SQROO): + SQ Read-Only Port GFX Read (SQROO): + SQ Read-Only Port GFX Read Ownership Indication This indicates the type of + request that is issued to uncore for each read cycle from the GFX Read-Only + port which produces a miss in the MLC. By default, read cycles that have no + matching MLC entry will produce a regular read request from uncore through the + IDI. If this bit is set, the request is changed from a regular read to a request for + ownership (RFO) of the cacheline. This applies for all read requests from the + GFX Read-Only port ONLY. 1 = All GFX reads from RO port require ownership + of the cacheline 0 = GFX reads from RO port do + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 17 + 1.1.8 SQERR - SQ Error Status +B/D/F/Type: 0/2/0/MMADR_MBCunit_Config +Address Offset: 9034-9037h +Default Value: 00000000h +Access: RWC, RO +Size: 32 bits +SQ Error Status register +Bits Access Default Value RST/PWR Description +31:1 RO 00000000h Core + RSVD (RSVD): + RSVD + 0 RWC 0b Core + SQ Address Decode Error (SQADDRERR): + SQ Address Decode Error + + + +1.1.9 MFCR - Fence Control Register +B/D/F/Type: 0/2/0/MMADR_MBCunit_Config +Address Offset:9070-9073h +Default Value: 00000000h +Access: RW, RO +Size: 32 bits +Fence Control Register: + Bits Access Default Value RST/PWR Description +31:16 RW 0000h Core + ECO RSVD (ECORSVD): + ECO purposes Reserved. +15:5 RO 00000000000b Core + RSVD (RSVD): + Reserved. + 2 RW 0b Core + Write/Read Port Block (MFCBLK): + 0: Dont Block the R/W port when Query is started. + 1: Block the R/W port until the Memory Fence is completed + This is applicable for only Memory Fence. + 1 RW 0b Core + LLC Query Enable (MFCLLC): + 0: Query for 16 Ways. + 1: Query for 32 Ways. + No Flexing. + + 0 RW 0b Core + Fence Controller GFDT Mode (MFCGFDT): + Fence Controller GFDT Mode: + 0: Single bit GFDT mode. + 1: Two bit GFDT mode. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 18 + 1.1.10 MBCTL - MBC Control Register +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset:907C-907Fh +Default Value: 00000000h +Access: RW, RO +Size: 32 bits +MBC Control Register: + Bits Access Default Value RST/PWR Description +31:16 RW 0000000000000000b Core + ECORSVD (ECORSVD): + ECO purposes Reserved. +18:17 R/W 00 Core + Multicast slice Read Return Select: + This field is provided to MCHGunit. End point based on this value + selects one of the registers from multicast destinations. + 00b means upper left half slice. + 01b means upper right half slice. + 10b means lower left half slice. + 11b means lower right half slice. +16 R/W 0 Core + VCR fuse R/W as posted. + 0: Not posted. + 1: Posted. +15:6 RO 0000000000b Core + RSVD (RSVD): + RSVD. + + 5 RO 0h Reserved (RSVD). + 4 RW 0 + Enable Boot Fetch: + Config bit for driver managed boot kick off. + 1 - Enable Boot Fetch without any PM interaction. + 0 - Default (no action). + The driver must set this bit in the following scenarios: +  To reload the HW boot context every time it gets loaded through + the OS. +  After an FLR clears the register (the BIOS won’t run afterwards). + + RW 0b Core + 3 Context Fetch Needed (CTXTFETCH): + Context Fetch Needed for Power Exits. + 0 - Context Fetch Not Needed. + 1 - Context Fetch Needed for Power Exits ( CPD Entry). + 2 RW 0b Core + BME Update Enable (BMEUE): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 19 + Bits Access Default Value RST/PWR Description + BME Update Enable: + 0: Default. BME Update is not Enabled. MBC ignores all BME updates + from SA. + 1: BME update is Enabled. + 1 RW 0b Core + MAE Update Enable (MBEUE): + MAE Update Enable - + 0: Default. Mae Update is not Enabled. MBC ignores all MAE updates + from SA. + 1: MAE update is Enabled. MBC responds to MAE updates. + 0 RW 0b Core + Boot Fetch Mechanism (BOOTF): + Choose between 2 different boot context fetch mechanisms: + 0: Use MBC to GAM path with 8B reads (default). + 1: Use MBC to Config Agent register interface with 4B reads. + + + +1.1.11 TOLUD - Mirror of TOLUD +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 9090-9093h +Default Value: 00100000h +Access: RO +Size: 32 bits +Top of Low usable Dram. + Default + Bits Access Value RST/PWR Description +31:20 RO 001h Core + TOLUD (TOLUD): + This register contains bits 31 to 20 of an address one byte above the maximum + DRAM memory below 4G that is usable by the operating system. Address bits 31 + down to 20 programmed to 01h implies a minimum memory size of 1MB. + Configuration software must set this value to the smaller of the following 2 choices: + maximum amount memory in the system minus ME stolen memory plus one byte + or the minimum address allocated for PCI memory. Address bits 19:0 are assumed + to be 0_0000h for the purposes of address comparison. The Host interface + positively decodes an address towards DRAM if the incoming address is less than + the value programmed in this register. + The Top of Low Usable DRAM is the lowest address above both Graphics Stolen + memory and Tseg. BIOS determines the base of Graphics Stolen Memory by + subtracting the Graphics Stolen Memory Size from TOLUD and further decrements + by Tseg size to determine base of Tseg. + This register must be 1MB aligned when reclaim is enabled. + +19:0 RO 00000h Core + RSVD (RSVD): + Reserved + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 20 + 1.1.12 MGGC - Mirror of GMCH Graphics Control Register +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset:9094-9097h +Default Value: 00000030h +Access: RO +Size: 32 bits +Mirror of GMCH Graphics Control Register: + Default + Bits Access Value RST/PWR Description +31:16 RO 0000h Core + RSVD (RSVD): + Reserved. + 15 RO 0b Core + FLR Capability Structure Select (FLRCSSEL): + 1: The Vendor Specific Capability Structure is selected for FLR. + 0: FLR uses the Standard Capability Structure with unique Capability ID assigned + by PCISIG. + 14 RO 0b Core + Versatile Acceleration Mode Enable (VAMEN): + Enables the use of the iGFX engines for Versatile Acceleration. + 1 - iGFX engines are in Versatile Acceleration Mode. Device 2 Class Code is + 048000h. + 0 - iGFX engines are in iGFX Mode. Device 2 Class Code is 030000h. + +13:10 RO 0000b Core + RSVD (RSVD): + Reserved. + 9:8 RO 0h Core + GTT Graphics Memory Size (GGMS): + This field selects the amount of Main Memory that is pre-allocated to support the + Internal Graphics Translation Table. The BIOS ensures that memory is pre- + allocated only when Internal graphics is enabled. + GSM is assumed to be a contiguous physical DRAM space with DSM, and the + BIOS needs to allocate a contiguous memory chunk. Hardware derives the base + of GSM from DSM only using the GSM size programmed in the register. + 0h: No memory pre-allocated. GTT cycles (Mem and I/O) are not claimed. + 1h: 1 MB of memory pre-allocated for GTT. + 2h: 2 MB of memory pre-allocated for GTT. + 3h: Reserved. + Hardware functionality in case of programming this value to Reserved is not + guaranteed. + This register is locked and becomes Read Only when the D_LCK bit in the + SMRAMC register is set. + 7:4 RO 3h Core + Graphics Mode Select (GMS): + This field selects the amount of Main Memory that is pre-allocated to support the + Internal Graphics device in VGA (non-linear) and Native (linear) modes. The BIOS + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 21 + Default +Bits Access Value RST/PWR Description + ensures that memory is pre-allocated only when Internal graphics is enabled. + 0h: No memory pre-allocated. Device 2 (IGD) does not claim VGA cycles (Mem + and I/O), and the Sub-Class Code field within Device 2 function 0 Class Code + register is 80. + 1h-4h: Reserved. + 5h-Dh: DVMT (UMA) mode, memory pre-allocated for frame buffer, in quantities + as shown in the Encoding table. + Eh-Fh: Reserved. + NOTE: This register is locked and becomes Read Only when the D_LCK bit in the + SMRAMC register is set. This register is also LT lockable. + Hardware does not clear or set any of these bits automatically based on IGD + being disabled/enabled. + BIOS Requirement: BIOS must not set this field to 0h if IVD (bit 1 of this register) + is 0. + Encoding Description + 0h No memory preallocated + 5h 32 MB + 6h 48 MB + 7h 64 MB + 8h 128 MB + 9h 256 MB + Ah 96 MB + Bh 160 MB + Ch 224 MB + Dh 352 MB + 3:2 RO 00b Core + RSVD (RSVD): + Reserved. + 1 RO 0b Core + IGD VGA Disable (IVD): + 0: Enable. Device 2 (IGD) claims VGA memory and I/O cycles, and the Sub-Class + Code field within Device 2 Class Code register is 00. + 1: Disable. Device 2 (IGD) does not claim VGA cycles (Mem and I/O), and the + Sub-Class Code field within Device 2 function 0 Class Code register is 80. + BIOS Requirement: BIOS must not set this bit to 0 if the GMS field (bits 6:4 of this + register) pre-allocates no memory. + This bit MUST be set to 1 if Device 2 is disabled either via a fuse or fuse override + (CAPID0[46] == 1) or via a register (DEVEN[3] == 0). + This register is locked by LT lock. + 0 RO 0b Core + RSVD (RSVD): + Reserved. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 22 + 1.1.13 TOUUD - Mirror of TOUUD +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 9098-909Fh +Default Value: 0000000000000000h +Access: RO +Size: 64 bits + +TOUUD + Bits Access Default Value RST/PWR Description +63:39 RO 0000000h Core + RSVD (RSVD): + Reserved +38:20 RO 0000000000000000000b Core + TOUUD LOW (TOUUD): + This register contains bits 38 to 20 of an address one byte above + the maximum DRAM memory above 4G that is usable by the + operating system. Configuration software must set this value to + TOM minus all EP stolen memory if reclaim is disabled. If reclaim + is enabled, this value must be set to reclaim limit 1MB aligned + since reclaim limit + 1byte is 1MB aligned. Address bits 19:0 are + assumed to be 000_0000h for the purposes of address + comparison. The Host interface positively decodes an address + towards DRAM if the incoming address is less than the value + programmed in this register and greater than 4GB. +19:0 RO 00000000000000000000b Core + RSVD (RSVD): + Reserved + + + +1.1.14 DSMB - Mirror of DSMBASE +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 90A0-90A3h +Default Value: 00000000h +Access: RO +Size: 32 bits + +DSM Base: + Default + Bits Access Value RST/PWR Description +31:20 RO 000h Core + DSM Base Lower 32 Bits (DSMBL): + This register contains bits 31 to 20 of the base address of stolen DRAM memory. + The BIOS determines the base of graphics stolen memory by subtracting the + graphics stolen memory size (PCI Device 0 offset 52 bits 6:4) from TOLUD (PCI + Device 0 offset BC bits 31:20). + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 23 + Default +Bits Access Value RST/PWR Description +19:0 RO 00000h Core + RSVD (RSVD): + Reserved + + + +1.1.15 GSMB - Mirror of GSMBASE +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 90A4-90A7h +Default Value: 00000000h +Access: RO +Size: 32 bits + +This register contains the base address of stolen DRAM memory for the GTT. The BIOS determines the +base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 52 +bits 11:8) from the Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20). + Default + Bits Access Value RST/PWR Description +31:20 RO 000h Core + GSM Base (GSMB): + This register contains the base address of stolen DRAM memory for the GTT. The + BIOS determines the base of GTT stolen memory by subtracting the GTT graphics + stolen memory size (PCI Device 0 offset 52 bits 11:8) from the Graphics Base of + Data Stolen Memory (PCI Device 0 offset B0 bits 31:20). + +19:0 RO 00000h Core + RSVD (RSVD): + Reserved + + + +1.1.16 GCMD - Mirror of Global Command Register + B/D/F/Type: 0/0/0/MBCunit_Config + Address Offset: 90CC-90CFh + Default Value: 00000000h + Access: RO + Size: 32 bits + Default +Bits Access Value RST/PWR Description + 31 RO 0b Core + Translation Enable (TE): + Software writes to this field to request hardware to enable/disable + DMA-remapping hardware. + 0: Disable DMA-remapping hardware. + 1: Enable DMA-remapping hardware. + Hardware reports the status of the translation enable operation + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 24 + through the TES field in the Global Status register. + Before enabling (or re-enabling) DMA-remapping hardware + through this field, software must: + 1. Setup the DMA-remapping structures in memory. + 2. Flush the write buffers (through the WBF field), if write buffer + flushing is reported as required. + 3. Set the root-entry table pointer in hardware (through the + SRTP field). + 4. Perform global invalidation of the context cache and global + invalidation of the IOTLB. + 5. If advanced fault logging is supported, setup the fault log + pointer (through the SFL field) and enable advanced fault + logging (through the EAFL field). + Refer to Section 9 for detailed software requirements. + There may be active DMA requests in the platform when software + updates this field. Hardware must enable or disable remapping + logic only at deterministic transaction boundaries, so that any in- + flight transaction is either subject to remapping or not at all. + Hardware implementations supporting DMA draining must drain + any in-flight translated DMA read/write requests queued within + the root complex before completing the translation enable + command and reflecting the status of the command through the + TES field in the GSTS_REG. + Reading this bit returns an undefined value. +30 RO 0b Core + Set Root Table Pointer (SRTP): + Software sets this field to set/update the root-entry table pointer + used by hardware. The root-entry table pointer is specified + through the Root-entry Table Address register. + Hardware reports the status of the "root table pointer set" + operation through the RTPS field in the Global Status register. + The root table pointer set operation must be performed before + enabling or re-enabling (after disabling) DMA remapping through + the TE field. + After a "root table pointer set" operation, software must globally + invalidate the context cache and then globally invalidate the + IOTLB. This is required to ensure hardware uses only the + remapping structures referenced by the new root table pointer, + and not any stale cached entries. + While DMA remapping is active, software may update the root + table pointer through this field. However, to ensure valid in-flight + DMA requests are deterministically remapped, software must + ensure that the structures referenced by the new root table + pointer are programmed to provide the same remapping results + as the structures referenced by the previous root-table pointer. + Clearing this bit has no effect. Reading this bit returns an + undefined value. +29 RO 0b Core + Set Fault Log (SFL): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 25 + This field is valid only for implementations supporting advanced + fault logging. + Software sets this field to request hardware to set/update the + fault-log pointer used by hardware. + The fault-log pointer is specified through the Advanced Fault Log + register. + Hardware reports the status of the fault log set operation through + the FLS field in the Global Status register. + The fault log pointer must be set before enabling advanced fault + logging (through the EAFL field). Once advanced fault logging is + enabled, the fault log pointer may be updated through this field + while DMA remapping is active. + Clearing this bit has no effect. Reading this bit returns an + undefined value. +28 RO 0b Core + Enable Fault Logging (EAFL): + This field is valid only for implementations supporting advanced + fault logging. + Software writes to this field to request hardware to enable or + disable advanced fault logging. + 0: Disable advanced fault logging. In this case, translation faults + are reported through the Fault Recording registers. + 1: Enable use of memory-resident fault log. + When enabled, translation faults are recorded in the memory- + resident log. The fault log pointer must be set in hardware + (through the SFL field) before enabling advanced fault logging. + Hardware reports the status of the advanced fault logging enable + operation through the AFLS field in the Global Status register. + Reading this bit returns an undefined value. + +27 RO 0b Core + Write Buffer Flush (WBF): + This bit is valid only for implementations requiring write buffer + flushing. + Software sets this field to request hardware to flush the root- + complex internal write buffers. This is done to ensure any + updates to the memory-resident remapping structures are not + held in any internal write posting buffers. + Refer to Section 11.1 for details on write-buffer flushing + requirements. + Hardware reports the status of the write buffer flushing operation + through the WBFS field in the Global Status register. + Clearing this bit has no effect. Reading this bit returns an + undefined value. +26 RO 0b Core + Queued Invalidation Enable (QIE): + This field is valid only for implementations supporting queued + invalidations. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 26 + Software writes to this field to enable or disable queued + invalidations. + 0: Disable queued invalidations. + 1: Enable queued invalidations. + Hardware reports the status of queued invalidation enable + operations through the QIES field in the Global Status register. + Refer to Section 6.2.2 for software requirements for + enabling/disabling queued invalidations. + Reading this bit returns an undefined value. +25 RO 0b Core + Interrupt Remapping Enable (IRE): + This field is valid only for implementations supporting interrupt + remapping. + 0: Disable interrupt-remapping hardware + 1: Enable interrupt-remapping hardware + Hardware reports the status of the interrupt remapping enable + operation through the IRES field in the Global Status register. + There may be active interrupt requests in the platform when + software updates this field. Hardware must enable or disable + interrupt-remapping logic only at deterministic transaction + boundaries, so that any in-flight interrupts are either subject to + remapping or not at all. + Hardware implementations must drain any in-flight interrupts + requests queued in the Root-Complex before completing the + interrupt-remapping enable command and reflecting the status of + the command through the IRES field in the Global Status register. + Reading this bit returns an undefined value. + +24 RO 0b Core + Set Interrupt Remap Table Pointer (SIRTP): + This field is valid only for implementations supporting interrupt- + remapping. + Software sets this field to set/update the interrupt remapping + table pointer used by hardware. The interrupt remapping table + pointer is specified through the Interrupt Remapping Table + Address register. + Hardware reports the status of the interrupt remapping table + pointer set operation through the IRTPS field in the Global Status + register. + The interrupt remap table pointer set operation must be + performed before enabling or re-enabling (after disabling) + interrupt-remapping hardware through the IRE field. + After an interrupt remap table pointer set operation, software + must globally invalidate the interrupt entry cache. This is required + to ensure hardware uses only the interrupt-remapping entries + referenced by the new interrupt remap table pointer, and not any + stale cached entries. + While interrupt remapping is active, software may update the + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 27 + interrupt remapping table pointer through this field. However, to + ensure valid in-flight interrupt requests are deterministically + remapped, software must ensure that the structures referenced + by the new interrupt remap table pointer are programmed to + provide the same remapping results as the structures referenced + by the previous interrupt remap table pointer. + Clearing this bit has no effect. Reading this bit returns an + undefined value. +23 RO 0b Core + Compatibility Format Interrupt (CFI): + This field is valid only for Intel(R)64 implementations supporting + interrupt-remapping. + Software writes to this field to enable or disable Compatibility + Format interrupts on Intel(R)64 platforms. The value in this field is + effective only when interrupt-remapping is enabled and Legacy + Interrupt Mode is active. + 0: Block Compatibility format interrupts. + 1: Process Compatibility format interrupts as pass-throughs + (bypass interrupt remapping). + Hardware reports the status of updating this field through the + CFIS field in the Global Status register. + Refer to Section 5.4.1 for details on Compatibility Format interrupt + requests. + The value returned on a read of this field is undefined. + This field is not implemented on Itanium(TM) implementations. + +22:0 RO 000000h Core + RSVD (RSVD): + Reserved + + + +1.1.17 GTTMMADR - Mirror of Graphics Translation Table and + Memory Mapped Range Address +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 9124-912Bh +Default Value: 0000000000000000h +Access: RO +Size: 64 bits + +This register requests allocation for the combined Graphics Translation Table Modification Range and +Memory Mapped Range. The range requires 4 MB combined for MMIO and Global GTT aperture, with +2MB of that used by MMIO and 2MB used by GTT. GTTADR begins at (GTTMMADR + 2 MB) while the +MMIO base address is the same as GTTMMADR. +For the Global GTT, this range is defined as a memory BAR in graphics device config space. It is an alias +into which software is required to write Page Table Entry values (PTEs). Software may read PTE values +from the global Graphics Translation Table (GTT). PTEs cannot be written directly into the global GTT +memory area. + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 28 + The device snoops writes to this region to invalidate any cached translations within the various TLBs +implemented on-chip. There are some exceptions to this - see GTT-TLB in the Programming Interface +chapter. +The allocation is for 4MB and the base address is defined by bits [38:22]. + Bits Access Default Value RST/PWR Description +63:39 RO 0000000h Core + RSVD (RSVD): + Reserved +38:22 RO 00000000000000000b Core + Memory Base Address (MMADR): + Set by the OS, these bits correspond to address signals [38:22]. + 4MB combined for MMIO and Global GTT table aperture (2MB for + MMIO and 2 MB for GTT). +21:4 RO 000000000000000000b Core + RSVD (RSVD): + Reserved + 3 RO 0b Core + Prefetchable Memory (PREFMEM): + Hardwired to 0 to prevent prefetching. + + 2:1 RO 00b Core + Memory Type (MEMTYP): + 00b: To indicate 32 bit base address + 01b: Reserved + 10b: To indicate 64 bit base address + 11b: Reserved + 0 RO 0b Core + Memory I/O Space (MIOS): + Hardwired to 0 to indicate memory space. + + + +1.1.18 PCICMD - Mirror of PCICMD MAE/BME +B/D/F/Type: 0/0/0/MBCunit_Config +Address Offset: 912C-912Fh +Default Value: 00000000h +Access: RW +Size: 32 bits + +Mirror of PCICMD MAE/BME: + Default + Bits Access Value RST/PWR Description +31:11 RW 000000h Core + RSVD (RSVD): + Reserved. + 10 RW 0b Core + Interrupt Disable (INTDIS): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 29 + Default +Bits Access Value RST/PWR Description + This bit disables the device from asserting INTx#. + 0: Enable the assertion of this device's INTx# signal. + 1: Disable the assertion of this device's INTx# signal. DO_INTx messages are + not sent to DMI. + GSA Implementation: + When 1, blocks the sending of a MSI interrupt and blocks the sending of a Line + interrupt. (The interrupt status is not blocked from being reflected in the INTSTS + bit.) + When 0, permits the sending of a MSI interrupt or Line interrupt. + 9 RW 0b Core + Fast Back to Back (FB2B): + Not Implemented. Hardwired to 0. + 8 RW 0b Core + SERR Enable (SERRE): + Not Implemented. Hardwired to 0. + + 7 RW 0b Core + Address/Data Stepping Enable (ADSPTEP): + Not Implemented. Hardwired to 0. + 6 RW 0b Core + Parity Error Enable (PERRE): + Not Implemented. Hardwired to 0. Since the IGD belongs to the category of + devices that does not corrupt programs or data in system memory or hard drives, + the IGD ignores any parity error that it detects and continues with normal + operation. + 5 RW 0b Core + Video Pallete Snooping (VPS): + This bit is hardwired to 0 to disable snooping. + 4 RW 0b Core + Memory Write and Invalidate Enable (MWIE): + Hardwired to 0. The IGD does not support memory write and invalidate + commands. + + 3 RW 0b Core + Special Cycle Enable (SCE): + This bit is hardwired to 0. The IGD ignores Special cycles. + 2 RW 0b Core + Bus Master Enable (BME): + 0: Disable IGD bus mastering. + 1: Enable the IGD to function as a PCI compliant master. + GSA Implementation: + 0: Disable sending MSI interrupts. + 1: Enable sending MSI interrupts. + (Note: See descriptions of INTDIS, MSE, and INTSTS bits.) + 1 RW 0b Core + Memory Access Enable (MAE): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 30 + Default +Bits Access Value RST/PWR Description + This bit controls the IGD's response to memory space accesses. + 0: Disable. + 1: Enable. + 0 RW 0b Core + I/O Access Enable (IOAE): + This bit controls the IGD's response to I/O space accesses. + 0: Disable. + 1: Enable. + + + +1.1.19 PERFCNT1 - Performance Counter 1 +B/D/F/Type: 0/2/0/MMADR_MBCunit_Config +Address Offset: 91B8-91BFh +Default Value: 0000000000000000h +Access: RO, RW +Size: 64 bits + +GT implements two general purpose counters each with 44 bits. Each counter can be programmed to +count one main event out of set of events (see the event list). Some events are simple duration events +and some are edge detects (0=>1 transition is counted). The nature of the event is also programmed to +the register that allocates the counter value. +Bits Access Default Value RST/PWR Description + 63 RW 0b Core + Counter 1 Enable (CNT1EN): + Counter#1 Enable + 0: Counter is disabled, the count value is not deterministic. + 1: Counter is enabled. Once enabled, the counter is activated if the global + enable (from NCU is also asserted). + + 62 RW 0b Core + Overflow Enable (OVFEN): + Overflow Enable + 0: Overflow reporting is enabled. + 1: Overflow reporting is disabled. + 61 RW 0b Core + Edge Detect (EDGEDET): + Edge Detect: + 0: Edge detect is enabled. + 1: Edge detect is disabled. + 60 RW 0b Core + Counter Clear (CNTCLR): + Counter Clear. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 31 + Bits Access Default Value RST/PWR Description +59:52 RW 00000000b Core + Event Selection (EVENTSEL): + Event Selection: The event list (see attached). Used as a MUX control to + select the event to Counter. +51:44 RO 00000000b Core + RSVD (RSVD): + Reserved. +43:0 RO 00000000000h Core + Counter Value (CNTVALUE): + The Counter Value: This is the field where the counter value can be + observed via a simple read from the register. + + + +1.1.20 PERFCNT2 - Performance Counter 2 +B/D/F/Type: 0/2/0/MMADR_MBCunit_Config +Address Offset: 91C0-91C7h +Default Value: 0000000000000000h +Access: RO, RW +Size: 64 bits + +GT implements two general purpose counters each with 44 bits. Each counter can be programmed to +count one main event out of the set of events (see the event list). Some events are simple duration +events and some are edge detects (0=>1 transition is counted). The nature of the event is also +programmed to the register that allocates the counter value. +Bits Access Default Value RST/PWR Description + 63 RW 0b Core + Counter 2 Enable (CNT2EN): + Counter#2 Enable + 0: Counter is disabled, the count value is not deterministic. + 1: Counter is enabled. Once enabled, the counter is activated if the global + enable (from NCU is also asserted). + + 62 RW 0b Core + Overflow Enable (OVFEN): + Overflow Enable + 0: Overflow reporting is enabled. + 1: Overflow reporting is disabled. + 61 RW 0b Core + Edge Detect (EDGEDET): + Edge Detect: + 0: Edge detect is enabled. + 1: Edge detect is disabled. + 60 RW 0b Core + Counter Clear (CNTCLR): + Counter Clear. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 32 + Bits Access Default Value RST/PWR Description +59:52 RW 00000000b Core + Event Selection (EVENTSEL): + Event Selection: The event list (see attached). Used as a MUX control to + select the event to Counter. +51:44 RO 00000000b Core + RSVD (RSVD): + Reserved. +43:0 RO 00000000000h Core + Counter Value (CNTVALUE): + The Counter Value: This is the field where the counter value can be + observed via a simple read from the register. + + + +1.1.21 PERFMATRIX - Performance Matrix Events +B/D/F/Type: 0/2/0/MMADR_MBCunit_Config +Address Offset: 91C8-91CFh +Default Value: 0000000000000000h +Access: RW, RO +Size: 64 bits + +Performance Matrix Events: + Default + Bits Access Value RST/PWR Description +63:38 RO 0000000h Core + RSVD (RSVD): + Reserved. + 37 RW 0b Core + NON Dram (NONDRAM): + Non DRAM - Target was non-DRAM system address. + 36 RW 0b Core + Hit Modified (HITM): + A snoop was needed and it HitMed in local or remote cache. HitM denotes a + cache-line was modified before snoop effect. This includes: + -Snoop HitM w/ Invalidation and WB (LLC miss, CRD/DRD) + -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) + -Snoop MtoS (LLC Hit, CRD/DRD) + 35 RW 0b Core + Hit with Forward (HITFWD): + A snoop was needed and data was Forwarded from a remote socket. + -Snoop Forward Clean, Left Shared (LLC Miss, CRD/DRD) + + 34 RW 0b Core + Hit No Forward (HITNOFWD): + A snoop was needed and it Hits in at least one snooped cache. Hit denotes a + cache-line was valid before snoop effect. This includes: + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 33 + Default +Bits Access Value RST/PWR Description + -Snoop Hit w/ Invalidation (LLC Hit, RFO) + -Snoop Hit, Left Shared (LLC Hit/Miss, CRD/DRD) + -Snoop Forward Clean w/ Invalidation (LLC Miss, RFO) + 33 RW 0b Core + SNOOP Miss (SMISS): + A snoop was need and it missed all snooped caches: + -For LLC Hit, ResIHitI was returned by all cores + -For LLC Miss, RspI was returned by all sockets + 32 RW 0b Core + NO Snoop Was needed (NOSNP): + No snoop was neeeded to satisfy the request. + + 31 RW 0b Core + NONE - No Details as to Snoop related infor (NONE): + NONE - No Details as to Snoop related information. + 30 RW 0b Core + NID7 (NID 7): + NID 7 + 29 RW 0b Core + NID6 (NID 6): + NID 6 + 28 RW 0b Core + NID5 (NID 5): + NID 5 + + 27 RW 0b Core + NID4 (NID 4): + NID 4 + 26 RW 0b Core + NID3 (NID 3): + NID 3 + 25 RW 0b Core + NID2 (NID 2): + NID 2 + 24 RW 0b Core + NID1 (NID 1): + NID 1 + + 23 RW 0b Core + NID0 (NID0): + NID 0 + 22 RW 0b Core + Local Node (LOCALNODE): + Local Node. + 21 RW 0b Core + F-STATE (FSTATE): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 34 + Default +Bits Access Value RST/PWR Description + F-STATE + 20 RW 0b Core + S-State (SSTATE): + S-State + 19 RW 0b Core + E-STATE (ESTATE): + E-STATE + + 18 RW 0b Core + M-STATE (MSTATE): + M-state + 17 RW 0b Core + No Supplier Details (NONE): + No Supplier Details. + 16 RW 0b Core + Snoop Response from Uncore (SNPRSP): + Account for any snoop response from Uncore. + 15 RW 0b Core + IDI requests (ANYIDIREQ): + Any - any requests that crosses IDI. + +14:12 RO 000b Core + RSVD (RSVD): + Reserved. + 11 RW 0b Core + WCIL AND WCILF (WCIL): + Write Combining. + 10 RW 0b Core + LOCK (LCKSPLIT): + Locks – count locks and split lock requests. + 9 RW 0b Core + MLC Prefetch to LLC (LLCPREFCODE): + MLC prefetch to LLC - Code. + + 8 RW 0b Core + LLCRFO (LLCPREFRFO): + MLC prefetch to LLC - RFO. + 7 RW 0b Core + MLC Prefetch to LLC (LLCPREFDATA): + MLC prefetch to LLC - Load (exclude LRUhints). + 6 RW 0b Core + MPL RFOs (PFRFO): + PF Ifetch = MPL Fetches. + 5 RW 0b Core + PF Ifetch (PFFETCH): + PF Ifetch = MPL Fetches. + 4 RW 0b Core + MPL Reads (PFDATARD): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 35 + Default +Bits Access Value RST/PWR Description + PF Data Rd = MPL Reads. + 3 RW 0b Core + Write Back (DCUWB): + Writeback = MLC_EVICT/DCUWB. + 2 RW 0b Core + Demand Ifetch (IFUFETCH): + Demand Ifetch = IFU Fetches. + + 1 RW 0b Core + Demand RFO (DCURFO): + Demand RFO = DCU RFOs. + 0 RW 0b Core + Demand Data Rd (DATARD): + Demand Data Rd = DCU reads (exclude partials). + + + +1.2 MBCunit Message + Register Name Register Symbol Register Start Register End Default Value Access +IDI MESSAGES IDIMSG 8500h 8503h 00000000h RO, RW +BOOT VECTOR BOOTMSG 8504h 8507h 00000000h RO, RW +GFX / DPR Update Message Bits GFXPMRDPR 8508h 850Bh 00000000h RO, RW +IDI Lookup Register 1 IDILK1 8510h 8513h 00000000h RW, RO +IDI Lookup Register 2 IDILK2 8514h 8517h 00000000h RW, RO + + +1.2.1 IDIMSG - IDI MESSAGES +B/D/F/Type: 0/0/0/MBCunit_Message +Address Offset: 8500-8503h +Default Value: 00000000h +Access: RO, RW +Size: 32 bits +BIOS Optimal Default 00h + +IDI Message: + Default + Bits Access Value RST/PWR Description +31:16 RO 0000h Core + Mask Bits (MASKB): + Reserved +15:11 RO 0h Reserved (RSVD) + 10 RW 0b Core + MBC Busy ACK (BUSYACK): + 1 - Busy ACK from GPMunit(Non-Idle). + 0 - Non Busy ACK from Gpmunit (Idle). + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 36 + Default +Bits Access Value RST/PWR Description + This bit is valid only if bit 26 of this register is set. + 9 RW 0b Core + VTD Invalidation (VTDINV): + VTD invalidation from SA. This bit is valid only if bit 25 of this register is set. + 8 RW 0b Core + VTD Enable and Disable (VTDED): + VTD Enable and Disable message from SA. This bit is valid only if bit 24 of this + register is set. + + 7 RO 0b Core + RSVD (RSVD): + RSVD. + 6 RW 0b Core + CPD Entry and Exits (CPD): + CPD Entry and Exit indication. This bit is valid only if bit 22 of this register is + set. + CPD Entry = 1. + CPD Exit = 0. + 5 RW 0b Core + Unblock MMIO ack (UNBLKACK): + Unblock MMIO ACK coming from SA. This bit is valid only if bit 21 of this + register is set. + 4 RW 0b Core + Mbcunit Arbitration request/Release ACK (ARBREQRELACK): + Arbitration request is sent during the MAE update. The ack is received from + GPMunit. + This bit is valid only if bit 20 of this register is set. + Arb req ack = 1. + Arb release ack = 0. + + 3 RW 0b Core + IDI Shutdown request (IDISD): + IDI Shutdown Request from GPM to MBCunit. This bit is valid only if bit 19 of + this register is set. + 2 RW 0b Core + IDI Wakeup Message (IDIWK): + IDI wakeup message from PM to MBCunit. This bit is valid only if bit 18 of this + register is set. + 1 RW 0b Core + Credit Active De-assertreq ACK (CDA): + Credit Active De-assertreq ACK - GPMunit sends to the MBCunit. + This bit is valid only if bit 17 of this register is set. + 0 RO 0b Core + RSVD (RSVD): + Reserved + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 37 + 1.2.2 BOOTMSG - BOOT VECTOR +B/D/F/Type: 0/0/0/MBCunit_Message +Address Offset: 8504-8507h +Default Value: 00000000h +Access: RO, RW +Size: 32 bits + + + + Bits Access Default Value RST/PWR Description +31:30 RO 00b Core Reserved (RSVD) +29:26 RW 0000b Core + APICID (APICID): + Place holder for APIC ID +25:21 RW 00000b Core + Way Number for C6 (WC6): + Way Marker for C6 Save area +20:17 RW 0000b Core + Slice Marker for C6 save area (SLC6): + Slice Marker for C6 Save area + + 16 RO 0b Core Reserved (RSVD) +15:9 RW 0000000b Core + C6 Area Pointer (C6PTR): + C6 Area Pointer + 8 RW 0b Core Patch Restore (PR) + 7 RW 0b Core APIC RESTORE (APR) + 6 RW 0b Core Core Content Restore (CCR) + 5:4 RW 00b Core Reset Type Register (RTYP) + 3:0 RW 0000b Core Ring Stop ID (RID) + + +1.2.3 GFXPMRDPR - GFX/DPR Update Message Bits +B/D/F/Type: 0/0/0/MBCunit_Message +Address Offset: 8508-850Bh +Default Value: 00000000h +Access: RO, RW +Size: 32 bits + +This is the GFX, and DPR update Message from SA. The MBCunit does the needed operation whenever +there is an Update. + Bits Access Default Value RST/PWR Description +31:16 RO 0000h Core Mask Bits (MB): + 15:8 RO 00000000b Core + RSVD (RSVD): + Reserved + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 38 + Bits Access Default Value RST/PWR Description + 7 RW 0b Core + VCSFLUSH ACK (VCSFLSHACK): + VCS to MBC Flush ACK message. + 6 RW 0b Core + BCS2MBCFLSH ACK (BCSFLSHACK): + BCS2MBC Flush ACK message. + 5 RW 0b Core + CS2MBC Flush ACK (CSFLSHACK): + CS 2 MBC Flush ACK Message Bit. + 4 RW 0b Core + VCS to MBC stop execution ACK (VCSSTOPEXACK): + BCS to MBC stop execution ACK message. + + 3 RW 0b Core + BCS to MBC Stop Execution ACK (BCSSTOPEXACK): + BCS to MBC stop execution ACK. + 2 RW 0b Core + CS MBC VTD Stop Ex ACK (CSSTOPACK): + CS to MBC ACK message for stopping the Execution of CS. + 1 RW 0b Core + DPR Update (DPRED): + DPR Update - Valid with Mask bit 17th. + + + +1.2.4 IDILK1 - IDI Lookup Register 1 +B/D/F/Type: 0/0/0/MBCunit_Message +Address Offset: 8510-8513h +Default Value: 00000000h +Access: RW, RO +Size: 32 bits + +IDI Lookup Register 1: + Default + Bits Access Value RST/PWR Description +31:17 RO 0000h Core + Reserved (RSVD): + Reserved. +16:13 RW 0000b Core + GT Logical ID (LOGID): + Logical ID for GT. + 12 RO 0b Core + RSVD for SA (RSVD): + Reserved for SA slice. + 11 RW 0b Core + Colloc bit for SA Slice (CBSA): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 39 + Default +Bits Access Value RST/PWR Description + Co-located indicates that the Collocated Cbo should receive this request. + 10 RW 0b Core + Direction Bit for SA (DBSA): + In Half ring uncore topologies this bit indicates if the request needs to be driven + on the Up going (1) or the Down going (0) ring direction. For Full ring it indicates + clockwise (1) or counterclockwise (0) directions. + 1: Going Up. + 0: Going Down. + 9 RW 0b Core + Polarity bit for SA Slice (PBSA): + Polarity based on the current core Slice ID and the Destination Cbo ID - should + this request be sent to the rings in Even or Odd cycles (this is basically the + Distance between the source and destination). + 1 - Even. + 0 - Odd. + + 8 RW 0b Core + For Me bit for SA (FMSA): + The next slice the Target of this request (MyNeighborId == DestCboId). + 7:4 RW 0000b Core + Number of LLC SA Slices (LLCNUMSLICE): + Number of Slice information in the system. + This register contains the number of LLC cache slices on the RING. + Default: 0000b + 3:0 RW 0000b Core + Colocated Slice ID for GT (CLSID): + This register contains the ID of the slice that is servicing GT’s co-located cycles. + The default is for slice0 to service GT. + + + +1.2.5 IDILK2 - IDI Lookup Register 2 +B/D/F/Type: 0/0/0/MBCunit_Message +Address Offset: 8514-8517h +Default Value: 00000000h +Access: RW, RO +Size: 32 bits + +IDI Lookup Register 2: + Default + Bits Access Value RST/PWR Description +31:30 RO 00b Core + RSVD (RSVD): + Reserved. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 40 + Default +Bits Access Value RST/PWR Description + 29 RO 0b Core + Reserved for Slice 5 (RSVD): + Reserved for Slice 5. + 28 RW 0b Core + Colloc bit for Slice 5 (CBS5): + Co-located indicates that the Collocated Cbo should receive this request. + 27 RW 0b Core + Direction bit for Slice 5 (DBS5): + In Half ring uncore topologies this indicates: + 1: Going Up. + 0: Going Down. + + 26 RW 0b Core + Polarity bit for Slice 5 (PBS5): + Polarity based on the current core Slice ID and the Destination Cbo ID - should + this request be sent to the rings in Even or Odd cycles (this is basically the + Distance between the source and destination). + 1 - Even. + 0 - Odd. + 25 RW 0b Core + For Me for Slice 5 (FMS5): + The next slice the Target of this request (MyNeighborId == DestCboId ) + 24 RO 0b Core + Reserved for Slice 4 (RSVD): + Reserved. + 23 RW 0b Core + Colloc bit for Slice 4 (CBS4): + Co-located indicates that the Collocated Cbo should receive this request. + + 22 RW 0b Core + Direction bit for Slice 4 (DBS4): + In Half ring uncore topologies this indicates: + 1: Going Up. + 0: Going Down. + 21 RW 0b Core + Polarity Bit for Slice 4 (PBS4): + Polarity based on the current core Slice ID and the Destination Cbo ID - should + this request be sent to the rings in Even or Odd cycles (this is basically the + Distance between the source and destination). + 1 - Even. + 0 - Odd. + 20 RW 0b Core + For Me bit for Slice 4 (FMS4): + The next slice the Target of this request (MyNeighborId == DestCboId). + 19 RW 0b Core + Reserved for Slice 3 (RSVD): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 41 + Default +Bits Access Value RST/PWR Description + Reserved for Slice 3. + 18 RW 0b Core + Colloc bit for Slice 3 (CBS3): + Co-located indicates that the Collocated Cbo should receive this request. + 17 RW 0b Core + Direction bit for S3 (DBS3): + In Half ring uncore topologies this indicates: + 1: Going Up. + 0: Going Down. + + 16 RW 0b Core + Polarity Bit for Slice 3 (PBS3): + Polarity based on the current core Slice ID and the Destination Cbo ID - should + this request be sent to the rings in Even or Odd cycles (this is basically the + Distance between the source and destination). + 1 - Even. + 0 - Odd. + 15 RW 0b Core + For Me Bit for Slice 3 (FMS3): + The next slice the Target of this request (MyNeighborId == DestCboId). + 14 RO 0b Core + Reserved for Slice 2 (RSVD): + Reserved for Slice2. + 13 RW 0b Core + Colloc bit for Slice 2 (CBS2): + Co-located indicates that the Collocated Cbo should receive this request. + + 12 RW 0b Core + Direction Bit for Slice 2 (DBS2): + In Half ring uncore topologies this indicates: + 1: Going Up. + 0: Going Down. + 11 RW 0b Core + Polarity Bit for Slice 2 (PBS2): + Polarity based on the current core Slice ID and the Destination Cbo ID - should + this request be sent to the rings in Even or Odd cycles (this is basically the + Distance between the source and destination). + 1 - Even. + 0 - Odd. + 10 RW 0b Core + For me Bit for Slice 2 (FMS2): + The next slice the Target of this request (MyNeighborId == DestCboId). + 9 RO 0b Core + Reserved bit for Slice 1 (RSVD): + Reserved for Slice1. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 42 + Default +Bits Access Value RST/PWR Description + 8 RW 0b Core + Colloc Bit for Slice 1 (CBS1): + Co-located indicates that the Collocated Cbo should receive this request. + 7 RW 0b Core + Direction Bit for Slice 1 (DBS1): + In Half ring uncore topologies this indicates: + 1: Going Up. + 0: Going Down. + 6 RW 0b Core + Polarity Bit for Slice 1 (PBS1): + Polarity based on the current core Slice ID and the Destination Cbo ID - should + this request be sent to the rings in Even or Odd cycles (this is basically the + Distance between the source and destination). + 1 - Even. + 0 - Odd. + + 5 RW 0b Core + For Me Bit for Slice 1 (FMS1): + The next slice the Target of this request (MyNeighborId == DestCboId). + 4 RO 0b Core + Reserved for Slice 0 (RSVD): + Reserved for Slice 0. + 3 RW 0b Core + Colloc Bit for Slice 0 (CBS0): + Co-located indicates that the Collocated Cbo should receive this request. + 2 RW 0b Core + Direction Bit in Slice0 (DBS0): + Direction bit for Slice0: + In Half ring uncore topologies this indicates if the reqeust needs to be driven on + the Up going (1) or the Down going (0) ring direction. For Full ring it indicates + clockwise (1) or counterclockwise (0) directions. + 1: Going Up. + 0: Going Down. + + 1 RW 0b Core + Polarity Bit for Slice 0 (PBS0): + Polarity based on the current core Slice ID and the Destination Cbo ID - should + this request be sent to the rings in Even or Odd cycles (this is basically the + Distance between the source and destination). + 1 - Even. + 0 - Odd. + 0 RW 0b Core + For Me bit for Slice0 (FMS0): + The next slice the Target of this request (MyNeighborId == DestCboId). + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 43 + 1.3 GDTunit Config Space + Register Name Register Symbol Register Start Register End Default Value Access +PSMI Base Register PSMIBase 9870 9873 00000000h RW +PSMI Control PSMICtrl 9874 9877 00000000h RO, RW/L +PSMI Status PSMIStatus 9878 987C 0000000000h RO + + +1.3.1 PSMIBase - PSMI Base Register +B/D/F/Type: 0/2/0/MMADR_GDTunit_Config +Address Offset: 9870-9873h +Default Value: 00000000h +Access: RW +Size: 32 bits + +Host Physical Address of the PSMI Base of GT: +Bits Access Default Value RST/PWR Description +31:0 RW 00000000h Core PSMI Base of GT (ADDR). + + +1.3.2 PSMICtrl - PSMI Control +B/D/F/Type: 0/2/0/MMADR_GDTunit_Config +Address Offset: 9874-9877h +Default Value: 00000000h +Access: RO, RW/L +Size: 32 bits + +PSMI Control: +Bits Access Default Value RST/PWR Description +31:4 RO 0000000h Core Reserved (RSVD). + 3 RW/L 0b Core + Status of GT Sync (PSMISYNC): + Handler checks whether there is a need to sync the GT content. + 2 RW/L 0b Core Start PSMI Context Restore (PSMICON): + Before sending the PSMI restore request, poll until + 12050h[4] == 1 AND 22050h[4] == 1. + 1 RW/L 0b Core Start PSMI Context Save (PSMIRES). + 0 RW/L 0b Core + AS1/AS2 Mode PSMI (Sync Mode) (PSMISEL): + 0: AS1 Mode PSMI - Sync Mode. + 1: AS2 Mode PSMI - Scan Chain Based Approach. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 44 + 1.3.3 PSMIStatus - PSMI Status +B/D/F/Type: 0/2/0/MMADR_GDTunit_Config +Address Offset: 9878-987Ch +Default Value: 0000000000h +Access: RO +Size: 40 bits +BIOS Optimal Default: 0h + +PSMI Status: + Bits Access Default Value RST/PWR Description +39:32 RO 0h Reserved (RSVD) + 31:2 RO 000000000000000000000000000000b Core + Reserved (RSVD): + Reserved. + 1 RO 0b Core + Context Restore Done Status (PSMICNT): + 1: Context Restore Is Done. + 0: Context Restore is Not Done. + 0 RO 0b Core + Reserved (RSVD): + Reserved. + + + +1.4 GCPunit Config Register Space + Register Register Register Default + Register Name Symbol Start End Value Access +Unit Level Clock Gating Control 1 UCGCTL1 9400 9403 02F00000h RW +Unit Level Clock Gating Control 2 UCGCTL2 9404 9407 00000000h RW +Unit Level Clock Gating Control 3 UCGCTL3 9408 940B 04000000h RW +Unit Level Clock Gating Control 4 UCGCTL4 940C 940F 00000003h RO, RW +RAM Clock Gating Control 1 RCGCTL1 9410 9413 00000180h RW, RO +RAM Clock Gating Control 2 RCGCTL2 9414 9417 00000000h RW, RO +Integrated Power Supply Frequency IFDIMCTL 9418 941B 00000000h RO, RW +Domain +Impedance Meter Controls +Graphics Device Reset Control GDRST 941C 941F 00000000h RWHC, + RO +Misc. Reset Control Register RSTCTL 9420 9423 00000000h RW, RO +Misc. Clocking/Reset Control Registers MISCCPCTL 9424 9427 00000000h RW + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 45 + 1.4.1 UCGCTL1 - Unit Level Clock Gating Control 1 +B/D/F/Type: 0/2/0/MMADR_GCPunit_Config +Address Offset: 9400-9403h +Default Value: 02F00000h +Access: RW +Size: 32 bits + +Unit Level Clock Gating Control Registers. + Default +Bits Access Value RST/PWR Description + 31 RW 0b Core + ISCunit Clock Gating Disable (cg3ddisisc): + ISCunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +30 RW 0b Core + IEFunit Clock Gating Disable (cg3ddisief): + IEFunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + +29 RW 0b Core + IECPunit Clock Gating Disable (cg3ddisiecp): + IECPunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can + be gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +28 RW 0b Core + ICunit Clock Gating Disable (cg3ddisic): + ICunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +27 RW 0b Core + HIZunit Clock Gating Disable (cg3ddishiz): + HIZunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +26 RW 0b Core + GWunit Clock Gating Disable (cg3ddisgw): + GWunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + +25 RW 1b Core + GTIunit Clock Gating Disable (cg3ddisgti): + GTI Units Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can + be gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 46 + Default +Bits Access Value RST/PWR Description + 24 RW 0b Core + GSunit Clock Gating Disable (cg3ddisgs): + GSunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +23 RW 1b Core + GPMunit Clock Gating Disable (cg3ddisgpm): + GPMunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can + be gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +22 RW 1b Core + GAMunit Clock Gating Disable (cg3ddisgam): + GAMunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can + be gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + +21 RW 1b Core + GACunit Clock Gating Disable (cg3ddisgac): + GACunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can + be gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +20 RW 1b Core + GABunit Clock Gating Disable (cg3ddisgab): + GABunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +19 RW 0b Core + FTunit Clock Gating Disable (cg3ddisft): + FTunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +18 RW 0b Core + FLunit Clock Gating Disable (cg3ddisfl): + FLunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + +17 RW 0b Core + EU_MSunit Clock Gating Disable (cg3ddiseu_ms): + EU_MSunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can + be gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +16 RW 0b Core + EU_MDunit Clock Gating Disable (cg3ddiseu_md): + EU_MDunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can + be gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +15 RW 0b Core + EU_IFunit Clock Gating Disable (cg3ddiseu_if): + EU_IFunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can + be gated when they are not required to toggle for functionality)1: Clock Gating + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 47 + Default +Bits Access Value RST/PWR Description + Disabled. (i.e., clocks are toggling, always) +14 RW 0b Core + EU_GAunit Clock Gating Disable (cg3ddiseu_ga): + EU_GAunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can + be gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +13 RW 0b Core + EUunit Clock Gating Disable (cg3ddiseu): + EUunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + +12 RW 0b Core + EMunit Clock Gating Disable (cg3ddisem): + EMunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + This bit must be 1. +11 RW 0b Core + DTunit Clock Gating Disable (cg3ddisdt): + DTunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) +10 RW 0b Core + DMunit Clock Gating Disable (cg3ddisdm): + DMunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + 9 RW 0b Core + DGunit Clock Gating Disable (cg3ddisdg): + DGunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + {W/A}]: This bit must be 1. + + 8 RW 0b Core + DAPunit Clock Gating Disable (cg3ddisdap): + DAPunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + 7 RW 0b Core + CSunit Clock Gating Disable (cg3ddiscs): + CSunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + 6 RW 0b Core + CLunit Clock Gating Disable (cg3ddiscl): + CLunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 48 + Default +Bits Access Value RST/PWR Description + Disabled. (i.e., clocks are toggling, always) + 5 RW 1b Core + BLBunit Clock Gating Disable (cg3ddisblb): + BLBunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + 4 RW 0b Core + BFunit Clock Gating Disable (cg3ddisbf): + BFunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + + 3 RW 0b Core + BDunit Clock Gating Disable (cg3ddisbd): + BDunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + 2 RW 0b Core + BCSunit Clock Gating Disable (cg3ddisbcs): + BCSunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + 1 RW 0b Core + AVSunit Clock Gating Disable (cg3ddisavs): + AVSunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + 0 RW 0b Core + AVDunit Clock Gating Disable (cg3ddisavd): + AVDunit Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks can be + gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + + + + +1.4.2 UCGCTL2 - Unit Level Clock Gating Control 2 +B/D/F/Type: 0/2/0/MMADR_GCPunit_Config +Address Offset: 9404-9407h +Default Value: 00000000h +Access: RW +Size: 32 bits + +Unit Level Clock Gating Control Registers. +IVB:GT2:A0: 0x9404 Bit 22 must be high (TDLunit clock gating) +IVB: 0x9404 Bit 13 must be high (RCZunit clock-gating) + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 49 + Default +Bits Access Value RST/PWR Description + 31 RW 0b Core + VFunit Clock Gating Disable (cg3ddisvf): + VFunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +30 RW 0b Core + VDSunit Clock Gating Disable (cg3ddisvds): + VDSunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +29 RW 0b Core + VDIunit Clock Gating Disable (cg3ddisvdi): + VDIunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +28 RW 0b Core + VCSunit Clock Gating Disable (cg3ddisvcs): + VCSunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +27 RW 0b Core + DTOunit Clock Gating Disable (cg3ddisdto): + DTOunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +26 RW 0b Core + VCPunit Clock Gating Disable (cg3ddisvcp): + VCPunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +25 RW 0b Core + VCDunit Clock Gating Disable (cg3ddisvcd): + VCDunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 50 + Default +Bits Access Value RST/PWR Description + 24 RW 0b Core + URBunit Clock Gating Disable (cg3ddisurb): + URBunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +23 RW 0b Core + TSunit Clock Gating Disable (cg3ddists): + TSunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +22 RW 0b Core + TDunit Clock Gating Disable (cg3ddistd): + TDunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +21 RW 0b Core + SVTSunit Clock Gating Disable (cg3ddissvts): + SVTSunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +20 RW 0b Core + SVSMunit Clock Gating Disable (cg3ddissvsm): + SVSMunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +19 RW 0b Core + SVGunit Clock Gating Disable (cg3ddissvg): + SVGunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +18 RW 0b Core + SOunit Clock Gating Disable (cg3ddisso): + SOunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 51 + Default +Bits Access Value RST/PWR Description + 17 RW 0b Core + SIunit Clock Gating Disable (cg3ddissi): + SIunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +16 RW 0b Core + SFunit Clock Gating Disable (cg3ddissf): + SFunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +15 RW 0b Core + SECunit Clock Gating Disable (cg3ddissec): + SECunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +14 RW 0b Core + SCunit Clock Gating Disable (cg3ddissc): + SCunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +13 RW 0b Core + RCZunit Clock Gating Disable (cg3ddisrcz): + RCZunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +12 RW 0b Core + RCPBunit Clock Gating Disable (cg3ddisrcpb): + RCPBunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +11 RW 0b Core + RCCunit Clock Gating Disable (cg3ddisrcc): + RCCunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 52 + Default +Bits Access Value RST/PWR Description + 10 RW 0b Core + QCunit Clock Gating Disable (cg3ddisqc): + QCunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 9 RW 0b Core + PSDunit Clock Gating Disable (cg3ddispsd): + PSDunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 8 RW 0b Core + PLunit Clock Gating Disable (cg3ddispl): + PLunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 7 RW 0b Core + MTunit Clock Gating Disable (cg3ddismt): + MTunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 6 RW 0b Core + MPCunit Clock Gating Disable (cg3ddismpc): + MPCunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 5 RW 0b Core + MLC Tag Logic and Tag / State / LRU Arrays Clock Gating Disable + (cg3ddismlctag): + MLC Tag Logic and Tag / State / LRU Arrays Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 4 RW 0b Core + MLC ECC and Error Detection / Correction Logic Clock Gating Disable + (cg3ddismlcecc): + MLC ECC and Error Detection / Correction Logic Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 53 + Default +Bits Access Value RST/PWR Description + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 3 RW 0b Core + MLC Data Array Clock Gating Disable (cg3ddismlcdbank): + MLC Data Array Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 2 RW 0b Core + MLC Data Pipeline and Scheduler Logic Clock Gating Disable + (cg3ddismlcdata): + MLC Data Pipeline and Scheduler Logic Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 1 RW 0b Core + MAunit Clock Gating Disable (cg3ddisma): + MAunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 0 RW 0b Core + IZunit Clock Gating Disable (cg3ddisiz): + IZunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 54 + 1.4.3 UCGCTL3 - Unit Level Clock Gating Control 3 +B/D/F/Type: 0/2/0/MMADR_GCPunit_Config +Address Offset: 9408-940Bh +Default Value: 04000000h +Access: RW +Size: 32 bits + +Unit Level Clock Gating Control Registers. + Default +Bits Access Value RST/PWR Description + 31 RW 0b Core + VXCunit Clock Gating Disable (cg3ddisvxc): + VXCunits' Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +30 RW 0b Core + SVRRunit Clock Gating Disable (cg3ddissvrr): + SVRRunits' Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +29 RW 0b Core + VCRunit Clock Gating Disable (cg3ddisvcr): + VCRunits' Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +28 RW 0b Core + EDTunit Clock Gating Disable (cg3ddisedt): + EDTunits' Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +27 RW 0b Core + VCIunit Clock Gating Disable (cg3ddisvci): + VCIunits' Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +26 RW 1b Core + CCRunit Clock Gating Disable (cg3ddisccr): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 55 + Default +Bits Access Value RST/PWR Description + CCRunits' Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +25 RW 0b Core + MLCunit Clock Gating Disable (cg3ddismlc): + MLCunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +24 RW 0b Core + CTCunit Clock Gating Disable (cg3ddisctc): + CTCunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +23 RW 0b Core + QRCunit Clock Gating Disable (cg3ddisqrc): + QRCunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +22 RW 0b Core + MSPBISTunit Clock Gating Disable (cg3ddismspbist): + MSPBISTunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +21 RW 0b Core + BSPunit Clock Gating Disable (cg3ddisbsp): + BSPunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +20 RW 0b Core + OACSunit Clock Gating Disable (cg3ddisoacs): + OACSunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +19 RW 0b Core + OACRMunit Clock Gating Disable (cg3ddisoacrm): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 56 + Default +Bits Access Value RST/PWR Description + OACRMunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +18 RW 0b Core + OACRROWunit Clock Gating Disable (cg3ddisoacrrow): + OACRROWunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +17 RW 0b Core + WMBE Clock Gating Disable (cg3ddiswmbe): + WMBEunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +16 RW 0b Core + WMFEunit Clock Gating Disable (cg3ddiswmfe): + WMFEunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +15 RW 0b Core + VSCunit Clock Gating Disable (cg3ddisvsc): + VSCunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +14 RW 0b Core +13 RW 0b Core + USBunit Clock Gating Disable (cg3ddisusb): + USBunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +12 RW 0b Core + STCunit Clock Gating Disable (cg3ddisstc): + STCunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +11 RW 0b Core + VS0unit Clock Gating Disable (cg3ddisvs0): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 57 + Default +Bits Access Value RST/PWR Description + VS0unit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +10 RW 0b Core + VOPunit Clock Gating Disable (cg3ddisvop): + VOPunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 9 RW 0b Core + VMXunit Clock Gating Disable (cg3ddisvmx): + VMXunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 8 RW 0b Core + VMEunit Clock Gating Disable (cg3ddisvme): + VMEunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 7 RW 0b Core + VMDunit Clock Gating Disable (cg3ddisvmd): + VMDunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 6 RW 0b Core + VMCunit Clock Gating Disable (cg3ddisvmc): + VMCunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 5 RW 0b Core + VLFunit Clock Gating Disable (cg3ddisvlf): + VLFunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 4 RW 0b Core + VITunit Clock Gating Disable (cg3ddisvit): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 58 + Default +Bits Access Value RST/PWR Description + VITunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 3 RW 0b Core + VIPunit Clock Gating Disable (cg3ddisvip): + VIPunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 2 RW 0b Core + VINunit Clock Gating Disable (cg3ddisvin): + VINunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 1 RW 0b Core + VFTunit Clock Gating Disable (cg3ddisvft): + VFTunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 0 RW 0b Core + VFEunit Clock Gating Disable (cg3ddisvfe): + VFEunit Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + + + +1.4.4 UCGCTL4 - Unit Level Clock Gating Control 4 +B/D/F/Type: 0/2/0/MMADR_GCPunit_Config +Address Offset: 940C-940Fh +Default Value: 00000003h +Access: RO, RW +Size: 32 bits + +Unit Level Clock Gating Control Registers. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 59 + Bits Access Default Value RST/PWR Description +31:26 RO 00000000000000000000000000000b Core + Reserved (RSVD): + Reserved. + 25 RW 0 Core + L3 Bank 2x Clock Disable: + 0: Clock Gating Enabled. (i.e., clocks can be gated + when they are not required to toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, + always) + For IVBA/B-steppings, this bit needs to be "1" +24:3 RO 0 Core + Reserved (RSVD): + Reserved. + 2 RW 0b Core + VID2 VINunit Clock Gating Disable + (cg3ddisvin_vid2): + VID2 VINunits' Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated + when they are not required to toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, + always) + + 1:0 RW 11b Core + MSQCunit Clock Gating Disable (cg3ddismsqc): + MSQCunits' Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated + when they are not required to toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, + always) + + + +1.4.5 RCGCTL1 - RAM Clock Gating Control 1 +B/D/F/Type: 0/2/0/MMADR_GCPunit_Config +Address Offset: 9410-9413h +Default Value: 00000180h +Access: RW, RO +Size: 32 bits + +RAM Clock Gating Control Registers. + Default +Bits Access Value RST/PWR Description + 31 RW 0b Core + USBunit RAM Clock Gating Disable (ramcgdis_usb): + USBunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 60 + Default +Bits Access Value RST/PWR Description + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +30 RW 0b Core + VLFunit RAM Clock Gating Disable (ramcgdis_vlf): + VLFunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +29 RW 0b Core + VDSunit RAM Clock Gating Disable (ramcgdis_vds): + VDSunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +28 RW 0b Core + STCunit RAM Clock Gating Disable (ramcgdis_stc): + STCunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +27 RW 0b Core + AVDunit RAM Clock Gating Disable (ramcgdis_avd): + AVDunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +26 RW 0b Core + VMCunit RAM Clock Gating Disable (ramcgdis_vmc): + VMCunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +25 RW 0b Core + QRCunit RAM Clock Gating Disable (ramcgdis_qrc): + QRCunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +24 RW 0b Core + SCunit RAM Clock Gating Disable (ramcgdis_sc): + SCunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 61 + Default +Bits Access Value RST/PWR Description + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +23 RW 0b Core + WMBEunit RAM Clock Gating Disable (ramcgdis_wmbe): + WMBEunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +22 RW 0b Core + VFunit RAM Clock Gating Disable (ramcgdis_vfm): + VFunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +21 RW 0b Core + URBunit RAM Clock Gating Disable (ramcgdis_urb): + URBunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +20 RW 0b Core + SVSMunit RAM Clock Gating Disable (ramcgdis_svsm): + SVSMunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +19 RO 0b Core + Reserved (Rsvd3): + Reserved +18 RW 0b Core + RCZunit RAM Clock Gating Disable (ramcgdis_rcz): + RCZunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +17 RW 0b Core + RCPBEunit RAM Clock Gating Disable (ramcgdis_rcpbe): + RCPBEunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +16 RW 0b Core + RCCunit RAM Clock Gating Disable (ramcgdis_rcc): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 62 + Default +Bits Access Value RST/PWR Description + RCCunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +15 RW 0b Core + PSDunit RAM Clock Gating Disable (ramcgdis_psd): + PSDunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +14 RW 0b Core + MTunit RAM Clock Gating Disable (ramcgdis_mt): + MTunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + +13 RO 0b Core + Reserved (Rsvd1): + Reserved +12 RW 0b Core + IZunit RAM Clock Gating Disable (ramcgdis_iz): + IZunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +11 RW 0b Core + ISCunit RAM Clock Gating Disable (ramcgdis_isc): + ISCunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) +10 RW 0b Core + ICunit RAM Clock Gating Disable (ramcgdis_ic): + ICunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 9 RW 0b Core + HIZunit RAM Clock Gating Disable (ramcgdis_hiz): + HIZunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 63 + Default +Bits Access Value RST/PWR Description + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 8 RW 1b Core + GAMunit RAM Clock Gating Disable (ramcgdis_gam): + GAMunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always + 7 RW 1b Core + GACunit RAM Clock Gating Disable (ramcgdis_gac): + GACunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 6 RO 0b Core + Reserved (RSVD): + Reserved. + 5 RW 0b Core + DMunit RAM Clock Gating Disable (ramcgdis_dm): + DMunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 4 RW 0b Core + DAPunit RAM Clock Gating Disable (ramcgdis_dap): + DAPunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 3 RW 0b Core + CSunit RAM Clock Gating Disable (ramcgdis_cs): + CSunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 2 RW 0b Core + BLBunit RAM Clock Gating Disable (ramcgdis_blb): + BLBunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 1 RW 0b Core + MPCunit RAM Clock Gating Disable (ramcgdis_mpc): + MPCunit RAM Clock Gating Disable Control: + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 64 + Default +Bits Access Value RST/PWR Description + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 0 RW 0b Core + BFunit RAM Clock Gating Disable (ramcgdis_bf): + BFunit RAM Clock Gating Disable Control: + 0: Clock Gating Enabled. (i.e., clocks can be gated when they are not required to + toggle for functionality) + 1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + + +1.4.6 RCGCTL2 - RAM Clock Gating Control 2 +B/D/F/Type: 0/2/0/MMADR_GCPunit_Config +Address Offset: 9414-9417h +Default Value: 00000000h +Access: RW, RO +Size: 32 bits + +RAM Clock Gating Control Registers. + Default + Bits Access Value RST/PWR Description +31:27 RO 00000b Core + Reserved (RSVD): + Reserved. + 26 RW 0b Core + VMXunit RAM Clock GatingDisable (ramcgdis_vmx): + VMXunit RAM Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks + can be gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + 25 RW 0b Core + MSunit RAM Clock Gating Disable in EU2 ROW3 (ramcgdis_ms_eu2_row3): + MSunit RAM Clock Gating Disable Control in EU2 ROW3:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 24 RW 0b Core + MSunit RAM Clock Gating Disable in EU1 ROW3 (ramcgdis_ms_eu1_row3): + MSunit RAM Clock Gating Disable Control in EU1 ROW3:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 23 RW 0b Core + MSunit RAM Clock Gating Disable in EU0 ROW3 (ramcgdis_ms_eu0_row3): + MSunit RAM Clock Gating Disable Control in EU0 ROW3:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 65 + Default +Bits Access Value RST/PWR Description + 22 RW 0b Core + MSunit RAM Clock Gating Disable in EU2 ROW2 (ramcgdis_ms_eu2_row2): + MSunit RAM Clock Gating Disable Control in EU2 ROW2:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 21 RW 0b Core + MSunit RAM Clock Gating Disable in EU1 ROW2 (ramcgdis_ms_eu1_row2): + MSunit RAM Clock Gating Disable Control in EU1 ROW2:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 20 RW 0b Core + MSunit RAM Clock Gating Disable in EU0 ROW2 (ramcgdis_ms_eu0_row2): + MSunit RAM Clock Gating Disable Control in EU0 ROW2:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 19 RW 0b Core + MSunit RAM Clock Gating Disable in EU2 ROW1 (ramcgdis_ms_eu2_row1): + MSunit RAM Clock Gating Disable Control in EU2 ROW1:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 18 RW 0b Core + MSunit RAM Clock Gating Disable in EU1 ROW1 (ramcgdis_ms_eu1_row1): + MSunit RAM Clock Gating Disable Control in EU1 ROW1:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 17 RW 0b Core + MSunit RAM Clock Gating Disable in EU0 ROW1 (ramcgdis_ms_eu0_row1): + MSunit RAM Clock Gating Disable Control in EU0 ROW1:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 16 RW 0b Core + MSunit RAM Clock Gating Disable in EU2 ROW0 (ramcgdis_ms_eu2_row0): + MSunit RAM Clock Gating Disable Control in EU2 ROW0:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 15 RW 0b Core + MSunit RAM Clock Gating Disable in EU1 ROW0 (ramcgdis_ms_eu1_row0): + MSunit RAM Clock Gating Disable Control in EU1 ROW0:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 14 RW 0b Core + MSunit RAM Clock Gating Disable in EU0 ROW0 (ramcgdis_ms_eu0_row0): + MSunit RAM Clock Gating Disable Control in EU0 ROW0:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 13 RW 0b Core + GAunit RAM Clock Gating Disable in EU2 ROW3 (ramcgdis_ga_eu2_row3): + GAunit RAM Clock Gating Disable Control in EU2 ROW3:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 66 + Default +Bits Access Value RST/PWR Description + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 12 RW 0b Core + GAunit RAM Clock Gating Disable in EU1 ROW3 (ramcgdis_ga_eu1_row3): + GAunit RAM Clock Gating Disable Control in EU1 ROW3:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 11 RW 0b Core + GAunit RAM Clock Gating Disable in EU0 ROW3 (ramcgdis_ga_eu0_row3): + GAunit RAM Clock Gating Disable Control in EU0 ROW3:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 10 RW 0b Core + GAunit RAM Clock Gating Disable in EU2 ROW2 (ramcgdis_ga_eu2_row2): + GAunit RAM Clock Gating Disable Control in EU2 ROW2:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 9 RW 0b Core + GAunit RAM Clock Gating Disable in EU1 ROW2 (ramcgdis_ga_eu1_row2): + GAunit RAM Clock Gating Disable Control in EU1 ROW2:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 8 RW 0b Core + GAunit RAM Clock Gating Disable in EU0 ROW2 (ramcgdis_ga_eu0_row2): + GAunit RAM Clock Gating Disable Control in EU0 ROW2:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 7 RW 0b Core + GAunit RAM Clock Gating Disable in EU2 ROW1 (ramcgdis_ga_eu2_row1): + GAunit RAM Clock Gating Disable Control in EU2 ROW1:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + + 6 RW 0b Core + GAunit RAM Clock Gating Disable in EU1 ROW1 (ramcgdis_ga_eu1_row1): + GAunit RAM Clock Gating Disable Control in EU1 ROW1:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 5 RW 0b Core + GAunit RAM Clock Gating Disable in EU0 ROW1 (ramcgdis_ga_eu0_row1): + GAunit RAM Clock Gating Disable Control in EU0 ROW1:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 4 RW 0b Core + GAunit RAM Clock Gating Disable in EU2 ROW0 (ramcgdis_ga_eu2_row0): + GAunit RAM Clock Gating Disable Control in EU2 ROW0:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 3 RW 0b Core + GAunit RAM Clock Gating Disable in EU1 ROW0 (ramcgdis_ga_eu1_row0): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 67 + Default +Bits Access Value RST/PWR Description + GAunit RAM Clock Gating Disable Control in EU1 ROW0:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 2 RW 0b Core + GAunit RAM Clock Gating Disable in EU0 ROW0 (ramcgdis_ga_eu0_row0): + GAunit RAM Clock Gating Disable Control in EU0 ROW0:0: Clock Gating + Enabled. (i.e., clocks can be gated when they are not required to toggle for + functionality)1: Clock Gating Disabled. (i.e., clocks are toggling, always) + 1 RW 0b Core + GSunit RAM Clock Gating Disable (ramcgdis_gs): + GSunit RAM Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks + can be gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + + 0 RW 0b Core + CTCunit RAM Clock Gating Disable (ramcgdis_ctc): + CTCunit RAM Clock Gating Disable Control:0: Clock Gating Enabled. (i.e., clocks + can be gated when they are not required to toggle for functionality)1: Clock Gating + Disabled. (i.e., clocks are toggling, always) + + + +1.4.7 IFDIMCTL - Integrated Power Supply Frequency Domain + Impedance Meter Controls +B/D/F/Type: 0/2/0/MMADR_GCPunit_Config +Address Offset: 9418-941Bh +Default Value: 00000000h +Access: RO, RW +Size: 32 bits + +Integrated Power Supply Frequency Domain Impedance Meter (IFDIM) Controls: +Bits Access Default Value RST/PWR Description + 31 RO 0b Core + Reserved (RSVD): + Reserved. +30:4 RW 000000000000000000000000000b Core + IFDIM Modulation Counter Delay Value + (IFDIMCNTVAL): + The IFDIM Modulation Counter Delay Value. + Note that this 27-bit count value is not exact. The counter + sits in csclk domain, and the modulation gating/un-gating + is done on clock beat alignments. + 3 RW 0b Core + CSCLK Moudlation Enable (CSMODEN): + csclk Modulation Enable: + 1 - Enable csclk domain clock modulation. + 0 - Disable csclk domain clock modulation; csclk domain + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 68 + Bits Access Default Value RST/PWR Description + is gated. + 2 RW 0b Core + MLCCLK Modulation Enable (MLCMODEN): + mlcclk Modulation Enable: + 1 - Enable mlcclk domain clock modulation. + 0 - Disable mlcclk domain clock modulation; mlcclk + domain is gated. + 1 RW 0b Core + CRCLK Modulation Enable (CRMODEN): + crclk Modulation Enable: + 1 - Enable crclk domain clock modulation. + 0 - Disable crclk domain clock modulation; crclk domain is + gated. + 0 RW 0b Core + Enable IFDIM (IFDIMEN): + Enable IFDIM Operation: + 1 - IFDIM operation enabled; Selected clocks (see bits + #1, #2, #3) are modulated. + 0 - IFDIM operation disabled. + + + +1.4.8 GDRST - Graphics Device Reset Control +B/D/F/Type: 0/2/0/MMADR_GCPunit_Config +Address Offset: 941C-941Fh +Default Value: 00000000h +Access: RWHC, RO +Size: 32 bits + +Graphics Device Reset Control Registers: + Default +Bits Access Value RST/PWR Description +31:4 RO 0000000h Core + Reserved (RSVD): + Reserved + 3 RWHC 0b Core + Initiate Graphics Blitter Soft Reset (INIT_BLIT_SR): + Graphics Blitter Soft-Reset Control: + 1: Initiate a graphics blitter domain reset. - Cleared by CP once the reset is + complete. + 0: N/A - Once set, clearing this bit has no effect on CP. Only CP can reset this + bit. Note: This is a non-posted register. + 2 RWHC 0b Core + Initiate Graphics Media Soft Reset (INIT_MEDIA_SR): + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 69 + Default +Bits Access Value RST/PWR Description + Graphics Media Soft-Reset Control: + 1: Initiate a graphics media domain reset. - Cleared by CP once the reset is + complete. + 0: N/A - Once set, clearing this bit has no effect on CP. Only CP can reset this + bit. Note: This is a non-posted register. + 1 RWHC 0b Core + Initiate Graphics Render Soft Reset (INIT_RENDER_SR): + Graphics Render Soft-Reset Control: + 1: Initiate a graphics render domain reset. - Cleared by CP once the reset is + complete. + 0: N/A - Once set, clearing this bit has no effect on CP. Only CP can reset this + bit. Note: This is a non-posted register. + 0 RWHC 0b Core + Initiate Graphics Full Soft Reset (INIT_GFXFULL_SR): + Graphics Full Soft-Reset Control: + 1: Initiate a full graphics reset (i.e., graphics render, media, and blitter reset). - + Cleared by CP once the reset is complete. + 0: N/A - Once set, clearing this bit has no effect on CP. Only CP can reset this + bit. Note: This is a non-posted register. + + + +1.4.9 RSTCTL - Misc. Reset Control Register +B/D/F/Type: 0/2/0/MMADR_GCPunit_Config +Address Offset: 9420-9423h +Default Value: 00000000h +Access: RW, RO +Size: 32 bits + +Miscellaneous reset control registers. + Default +Bits Access Value RST/PWR Description +31:4 RO 0000000h Core + Reserved (Rsvd.): + Reserved +3:2 RW 00b Core + Reset Staggering Period Control (RSTSTGRT): + Reset assertion staggering period between reset domains: "00" : no reset + assertion staggering "01" : 16 cs clocks "10" : 32 cs clocks "11" : 64 cs clocks +1:0 RW 00b Core + Reset Residency Control (RSTRSDNCY): + Reset assertion residency period for FLR and soft-resets. "00" : 8 cs clocks "01" + : 16 cs clocks "10" : 32 cs clocks "11" : 64 cs clocks + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 70 + 1.4.10 MISCCPCTL - Misc. Clocking/Reset Control Register +B/D/F/Type: 0/2/0/MMADR_GCPunit_Config +Address Offset: 9424-9427h +Default Value: 00000000h +Access: RW +Size: 32 bits + +Miscellaneous Clocking/Reset Control Register: +Bits Access Default Value RST/PWR Description +31:2 RW 000000000000000000000000000000b Core + Bonus (BONUS): + Reserved. + 1 RW 0b Core + L1 Clock Ungate Enabling Control During Reset + (L1UGTEN4RST): + Control to enable/disable L1 clock gating during soft + resets and FLR reset processing. + 1: Disable L1 clock gating during soft resets and FLR. + 0: Enable L1 clock gating during soft resets and FLR + (default op). + 0 RW 0b Core + DOP Clock Gating Enable for Row and Media + Clocks (DOPCGEN): + Controls the Enabling of the DOP-level Row and + Media Clock Gating via PM event messages: + 1: Clock gating is enabled. + 0: Clock gating is disabled. + + + +1.5 GCPunit Message Register Space + Register Name Register Symbol Register Start Register End Default Value Access +GT Function Level Reset Control Message FLRCTLMSG 8100 8103 00000000h RO, RWHC +Glock Gating Messages CGMSG 8104 8107 00000000h RO, RW +Reset Flow Control Messages RSTFCTLMSG 8108 810B 00000000h RO, RW + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 71 + 1.5.1 FLRCTLMSG - GT Function Level Reset Control Message +B/D/F/Type: 0/2/0/MMADR_GCPunit_Message +Address Offset: 8100-8103h +Default Value: 00000000h +Access: RO, RWHC +Size: 32 bits + +GT FLR Control Register: + Bits Access Default Value RST/PWR Description +31:16 RO 0000h Core + Message Mask (MSGMSK): + Message Mask + To write to bits 15:0, the corresponding message mask bits must be + written. + For example, for bit 14 to be set, bit 30 needs to be 1: 40004000h. + +15:1 RO 000000000000000b Core + Reserved (RSVD): + Reserved. + 0 RWHC 0b Core + Initiate GT Function Level Reset Message (INIT_FLR): + GT Function Level Reset (FLR) + 1: Initiate GT FLR + - This is a Non-Posted message to reset Render, Media, Blitter, and + GTI-Device domains. + This bit is cleared by the CPunit on completion of the reset. + + + +1.5.2 CGMSG - Glock Gating Messages +B/D/F/Type: 0/2/0/MMADR_GCPunit_Message +Address Offset: 8104-8107h +Default Value: 00000000h +Access: RO, RW +Size: 32 bits + +Clock Gating Messages Register: + Bits Access Default Value RST/PWR Description +31:16 RO 0000h Core + Message Mask (MSGMSK): + Message Mask + To write to bits 15:0, the corresponding message mask bits must be + written. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 72 + Bits Access Default Value RST/PWR Description + For example, for bit 14 to be set, bit 30 needs to be 1: 40004000h. +15:2 RO 00000000000000b Core + Reserved (RSVD): + Reserved. + 1 RW 0b Core + Media Clock Gating Control Message (MCGCTL): + Gate Media Clock Message: + 0: Media Clock Un-gate Request (un-gates the crmclk clock). + 1: Media Clock Gate Request (gates the crmclk clock). + 0 RW 0b Core + Row Clock Gating Control Message (RCGCTL): + Gate Row Clocks Message : + 0: Row Clock Un-gate Request (un-gates the csrowclk and crrowclk + clocks). + 1: Row Clock Gate Request (gates the csrowclk and crrowclk clocks). + + + +1.5.3 RSTFCTLMSG - Reset Flow Control Messages +B/D/F/Type: 0/2/0/MMADR_GCPunit_Message +Address Offset: 8108-810Bh +Default Value: 00000000h +Access: RO, RW +Size: 32 bits + +Soft-Reset and FLR Flow Control Message Registers + Default + Bits Access Value RST/PWR Description +31:16 RO 0000h Core + Message Mask (MSGMAK): + Message Mask + To write to bits 15:0, the corresponding message mask bits must be written. + For example, for bit 14 to be set, bit 30 needs to be 1: 40004000 +15:8 RO 00h Core + Reserved (RSVD): + Reserved. + 7 RW 0b Core + Blitter Reset Flow Acknowledgement Messages (BLITRSTACK): + PM Acknowledgement Messages for Blitter reset: + 1: PREP_RST_BLIT_ACK + - Acknowledgement that graphics blitter is prepared for reset assertion. + 0: DONE_BLIT_RST_ACK + - Acknowledgement that graphics blitter reset is de-asserted + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 73 + Default +Bits Access Value RST/PWR Description + 6 RW 0b Core + Media Reset Flow Acknowledgement Messages (MEDIARSTACK): + PM Acknowledgement Messages for Media reset: + 1: PREP_RST_MEDIA_ACK + - Acknowledgement that graphics media block is prepared for reset assertion. + 0: DONE_MEDIA_RST_ACK + - Acknowledgement that the graphics media reset is de-asserted + 5 RW 0b Core + Render Reset Flow Acknowledgement Messages (RENDERRSTACK): + PM Acknowledgement Messages for Render reset: + 1: PREP_RST_RENDER_ACK + - Acknowledgement that the graphics render block is prepared for reset + assertion. + 0: DONE_RENDER_RST_ACK + - Acknowledgement that the graphics render reset is de-asserted + 4 RW 0b Core + GTI-Device Reset Flow Acknowledgement Messages (GTIDEVRSTACK): + PM Acknowledgement Messages for GTI-Device reset: + 1: PREP_RST_GTIDEV_ACK + - Acknowledgement that the GTI device is prepared for reset assertion. + 0: DONE_GTIDEV_RST_ACK + - Acknowledgement that the GTI device reset is de-asserted + + 3:2 RO 00b Core + Reserved (Rsvd.): + Reserved + 1 RW 0b Core + Global Resource Arbitration Acknowledgement Messages (GRARBACK): + Global Resource Arbitration Acknowledgement Message from PM: + 1: CP_ARB_REQ_ACK - Acknowledgement for CPunit's global resource + arbitration request + 0: CP_ARB_RELEASE_ACK - Acknowledgement to CPunit's release of global + resources + 0 RW 0b Core + CP Busy / Idle Status Acknowledgement Messages (CPBUSYSTATACK): + CP Busy / Idle Status Acknowledgement Message from PM: + 0: CP_NOT_BUSY_ACK - Acknowledgement that the CPunit is idle. + 1: CP_BUSY_ACK - Acknowledgement that the CPunit is busy. + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 74 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V1 Pt 6 – 05 12 5/31/2012 75 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol1_part7.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part7.txt new file mode 100644 index 0000000..1ff8320 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol1_part7.txt @@ -0,0 +1,3350 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 1 Part 7: L3$/URB +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. 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Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 + Contents +1. L3$/URB.................................................................................................................................................. 5 + 1.1 Overview .............................................................................................................................................. 5 + 1.2 L3$ Cache Configuration ..................................................................................................................... 5 + 1.3 Memory Object Control State on Cacheability ..................................................................................... 6 +2. Atomics .................................................................................................................................................. 7 + 2.1 Atomics in L3 ........................................................................................................................................ 8 + 2.2 Atomics in SLM .................................................................................................................................... 9 + 2.3 Atomics in URB .................................................................................................................................... 9 +3. L3 Allocation and Programming ........................................................................................................ 10 + 3.1 Non-SLM mode Allocation ................................................................................................................. 10 + 3.2 SLM mode Allocation ......................................................................................................................... 11 +4. L3 Invalidation and Flush Flows ........................................................................................................ 12 + 4.1 Read Only Stream Invalidations ........................................................................................................ 12 + 4.2 Pipelined Flush for Writes .................................................................................................................. 13 + 4.3 Global Invalidation .............................................................................................................................. 14 +5. Shared Local Memory (SLM) .............................................................................................................. 15 + 5.1 Protocol .............................................................................................................................................. 15 +6. Control Field Definition ....................................................................................................................... 17 +7. Dynamic Parity Feature for GFX L3 Cache ....................................................................................... 18 + 7.1 Feature Definition ............................................................................................................................... 18 + 7.2 Hardware and Software Flows ........................................................................................................... 18 + 7.2.1 Parity Generation & Detection ...................................................................................................... 18 + 7.2.2 Correction Using Parity Error data and Redundant Rows ............................................................ 18 + 7.2.3 Number of Corrections ................................................................................................................. 19 + 7.2.4 Summary ...................................................................................................................................... 19 + 7.2.5 Sub-banks with more than two persistent parity error rows ......................................................... 19 + 7.2.6 Interrupt Enabling ......................................................................................................................... 20 + 7.2.7 Clearing the Error Reporting Registers ........................................................................................ 20 + 7.3 Hardware Registers ........................................................................................................................... 20 + 7.3.1 Error Report Registers .................................................................................................................. 20 + 7.3.2 Row Replacement Registers ........................................................................................................ 22 +8. L3 Register Space (Bspec) ................................................................................................................. 23 + 8.1 config space for L3 ............................................................................................................................. 23 + 8.1.1 SARERRST - SARB Error Status ................................................................................................. 24 + 8.1.2 L3CDERRST2 - L3CD Error Status register 2 ............................................................................. 25 + 8.1.3 L3SQCREG1 - L3 SQC registers 1 .............................................................................................. 26 + 8.1.4 L3SQCREG2 - L3 SQC registers 2 .............................................................................................. 30 + 8.1.5 L3SQCREG3 - L3 SQC registers 3 .............................................................................................. 32 + 8.1.6 L3CNTLREG1 - L3 Control Register1 .......................................................................................... 36 + 8.1.7 L3CNTLREG2 - L3 Control Register2 .......................................................................................... 38 + 8.1.8 L3CNTLREG3 - L3 Control Register3 .......................................................................................... 40 + 8.1.9 L3SLMREG - L3 SLM Register .................................................................................................... 41 + 8.1.10 GARBCNTLREG - Arbiter Control Register ............................................................................... 42 + 8.1.11 L3SQCREG4 - L3 SQC register 4 .............................................................................................. 44 + 8.1.12 SCRATCH1 - SCRATCH1.......................................................................................................... 45 + 8.1.13 L3B0REG1 - L3 bank0 reg1 log error ......................................................................................... 46 + 8.1.14 L3B0REG2 - L3 bank0 reg2 log error ......................................................................................... 47 + 8.1.15 L3B0REG3 - L3 bank0 reg3 log error ......................................................................................... 48 + 8.1.16 L3B0REG4 - L3 bank0 reg4 log error ......................................................................................... 49 + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 3 + 8.1.17 L3B0REG5 - L3 bank0 reg5 log error ......................................................................................... 50 + 8.1.18 L3B0REG6 - L3 bank0 reg6 log error ......................................................................................... 51 + 8.1.19 L3B0REG7 - L3 bank0 reg7 log error ......................................................................................... 52 + 8.1.20 L3B1REG0 - L3 bank1 reg0 log error ......................................................................................... 53 + 8.1.21 L3B1REG1 - L3 bank1 reg1 log error ......................................................................................... 54 + 8.1.22 L3B1REG2 - L3 bank1 reg2 log error ......................................................................................... 55 + 8.1.23 L3B1REG3 - L3 bank1 reg3 log error ......................................................................................... 56 + 8.1.24 L3B1REG4 - L3 bank1 reg4 log error ......................................................................................... 57 + 8.1.25 L3B1REG5 - L3 bank1 reg5 log error ......................................................................................... 58 + 8.1.26 L3B1REG6 - L3 bank1 reg6 log error ......................................................................................... 59 + 8.1.27 L3B1REG7 - L3 bank1 reg7 log error ......................................................................................... 60 + 8.1.28 L3B2REG0 - L3 bank2 reg0 log error ......................................................................................... 61 + 8.1.29 L3B2REG1 - L3 bank2 reg1 log error ......................................................................................... 62 + 8.1.30 L3B2REG2 - L3 bank2 reg2 log error ......................................................................................... 63 + 8.1.31 L3B2REG3 - L3 bank2 reg3 log error ......................................................................................... 64 + 8.1.32 L3B2REG4 - L3 bank2 reg4 log error ......................................................................................... 65 + 8.1.33 L3B2REG5 - L3 bank2 reg5 log error ......................................................................................... 66 + 8.1.34 L3B2REG6 - L3 bank2 reg6 log error ......................................................................................... 67 + 8.1.35 L3B2REG7 - L3 bank2 reg7 log error ......................................................................................... 68 + 8.1.36 L3B3REG0 - L3 bank3 reg0 log error ......................................................................................... 69 + 8.1.37 L3B3REG1 - L3 bank3 reg1 log error ......................................................................................... 70 + 8.1.38 L3B3REG2 - L3 bank3 reg2 log error ......................................................................................... 71 + 8.1.39 L3B3REG3 - L3 bank3 reg3 log error ......................................................................................... 72 + 8.1.40 L3B3REG4 - L3 bank3 reg4 log error ......................................................................................... 73 + 8.1.41 L3B3REG5 - L3 bank3 reg5 log error ......................................................................................... 74 + 8.1.42 L3B3REG6 - L3 bank3 reg6 log error ......................................................................................... 75 + 8.1.43 L3B3REG7 - L3 bank3 reg7 log error ......................................................................................... 76 + 8.1.44 SARBCSR - SARB config save msg .......................................................................................... 77 + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 4 + 1. L3$/URB +1.1 Overview +GFX L3 cache is introduced for GFX core as a large storage which backs up various L2/L1 caches on +many clients. It provides a simple way based partitioning option for each or a cluster of clients to get a +dedicated chunk of the cache. It also acts as a GFX URB and can be configured as highly banked +memory for EUs/ROWs. +In order to provide the bandwidth needed L3 has been separated into 4x128KB structures which can be +accessed concurrently. A 2x clocking is introduced to further enhance the bandwidth and cover the +limitations of SRAM (6T) design. + +  Formed as 4 (2 for GT1) individual banks each with 128KB in size +  Each logical bank consists of + o Data Array + o Tag Array + o LRU Array (implements a Pseudo Least Recently Used algorithm) + o State Array + o SuperQ Data Buffer + o Atomic Processing Unit + +  The rest of the support logic around L3 are + o SuperQ (main scheduler) + o Ingress/Egress queues to L3/SQ (L3 arbiter) + o CAM structures to maintain coherency. + o Crossbars for data routing + +  Use of 2x/1x clocking +  L3 operates in GFX coherent domain +  A portion of L3 can be allocated as highly banked memory + + +1.2 L3$ Cache Configuration +  4x128KB cache, 64 logical ways +  64B Cacheline with a portion capable of highly banked memory (with 16x4B + capability) +  Interface 64B to SQDB for the fill/write path, 64B Read/Evict path to SQDB +  Data Array built via 6T cells + o Data protection via parity + +  TAG/LRU/STATE (using gen-ram via RLS flows) + o 32-bit GFX addressing support in TAG + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 5 + o 2 bit state + o Intel pseudo-LRU implementation for selecting the line to be replaced + +  Repetition rates for each operation + o All operations – 1 every 2x clock +  With b2b restriction for same type of accesses (i.e. read to read or + write to write) + + +1.3 Memory Object Control State on Cacheability +This 4-bit field is used in various state commands and indirect state objects to define MLC/LLC +cacheability, graphics data type for memory objects. + + Bit Description + + 3 Reserved + 2 + Graphics Data Type (GFDT) + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the + GTT. The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This + field is ignored for reads. + The GFDT bit is stored in the LLC and selective cache flushing of lines with GFDT set is + supported. It is intended to be set on displayable data, which enables efficient flushing of data to + be displayed after rendering, since display engine does not snoop the rendering caches. + Format = U1 + 1 + LLC Cacheability Control (LLCCC) + This is the field used in GT interface block to determine what type of access need to be + generated to uncore. For the cases where the LLCCC is set, cacheable transaction are + generated to enable LLC usage for particular stream. + 0: use cacheability controls from GTT entry + 1: Data is cached in LLC + + 0 + L3 Cacheability Control (L3CC) + This field is used to control the L3 cacheability (allocation) of the stream. + 0: not cacheable within L3 + 1: cacheable in L3 + Note: even if the surface is not cacheable in L3, it is still kept coherent with L3 content. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 6 + 2. Atomics +An atomic operation may involve both reading from and then writing to a memory location. Atomic +operations apply only to either u# (Unordered Access Views) or g# (Thread Group Shared Memory). It is +guaranteed that when a thread issues an atomic operation on a memory address, no write to the same +address from outside the current atomic operation by any thread can occur between the atomic read and +write. +If multiple atomic operations from different threads target the same address, the operations are serialized +in an undefined order. This serialization happens outside of the L3 control logic. +Atomic operations do not imply a memory or thread fence. If the program author/compiler does not make +appropriate use of fences, it is not guaranteed that all threads see the result of any given memory +operation at the same time, or in any particular order with respect to updates to other memory addresses. +Atomicity is implemented at 32-bit granularity. If a load or store operation spans more than 32-bits, the +individual 32-bit operations are atomic, but not the whole. +Limitation: Atomic operations on Thread Group Shared Memory are atomic with respect to other atomic +operations, as well as operations that only perform reads (“load”s). However atomic operations on Thread +Group Shared Memory are NOT atomic with respect to operations that perform only writes (“store”s) to +memory. Mixing of atomics and stores on the same Thread Group Shared Memory address without +thread synchronization and memory fencing between them produces undefined results at the address +involved. This limitation arises because some implementations of loads and stores do not honor the +locking semantics for implementing atomics. It turns out this has no impact on loads, since they are +guaranteed to retrieve a value either before or after an atomic (they will not retrieve partially updated +values, given they are all defined at 32-bit quanta). However store operations could find their way into the +middle of an atomic operation and thus have their effect possibly lost. +In L3 or SLM, the atomic operation leads to a read-modify-write operation on the destination location with +the option of returning value back to requester. The table below is defined as a list of atomic operations +needed: + Atomic Description New Return Value + Operation Destination (optional) + Value + Atomic_AND Single component 32-bit bitwise AND of operand src0 “old_dst” AND old_dst + into dst at 32-bit per component address dstAddress, “src0” + performed atomically. + Atomic_OR Single component 32-bit bitwise OR of operand src0 “old_dst” OR old_dst + into dst at 32-bit per component address dstAddress, “src0” + performed atomically. + Atomic_XOR Single component 32-bit bitwise XOR of operand src0 “old_dst” XOR old_dst + into dst at 32-bit per component address dstAddress, “src0” + performed atomically. + Atomic_MOVE Replacement of the dst with src0. “src0” old_dst + Atomic_INC Single component 32-bit integer increment of dst back “old_dst + 1” old_dst + into dst + Atomic_DEC Single component 32-bit integer decrement of dst back “old_dst - 1” old_dst + into dst + Atomic_ADD Single component 32-bit integer add of operand src0 “old_dst + + old_dst + into dst at 32-bit per component address src0” + performed atomically. Insensitive to sign + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 7 + Atomic Description New Return Value + Operation Destination (optional) + Value + Atomic_SUB Single component 32-bit integer subtraction of operand “old_dst - src0” + old_dst + src0 into dst at 32-bit per component address + performed atomically. Insensitive to sign + Atomic_RSUB Single component 32-bit integer subtraction of operand “src0 - old_dst” + old_dst + dst from src0 into dst at 32-bit per component + address performed atomically. Insensitive to + sign + Atomic_IMAX Single component 32-bit signed MAX of operand src0 IMAX (old_dst, old_dst + into dst at 32-bit per component address dstAddress, src0) + performed atomically. + Atomic_IMIN Single component 32-bit signed MIN of operand src0 IMIN (old_dst, old_dst + into dst at 32-bit per component address dstAddress, src0) + performed atomically. + Atomic_UMAX Single component 32-bit unsigned MAX of operand UMAX old_dst + src0 into dst at 32-bit per component address (old_dst, src0) + dstAddress, performed atomically. + Atomic_UMIN Single component 32-bit unsigned MIN of operand src0 UMIN (old_dst, old_dst + into dst at 32-bit per component address dstAddress, src0) + performed atomically. + Atomic_CMP/WR old_dst + Single component 32-bit value compare of operand (src0 == + src0 with dst at 32-bit per component address old_dst)? + dstAddress + src1: + If the compared values are identical, the single- + old_dst + component 32-bit value in src1 is written to destination + memory, else the destination is not changed + The entire compare+write operation is performed + atomically + Atomic_PREDEC Single component 32-bit integer decrement of dst back “old_dst - 1” new_dst + into dst + +Atomics for unstructured data types will take place in L3each via a single DW atomics engine. Each L3 +bank will have 2 independent atomics engines, one for L3 and one for SLM. Both L3 or SLM atomic +requests are going to be reduced to a single index (1 DW) request by DC before getting pushed to L3. In +L3, a single 32bit atomics engine is suffice to service DC requests. +The DC request for atomic will have the proper DW only byte enables set for the 32 bit of interest. The +address down to bit[2] (dword address) will also be provided to point to correct DW out of 16 lanes in +64Bytes. +The processing of atomics will follow 2 separate pipelines of operation (either SLM or L3) depending on +the destination of the access. + + +2.1 Atomics in L3 +Atomics in L3 are handled separately in each bank, to achieve this function 2 Atomics blocks are +instantiated along with each bank. Each operand being moved to SQ also moves its data (up to 2 DWs) +into an assigned atomics block to be used later on (when he destination data is available). + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 8 + A separate credit is given to L3 arbiter for atomics, once an atomic request is moved from L3 arbiter to +SQ – both the SQ credits and Atomics credits need to be deducted to regulate the number of atomic +requests in SQ. For GT2, this process allows upto 8 atomics to be performed in a given clock. +The request interface allows only 1 DW of atomics per request, data from DC will be given on DW0 (also +in DW1 if src1 is given) for all atomic operations regardless of the address of byte enables. Cacheline +address will be provided on the interface with proper Byte Enables singling the DW location of the +destination. +If final data is returned to client (optional), the DW of interest will be given in the same position pointed out +by byte enables (in fact the same DW will be replicated over 16 positions). + + +2.2 Atomics in SLM +SLM pipeline has a mechanism to handle atomics similar to L3/URB pipeline. There is only 1 ALU per +SLM bank. The protocol between DC and L3 allows one atomics to be performed at a given time, the +SLM controller will stall the interface if needed. Per atomics request from the DC, only ONE DW can be +active on one SLM bank. SLM pipeline can execute b2b atomics request (1 every 1x clock) as long as +b2b operations do not conflict on the same bank. If conflict is detected a single clock of bubble is inserted +into pipeline in order to update the corresponding bank with SLM output before next operation can be +performed (see SLM pipeline details) +Data from DC will be always given on DW0 and DW (if needed) and VALIDs will point to the bank of +interest out of 16 banks of SLM. Correct set of byte enables should be provided which is active for the +valid bank. +DW of interest is returned to DC on the byte enable corresponding lane of the cacheline. + + +2.3 Atomics in URB +Simple atomics are possible to be processed for URB locations as well. The process should fall out from +the L3 path of the atomics and is restricted similar to L3 atomics. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 9 + 3. L3 Allocation and Programming +L3 Cache allocation is done on a per way basis which should be consistent across all 4 banks (2 banks +for GT1). The way allocation between URB and any of the L3 clients can only be changed post pipeline +flush where L3 contains no data. This is required for stream based flushes to be dependent on the way +allocation of these corresponding streams. S/W should not be removing ways under a particular stream +and expect a later pipelined stream flush to target all the corresponding locations. The stream based flush +will be performed on the existing way allocation of that stream, there is no history of previous way +allocation tracked in the hardware. +L3 Cache has been divided into following client pools: + +  Shared Local Memory: When enabled its size is always fixed to 128KB (64KB for + GT1) +  URB: Local memory space, provides a flexible allocation on per 8KB granularity +  DC: Data Cluster Data type +  Inst/State: Both instructions and state allocation is combined +  Constants: Pull constants for EUs +  Textures: texture allocation to back-up L2$ + +In addition to these sub-groups, a collection of groups are generated to bundle multiple clients under the +same allocation set: + +  All L3 Clients: DC, Inst/State, Constants & Textures +  Read-Only Clients: Inst/State, Constants & Textures + +Each of the L3 way allocations are managed via pLRU, hence best performance can be attained via +assigning a power-of-2 number of ways. This is to ensure pLRU to distribute the ways w/o hot spotting +within that client’s group. Even though design provides a flexible (per way basis) programming model for +way allocation for each client following table is given for validation and s/w programming models. The +programming options in the following table represents most likely cases for different operation modes. +For GT1, hardware will retain 2 of the L3 banks hence all following allocations will be reduced half the +size. + + +3.1 Non-SLM mode Allocation +Normal L3/URB mode (non-SLM mode), uses all 4 banks of L3 equally to distribute cycles. The following +allocation is a suggested programming model. Note all numbers below are given in KBytes. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 10 + 3.2 SLM mode Allocation +With the existence of Shared Local Memory, a 64KB chunk from each of the 2 L3 banks will be reserved +for SLM usage. The remaining cache space is divided between the remaining clients. SLM allocation is +done via reducing the number of ways on the two banks from 64 to 32. + + + + +Given the reduction on the 2 banks for L3, we have a unique problem of how to manage HASH between +4 un-equal size banks. The way to address that issue is to identify “Low Bandwidth” clients and allocate +them into un-even ways of the large banks and handle them via a 2-way HASH. The remaining clients are +allocated between 4 banks with the equal number of ways on each bank. The shaded clients in +corresponding table are supposed to correspond to low bandwidth clients and their total should be +128KB. +Note that, having mixture of 2 hashes need to ensure “there are no coherency requirements between the +high b/w and low b/w clients”. This solution prevents any producer/consumer models cross groups within +L3. When programming the low b/w vs high b/w client profile, the need for coherency with the L3 fabric +has to be considered. +Note that URB needs to be set as low b/w client in SLM mode, else the hash will fail. This is a required +s/w model. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 11 + 4. L3 Invalidation and Flush Flows +In, L3 fabric will support two different invalidation/flush flows. One for Read only streams and it could be +per stream basis and the other one is the pipelined flush for modified lines in L3. + + +4.1 Read Only Stream Invalidations +All read-only stream invalidations are done at the TOP of the pipe and communicated to L3 fabric directly +from the main command streamer. Once send to L3, command streamer can kick off the next workload to +re-use the same memory space. There are four type streams that can be covered individually or +overlapped: + +  Texture Invalidation +  Instruction Invalidation +  Constant Invalidation +  State Invalidation + +For all types of invalidations the flows are the same from L3 arbiter perspective: first invalidation will +directly come from the command streamer and the “state invalidation” is sent via state arbiter unit. +L3 arbiter will propagate the invalidation only after the corresponding streams’ requests are retired to +superQs. Once a particular invalidation is received, L3 arbiter will put a marker where all the existing +requests from that stream. This will allow the already existing requests to be sent to superQ while +accepting new requests, however new requests should never be sent to SuperQ until the existing +invalidation is complete. Once all existing (marked requests) moved to SQ, L3 arbiter will propagate the +invalidation request to SuperQ and keep the corresponding ingress FIFOs blocked. +Note: There may be two sources of the corresponding stream (i.e. Textures from either half-slice +arbiters…). L3 arbiter needs to ensure both streams are serviced before propagating the “invalidation to +SuperQ”. +Once SuperQ receives the invalidation, it will start monitoring particular streams transactions that could +be still in SuperQ and wait for them to retire. If there is no such requests, this process would be +immediate. The invalidation will be forwarded to L3 as SuperQ ensures there is no more requests in its +slots with the matching clientID assignment. +Once L3 cache receives the invalidation, it is guaranteed that none of its requests in the TAG pipeline +belongs to OLD marked requests from the stream getting the invalidation. SuperQ already guarantees +this process by waiting for the retirement of the marked requests. TAG pipeline controller will stall the +operations and wait for the TAG pipeline to clear than send the indication to STATE Array controller. For +the ways that are corresponding to invalidation type, all ways for matching stream type will be updated in +one shot. Once invalidation is complete, each L3 bank will send the indication to Pixel Arbiter (GAP). Note +that multiple invalidations will be serialized in L3. +GAP will collect all invalidation requests from 4 banks (2 banks for GT1) and make sure all are complete +before sending this completion back to corresponding L3 arbiters. L3 arbiters will ungate the ingress +FIFOs of the completed invalidation as they complete the last step required. +This is exception part of the Read-Only Stream invalidations where state arbiter needs to stop sending +new requests to L3 arbiters and ensure all pre-committed requests already sent to L3 arbiters: + +  Stop and discard any prefetch requests that may be ongoing + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 12 +  Finish any state requests with the length fields. + +Once above conditions are satisfied the “state invalidation” will be forwarded to L3 arbiters and state +arbiter will stop sending processing any other state requests while processing the invalidation. The +ingress FIFOs will be kept blocked towards the arbiter until L3 arbiters send an indicator (all 4 of them) to +state arbiter for the completion of the state invalidation. Note that this is an extra step for L3 arbiters only +for the case of state invalidation within Read-Only streams. +Note that state arbiter needs to accumulate any new state requests that falls behind the invalidation event +and not process them until the state invalidation complete indicator is seen from GAP. It needs to ensure +old state data is cleared before sending the new state requests from clients. +There is a possibility where multiple invalidations could exist for a given stream. This is where L3 arbiters +need to co-ordinate the when the invalidation requests would be processed. As L3 arbiter receives a +particular invalidation to the time response is received from GAP, there could be yet another invalidation +for the same stream. However since the ingress FIFOs are blocked, new invalidation request should not +be processed before the prior request is complete. When L3 arbiter receives the completion from GAP, it +will start processing the new invalidation as if it was received right at the same cycle. +Same rules apply for state arbiter as well where while the completion for a prior invalidation is pending, +there may be another invalidation request from the main command streamer. State arbiter will hold off the +execution of the newer invalidation until the completions are seen from the L3 arbiters. +Note that there could be third, forth invalidations while the very invalidation is being processed. All +invalidations for a given stream could be collapsed while the prior one is being processed. + + +4.2 Pipelined Flush for Writes +Pipelined flush for data cluster writes will be propagated from DC directly to L3 arbiters as their buffers +are flushed. L3 arbiters will be getting a flush indicator from each DC independently, there is no point of +acting on the first flush indicator, it is easier to wait for both DCs to send their flush request and process +them together. Once both flush indicators are seen, L3 arbiter will flush all its ingress FIFOs and block +outlet of them being processed. L3 arbiter should not be sending any other requests to SuperQs until a +completion is seen. +SuperQ as a response to Write Flush will wait for all its slots to retire, this is to prevent any boundary +cases and ensure all writes are retired to L3 (if any). Once emptied, SQ will start accumulating “Flush” +requests to the defined sets and ways (defined as data cluster reserved ways) and walk through each +entry of the L3. These flush requests are to invalidate and evict any modified lines that may be present in +L3s. +After all defined ways are walked with FLUSH requests, SuperQ should wait for empty indicator once +again. This is to make sure all evicted data is retired towards GAP. +As GAP receives the flush complete indicator from each bank of L3 (4 for GT2 and 2 for GT1), it will +ensure the eviction path is retired towards GAM, Once all done, it will send an indicator to PSD units in +each half-slice. Same signal will be received by all L3 arbiters and used to un-block their interfaces +towards SuperQ. +Note that SuperQ should not release any credits to L3 arbiter when retiring an internally generated flush +request. +Similar to RO invalidations, the status of the write flush can also be tracked via register space. The +indication of each bank will be reported via its corresponding L3 arbiter to a register space. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 13 + 4.3 Global Invalidation +Once written a global indicator will be sent to L3 arbiters and state arbiter which will kick-off all +invalidations at once. The same register space will collect all completion from L3 arbiters and state arbiter +to clear the same bit. +Register bit can be polled by s/w to track to completion of all invalidations. + Default + Bit Access Value Description + 0 RW/C 0 L3 Global Invalidations: Once written it will kick off a global invalidation for L3 + both on RO and WR streams. S/W is expected to write logic1 to kick-off the + invalidation and H/W will clear the bit once all invalidations are complete. + Meanwhile S/W can poll the bit to track the completion of invalidation. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 14 + 5. Shared Local Memory (SLM) +Shared local memory (aka highly-banked memory) is a portion of L3 which will be dedicated to EUs as a +local memory when enabled. The accesses are only possible through data cluster with the destination +flag set as SLM. In order to support a highly banked design, 2 of the L3 banks are structured to have +16x4KB portion which could be accessed independently per clock. This part of the L3 can support 16 dw +size accesses (per SLM) in a given clock cycle. +These 16 banks can either be used as L3/URB or used as shared local memory with parallel accesses to +all banks. The choice of enabling SLM mode is done through MMIO programming + Default + Bit Access Value Description + 0 RW/C 0 Enable Shared Local Memory: When set, it enables the use of 2 banks of L3 as + shared local memory which allows 64KB of L3 to be banked as 16x4KB and + allows independent accesses to all banks within the same clock cycle. + Note: This mode can only be enabled once L3 content is completely flushed. + +In, SLM is structured as 64KB per half slice (6 EUs) and each 64KB allow up to 16 accesses to a +particular 4KB bank. Each 4KB bank is addressed separately where their requests are placed on a 160bit +address bus where each 10-bit correspond to a bank sequentially. Each bank gets addressed with 10bits +and provides 4B access with a total of 4KB per bank. When SLM mode is not enabled, SLM banks are +considered a part of L3 and used for cache or URB. + + +SLM requests are forked around the L3 arbiter, post ingress FIFOs for DC. L3 arbiter delivers +request/data to SLM controller upon the availability of credits. Request will be crossed to 2x clock domain +routed to corresponding banks. Individual bank controls are managed via SLM controller which are +muxed with L3/URB accesses. Note that SLM accesses do carry byte enables and needs to be honored +towards the banks. If the request has atomic requirements, SLM controller will provide the data to ALU +along with the atomic type. Output data is again managed with SLM controller towards the output cross +bars. + + +5.1 Protocol +The interface to access the Shared Local Memory is very similar to DC accesses to L3/URB with some +additional fields: + +  Bank Valids: A 16bit vector that points to which request in each bank’s lane being + active. DC is required to set the corresponding valid bit to perform a read or write + operation for a corresponding bank. +  Bank DW offsets: 10-bit address is provided per bank basis. Each bank can be + accessed with a different address within the same clock cycle +  Byte Enables could be set for any format or combination + +The protocol also restricts some of the capabilities + +  In a given clock cycle same type of command have to be used for all banks. This + allows to read or write but not to combine different cycle operation within the same + clock. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 15 +  Only 1 valid could be set if the SLM access requires atomics. +  In case of atomics, the data is provided always on the lower DW lanes (src0=DW0 + and src1=DW1). The read return from SLM will have the DW of interest in the + natural aligned location within 64B + +SLM requests are routed through the same L3/URB arbiter using the protocol credits that are available +between DC and L3, however right after the ingress queues SLM packets are routed to SLM controller +w/o going through the arbitration. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 16 + 6. Control Field Definition +For the state control fields are re-defined to comprehend L3 addition as following: + Bit[2] GFDT GFDT flag to color the displayable surfaces in LLC. This field is later used by GT + to poll the LLC during query/flush mechanism and used to push the data to + DRAM prior to Display Accesses + Bit[1:0] Cacheability + Control for LLC and L3 cacheabiltiy fields + Controls + Bit[1]: LLC cacheability + Bit[0]: L3 cacehability + 0: Access is NOT cacheable + 1: Access is cacheable + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 17 + 7. Dynamic Parity Feature for GFX L3 + Cache +This document is meant to outline and describe dynamic parity detection function in the graphics L3 +cache. + + +7.1 Feature Definition +The concept of DPF is to provide a run-time protection for graphics L3 cache via parity detection and +redundant rows. Parity errors are considered to be an extremely rare occurrence, but this mechanism +provides a means to address them should they occur. +In order to mitigate error detection needs of graphics L3 cache, parity detection capability has been +added to each sub-bank of the L3. A sub-bank is defined as a 16KB entity of the total 512KB cache. This +would translate into 32 independent sub-banks which all have 2 independent redundant rows for a total of +64 possible replacement rows. Redundant rows can be activated to replace a row with identified parity +errors via writing the address of the parity error row into hardware registers. +DPF allows the HW to notify SW (driver) when any single bit graphics L3 parity error has occurred and +also provide a mechanism to allow SW to fix persistent bit errors where a susceptible bit fails multiple +times. +In order to support robust GPGPU / compute workloads on graphics, Intel recommends that driver +developers implement this suggested DPF flow. Regardless, all usages of the graphics L3 cache can +benefit from the added parity protection. + + +7.2 Hardware and Software Flows + +7.2.1 Parity Generation & Detection +The graphics L3 cache will generate 1-bit parity as data is stored in the cache. The parity bit will be +written along with data for future verification. As the same content is accessed later in time, HW re- +calculates the parity based on read content and compares with the stored parity value. +Once a mismatch is detected, HW generates a parity interrupt for the graphics driver to service. +Meanwhile, HW continues forward progress in execution. There is no implicit halt or execution stopping +for the IVB / Gen7 HW. +Along with the interrupt, the HW will update a set of registers to indicate which bank/sub-bank/row in +which the error has been detected. + + +7.2.2 Correction Using Parity Error data and Redundant Rows +Each sub-bank contains 2 redundant rows which could be used to replace the rows with reported parity +errors. The graphics driver, once servicing the parity interrupt, will access the reporting registers and +record the bank/sub-bank/row information. This information should be stored in a permanent (non-volatile +memory: ie: disk, registry or similar) location for future use by the graphics driver. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 18 + The graphics driver will then reset the render engine (i.e. render specific reset) to prevent propagation of +the data with the parity error. Even though the graphics driver will terminate the context via resetting the +GPU upon a parity interrupt, there is a possibility that the parity interrupt may be observed by the driver +after the graphics context is complete or about to switch to a new context. For non-graphics workloads +that require high data integrity, such as GPGPU computing, the driver should prevent this possible +boundary case by polling the error reporting registers when a context completion or context switch +interrupt is registered by the driver. Upon identifying that the error reporting registers are active, the driver +should follow the same steps as servicing a parity interrupt. +Post any reset event (graphics reset, power up, etc..), the graphics driver retrieve the parity failure row +information from non-volatile storage. It will then program the parity failure row information into +corresponding bank/sub-bank registers and start normal graphics operation. Parity failure rows would +then be effectively replaced with the extra redundant rows until next system reset. +In the extremely rare probability that redundant rows themselves have a parity errors, the parity error will +be reported as the row they have replaced. SW drivers should recognize the use of redundant row and +skip the replacement. + + +7.2.3 Number of Corrections +Given DPF is designed to deal with persistent errors, graphics drivers need to be able to identify which +sub-bank rows are producing the most number of errors. Hence, the driver should keep a list of the +reported parity error rows and record the number of times each row reports a parity error. If there are +more than 2 parity error rows identified for a given sub-bank, the driver should replace the top two rows +first (decided by historical error count). This will force rows with consistent parity errors to bubble up to the +top of the list to be replaced. +SW driver tracking of parity error rows should be saved in non-volatile memory, so the driver can keep +track of parity failure rows across reboot/reset. + + +7.2.4 Summary +Basic Algorithm: + +  Each sub-bank has two redundant rows. (By HW design) +  Driver SW keeps track of each sub-bank’s parity failure rows and keeps a count of failures of each + row. +  Error count row information is saved to non-volatile memory, so it persists across reboot and + graphics resets. +  At all times, the two redundant sub-bank rows are used to replace the highest count parity failure + rows. +  SW always forces reset (graphics render reset is sufficient) on L3 errors. +  SW programs all necessary replacement rows after any reset. + + +7.2.5 Sub-banks with more than two persistent parity error rows +While not expected during normal lifetime operation, a problematic case could occur when the HW +reports more than 2 rows on a particular sub-bank are causing parity errors. For this case, the graphics +driver should keep replacing the rows, always selecting the two rows with the highest parity error failure +count. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 19 + 7.2.6 Interrupt Enabling +In order to enable proper DPF notification, the graphics driver must enable the correct interrupt paths +from render command streamer (x20A8) as well as rest of the interrupt structures around GTISR +(x44010), GTIMR (x44014), GTIIR (x44018), GTIER (x4401C). Bit5 has been selected for L3 parity +interrupts. Please refer to the appropriate register sections for generic graphics interrupt enabling details. + + +7.2.7 Clearing the Error Reporting Registers +Clearing error status registers for the L3 cache should be done by writing to L3CD Error Status Register +bit[13] with a logical value of “1”. This should be done after an error is reported and a row has been +replaced. The graphics driver can do this in two different ways: +1. Via batch buffer executed in HW (via LRI or LRM mechanisms) +2. Direct writes to graphics HW MMIO space +Direct reads and writes using graphics MMIO (for both error log and status registers) requires DOP level +clock gating to be turned off as HW might have finished execution, which will result in a hang when +accessing the L3 parity registers. This requires graphics MISCCPCTL bit 0 (x9424[0]) to be cleared prior +to register updates. It must be set again post register updates. Do not leave the DOP clock gating bit +cleared. Doing so will significantly affect graphics power. +Note that the HW parity registers will clear with any reset, hence error and row replacement registers will +have to be re-programmed any time the driver performs a HW reset or driver is re-loaded. + + +7.3 Hardware Registers +Various registers are used to report and contain the parity error failing row information: + + +7.3.1 Error Report Registers +This is the lead section for this topic and will be updated over time with introductory comments and links +to related information. +Use the “Next Topic” (right arrow) button above to proceed to the first detail section. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 20 + 7.3.1.1 L3CDERRST1 - L3CD Error Status register 1 +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B008-B00Bh +Default Value: 00000000h +Access: RW; RO; WO; +Size: 32 bits + + + + Bit Access Default RST/PWR Description + Value + +31:25 RO 0000000b Core + Reserved (RSVD): + Reserved +24:14 RWC 00000000000b Core + Parity row address error (PRTYROWNUM): + Data array address which has parity B1: + Report the data array address which has the Error + ltcd_sarb_parity_err_rownum[10:0] + Once set by HW, it can be cleared only by MMIO Write of 1 to this register + bit 13 . + + 13 RWC 0b Core + Parity Error Valid (PRTYERRVLD): + Parity Error valid + Report the Parity Error + ltcd_sarb_parity_err_valid + Once set by HW, it can be cleared only by MMIO Write of 1 to this register + bit 13 . +12:11 RWC 00b Core + Parity error bank number (PRTYBNKNUM): + bank number which has parity error + Report the bank no. which has the Error + ltcd_sarb_parity_err_banknum[1:0] + Once set by HW, it can be cleared only by MMIO Write of 1 to this register + bit 13 . +10:8 RWC 000b Core + Parity Error sub-bank no (PRTYSBNKNUM): + Parity Error in sub bank: + ltcd0_sarb_parity_err_subanknum[2:0] + Once set by HW, it can be cleared only by MMIO Write of 1 to this register + bit 13 . + 7 RW 1b Core + Parity report enable (LCPRTYRPTEN): + sarbcf_csr_lc_parity_report_en + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 21 + this is the parity reporting enable, by default it is enabled. + When enabled parity will be reported by ltcd to sarb. + When disabled by driver, ltcd should not send out any parity error to + SARB. + 6:0 RO 00h Core Reserved (RSVD): + + +7.3.2 Row Replacement Registers +The range of row replacement registers is addresses xB070 (bank0/sub-bank0) to xB0EC (bank3/sub- +bank7). Only the first register format is given below - all registers have the same format. + +7.3.2.1 L3B0REG0 - L3 bank0 reg0 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B070-B073h +Default Value: 00000000h +Access: RW; RO +Size: 32 bits +The log error registers of the L3 will maintain the bad row information for each of the 16KB sub-bank +groups. The log should be programmed by the driver before any workloads are submitted if it is +necessary to replace parity failing rows. The contents of the log register are included in any context save +and restore by HW for RC6 power events. +All L3 error registers are put as part of HW context which could lead the same error to be reported +multiple times (i.e. when context gets reloaded). + + Bit Access Default RST/PWR Description + Value + +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has + been detected. The number of rows vary between 4K vs 8K/16K subbanks + which requires 10bits vs 11bits respectively. This field contains the row# with + the error. +20:17 RO 0000b Core Reserved (RSVD): + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical + 16KB group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has + been detected. The number of rows vary between 4K vs 8K/16K subbanks + which requires 10bits vs 11bits respectively. This field contains the row# with + the error. + 4:1 RO 0000b Core Reserved (RSVD): + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical + 16KB group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 22 + 8. L3 Register Space (Bspec) +8.1 config space for L3 + Register Name Register Symbol Register Start Register End Default Value Access +SARB Error Status SARERRST B004 B007 00000000h RO; +L3CD Error Status register 1 L3CDERRST1 B008 B00B 00000080h RW; RO; +L3CD Error Status register 2 L3CDERRST2 B00C B00F 00000000h RO; +L3 SQC registers 1 L3SQCREG1 B010 B013 01730000h RW; RO; +L3 SQC registers 2 L3SQCREG2 B014 B017 00004567h RO; RW; +L3 SQC registers 3 L3SQCREG3 B018 B01B 00001ABFh RO; RW; +L3 Control Register1 L3CNTLREG1 B01C B01F 8C47FF80h RW; RO; +L3 Control Register2 L3CNTLREG2 B020 B023 00080040h RW; RO; +L3 Control Register3 L3CNTLREG3 B024 B027 00000000h RO; RW; +L3 SLM Register L3SLMREG B028 B02B 40000000h RO; RW; +Arbiter Control Register GARBCNTLREG B02C B02F 29000000h RO; RW; +L3 SQC register 4 L3SQCREG4 B034 B037 88000000h RW; RO; +L3 bank0 reg0 log error L3B0REG0 B070 B073 00000000h RW; RO; +L3 bank0 reg1 log error L3B0REG1 B074 B077 00000000h RW; RO; +L3 bank0 reg2 log error L3B0REG2 B078 B07B 00000000h RW; RO; +L3 bank0 reg3 log error L3B0REG3 B07C B07F 00000000h RW; RO; +L3 bank0 reg4 log error L3B0REG4 B080 B083 00000000h RW; RO; +L3 bank0 reg5 log error L3B0REG5 B084 B087 00000000h RW; RO; +L3 bank0 reg6 log error L3B0REG6 B088 B08B 00000000h RW; RO; +L3 bank0 reg7 log error L3B0REG7 B08C B08F 00000000h RW; RO; +L3 bank1 reg0 log error L3B1REG0 B090 B093 00000000h RW; RO; +L3 bank1 reg1 log error L3B1REG1 B094 B097 00000000h RW; RO; +L3 bank1 reg2 log error L3B1REG2 B098 B09B 00000000h RW; RO; +L3 bank1 reg3 log error L3B1REG3 B09C B09F 00000000h RW; RO; +L3 bank1 reg4 log error L3B1REG4 B0A0 B0A3 00000000h RW; RO; +L3 bank1 reg5 log error L3B1REG5 B0A4 B0A7 00000000h RW; RO; +L3 bank1 reg6 log error L3B1REG6 B0A8 B0AB 00000000h RW; RO; +L3 bank1 reg7 log error L3B1REG7 B0AC B0AF 00000000h RW; RO; +L3 bank2 reg0 log error L3B2REG0 B0B0 B0B3 00000000h RW; RO; +L3 bank2 reg1 log error L3B2REG1 B0B4 B0B7 00000000h RW; RO; +L3 bank2 reg2 log error L3B2REG2 B0B8 B0BB 00000000h RW; RO; +L3 bank2 reg3 log error L3B2REG3 B0BC B0BF 00000000h RW; RO; +L3 bank2 reg4 log error L3B2REG4 B0C0 B0C3 00000000h RW; RO; +L3 bank2 reg5 log error L3B2REG5 B0C4 B0C7 00000000h RW; RO; +L3 bank2 reg6 log error L3B2REG6 B0C8 B0CB 00000000h RW; RO; +L3 bank2 reg7 log error L3B2REG7 B0CC B0CF 00000000h RW; RO; +L3 bank3 reg0 log error L3B3REG0 B0D0 B0D3 00000000h RW; RO; +L3 bank3 reg1 log error L3B3REG1 B0D4 B0D7 00000000h RW; RO; +L3 bank3 reg2 log error L3B3REG2 B0D8 B0DB 00000000h RW; RO; +L3 bank3 reg3 log error L3B3REG3 B0DC B0DF 00000000h RW; RO; +L3 bank3 reg4 log error L3B3REG4 B0E0 B0E3 00000000h RW; RO; +L3 bank3 reg5 log error L3B3REG5 B0E4 B0E7 00000000h RW; RO; +L3 bank3 reg6 log error L3B3REG6 B0E8 B0EB 00000000h RW; RO; +L3 bank3 reg7 log error L3B3REG7 B0EC B0EF 00000000h RW; RO; + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 23 + Register Name Register Symbol Register Start Register End Default Value Access +SARB config save msg SARBCSR B1FC B1FF 00000000h RWHC; RO; + + +8.1.1 SARERRST - SARB Error Status + +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B004-B007h +Default Value: 00000000h +Access: RO +Size: 32 bits +Reports the error if any has occurred for certain sarb features. + + Bit Access Default Value RST/PWR Description + + 31 RO 0b Core Error if general bound is zero (ERRGENBDZO): + Error if general bound is zero set by sarbunit + 1: general bound address is 0 + sarbcf_csr_gen_bnd_zero_err + + 30 RO 0b Core Error if dynamic bound is zero (ERRDYDNZO): + Error if dynamic bound is zero- set by sarbunit + 0:no error + 1: dynamic address is 0 + sarbcf_csr_dyn_bnd_zero_err + + 29 RO 0b Core Reserved (RSVD): + + 28 RO 0b Core General Bound Check Overflow Error (GENBNDOVF): + General Bound Check Overflow Error - set by sarbunit + 1: overflow for general bound check + sarbcf_csr_gen_bnd_ovflw_err + + 27 RO 0b Core Dynamic Bound Check Overflow Error (DYNBDOVF): + Dynamic Bound Check Overflow Error -set by sarbunit + 1: overflow for dynamic bound check + sarbcf_csr_dyn_bnd_ovflw_err + + 26 RO 0b Core Lower Bound Check Overflow Error (LWRBDOVF): + Lower Bound Check Overflow Error-set by sarbunit + lower bound overflow + sarbcf_csr_lower_bnd_err + +25:21 RO 00000b Core INVALIDATION FLUSH STATUS REPORTING (INVSTRPT): + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 24 + invalidation status for l3 is reported in this register. + +20:18 RO 000b Core SARB invalidation Status reporting (SARBINVSTRPT): + invalidation status of sarb is reported in this register. + + 17:0 RO 00000h Core Reserved (RSVD): + Reserved + + + +8.1.2 L3CDERRST2 - L3CD Error Status register 2 +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B00C-B00Fh +Default Value: 00000000h +Access: RO; RWC; +Size: 32 bits + + + Default + Bit Access Value RST/PWR Description +31:29 RO 000b Core + Reserved (RSVD): + reserved + 28 RWC 0b Core + URB High Limit Error on B3 (URBHLB3): + URB High Limit Error on B3: + Report the URB High Limit Error- Address Bound check + Once set, it can be cleared only by MMIO Write to this register. A write of value + 1 will clear it + ( LTCC generates a Pulse to SARB Config , Sarb Config sets and reflect it in + the MMIO as Error status. This can be only cleared by MMIO Write to that Bit. ) + ltcc3_sarb_urboff_error + 27 RWC 0b Core + URB High Limit Error on B2 (URBHLB2): + URB High Limit Error on B2: + Report the URB High Limit Error- Address Bound check + Once set, it can be cleared only by MMIO Write to this register. + ( LTCC generates a Pulse to SARB Config , Sarb Config sets and reflect it in + the MMIO as Error status. This can be only cleared by MMIO Write to that Bit. ) + ltcc2_sarb_urboff_error + 26 RWC 0b Core + URB High Limit Error on B1 (URBHLB1): + URB High Limit Error on B1: + Report the URB High Limit Error - Address Bound check + Once set, it can be cleared only by MMIO Write to this register. + ( LTCC generates a Pulse to SARB Config , Sarb Config sets and reflect it in + the MMIO as Error status. This can be only cleared by MMIO Write to that Bit. ) + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 25 + Default + Bit Access Value RST/PWR Description + ltcc1_sarb_urboff_error + + 25 RWC 0b Core + URB High Limit Error on B0 (URBHLB0): + URB High Limit Error on B0 : + Report the URB High Limit Error - Address Bound check + Once set, it can be cleared only by MMIO Write to this register. + ( LTCC generates a Pulse to SARB Config , Sarb Config sets and reflect it in + the MMIO as Error status. This can be only cleared by MMIO Write to that Bit. ) + ltcc0_sarb_urboff_error +24:0 RO 0000000h Core + Reserved (RSVD): + + + +8.1.3 L3SQCREG1 - L3 SQC registers 1 +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B010-B013h +Default Value: 01730000h +Access: RW; RO; +Size: 32 bits + + + Acces Default RST/PW + Bit s Value R Description + 31:2 RO 0000b Core Reserved (RSVD): + 8 + Reserved + + 27 RW 0b Core Convert L3 cycle for texture to uncachable (CON4TXTUNC): + Convert L3 cycle for texture to uncachable + 1: texture has no way allocation in L3 + 0: texture has atleast 1 way allocated in L3 (default) + sarbcf_csr_lsqc_cnvt_txt_unchble + This bit should be set/cleared according to L3 configuration in registers at offset + 0xB020 and 0xB024 + + 26 RW 0b Core Convert L3 cycle for constant to uncachable (CON4CONSUNC): + Convert L3 cycle for constant to uncachable + 1: constant has no way allocation in L3 + 0: constant has atleast 1 way allocated in L3 (default) + sarbcf_csr_lsqc_cnvt_const_unchble + This bit should be set/cleared according to L3 configuration in registers at offset + 0xB020 and 0xB024 + + 25 RW 0b Core Convert L3 cycle for Inst/State to uncachable (CON4INSSTUNC): + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 26 + Acces Default RST/PW + Bit s Value R Description + Convert L3 cycle for Inst/State to uncachable + 1: Inst/State has no way allocation in L3 + 0: Inst/State has atleast 1 way allocated in L3 (default) + sarbcf_csr_lsqc_cnvt_ins_st_unchble + This bit should be set/cleared according to L3 configuration in registers at offset + 0xB020 and 0xB024 + + 24 RW 1b Core Convert L3 cycle for DC to uncachable (CON4DCUNC): + Convert L3 cycle for DC to uncachable + 1: DC has no way allocation in L3 (default) + 0: DC has atleast 1 way allocated in L3 sarbcf_csr_lsqc_cnvt_dc_unchble + This bit should be set/cleared according to L3 configuration in registers at offset + 0xB020 and 0xB024 + If 0xB020[26:21] (DC Way Assignment) field is 000000, this bits needs to be + set (1). For all other values of 0xB020[26:21], this bit needs to be cleared (0) + + 23:1 RW 01110011 Core L3SQ General / High Priority Credit Initialization (SQGHPCI): + 6 b + L3SQ General / High Priority Credit Initialization (SQGHPCI)Number of general + and high priority credits that SQ presents to L3 Arbiter blocks. This inherently + also determines the depth of the SQ; reduce the number of credits and SQ will + use fewer slots.Any value not listed here, is considered Reserved. + Value # General Credits # High Pri Credits SQ depth + 00010000 2 0 2 + 00010001 2 2 4 + 00100000 4 0 4 + 00100001 4 2 6 + 00100010 4 4 8 + 00110000 6 0 6 + 00110001 6 2 8 + 00110010 6 4 10 + 00110011 6 6 12 + 01000000 8 0 8 + 01000001 8 2 10 + 01000010 8 4 12 + 01000011 8 6 14 + 01000100 8 8 16 + 01010000 12 0 12 + 01010001 12 2 14 + 01010010 12 4 16 + 01010011 12 6 18 + 01010100 12 8 20 + 01010101 12 12 24 + 01100000 16 0 16 + 01100001 16 2 18 + 01100010 16 4 20 + 01100011 16 6 22 + 01100100 16 8 24 + 01110000 18 0 18 + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 27 + Acces Default RST/PW + Bit s Value R Description + 01110001 18 2 20 + 01110010 18 4 22 + 01110011 18 6 24(default) + 10000000 20 0 20 + 10000001 20 2 22 + 10000010 20 4 24 + 10010000 22 0 22 + 10010001 22 2 24 + 10100000 24 0 24 + sarbcf_csr_lsqc_hp_gen_credit_init[7:0] + + +15:14 RO 00b Core + Reserved (RSVD): + Reserved +13:12 RW 00b Core + L3SQ Atomics Credit Initialization (SQACI): + L3SQ Atomics Credit Initialization (SQACI)Number of atomics credits that SQ + presents to L3 Arbiter blocks. + 00 = 2 Credits (default) + 01 = 1 Credit1X = Reserved + sarbcf_csr_lsqc_atom_credit_init[1:0] + +11:10 RW 00b Core + L3SQ Data Credit Initialization (SQDCI): + L3SQ Data Credit Initialization (SQDCI)Number of data credits that SQ presents + to L3 Arbiter blocks. + 00 = 4 Credits (default) + 01 = 1 Credit + 10 = 2 Credits + 11 = 3 Credits + sarbcf_csr_lsqc_data_credit_init[1:0] + 9 RW 0b Core + L3SQ Read Once Enable for Sampler Client (SQROE): + L3SQ Read Once Enable for Sampler Client (SQROE): Enables Read Once + indications to L3 Cache from SQ. Once enabled, any reads from Sampler client + (MT) will be sent as Read Once + 0 = Reads from Sampler clients issue Read to L3 Cache (default) + 1 = Reads from Sampler clients issue Read Once to L3 Cache + sarbcf_csr_sampler_readonce_en + 8:6 RW 000b Core + L3SQ Outstanding GAP Reads (SQOUTSGAP): + L3SQ Outstanding GAP Reads (SQOUTSGAP): Identifies the number of Pixel + Arbiter Reads that can be outstanding before SQ throttles the puts to GAP. This + is not an exact limit, but instead it is used as a threshold to throttling; once the + read count is greater than or equal to the threshold, then no reads will be issued + until data returns are received to bring the outstanding count back below the + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 28 + Acces Default RST/PW + Bit s Value R Description + threshold. + 000 = No limit (default) + 001 = 1 read 010 = 2 reads + 011 = 4 reads100 = 8 reads + 101 = 16 reads11X = Reserved + sarbcf_csr_lsqc_outs_gaprd[2:0] + + 5:3 RW 000b Core + L3SQ Outstanding L3 Fills (SQOUTSL3F): + L3SQ Outstanding L3 Fills (SQOUTSL3F): Identifies the number of L3 Fills that + can be outstanding before SQ throttles the fill requests to L3 Cache. This is not + an exact limit, but instead it is used as a threshold to throttling; once the fill count + is greater than or equal to the threshold, then no fills will be issued until the fill + responses are received to bring the outstanding count back below the threshold. + 000 = No limit (default) + 001 = 1 fill + 010 = 2 fills + 011 = 4 fills + 100 = 8 fills + 101 = 16 fills + 11X = Reserved + sarbcf_csr_lsqc_outs_fill[2:0] + 2:0 RW 000b Core + L3SQ Outstanding L3 Lookups (SQOUTSL3L): + L3SQ Outstanding L3 Lookups (SQOUTSL3L): Identifies the number of L3 + lookups that can be outstanding before SQ throttles the lookup requests to L3 + Cache. This is not an exact limit, but instead it is used as a threshold to throttling; + once the lookup count is greater than or equal to the threshold, then no lookups + will be issued until the lookup responses are received to bring the outstanding + count back below the threshold. + 000 = No limit (default) + 001 = 1 lookup + 010 = 2 lookups + 011 = 4 lookups + 100 = 8 lookups + 101 = 16 lookups + 11X = Reserved + sarbcf_csr_lsqc_outs_lookup[2:0] + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 29 + 8.1.4 L3SQCREG2 - L3 SQC registers 2 +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B014-B017h +Default Value: 00004567h +Access: RO; RW; +Size: 32 bits + + + Bit Access Default Value RST/PWR Description +31:17 RO 000000000000000b Core + Reserved (RSVD): + Reserved + 16 RW 0b Core + L3SQ Priority Selection Disable (SQPRIDIS): + L3SQ Priority Selection Disable (SQPRIDIS)Enables the use of priority + selection based on client ID decodes. If disabled, all cycles in SQ will + be treated as same priority + 0 = Priority selection is enabled (default) + 1 = Priority selection is disabled + sarbcf_csr_priority_cnt_disable + 15 RW 0b Core + L3SQ Priority 3 Pool Count Disable (SQPRI3CNTDIS): + L3SQ Priority 3 Pool Count Disable (SQPRI3CNTDIS): When set, + priority3 pool becomes unlimited. And priority3 pool count value should + not be used in reset of the remaining counters. + 0 = Priority 3 pool count is enabled (default) + 1 = Priority 3 pool count is disabled + sarbcf_csr_priority3_cnt_disable + +14:12 RW 100b Core + L3SQ Priority 3 Pool Counter (SQPRI3CNT): + L3SQ Priority 3 Pool Counter (SQPRI3CNT): The count of cycles will + be selected from priority3 pool before switching to other priority pools. + Count is used as the power of 2. + 000 = 1 request + 001 = 2 requests + 010 = 4 requests + 011 = 8 requests + .. + 111 = 128 requests + sarbcf_csr_priority3_cnt[2:0] + 11 RW 0b Core + L3SQ Priority 2 Pool Count Disable (SQPRI2CNTDIS): + L3SQ Priority 2 Pool Count Disable (SQPRI2CNTDIS): When set, + priority2 pool becomes unlimited. And priority2 pool count value should + not be used in reset of the remaining counters. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 30 + Bit Access Default Value RST/PWR Description + 0 = Priority 2 pool count is enabled (default) + 1 = Priority 2 pool count is disabled + sarbcf_csr_priority2_cnt_disable +10:8 RW 101b Core + L3SQ Priority 2 Pool Counter (SQPRI2CNT): + L3SQ Priority 2 Pool Counter (SQPRI2CNT): The count of cycles will + be selected from priority2 pool before switching to other priority pools. + Count is used as the power of 2. + 000 = 1 request + 001 = 2 requests + 010 = 4 requests + 011 = 8 requests + .. + 111 = 128 requests + sarbcf_csr_priority2_cnt[2:0] + + 7 RW 0b Core + L3SQ Priority 1 Pool Count Disable (SQPRI1CNTDIS): + L3SQ Priority 1 Pool Count Disable (SQPRI1CNTDIS): When set, + priority1 pool becomes unlimited. And priority1 pool count value should + not be used in reset of the remaining counters. + 0 = Priority 1 pool count is enabled (default) + 1 = Priority 1 pool count is disabled + sarbcf_csr_priority1_cnt_disable + 6:4 RW 110b Core + L3SQ Priority 1 Pool Counter (SQPRI1CNT): + L3SQ Priority 1 Pool Counter (SQPRI1CNT): The count of cycles will + be selected from priority1 pool before switching to other priority pools. + Count is used as the power of 2. + 000 = 1 request + 001 = 2 requests + 010 = 4 requests + 011 = 8 requests + .. + 111 = 128 requests + sarbcf_csr_priority1_cnt[2:0] + 3 RW 0b Core + L3SQ Priority 0 Pool Count Disable (SQPRI0CNTDIS): + L3SQ Priority 0 Pool Count Disable (SQPRI0CNTDIS): When set, + priority0 pool becomes unlimited. And priority0 pool count value should + not be used in reset of the remaining counters. + 0 = Priority 0 pool count is enabled (default) + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 31 + Bit Access Default Value RST/PWR Description + 1 = Priority 0 pool count is disabled + sarbcf_csr_priority0_cnt_disable + 2:0 RW 111b Core + L3SQ Priority 0 Pool Counter (SQPRI0CNT): + L3SQ Priority 0 Pool Counter (SQPRI0CNT): The count of cycles will + be selected from priority0 pool before switching to other priority pools. + Count is used as the power of 2. + 000 = 1 request + 001 = 2 requests + 010 = 4 requests + 011 = 8 requests + .. + 111 = 128 requests (default) + sarbcf_csr_priority0_cnt[2:0] + + + +8.1.5 L3SQCREG3 - L3 SQC registers 3 +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B018-B01Bh +Default Value: 00001ABFh +Access: RO; RW; +Size: 32 bits + + + Default + Bit Access Value RST/PWR Description +31:30 RO 00b Core + Reserved (RSVD): + Reserved +29:28 RW 00b Core + SOLunit Priority Value (SQSOLPRIVAL): + SOLunit Priority Value (SQSOLPRIVAL): Identifies the priority value for all cycles + that are initiated by SOLunit. Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 (default) + 01 = Priority 1 + 10 = Priority 2 + 11 = Priority 3 + sarbcf_csr_sol_priority[1:0] +27:26 RW 00b Core + GSunit Priority Value (SQGSPRIVAL): + GSunit Priority Value (SQGSPRIVAL): Identifies the priority value for all cycles + that are initiated by GSunit. Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 (default) + 01 = Priority 1 + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 32 + Default + Bit Access Value RST/PWR Description + 10 = Priority 2 + 11 = Priority 3 + sarbcf_csr_gs_priority[1:0] + +25:24 RW 00b Core + TEunit Priority Value (SQTEPRIVAL): + TEunit Priority Value (SQTEPRIVAL): Identifies the priority value for all cycles + that are initiated by TEunit. Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 (default) + 01 = Priority 1 + 10 = Priority 2 + 11 = Priority 3 + sarbcf_csr_te_priority[1:0] +23:22 RW 00b Core + CLunit Priority Value (SQCLPRIVAL): + CLunit Priority Value (SQCLPRIVAL): Identifies the priority value for all cycles + that are initiated by CLunit. Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 (default) + 01 = Priority 110 = Priority 2 + 11 = Priority 3 + sarbcf_csr_cl_priority[1:0] +21:20 RW 00b Core + TSunit Priority Value (SQTSPRIVAL): + TSunit Priority Value (SQTSPRIVAL): Identifies the priority value for all cycles + that are initiated by TSunit. Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 (default) + 01 = Priority 1 + 10 = Priority 2 + 11 = Priority 3 + sarbcf_csr_ts_priority[1:0] +19:18 RW 00b Core + SFunit Priority Value (SQSFPRIVAL): + SFunit Priority Value (SQSFPRIVAL): Identifies the priority value for all cycles + that are initiated by SFunit. Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 (default) + 01 = Priority 1 + 10 = Priority 2 + 11 = Priority 3 + sarbcf_csr_sf_priority[1:0] +17:16 RW 00b Core + SVSM Priority Value (SQSVSMPRIVAL): + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 33 + Default + Bit Access Value RST/PWR Description + SVSM Priority Value (SQSVSMPRIVAL): Identifies the priority value for all cycles + that are initiated by SVSM. Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 (default) + 01 = Priority 1 + 10 = Priority 2 + 11 = Priority 3 + sarbcf_csr_svsm_priority[1:0] + +15:14 RW 00b Core + SARB Priority Value (SQSARBPRIVAL): + SARB Priority Value (SQSARBPRIVAL): Identifies the priority value for all cycles + that are initiated by State Arbiter (SARB). Priority is used in the L3 Super Queue + (L3SQ). + 00 = Priority 0 (default) + 01 = Priority 1 + 10 = Priority 2 + 11 = Priority 3 + sarbcf_csr_sarb_priority[1:0] +13:12 RW 01b Core + SBE Priority Value (SQSBEPRIVAL): + SBE Priority Value (SQSBEPRIVAL): Identifies the priority value for all cycles that + are initiated by SBE. Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 + 01 = Priority 1 (default) + 10 = Priority 2 + 11 = Priority 3 + sarbcf_csr_sbe_priority[1:0] +11:10 RW 10b Core + IC$ Priority Value (SQICPRIVAL): + IC$ Priority Value (SQICPRIVAL): Identifies the priority value for all cycles that + are initiated by Instruction Cache (IC$). Priority is used in the L3 Super Queue + (L3SQ). + 00 = Priority 0 + 01 = Priority 1 + 10 = Priority 2 (default) + 11 = Priority 3 + sarbcf_csr_ic_priority[1:0] + 9:8 RW 10b Core + TDL Priority Value (SQTDLPRIVAL): + TDL Priority Value (SQTDLPRIVAL): Identifies the priority value for all cycles that + are initiated by TDL. Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 34 + Default + Bit Access Value RST/PWR Description + 01 = Priority 1 + 10 = Priority 2 (default) + 11 = Priority 3 + sarbcf_csr_tdl_priority[1:0] + + 7:6 RW 10b Core + DCunit Priority Value (SQDCPRIVAL): + DCunit Priority Value (SQDCPRIVAL): Identifies the priority value for all cycles + that are initiated by DC. Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 + 01 = Priority 1 + 10 = Priority 2 (default) + 11 = Priority 3 + sarbcf_csr_dc_priority[1:0] + 5:4 RW 11b Core + DAPR Priority Value (SQDAPRPRIVAL): + DAPR Priority Value (SQDAPRPRIVAL): Identifies the priority value for all cycles + that are initiated by DAPR. Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 + 01 = Priority 1 + 10 = Priority 2 + 11 = Priority 3 (default) + sarbcf_csr_dapr_priority[1:0] + 3:2 RW 11b Core + MTunit Priority Value (SQMTPRIVAL): + MTunit Priority Value (SQMTPRIVAL): Identifies the priority value for all cycles + that are initiated by Sampler (MT). Priority is used in the L3 Super Queue (L3SQ). + 00 = Priority 0 + 01 = Priority 1 + 10 = Priority 2 + 11 = Priority 3 (default) + sarbcf_csr_mt_priority[1:0] + 1:0 RW 11b Core + LSQCunit Priority Value (SQPRIVAL): + LSQCunit Priority Value (SQPRIVAL): Identifies the priority value for all cycles + that are initiated by Super Queue (L3 Evictions). Priority is used in the L3 Super + Queue (L3SQ). + 00 = Priority 0 + 01 = Priority 1 + 10 = Priority 2 + 11 = Priority 3 (default) + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 35 + Default + Bit Access Value RST/PWR Description + sarbcf_csr_lsqc_priority[1:0] + + + +8.1.6 L3CNTLREG1 - L3 Control Register1 +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B01C-B01Fh +Default Value: 8C47FF80h +Access: RW; RO; +Size: 32 bits + + + Default + Bit Access Value RST/PWR Description +31:28 RW 1000b Core + Data Fifo Depth Control (DFIFODC): + Data Fifo Depth Control (TS mode) + Stall Control: POR is 1000b. Flexing for Hitting the stall + Validation scenarios + Maximum available setting for h/w is "1000" + sarbcf_csr_lc_datafifo_depth[3:0] + Due to w/a of bug#3665919, the depth has to be set to + “0011” +27:24 RW 1100b Core + Data Clock off time (DCLKOFFT): + Data Clock off time (DATACLKOFF): Data Clock off time - + Data block is shut off after these many number of clocks + programmed in this register bits. + sarbcf_csr_lc_dataclkoff_time[3:0] +23:20 RW 0100b Core + TAG CLK OFF TIME (TAGCLKOFF): + TAG CLK OFF TIME (TAGCLKOFF): TAG Clock Off time. + This is the time, which Clock gating Logic check before it + turn off the clock. + sarbcf_csr_lc_tagclkoff_time[3:0] + 19 RW 0b Core + L3 Aging Disable Bit (L3AGDIS): + L3 Aging Disable Bit (L3AGDIS): Aging Disable + sarbcf_csr_lc_agingdis + +18:15 RW 1111b Core + Fill aging (L3AGF): + Fill aging (L3AGF): Aging Counter for Fill + sarbcf_csr_lc_fill_aging_cnt[3:0] +14:11 RW 1111b Core + Aging Counter for Read 1 Port (L3AGR1): + Aging Counter for Read 1 Port (L3AGR1): Aging Counter + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 36 + Default + Bit Access Value RST/PWR Description + for Read 1 Port + sarbcf_csr_lc_rd1_aging_cnt[3:0] + +10:7 RW 1111b Core + L3 Aging Counter for R0 (L3AGR0): + L3 Aging Counter for R0 (L3AGR0): Aging Counter for R0 + Port + sarbcf_csr_lc_rd0_aging_cnt[3:0] + 6:3 RW 0000b Core + Number of NOPs (L3NOP): + Number of NOPs (L3NOP): Number of NOPs to be inserted + between the Tag commands. + sarbcf_csr_lc_num_nop[3:0] + Due to w/a of bug#3665919, the depth has to be set to + “0001” + 2 RW 0b Core + OP0/OP1 Disable (L3OPDIS): + OP0/OP1 Disable (L3OPDIS): This bit is used to enable the + feature of inserting the number of cycles between the tag + pipeline operation. + sarbcf_csr_lc_op0op1_disable + Due to w/a of bug#3665919, the OP1 has to be set to “1” + 1 RW 0b Core + L3 OP1 Disable Mode (L3OP1DIS): + L3 OP1 Disable Mode (L3OP1DIS): + OP1 in L3 can be disabled which means there will be one + Command transferred to the Tag pipeline in 1X Domain + sarbcf_csr_lc_op1_disable + Note: If this bit is set Aging mode needs to be disabled as + well. + 0 RO 0b Core + Reserved (RSVD): + Reserved + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 37 + 8.1.7 L3CNTLREG2 - L3 Control Register2 +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B020-B023h +Default Value: 00080040h +Access: RW; RO; +Size: 32 bits + + + Default + Bit Access Value RST/PWR Description +31:28 RO 0000b Core + Reserved (RSVD): + + 27 RW 0b Core + DC way assignment SLM Behavior (DCWASLMB): + DC way assignment SLM Behavior: In shared local memory mode DC is + assigned into low b/w mode which requires it to be assigned non-matched ways + of bigger banks and it will be hashed to 2 banks. + sarbcf_csr_dc_slm_lowbw +26:21 RW 000000b Core + DC Way Assignment (DCWASS): + DC Way Assignment: Number of ways allocated for DC. Note this allocation is + only for DC data types. 000000: 0KB000001: 8KB (4KB for GT1) 000010: 16KB + (8KB for GT1) 111111: 504KB (252KB for GT1)Note: This field must be 0KB is All + L3 Client Pool is non-zero. + sarbcf_csr_dc_size[5:0] + 20 RW 0b Core + RO Client Pool SLM Behavior (ROCPSLMB): + RO Client Pool SLM Behavior: In shared local memory mode Read Only Clients + are assigned into low b/w mode which requires it to be assigned non-matched + ways of bigger banks and it will be hashed to 2 banks. + sarbcf_csr_ro_slm_lowbw +19:14 RW 100000b Core + Read Only Client Pool (RDOCPL): + Read Only Client Pool: Number of ways allocated for ROnly L3 clients. This is a + combined pool for all RO clients. + 000000: 0KB + 000001: 8KB (4KB for GT1) + 000010: 16KB (8KB for GT1) + 111111: 504KB (252KB for GT1) + Note: If all ROClient pool is non-zero, than Inst/state, Const and Texture client + allocation should have 0KB allocation. + sarbcf_csr_ro_size[5:0] + +13:8 RW 000000b Core + All L3 Client Pool (ALL3CLPL): + All L3 Client Pool: Number of ways allocated for all L3 clients. This is a combined + pool for all L3 clients. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 38 + Default + Bit Access Value RST/PWR Description + 000000: 0KB + 000001: 8KB (4KB for GT1) + 000010: 16KB (8KB for GT1) + 111111: 504KB (252KB for GT1) + Note: If all L3 Client pool is non-zero, than all L3 client pools should have 0KB + allocation. + sarbcf_csr_l3_size[5:0] + + 7 RW 0b Core + URB SLM Behavior (URBSLMB): + URB SLM Behavior: In shared local memory mode URB is assigned into low b/w + mode which requires it to be assigned non-matched ways of bigger banks and it + will be hashed to 2 banks. + sarbcf_csr_urb_slm_lowbw + 6:1 RW 100000b Core + URB Allocation (URBALL): + URB Allocation: Number of ways allocated for URB usage + 000000: 0KB + 000001: 8KB (4KB for GT1) + 000010: 16KB (8KB for GT1) + 111111: 504KB (252KB for GT1) + sarbcf_csr_urb_size[5:0] + 0 RW 0b Core + SLM Mode Enable (SLMMENB): + SLM Mode Enable: When enabled, a 128KB region of L3 is reserved for SLM. + This allocation is done on 2 banks with 64KB per half-slice. + 0: SLM is disabled + 1: SLM is enabled + Note: For GT1, there is only one 64KB allocation for single half-slice. + sarbcf_csr_slm_mode + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 39 + 8.1.8 L3CNTLREG3 - L3 Control Register3 +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B024-B027h +Default Value: 00000000h +Access: RO; RW; +Size: 32 bits + + + Default + Bit Access Value RST/PWR Description +31:22 RO 0000000000b Core + Reserved (RSVD): + + 21 RW 0b Core + Textures Way Allocation SLM Behavior (TWALSLMB): + Textures Way Allocation SLM Behavior: In shared local memory mode + Textures is assigned into low b/w mode which requires it to be assigned non- + matched ways of bigger banks and it will be hashed to 2 banks. + sarbcf_csr_tex_slm_lowbw + +20:15 RW 000000b Core + Textures Way Allocation (TXWYALL): + Textures Way Allocation: Number of ways allocated for Textures. + 000000: 0KB + 000001: 8KB (4KB for GT1) + 000010: 16KB (8KB for GT1) + 111111: 504KB (252KB for GT1) + Note: This field must be 0KB is All L3 Client Pool or Read-Only Client Pool is + non-zero. + sarbcf_csr_tex_size[5:0] + 14 RW 0b Core + Constants Way Allocation SLM Behavior (CWASLMB): + Constants Way Allocation SLM Behavior: In shared local memory mode + Instruction/state is assigned into low b/w mode which requires it to be + assigned non-matched ways of bigger banks and it will be hashed to 2 banks. + sarbcf_csr_const_slm_lowbw +13:8 RW 000000b Core + Constants Way Allocation (CTWALL): + Constants Way Allocation: Number of ways allocated for Constants. + 000000: 0KB + 000001: 8KB (4KB for GT1) + 000010: 16KB (8KB for GT1) + 111111: 504KB (252KB for GT1) + Note: This field must be 0KB is All L3 Client Pool or Read-Only Client Pool is + non-zero. + sarbcf_csr_const_size[5:0] + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 40 + Default + Bit Access Value RST/PWR Description + 7 RW 0b Core + Instruction/State Way Allocation SLM Behavior (ISWASLMB): + Instruction/State Way Allocation SLM Behavior: In shared local memory mode + Instruction/state is assigned into low b/w mode which requires it to be + assigned non-matched ways of bigger banks and it will be hashed to 2 banks. + sarbcf_csr_is_slm_lowbw + + 6:1 RW 000000b Core + Instruction/State Way Allocation (ISWYALL): + Instruction/State Way Allocation: Number of ways allocated for + Instruction/State usage + 000000: 0KB + 000001: 8KB (4KB for GT1) + 000010: 16KB (8KB for GT1) + 111111: 504KB (252KB for GT1) + Note: This field must be 0KB is All L3 Client Pool or Read-Only Client Pool is + non-zero. + sarbcf_csr_is_size[5:0] + 0 RO 0b Core + Reserved (RSVD): + Reserved + + + + +8.1.9 L3SLMREG - L3 SLM Register +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B028-B02Bh +Default Value: 40000000h +Access: RO; RW; +Size: 32 bits + + + Default + Bit Access Value RST/PWR Description + 31 RW 0b Core + Disable Periodic SLM/SQ slot allocation (DPSLMALL): + Disable Periodic SLM/SQ slot allocation: When cfg_lslm_livelock_fairarb_dis=1 + lslm unit will always have the higher priority and lslm_lsqc_block to lsqcunit is + asserted as long as there are requests in SLM FIFO + sarbcf_csr_lslm_livelock_fairarb_dis + +30:27 RW 1000b Core + LSLM_SQ_PENDING_MAX (LSLMSQPEND): + If lslmunit has read data to be sent to lcbrunit this cfg register specifies the + maximum number of clocks for which LSLMunit can block SQ request from + being sent to lcbrunit + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 41 + Default + Bit Access Value RST/PWR Description + Default value = 8 + sarbcf_csr_lslm_sqpend_max[3:0] + +26:0 RO 0000000h Core + Reserved (RSVD): + + + + +8.1.10 GARBCNTLREG - Arbiter Control Register +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B02C-B02Fh +Default Value: 29000000h +Access: RO; RW; +Size: 32 bits + + + Default + Bit Access Value RST/PWR Description + 31 + 30 RW 0b Core + Disables hashing function (DISHHF): + Disables hashing function to generate bank_id[1:0] for L3$ bank accessing, and + forces the use of address[7:6] for bank_id[1:0]. + 0 : (default) Hash function enabled to generate L3$ bank IDs. + 1 : L3$ address[7:6] used as L3$ bank IDs. + sarbcf_csr_l3bankidhashdis +29:28 RW 10b Core + Arbitration priority order between RCC and MSC (APORM): + Arbitration priority order between RCC and MSC. + 00/11: Invalid; default setting used + 10 : Default setting; RCC < MSC (i.e., MSC has higher priority) + 01: RCC > MSC (i.e., RCC has higher priority) + sarbcf_csr_rcc_msc_pri[1:0] + +27:22 RW 100100b Core + Arbitration priority order between RCZ, STC, and HIZ (APORSH): + Arbitration priority order between RCZ, STC, and HIZ. + 100100 : Default setting; RCZ < STC < HIZ (i.e., RCZ has lowest + priority; HIZ has highest priority) + 100001 : RCZ < HIZ < STC0 + 11000 : STC < RCZ < HIZ0 + 10010 : STC < HIZ < RCZ + 001001 : HIZ < RCZ < STC + 000110 : HIZ < STC < RCZ + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 42 + Default + Bit Access Value RST/PWR Description + Note: Others settings are invalid, and result in use of default. + sarbcf_csr_rcz_stc_hiz_pri[5:0] + +21:19 RW 000b Core + Write data port arbitration priority between Z client writes and L3$ + evictions (WDPAGAPZ): + Write data port arbitration priority between Z client writes and L3$ evictions. + 000 : L3:Z=1:0 - i.e., L3$ evictions > Z writes; Fixed priority; Default setting. + 001 : L3:Z=1:1 - i.e., L3$ evictions = Z writes; Round-robin priority + 010 : L3:Z=2:1 - i.e., Z writes will have higher priority after 2 L3$ evictions have + been continuously granted earlier + 011 : L3:Z=3:1 - i.e., Z writes will have higher priority after 3 L3$ evictions have + been continuously granted earlier + ... + 111 : L3:Z=7:1 - i.e., Z writes will have higher priority after 7 L3$ evictions have + been continuously granted + sarbcf_csr_wdpagapz[2:0] +18:16 RW 000b Core + Write data port arbitration priority between C client writes and Z/L3$ + writes/evictions (WDPAGAPC): + Write data port arbitration priority between C client writes and Z/L3$ + writes/evictions. + 000 : L3:Z=1:0 – i.e., Z/L3$ writes/evictions > C writes; Fixed priority; Default + setting. + 001 : L3:Z=1:1 – i.e., Z/L3$ writes/evictions = C writes; Round-robin priority + 010 : L3:Z=2:1 – i.e., C writes will have higher priority after 2 Z/L3$ + writes/evictions have been continuously granted earlier + 011 : L3:Z=3:1 – i.e., C writes will have higher priority after 3 Z/L3$ + writes/evictions have been continuously granted earlier + ... + 111 : L3:Z=7:1 – i.e., C writes will have higher priority after 7 Z/L3$ + writes/evictions have been continuously granted earlier + sarbcf_csr_wdpagapc[2:0] +15:0 RO 0000h Core + Reserved (RSVD): + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 43 + 8.1.11 L3SQCREG4 - L3 SQC register 4 +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B034-B037h +Default Value: 08000000h +Access: RWHC; RO; RW; +Size: 32 bits + + + Default + Bit Access Value RST/PWR Description + 31 RO 0b Core + Reserved (RSVD): + + 30 RW 0b Core + L3SQ Mode select for FF32 cycles on Crossbar 0/2 (SQFF32MODE): + L3SQ Mode select for FF32 cycles on Crossbar 0/2 (SQFF32MODE): + Selects the mode in which SQ arbitrates FF32 cycles versus Half slice clients + during Crossbar 2 arbitration. Qualified with the assertion of the crossbar 0/2 + enable (SQFF32EN). + In mode 0, crossbar 0/2 arbitration operates normally, and is determined strictly + by the priority bits assigned by client (SQ*PRIVAL). + In mode 1, FF32 priority values are determined by the FF32 priority override + (SQFF32PRIOVER) when an indication is observed from GAFS (greater than 32 + FF cycles are pending) + 1 = all FF32 cycles will receive the overridden value instead of the default client + priority value when indicated by GAFS counter + 0 = all FF32 cycles will receive normal priority values (default) +29:28 RW 00b Core + L3SQ Priority Override for FF32 cycles on Crossbar 0/2 (SQFF32PRIOVER): + L3SQ Priority Override for FF32 cycles on Crossbar 0/2 (SQFF32PRIOVER): + Identifies the priority value for all FF32 cycles that are initiated by GAL3. Priority is + used in the L3 Super Queue (L3SQ). Qualified with the assertion of the crossbar + 0/2 enable (SQFF32EN) and the assertion of ff32 mode select (SQFF32MODE). + 00 = Priority 0 (default) + 01 = Priority 1 + 10 = Priority 2 + 11 = Priority 3 + 27 RW 1b Core + L3SQ URB Read CAM Match Disable (SQURBRDCAMDIS): + L3SQ URB Read CAM Match Disable (SQURBRDCAMDIS): + Disables the L3SQ Cam Match ability for URB Reads. By disabling, this allows a + performance mode where URB reads are not dependent upon one another but + only on any previous URB writes to the same address. This allows many URB + reads to the same cacheline at any given time instead of serializing the requests. + 1 = URB Read CAM matching is disabled; multiple URB reads to the same + cacheline are allowed to be concurrent(default) + 0 = URB Read CAM matching is enabled; multiple URB reads to the same + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 44 + Default + Bit Access Value RST/PWR Description + cacheline are serialized + + 26 RWHC 0b Core + LSQC reset fcount (LSQCRFCNT): + self clearing register bit - Write to this register generates 1 clock pulse + sarbcf_csr_lsqc_rst_fcount to lsqc and also used to clear the register + sarbcf_csr_lsqc_rst_fcount_lvl is output of configdb. + 25 RWHC 0b Core + LSLM1 reset fcount (LSLM1RFCNT): + self clearing register bit - Write to this register generates 1 clock pulse + sarbcf_csr_lslm1_rst_fcount goes to lslm1 and also used to clear this register bit + sarbcf_csr_lslm1_rst_fcount_lvl is ouput of configdb + 24 RWHC 0b Core + LSLM3 reset fcount (LSLM3RFCNT): + self clearing register bit - Write to this register generates 1 clock pulse + sarbcf_csr_lslm3_rst_fcount goes to lslm3 and used to clear this register too + sarbcf_csr_lslm1_rst_fcount_lvl is output of configdb. +23:0 RO 000000h Core + reserved (RSVD): + + + + +8.1.12 SCRATCH1 - SCRATCH1 +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B038-B03Bh +Default Value: 00000000h +Access: RWHC; RO; RW; +Size: 32 bits + + + Bit Access Default Value RST/PWR Description +31:1 RW 00000000h Core + SCRATCH (SCRATCH): + + 0 RW 0b Core + L3 Starvation Limit: + sarbcf_csr_hs_l3starvlimit - + 0 : GAHS* could get starved if HDC reads are streaming + 1 : GAHS* arbitrated at higher priority than HDC* read reqs + serviced in 7 clocks + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 45 + 8.1.13 L3B0REG1 - L3 bank0 reg1 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B074-B077h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error. +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error. + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 46 + 8.1.14 L3B0REG2 - L3 bank0 reg2 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B078-B07Bh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error. + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error. + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 47 + 8.1.15 L3B0REG3 - L3 bank0 reg3 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B07C-B07Fh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 48 + 8.1.16 L3B0REG4 - L3 bank0 reg4 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B080-B083h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 49 + 8.1.17 L3B0REG5 - L3 bank0 reg5 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B084-B087h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 50 + 8.1.18 L3B0REG6 - L3 bank0 reg6 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B088-B08Bh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 51 + 8.1.19 L3B0REG7 - L3 bank0 reg7 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B08C-B08Fh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 52 + 8.1.20 L3B1REG0 - L3 bank1 reg0 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B090-B093h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 53 + 8.1.21 L3B1REG1 - L3 bank1 reg1 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B094-B097h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 54 + 8.1.22 L3B1REG2 - L3 bank1 reg2 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B098-B09Bh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 55 + 8.1.23 L3B1REG3 - L3 bank1 reg3 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B09C-B09Fh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 56 + 8.1.24 L3B1REG4 - L3 bank1 reg4 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0A0-B0A3h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 57 + 8.1.25 L3B1REG5 - L3 bank1 reg5 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0A4-B0A7h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 58 + 8.1.26 L3B1REG6 - L3 bank1 reg6 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0A8-B0ABh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 59 + 8.1.27 L3B1REG7 - L3 bank1 reg7 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0AC-B0AFh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 60 + 8.1.28 L3B2REG0 - L3 bank2 reg0 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0B0-B0B3h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 61 + 8.1.29 L3B2REG1 - L3 bank2 reg1 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0B4-B0B7h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 62 + 8.1.30 L3B2REG2 - L3 bank2 reg2 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0B8-B0BBh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 63 + 8.1.31 L3B2REG3 - L3 bank2 reg3 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0BC-B0BFh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 64 + 8.1.32 L3B2REG4 - L3 bank2 reg4 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0C0-B0C3h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 65 + 8.1.33 L3B2REG5 - L3 bank2 reg5 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0C4-B0C7h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 66 + 8.1.34 L3B2REG6 - L3 bank2 reg6 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0C8-B0CBh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 67 + 8.1.35 L3B2REG7 - L3 bank2 reg7 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0CC-B0CFh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 68 + 8.1.36 L3B3REG0 - L3 bank3 reg0 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0D0-B0D3h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 69 + 8.1.37 L3B3REG1 - L3 bank3 reg1 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0D4-B0D7h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 70 + 8.1.38 L3B3REG2 - L3 bank3 reg2 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0D8-B0DBh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 71 + 8.1.39 L3B3REG3 - L3 bank3 reg3 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0DC-B0DFh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 72 + 8.1.40 L3B3REG4 - L3 bank3 reg4 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0E0-B0E3h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 73 + 8.1.41 L3B3REG5 - L3 bank3 reg5 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0E4-B0E7h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 74 + 8.1.42 L3B3REG6 - L3 bank3 reg6 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0E8-B0EBh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 75 + 8.1.43 L3B3REG7 - L3 bank3 reg7 log error +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B0EC-B0EFh +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits +The ERROR LOG registers of L3 will maintain the bad row information for each of the 16KB subbank +groups. The LOG will be programmed by driver before any workloads are submitted. The contents of the +LOG register will be context Save&Restored by h/w around rc6 events. + Default + Bit Access Value RST/PWR Description +31:21 RW 000h Core + Row Number for Error1 (RNUMERR1): + Row Number for Error1: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + +20:17 RO 0000b Core + Reserved (RSVD): + + 16 RW 0b Core + Valid Error 1 (VLDERR1): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. +15:5 RW 000h Core + Row Number for Error0 (RNUMERR0): + Row Number for Error0: The physical row number where the parity error has been + detected. The number of rows vary between 4K vs 8K/16K subbanks which + requires 10bits vs 11bits respectively. This field contains the row# with the error + 4:1 RO 0000b Core + Reserved (RSVD): + + 0 RW 0b Core + Valid Error 0 (VLDERR0): + Valid Error: The error located in field 15:5 is valid and corresponding logical 16KB + group should bypass this row. + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 76 + 8.1.44 SARBCSR - SARB config save msg +B/D/F/Type: 0/0/0/SARBunit_Config +Address Offset: B1FC-B1FFh +Default Value: 00000000h +Access: RWHC; RO; +Size: 32 bits +This register is not context saved + Default + Bit Access Value RST/PWR Description +31:2 RO 00000000h Core + Reserved (RSVD): + + 1 RWHC 0b Core + Context restore ack (CTXRSTRACK): + A write from cs to this bit along with mask bit 17 will prompt sarb to ack ctx + restore ack . + sarb_ctx_restore - ctx restore from cs + clr_sarb_ctx_restore - sarb clr this bit. + 0 RWHC 0b Core + Context save bit (SARBCS): + A write from cs to this bit along with mask bit 16 will prompt sarb to start + context save to cs. + sarb_ctx_save - ctx save from cs + clr_sarb_ctx_save - sarb clr this bit once ctx save sm kicks in . + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 77 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V1 Pt 7 – 05 12 5/31/2012 78 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol2_part1.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol2_part1.txt new file mode 100644 index 0000000..b9c8d19 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol2_part1.txt @@ -0,0 +1,18116 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 2 Part 1: 3D/Media – 3D Pipeline +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 5/29/2012 2 + Contents +1. 3D Pipeline ............................................................................................................................................. 9 + 1.1 Introduction .......................................................................................................................................... 9 + 1.2 3D Pipeline Overview ........................................................................................................................... 9 + 1.2.1 3D Pipeline Stages ......................................................................................................................... 9 + 1.3 3D Primitives Overview ...................................................................................................................... 10 + 1.4 3D Pipeline State Overview ............................................................................................................... 16 + 1.4.1 3D State Model ............................................................................................................................. 16 + 1.4.2 3DSTATE_CC_STATE_POINTERS ............................................................................................ 18 + 1.4.3 3DSTATE_BLEND_STATE_POINTERS ..................................................................................... 19 + 1.4.4 3DSTATE_DEPTH_STENCIL_STATE_POINTERS .................................................................... 20 + 1.4.5 3DSTATE_BINDING_TABLE_POINTERS .................................................................................. 21 + 1.5 3DSTATE_SAMPLER_STATE_POINTERS...................................................................................... 26 + 1.5.1 1.5.1 3DSTATE_SAMPLER_STATE_POINTERS_VS ............................................................... 26 + 1.5.2 3DSTATE_SAMPLER_STATE_POINTERS_HS ......................................................................... 27 + 1.5.3 3DSTATE_SAMPLER_STATE_POINTERS_DS ......................................................................... 28 + 1.5.4 3DSTATE_SAMPLER_STATE_POINTERS_GS ......................................................................... 29 + 1.5.5 3DSTATE_SAMPLER_STATE_POINTERS_PS ......................................................................... 30 + 1.6 3DSTATE_VIEWPORT_STATE_POINTERS.................................................................................... 31 + 1.6.1 3DSTATE_VIEWPORT_STATE_POINTERS_CC ....................................................................... 31 + 1.6.2 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP ............................................................. 32 + 1.6.3 3DSTATE_SCISSOR_STATE_POINTERS ................................................................................. 33 + 1.7 3DSTATE_URB Commands .............................................................................................................. 34 + 1.7.1 3DSTATE_URB_VS ..................................................................................................................... 34 + 1.7.2 3DSTATE_URB_HS ..................................................................................................................... 36 + 1.7.3 3DSTATE_URB_DS ..................................................................................................................... 37 + 1.7.4 3DSTATE_URB_GS ..................................................................................................................... 39 + 1.7.5 Gather Constants ......................................................................................................................... 40 + 1.7.6 Dx9 Constant Buffer Generation .................................................................................................. 40 + 1.8 Vertex Data Overview ........................................................................................................................ 41 + 1.8.1 Vertex URB Entry (VUE) Formats ................................................................................................ 41 + 1.8.2 Vertex Positions ............................................................................................................................ 43 + 1.9 3D Pipeline Stage Overview .............................................................................................................. 45 + 1.9.1 Generic 3D FF Unit Block Diagram .............................................................................................. 46 + 1.9.2 1Common 3D FF Unit Functions .................................................................................................. 46 + 1.9.3 Thread Initiation Management ...................................................................................................... 48 + 1.9.4 Thread Request Generation ......................................................................................................... 48 + 1.9.5 Thread Output Handling ............................................................................................................... 54 + 1.9.6 VUE Readback ............................................................................................................................. 54 + 1.9.7 Statistics Gathering ...................................................................................................................... 54 + 1.10 Synchronization of the 3D Pipeline ................................................................................................... 56 + 1.10.1 Top-of-Pipe Synchronization ...................................................................................................... 56 + 1.10.2 End-of-Pipe Synchronization ...................................................................................................... 56 + 1.10.3 Synchronization Actions ............................................................................................................. 57 + 1.10.4 PIPE_CONTROL Command ...................................................................................................... 58 + 1.11 Push Constant URB Allocation ......................................................................................................... 67 +2. 3D Pipeline – Vertex Fetch (VF) Stage .............................................................................................. 71 + 2.1 Vertex Fetch (VF) Stage Overview .................................................................................................... 71 + 2.1.1 Input Assembly ............................................................................................................................. 71 + 2.1.2 Vertex Cache ................................................................................................................................ 72 + 2.1.3 Input Data: Push Model vs. Pull Model ........................................................................................ 72 + 2.1.4 Generated IDs .............................................................................................................................. 72 + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 5/29/2012 3 + 2.2 Index Buffer (IB) ................................................................................................................................. 73 + 2.2.1 3DSTATE_INDEX_BUFFER ........................................................................................................ 73 + 2.2.2 Index Buffer Access ...................................................................................................................... 76 + 2.3 Vertex Buffers (VBs) .......................................................................................................................... 76 + 2.3.1 3DSTATE_VERTEX_BUFFERS .................................................................................................. 77 + 2.3.2 VERTEX_BUFFER_STATE Structure ......................................................................................... 78 + 2.3.3 VERTEXDATA Buffers – SEQUENTIAL Access.......................................................................... 81 + 2.3.4 VERTEXDATA Buffers – RANDOM Access ................................................................................ 82 + 2.3.5 INSTANCEDATA Buffers ............................................................................................................. 83 + 2.4 Input Vertex Definition ........................................................................................................................ 83 + 2.4.1 3DSTATE_VERTEX_ELEMENTS ............................................................................................... 84 + 2.4.2 VERTEX_ELEMENT_STATE Structure ....................................................................................... 85 + 2.4.3 Vertex Element Data Path ............................................................................................................ 89 + 2.5 3D Primitive Processing ..................................................................................................................... 90 + 2.5.1 3D PRIMITIVE Command ............................................................................................................ 90 + 2.5.2 Functional Overview ..................................................................................................................... 94 + 2.5.3 CommandInit ................................................................................................................................ 94 + 2.5.4 InstanceLoop ................................................................................................................................ 94 + 2.5.5 VertexLoop ................................................................................................................................... 95 + 2.5.6 VertexIndexGeneration ................................................................................................................. 95 + 2.5.7 TerminatePrimitive ........................................................................................................................ 96 + 2.5.8 VertexCacheLookup ..................................................................................................................... 96 + 2.5.9 VertexElementLoop ...................................................................................................................... 96 + 2.5.10 SourceElementFetch .................................................................................................................. 97 + 2.5.11 Format Conversion ..................................................................................................................... 97 + 2.5.12 DestinationFormatSelection ....................................................................................................... 99 + 2.5.13 PrimitiveInfoGeneration ............................................................................................................ 100 + 2.5.14 URBWrite .................................................................................................................................. 101 + 2.5.15 OutputBufferedVertex ............................................................................................................... 101 + 2.6 Dangling Vertex Removal ................................................................................................................ 101 + 2.7 Other Vertex Fetch Functionality ..................................................................................................... 102 + 2.7.1 Statistics Gathering .................................................................................................................... 102 +3. 3D Pipeline – Vertex Shader (VS) Stage .......................................................................................... 104 + 3.1 VS Stage Overview .......................................................................................................................... 104 + 3.1.1 Vertex Caching ........................................................................................................................... 104 + 3.2 VS Stage Input ................................................................................................................................. 106 + 3.2.1 State ........................................................................................................................................... 106 + 3.2.2 Input Vertices .............................................................................................................................. 116 + 3.3 SIMD4x2 VS Thread Request Generation ....................................................................................... 116 + 3.3.1 Thread Payload .......................................................................................................................... 117 + 3.4 SIMD4x2 VS Thread Execution ....................................................................................................... 119 + 3.4.1 Vertex Output.............................................................................................................................. 119 + 3.4.2 Thread Termination .................................................................................................................... 119 + 3.5 Primitive Output ................................................................................................................................ 119 + 3.6 Other VS Functions .......................................................................................................................... 119 + 3.6.1 Statistics Gathering .................................................................................................................... 119 +4. 3D Pipeline – Hull Shader (HS) Stage .............................................................................................. 121 + 4.1 HS Stage Overview .......................................................................................................................... 121 + 4.2 HS Stage Input ................................................................................................................................. 121 + 4.2.1 State ........................................................................................................................................... 121 + 4.3 3DSTATE_CONSTANT_HS ............................................................................................................ 124 + 4.4 3DSTATE_HS .................................................................................................................................. 127 + 4.5 Patch Object Staging ....................................................................................................................... 133 + 4.6 HS Thread Payload .......................................................................................................................... 133 + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 5/29/2012 4 + 4.6.1 SINGLE_PATCH Layout (SINGLE-PATCH Mode) .................................................................... 133 + 4.7 HS Thread Execution ....................................................................................................................... 136 + 4.7.1 Dispatch Mask ............................................................................................................................ 137 + 4.8 ICP Dereferencing............................................................................................................................ 137 + 4.9 Patch URB Entry (Patch Record) Output ......................................................................................... 137 + 4.9.1 Patch Header .............................................................................................................................. 137 + 4.9.2 DOMAIN_POINT Structure ......................................................................................................... 139 + 4.10 Statistics Gathering......................................................................................................................... 140 + 4.10.1 HS Invocations ......................................................................................................................... 140 +5. 3D Pipeline – Tessellation Engine (TE) ........................................................................................... 141 + 5.1 3DSTATE_TE .................................................................................................................................. 141 + 5.2 Domain Types and Output Topologies ............................................................................................ 144 + 5.3 QUAD Domain Tessellation ............................................................................................................. 144 + 5.3.1 TRI Domain Tessellation ............................................................................................................ 146 + 5.4 ISOLINE Domain Tessellation ......................................................................................................... 147 + 5.5 Patch Culling .................................................................................................................................... 147 + 5.6 Tessellation Factor Limits ................................................................................................................ 147 + 5.7 Partitioning ....................................................................................................................................... 148 +6. 3D Pipeline – Domain Shader (DS) Stage ....................................................................................... 149 + 6.1 3DSTATE_DS .................................................................................................................................. 149 + 6.1.1 3DSTATE_PUSH_CONSTANT_ALLOC_DS ............................................................................. 154 + 6.1.2 3DSTATE_CONSTANT_DS....................................................................................................... 156 + 6.2 Thread Payload ................................................................................................................................ 159 + 6.3 DS Thread Execution ....................................................................................................................... 163 + 6.4 Statistics Gathering .......................................................................................................................... 164 +7. 3D Pipeline – Geometry Shader (GS) Stage ................................................................................... 165 + 7.1 GS Stage Overview.......................................................................................................................... 165 + 7.2 GS Stage Input ................................................................................................................................. 165 + 7.2.1 State ........................................................................................................................................... 165 + 7.3 Object Staging .................................................................................................................................. 178 + 7.4 GS Thread Request Generation ...................................................................................................... 178 + 7.4.1 Object Vertex Ordering ............................................................................................................... 178 + 7.4.2 GS Thread Payload High-Level Layout ...................................................................................... 182 + 7.4.3 GS Thread Payload SIMD 4x2 ................................................................................................... 183 + 7.5 GS Thread Execution ....................................................................................................................... 188 + 7.5.1 GS Thread Output ...................................................................................................................... 189 + 7.5.2 Stream Output ............................................................................................................................ 190 + 7.5.3 Thread Termination .................................................................................................................... 191 + 7.6 Primitive Output ................................................................................................................................ 191 + 7.7 Other Functionality ........................................................................................................................... 191 + 7.7.1 Statistics Gathering .................................................................................................................... 191 +8. 3D Pipeline - Stream Output Logic (SOL) Stage ............................................................................ 193 + 8.1 Input Buffering .................................................................................................................................. 193 + 8.2 Stream Output Buffers ..................................................................................................................... 195 + 8.3 Stream Output Function ................................................................................................................... 196 + 8.4 3DSTATE_STREAMOUT ................................................................................................................ 196 + 8.5 3DSTATE_SO_DECL_LIST Command ........................................................................................... 201 + 8.5.1 SO_DECL Structure Definition ................................................................................................... 205 + 8.6 3DSTATE_SO_BUFFER ................................................................................................................. 207 + 8.7 Rendering Disable............................................................................................................................ 208 + 8.8 Statistics ........................................................................................................................................... 208 +9. 3D Pipeline – Clip Stage ................................................................................................................... 209 + 9.1 3D Pipeline – CLIP Stage Overview ................................................................................................ 209 + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 5/29/2012 5 + 9.1.1 Clip Stage – General-Purpose Processing ................................................................................. 209 + 9.1.2 Clip Stage – 3D Clipping ............................................................................................................ 209 + 9.1.3 Fixed Function Clipper ................................................................................................................ 210 + 9.2 Concepts .......................................................................................................................................... 210 + 9.2.1 The Clip Volume ......................................................................................................................... 210 + 9.2.2 User-Specified Clipping .............................................................................................................. 212 + 9.2.3 Guard Band ................................................................................................................................ 212 + 9.2.4 Vertex-Based Clip Testing & Considerations ............................................................................. 215 + 9.2.5 3D Clipping ................................................................................................................................. 217 + 9.3 CLIP Stage Input .............................................................................................................................. 217 + 9.3.1 State ........................................................................................................................................... 218 + 9.4 Object Staging .................................................................................................................................. 223 + 9.4.1 Partial Object Removal ............................................................................................................... 223 + 9.4.2 ClipDetermination Function ........................................................................................................ 223 + 9.4.3 ClipMode..................................................................................................................................... 226 + 9.5 Object Pass-Through ....................................................................................................................... 227 + 9.6 Primitive Output ................................................................................................................................ 228 + 9.7 Other Functionality ........................................................................................................................... 229 + 9.7.1 Statistics Gathering .................................................................................................................... 229 +10. 3D Pipeline - Strips and Fans (SF) Stage ........................................................................................ 230 + 10.1 Overview ......................................................................................................................................... 230 + 10.1.1 Inputs from CLIP ....................................................................................................................... 230 + 10.1.2 Attribute Setup/Interpolation Process ....................................................................................... 231 + 10.1.3 Outputs to WM .......................................................................................................................... 231 + 10.2 Primitive Assembly ......................................................................................................................... 231 + 10.2.1 Point List Decomposition .......................................................................................................... 234 + 10.2.2 Line List Decomposition ........................................................................................................... 235 + 10.2.3 Line Strip Decomposition .......................................................................................................... 236 + 10.2.4 Triangle List Decomposition ..................................................................................................... 237 + 10.2.5 Triangle Strip Decomposition ................................................................................................... 238 + 10.2.6 Triangle Fan Decomposition..................................................................................................... 239 + 10.2.7 Polygon Decomposition ............................................................................................................ 240 + 10.2.8 Rectangle List Decomposition .................................................................................................. 240 + 10.3 Object Setup ................................................................................................................................... 241 + 10.3.1 Invalid Position Culling (Pre/Post-Transform) .......................................................................... 241 + 10.3.2 Viewport Transformation .......................................................................................................... 241 + 10.3.3 Destination Origin Bias ............................................................................................................. 241 + 10.3.4 Point Rasterization Rule Adjustment ........................................................................................ 242 + 10.3.5 Drawing Rectangle Offset Application ...................................................................................... 243 + 10.3.6 Point Width Application ............................................................................................................. 246 + 10.3.7 Rectangle Completion .............................................................................................................. 247 + 10.3.8 Vertex X,Y Clamping and Quantization .................................................................................... 247 + 10.3.9 Degenerate Object Culling ....................................................................................................... 248 + 10.3.10 Triangle Orientation (Face) Culling ........................................................................................ 248 + 10.3.11 Scissor Rectangle Clipping..................................................................................................... 249 + 10.3.12 Line Rasterization ................................................................................................................... 250 + 10.3.13 3DSTATE_SF ......................................................................................................................... 257 + 10.3.14 3DSTATE_SBE ...................................................................................................................... 263 + 10.3.15 SF_CLIP_VIEWPORT ............................................................................................................ 270 + 10.3.16 SCISSOR_RECT .................................................................................................................... 271 + 10.4 Attribute Interpolation Setup ........................................................................................................... 272 + 10.4.1 Attribute Swizzling .................................................................................................................... 272 + 10.4.2 1Interpolation Modes ................................................................................................................ 273 + 10.4.3 Point Sprites ............................................................................................................................. 273 + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 5/29/2012 6 + 10.5 Depth Offset .................................................................................................................................... 274 + 10.6 Other SF Functions ......................................................................................................................... 274 + 10.6.1 Statistics Gathering .................................................................................................................. 274 +11. 3D Pipeline – Windower (WM) Stage ............................................................................................... 275 + 11.1 Overview ......................................................................................................................................... 275 + 11.1.1 Inputs from SF to WM ............................................................................................................... 275 + 11.2 Windower Pipelined State............................................................................................................... 276 + 11.2.1 3DSTATE_WM ......................................................................................................................... 276 + 11.2.2 3DSTATE_PS ........................................................................................................................... 283 + 11.2.3 3DSTATE_CONSTANT_PS ..................................................................................................... 291 + 11.2.4 3DSTATE_PUSH_CONSTANT_ALLOC_PS ........................................................................... 292 + 11.2.5 3DSTATE_SAMPLE_MASK..................................................................................................... 293 + 11.3 Rasterization ................................................................................................................................... 294 + 11.3.1 Drawing Rectangle Clipping ..................................................................................................... 295 + 11.3.2 Line Rasterization ..................................................................................................................... 295 + 11.3.3 Polygon (Triangle and Rectangle) Rasterization ...................................................................... 300 + 11.4 Multisampling .................................................................................................................................. 303 + 11.4.1 Multisample Modes/State ......................................................................................................... 303 + 11.4.2 3DSTATE_MULTISAMPLE ...................................................................................................... 304 + 11.5 Early Depth/Stencil Processing ...................................................................................................... 309 + 11.5.1 Depth Offset.............................................................................................................................. 309 + 11.5.2 Early Depth Test/Stencil Test/Write.......................................................................................... 310 + 11.5.3 Hierarchical Depth Buffer ......................................................................................................... 311 + 11.5.4 Separate Stencil Buffer............................................................................................................. 314 + 11.5.5 Depth/Stencil Buffer State ........................................................................................................ 315 + 11.6 Barycentric Attribute Interpolation .................................................................................................. 325 + 11.7 MCS Buffer for Render Target(s) ................................................................................................... 325 + 11.8 Render Target Fast Clear ............................................................................................................... 328 + 11.9 Render Target Resolve................................................................................................................... 328 + 11.10 Pixel Shader Thread Generation .................................................................................................. 329 + 11.10.1 Pixel Grouping (Dispatch Size) Control .................................................................................. 329 + 11.10.2 Multisampling Effects on Pixel Shader Dispatch .................................................................... 332 + 11.10.3 PS Thread Payload for Normal Dispatch ............................................................................... 336 + 11.11 Other WM Functions ..................................................................................................................... 349 + 11.11.1 Statistics Gathering ................................................................................................................ 349 +12. 3D Pipeline – Color Calculator (Output Merger)............................................................................. 351 + 12.1 Overview ......................................................................................................................................... 351 + 12.1.1 Alpha Coverage ........................................................................................................................ 352 + 12.1.2 Alpha Test................................................................................................................................. 352 + 12.1.3 Depth Coordinate Offset ........................................................................................................... 353 + 12.1.4 Stencil Test ............................................................................................................................... 353 + 12.1.5 Depth Test ................................................................................................................................ 354 + 12.1.6 Pre-Blend Color Clamping ........................................................................................................ 354 + 12.1.7 Color Buffer Blending ............................................................................................................... 355 + 12.1.8 Post-Blend Color Clamping ...................................................................................................... 357 + 12.1.9 Dithering ................................................................................................................................... 358 + 12.1.10 Logic Ops................................................................................................................................ 358 + 12.1.11 Buffer Update ......................................................................................................................... 359 + 12.2 Pixel Pipeline State Summary ........................................................................................................ 361 + 12.2.1 COLOR_CALC_STATE............................................................................................................ 361 + 12.2.2 DEPTH_STENCIL_STATE....................................................................................................... 362 + 12.2.3 BLEND_STATE ........................................................................................................................ 366 + 12.2.4 CC_VIEWPORT ....................................................................................................................... 373 + 12.3 Other Pixel Pipeline Functions ....................................................................................................... 374 + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 5/29/2012 7 + 12.3.1 Statistics Gathering .................................................................................................................. 374 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 5/29/2012 8 + 1. 3D Pipeline +1.1 Introduction +This section covers the programming details for the 3D fixed functions. + + +1.2 3D Pipeline Overview + +1.2.1 3D Pipeline Stages +The following table lists the various stages of the 3D pipeline and describes their major functions. + Pipeline Stage Functions Performed +Command Stream (CS) + The Command Stream stage is responsible for managing the 3D pipeline + and passing commands down the pipeline. In addition, the CS unit reads + “constant data” from memory buffers and places it in the URB. + Note that the CS stage is shared between the 3D and Media pipelines. +Vertex Fetch (VF) The Vertex Fetch stage, in response to 3D Primitive Processing + commands, is responsible for reading vertex data from memory, + reformatting it, and writing the results into Vertex URB Entries. It then + outputs primitives by passing references to the VUEs down the pipeline. +Vertex Shader (VS) The Vertex Shader stage is responsible for processing (shading) incoming + vertices by passing them to VS threads. +Hull Shader (HS) + The Hull Shader is responsible for processing (shading) incoming patch + primitives as part of the tessellation process. + +Tesselation Engine (TE) + The Tessellation Engine is responsible for using tessellation factors + (computed in the HS stage) to tessellate U,V parametric domains into + domain point topologies. +Domain Shader (DS) + The Domain Shader stage is responsible for processing (shading) the + domain points (generated by the TE stage) into corresponding vertices. +Geometry Shader (GS) The Geometry Shader stage is responsible for processing incoming + objects by passing each object’s vertices to a GS thread. +Stream Output Logic (SOL) + The Stream Output Logic is responsible for outputting incoming object + vertices into Stream Out Buffers in memory. +Clipper (CLIP) + The Clipper stage performs Clip Tests on incoming objects and clips + objects if required. + Objects are clipped using fixed-function hardware. +Strip/Fan (SF) + The Strip/Fan stage performs object setup. + Object setup uses fixed-function hardware. +Windower/Masker (WM) The Windower/Masker performs object rasterization and spawns WM + thread (aka PS thread) to process (shade) the object pixels. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 9 + 1.3 3D Primitives Overview +The 3DPRIMITIVE command (defined in the VF Stage chapter) is used to submit 3D primitives to be +processed by the 3D pipeline. Typically the processing results in the rendering of pixel data into the +render targets, but this is not required. +Terminology Note: There is considerable confusion surrounding the term ‘primitive’, e.g., is a triangle strip +a ‘primitive’, or is a triangle within a triangle strip a ‘primitive’? In this spec, we will try to avoid ambiguity +by using the term ‘object’ to represent the basic shapes (point, line, triangle), and ‘topology’ to represent +input geometry (strips, lists, etc.). Unfortunately, terms like ‘3DPRIMITIVE’ must remain for legacy +reasons. +The following table describes the basic primitive topology types supported in the 3D pipeline. +Notes: + +  There are several variants of the basic topologies. These have been introduced to allow slight + variations in behavior without requiring a state change. +  Number of vertices: + o Dangling Vertices: Topologies have an “expected” number of vertices in order to + form complete objects within the topologies (e.g., LINELIST is expected to have an + even number of vertices). The actual number of vertices specified in the + 3DPRIMITIVE command, and as output from the GS unit, is allowed to deviate from + this expected number --- in which case any “dangling” vertices are discarded. The + removal of dangling vertices is initially performed in the VF unit. In order to filter out + dangling vertices emitted by GS threads, the CLIP unit also performs dangling-vertex + removal at its input. + +3D Primitive Topology Types + 3D Primitive Topology Type + (ordered alphabetically) Description +LINELIST + A list of independent line objects (2 vertices per line). + Programming Restrictions: + Normal usage expects a multiple of 2 vertices, though incomplete + objects are silently ignored. +LINELIST_ADJ + A list of independent line objects with adjacency information (4 + vertices per line). + Programming Restrictions: + Normal usage expects a multiple of 4 vertices, though incomplete + objects are silently ignored. + Not valid as output from GS thread. +LINELOOP + Similar to a 3DPRIM_LINESTRIP, though the last vertex is + connected back to the initial vertex via a line object. The + LINELOOP topology is converted to LINESTRIP topology at the + beginning of the 3D pipeline. + Programming Restrictions: + Normal usage expects at least 2 vertices, though incomplete objects + are silently ignored. (The 2-vertex case is required by OGL). + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 10 + 3D Primitive Topology Type + (ordered alphabetically) Description + Not valid after the GS stage (i.e., must be converted by a GS thread + to some other primitive type). + +LINESTRIP + A list of vertices connected such that, after the first vertex, each + additional vertex is associated with the previous vertex to define a + connected line object. + Programming Restrictions: + Normal usage expects at least 2 vertices, though incomplete objects + are silently ignored. +LINESTRIP_ADJ + A list of vertices connected such that, after the first vertex, each + additional vertex is associated with the previous vertex to define + connected line object. The first and last segments are adjacent–only + vertices. + Programming Restrictions: + Normal usage expects at least 4 vertices, though incomplete objects + are silently ignored. + Not valid as output from GS thread. +LINESTRIP_BF + Similar to LINESTRIP, except treated as “backfacing’ during + rasterization (stencil test). + This can be used to support “line” polygon fill mode when two-sided + stencil is enabled. +LINESTRIP_CONT + Similar to LINESTRIP, except LineStipple (if enabled) is continued + (vs. reset) at the start of the primitive topology. + This can be used to support line stipple when the API-provided + primitive is split across multiple tolopologies. + +LINESTRIP_CONT_BF Combination of LINESTRIP_BF and LINESTRIP_CONT variations. +POINTLIST A list of point objects (1 vertex per point). +POINTLIST_BF + Similar to POINTLIST, except treated as “backfacing’ during + rasterization (stencil test). + This can be used to support “point” polygon fill mode when two- + sided stencil is enabled. +POLYGON + Similar to TRIFAN, though the first vertex always provides the “flat- + shaded” values (vs. this being programmable through state). + Programming Restrictions: + Normal usage expects at least 3 vertices, though incomplete objects + are silently ignored. +QUADLIST + A list of independent quad objects (4 vertices per quad). The + QUADLIST topology is converted to POLYGON topology at the + beginning of the 3D pipeline. + Programming Restrictions: + Normal usage expects a multiple of 4 vertices, though incomplete + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 11 + 3D Primitive Topology Type + (ordered alphabetically) Description + objects are silently ignored. + +QUADSTRIP + A list of vertices connected such that, after the first two vertices, + each additional pair of vertices are associated with the previous two + vertices to define a connected quad object. + Programming Restrictions: + Normal usage expects an even number (4 or greater) of vertices, + though incomplete objects are silently ignored. + : To work around IVB bug #3665983 the driver must detect the use + of a QUADSTRIP input topology along with the use of primitive ID in + the pixel shader, and correspondingly shift right by 1the primitive ID + in the pixel shader. +RECTLIST + A list of independent rectangles, where only 3 vertices are provided + per rectangle object, with the fourth vertex implied by the definition + of a rectangle. V0=LowerRight, V1=LowerLeft, V2=UpperLeft. + Implied V3 = V0-V1+V2. + Programming Restrictions: + Normal usage expects a multiple of 3 vertices, though incomplete + objects are silently ignored. + The RECTLIST primitive is supported specifically for 2D operations + (e.g., BLTs and “stretch” BLTs) and not as a general 3D primitive. + Due to this, a number of restrictions apply to the use of RECTLIST: + Must utilize “screen space” coordinates (VPOS_SCREENSPACE) + when the primitive reaches the CLIP stage. The W component of + position must be 1.0 for all vertices. The 3 vertices of each object + should specify a screen-aligned rectangle (after the implied vertex is + computed). + Clipping: Must not require clipping or rely on the CLIP unit’s + ClipTest logic to determine if clipping is required. Either the CLIP + unit should be DISABLED, or the CLIP unit’s Clip Mode should be + set to a value other than CLIPMODE_NORMAL. + Viewport Mapping must be DISABLED (as is typical with the use of + screen-space coordinates). +TRIFAN + Triangle objects arranged in a fan (or polygon). The initial vertex is + maintained as a common vertex. After the second vertex, each + additional vertex is associated with the previous vertex and the + common vertex to define a connected triangle object . + Programming Restrictions: + Normal usage expects at least 3 vertices, though incomplete objects + are silently ignored. + +TRIFAN_NOSTIPPLE + Similar to TRIFAN, but poylgon stipple is not applied (even if + enabled). + This can be used to support “point” polygon fill mode, under the + combination of the following conditions: + (a) when the frontfacing and backfacing polygon fill modes are + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 12 + 3D Primitive Topology Type + (ordered alphabetically) Description + different (so the final fill mode is not known to the driver), + (b) one of the fill modes is “point” and the other is “solid”, + (c) point mode is being emulated by converting the point into a + trifan, + (d) polygon stipple is enabled. In this case, polygon stipple should + not be applied to the points-emulated-as-trifans. + +TRILIST + A list of independent triangle objects (3 vertices per triangle). + Programming Restrictions: + Normal usage expects a multiple of 3 vertices, though incomplete + objects are silently ignored. +TRILIST_ADJ + A list of independent triangle objects with adjacency information (6 + vertices per triangle). + Programming Restrictions: + Normal usage expects a multiple of 6 vertices, though incomplete + objects are silently ignored. + Not valid as output from GS thread. +TRISTRIP + A list of vertices connected such that, after the first two vertices, + each additional vertex is associated with the last two vertices to + define a connected triangle object. + Programming Restrictions: + Normal usage expects at least 3 vertices, though incomplete objects + are silently ignored. +TRISTRIP_ADJ + A list of vertices where the even-numbered (including 0th) vertices + are connected such that, after the first two vertex pairs, each + additional even-numbered vertex is associated with the last two + even-numbered vertices to define a connected triangle object. The + odd-numbered vertices are adjacent-only vertices. + Programming Restrictions: + Normal usage expects at least 6 vertices, though incomplete objects + are silently ignored. + Not valid as output from GS thread. + +TRISTRIP_REVERSE Similar to TRISTRIP, though the sense of orientation (winding order) + is reversed – this allows SW to break long tristrips into smaller pieces + and still maintain correct face orientations. +PATCHLIST_n List of n-vertex “patch” objects. These topologies cannot be + rendered directly – the tessellation units must be utilized to convert + them into points, lines or triangles in order to produce rasterization + results. (VS, GS and StreamOutput operations can also be + performed). + +The following diagrams illustrate the basic 3D primitive topologies. (Variants are not shown if they have +the same definition with respect to the information provided in the diagrams). + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 13 + A note on the arrows you see below: These arrows are intended to show the vertex ordering of triangles +that are to be considered having “clockwise” winding order in screen space. Effectively, the arrows show +the order in which vertices are used in the cross-product (area, determinant) computation. Note that for +TRISTRIP, this requires that either the order of odd-numbered triangles be reversed in the cross-product +or the sign of the result of the normally-ordered cross-product be flipped (these are identical operations). + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 14 + Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 15 + 1.4 3D Pipeline State Overview + +1.4.1 3D State Model +The locations of the sampler state and viewport state pointers have been moved from the state +descriptors to the ring buffer as compared to In addition, the state for the fixed function pipeline has +been moved from indirect state descriptors to inline commands. The color calculator state has been +repartitioned. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 16 + Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 17 + 1.4.2 3DSTATE_CC_STATE_POINTERS + + 3DSTATE_CC_STATE_POINTERS + +Length Bias: 2 +The 3DSTATE_CC_STATE_POINTERS command is used to set up the pointers to the color calculator state. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 0Eh 3DSTATE_CC_STATE_POINTERS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n +1 31:6 Pointer to COLOR_CALC_STATE + Project: All + Format: DynamicStateOffset[31:6]COLOR_CALC_STATE + Specifies the 64-byte aligned offset of the COLOR_CALC_STATE. This offset is relative to the + Dynamic State Base Address. + + 5:1 Reserved + Project: All + Format: MBZ + 0 Reserved + + Format: MB0 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 18 + 1.4.3 3DSTATE_BLEND_STATE_POINTERS + + 3DSTATE_BLEND_STATE_POINTERS + +Length Bias: 2 +The 3DSTATE_BLEND_STATE_POINTERS command is used to set up the pointers to the color calculator state. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 24h 3DSTATE_BLEND_STATE_POINTERS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n +1 31:6 Pointer to BLEND_STATE + Project: All + Format: DynamicStateOffset[31:6]BLEND_STATE*8 + Specifies the 64-byte aligned offset of the BLEND_STATE. This offset is relative to the Dynamic State + Base Address. + + 5:1 Reserved + Project: All + Format: MBZ + 0 Reserved + + Format: MB0 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 19 + 1.4.4 3DSTATE_DEPTH_STENCIL_STATE_POINTERS + + 3DSTATE_DEPTH_STENCIL_STATE_POINTERS + +Length Bias: 2 +Set up the pointer to the Depth Stencil state. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 25h 3DSTATE_DEPTH_STENCIL_STATE_POINTERS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n +1 31:6 Pointer to DEPTH_STENCIL_STATE + Project: All + Format: DynamicStateOffset[31:6]DEPTH_STENCIL_STATE + Specifies the 64-byte aligned offset of the DEPTH_STENCIL_STATE. This offset is relative to the + Dynamic State Base Address. + + 5:1 Reserved + Project: All + Format: MBZ + 0 Reserved + + Format: MB0 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 20 + 1.4.5 3DSTATE_BINDING_TABLE_POINTERS + +1.4.5.1 3DSTATE_BINDING_TABLE_POINTERS_VS + + 3DSTATE_BINDING_TABLE_POINTERS_VS + +Length Bias: 2 +The 3DSTATE_BINDING_TABLE_POINTERS_VS command is used to define the location of fixed functions’ +BINDING_TABLE_STATE. Only some of the fixed functions utilize binding tables. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 26h 3DSTATE_BINDING_TABLE_POINTERS_VS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n +1 31:16 Reserved + Project: All + Format: MBZ + 15:5 Pointer to VS Binding Table + + Format: SurfaceStateOffset[15:5]BINDING_TABLE_STATE*256 + Specifies the 32-byte aligned address offset of the VS function’s BINDING_TABLE_STATE. This + offset is relative to the Surface State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 21 + 1.4.5.2 3DSTATE_BINDING_TABLE_POINTERS_HS + + 3DSTATE_BINDING_TABLE_POINTERS_HS + +Length Bias: 2 +The 3DSTATE_BINDING_TABLE_POINTERS_HS command is used to define the location of fixed functions’ +BINDING_TABLE_STATE. Only some of the fixed functions utilize binding tables. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 27h 3DSTATE_BINDING_TABLE_POINTERS_HS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n +1 31:16 Reserved + Project: All + Format: MBZ + 15:5 Pointer to HS Binding Table + + Format: SurfaceStateOffset[15:5]BINDING_TABLE_STATE*256 + + Specifies the 32-byte aligned address offset of the HS function’s BINDING_TABLE_STATE. This + offset is relative to the Surface State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 22 + 1.4.5.3 3DSTATE_BINDING_TABLE_POINTERS_DS + + 3DSTATE_BINDING_TABLE_POINTERS_DS + +Length Bias: 2 +The 3DSTATE_BINDING_TABLE_POINTERS_DS command is used to define the location of fixed functions’ +BINDING_TABLE_STATE. Only some of the fixed functions utilize binding tables. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 28h 3DSTATE_BINDING_TABLE_POINTERS_DS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n +1 31:16 Reserved + Project: All + Format: MBZ + 15:5 Pointer to DS Binding Table + + Format: SurfaceStateOffset[15:5]BINDING_TABLE_STATE*256 + + Specifies the 32-byte aligned address offset of the DS function’s BINDING_TABLE_STATE. This + offset is relative to the Surface State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 23 + 1.4.5.4 3DSTATE_BINDING_TABLE_POINTERS_GS + + 3DSTATE_BINDING_TABLE_POINTERS_GS + +Length Bias: 2 +The 3DSTATE_BINDING_TABLE_POINTERS_GS command is used to define the location of fixed functions’ +BINDING_TABLE_STATE. Only some of the fixed functions utilize binding tables. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 29h 3DSTATE_BINDING_TABLE_POINTERS_GS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n +1 31:16 Reserved + Project: All + Format: MBZ + 15:5 Pointer to GS Binding Table + + Format: SurfaceStateOffset[15:5]BINDING_TABLE_STATE*256 + + Specifies the 32-byte aligned address offset of the GS function’s BINDING_TABLE_STATE. This + offset is relative to the Surface State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 24 + 1.4.5.5 3DSTATE_BINDING_TABLE_POINTERS_PS + + 3DSTATE_BINDING_TABLE_POINTERS_PS + +Length Bias: 2 +The 3DSTATE_BINDING_TABLE_POINTERS_PS command is used to define the location of fixed functions’ +BINDING_TABLE_STATE. Only some of the fixed functions utilize binding tables. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 2Ah 3DSTATE_BINDING_TABLE_POINTERS_PS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n +1 31:16 Reserved + Project: All + Format: MBZ + 15:5 Pointer to PS Binding Table + + Format: SurfaceStateOffset[15:5]BINDING_TABLE_STATE*256 + Specifies the 32-byte aligned address offset of the PS function’s BINDING_TABLE_STATE. This + offset is relative to the Surface State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 25 + 1.5 3DSTATE_SAMPLER_STATE_POINTERS + +1.5.1 1.5.1 3DSTATE_SAMPLER_STATE_POINTERS_VS + + 3DSTATE_SAMPLER_STATE_POINTERS_VS + +Length Bias: 2 +The 3DSTATE_SAMPLER_STATE_POINTERS_VS command is used to define the location of VS +SAMPLER_STATE table. Only some of the fixed functions utilize sampler state tables. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 2Bh 3DSTATE_SAMPLER_STATE_POINTERS_VS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Format: =n +1 31:5 Pointer to VS Sampler State + Project: All + Format: DynamicStateOffset[31:5]SAMPLER_STATE*16 + Specifies the 32-byte aligned address offset of the VS function’s SAMPLER_STATE table. This offset + is relative to the Dynamic State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 26 + 1.5.2 3DSTATE_SAMPLER_STATE_POINTERS_HS + + 3DSTATE_SAMPLER_STATE_POINTERS_HS + +Length Bias: 2 +The 3DSTATE_SAMPLER_STATE_POINTERS_HS command is used to define the location of HS +SAMPLER_STATE table. Only some of the fixed functions utilize sampler state tables. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 2Ch 3DSTATE_SAMPLER_STATE_POINTERS_HS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Format: =n +1 31:5 Pointer to HS Sampler State + Project: All + Format: DynamicStateOffset[31:5]SAMPLER_STATE*16 + Specifies the 32-byte aligned address offset of the HS function’s SAMPLER_STATE table. This offset + is relative to the Dynamic State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 27 + 1.5.3 3DSTATE_SAMPLER_STATE_POINTERS_DS + + 3DSTATE_SAMPLER_STATE_POINTERS_DS + +Length Bias: 2 +The 3DSTATE_SAMPLER_STATE_POINTERS_DS command is used to define the location of DS +SAMPLER_STATE table. Only some of the fixed functions utilize sampler state tables. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 2Dh 3DSTATE_SAMPLER_STATE_POINTERS_DS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Format: =n +1 31:5 Pointer to DS Sampler State + Project: All + Format: DynamicStateOffset[31:5]SAMPLER_STATE*16 + Specifies the 32-byte aligned address offset of the DS function’s SAMPLER_STATE table. This offset + is relative to the Dynamic State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 28 + 1.5.4 3DSTATE_SAMPLER_STATE_POINTERS_GS + + 3DSTATE_SAMPLER_STATE_POINTERS_GS + +Length Bias: 2 +The 3DSTATE_SAMPLER_STATE_POINTERS_GS command is used to define the location of GS +SAMPLER_STATE table. Only some of the fixed functions utilize sampler state tables. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 2Eh 3DSTATE_SAMPLER_STATE_POINTERS_GS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Format: =n +1 31:5 Pointer to GS Sampler State + Project: All + Format: DynamicStateOffset[31:5]SAMPLER_STATE*16 + Specifies the 32-byte aligned address offset of the GS function’s SAMPLER_STATE table. This offset + is relative to the Dynamic State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 29 + 1.5.5 3DSTATE_SAMPLER_STATE_POINTERS_PS + + 3DSTATE_SAMPLER_STATE_POINTERS_PS + +Length Bias: 2 +The 3DSTATE_SAMPLER_STATE_POINTERS_PS command is used to define the location of PS +SAMPLER_STATE table. Only some of the fixed functions utilize sampler state tables. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 2Fh 3DSTATE_SAMPLER_STATE_POINTERS_PS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Format: =n +1 31:5 Pointer to PS Sampler State + Project: All + Format: DynamicStateOffset[31:5]SAMPLER_STATE*16 + Specifies the 32-byte aligned address offset of the PS function’s SAMPLER_STATE table. This offset + is relative to the Dynamic State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 30 + 1.6 3DSTATE_VIEWPORT_STATE_POINTERS + +1.6.1 3DSTATE_VIEWPORT_STATE_POINTERS_CC + + 3DSTATE_VIEWPORT_STATE_POINTERS_CC + +Length Bias: 2 +The 3DSTATE_VIEWPORT_STATE_POINTERS_CC command is used to define the location of fixed functions’ +viewport state table. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 23h 3DSTATE_VIEWPORT_STATE_POINTERS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Format: =n +1 31:5 Pointer to CC_VIEWPORT + Project: All + Format: DynamicStateOffset[31:5]CC_VIEWPORT*16 + Specifies the 32-byte aligned address offset of the CC_VIEWPORT state. This offset is relative to the + Dynamic State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 31 + 1.6.2 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP + + 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP + +Length Bias: 2 +The 3DSTATE_VIEWPORT_STATE_POINTERS_CLIP command is used to define the location of fixed functions’ +viewport state table. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 21h 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Format: =n +1 31:6 Pointer to SF_CLIP_VIEWPORT + Project: All + Format: DynamicStateOffset[31:6]SF_CLIP_VIEWPORT*16 + Specifies the 64-byte aligned address offset of the SF_CLIP_VIEWPORT state. This offset is relative to + the Dynamic State Base Address. + + 5:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 32 + 1.6.3 3DSTATE_SCISSOR_STATE_POINTERS + + 3DSTATE_SCISSOR_STATE_POINTERS + +Length Bias: 2 +The 3DSTATE_SCISSOR_STATE_POINTERS command is used to define the location of the indirect +SCISSOR_RECT state. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 0Fh 3DSTATE_SCISSOR_STATE_POINTERS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Format: =n +1 31:5 Pointer to SCISSOR_RECT + Project: All + Format: DynamicStateOffset[31:5]SCISSOR_RECT*16 + Specifies the 32-byte aligned address offset of the SCISSOR_RECT state. This offset is relative to the + Dynamic State Base Address. + + 4:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 33 + 1.7 3DSTATE_URB Commands + +1.7.1 3DSTATE_URB_VS + + 3DSTATE_URB_VS + +Length Bias: 2 + Description Project +VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may cause performance to decrease due to +banking in the URB. Element sizes of 16 to 20 should be programmed with six 512-bit URB rows. +This command may not overlap with the push constants in the URB defined by the +3DSTATE_PUSH_CONSTANT_ALLOC_VS, 3DSTATE_PUSH_CONSTANT_ALLOC_DS, +3DSTATE_PUSH_CONSTANT_ALLOC_HS, and 3DSTATE_PUSH_CONSTANT_ALLOC_GS commands. + Programming Notes +3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be programmed in order for the +programming of this state to be valid. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 30h 3DSTATE_URB_VS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n +1 31 Reserved + + Format: MBZ + 30 Reserved + + Format: MBZ + 29:25 VS URB Starting Address + + Format: U5 + Offset from the start of the URB memory where VS starts its allocation, specified in multiples of 8 KB. + Value Name Project + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 34 + 3DSTATE_URB_VS + [0,31] + [0,15] + 24:16 VS URB Entry Allocation Size + Project: All + Format: U9-1 count of 512-bit units + + + Specifies the length of each URB entry owned by VS. This field is always used (even if VS Function + Enable is DISABLED). + Programming Notes + Programming Restriction: As the VS URB entry serves as both the per-vertex input and output of the + VS shader, the VS URB Allocation Size must be sized to the maximum of the vertex input and output + structures. + 15:0 VS Number of URB Entries + Project: All + Format: U16 + Specifies the number of URB entries that are used by VS. This field is always used (even if VS + Function Enable is DISABLED). + Value Name Project + [32,704] + [32,512] + + + Programming Notes + Programming Restriction: VS Number of URB Entries must be divisible by 8 if the VS URB Entry + Allocation Size is less than 9 512-bit URB entries.“2:0” = reserved “000b” + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 35 + 1.7.2 3DSTATE_URB_HS + + 3DSTATE_URB_HS + +Length Bias: 2 +This command may not overlap with the push constants in the URB defined by the +3DSTATE_PUSH_CONSTANT_ALLOC_VS, 3DSTATE_PUSH_CONSTANT_ALLOC_DS, +3DSTATE_PUSH_CONSTANT_ALLOC_HS, and 3DSTATE_PUSH_CONSTANT_ALLOC_GS commands. + Programming Notes +3DSTATE_URB_VS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be programmed in order for the +programming of this state to be valid. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 31h 3DSTATE_URB_HS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n +1 31 Reserved + + Format: MBZ + 30 Reserved + + Format: MBZ + 29:25 HS URB Starting Address + + Format: U5 + Offset from the start of the URB memory where HS starts its allocation, specified in multiples of 8 KB. + Value Name Project + [0,31] + [0,15] + 24:16 HS URB Entry Allocation Size + Project: All + Format: U9-1 Count of 512-bit units + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 36 + 3DSTATE_URB_HS + + Specifies the length of each URB entry owned by HS. This field is always used (even if HS Function + Enable is DISABLED). + + 15:0 HS Number of URB Entries + Project: All + + Specifies the number of URB entries that are used by HS. This field is always used (even if HS + Function Enable is DISABLED). + + Programming Restriction:HS Number of URB Entries must be divisible by 8 if the HS URB Entry + Allocation Size is less than 9 512-bit URB entries.“2:0” = reserved “000” + Value Name Project + [0,64] + [0,32] + + + + +1.7.3 3DSTATE_URB_DS + + 3DSTATE_URB_DS + +Length Bias: 2 +This command may not overlap with the push constants in the URB defined by the +3DSTATE_PUSH_CONSTANT_ALLOC_VS, 3DSTATE_PUSH_CONSTANT_ALLOC_DS, +3DSTATE_PUSH_CONSTANT_ALLOC_HS, and 3DSTATE_PUSH_CONSTANT_ALLOC_GS commands. + Programming Notes +3DSTATE_URB_VS, 3DSTATE_URB_HS, and 3DSTATE_URB_GS must also be programmed in order for the +programming of this state to be valid. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 32h 3DSTATE_URB_DS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 37 + 3DSTATE_URB_DS + Format: =n +1 31 Reserved + + Format: MBZ + 30 Reserved + + Format: MBZ + 29:25 DS URB Starting Address + + Format: U5 + Offset from the start of the URB memory where DS starts its allocation, specified in multiples of 8 KB. + Value Name Project + [0,31] + [0,15] + 24:16 DS URB Entry Allocation Size + Project: All + Format: U9-1 Count of 512-bit units + + + Specifies the length of each URB entry owned by DS. This field is always used (even if DS Function + Enable is DISABLED). + Value Name + [0,9] + 15:0 DS Number of URB Entries + Project: All + + + Description Project + Specifies the number of URB entries that are used by DS. This field is always used (even if DS + Function Enable is DISABLED). + If Domain Shader Thread Dispatch is Enabled then the minimum number handles that must be + allocated is 138 URB entries. + "2:0" = reserved "000" + + + Value Name Project + [0,448] + [0,288] + + + Programming Notes + DS Number of URB Entries must be divisible by 8 if the DS URB Entry Allocation Size is less than 9 + 512-bit URB entries.If Domain Shader Thread Dispatch is Enabled then the minimum number of + handles that must be allocated is 10 URB entries. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 38 + 1.7.4 3DSTATE_URB_GS + + 3DSTATE_URB_GS + +Length Bias: 2 +This command may not overlap with the push constants in the URB defined by the +3DSTATE_PUSH_CONSTANT_ALLOC_VS, 3DSTATE_PUSH_CONSTANT_ALLOC_DS, +3DSTATE_PUSH_CONSTANT_ALLOC_HS, and 3DSTATE_PUSH_CONSTANT_ALLOC_GS commands. + Programming Notes +3DSTATE_URB_VS, 3DSTATE_URB_HS, and 3DSTATE_URB_DS must also be programmed in order for the +programming of this state to be valid. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 33h 3DSTATE_URB_GS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n +1 31 Reserved + + Format: MBZ + 30 Reserved + + Format: MBZ + 29:25 GS URB Starting Address + + Format: U5 + Offset from the start of the URB memory where GS starts its allocation, specified in multiples of 8 + KB. + Value Name Project + [0,31] + [0,15] + 24:16 GS URB Entry Allocation Size + Project: All + Format: U9-1 512-bit units + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 39 + 3DSTATE_URB_GS + + + Specifies the length of each URB entry owned by GS. This field is always used (even if GS + Function Enable is DISABLED). + + 15:0 GS Number of URB Entries + Project: All + + Specifies the number of URB entries that are used by GS. This field is always used (even if GS + Function Enable is DISABLED). + + Programming Restriction: + GS Number of URB Entries must be divisible by 8 if the GS URB Entry Allocation Size is less than + 9 512-bit URB entries. + + “2:0” = reserved “000” + Value Name Project + [0,320] + [0,192] + + + + +1.7.5 Gather Constants +In Dx10 the app can provide up to 16 constant buffers. The compiler does some optimizations of constant +usage and determines which elements of which constants should be packed in which push constant +register for optimum shader performance. While this gathering and packing of constant elements into +push constant registers optimizes the shader, it cause the driver additional work at draw call time, since +the driver must do the gather and packing at draw time. A new cmd 3D_STATE_GATHER_CONSTANT_* +is added to offload the gather and packing functions from the driver. There are 5 FF which support push +constants (VS, GS, DS, HS, PS) and they all have corresponding gather cmds. The compiler generates a +gather table which instructs what elements of what buffers should be pack into the gather buffer. The +gather table indexes the BT to get the surface state which points to the constant buffer. The resource +streamer fills gather buffer when it executes a 3D_STATE_GATHER_CONSTANT_* cmd. Once the +gather buffer has been filled, the Cmd streamer will execute the 3D_STATE_CONSTANT_* to load the +push constant into the URB. +Note: The gather push constants can only be used if the HW generated binding tables are also used. + + +1.7.6 Dx9 Constant Buffer Generation +The Dx9 constant model is a set of register that the App can incrementally update. The HW requires a +constant buffer which lives until the last shader using that buffer retires. To offload the driver the +3DSTATE_DX9_CONSTANT*_* cmds are added. These commands allow the on-die constant register to +be maintained. When all the edits to the constant register have been completed, the +3DSTATE_DX9_GENERATE_ACTIVE_* cmd is used to write out a constant buffer to the Dx9 Constant +buffer pool. The Dx9 constant buffers are fixed 8KB in size, w/ a large portion of the 2 nd 4KB unused. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 40 + 1.8 Vertex Data Overview +The 3D pipeline FF stages (past VF) receive input 3D primitives as a stream of vertex information +packets. (These packets are not directly visible to software). Much of the data associated with a vertex is +passed indirectly via a VUE handle. The information provided in vertex packets includes: + +  The URB Handle of the VUE: This is used by the FF unit to refer to the VUE and perform any + required operations on it (e.g., cause it to be read into the thread payload, dereference it, etc.). +  Primitive Topology Information: This information is used to identify/delineate primitive topologies + in the 3D pipeline. Initially, the VF unit supplies this information, which then passes through the VS + stage unchanged. GS and CLIP threads must supply this information with each vertex they produce + (via the URB_WRITE message). If a FF unit directly outputs vertices (that were not generated by a + thread they spawned), that FF unit is responsible for providing this information. + o PrimType: The type of topology, as defined by the corresponding field of the + 3DPRIMITIVE command. + o StartPrim: TRUE only for the first vertex of a topology. + o EndPrim: TRUE only for the last vertex of a topology. + o The FF unit which owns the VUE + o Sequence numbers which uniquely identify (with some limits) the VUE output by the + owning FF unit. (This data can be used to trap on a specific vertex) + +  (Possibly, depending on FF unit) Data read back from the Vertex Header of the VUE. + + +1.8.1 Vertex URB Entry (VUE) Formats +In general, vertex data is stored in Vertex URB Entries (VUEs) in the URB, processed by CLIP threads, +and only referenced by the pipeline stages indirectly via VUE handles. Therefore (for the most part) the +contents/format of the vertex data is not exposed to 3D pipeline hardware – the FF units are typically only +aware of the handles and sizes of VUEs. +VUEs are written in two ways: + +  At the top of the 3D Geometry pipeline, the VF’s InputAssembly function creates VUEs and initializes + them from data extracted from Vertex Buffers as well as internally-generated data. +  VS, GS, and CLIP threads can compute, format and write new VUEs as thread output. + +There are only two points in the 3D FF pipeline where the FF units are exposed to the VUE data. +Otherwise the VUE remains opaque to the 3D pipeline hardware. + +  Just prior to the CLIP stage, all VUEs are read-back: + o : Optional readback of ClipDistance values (up to 8 floats in an aligned 256-bit URB + row) + +  Just after the CLIP stage, on clip-generated VUEs are read-back: + o Readback of the Vertex Header (first 256 bits of the VUE) + +Software must ensure that any VUEs subject to readback by the 3D pipeline start with a valid Vertex +Header. This extends to all VUEs with the following exceptions listed below: + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 41 +  If the VS function is enabled, the VF-written VUEs are not required to have Vertex Headers, as the + VS-incoming vertices are guaranteed to be consumed by the VS (i.e., the VS thread is responsible + for overwriting the input vertex data). +  If the GS FF is enabled, neither VF-written VUEs nor VS thread-generated VUEs are required to + have Vertex Headers, as the GS will consume all incoming vertices. +  (There is a pathological case where the CLIP state can be programmed to guarantee that all CLIP- + incoming vertices are consumed – regardless of the data read back prior to the CLIP stage – and + therefore only the CLIP thread-generated vertices would require Vertex Headers). + +The following table defines the Vertex Header. The Position fields are described in further detail below. + +VUE Vertex Header () +DWord Bit Description +D0 31:0 Reserved: MBZ +D1 31:0 + Render Target Array Index (RTAIndex). This value is (eventually) used to index into a specific element + of an “array” Render Target. It is read back by the GS unit (for all exiting vertices) and the Clip unit (for + all clip-generated vertices), subsequently routed into the PS thread payload, and eventually included in + the RTWrite DataPort message header for use by the DataPort shared function. + Software is responsible for ensuring this field is zero whenever a programmable index value is not + required. When a programmable index value is required (e.g. ) software must ensure that the correct + 11-bit value is written to this field. Specifically, the kernels must perform a reange check of computed + index values against [0,2047], and output zero if that range is exceeded. Note that the unmodified + “renderTargetArrayIndex” must be maintained in the VUE outside of the Vertex Header. + Software can force an RTAIndex of 0 to be used (effectively ignoring the setting of this DWord) by use of + the ForceZeroRTAIndex bit (3DSTATE_CLIP). Otherwise the read-back value will be used to select an + RTArray element, after being clamped to the RTArray surface’s [MinimumArrayElement, Depth] range + (SURFACE_STATE). + Format: 0-based U32 index value +D2 31:0 + Viewport Index. This value is used to select one of a possible 16 sets of viewport (VP) state + parameters in the Clip unit’s VertexClipTest function and in the SF unit’s ViewportMapping and Scissor + functions. + The GS unit (even if disabled) will read back this value for all vertices exiting the GS stage and entering + the Clip stage. When enabled, the GS unit will range-check the value against [0,Maximum VPIndex] + (see GS_STATE, CLIP_STATE). After this range-check the values are sent down the pipeline and used + in the Clip unit’s VertexClipTest function. For vertices passing through the Clip stage, these values will + also be sent to the SF unit for use in ViewportMapping and Scissor functions. + The Clip unit (if enabled) will read back this value only for vertices generated by CLIP threads. The Clip + unit will perform a range clamp similar to the GS unit. + Software can force a value of 0 to be used by programming Maximum VPIndex to 0. + Format: 0-based U32 index value + +D3 31:0 + Point Width. This field specifies the width of POINT objects in screen-space pixels. It is used only for + vertices within POINTLIST and POINTLIST_BF primitive topologies, and is ignored for vertices + associated with other primitive topologies. + This field is read back by both the GS and Clip units. + Format: FLOAT32 +D4 31:0 + Vertex Position X Coordinate. This field contains the X component of the vertex’s 4D space position. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 42 + DWord Bit Description + Format: FLOAT32 +D5 31:0 + Vertex Position Y Coordinate. This field contains the Y component of the vertex’s 4D space position + Format: FLOAT32 + +D6 31:0 + Vertex Position Z Coordinate. This field contains the Z component of the vertex’s NDC space position + Format: FLOAT32 +D7 31:0 + Vertex Position W Coordinate. This field contains the Z component of the vertex’s 4D space position + Format: FLOAT32 +D8 31:0 + ClipDistance 0 Value (optional). If the UserClipDistance Clip Test Enable Bitmask bit + (3DSTATE_CLIP) is set, this value will be read from the URB in the Clip stage. If the value is found to + be less than 0 or a NaN, the vertex’s UCF<0> bit will set in the Clip unit’s VertexClipTest function. + If the UserClipDistance Clip Test Enable Bitmask bit is clear, this value will not be read back, and the + vertex’s UCF<0> bit will be zero by definition. + Format: FLOAT32 +D9 31:0 + ClipDistance 1 Value (optional). See above + +D10 31:0 + ClipDistance 2 Value (optional). See above + +D11 31:0 + ClipDistance 3 Value (optional). See above + +D12 31:0 + ClipDistance 4 Value (optional). See above + +D13 31:0 + ClipDistance 5 Value (optional). See above + +D14 31:0 + ClipDistance 6 Value (optional). See above + +D15 31:0 + ClipDistance 7 Value (optional). See above + + 31:0 + (Remainder of Vertex Elements). + The absolute maximum size limit on this data is specified via a maximum limit on the amount of data + that can be read from a VUE (including the Vertex Header) (Vertex Entry URB Read Length has a + maximum value of 63 256-bit units). Therefore the Remainder of Vertex Elements has an absolute + maximum size of 62 256-bit units. Of course the actual allocated size of the VUE can and will limit the + amount of data in a VUE. + + + +1.8.2 Vertex Positions + (For the sake of brevity, the following discussion will use the term map as a shorthand for “compute +screen space coordinate via perspective divide followed by viewport transform”.) +The “Position” fields of the Vertex Header are the only vertex position coordinates exposed to the 3D +Pipeline. The CLIP and SF units are the only FF units which perform operations using these positions. +The VUE will likely contain other position attributes for the vertex outside of the Vertex Header, though +this information is not directly exposed to the FF units. For example, the Clip Space position will likely be + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 43 + required in the VUE (outside of the Vertex Header) in order to perform correct and robust 3D Clipping in +the CLIP thread. +In the CLIP unit, the read-back Position fields are interpreted as being in one of two coordinate systems, +depending on the CLIP_STATE.VertexPositionSpace bit. The CLIP unit will modify its VertexClipTest +function depending on the coordinate space of the incoming vertices. + +  VPOS_CLIPSPACE (Homogeneous 4D Clip-space coordinates, pre-perspective division): The + Clip Space position is defined in a homogeneous 4D coordinate space (pre-perspective divide), + where the visible “view volume” is defined by the APIs. The API’s VS or GS shader program will + include geometric transforms in the computation of this clip space position such that the resulting + coordinate is positioned properly in relation to the view volume (i.e., it will include a “view transform” + in this computation path). When this coordinate system is selected, the 3D FF pipeline will perform a + perspective projection (division of x,y,z by w), perform clip-test on the resulting NDC (Normalized + Device Coordinates), and eventually perform viewport mapping (in the SF unit) to yield screen-space + (pixel) coordinates. +  VPOS_SCREENSPACE (Screen Space position): Under certain circumstances, the position in the + Vertex Header will contain the screen-space (pixel) coordinates (post viewport mapping). + +The SF unit does not have a state bit defining the coordinate space of the incoming vertex positions. +Software must use the Viewport Mapping function of the SF unit in order to ensure that screen-space +coordinates are available after that function. If screen space coordinates are passed into SF, then +software will likely turn off the Viewport Mapping function. +The following subsections briefly describe the three relevant coordinate spaces. + +1.8.2.1 Clip Space Position +The clip-space position of a vertex is defined in a homogeneous 4D coordinate space where, after +perspective projection (division by W), the visible “view volume” is some canonical (3D) cuboid. Typically +the X/Y extents of this cuboid are [-1,+1], while the Z extents are either [-1,+1] or [0,+1]. The API’s VS or +GS shader program will include geometric transforms in the computation of this clip space position such +that the resulting coordinate is positioned properly in relation to the view volume (i.e., it will include a +“view transform” in this computation path). +Note that, under typical perspective projections, the clip-space W coordinate is equal to the view-space Z +coordinate. +A vertex’s clip-space coordinates must be maintained in the VUE up to 3D clipping, as this clipping is +performed in clip space. + +  In , vertex clip-space positions must be included in the Vertex Header, so that they can be read-back + (prior to Clipping) and then subjected to perspective projection (in hardware) and subsequent use by + the FF pipeline. + +1.8.2.2 NDC Space Position +A perspective divide operation performed on a clip-space position yields a [X,Y,Z,RHW] NDC (Normalized +Device Coordinates) space position. Here “normalized” means that visible geometry is located within the +[-1,+1] or [0,+1] extent view volume cuboid (see clip-space above). + +  The NDC X,Y,Z coordinates are the clip-space X,Y,Z coordinates (respectively) divided by the clip- + space W coordinate (or, more correctly, the clip-space X,Y,Z coordinates are multiplied by the + reciprocal of the clip space W coordinate). + o Note that the X,Y,Z coordinates may contain INFINITY or NaN values (see below). + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 44 +  The NDC RHW coordinate is the reciprocal of the clip-space W coordinate and therefore, under + normal perspective projections, it is the reciprocal of the view-space Z coordinate. Note that NDC + space is really a 3D coordinate space, where this RHW coordinate is retained in order to perform + perspective-correct interpolation, etal. Note that, under typical perspective projections. + o Note that the RHW coordinate make contain an INFINITY or NaN value (see below). + +1.8.2.3 Screen-Space Position +Screen-space coordinates are defined as: + +  X,Y coordinates are in absolute screen space (pixel coordinates, upper left origin). See Vertex X,Y + Clamping and Quantization in the SF section for a discussion of the limitations/restrictions placed on + screenspace X,Y coordinates. +  Z coordinate has been mapped into the range used for DepthTest. + +  RHW coordinate is actually the reciprocal of clip-space W coordinate (typically the reciprocal of the + view-space Z coordinate). + + +1.9 3D Pipeline Stage Overview +The fixed-function (FF) stages of the 3D pipeline share some common functionality, specifically related to +the creation and management of threads. This chapter is intended to describe the behavior and +programming model of these common functions, in an effort to not replicate this information for each +pipeline stage. Stage-specific exceptions to the information provided here will be included in the stage- +specific chapters to follow. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 45 + 1.9.1 Generic 3D FF Unit Block Diagram +The following block diagram, in general, applies to the VS, GS and CLIP stages. + + + + +1.9.2 1Common 3D FF Unit Functions +A major role of the FF stages is in managing the threads that perform the majority of the processing on +the vertex/pixel data. (In general, the amount of non-thread processing performed by the 3DPIPE stages +increases towards the end of the pipeline.) In a generic sense, the key functions included are: + +  Bypass Mode +  URB Entry Management +  Thread Initiation Management +  Thread Request Data Generation + o Thread Control Information Generation + o Thread Payload Header Generation + o Thread Payload Data Generation + +  Thread Output Handling +  URB Entry Readback +  Statistics Gathering + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 46 + The following table lists the various state variables used to control the common FF functions: + State Variable Programmed Via Generic Functions Affected + Bypass Mode + Enable + + Thread Request Data Gen. +Kernel Start Pointer + + Thread Request Data Gen. +GRF Register Block Count + + Thread Request Data Gen. +Single Program Flow + + Thread Request Data Gen. +Thread Priority + + Thread Request Data Gen. +Floating Point Mode + + Thread Request Data Gen. +Exceptions Enable + + Thread Request Data Gen. +Scratch Space Base +Pointer + + Thread Request Data Gen. +Per Thread Scratch Space + + Payload Data Gen. +Constant URB Entry Read +Length + + Payload Data Gen. +Constant URB Entry Read +Offset + + Payload Data Gen. +Vertex URB Entry Read +Length + + Payload Data Gen. +Vertex URB Entry Read +Offset + + Payload Data Gen. +Dispatch GRF Start +Register for URB Data + +Maximum Number of Thread Resource Alloc. +Threads + Scratch Space Mgt. + URB_FENCE_POINTER URB Entry Mgt. + Fence + + URB Entry Mgt. +URB Entry Allocation Size + + URB Entry Mgt. +Number of URB Entries + + Payload Header Gen. +Sampler State Pointer : + 3DSTATE_SAMPLER_STATE_POINTERS + 3DSTATE_BINDING_TABLE_POINTERS This gets routed directly to shared + Binding Table + functions (transparent to software). +Pointer + + Thread Request Data Gen. +Sampler Count + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 47 + State Variable Programmed Via Generic Functions Affected + Thread Request Data Gen. +Binding Table Entry Count + + Statistics Gathering +Statistics Enable + + + +1.9.3 Thread Initiation Management +Those FF stages that can spawn threads must have buffered the input (URB entries) available to supply a +thread, and then ensure that there are sufficient resources (within the domain of the 3D pipeline) to make +the thread request. +Once a FF stage determines a thread request can be submitted, (a) all input data required to initiate the +thread is generated, (b) this information is submitted to the common thread dispatcher, (c) the thread +dispatcher will spawn the thread as soon as an EU with sufficient GRF resources becomes available, and +finally (d) the thread will start execution. With respect to concurrent threads, steps (c) and (d) can proceed +out of order (i.e., a threads are not necessarily dispatched in the order that the thread requests are +submitted to the thread dispatcher). + +1.9.3.1 Thread Input Buffering +Each FF stage varies with regard to thread input requirements, and so this will not be discussed in this +chapter other than the overview information provided in the following table: + + + FF Stage + Thread Input Requirements + N/A (does not spawn threads) +CS + + N/A (does not spawn threads) +VF + + Normally, two vertices are buffered before a VS thread is spawned to shade the pair in parallel. +VS + Under some circumstances (e.g., a flush, state change, etc.) a single vertex will be shaded. + All the vertices associated with an object must be buffered before a GS thread can be initiated to +GS + process the object. + Threads spawned as required by the rasterization algorithm. +WM + + + +1.9.3.2 Thread Resource Allocation +In general, the considerations listed in the preceding section are relevant, with the following exceptions: + +  CLIP, SF: Threads are not spawned. + + +1.9.4 Thread Request Generation +Once a FF unit determines that a thread can be requested, it must gather all the information required to +submit the thread request to the Thread Dispatcher. This information is divided into several categories, +as listed below and subsequently described in detail. + +  Thread Payload Header: This is the first portion of the thread payload passed in the GRF, starting + at GRF R0. This is information passed directly from the FF unit. It precedes the Thread Payload + Input URB Data. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 48 +  Thread Payload Input URB Data: This is the second portion of the thread payload. It is read from + the URB using entry handles supplied by the FF unit. + +1.9.4.1 Thread Control Information +The following table describes the various state variables that a FF unit uses to provide information to the +Thread Dispatcher and which affect the thread execution environment. Note that this information is not +directly passed to the thread in the thread payload (though some fields may be subsequently accessed by +the thread via architectural registers). + +State Variables Included in Thread Control Information +State Variable Usage FFs + All FFs +Kernel Start This field, together with the General State Pointer, specifies the starting location + spawning +Pointer (1st core instruction) of the kernel program run by threads spawned by this FF unit. + threads + It is specified as a 64-byte-granular offset from the General State Pointer. + + Specifies, in 16-register blocks, how many GRF registers are required to run the All FFs +GRF Register + kernel. The Thread Dispatcher will only seek candidate EUs that have a sufficient spawning +Block Count + number of GRF register blocks available. Upon selecting a target EU, the Thread threads + DIspatcher will generate a logical-to-physical GRF mapping and provide this to the + target EU. + All FFs +Single Specifies whether the kernel program has a single program flow (SIMDnxm with m + spawning +Program Flow = 1) or multiple program flows (SIMDnxm with m > 1). See CR0 description in ISA +(SPF) threads + Execution Environment. + + The Thread Dispatcher will give priority to those thread requests with Thread All FFs +Thread + Priority of HIGH_PRIORITY over those marked as LOW_PRIORITY. Within these spawning +Priority + two classes of thread requests, the Thread Dispatcher applies a priority order (e.g., threads + round-robin --- though this algorithm is considered a device implementation- + dependent detail). + All FFs +Floating Point This determines the initial value of the Floating Point Mode bit of the EU’s CR0 + spawning +Mode architectural register that controls floating point behavior in the EU core. (See ISA.) + threads + This bitmask controls the exception handing logic in the EU. (See ISA.) All FFs +Exceptions + spawning +Enable + threads + All stages +Sampler This is a hint which specifies how many indirect SAMPLER_STATE structures + supporting +Count should be prefetched concurrent with thread initiation. It is recommended that + sampling (VS, + software program this field to equal the number of samplers, though there may be + some minor performance impact if this number gets large. GS, WM) + + This value should not exceed the number of samplers accessed by the thread as + there would be no performance advantage. Note that the data prefetch is treated + as any other memory fetch (with respect to page faults, etc.). + + All FFs +Binding Table This is a hint which specifies how many indirect BINDING_TABLE_STATE + spawning +Entry Count structures should be prefetched concurrent with thread initiation. (The notes + threads + included in Sampler Count (above) also apply to this field). + + +1.9.4.2 Thread Payload Generation +FF units are responsible for generating a thread payload – the data pre-loaded into the target EU’s GRF +registers (starting at R0) that serves as the primary direct input to a thread’s kernel. The general format of + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 49 + these payloads follow a similar structure, though the exact payload size/content/layout is unique to each +stage. This subsection describes the common aspects – refer to the specific stage’s chapters for details +on any differences. +The payload data is divided into two main sections: the payload header followed by the payload URB +data. The payload header contains information passed directly from the FF unit, while the payload URB +data is obtained from URB locations specified by the FF unit. +NOTE: The first 256 bits of the thread payload (the initial contents of R0, aka “the R0 header”) is specially +formatted to closely match (and in some cases exactly match) the first 256 bits of thread-generated +messages (i.e., the message header) accepted by shared functions. In fact, the send instruction supports +having a copy of a GR’s contents (such as R0) used as the message header. Software must take this +intention into account (i.e., “don’t muck with R0 unless you know what you’re doing”). This is especially +important given the fact that several fields in the R0 header are considered opaque to SW, where use or +modification of their contents might lead to UNDEFINED results. +The payload header is further (loosely) divided into a leading fixed payload header section and a trailing, +variable-sized extended payload header section. In general the size, content and layout of both payload +header sections are FF-specific, though many of the fixed payload header fields are common amongst +the FF stages. The extended header is used by the FF unit to pass additional information specific to that +FF unit. The extended header is defined to start after the fixed payload header and end at the offset +defined by Dispatch GRF Start Register for URB Data. Software can cause use the Dispatch GRF +Start Register for URB Data field to insert padding into the extended header in order to maintain a fixed +offset for the start of the URB data. + +1.9.4.2.1 Fixed Payload Header +The payload header is used to pass FF pipeline information required as thread input data. This +information is a mixture of SW-provided state information (state table pointers, etc.), primitive information +received by the FF unit from the FF pipeline, and parameters generated/computed by the FF unit. most of +the fields of the fixed header are common between the FF stages. These non-FF-specific fields are +described in Fixed Payload Header. Note that a particular stage’s header may not contain all these fields, +so they are not “common” in the strictest sense. + +Fixed Payload Header Fields (non-FF-specific) + + Fixed Payload Header Field + (non-FF-specific) + Description FFs + Function ID of the FF unit. This value identifies the FF unit within All FFs +FF Unit ID + the subsystem. The FF unit will use this field (when transmitted spawning + in a Message Header to the URB Function) to detect messages threads + emanating from its spawned threads. + All FFs +Snapshot Flag + spawning + threads + All FFs +Thread ID + spawning + threads + All FFs +Scratch Space Pointer This is the starting location of the thread’s allocated scratch + spawning + space, specified as an offset from the General State Base + Address. Note that scratch space is allocated by the FF unit on threads + a per-thread basis, based on the Scratch Space Base Pointer + and Per-Thread Scratch Space Size state variables. FF units + will assign a thread an arbitrarily-positioned region within this + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 50 + Fixed Payload Header Field + (non-FF-specific) + Description FFs + space. The scratch space for multiple (API-visible) entities + (vertices, pixels) will be interleaved within the thread’s scratch + space. + All FFs +Dispatch ID This field identifies this thread within the outstanding threads + spawning + spawned by the FF unit. This field does not uniquely identify the + threads + thread over any significant period of time. + Implementation Note: This field is effectively an “active thread + index”. It is used on a thread’s URB allocation request to + identify which thread’s handle pool is to source the allocation. It + is used upon thread termination to free up the thread’s scratch + space allocation. + + All FFs +Binding Table Pointer This field, together with the Surface State Base Pointer, + spawning + specifies the starting location of the Binding Table used by + threads + threads spawned by the FF unit. It is specified as a 64-byte- + granular offset from the Surface State Base Pointer. + See Shared Functions for a description of a Binding Table. + + All FFs +Sampler State Pointer This field, together with the General State Base Pointer, + spawning + specifies the starting location of the Sampler State Table used + threads which + by threads spawned by the FF unit. It is specified as a 64-byte- + granular offset from the General State Base Pointer. sample (VS, + GS, WM) + See Shared Functions for a description of a Sampler State + Table. + All FFs +Per Thread Scratch Space This field specifies the amount of scratch space allocated to + spawning + each thread spawned by the FF unit. + threads + The driver must allocate enough contiguous scratch space, + starting at the Scratch Space Base Pointer, to ensure that the + Maximum Number of Threads can each get Per-Thread + Scratch Space size without exceeding the driver-allocated + scratch space. + VS,GS,CLIP,SF +Handle ID This ID is assigned by the FF unit and links the thread to a + specific entry within the FF unit. The FF unit will use this + information upon detecting a URB_WRITE message issued by + the thread. + Threads spawned by the GS, CLIP, and SF units are provided + with a single Handle ID / URB Return Handle pair. Threads + spawned by the VS are provided with one or two pairs + (depending on how many vertices are to be processed). + Threads spawned by the WM do not write to URB entries, and + therefore this info is not supplied. + + VS,GS,CLIP,SF +URB Return Handle This is an initial destination URB handle passed to the thread. If + the thread does output URB entries, this identifies the + destination URB entry. + Threads spawned by the GS, CLIP, and SF units are provided + with a single Handle ID / URB Return Handle pair. Threads + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 51 + Fixed Payload Header Field + (non-FF-specific) + Description FFs + spawned by the VS are provided with one or two pairs + (depending on how many vertices are to be processed). + Threads spawned by the WM do not write to URB entries, and + therefore this info is not supplied. + GS, CLIP, SF, +Primitive Topology Type As part of processing an incoming primitive, a FF unit is often + WM + required to spawn a number of threads (e.g., for each individual + triangle in a TRIANGLE_STRIP). This field identifies the type of + primitive which is being processed by the FF unit, and which + has lead to the spawning of the thread. + Kernels written to process different types of objects can use this + value to direct that processing. E.g., when a CLIP kernel is to + provide clipping for all the various primitive types, the kernel + would need to examine the Primitive Topology Type to + distinguish between point, lines, and triangle clipping requests. + NOTE: In general, this field is identical to the Primitive Topology + Type assoociated with the primitive vertices as received by the + FF unit. Refer to the individual FF unit chapters for cases where + the FF unit modifies the value before passing it to the thread. + (E.g., certain units perform toggling of TRIANGLESTRIP and + TRIANGLESTRIP_REV). + + +1.9.4.2.2 Extended Payload Header +The extended header is of variable-size, where inclusion of a field is determined by FF unit state +programming. +In order to permit the use of common kernels (thus reducing the number of kernels required), the +Dispatch GRF Start Register for URB Data state variable is supported in all FF stages. This SV is used +to place the payload URB data at a specific starting GRF register, irrespective of the size of the extended +header. A kernel can therefore reference the payload URB data at fixed GRF locations, while +conditionally referencing extended payload header information. + +1.9.4.2.3 Payload URB Data +In each thread payload, following the payload header, is some amount of URB-sourced data required as +input to the thread. This data is divided into an optional Constant URB Entry (CURBE), following either by +a Primitive URB Entry (WM) or a number of Vertex URB Entries (VS, GS, CLIP, SF). A FF unit only +knows the location of this data in the URB, and is never exposed to the contents. For each URB entry, the +FF unit will supply a sequence of handles, read offsets and read lengths to the subsystem. The +subsystem will read the appropriate 256-bit locations of the URB, optionally perform swizzling (VS only), +and write the results into sequential GRF registers (starting at Dispatch GRF Start Register for URB +Data). + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 52 + State Variables Controlling Payload URB Data + State Variable Usage FFs + FFs +Dispatch GRF This SV identifies the starting GRF register receiving payload URB data. + spawning +Start Register for + Software is responsible for ensuring that URB data does not overwrite the Fixed or threads +URB Data + Extended Header portions of the payload. + + + + +Vertex URB This SV specifies the starting offset within VUEs from which vertex data is to be VS, GS, +Entry Read read and supplied in this stage’s payloads. It is specified as a 256-bit offset into any + t +Offset and all VUEs passed in the payload. + This SV can be used to skip over leading data in VUEs that is not required by the + stage’s threads (e.g., skipping over the Vertex Header data at the SF stage, as that + information is not required for setup calculations). Skipping over irrelevant data can + only help to improve performance. + Specifying a vertex data source extending beyond the end of a vertex entry is + UNDEFINED. + +Vertex URB This SV determines the amount of vertex data (starting at Vertex URB Entry Read +Entry Read Offset) to be read from each VUEs and passed into the payload URB data. It is +Length specified in 256-bit units. + A zero value is INVALID (at very least one 256-bit unit must be read). + Specifying a vertex data source extending beyond the end of a VUE is + UNDEFINED. + +Programming Restrictions: (others may already been mentioned) +  The maximum size payload for any thread is limited by the number of GRF registers available to the + thread, as determined by min( 128, 16 * GRF Register Block Count). Software is responsible for + ensuring this maximum size is not exceeded, taking into account: + o The size of the Fixed and Extended Payload Header associated with the FF unit. + o The Dispatch GRF Start Register for URB Data SV. + o The amount of CURBE data included (via Constant URB Entry Read Length) + o The number of VUEs included (as a function of FF unit, it’s state programming, and + incoming primitive types) + o The amount of VUE data included for each vertex (via Vertex URB Entry Read + Length) + o (For WM-spawned PS threads) The amount of Primitive URB Entry data. + +  For any type of URB Entry reads: + o Specifying a source region (via Read Offset, Read Length) that goes past the end of + the URB Entry allocation is illegal. +  The allocated size of Vertex/Primitive URB Entries is determined by the URB + Entry Allocation Size value provided in the pipeline state descriptor of the FF + unit owning the VUE/PUE. +  The allocated size of CURBE entries is determined by the URB Entry + Allocation Size value provided in the CS_URB_STATE command. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 53 + 1.9.5 Thread Output Handling +Those FF units spawning threads are responsible for monitoring and responding to certain events +generated by their spawned threads. Such events are indirectly detected by these FF units monitoring +messages sent from threads to the URB Shared Function. By snooping the Message Bus Sideband and +Header information, a FF can detect when a particular spawned thread sends a message to the URB +function. A subset of this information is then captured and acted upon. Refer to the URB chapter for more +details (including a table of valid/invalid combinations of the Complete, Used, Allocate, and EOT bits) +The following subsections describe functions that FF units perform as part of Thread Output Handling. + +1.9.5.1 VUE Allocation (GS) +The following description is applicable only to the GS stage. +The threads are not passed an initial handle. Instead, they request a first handle (if any) via the URB +shared function’s FF_SYNC message (see Shared Functions). If additional handles are required, the +URB_WRITE allocate mechanism (mentioned above) is used. + +1.9.5.2 Thread Termination +All threads must explicitly terminate by executing a SEND instruction with the EOT bit set. (See EU +chapters). When a thread spawned by a 3D FF unit terminates, the spawning FF unit detects this +termination as a part of Thread Management. This allows the FF units to manage the number of +concurrent threads it has spawned and also manage the resources (e.g., scratch space) allocated to +those threads. + + +1.9.6 VUE Readback +Starting with the CLIP stage, the 3D pipeline requires vertex information in addition to the VUE handle. +For example, the CLIP unit’s VertexClipTest function needs the vertex position, as does the SF unit’s +functions. This information is obtained by the 3D pipeline reading a portion of each vertex’s VUE data +directly from the URB. This readback (effectively) occurs immediately before the CLIP VertexClipTest +function, and immediately after a CLIP thread completes the output of a destination VUE. +The Vertex Header (first 256 bits) of the VUE data is read back. (See the previous VUE Formats +subsection (above) for details on the content and format of the Vertex Header.) : Additional Clip/Cull data +(located immediately past the Vertex Header) may be read prior to clipping. +This readback occurs automatically and is not under software control. The only software implication is that +the Vertex Header must be valid at the readback points, and therefore must have been previously loaded +or written by a thread. + + +1.9.7 Statistics Gathering +The table below describes how supports the required API statistics counters. + DX Statistic HW Support +IAVertices = # of vertices IA generated. May or may not VF maintains IA_VERTICES_COUNT. +include (a) vertices in partial primitives, (b) unused adjacent- + Will include unused adjacent-only vertices. Will not +only vertices. Not affected by vertex caching. + include vertices in partial primitives. + +IAPrimitives = # of primitives (objects) IA generated. May or VF maintains IA_PRIMITIVES_COUNT. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 54 + DX Statistic HW Support +may not include partial primitives. Will not include partial primitives. Will not count + patch topologies that do not match what the HS or + GS expects as input , if enabled (i.e., mismatching + patch topologies are discarded by VF). + +VSInvocations = # of times VS is executed. May be affected VS maintains VS_INVOCATION_COUNT. +by vertex caching. May or may not include (a) shared vertices + Impacted by vertex caching. Will not include vertices +in non-indexed strips, (b) vertices in partial primitives, (c) + in partial primitives. Will include unused adjacent- +unused adjacent-only vertices. + only vertices. Will not include shared vertices in non- + indexed strips, unless pre-empted. Increments even + if VS Function Enable is DISABLED. + +HSInvocations = # of patches executed by HS. HS maintains HS_INVOCATION_COUNT. This gets + incremented by 1 for each patch whenever HS is + enabled. + +DSInvocations = # of times DS is executed to shade a DS maintains DS_INVOCATION_COUNT. This is +domain point. Allows HW to shade identical domain points incremented for each domain point passed to a DS +multiple times, with the exception of point outputs where only thread. +unique domain points can be generated. + +GSInvocations = # of times GS is executed. Obviously does GS maintains GS_INVOCATION_COUNT, +not include partial primitives. May be incremented when incrementing it by GSInvocations Increment Value +StreamOut enabled, even if NULL_GS. for each dispatched instance. + Will not be incremented if NULL_GS. + +GSPrimitives = # of primitives GS generated. Does not GS maintains GS_PRIMITIVE_COUNT. GS unit will +include primitives passing through a disabled GS stage. May increment this as it parses the GS thread output. +or may not include partial primitives output by GS. + Will not include partial primitives output by GS + threads. + +NumPrimitivesWritten[] = # of complete SOL maintains SO_NUM_PRIMS_WRITTEN[0-3]. +primitives written to the stream’s SO buffer, subject to buffer +overflow. + +PrimitiveStorageNeeded[] = # of complete SOL maintains SO_PRIM_STORAGE_NEEDED[0- +primitives which would have been written to the stream’s SO 3]. +buffer ignoring any overflow. + +CInvocations = # of primitives entering rasterization (which CL OSB maintains CL_INVOCATION_COUNT. +starts with the clipper) and isn’t affected by any actual clipping. + Will not include partial primitives. Note that the SOL +Does not increment when rasterization is disabled (e.g., when + (regardless of SO enabled) will discard primitives if +StreamOut is the last enabled stage). May or may not include + rendering is disabled, so these primitives will not +partial primitives. + reach the CL unit. + +CPrimitives = # of primitives output from clipper. I.e., doesn’t SF OSB maintains CL_PRIMITIVES_COUNT. +increment if TrivReject or dropped due to NaNs, increments by + Will not include partial primitives. +1 if TrivAccept, or increments by number of primitives +generated if MustClip. Does not increment when rasterization +is disabled. May or may not include partial primitives. +Accomodates infinite or no guardband. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 55 + DX Statistic HW Support +PSInvocations = # of times PS is executed, including unlit WIZ maintains PS_INVOCATION_COUNT. +“helper pixels” within a subspan that need to go through the +PS shader to provide 2x2 gradients. Accomodates early +depth/stencil. Does not increment if NULL PS. Multisampling: +counts pixels shaded If PERPIXEL or samples shaded if +PERSAMPLE. + +Occlusion = # of “visible” multisamples which passed both WIZ & PBE maintain PS_DEPTH_COUNT. +depth and stencil testing. Doesn’t include PS-discarded pixels +or oMask/AlphaToCoverage-killed samples. Both (a) a +disabled test (depth or stencil) and (b) no bound RT or +Depth/Stencil buffer conditions count as always passing. + + + +1.10 Synchronization of the 3D Pipeline +Two types of synchronizations are supported for the 3D pipe: top of the pipe and end of the pipe. Top of +the pipe synchronization really enforces the read-only cache invalidation. This synchronization +guarantees that primitives rendered after such synchronization event fetches the latest read-only data +from memory. End of the pipe synchronization enforces that the read and/or read-write buffers do not +have outstanding hardware accesses. These are used to implement read and write fences as well as to +write out certain statistics deterministically with respect to progress of primitives through the pipeline (and +without requiring the pipeline to be flushed.) The PIPE_CONTROL command (see details below) is used +to perform all of above synchronizations. + + +1.10.1 Top-of-Pipe Synchronization +Top-of-pipe synchronization refers to SW actions to prepare HW for new state-binding at the beginning of +the rendering sequence in a given context. HW may have residual states cached in the state-caches and +read-only surfaces in various caches. With new rendering sequence, read-only surfaces may go through +change in the binding. Hence read-only invalidation is required before such new rendering sequence. +Read-only cache invalidation is top-of-pipe synchronization. Upon parsing this specific pipe-control +command, HW invalidates all caches in GT domain that have read-only surfaces but does not guarantee +invalidation beyond GT caches (i.e. LLC). Further, HW does not guarantee that all prior accesses to those +read-only surfaces have completed. Therefore SW must guarantee that there are no pending accesses to +those read-only surfaces before initializing the top-of-pipe synchronization. PIPE-CONTROL command +described below allows for invalidating individual read-only stream type. It is recommended that driver +invalidates only the required caches on the need basis so that cache warm-up overhead can be reduced. + + +1.10.2 End-of-Pipe Synchronization +The driver can use end-of-pipe synchronization to know that rendering is complete (although not +necessarily in memory) so that it can de-allocate in-memory rendering state, read-only surfaces, +instructions, and constant buffers. An end-of-pipe synchronization point is also sufficient to guarantee that +all pending depth tests have completed so that the visible pixel count is complete prior to storing it to +memory. End-of-pipe completion is sufficient (although not necessary) to guarantee that read events are +complete (a “read fence” completion). Read events are still pending if work in the pipeline requires any +type of read except a render target read (blend) to complete. +Write synchronization is a special case of end-of-pipe synchronization that requires that the render cache +and/or depth related caches are flushed to memory, where the data will become globally visible. This type + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 56 + of synchronization is required prior to SW (CPU) actually reading the result data from memory, or initiating +an operation that will use as a read surface (such as a texture surface) a previous render target and/or +depth/stencil buffer. + + +1.10.3 Synchronization Actions +In order for the driver to act based on a synchronization point (usually the whole point), the reaching of +the synchronization point must be communicated to the driver. This section describes the actions that +may be taken upon completion of a synchronization point which can achieve this communication. + +1.10.3.1 Writing a Value to Memory +The most common action to perform upon reaching a synchronization point is to write a value out to +memory. An immediate value (included with the synchronization command) may be written. In lieu of an +immediate value, the 64-bit value of the PS_DEPTH_COUNT (visible pixel count) or TIMESTAMP register +may be written out to memory. The captured value will be the value at the moment all primitives parsed +prior to the synchronization commands have been completely rendered, and optionally after all said +primitives have been pushed to memory. It is not required that a value be written to memory by the +synchronization command. +Visible pixel or TIMESTAMP information is only useful as a delta between 2 values, because these +counters are free-running and are not to be reset except at initialization. To obtain the delta, two +PIPE_CONTROL commands should be initiated with the command sequence to be measured between +them. The resulting pair of values in memory can then be subtracted to obtain a meaningful statistic about +the command sequence. + +1.10.3.2 PS_DEPTH_COUNT +If the selected operation is to write the visible pixel count (PS_DEPTH_COUNT register), the +synchronization command should include the Depth Stall Enable parameter. There is more than one +point at which the global visible pixel count can be affected by the pipeline; once the synchronization +command reaches the first point at which the count can be affected, any primitives following it are stalled +at that point in the pipeline. This prevents the subsequent primitives from affecting the visible pixel count +until all primitives preceding the synchronization point reach the end of the pipeline, the visible pixel count +is accurate and the synchronization is completed. This stall has a minor effect on performance and should +only be used in order to obtain accurate “visible pixel” counts for a sequence of primitives. +The PS_DEPTH_COUNT count can be used to implement an (API/DDI) “Occlusion Query” function. + +1.10.3.3 Generating an Interrupt +The synchronization command may indicate that a “Sync Completion” interrupt is to be generated (if +enabled by the MI Interrupt Control Registers – see Memory Interface Registers) once the rendering of all +prior primitives is complete. Again, the completion of rendering can be considered to be when the internal +render cache has been updated, or when the cache contents are visible in memory, as selected by the +command options. + +1.10.3.4 Invalidating of Caches +If software wishes to use the notification that a synchronization point has been reached in order to reuse +referenced structures (surfaces, state, or instructions), it is not sufficient just to make sure rendering is +complete. If additional primitives are initiated after new data is laid over the top of old in memory following +a synchronization point, it is possible that stale cached data will be referenced for the subsequent + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 57 + rendering operation. In order to avoid this, the PIPE_CONTROL command must be used. (See +PIPE_CONTROL Commanddescription below). + + +1.10.4 PIPE_CONTROL Command +The PIPE_CONTROL command is used to effect the synchronization described above. Parsing of a +PIPE_CONTROL command stalls 3D pipe only if the stall enable bit is set. Commands after +PIPE_CONTROL will continue to be parsed and processed in the 3D pipeline. This may include additional +PIPE_CONTROL commands. The implementation does enforce a practical upper limit (8) on the +number of PIPE_CONTROL commands that may be outstanding at once. Parsing of a PIPE_CONTROL +command that causes this limit to be reached will stall the parsing of new commands until the first of the +outstanding PIPE_CONTROL commands reaches the end of the pipe and retires. +Note that although PIPE_CONTROL is intended for use with the 3D pipe, it is legal to issue +PIPE_CONTROL when the Media pipe is selected. In this case PIPE_CONTROL will stall at the top of the +pipe until the Media FFs finish processing commands parsed before PIPE_CONTROL. Post- +synchronization operations, flushing of caches and interrupts will then occur if enabled via +PIPE_CONTROL parameters. Due to this stalling behavior, only one PIPE_CONTROL command can be +outstanding at a time on the Media pipe. +For the invalidate operation of the pipe control, the following pointers are affected. The invalidate +operation affects the restore of these packets. If the pipe control invalidate operation is completed before +the context save, the indirect pointers will not be restored from memory. + 1. Pipeline State Pointer + 2. Media State Pointer + 3. Constant Buffer Packet + It is up to software to program the appropriate read-only cache invalidation such as the sampler and +constant read caches or the instruction and state caches. Once notification is observed, new data may +then be loaded (potentially “on top of” the old data) without fear of stale cache data being referenced for +subsequent rendering. +If software wishes to access the rendered data in memory (for analysis by the application or to copy it to a +new location to use as a texture, for examples), it must also ensure that the write cache (render cache) is +flushed after the synchronization point is reached so that memory will be updated. This can be +accomplished by setting the Write Cache Flush Enable bit. Note that the Depth Stall Enable bit must be +clear in order for the flush of the render cache to occur. Depth Stall Enable is intended only for accurate +reporting of the PS_DEPTH counter; the render cache cannot be flushed nor can the read caches be +invalidated (except for the instruction/state cache) in conjunction with this operation. + +1.10.4.1 PIPE_CONTROL +Hardware can support up to 8 pending PIPE_CONTROL flushes + + +2 Store Data Commands (such as MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) + PIPE_CONTROL w/ stall (20) and TLB inv bit (18) set + + + Ring/Batch Contents - ILLEGAL + 3DPRIMITIVE + np-state +pipelined (bit 20 = ‘0’) PIPE_CONTROL + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 58 + Ring/Batch Contents - ILLEGAL + np-state + 3DPRIMITIVE + + + Ring/Batch Contents - LEGAL + 3DPRIMITIVE + np-state + 3DPRIMITIVE +pipelined (bit 20 = ‘0’) PIPE_CONTROL + np-state + 3DPRIMITIVE +  Pipe_control with CS-stall bit set must be issued before a pipe-control command that has the State + Cache Invalidate bit set. + +Caches Invalidated/Flushed by PIPE_CONTROL Bit Settings +The table below explains all the different flush/invalidation scenerios. + Write non-VF RO pipeline Top of pipe + cache Notification Cache VF RO Cache Marker marker Completion invalidate pulse + flush Enabled Invalidate Invalidate Sent enable Requested from CS + 0 0 0 0 N/A N/A N/A N/A + 0 0 0 1 Yes No N/A No + 0 0 1 0 No N/A N/A Yes + 0 0 1 1 Yes No No Yes + X 1 0 X Yes Yes Yes No + X 1 1 X Yes Yes Yes Yes + 1 X 0 X Yes Yes Yes No + 1 X 1 X Yes Yes Yes Yes + + + + + PIPE_CONTROL + +Length Bias: 2 +The PIPE_CONTROL command is used to effect the synchronization described above. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 2h PIPE_CONTROL + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 0h PIPE_CONTROL + Format: OpCode + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 59 + PIPE_CONTROL + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 3h DWORD_COUNT_n + + Format: =n +1 31:28 Reserved + Project: All + Format: MBZ + 27 Reserved + + Format: MBZ + 26 Reserved + Project: All + Format: MBZ + 25 Reserved + + Format: MBZ + 24 Destination Address Type + + Defines address space of Destination Address + Value Name Description Project + 0h PPGTT Use PPGTT address space for DW write All + 1h GGTT Use GGTT address space for DW write All + + + Programming Notes + Ignored if “”No Write” is selected in Operation. + 23 LRI Post-Sync Operation + + + + + Value Name Description Project + 0h No LRI Operation No LRI operation occurs as a result of this instruction. The Post-Sync All + Operation field is valid and may be used to specify an operation. + 1h MMIO Write Write the DWord contained in Immediate Data Low (DW3) to the All + Immediate Data MMIO offset specifed in the Address field. + + + Programming Notes + This bit caues a post sync operation with an LRI (Load Register Immediate) operation. If this bit is set + then the Post-Sync Operation field must be cleared. + 21 Store Data Index + Project: All + Format: U1 + Ring Buffer Mode Scheduling: This field is valid only if the post-sync operation is not 0. If this bit is set, + the store data address is actually an index into the global hardware status page. This bit only applies to + the Global HW status page. If this field is 1, the Destination Address Type in this command must be set + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 60 + PIPE_CONTROL + to 1 (GGTT). + Execlist Mode Scheduling: This field is valid only if the post-sync operation is not 0. If this bit is set, the + store data address is index into the global hardware status page when destination address type in the + command is set to 1 (GGTT). The store data address is index into the per-process hardware status + page when destination address type in the command is set to 0 (PPGTT). + + 20 CS Stall + Project: All + Format: U1 + If ENABLED, the sync operation will not occur until all previous flush operations pending a completion + of those previous flushes will complete, including the flush produced from this command. This enables + the command to act similar to the legacy MI_FLUSH command. + Programming Notes Project + One of the following must also be set: + + +  + Render Target Cache Flush Enable ([12] of DW1) +  + Depth Cache Flush Enable ([0] of DW1) +  + Stall at Pixel Scoreboard ([1] of DW1) +  + Depth Stall ([13] of DW1) +  + Post-Sync Operation ([13] of DW1) + + 19 Global Snapshot Count Reset + Project: All + Format: U1 + + + Value Name Description Project + 0h Don’t Do not reset the snapshot counts or Statistics Counters. All + Reset + 1h Reset Reset the snapshot count for all the units and reset the Statistics Counters All + except as noted above. + + + Programming Notes Project + TIMESTAMP is not reset by PIPE_CONTROL with this bit set. + When Post Sync Operation is set to “Write PS Depth Count” along with Global Snapshot + Count Reset, PS Depth Count is Reported first before resetting the value. + 18 TLB Invalidate + Project: All + Format: U1 + + + If ENABLED, all TLBs will be invalidated once the flush operation is complete. Note that if the flush + TLB invalidation mode is clear, a TLB invalidate will occur irrespective of this bit setting + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 61 + PIPE_CONTROL + If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to + Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set. + + + Programming Notes Project + If ENABLED, all TLBs will be invalidated once the flush operation is complete. Note that if the + flush TLB invalidation mode is clear, a TLB invalidate will occur irrespective of this bit setting. + 17 Reserved + + Format: MBZ + 16 Generic Media State Clear + + Format: Disable + If set, all generic media state context information will not be included with the next context save, + assuming no new state is initiated after the flush. If clear, the generic media state context save state + will not be affected. An MI_FLUSH with this bit set should be issued once all the Media Objects that will + be processed by a given persistent root thread have been issued or when an MI_SET_CONTEXT + switching from a generic media context to a 3D context completes. When using MI_SET_CONTEXT, + once state is programmed, it will be saved and restarted as part of any context each time that context is + saved/restored until an MI_FLUSH with this bit set is issued in that context. + + 15:14 Post-Sync Operation + Project: All + + + Description Project + This field specifies an optional action to be taken upon completion of the synchronization + operation. + This field must be cleared if the LRI Post-Sync Operation bit is set. + + + Value Name Description Project + 0h No Write No write occurs as a result of this instruction. This can be used to All + implement a “trap” operation, etc. + 1h Write Immediate Write the QWord containing Immediate Data Low, High DWs to the All + Data Destination Address + 2h Write PS Depth Write the 64-bit PS_DEPTH_COUNT register to the Destination All + Count Address + 3h Write Timestamp Write the 64-bit TIMESTAMP register to the Destination Address All + + + Programming Notes + If executed in non-secure batch buffer, the address given will be in a PPGTT address space. If in a + secure ring or batch, address given will be in GGTT space + 13 Depth Stall Enable + Project: All + Format: Enable + This bit should be set when obtaining a “visible pixel” count to preclude the possible inclusion in the + PS_DEPTH_COUNT value written to memory of some fraction of pixels from objects initiated after the + PIPE_CONTROL command. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 62 + PIPE_CONTROL + Value Name Description Project + 0h Disable 3D pipeline will not stall subsequent primitives at the Depth Test stage. All + 1h Enable 3D pipeline will stall any subsequent primitives at the Depth Test stage until the All + Sync and Post-Sync operations complete. + + + Programming Notes + This bit should be DISABLED for operations other than writing PS_DEPTH_COUNT. + This bit will have no effect (besides preventing write cache flush) if set in a PIPE_CONTROL command + issued to the Media pipe. + 12 Render Target Cache Flush Enable + Project: All + Format: Enable + Setting this bit will force Render Cache to be flushed to memory prior to this synchronization point + completing. This bit should be set for all write fence sync operations to assure that results from + operations initiated prior to this command are visible in memory once software observes this + synchronization. + Value Name Description Project + 0h Disable Flush Render Target Cache is NOT flushed. All + 1h Enable Flush Render Target Cache is flushed. All + + + Programming Notes + This bit should be DISABLED for End-of-pipe (Read) fences, PS_DEPTH_COUNT or TIMESTAMP + queries. + This bit must not be set when Depth Stall Enable bit is set in this packet. + 11 Instruction Cache Invalidate Enable + Project: All + Format: Enable + Setting this bit is independent of any other bit in this packet. This bit controls the invalidation of the L1 + and L2 at the top of the pipe i.e. at the parsing time. + + 10 Texture Cache Invalidation Enable + Project: All + Format: Enable + Setting this bit is independent of any other bit in this packet. This bit controls the invalidation of the + texture caches at the top of the pipe i.e. at the parsing time. + + 9 Indirect State Pointers Disable + Project: All + Format: Enable + + + Description Project + At the completion of the post-sync operation associated with this pipe control packet, the + indirect state pointers in the hardware are considered invalid; the indirect pointers are not + saved in the context. If any new indirect state commands are executed in the command stream + while the pipe control is pending, the new indirect state commands are preserved. + + Using Invalidate State Pointer (ISP) only inhibits context restoring of Push Constant + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 63 + PIPE_CONTROL + (3DSTATE_CONSTANT_*) commands. Push Constant commands are only considered as + Indirect State Pointers. Once ISP is issued in a context, SW must initialize by programming + push constant commands for all the shaders (at least to zero length) before attempting any + rendering operation for the same context. + 8 Notify Enable + Project: All + Format: Enable + If ENABLED, a Sync Completion Interrupt will be generated (if enabled by the MI Interrupt Control + registers) once the sync operation is complete. See Interrupt Control Registers in Memory Interface + Registers for details. + + 7 PIPE_CONTROL Flush Enable + + Format: Enable + If ENABLED, the PIPE_CONTROL command will wait until all previous writes of immediate data from + post sync circles are complete before executing the next command. + + 5 DC Flush Enable + + Format: Enable + Setting this bit enables flushing of the L3$ portions that caches DC writes. + + 4 VF(address based) Cache Invalidation Enable + Project: All + Format: Enable + Setting this bit is independent of any other bit in this packet. This bit controls the invalidation of VF + address based cache at the top of the pipe i.e. at the parsing time. + + 3 Constant Cache Invalidation Enable + Project: All + Format: Enable + Setting this bit is independent of any other bit in this packet. This bit controls the invalidation of the + constant cache at the top of the pipe i.e. at the parsing time. + + 2 State Cache Invalidation Enable + Project: All + Format: Enable + Setting this bit is independent of any other bit in this packet. This bit controls the invalidation of the L1 + and L2 state caches at the top of the pipe i.e. at the parsing time. + + 1 Stall At Pixel Scoreboard + Project: All + Format: Enable + Defines the behavior of PIPE_CONTROL command at the pixel scoreboard. + Value Name Description Project + 0h Disable Stall at the pixel scoreboard is disabled. All + 1h Enable Stall at the pixel scoreboard is enabled. All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 64 + PIPE_CONTROL + Programming Notes + This bit should be DISABLED for End-of-pipe (Read) fences, PS_DEPTH_COUNT or TIMESTAMP + queries. This bit is ignored if Depth Stall Enable is set. Further the render cache is not flushed even if + Write Cache Flush Enable bit is set. + 0 Depth Cache Flush Enable + Project: All + Format: Enable + Setting this bit enables flushing (i.e. writing back the dirty lines to memory and invalidating the tags) of + depth related caches. This bit applies to HiZ cache, Stencil cache and depth cache. + Value Name Description Project + 0h Flush Disabled Depth relates caches (HiZ, Stencil and Depth) are NOT flushed. All + 1h Flush Enabled Depth relates caches (HiZ, Stencil and Depth) are flushed. All + + + Programming Notes + Ideally depth caches need to be flushed only when depth is required to be coherent in memory for later + use as a texture, source or honoring CPU lock. This bit should be DISABLED for End-of-pipe (Read) + fences, PS_DEPTH_COUNT or TIMESTAMP queries. + This bit must not be set when Depth Stall Enable bit is set in this packet. +2 31:2 Address + + Format: GraphicsAddress[31:2]U32 + If Post Sync Operation is set to 1h (LRI Post-Sync Operation must be clear): Bits 31:3 secify the QW + address of where the Immediate Data following this DW in the packet to be stored. Bit 2 MBZ Ignored if + "No Write" is the selected in Post-Sync Operation If LRI Post-Sync Operation is set: Bits 31:2 specify + the MMIO offset destination for the data in the Immediate Data Low (DW3) field. Only DW writes are + valid. + + 1:0 Reserved + Project: All + Format: MBZ +3 31:0 Immediate Data + Project: All + Format: U32 + This field specifies the Lower DWord value to be written to the targeted location. Only valid when Post- + Sync Operation is 1h (Write Immediate Data) or LRI Post-Sync Operation is set. + Ignored if Post-Sync Operation is “No write”, “Write PS_DEPTH_COUNT” or “Write TIMESTAMP”. + +4 31:0 Immediate Data + Project: All + Format: U32 + This field specifies the Upper DWord value to be written to the targeted location. Only valid when Post- + Sync Operation is 1h (Write Immediate Data) Ignored if Post-Sync Operation is “No write”, “Write + PS_DEPTH_COUNT”, “Write TIMESTAMP” or “LRI Post Sync Opeation”. + + + +1.10.4.2 Programming Restrictions for PIPE_CONTROL +PIPE_CONTROL arguments can be split up into three categories: + +  Post-sync operations + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 65 +  Flush Types +  Stall + +Post-sync operation is only indirectly affected by the flush type category via the stall bit. The stall category +depends on the both flush type and post-sync operation arguments. A PIPE_CONTROL with no +arguments set is Invalid. + +1.10.4.2.1 Post-Sync Operation +These arguments relate to events that occur after the marker initiated by the PIPE_CONTROL command +is completed. The table below shows the restrictions: + Arguments Bits Restrictions +LRI Post Sync Operation 23 Post Sync Operation ([15:14] of DW1) must be set to 0x0. +Global Snapshot Count 19 Requires stall bit ([20] of DW1) set. +Reset +Generic Media State 16 Requires stall bit ([20] of DW1) set. +Clear +Indirect State Pointers 9 Requires stall bit ([20] of DW1) set. +Disable +Store Data Index 21 Post-Sync Operation ([15:14] of DW1) must be set to something other than ‘0’. +Sync GFDT 17 Post-Sync Operation ([15:14] of DW1) must be set to something other than ‘0’ or + 0x2520[13] must be set. +TLB inv 18 + Also Requires stall bit ([20] of DW1) set. +Post Sync Op 15:14 + No Restriction. + LRI Post Sync Operation ([23] of DW1) must be set to ‘0’. + +Notify En 8 No Restriction. + + +1.10.4.2.2 Flush Types +These are arguments related to the type of read only invalidation or write cache flushing is being +requested. Note that there is only intra-dependency. That is, it is not affected by the post-sync operation +or the stall bit. The table below shows the restrictions. + Arguments Bit Restrictions +Depth Stall 13 + The following bits must be clear +  Render Target Cache Flush Enable ([12] of + DW1) +  Depth Cache Flush Enable ([0] of DW1) + + 12 +Render Target Cache Flush Depth Stall must be clear ([13] of DW1) +Depth Cache Flush 0 + Depth Stall must be clear ([13] of DW1) +Stall Pixel Scoreboard 1 No Restriction +Inst invalidate. 11 No Restriction +Tex invalidate. 10 No Restriction +VF invalidate 4 No Restriction +Constant invalidate 3 No Restriction +State Invalidate 2 No Restriction + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 66 + 1.10.4.2.3 \ Stall +If the stall bit is set, the command streamer waits until the pipe is completely flushed. +Arguments Bit Restrictions + 20 + Stall Bit [All Stepping][All SKUs]: + One of the following must also be set +  Render Target Cache Flush Enable ([12] of DW1) +  Depth Cache Flush Enable ([0] of DW1) +  Stall at Pixel Scoreboard ([1] of DW1) +  Depth Stall ([13] of DW1) +  Post-Sync Operation ([13] of DW1) +  Notify Enable ([8] of DW1) + + + + +1.11 Push Constant URB Allocation +The push constants are stored into the URB which is part of the L3$. Software is required to program the +hardware to allocate space in the URB for each shader push constant. The software is limited to the +bottom address of the URB and must ensure that none of the shaders have overlapping handles. Below +is a diagram that represents a possible programming of the URB with Push Constants: + + + +The sizes of the regions in the diagram will change to 16KB and 80KB, respectively + +URB Allocation + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 67 + In the above scheme we are allocating 16KB of push constants and 240KB of URB space. The handle +allocation is shown in the order of the FF pipeline but with the current hardware and state, the software +can program these to be any order and may size them to zero. Software may also use some if not all of +the 16KB above as handle allocations as long as none of the push constants or handle allocations +overlap. The only limitations are the sizes based off the table below and the restrictions in granularity +which are specified in the command descriptions of the URB state and the push constant allocation state +for each fixed function. +Below is a table that specifies the maximum size of each buffer: +Max Constant Buffer URB size + 16KB 256KB + 16KB 128KB + +Below is a diagram that represents how the hardware may move and store one CONSTANT_BUFFER +command for a fixed function shader: + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 68 + The bubbles in the URB are caused by the constant buffer in memory starting on a half cacheline and +being an even number in length. If the constant buffer starts on an odd cacheline and has an odd number +length then there will only be a bubble at the beginning of the buffer in the URB. If the constant buffer in + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 69 + memory starts on a cache line boundary and has an odd number length then the bubble will only be at the +end of the constant buffer in the URB. Once the constant buffer is written to the GRF space then all the +bubbles will be removed. +Software must guarantee that there is enough space in the push constant buffer in the URB to hold one +constant buffer from memory. This includes any buffering to write the 512b aligned requests from memory +into the URB. Because the L3$ only supports writes from memory in 512b chunks, the URB may have +some bubbles between each constant buffer fetch. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 70 + 2. 3D Pipeline – Vertex Fetch (VF) Stage +2.1 Vertex Fetch (VF) Stage Overview +The VF stage performs one major function: executing 3DPRIMITIVE commands. This is handled by the +VF’s InputAssembly function. The InputAssembly process is closely matched to the Input Assembly +function. Minor enhancements have been included to better support OpenGL. +The following subsections describe some high-level concepts associated with the VF stage. + + +2.1.1 Input Assembly +The VF’s InputAssembly function includes (for each vertex generated): + +  Generation of VertexIndex and InstanceIndex for each vertex, possibly via use of an Index Buffer. +  Lookup of the VertexIndex in the Vertex Cache (if enabled) +  If a cache miss is detected: + o Use of computed indices to fetch data from memory-resident vertex buffers + o Format conversion of the fetched vertex data + o Assembly of the format conversion results (and possibly some internally generated + data) to form the complete “input” (raw) vertex + o Storing the input vertex data in a Vertex URB Entry (VUE) in the URB + o Output of the VUE handle of the input vertex to the VS stage + +  If a cache hit is detected, the VUE handle from the Vertex Cache is passed to the VS stage (marked + as a cache hit to prevent any VS processing). + +2.1.1.1 Vertex Assembly +The VF utilizes a number of VERTEX_ELEMENT state structures to define the contents and format of the +vertex data to be stored in Vertex URB Entries (VUEs) in the URB. See below for a detailed description of +the command used to define these structures (3DSTATE_VERTEX_ELEMENTS). +Each active VERTEX_ELEMENT structure defines up to 4 contiguous DWords of VUE data, where each +DWord is considered a “component” of the vertex element. The starting destination DWord offset of the +vertex element in the VUE is specified, and the VERTEX_ELEMENT structures must be defined with +monotonically increasing VUE offsets. For each component, the source of the component is specified. +The source may be a constant (0, 0x1, or 1.0f), a generated ID (VertexID, InstanceID or PrimitiveID), or a +component of a structure in memory (e.g,. the Y component of an XYZW position in memory). In the case +of a memory source, the Vertex Buffer sourcing the data, and the location and format of the source data +with that VB are specified. +The VF’s Vertex Assembly process can be envisioned as the VF unit stepping through the +VERTEX_ELEMENT structures in order, fetching and format-converting the source information (if +memory resident), and storing the results in the destination VUE. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 71 + 2.1.2 Vertex Cache +The VF stage communicates with the VS stage in order to implement a Vertex Cache function in the 3D +pipeline. The Vertex Cache is strictly a performance-enhancing feature and has no impact on 3D pipeline +results (other than a few statistics counters). +The Vertex Cache contains the VUE handles of VS-output (shaded) vertices if the VS function is enabled, +and the VUE handles of VF-output (raw) vertices if the VS function is disabled. (Note that the actual +vertex data is held in the URB, and only the handles of the vertices are stored in the cache). In either +case, the contents of the cache (VUE handles) are tagged with the VertexIndex value used to fetch the +input vertex data. The rationale for using the VertexIndex as the tag is that (assuming no other state or +parameters change) a vertex with the same VertexIndex as a previous vertex will have the same input +data, and therefore the same result from the VF+VS function. +Note that any change to the state controlling the InputAssembly function (e.g., vertex buffer definition), or +any change to the state controlling the VS function (if enabled) (e.g., VS kernel), will result in the Vertex +Cache being invalidated. In addition, any non-trivial use of instancing (i.e., more than one instance per +3DPRIMITIVE command and the inclusion of instance data in the input vertex) will effectively invalidate +the cache between instances, as the InstanceIndex is not included in the cache tag. See Vertex Caching +in Vertex Shader for more information on the Vertex Cache (e.g., when it is implicitly disabled, etc.) + + +2.1.3 Input Data: Push Model vs. Pull Model +Given the programmability of the pipeline, and the ability of shaders to input (load/sample) data from +memory buffers in an arbitrary fashion, the decision arises in whether to push instance/vertex data into +the front of the pipeline or defer the data access (pull) to the shaders that require it. +There are tradeoffs involved in deciding between these models. For vertex data, it is probably always +better to push the data into the pipeline, as the VF hardware attempts to cover the latency of the data +fetch. The decision is less clear for instance data, as pushing instance data leads to larger Vertex URB +entries which will be holding redundant data (as the instance data for vertices of an object are by +definition the same). Regardless, the GEN 3D pipeline supports both models. + + +2.1.4 Generated IDs +[Note that the generated IDs are considered separate from any offset computations performed by the VF +unit, and are therefore described separately here.] +The VF generates InstanceID, VertexID, and PrimitiveID values as part of the InputAssembly process. +VertexID and InstanceID are only allowed to be inserted into the input vertex data as it is gathered and +written into the URB as a VUE. +The definition/use of PrimitiveID is more complicated than the other auto-generated IDs. PrimitiveID is +associated with an “object” , not a particular vertex. It is only available to the GS (: and HS) as a special +non-vertex input, and the PS as a constant-interpolated attribute. It is not seen by the VS (or DS) at all. +The PrimitiveID therefore is kept separate from the vertex data. Take for example a TRILIST primitive +topology: It should be possible to share vertices between triangles in the list (i.e., reuse the VS output of a +vertex), even though each triangle has a different PrimitiveID associated with it. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 72 + 2.1.4.1 Generated IDs +The InstanceID, VertexID, and PrimitiveID values associated with each vertex can be stored in the +vertex's VUE, via use of the Component n Control fields in the VERTEX_ELEMENT structure. This +makes the values available to the VS thread. +While the PrimitiveID can still be stored in the VUE (see above), there should be no API-specific reason +to do so. The 32-bit PrimitiveIDs associated with objects are passed down the FF pipeline and made +available to GS and Setup threads as payload header data. A side effect of this feature is that the vertex +cache can operate even when PrimitiveIDs are being used. + + +2.2 Index Buffer (IB) +The 3DSTATE_INDEX_BUFFER command is used to define an Index Buffer (IB) used in subsequent +3DPRIMITIVE commands. +The RANDOM access mode of the 3DPRIMITIVE command involves the use of a memory-resident IB. +The IB, defined via the 3DSTATE_INDEX_BUFFER command described below, contains a 1D array of 8, +16 or 32-bit index values. These index values will be fetched by the InputAssembly function, and +subsequently used to compute locations in VERTEXDATA buffers from which the actual vertex data is to +be fetched. (This is opposed to the SEQUENTIAL access mode were the vertex data is simply fetched +sequentially from the buffers). +Software is responsible for ensuring that accesses outside the IB do not occur. This is possible as +software can compute the range of IB values referenced by a 3DPRIMITIVE command (knowing the +StartVertexLocation, InstanceCount, and VerticesPerInstance values) and can then compare this +range to the IB extent. + + +2.2.1 3DSTATE_INDEX_BUFFER + 3DSTATE_INDEX_BUFFER + + +Source: RenderCS +Length Bias: 2 + +This command is used to specify the current IB state used by the VF function. At most one IB is defined and active +at any given time. +NOTES: The IB must be specified before any RANDOM 3D_PRIMITIVE commands are issued It is possible to have +vertex elements source completely from generated ID values and therefore not require any Index Buffer accesses. +In this case, VF function will simply ignore the Index Buffer state. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 73 + 3DSTATE_INDEX_BUFFER + 23:16 3D Command Sub Opcode + Default Value: 0Ah 3DSTATE_INDEX_BUFFER + Format: OpCode + 15:12 Index Buffer Object Control State + + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for this index buffer. + + 11 Reserved + Project: All + Format: MBZ + 10 Cut Index Enable + + Format: Enable + If ENABLED, the largest index value (0xFF,0xFFFF,0xFFFFFFFF, depending on Index Format) is + interpreted as the “cut” index. (See description of this elsewhere in this section). (Expected OpenGL + driver usage)This field can only be enabled for certain primitive topology types. Refer to the table later + in this section for details. + + 9:8 Index Format + Project: All + Format: U2 enumerated type + + + This field specifies the data format of the index buffer. All index values are UNSIGNED. + Value Name Project + 0h INDEX_BYTE All + 1h INDEX_WORD All + 2h INDEX_DWORD All + 7:0 DWord Length + Default Value: 1h Excludes DWord (0,1) + Project: All + Format: =n Total Length – 2 + + + +1 31:0 Buffer Starting Address + Project: All + Format: GraphicsAddress[31:0]Index_Buffer_Entry + This field contains the size-aligned (as specified by Index Format) Graphics Address of the first element + of interest within the index buffer.Software must program this value with the combination (sum) of the + base address of the memory resource and the byte offset from the base address to the starting + structure within the buffer. + Programming Notes + Index Buffers can only be allocated in linear (not tiled) graphics memory +2 31:0 Buffer Ending Address + Project: All + Format: GraphicsAddress[31:0] + If non-zero, this field contains the address of the last valid byte in the index buffer. Any index buffer + reads past this address returns an index value of 0 (as if the index buffer was zero-extended). + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 74 + 3DSTATE_INDEX_BUFFER + Software must guarantee that the buffer ends on an index boundary (e.g., for an INDEX_DWORD + buffer, Bits [1:0] == 11b). + Errata Description Project + Software needs to disable the index buffer by setting Index Buffer Start address AFTER + Index Buffer End address for draws where the starting index location is greater than the + index buffer size. + + + +The following table lists which primitive topology types support the presence of Cut Indices. +When 3DSTATE_INDEX_BUFFER has Cut Index Enable set,it is UNDEFINED to issue a 3DPRIMITIVE +with a primitive topology type not supporting a Cut Index (even if no cut indices are actually present in the +index buffer. + + Definition Cut Index? + 3DPRIM_POINTLIST Y + 3DPRIM_LINELIST Y + 3DPRIM_LINESTRIP Y + 3DPRIM_TRILIST Y + 3DPRIM_TRISTRIP Y + 3DPRIM_TRIFAN + N + 3DPRIM_QUADLIST + N + 3DPRIM_QUADSTRIP + N + 3DPRIM_LINELIST_ADJ Y + 3DPRIM_LINESTRIP_ADJ Y + 3DPRIM_TRILIST_ADJ Y + 3DPRIM_TRISTRIP_ADJ Y + 3DPRIM_TRISTRIP_REVERSE Y + 3DPRIM_POLYGON + N + 3DPRIM_RECTLIST N + 3DPRIM_LINELOOP + N + 3DPRIM_POINTLIST_BF Y + 3DPRIM_LINESTRIP_CONT Y + 3DPRIM_LINESTRIP_BF Y + 3DPRIM_LINESTRIP_CONT_BF Y + 3DPRIM_TRIFAN_NOSTIPPLE N + 3DPRIM_PATCHLIST_n + Y + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 75 + 2.2.2 Index Buffer Access +The following figure illustrates how the Index Buffer is accessed. + + + + +2.3 Vertex Buffers (VBs) +The 3DSTATE_VERTEX_BUFFERs and 3DSTATE_INSTANCE_STEP_RATE commands are used to +define Vertex Buffers (VBs) used in subsequent 3DPRIMITIVE commands. +Most input vertex data is sourced from memory-resident VBs. A VB is a 1D array of structures, where the +size of the structure as defined by the VB’s BufferPitch. VBs are accessed either as VERTEXDATA +buffers or INSTANCEDATA buffers, as defined by the VB’s BufferAccessType. The VB’s access type +will determine whether the VF-computed VertexIndex or InstanceIndex is used to access data in the VB. +Given that the RANDOM access mode of the 3DPRIMITIVE command utilizes an IB (possibly provided by +an application) to compute VB index values, VB definitions contain a MaxIndex value used to detect +accesses beyond the end of the VBs. Any access outside the extent of a VB returns 0. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 76 + 2.3.1 3DSTATE_VERTEX_BUFFERS + 3DSTATE_VERTEX_BUFFERS + + +Source: RenderCS +Length Bias: 2 + + This command is used to specify VB state used by the VF function. + This command can specify from 1 to 33 VBs. + The VertexBufferID field within a VERTEX_BUFFER_STATE structure indicates the specific VB. If a VB definition is + not included in this command, its associated state is left unchanged and is available for use if previously defined. + Programming Notes +It is possible to have individual vertex elements sourced completely from generated ID values and therefore not +require any vertex buffer accesses for that vertex element. In this case, VF function will simply ignore the VB state +associated with that vertex element. If all enabled vertex elements have this characteristic, no VBs are required to +process 3DPRIMITIVE commands. For example, this might arise when the user wants to perform all data lookups in +the first shader, so only generated index values need to be passed down to it. In this extreme case, SW would not +need to program any VB state, and therefore not need to issue any 3DSTATE_VERTEX_BUFFERS commands. +For any 3DSTATE_VERTEX_BUFFERS command, at least one VERTEX_BUFFER_STATE structure must be +included. +VERTEX_BUFFER_STATE structures are 4 DWords for both VERTEXDATA buffers and INSTANCEDATA buffers. +Inclusion of partial VERTEX_BUFFER_STATE structures is UNDEFINED. +The order in which VBs are defined within this command can be arbitrary, though a vertex buffer must be defined +only once in any given command (otherwise operation is UNDEFINED). + DWord Bit Description +0 31:29 Instruction Type + Default Value: 03h GFXPIPE + Format: Opcode + 28:27 Instruction Sub-Type + Default Value: 3h 3D + Format: Opcode + 26:24 Instruction Opcode + Default Value: 0h 3DSTATE_VERTEX_BUFFERS + Format: Opcode + 23:16 Instruction Sub-Opcode + Default Value: 08h 3DSTATE_VERTEX_BUFFERS + Format: Opcode + 15:8 Reserved + 7:0 DWord Count + Default Value: 3 DWORD_COUNT_n + Format: =n + n = 4b-1 (where b = # of buffer states included) + +1..n 127:0 Vertex Buffer State [n] + Format: VERTEX_BUFFER_STATE + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 77 + 2.3.2 VERTEX_BUFFER_STATE Structure + VERTEX_BUFFER_STATE + + +Source: RenderCS +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +This structure is used in 3DSTATE_VERTEX_BUFFERS to set the state associated with a VB. The VF function will +use this state to determine how/where to extract vertex element data for all vertex elements associated with the VB. +The VERTEX_BUFFER_STATE structure is 4 DWords for both INSTANCEDATA and VERTEXDATA buffers.A VB +is defined as a 1D array of vertex data structures, accessed via a computed index value. The VF function therefore +needs to know the starting address of the first structure (index 0) and size of the vertex data structure. + Programming Notes Project +Vertex element accesses which straddle or go past the VB’s End Address will return 0’s for all elements. +DWord Bit Description +0 31:26 Vertex Buffer Index + + Format: U6 Index + + + This field contains an index value which selects the VB state being defined. + Value Name + [0,32] + 25:21 Reserved + Project: All + Format: MBZ + 20 Buffer Access Type + + This field determines how vertex element data is extracted from this VB. This control applies to all + vertex elements associated with this VB. + Value Name Description Project + 00b VERTEXDATA For SEQUENTIAL vertex access, each vertex of an instance is All + sourced from sequential structures within the VB. For RANDOM + vertex access, each vertex of an instance is looked up + (separately) via a computed index value + 01b INSTANCEDATA Each vertex of an instance is sourced with the same (instance) All + data. Subsequent instances may be sourced with the same or + different data, depending on Instance Data Step Rate. + 19:16 Vertex Buffer Memory Object Control State + Project: All + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for this vertex buffer. + + 15 Reserved + Project: All + Format: MBZ + 14 Address Modify Enable + + If set, the Buffer Starting Address and End Address fields are used to update the state of this buffer. If + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 78 + VERTEX_BUFFER_STATE + clear, those fields are ignored and the previously-programmed values are maintained. + + 13 Null Vertex Buffer + + Format: Enable + This field enabled causes any fetch for vertex data to return 0. + + 12 Vertex Fetch Invalidate + Default Value: 0h + + Invalidate the Vertex overfetch cache when this bit is set. For multiple vertex buffer state structures in + one packet, this bit may be set only once in the entire packet. + + 11:0 Buffer Pitch + Format: U12 Count of bytes + + + This field specifies the pitch in bytes of the structures accessed within the VB. This information is + required in order to access elements in the VB via a structure index. + Value Name Description Project + [0,2048] Bytes + + + Programming Notes +  + Different VERTEX_BUFFER_STATE structures can refer to the same memory region using different + Buffer Pitch values. +  + See note on 64-bit float alignment in Buffer Starting Address. + + 31:0 Buffer Starting Address +1 Format: GraphicsAddress[31:0] + + + Description Project + This field contains the byte-aligned Graphics Address of the first element of interest within the + VB. Software must program this value with the combination (sum) of the base address of the + memory resource and the byte offset from the base address to the starting structure within the + buffer. + If the Address ModifyEnable bit is clear, this field is ignored and the previous value of Buffer + Starting Address for this buffer is maintained. + + + Programming Notes + 64-bit floating point values must be 64-bit aligned in memory, or UNPREDICTABLE data will be + fetched. When accessing an element containing 64-bit floating point values, the Buffer Starting + Address and Source Element Offset values must add to a 64-bit aligned address, and BufferPitch must + be a multiple of 64-bits. + VBs can only be allocated in linear (not tiled) graphics memory. + As computed index values are, by definition, interpreted as unsigned values, there is no issue with + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 79 + VERTEX_BUFFER_STATE + accesses to locations before (lower address value) the start of the buffer. However, these wrapped + indices are subject to Max Index checking (see below). +2 31:0 End Address + + Format: GraphicsAddress[31:0]U32 + + + Description Project + This field defines the address of the last valid byte in this particular VB. Access of a vertex + element which either straddles or is beyond this address will return 0’s for any data read. + If the Address ModifyEnable bit is clear, this field is ignored and the previous value of End + Address for this buffer is maintained. + + + + Value Name + [0,FFFFFFFFh] + 0h [Default] +3 31:0 Instance Data Step Rate + Format: U32 + This field only applies to INSTANCEDATA buffers – it is ignored (but still present) for VERTEXDATA + buffers). + This field determines the rate at which instance data for this particular INSTANCEDATA vertex buffer is + changed in sequential instances. Only after the number of instances specified by this field is generated + is new (sequential) instance data provided. This process continues for each group of instances defined + in the draw command. For example, a value of 1 in this field causes new instance data to be supplied + with each sequential (instance) group of vertices. A value of 2 causes every other instance group of + vertices to be provided with new instance data. The special value of 0 causes all vertices of all + instances generated by the draw command to be provided with the same instance data. (The same + effect can be achieved by setting this field to its maximum value.) + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 80 + 2.3.3 VERTEXDATA Buffers – SEQUENTIAL Access +Instead of “VBState.StartingBufferAddress + VBState.MaxIndex x VBState.BufferPitch”, the address of +the byte immediately beyond the last valid byte of the buffer is determined by “VBState.EndAddress+1”. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 81 + 2.3.4 VERTEXDATA Buffers – RANDOM Access +Instead of “VBState.StartingBufferAddress + VBState.MaxIndex x VBState.BufferPitch”, the address of +the byte immediately beyond the last valid byte of the buffer is determined by “VBState.EndAddress+1”. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 82 + 2.3.5 INSTANCEDATA Buffers +Instead of “VBState.StartingBufferAddress + VBState.MaxIndex x VBState.BufferPitch”, the address of +the byte immediately beyond the last valid byte of the buffer is determined by “VBState.EndAddress+1”. + + + + +2.4 Input Vertex Definition +The 3DSTATE_VERTEX_ELEMENTS command is used to define the source and format of input vertex +data and the format of how it is stored in the destination VUE as part of 3DPRIMITIVE processing in the +VF unit. +Refer to 3DPRIMITIVE Processing below for the general flow of how input vertices are input and stored +during processing of the 3DPRIMITIVE command. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 83 + 2.4.1 3DSTATE_VERTEX_ELEMENTS + 3DSTATE_VERTEX_ELEMENTS + + +Source: RenderCS +Length Bias: 2 +This is a variable-length command used to specify the active vertex elements (up to 34) Each +VERTEX_ELEMENT_STATE structure contains a Valid bit which determines which elements are used. + Programming Notes Project +At least one VERTEX_ELEMENT_STATE structure must be included. +Inclusion of partial VERTEX_ELEMENT_STATE structures is UNDEFINED. +SW must ensure that at least one vertex element is defined prior to issuing a 3DPRIMTIVE command, or +operation is UNDEFINED. +There are no ‘holes’ allowed in the destination vertex: NOSTORE components must be overwritten by +subsequent components unless they are the trailing DWords of the vertex. Software must explicitly chose +some value (probably 0) to be written into DWords that would otherwise be ‘holes’. +Within a VERTEX_ELEMENT_STATE structure, if a Component Control field is set to something other than +VFCOMP_STORE_SRC, no higher-numbered Component Control fields may be set to +VFCOMP_STORE_SRC. In other words, only trailing components can be set to something other than +VFCOMP_STORE_SRC. +(See additional restrictions listed in the command fields and VERTEX_ELEMENT_STATE description). +Element[0] must be valid. +All elements must be valid from Element[0] to the last valid element. (i.e. if Element[2] is valid then +Element[1] and Element[0] must also be valid) +The pitch between elements packed in the URB will always be 128 bits. + DWord Bit Description +0 31:29 Instruction Type + Default Value: 03h GFXPIPE + Format: Opcode + 28:27 Instruction Sub-Type + Default Value: 3h 3D + Format: Opcode + 26:24 Instruction Opcode + Default Value: 0h 3DSTATE_VERTEX_ELEMENTS + Format: Opcode + 23:16 Instruction Sub-Opcode + Default Value: 09h 3DSTATE_VERTEX_ELEMENTS + Format: Opcode + 15:8 Reserved + 7:0 DWord Count + Format: =n + Vertex Element Count = (DWord Count + 1) / 2 + Value Name Description Project + 1 DWORD_COUNT_n [Default] excludes DWords 0,1 + [0,66] Range 1-34 Elements +1..n 63:0 Element [n] + Format: VERTEX_ELEMENT_STATE + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 84 + 2.4.2 VERTEX_ELEMENT_STATE Structure + VERTEX_ELEMENT_STATE + +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +This structure is used in 3DSTATE_VERTEX_ELEMENTS to set the state associated with a vertex element. A vertex +element is defined as an entity supplying from 1 to 4 DWord vertex components to be stored in the vertex URB entry. +The number of supported vertex elements is: 34 +The VF function will use this state, and possibly the state of the associated vertex buffer, to fetch/generate the +source vertex element data, perform any required format conversions, padding with zeros, and store the resulting +destination vertex element data into the vertex URB entry. +DWord Bit Description +0 31:26 Vertex Buffer Index + + Format: U6 + This field specifies which vertex buffer the element is sourced from. + Value Name + [0,32] Up to 33 VBs are supported + + + Programming Notes + It is possible for a vertex element to include only internally-generated data (VertexID, etc.), in which + case the associated vertex buffer state is ignored. + 25 Valid + + Format: Boolean + + + + Value Name Description Project + 1h TRUE this vertex element is used in vertex assembly All + 0h FALSE this vertex element is not used. All + 24:16 Source Element Format + Project: All + Format: SURFACE_FORMAT + + + Range: Valid encodings are those marked as “Y” in the “Vertex Buffer” column of the table of Surface + Format encodings in the Sampler chapter. + Format: The encoding of this field is identical the Surface Format field of the SURFACE_STATE + structure, as described in the Sampler chapter. + This field specifies the format in which the memory-resident source data for this particular vertex + element is stored in the memory buffer. This only applies to elements stored with + VFCOMP_STORE_SRC component control. (All other component types have an explicit format). + 15 Edge Flag Enable + + Format: Enable + Description Project + When ENABLED, the source element is interpreted as an EdgeFlag for the vertex. If the + source element is zero, the EdgeFlag will be set to FALSE. If the source element is non-zero, + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 85 + VERTEX_ELEMENT_STATE + the EdgeFlag will be set to TRUE. The EdgeFlag bit will travel down the fixed function pipeline + along with the vertex handle, etc. and not be stored in the vertex data like the other vertex + elements. Refer to the fixed function descriptions for how this EdgeFlag affects rendering. + Edge flags are supported for the following primitive topology types only, otherwise + EdgeFlagEnable must not be ENABLED. +  3DPRIM_TRILIST* +  3DPRIM_TRISTRIP* +  3DPRIM_TRIFAN* +  3DPRIM_POLYGON + + If this bit is DISABLED for all valid VERTEX_ELEMENTs, the vertex will be assigned a default + EdgeFlag of TRUE. + EdgeFlagEnable must not be ENABLED for 3DPRIM_TRISTRIP* and 3DPRIM_TRIFAN* + Edge flags are supported for all primitive topology types. + + + Programming Notes Project +  This bit must only be ENABLED on the last valid VERTEX_ELEMENT structure. +  When set, Component 0 Control must be set to VFCOMP_STORE_SRC, and + Component 1-3 Control must be set to VFCOMP_NOSTORE. + + Edge Flags are not supported for QUADLIST primitives. Software may elect to convert + QUADLIST primitives to some set of corresponding edge-flag-supported primitive types (e.g., + POLYGONs) prior to submission to the 3D pipeline. + 14:11 Reserved + Project: All + Format: MBZ + 10:0 Source Element Offset (in bytes) + Project: All + Format: U11 byte offset + + + Byte offset of the source vertex element data in the structures comprising the vertex buffer. + Value Name + [0,2047] + + + Programming Notes + See note on 64-bit float alignment in Buffer Starting Address. +1 31 Reserved + Project: All + Format: MBZ + 30:28 Component 0 Control + Project: All + Format: 3D_VertexComponentControl + Refer to the 3D_VertexComponentControl table below + + 27 Reserved + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 86 + VERTEX_ELEMENT_STATE + + Project: All + Format: MBZ + 26:24 Component 1 Control + Format: 3D_VertexComponentControl + Refer to the 3D_VertexComponentControl table below + + 23 Reserved + Project: All + Format: MBZ + 22:20 Component 2 Control + Format: 3D_VertexComponentControl + Refer to the 3D_VertexComponentControl table below + + 19 Reserved + Project: All + Format: MBZ + 18:16 Component 3 Control + Format: 3D_VertexComponentControl + Refer to the 3D_VertexComponentControl table below + + 15:8 Reserved + Project: All + Format: MBZ + 7:0 Reserved + + Format: MBZ + + + + + 3D_VertexComponentControl + +Project: All +Source: RenderCS +Size (in bits): 3 + +Value Name Description Project +0 VFCOMP_NOSTORE Don’t store this component. (Not valid for Component 0, but can be All + used for Component 1-3). Once this setting is used for a component, + all higher-numbered components (if any) MUST also use this + setting. (I.e., no holes within any particular vertex element). Also, + there are no ‘holes’ allowed in the destination vertex: NOSTORE + components must be overwritten by subsequent components unless + they are the trailing DWords of the vertex. Software must explicitly + chose some value (probably 0) to be written into DWords that would + otherwise be ‘holes’. +1 VFCOMP_STORE_SRC Store corresponding component from format-converted source All + element. Storing a component that is not included in the Source + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 87 + 3D_VertexComponentControl + Element Format results in an UNPREDICTABLE value being stored. + Software should used the STORE_0 or STORE_1 encoding to + supply default components.Within a VERTEX_ELEMENT_STATE + structure, if a Component Control field is set to something other than + VFCOMP_STORE_SRC, no higher-numbered Component Control + fields may be set to VFCOMP_STORE_SRC. In other words, only + trailing components can be set to something other than + VFCOMP_STORE_SRC. +2 VFCOMP_STORE_0 Store 0 (interpreted as 0.0f if accessed as a float value) All +3 VFCOMP_STORE_1_FP Store 1.0f All +4 VFCOMP_STORE_1_INT Store 0x1 All +5 VFCOMP_STORE_VID Store Vertex ID (as U32) +6 VFCOMP_STORE_IID Store Instance ID (as U32) +7 VFCOMP_STORE_PID Store Primitive ID (as U32)Software should no longer need to use All + this encoding as PrimitiveID is passed down the FF pipeline – see + explanation above. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 88 + 2.4.3 Vertex Element Data Path +The following diagram shows the path by which a vertex element within the destination VUE is generated +and how the fields of the VERTEX_ELEMENT_STATE structure is used to control the generation. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 89 + 2.5 3D Primitive Processing + +2.5.1 3D PRIMITIVE Command + 3DPRIMITIVE + + +Source: RenderCS +Length Bias: 2 + +The 3DPRIMITIVE command is used to submit 3D primitives to be processed by the 3D pipeline. Typically the +processing results in rendering pixel data into the render targets, but this is not required. +The parameters passed in this command are forwarded to the Vertex Fetch function. The Vertex Fetch function will +use this information to generate vertex data structures and store them in the URB. These vertices are then passed +down the 3D pipeline. + Programming Notes Project +If the threads spawned by this command are required to observe memory writes performed by threads +spawned from a previous command, software must precede this command with a command that performs a +(preferably pipelined) memory flush (e.g., 3D_PIPECONTROL). +Workloads enabling topology filter using MI_TOPOLOGY_FILTER must always program PIPECONTROL +command with only Post-Sync Operation (Write Immediate data) prior to every 3DPRIMTIVE command +programmed. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 3h 3DPRIMITIVE + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 0h 3DPRIMITIVE + Format: OpCode + 15:11 Reserved + Project: All + Format: MBZ + 10 Indirect Parameter Enable + Project: All + Format: U1 + If set, the values in DW 2-5 are ignored and replaced by the current values of the corresponding + 3DPRIM_xxx MMIO registers: +  3DPRIM_VERTEX_COUNT (instead of DW2: VertexCountPerInstance) +  3DPRIM_START_VERTEX (instead of DW3: StartVertexLocation) +  3DPRIM_INSTANCE_COUNT (instead of DW4: InstanceCount) +  3DPRIM_START_INSTANCE (instead of DW5: StartInstanceLocation) + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 90 + 3DPRIMITIVE + +  3DPRIM_BASE_VERTEX (instead of DW6: BaseVertexLocation) + + Indirect Parameter Enable and End Offset Enable must not be ENABLED at the same time, or + behavior is UNDEFINED. + + + 9 Reserved + + Format: MBZ + 8 Predicate Enable + Project: All + Format: Enable + If set, this command is executed (or not) depending on the current value of the MI Predicate internal + state bit. This command is ignored only if PredicateEnable is set and the Predicate state bit is 0. + + 7:0 DWord Length + Default Value: 5h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:10 Reserved + Project: All + Format: MBZ + 9 End Offset Enable + Project: All + Format: Enable + If set, the Vertex Count Per Instance field is IGNORED, and the VB0ENDOFFSET register is used to + indirectly specify the vertex count by defining the amount of valid data in VB0. The following + restrictions apply: +  VB0 must be enabled for use +  VertexAccessType = SEQUENTIAL +  Instance Count = 1 +  Start Vertex Location = 0 +  Start Instance Location = 0 +  Base Vertex Location = 0 + + Vertices are output until EndOffset is reached or exceeded in VB0. If EndOffset is reached or + exceeded within the data associated with a vertex, that vertex is considered incomplete and will not be + output. Partial objects will be discarded (as is normally done). + If clear, End Offset is ignored. + Indirect Parameter Enable and End Offset Enable must not be ENABLED at the same time, or + behavior is UNDEFINED. + + + 8 Vertex Access Type + Project: All + Format: VertexAccessType + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 91 + 3DPRIMITIVE + This field specifies how data held in vertex buffers marked as VERTEXDATA is accessed by Vertex + Fetch. + Value Name Description Project + 0h SEQUENTIAL VERTEXDATA buffers are accessed sequentiallyRequiref if End All + Offset Enable is ENABLED. + 1h RANDOM VERTEXDATA buffers are accessed randomly via an index All + obtained from the Index Buffer. + 7:6 Reserved + Project: All + Format: MBZ + 5:0 Primitive Topology Type + Project: All + Format: 3D_PrimTopoType See table below for encoding, see 3D Overview for diagrams and general + comments + + + This field specifies the topology type of 3D primitive generated by this command. Note that a single + primitive topology (list/strip/fan/etc.) can contain a number of basic objects (lines, triangles, etc.). + +2 31:0 Vertex Count Per Instance + Project: All + Format: U32 Count of vertices + + + Format: GraphicsAddress[31:0]U32*1 + This field specifies how many vertices are to be generated for each instance of the primitive topology. If + End Offset Enable is clear: + Format = U32 count of vertices + Range = [0, 2^32-1] (upper limit probably constrained by VB size) + Ignored if End Offset Enable or Indirect Parameter Enable is ENABLED. + Programming Notes +  This per-instance value should specify a valid number of vertices for the primitive topology type. + E.g., for 3DPRIM_TRILIST_ADJ, this field should specify a multiple of 6 vertices. However, in + cases where too few or too many vertices are provided, the unused vertices will be silently + discarded by the pipeline. +  A 0 value is this field effectively makes the command a ‘no-operation’. + +3 31:0 Start Vertex Location + Project: All + Format: U32 structure index + + + This field specifies the “starting vertex” for each instance. This allows skipping over part of the vertices + in a buffer if, for example, a previous 3DPRIMITIVE command had already drawn the primitives + associated with the earlier entries. + For SEQUENTIAL access, this field specifies, for each instance, a starting structure index into the + vertex buffers + For RANDOM access, this field specifies, for each instance, a starting index into the Index Buffer. + Programming Notes +  Access of any data outside of the valid extent of a vertex or index buffer will return the value 0 + (i.e., appears as if the data stored at the invalid location was 0). + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 92 + 3DPRIMITIVE + +  Must be set to 0 if End Offset Enable is ENABLED. +  Ignored if Indirect Parameter Enable is ENABLED + +4 31:0 Instance Count + Project: All + Format: U32 Count of instances + + + + + Description Project + This field specifies the number of instances by which the primitive topology is to be + regenerated. A value of 0 indicates “no instances” (no-op operation). A value of 1 effectively + specifies “non-instanced” operation, though vertex buffers will still be used to provide instance + data, if so programmed. + Ignored if Indirect Parameter Enable is ENABLED. + Must be set to 1 if End Offset Enable is ENABLED. + + + + Value Name + [0,FFFFFFFFh] +5 31:0 Start Instance Location + Project: All + Format: U32 structure index + + + + + Description Project + This field specifies the “starting instance” for the command as an initial structure index into + INSTANCEDATA buffers. + Subsequent instances will access sequential instance data structures, as controlled by the + Instance Data Step Rate. + + + Programming Notes +  Access of any data outside of the valid extent of a vertex or index buffer will return the value 0 + (i.e., appears as if the data stored at the invalid location was 0). +  Must be set to 0 if End Offset Enable is ENABLED. +  Ignored if Indirect Parameter Enable is ENABLED. + +6 31:0 Base Vertex Location + Project: All + Format: S31 index structure bias + + + This field specifies a signed bias to be added to values read from the index buffer. This allows the + same index buffer values to access different vertex data for different commands.This field applies only + to RANDOM access mode. This field is ignored for SEQUENTIAL access mode, where there Start + Vertex Location can be used to specify different regions in the vertex buffers. + Programming Notes + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 93 + 3DPRIMITIVE + +  Access of any data outside of the valid extent of a vertex or index buffer will return the value 0 + (i.e., appears as if the data stored at the invalid location was 0). +  Must be set to 0 if End Offset Enable is ENABLED. +  Ignored if Indirect Parameter Enable is ENABLED. + + + + +2.5.2 Functional Overview +The following pseudocode summarizes the general flow of 3D Primitive Processing. +CommandInit + InstanceLoop{ + VertexLoop{ + VertexIndexGeneration + if (CutFlag) + TerminatePrimitive + else + OutputBufferedVertex + VertexCacheLookup + if (miss) { + VertexElementLoop { + SourceElementFetch + FormatConversion + DestinationComponentSelection + PrimitiveInfoGeneration + URBWrite + } + } + } + TerminatePrimitive +} + + +2.5.3 CommandInit +The InstanceID value is initialized to 0. + + +2.5.4 InstanceLoop +The InstanceLoop is the outmost loop, iterating through each instance of primitives. There is no special +“non-instanced” mode – at a minimum there is one instance of primitives. +For SEQUENTIAL accessing, the VertexID value is initialized to 0 at the start of each instance. (For +RANDOM accessing, there is no initial value for VertexID, as it is derived from the fetched IB value). +The PrimitiveID is also initialized to 0 at the start of each instance. StartPrim is initialized to TRUE. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 94 + The VertexLoop (see below) is then executed to iterate through the instance vertices and output vertices +to the pipeline as required. +The end of each iteration of InstanceLoop includes an implied “cut” operation. +The InstanceID value is incremented at the end of each InstanceLoop. Note that each instance will +produce the same vertex outputs with the exception of any data dependent on InstanceID (i.e., “instance +data”). + + +2.5.5 VertexLoop +The VertexLoop iterates VertexNumber through the VertexCountPerInstance vertices for the instance. +For each iteration, a number of processing steps are performed (see below) to generate the information +that comprises a vertex. Note that, due to CutProcessing, each iteration does not necessarily output a +vertex to the pipeline. When a vertex is to be output, the following information is generated for that vertex: + +  PrimitiveType associated with the vertex. This is simply a copy of the PrimitiveTopologyType field of + the 3DPRIMITIVE +  VUE handle at which the vertex data is stored + o For a Vertex Cache hit, the VUE handle is marked with a VCHit boolean, so that the + VS unit will not attempt to process (shade) that vertex. + o Otherwise, the VertexLoop will generate and store the input vertex data into the VUE + referenced by this handle. + +  The PrimitiveID associated with the vertex. See PrimitiveInfoGeneration. +  PrimStart and PrimEnd booleans associated with the vertex. See PrimitiveInfoGeneration. + +(Note that a single vertex of buffering is required in order to associate PrimEnd with a vertex, as this +information may not be known until the next iteration through the VertexLoop (see +OutputPrimitiveDelimiter). +VertexNumber value is incremented by 1 at the end of the loop. + + +2.5.6 VertexIndexGeneration +A VertexIndex value needs to be derived for each vertex. With the exception of the “cut” index, this index +value is used as the vertex cache tag and will be used as a structure index into all VERTEXDATA VBs. +For SEQUENTIAL accessing, the VertexID and VertexIndex value is derived as shown below: + VertexIndex = StartVertexLocation + VertexNumber + VertexID = VertexNumber + +For RANDOM access, the VertexID and VertexIndex is derived from an IBValue read from the IB, as +shown below: + IBIndex = StartVertexLocation + VertexNumber + VertexID = IB[IBIndex] + + if (CutIndexEnable && VertexID == CutIndex) + CutFlag = 1 + else + VertexIndex = VertexID + BaseVertexLocation + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 95 + CutFlag = 0 + endif + + +2.5.7 TerminatePrimitive +For RANDOM accessing, and when enabled via Cut Index Enable, a fetched IBValue of ‘all ones’ (0xFF, +0xFFFF, or 0xFFFFFFFF depending on Index Format) is interpreted as a ‘cut value’ and signals the +termination of the current primitive and the possible start of the next primitive. This allows the application +to specify an instance as a sequence of variable-sized strip primitives (though the cut value applies to any +primitive type). +Also, there is an implied primitive termination at the end of each InstanceLoop (and so strip primitives +cannot span multiple instances). +In either case, the currently-buffered vertex (if any) is marked with EndPrim and then flushed out to the +pipeline. +The next-output vertex (if any) will be marked with StartPrim. +Whenever a primitive delimiter is encountered, the PIDCounterS and PIDCounterR counters are reset to +0. These counters control the incrementing (in PrimitiveInfoGeneration, below) of PrimitiveID within each +primitive topology of an instance. + if (PIDCounterS != 0) // There is a buffered vertex + if (primType == TRISTRIP_ADJ) + if (PIDCounterS==6 || PIDCounterR==1) + PrimitiveID++ + endif + endif + PrimEnd = TRUE + OutputBufferedVertex + endif + PrimEnd = FALSE + PrimStart = TRUE + + +2.5.8 VertexCacheLookup +The VertexIndex value is used as the tag value for the VertexCache (see Vertex Cacheabove). If the +Vertex Cache is enabled and the VertexIndex value hits in the cache, the VUE handle is read from the +cache and inserted into the vertex stream. It is marked with a VCHit boolean to surpress processing +(shading) in the VS unit. +Otherwise, for Vertex Cache misses, a VUE handle is obtained to provide storage for the generated +vertex data. VertexLoop processing then proceeds to iterate through the VEs to generate the destination +VUE data. + + +2.5.9 VertexElementLoop +The VertexElementLoop generates and stores vertex data in the destination VUE one VE at a time. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 96 + 2.5.10 SourceElementFetch +The following assumes the VE requires data from a VB, which is the typical case. In the case that the VE +is completely comprised of constant and/or auto-generated IDs, the SourceElementFetch and +FormatConversion steps are skipped. +The structure index within the VE’s selected VB is computed as follows: + if (VB is a VERTEXDATA VB) + VBIndex = VertexIndex + else // INSTANCEDATA VB + VBIndex = StartInstanceLocation + if (VB.InstanceDataStepRate > 0) + VBIndex += InstanceID/VB.InstanceDataStepRate + endif +If VBIndex is invalid (i.e., negative or past Max Index), the data returned from the VB fetch is defined to +be zero. Otherwise, the address of the source data required for the VE is then computed and the data is +read from the VB. The amount of data read from the VB is determined by the Source Element Format. + if ( (VBIndex<0) || (VBIndex>VB.MaxIndex) ) + srcData = 0 + else + pSrcData = VB.BufferStartingAddress + (VBIndex * VB.BufferPitch) + + VE.SourceElementOffset + srcData = MemoryRead( pSrcData, VE.SourceElementFormat ) + endif + + + + +2.5.11 Format Conversion +Once the VE source data has been fetched, it is subjected to format conversion. The output of format +conversion is up to 4 32-bit components, each either integer or floating-point (as specified by the Source +Element Format). See Sampler for conversion algorithms. +The following table lists the valid Source Element Format selections, along with the format and +availability of the converted components (if a component is listed as “-“, it cannot be used as source of a +VUE component). Note: This table is a subset of the list of supported surface formats defined in the +Sampler chapter. Please refer to that table as the “master list”. This table is here only to identify the +components available (per format) and their format. + +Source Element Formats supported in VF Unit + + Source Element Converted Component +Surface Format Name Format 0 1 2 3 +R32G32B32A32_FLOAT FLOAT R G B A +R32G32B32A32_SINT SINT R G B A +R32G32B32A32_UINT UINT R G B A + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 97 + Source Element Converted Component +Surface Format Name Format 0 1 2 3 +R32G32B32A32_UNORM FLOAT R G B A +R32G32B32A32_SNORM FLOAT R G B A +R64G64_FLOAT FLOAT R G - - +R32G32B32A32_SSCALED FLOAT R G B A +R32G32B32A32_USCALED FLOAT R G B A +R32G32B32_FLOAT FLOAT R G B - +R32G32B32_SINT SINT R G B - +R32G32B32_UINT UINT R G B - +R32G32B32_UNORM FLOAT R G B - +R32G32B32_SNORM FLOAT R G B - +R32G32B32_SSCALED FLOAT R G B - +R32G32B32_USCALED FLOAT R G B - +R16G16B16A16_UNORM FLOAT R G B A +R16G16B16A16_SNORM FLOAT R G B A +R16G16B16A16_SINT SINT R G B A +R16G16B16A16_UINT UINT R G B A +R16G16B16A16_FLOAT FLOAT R G B A +R32G32_FLOAT FLOAT R G - - +R32G32_SINT SINT R G - - +R32G32_UINT UINT R G - - +R32G32_UNORM FLOAT R G - - +R32G32_SNORM FLOAT R G - - +R64_FLOAT FLOAT R - - - +R16G16B16A16_SSCALED FLOAT R G B A +R16G16B16A16_USCALED FLOAT R G B A +R32G32_SSCALED FLOAT R G - - +R32G32_USCALED FLOAT R G - - +B8G8R8A8_UNORM FLOAT B G R A +R10G10B10A2_UNORM FLOAT R G B A +R10G10B10A2_UINT UINT R G B A +R10G10B10_SNORM_A2_UNORM FLOAT R G B A +R8G8B8A8_UNORM FLOAT R G B A +R8G8B8A8_SNORM FLOAT R G B A +R8G8B8A8_SINT SINT R G B A +R8G8B8A8_UINT UINT R G B A +R16G16_UNORM FLOAT R G - - +R16G16_SNORM FLOAT R G - - +R16G16_SINT SINT R G - - +R16G16_UINT UINT R G - - +R16G16_FLOAT FLOAT R G - - +R11G11B10_FLOAT FLOAT R G B - +R32_SINT SINT R - - - +R32_UINT UINT R - - - +R32_FLOAT FLOAT R - - - +R32_UNORM FLOAT R - - - +R32_SNORM FLOAT R - - - +R10G10B10X2_USCALED FLOAT R G B - +R8G8B8A8_SSCALED FLOAT R G B A +R8G8B8A8_USCALED FLOAT R G B A + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 98 + Source Element Converted Component +Surface Format Name Format 0 1 2 3 +R16G16_SSCALED FLOAT R G - - +R16G16_USCALED FLOAT R G - - +R32_SSCALED FLOAT R - - - +R32_USCALED FLOAT R - - - +R8G8_UNORM FLOAT R G - - +R8G8_SNORM FLOAT R G - - +R8G8_SINT SINT R G - - +R8G8_UINT UINT R G - - +R16_UNORM FLOAT R - - - +R16_SNORM FLOAT R - - - +R16_SINT SINT R - - - +R16_UINT UINT R - - - +R16_FLOAT FLOAT R - - - +R8G8_SSCALED FLOAT R G - - +R8G8_USCALED FLOAT R G - - +R16_SSCALED FLOAT R - - - +R16_USCALED FLOAT R - - - +R8_UNORM FLOAT R - - - +R8_SNORM FLOAT R - - - +R8_SINT SINT R - - - +R8_UINT UINT R - - - +R8_SSCALED FLOAT R - - - +R8_USCALED FLOAT R - - - +R8G8B8_UNORM FLOAT R G B - +R8G8B8_SNORM FLOAT R G B - +R8G8B8_SSCALED FLOAT R G B - +R8G8B8_USCALED FLOAT R G B - +R64G64B64A64_FLOAT FLOAT R G B A +R64G64B64_FLOAT FLOAT R G B A +R16G16B16_FLOAT FLOAT R G B - +R16G16B16_UNORM FLOAT R G B - +R16G16B16_SNORM FLOAT R G B - +R16G16B16_SSCALED FLOAT R G B - +R16G16B16_USCALED FLOAT R G B - + + +2.5.12 DestinationFormatSelection +The Component Select 0..3 bits are then used to select, on a per-component basis, which destination +components will be written and with which value. The supported selections are the converted source +component, VertexID, InstanceID, PrimitiveID, the constants 0 or 1.0f, or nothing +(VFCOMP_NO_STORE). If a converted component is listed as ‘-‘ (not available) in FormatConversion, it +must not be selected (via VFCOMP_STORE_SRC), or an UNPREDICTABLE value will be stored in the +destination component. +The selection process sequences from component 0 to 3. Once a Component Select of +VFCOMP_NO_STORE is encountered, all higher-numbered Component Select settings must also be +programmed as VFCOMP_NO_STORE. It is therefore not permitted to have ‘holes’ in the destination VE. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 99 + 2.5.13 PrimitiveInfoGeneration +A PrimitiveID value and PrimStart boolean need to be associated with the vertex. +If the vertex is either the first vertex of an instance or the first vertex following a ‘cut index’, the vertex is +marked with PrimStart. +PrimitiveID gets incremented such that subsequent per-object processing (i.e., in the GS or SF/WM) will +see an incrementing value associated with each sequential object within an instance. The PrimitiveID +associated with the provoking, non-adjacent vertex of an object is applied to the object. +The following pseudocode describe the logic used in the VertexLoop to compute the PrimitiveID value +associated with the vertex. Recall that PrimitiveID is reset to 0 at the start of each InstanceLoop. + if (PIDCounterS < S[primType]) + PIDCounterS++ + else + if (PIDCounterR < R[primType]) + PIDCounterR++ + else + PrimitiveID++ + PIDCounterR = 0 + endif + endif + +Two counters are employed to control the incrementing of PrimitiveID. The counters are compared +against two corresponding parameters associated with the primitive topology type. +The PIDCounterS is used to ‘skip over’ some number (possibly zero) initial vertices of the primitive +topology. This counter gets reset to 0 after each primitive is terminated. +Then the PIDCounterR is used to periodically increment the PrimitiveID, where the incrementing interval +(vertex count) is topology-specific. +The following table lists the S[] and R[] values associated with each primitive topology type. + +PrimTopologyType S, R PrimitiveID Outputs + 1, 0 0,1,2,3, .. +POINTLIST + + POINTLIST_BF +LINELIST 1, 1 0,0,1,1,2,2,3,3, .. +LINELIST_ADJ 1, 3 0,0,0,0,1,1,1,1,2,2,2,2,3,3,3,3 .. + 2, 0 0,0,1,2,3, .. +LINESTRIP + +LINESTRIP_BF + + LINESTRIP_CONT +LINESTRIP_ADJ 3, 0 + 0,0,1,2,3,.. + + Note: this breaks the usage model (as the initial vertex is the + provoking vertex for the closing line, but it has an invalid + PrimitiveID of 0), but is effectively a don’t care as PrimitiveID is + only required for LINELOOP is an OpenGL-only primitive.) + The LINELOOP topology is converted to LINESTRIP topology + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 100 + PrimTopologyType S, R PrimitiveID Outputs + at the beginning of the 3D pipeline. + 1, 2 0,0,0,1,1,1,2,2,2,3,3,3,.. +TRILIST + + RECTLIST +TRILIST_ADJ 1, 5 0,0,0,0,0,0,1,1,1,1,1,1,2,2,2,2,2,2,.. +TRISTRIP TRISTRIP_REV 3, 0 0,0,0,1,2,3, .. +TRISTRIP_ADJ 5, 1 0,0,0,0,0,0,1,1,2,2,3,3, .. + 3, 0 0,0,0,1,2,3, .. + TRIFAN + TRIFAN_NOSTIPPLE + POLYGON +QUADLIST 1, 3 + 0,0,0,0,1,1,1,1,2,2,2,2,3,3,3,3, .. + + Note: The QUADLIST topology is converted to POLYGON + topology at the beginning of the 3D pipeline. +QUADSTRIP 3, 1 + 0,0,0,0,1,1,2,2,3,3, .. + + Note: The QUADSTRIP topology is converted to POLYGON + topology at the beginning of the 3D pipeline. +PATCHLIST_n 1,n-1 + PATCHLIST_1: 0,1,2,3, .. + + PATCHLIST_2: 0,0,1,1,2,2,3,3 .. and so on. + + + + +2.5.14 URBWrite +The selected destination components are written into the destination VUE starting at Destination Offset +Select. See the description of 3DPRIMITIVE for restrictions on this field. + + +2.5.15 OutputBufferedVertex +In order to accommodate ‘cut’ processing, the VF unit buffers one output vertex. The generation of a new +vertex or the termination of a primitive causes the buffered vertex to be output to the pipeline. + + +2.6 Dangling Vertex Removal +The last functional stage of processing of the 3DPRIMITIVE command is the removal of “dangling” +vertices. This includes the discarding of primitive topologies without enough vertices for a single object +(e.g., a TRISTRIP with only two vertices), as well as the discarding of trailing vertices that do not form a +complete primitive (e.g., the last two vertices of a 5-vertex TRILIST). +This function is best described as a filter operating on the vertex stream emitted from the processing of +the 3DPRIMITIVE. The filter inputs the PrimType, PrimStart and PrimEnd values associated with the +generated vertices. The filter only outputs primitive topologies without dangling vertices. This requires the +filter to (a) be able to buffer some number of vertices, and (b) be able to remove dangling vertices from +the pipeline and dereference the associated VUE handles. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 101 + 2.7 Other Vertex Fetch Functionality + +2.7.1 Statistics Gathering + 3DSTATE_VF_STATISTICS + + +Source: RenderCS +Length Bias: 1 +The VF stage tracks two pipeline statistics, the number of vertices fetched and the number of objects generated. VF +will increment the appropriate counter for each when statistics gathering is enabled by issuing the +3DSTATE_VF_STATISTICS command with the [Statistics Enable] bit set. +DWord Bit Description +0 31:29 Instruction Type + Default Value: 03h GFXPIPE + Format: Opcode + 28:27 Instruction Sub-Type + Format: Opcode + + + + Value Name Project + 1h Pipelined, Single DWord [Default] + 26:24 Instruction Opcode + Default Value: 0h 3DSTATE_VF_STATISTICS + Format: Opcode + GFXPIPE[28:27 = 1h, 26:24 = 0h, 23:16 = 0Bh] (Pipelined, Single DWord) + + 23:16 Instruction Sub-Opcode + Default Value: 0Bh 3DSTATE_VF_STATISTICS + Format: Opcode + GFXPIPE[28:27 = 1h, 26:24 = 0h, 23:16 = 0Bh] (Pipelined, Single DWord) + + 15:1 Reserved + Format: MBZ + 0 Statistics Enable + Format: Enable + If ENABLED, VF will increment the pipeline statistics counters IA_VERTICES_COUNT and + IA_PRIMITIVES_COUNT for each vertex fetched and each object output, respectively, for + 3DPRIMITIVE commands issued subsequently. + If DISABLED, these counters will not be incremented for subsequent 3DPRIMITIVE commands. + + + + +2.7.1.1 Vertices Generated +VF will increment the IA_VERTICES_COUNT Register (see Memory Interface Registers in Volume Ia, +GPU) for each vertex it fetches, even if that vertex comes from a cache rather than directly from a vertex +buffer in memory. Any “dangling” vertices (fetched vertices that are part of an incomplete object) will not +be included. + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 102 + 2.7.1.2 Objects Generated +VF will increment the IA_PRIMITIVES_COUNT Register (see Memory Interface Registers in vol1a +System Overview) for each object (point, line, triangle, or quadrilateral) that it forwards down the pipeline. +Note: For LINELOOP, the last (closing) line object is not counted. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 103 + 3. 3D Pipeline – Vertex Shader (VS) + Stage +3.1 VS Stage Overview +The VS stage of the 3D Pipeline is used to perform processing (“shading”) of vertices after being +assembled and written to the URB by the VF function. The primary function of the VS stage is to pass +vertices that miss in the Vertex Cache to VS threads, and then pass the VS thread-generated vertices +down the pipeline. Vertices that hit in the Vertex Cache are passed down the pipeline unmodified. +When the VS stage is disabled, vertices flow through the unit unmodified (i.e., as written by the VF unit). +Refer to the Common 3D FF Unit Functions subsection in the 3D Overview chapter for a general +description of a 3D pipeline stage, as much of the VS stage operation and control falls under these +“common” functions; i.e., most stage state variables and VS thread payload parameters are described in +3D Overview, and although they are listed here for completeness, that chapter provides the detailed +description of the associated functions. +Refer to this chapter for an overall description of the VS stage, and any exceptions the VS stage exhibits +with respect to common FF unit functions. + + +3.1.1 Vertex Caching +The 3D Pipeline employs a Vertex Cache that is shared between the VF and VS units. (See Vertex Fetch +chapter for additional information). The Vertex Cache may be explicitly DISABLED via the Vertex Cache +Disable bit in VS_STATE. Even when explicitly ENABLED, the VS unit can (by default) implicitly +disable and invalidate the Vertex Cache when it detects one of the following conditions: + 1. Either VertexID or PrimitiveID is selected as part of the vertex data stored in the URB. + 2. Sequential indices are used in the 3DPRIMITIVE command (though this is effectively a don’t + care as there wouldn’t be any hits anyway). +The implicit disable will persist as long as one of these conditions persist. +The Vertex Cache is implicitly invalidated between 3DPRIMITIVE commands and between instances +within a 3DPRIMITIVE command – therefore use of InstanceID in a Vertex Element is not a condition +underwhich the cache is implicitly disabled. +The following table summarizes the modes of operation of the Vertex Cache: + + Vertex Cache VS Function Enable Mode of Operation + + DISABLED (implicitly or explicitly) DISABLED Vertex Cache is not used. VF unit will + assemble all vertices and write them into + the URB entry supplied by the VS unit. VS + unit will pass references to these VUEs + down the pipeline unmodified. + Usage Model: This is an exceptional + condition, only required when the VF- + generated vertices contain InstanceID or + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 104 + Vertex Cache VS Function Enable Mode of Operation + + PrimitiveID and more than one instance is + produced. Otherwise the Vertex Cache + should be enabled. + + + DISABLED ENABLED Vertex Cache is not used. VF unit will + assemble all vertices and write them into + (implicitly or explicitly) + the URB entry supplied by the VS unit. VS + unit will spawn VS threads to process all + vertices, overwriting the input data with + the results. The VS unit pass references + to these VUEs down the pipeline. + Usage Model: This mode is only used + when the VS function is required, but + either (a) the input vertex contains + InstanceID or PrimitiveID and more than + one instance is generated or (b) the VS + kernel produces a side effect (e.g., writes + to a memory buffer) which requires every + vertex to be processed by a VS thread. + + +ENABLED DISABLED Vertex Cache is used to provide reuse of + VF-generated vertices. The VF unit will + check the cache and only process + (assemble/write) vertices that miss in the + cache. In either case, the VS unit will pass + references to vertices (that hit or miss) + down the pipeline without spawning any + VS threads. + + Usage Model: Normal operation when + the VS function is not required. Note that + there may be situations which require the + VS function to be used even when not + explicitly required by the API. E.g., + perspective divide may be required for + clip testing. + +ENABLED ENABLED Vertex Cache is used to provide reuse of + VS-processed vertices. The VF unit will + check the cache and only process + (assemble/write) vertices that miss in the + cache. The VS unit will only process + (shade) the vertices that missed in the + cache. The VS unit sends references to hit + or missed vertices down the pipeline in + the correct order. + + Usage Model: Normal operation when + the VS function is required and use of the + Vertex Cache is permissible. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 105 + 3.2 VS Stage Input +As a stage of the 3D pipeline, the VS stage receives inputs from the previous (VF) stage. Refer to 3D +Overview for an overview of the various types of input to a 3D Pipeline stage. The remainder of this +subsection describes the inputs specific to the VS stage. + + +3.2.1 State +A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall needs to be sent just prior to any +3DSTATE_VS, 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS, +3DSTATE_BINDING_TABLE_POINTER_VS, 3DSTATE_SAMPLER_STATE_POINTER_VS command. +Only one PIPE_CONTROL needs to be sent before any combination of VS associated 3DSTATE. + +3.2.1.1 URB_FENCE +Refer to 3D Overview for a description of how the VS stage processes this command. + +3.2.1.2 3DSTATE_VS + 3DSTATE_VS + + +Source: RenderCS +Length Bias: 2 + Description Project +The state used by VS is defined with this inline state packet. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 10h 3DSTATE_VS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 4h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:6 Kernel Start Pointer + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 106 + 3DSTATE_VS + Format: InstructionBaseOffset[31:6]Kernel + This field specifies the starting location (1st core instruction) of the kernel program run by threads + spawned by this FF unit. It is specified as a 64-byte-granular offset from the Instruction Base Address. + This field is ignored if VS Function Enable is DISABLED. + + 5:0 Reserved + Project: All + Format: MBZ +2 31 Single Vertex Dispatch + Project: All + Format: U1 Enumerated type + + + This field can be used to force single vertex SIMD4x2 VS threads. + Value Name Description Project + 0h Multiple Dual vertex SIMD4x2 thread dispatches are allowed. All + 1h Single Single vertex SIMD4x2 thread dispatches are forced. All + 30 Vector Mask Enable (VME) + Project: All + When SPF=0, VME specifies which mask to use to initialize the initial channel enables. When SPF=1, + VME specifies which mask to use to generate execution channel enables. + Value Name Description Project + 0h Dmask Channels are enabled based on the dispatch mask All + 1h Vmask Channels are enabled based on the vector mask All + 29:27 Sampler Count + Project: All + Specifies how many samplers (in multiples of 4) the vertex shader 0 kernel uses. Used only for + prefetching the associated sampler state entries. This field is ignored if VS Function Enable is + DISABLED. + Value Name Description Project + 0h No Samplers no samplers used All + 1h 1-4 Samplers between 1 and 4 samplers used All + 2h 5-8 Samplers between 5 and 8 samplers used All + 3h 9-12 Samplers between 9 and 12 samplers used All + 4h 13-16 Samplers between 13 and 16 samplers used All + 26 Reserved + Project: All + Format: MBZ + 25:18 Binding Table Entry Count + Project: All + Format: U8 + Specifies how many binding table entries the kernel uses. Used only for prefetching of the binding table + entries and associated surface state. + Note: For kernels using a large number of binding table entries, it may be wise to set this field to zero + to avoid prefetching too many entries and thrashing the state cache. + This field is ignored if VS Function Enable is DISABLED. + Value Name + [0,255] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 107 + 3DSTATE_VS + 17 Reserved + Project: + Format: MBZ + 16 Floating Point Mode + Project: All + Format: U1 enumerated type + + + Specifies the initial floating point mode used by the dispatched thread.This field is ignored if VS + Function Enable is DISABLED. + Value Name Description Project + 0h IEEE-754 Use IEEE-754 Rules All + 1h Alternate Use alternate rules All + 15:14 Reserved + Project: All + Format: MBZ + 13 Illegal Opcode Exception Enable + Project: All + Format: Enable + This bit gets loaded into EU CR0.1[12] (note the bit # difference). See Exceptions and ISA Execution + Environment.This field is ignored if VS Function Enable is DISABLED. + + 12 Reserved + + Format: MBZ + 11:8 Reserved + Format: MBZ + 7 Software Exception Enable + Format: Enable + This bit gets loaded into EU CR0.1[13] (note the bit # difference). See Exceptions and ISA Execution + Environment.This field is ignored if VS Function Enable is DISABLED. + + 6:0 Reserved + Format: MBZ +3 31:10 Scratch Space Base Offset + Project: All + Format: GeneralStateOffset[31:10]ScratchSpace + Specifies the starting location of the scratch space area allocated to this FF unit as a 1K-byte aligned + offset from the General State Base Address. If required, each thread spawned by this FF unit will be + allocated some portion of this space, as specified by Per-Thread Scratch Space. The computed offset + of the thread-specific portion will be passed in the thread payload as Scratch Space Offset. The thread + is expected to utilize “stateless” DataPort read/write requests to access scratch space, where the + DataPort will cause the General State Base Address to be added to the offset passed in the request + header. + This field is ignored if VS Function Enable is DISABLED. + + 9:4 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 108 + 3DSTATE_VS + + Format: MBZ + 3:0 Per-Thread Scratch Space + Project: All + Format: U4 power of 2 Bytes over 1K Bytes + + + Specifies the amount of scratch space to be allocated to each thread spawned by this FF unit. + The driver must allocate enough contiguous scratch space, starting at the Scratch Space Base + Pointer, to ensure that the Maximum Number of Threads can each get Per-Thread Scratch Space size + without exceeding the driver-allocated scratch space. This field is ignored if VS Function Enable is + DISABLED. + Value Name Description + [0,11] indicating [1K Bytes, 2M Bytes] + + + Programming Notes + This amount is available to the kernel for information only. It will be passed verbatim (if not altered by + the kernel) to the Data Port in any scratch space access messages, but the Data Port will ignore it. +4 31:25 Reserved + Project: All + Format: MBZ + 24:20 Dispatch GRF Start Register for URB Data + + Format: U5 + Specifies the starting GRF register number for the URB portion (Constant + Vertices) of the thread + payload. This field is ignored if VS Function Enable is DISABLED. + Value Name Description + [0,31] indicating GRF [R0,R31] + 19:17 Reserved + Project: All + Format: MBZ + 16:11 Vertex URB Entry Read Length + Project: All + Format: U6 + Specifies the number of pairs of 128-bit vertex elements to be passed into the payload for each vertex. + This field is ignored if VS Function Enable is DISABLED. + For SIMD4x2 dispatch, each vertex element requires one GRF of payload data, therefore the number + of GRFs with vertex data will be double the value programmed in this field. + + Value Name + [1,63] + + + Programming Notes + It is UNDEFINED to set this field to 0 indicating no Vertex URB data to be read and passed to the + thread. + 10 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 109 + 3DSTATE_VS + + Format: MBZ + 9:4 Vertex URB Entry Read Offset + Project: All + Format: U6 + Specifies the offset (in 256-bit units) at which Vertex URB data is to be read from the URB before being + included in the thread payload. This offset applies to all Vertex URB entries passed to the thread. This + field is ignored if VS Function Enable is DISABLED. + Value Name + [0,63] + 3:0 Reserved + Project: All + Format: MBZ +5 31:25 Maximum Number of Threads + + Format: U7-1 representing thread count + + + Specifies the maximum number of simultaneous threads allowed to be active. Used to avoid using up + the scratch space. Programming the value of the max threads over the number of threads based off + number of threads supported in the execution units may improve performance since the architecture + allows threads to be buffered between the check for max threads and the actual dispatch into the EU. + Programming the max values to a number less than the number of threads supported in the execution + units may reduce performance. This field is ignored if VS Function Enable is DISABLED. + Value Name Project + [0,127] indicating thread count of [1,128] + [0,35] indicating thread count of [1,36] + 24:23 Reserved + + Format: MBZ + 22:11 Reserved + Project: All + Format: MBZ + 10 Statistics Enable + Project: All + Format: Enable + + + Description Project + If ENABLED, this FF unit will engage in statistics gathering. See the Statistics Gathering + section later in this chapter. If DISABLED, statistics information associated with this FF stage + will be left unchanged. + This field is used even if VS Function Enable is DISABLED. + 9:3 Reserved + Project: All + Format: MBZ + 2 Reserved + Format: MBZ + 1 Vertex Cache Disable + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 110 + 3DSTATE_VS + + Project: All + Format: Disable + This bit controls the operation of the Vertex Cache. This field is always used.If the Vertex Cache is + DISABLED and the VS Function is ENABLED, the Vertex Cache is not used and all incoming vertices + will be passed to VS threads. + If the Vertex Cache is ENABLED and the VS Function is ENABLED, incoming vertices that do not hit + in the Vertex Cache will be passed to VS threads. + If the Vertex Cache is ENABLED and the VS Function is DISABLED, input vertices that miss in the + Vertex Cache will be assembled and written to the URB, though pass thru the VS stage unmodified + (not shaded). + The Vertex Cache is invalidated whenever the Vertex Cache becomes DISABLED , whenever the VS + Function Enable toggles, between 3DPRIMITIVE commands and between instances within a + 3DPRIMITIVE command. + + 0 VS Function Enable + Project: All + Format: Enable + + + Description Project + If ENABLED, VS threads may be spawned to process VF-generated vertices before the + resulting vertices are passed down the pipeline. + If DISABLED, VF-generated vertices will pass thru the VS function and sent down the pipeline + unmodified. The Vertex Cache is still available in this mode, if enabled. + If Statistics Enable is ENABLED, VS_INVOCATION_COUNT will increment by 1 for every + vertex that passes through the VS stage, even if VS Function Enable is DISABLED. + This field is always used. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 111 + 3.2.1.3 3DSTATE_CONSTANT_VS + 3DSTATE_CONSTANT_VS + + +Source: RenderCS +Length Bias: 2 +This command sets pointers to the push constants for VS unit. The constant data pointed to by this command is +loaded into the VS unit’s push constant buffer (PCB). + Programming Notes Project +It is invalid to execute this command more than once between 3D_PRIMITIVE commands. +Constant buffers must be enabled in order from Constant Buffer 0 to Constant Buffer 3 within this command. +For example, it is not allowed to enable Constant Buffer 1 by programming a non-zero value in the VS +Constant Buffer 1 Read Length without a non-zero value in VS Constant Buffer 0 Read Length. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 15h 3DSTATE_CONSTANT_VS + Format: OpCode + 15:8 Reserved + + Format: MBZ + 7:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Project + 5h Excludes DWord (0,1) [Default] +1..6 191:0 Constant Body + Project: + Format: 3DSTATE_CONSTANT(Body) + Following table is the shared portion of the 3DSTATE_CONSTANT command for VS, HS, DS, + and GS + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 112 + 3DSTATE_CONSTANT(Body) + +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +DWord Bit Description +0 31:16 Constant Buffer 1 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 1. +  + If disabled, the Pointer to Constant Buffer 1 must be programmed to zero. + + 15:0 Constant Buffer 0 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes + +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 0. +  + If disabled, the Pointer to Constant Buffer 0 must be programmed to zero. + +1 31:16 Constant Buffer 3 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes + +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 3. +  + If disabled, the Pointer to Constant Buffer 3 must be programmed to zero. + + 15:0 Constant Buffer 2 Read Length + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 113 + 3DSTATE_CONSTANT(Body) + + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 2. +  + If disabled, the Pointer to Constant Buffer 2 must be programmed to zero. + +2 31:5 Pointer to Constant Buffer 0 + Project: All + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 0. The state of INSTPM determines whether the Dynamic State Base Address is added to this + pointer. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Constant Buffer Object Control State + + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for all constant buffers defined in this command. + +3 31:5 Pointer to Constant Buffer 1 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 1. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Reserved + Project: All + Format: MBZ +4 31:5 Pointer to Constant Buffer 2 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 2. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Reserved + Project: All + Format: MBZ +5 31:5 Pointer to Constant Buffer 3 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 3. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 114 + 3DSTATE_CONSTANT(Body) + 4:0 Reserved + + Format: MBZ + + + + 3.2.1.4 3DSTATE_PUSH_CONSTANT_ALLOC_VS + 3DSTATE_PUSH_CONSTANT_ALLOC_VS + + + Source: RenderCS + Length Bias: 2 + This command sets up the URB configuration for VS Push Constant Buffer. + Programming Notes + Programming Restriction: + + + + The sum of the Constant Buffer Offset and the Constant Buffer Size may not exceed the maximum value of the + Constant Buffer Size. + + The sum of the constant length programmed in 3DSTATE_CONSTANT_VS must be equal or smaller then the + size of the allocated space in the URB including the buffering for half cachelines. See Push Constant URB + Allocation section for more details. + + The 3DSTATE_CONSTANT_VS must be reprogrammed prior to the next 3DPRIMITIVE command after + programming the 3DSTATE_PUSH_CONSTANT_ALLOC_VS. + + + DWord Bit Description + 0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h GFXPIPE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 12h 3DSTATE_PUSH_CONSTANT_ALLOC_VS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + + + Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 115 + 3DSTATE_PUSH_CONSTANT_ALLOC_VS + + +1 31:20 Reserved + + Format: MBZ + 19:16 Constant Buffer Offset + + Format: U4 + Specifies the offset of the VS constant buffer into the URB. + Value Name + [0,15] (0KB - 15KB) + 0h 0KB [Default] + 15:5 Reserved + + Format: MBZ + 4:0 Constant Buffer Size + + Format: U5 + Specifies the size of the VS constant buffer. This value will determine the amount of data the command + stream can pre-fetch before the buffer is full. Value of zero is only valid when constants are not + enabled for VS. + Value Name + [0,15] (0KB – 15KB) Increments of 1KB + 0h 0KB [Default] + + + + +3.2.2 Input Vertices +Refer to 3D Overview for a description of the vertex information input to the VS stage. + + +3.3 SIMD4x2 VS Thread Request Generation +This section describes SIMD4x2 thread request generation, which is the only mode available. +The following discussion assumes the VS Function is ENABLED. +When the Vertex Cache is disabled, the VS unit will pass each pair of incoming vertices to a VS thread. +Under certain circumstances (e.g., prior to a state change or pipeline flush) the VS unit will spawn a VS +thread to process a single vertex. Note that, in this case, the “unused” vertex slot will be “disabled” via the +Execution Mask provided by the VS unit to the subsystem as part of the thread dispatch (See ISA doc). +The VS thread will in itself be unaware of the single-vertex case, and therefore a single VS kernel can be +used to process one or two vertices. (The performance of single-vertex processing will roughly equal the +two-vertex case). +When the Vertex Cache is enabled, the VF unit will detect vertices that hit in the cache and mark these +vertices so that they will bypass VS thread processing and be output via a reference to the cached VUE. +The VS unit will keep track of these cache-hit vertices as it proceeds to process cache-miss vertices. The +VS unit guarantees that vertices will exit the unit in the order they are received. This may require the VS +unit to issue single-vertex VS threads to process a cache-miss vertex that has yet to be paired up with +another cache-miss vertex (if this condition is preventing the VS unit from producing any output). + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 116 + 3.3.1 Thread Payload +The following table describes the payload delivered to VS threads. + +VS Thread Payload (SIMD4x2) + +DWord Bit Description +R0.7 31 + 30:0 Reserved +R0.6 31:24 Reserved + 23:0 + Thread ID: This field uniquely identifies this thread within the threads spawned by + this FF unit, over some period of time. + + Format: Reserved for HW Implementation Use. +R0.5 31:10 + Scratch Space Offset: Specifies the of the scratch space allocated to the thread, + specified as a 1KB-granular offset from the General State Base Address. See + Scratch Space Base Offset description in VS_STATE. + + (See 3D Pipeline for further description on scratch space allocation). + + Format = GeneralStateOffset[31:10] + 9.0 Reserved + 8:0 + FFTID: This ID is assigned by the FF unit and used to identify the thread within the + set of outstanding threads spawned by the FF unit. + + + + Format: Reserved for HW Implementation Use. + + + + Format: + + U7 + + + + Range: + + 0-127 +R0.4 31:5 + Binding Table Pointer. Specifies the 32-byte aligned pointer to the Binding Table. + It is specified as an offset from the Surface State Base Address. + + Format = SurfaceStateOffset[31:5] + 4:0 Reserved +R0.3 31:5 + Sampler State Pointer. Specifies the location of the Sampler State Table to be + used by this thread, specified as a 32-byte granular offset from the General State + Base Address or Dynamic State Base Address. + + Format = DynamicStateOffset[31:5] + 4 Reserved + 3:0 + Per Thread Scratch Space: Specifies the amount of scratch space allowed to be + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 117 + DWord Bit Description + used by this thread. The value specifies the power that two will be raised to (over + determine the amount of scratch space). + + (See 3D Pipeline for further description). + + Format = U4 power of two (in excess of 10) + + Range = [0,11] indicating [1K Bytes, 2M Bytes] +R0.2 31:0 Reserved : delivered as zeros (reserved for message header fields) +R0.1 31:16 Reserved + 15:0 + URB Return Handle 1: This is the 64B-aligned URB offset where the EU’s upper + channels (DWords 7:4) results are to be stored. + + If only one vertex is to be processed (shaded) by the thread, this field will + effectively be ignored (no results are stored for these channels, as controlled by + the thread’s Channel Mask). + + (See Generic FF Unit for further description). + + Format: U12 64B-aligned offset +R0.0 31:16 Reserved + 15:0 + URB Return Handle 0: This is the 64B-aligned URB offset where the EU’s lower + channels (DWords 3:0) results are to be stored. + + (See Generic FF Unit for further description). + + Format: U12 64B-aligned offset +[Varies] 255:0 +optional Constant Data (optional) : + + Some amount of constant data (possible none) can be extracted from the push + constant buffer (PCB) and passed to the thread following the R0 Header. The + amount of data provided is defined by the sum of the read lengths in the last + 3DSTATE_CONSTANT_VS command (taking the buffer enables into account). + + The Constant Data arrives in a non-interleaved format. +Varies 255:0 + Vertex Data : Data from (possibly) one or (more typically) two Vertex URB Entries + is passed to the thread in the thread payload. The Vertex URB Entry Read Offset + and Vertex URB Entry Read Length state variables define the regions of the URB + entries that are read from the URB and passed in the thread payload. These SVs + can be used to provide a subset of the URB data as required by SW. + + The vertex data is laid out in the thread header in an interleaved format. The lower + DWords (0-3) of these GRF registers always contain data from a Vertex URB + Entry. The upper DWords (4-7) may contain data from another Vertex URB Entry. + This allows two vertices to be processed (shaded) in parallel SIMD8 fashion. The + VS kernel is not aware of the validity of the upper vertex. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 118 + 3.4 SIMD4x2 VS Thread Execution +This section describes SIMD4x2 thread execution. +A VS kernel (with one exception mentioned below) assumes it is to operate on two vertices in parallel. +Input data is either passed directly in the thread payload (including the input vertex data) or indirectly via +pointers passed in the payload. +Refer to ISA chapters for specifics on writing kernels that operate in SIMD4x2 fashion. +Refer to 3D Pipeline Stage Overview (3D Overview) for information on FF-unit/Thread interactions. +In the (unlikely) event that the VS kernel needs to determine whether it is processing one or two vertices, +the kernel can compare the URB Return Handle 0 and URB Return Handle 1 fields of the thread +payload. These fields will be different if two vertices are being processed, and identical if one vertex is +being processed. An example of when this test may be required is if the kernel outputs some vertex- +dependent results into a memory buffer – without the test the single vertex case might incorrectly output +two sets of results. Note that this is not the case for writing the URB destinations, as the Execution Mask +will prevent the write of an undefined output. +Note: Prior to sending an End Of Thread, the kernel must dispatch a write commit cycle, if there were any +previous writes to memory that had caused no dependency checks. + + +3.4.1 Vertex Output +VS threads must always write the destination URB handles passed in the payload. VS threads are not +permitted to request additional destination handles. Refer to 3D Pipeline Stage Overview (3D Overview) +for details on how destination vertices are written and any required contents/formats. + + +3.4.2 Thread Termination +VS threads must signal thread termination, in all likelihood on the last message output to the URB shared +function. Refer to the ISA doc for details on End-Of-Thread indication. + + +3.5 Primitive Output +The VS unit will produce an output vertex reference for every input vertex reference received from the VF +unit, in the order received. The VS unit simply copies the PrimitiveType, StartPrim, and EndPrim +information associated with input vertices to the output vertices, and does not use this information in any +way. Neither does the VS unit perform any readback of URB data. + + +3.6 Other VS Functions + +3.6.1 Statistics Gathering +The VS stage tracks a single pipeline statistic, the number of times a vertex shader is executed. A vertex +shader is executed for each vertex that is fetched on behalf of a 3DPRIMITIVE command, unless the +shaded results for that vertex are already available in the vertex cache. If the Statistics Enable bit in +VS_STATE is set, the VS_INVOCATION_COUNT Register (see Memory Interface Registers in Volume +Ia, GPU) will be incremented for each vertex that is dispatched to a VS thread. This counter will often + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 119 + need to be incremented by 2 for each thread invoked since 2 vertices are dispatched to one VS thread in +the general case. +When VS Function Enable is DISABLED and Statistics Enable is ENABLED, +VS_INVOCATION_COUNT will increment by one for every vertex that passes through the VS stage, even +though no VS threads are spawned. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 120 + 4. 3D Pipeline – Hull Shader (HS) Stage +4.1 HS Stage Overview +The Hull Shader (HS) stage of the pipeline is used to process patchlist (PATCHLIST_n) topologies in +support of higher-order surface (HOS) tessellaton. If the HS stage is enabled, each incoming patch object +is processed by a possible series of HS threads. The combined output of these threads is a Patch URB +Entry (“patch record”) written to the URB. This patch record is used by subsequent stages (TE, DS) to +complete the HOS tessellation operations. +For SW Tessellation mode, the HS thread can also write tessellated domain point topologies to memory. +The domain point count and starting memory address of the domain points is passed via the Patch +Header in the patch record. +The vertices associated with patchlist primitives are also referred to as “Input Control Points” (ICPs) to +contrast them with any “Output Control Points” the HS threads may write to the patch record. (The +definition and use of OCPs are outside the scope of this document). +The HS stage also performs statistics counting. Incomplete topologies will not reach the HS stage. +The HS, TE and DS stages must be enabled and disabled together. When these stages are disabled, all +topologies (including patchlist topologies) will be simply pass through to the GS stage. When these +stages are enabled, only patchlist topologies should be issued to the pipeline, otherwise behavior is +UNDEFINED. + + +4.2 HS Stage Input + +4.2.1 State + +4.2.1.1 3DSTATE_CONSTANT_HS + 3DSTATE_CONSTANT_HS + + +Source: RenderCS +Length Bias: 2 +This command sets pointers to the push constants for the HS unit. The constant data pointed to by this command is +loaded into the HS unit’s push constant buffer (PCB). + Programming Notes Project +It is invalid to execute this command more than once between 3D_PRIMITIVE commands. +Constant buffers must be enabled in order from Constant Buffer 0 to Constant Buffer 3 within this command. +For example, It is not allowed to enable Constant Buffer 1 by programming a non-zero value in the HS +Constant Buffer 1 Read Length without a non-zero value in HS Constant Buffer 0 Read Length. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 121 + 3DSTATE_CONSTANT_HS + + Default Value: 3h + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 19h 3DSTATE_CONSTANT_HS + Format: OpCode + 15:8 Reserved + + Format: MBZ + 7:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Project + 5h Excludes DWord (0,1) [Default] +1..6 191:0 Constant Body + + Format: 3DSTATE_CONSTANT(Body) + Following table is the shared portion of the 3DSTATE_CONSTANT command for VS, HS, DS, + and GS + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 122 + 4.2.1.2 3DSTATE_PUSH_CONSTANT_ALLOC_HS + 3DSTATE_PUSH_CONSTANT_ALLOC_HS + + Project: All + Source: RenderCS + Length Bias: 2 + This command sets up the URB configuration for HS Push Constant Buffer. + Programming Notes + Programming Restriction: + + + + The sum of the Constant Buffer Offset and the Constant Buffer Size may not exceed the maximum value of the + Constant Buffer Size. + + The sum of the constant length programmed in 3DSTATE_CONSTANT_HS must be equal or smaller then the + size of the allocated space in the URB including the buffering for half cachelines. See Push Constant URB + Allocation section for more details. + + The 3DSTATE_CONSTANT_HS must be reprogrammed prior to the next 3DPRIMITIVE command after + programming the 3DSTATE_PUSH_CONSTANT_ALLOC_HS. + + + DWord Bit Description + 0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h GFXPIPE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 13h 3DSTATE_PUSH_CONSTANT_ALLOC_HS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + + 1 31:20 Reserved + + Format: MBZ + 19:16 Constant Buffer Offset + + + + + Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 123 + 3DSTATE_PUSH_CONSTANT_ALLOC_HS + + Format: U5 + Specifies the offset of the HS constant buffer into the URB. + Value Name + [0,15] (0KB - 15KB) + 0h 0KB [Default] + 15:5 Reserved + + Format: MBZ + 4:0 Constant Buffer Size + + Format: U5 + Specifies the size of the HS constant buffer. This value will determine the amount of data the + command stream can pre-fetch before the buffer is full. Value of zero is only valid when constants are + not enabled for HS. + Value Name + [0,15] (0KB – 15KB) Increments of 1KB + 0h 0KB [Default] + + + + +4.3 3DSTATE_CONSTANT_HS + 3DSTATE_CONSTANT_HS + + +Source: RenderCS +Length Bias: 2 +This command sets pointers to the push constants for the HS unit. The constant data pointed to by this command is +loaded into the HS unit’s push constant buffer (PCB). + Programming Notes Project +It is invalid to execute this command more than once between 3D_PRIMITIVE commands. +Constant buffers must be enabled in order from Constant Buffer 0 to Constant Buffer 3 within this command. +For example, It is not allowed to enable Constant Buffer 1 by programming a non-zero value in the HS +Constant Buffer 1 Read Length without a non-zero value in HS Constant Buffer 0 Read Length. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 19h 3DSTATE_CONSTANT_HS + Format: OpCode + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 124 + 3DSTATE_CONSTANT_HS + 15:8 Reserved + + Format: MBZ + 7:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Project + 5h Excludes DWord (0,1) [Default] +1..6 191:0 Constant Body + + Format: 3DSTATE_CONSTANT(Body) + Following table is the shared portion of the 3DSTATE_CONSTANT command for VS, HS, DS, + and GS + + + + + 3DSTATE_CONSTANT(Body) + +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +DWord Bit Description +0 31:16 Constant Buffer 1 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 1. +  + If disabled, the Pointer to Constant Buffer 1 must be programmed to zero. + + 15:0 Constant Buffer 0 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 125 + 3DSTATE_CONSTANT(Body) + +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 0. +  + If disabled, the Pointer to Constant Buffer 0 must be programmed to zero. + +1 31:16 Constant Buffer 3 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes + +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 3. +  + If disabled, the Pointer to Constant Buffer 3 must be programmed to zero. + + 15:0 Constant Buffer 2 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 2. +  + If disabled, the Pointer to Constant Buffer 2 must be programmed to zero. + +2 31:5 Pointer to Constant Buffer 0 + Project: All + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 0. The state of INSTPM determines whether the Dynamic State Base Address is added to this + pointer. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Constant Buffer Object Control State + + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for all constant buffers defined in this command. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 126 + 3DSTATE_CONSTANT(Body) +3 31:5 Pointer to Constant Buffer 1 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 1. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Reserved + Project: All + Format: MBZ +4 31:5 Pointer to Constant Buffer 2 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 2. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Reserved + Project: All + Format: MBZ +5 31:5 Pointer to Constant Buffer 3 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 3. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Reserved + + Format: MBZ + + + + +4.4 3DSTATE_HS +The state used by HS is defined with the following 3DSTATE_HS inline state packet. + + 3DSTATE_HS + + +Source: RenderCS +Length Bias: 2 +Controls the HS stage hardware. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 127 + 3DSTATE_HS + + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 1Bh 3DSTATE_HS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Format: =n + + + + Value Name Project + 5 Excludes DWord (0,1) [Default] +1 31:30 Reserved + Project: All + Format: MBZ + 29:27 Sampler Count + Project: All + Format: U3 + Specifies how many samplers (in multiples of 4) the HS kernels use. Used only for prefetching the + associated sampler state entries. + Value Name Description Project + 0h No Samplers no samplers used All + 1h 1-4 Samplers between 1 and 4 samplers used All + 2h 5-8 Samplers between 5 and 8 samplers used All + 3h 9-12 Samplers between 9 and 12 samplers used All + 4h 13-16 Samplers between 13 and 16 samplers used All + 5h-7h Reserved Reserved All + 26 Reserved + Project: All + Format: MBZ + 25:18 Binding Table Entry Count + Project: All + Format: U8 + When HW Generated Binding Table is disabled: + Specifies how many binding table entries the kernel uses. Used only for prefetching of the binding + table entries and associated surface state. + Note: For kernels using a large number of binding table entries, it may be wise to set this field to zero + to avoid prefetching too many entries and thrashing the state cache. + + 17 Reserved + + Format: MBZ + 16 Floating Point Mode + Project: All + Specifies the initial floating point mode used by the dispatched thread. + Value Name Description Project + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 128 + 3DSTATE_HS + + 0h IEEE-754 Use IEEE-754 Rules All + 1h alternate Use alternate rules All + 15:14 Reserved + Project: All + Format: MBZ + 13 Illegal Opcode Exception Enable + Project: All + Format: Enable + This bit gets loaded into EU CR0.1[12] (note the bit # difference). See Exceptions and ISA Execution + Environment. + + 12 Reserved + + Format: MBZ + 11:8 Reserved + Project: All + Format: MBZ + 7 Software Exception Enable + + Format: Enable + This bit gets loaded into EU CR0.1[13] (note the bit # difference). See Exceptions and ISA Execution + Environment. + + 6:0 Maximum Number of Threads + + Format: U7-1 thread count + + + Specifies the maximum number of simultaneous threads allowed to be active. Used to avoid using up + the scratch space. Programming the value of the max threads over the number of threads based off + number of threads supported in the execution units may improve performance since the architecture + allows threads to be buffered between the check for max threads and the actual dispatch into the EU. + Programming the max values to a number less than the number of threads supported in the execution + units may reduce performance. Limit is based on max number of HS URB handles. + Value Name Project + [0,127] indicating a thread count of [1,128] + [0,35] indicating a thread count of [1,36] + + + Programming Notes + A URB_FENCE command must be issued subsequent to any change to the value in this field and + before any subsequent pipeline processing (e.g., via 3DPRIMITIVE or CONSTANT_BUFFER). See + Graphics Processing Engine (Command Ordering Rules) +2 31 HS Enable + Project: All + Format: Enable + Specifies whether the HS function is enabled or disabled (pass-through). If ENABLED + MI_TOPOLOGY_FILTER must be used to silently discard any topologies that the HS kernel is not + expecting. E.g., if the HS kernel is expecting PATCHLIST_32 topologies, MI_TOPOLOGY_FILTER + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 129 + 3DSTATE_HS + must be set to PATCHLIST_32 so only those topologies can reach the enabled HS. + Programming Notes + The tessellation stages (HS, TE and DS) must be enabled/disabled as a group. I.e., draw commands + can only be issued if all three stages are enabled or all three stages are disabled, otherwise the + behavior is UNDEFINED. + 30 Reserved + Project: All + Format: MBZ + 29 HS Statistics Enable + Project: All + Format: Enable + This bit controls whether HS-unit-specific statistics register(s) will increment (for each patch). + Value Name Description Project + 0h Disable HS_INVOCATIONS_COUNT will not increment + 1h Enable HS_INVOCATIONS_COUNT will increment + 28:18 Reserved + Project: All + Format: MBZ + 16:8 Reserved + + Format: MBZ + 7:4 Reserved + Project: All + Format: MBZ + 3:0 Instance Count + Project: All + Format: U4-1 + This field determines the number of threads (minus one) spawned per input patch. + If the HS kernel uses a barrier function, software must restrict the Instance Count to the number of + threads that can be simultaneously active within a half-slice. Factors which must be considered + includes scratch memory availability. + Value Name Description + [0,15] representing [1,16] instances +3 31:6 Kernel Start Pointer + Project: All + Format: InstructionBaseOffset[31:6]Kernel + This field specifies the starting location (1st GEN core instruction) of the kernel program run by threads + spawned by this FF unit. It is specified as a 64-byte-granular offset from the Instruction Base Address. + + 5:0 Reserved + Project: All + Format: MBZ +4 31:10 Scratch Space Base Pointer + + Format: GeneralStateOffset[31:10] + Format: GraphicsAddress[31:0] + Specifies the location of the scratch space area allocated to this FF unit, specified as a 1KB-granular + offset from the General State Base Address. If required, each thread spawned by this FF unit will be + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 130 + 3DSTATE_HS + allocated some portion of this space, as specified by Per-Thread Scratch Space. + + 9:4 Reserved + + Format: MBZ + 3:0 Per-Thread Scratch Space + + Format: U4 power of 2 Bytes over 1K Bytes + + + Specifies the amount of scratch space to be allocated to each thread spawned by this FF unit.The + driver must allocate enough contiguous scratch space, starting at the Scratch Space Base Pointer, to + ensure that the Maximum Number of Threads can each get Per-Thread Scratch Space size without + exceeding the driver-allocated scratch space. + Value Name + [0,11] indicating [1K Bytes, 2M Bytes] +5 31:28 Reserved + + Format: MBZ + 27 Single Program Flow (SPF) + + Specifies the initial condition of the kernel program as either a single program flow (SIMDnxm with m = + 1) or as multiple program flows (SIMDnxm with m > 1). See CR0 description in ISA Execution + Environment. + Value Name Description Project + 0h Reserved All + 1h Enable Single Program Flow enabled All + 26 Vector Mask Enable + + Format: U1 FormatDesc: Enumerated Type + + + When SPF=0, VME specifies which mask to use to initialize the initial channel enables. When SPF=1, + VME specifies which mask to use to generate execution channel enables. + Value Name Description Project + 0h Dmask Channels are enabled based on the dispatch mask All + 1h Vmask Channels are enabled based on the vector mask All + 25 Reserved + + Format: MBZ + 24 Include Vertex Handles + + Format: Boolean + If set, all the input Vertex URB handles are included in payloads. This field is ignored if HS Function + Enable is DISABLED.Programming Restriction:This field must be set if value if Vertex URB Entry Read + Length is cleared to zero. + + 23:19 Dispatch GRF Start Register for URB Data + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 131 + 3DSTATE_HS + + + Format: U5 + Specifies the starting GRF register number for the URB portion (Constant + Vertices) of the thread + payload. This field is ignored if HS Function Enable is DISABLED. + Value Name + [0,31] indicating GRF [R0,R31] + 18:17 Reserved + + Format: MBZ + 16:11 Vertex URB Entry Read Length + + Format: U6 + Specifies the amount of URB data read and passed in the thread payload for each Vertex URB entry, in + 256-bit register increments.This field is ignored if HS Function Enable is DISABLED.Programming + Restriction:This field must be a non-zero value if Include Vertex Handles is cleared to zero. + Value Name + [0,63] + 10 Reserved + + Format: MBZ + 9:4 Vertex URB Entry Read Offset + + Format: U6 + Specifies the offset (in 256-bit units) at which Vertex URB data is to be read from the URB before being + included in the thread payload. This offset applies to all Vertex URB entries passed to the thread.This + field is ignored if HS Function Enable is DISABLED. + Value Name + [0,63] + 3:0 Reserved + + Format: MBZ +6 31:13 Reserved + Project: All + Format: MBZ + 12 Reserved + + Format: MBZ + 11:0 Semaphore Handle + + Format: URBOffset[17:6] + This is the URB offset pointing to the first of the GS semaphore DWords in the URB. The size of the + region is 32 DWs(16 – 512b URB entries). Software is responsible for allocating combined GS and/or + HS semaphore Dwords in a single contiguous region of the URB. Software must also make sure the 3D + pipeline is IDLE prior to allocating or deallocating the region. The semaphores can be located in an + unused area within a FF unit’s URB fenced region or an unused area within the Push Constant region. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 132 + 4.5 Patch Object Staging +The HS unit accepts patchlist topologies as a stream of incoming vertices. Depending on the number of +vertices per patch object (as specified by the PATCHLIST_n topology), the HS thread will assemble each +complete patch object and pass it (its vertices, PrimitiveID, etc.) to HS thread(s) as described below. + + +4.6 HS Thread Payload + +4.6.1 SINGLE_PATCH Layout (SINGLE-PATCH Mode) +The following tables show the layout of the payload delivered to HS threads. Refer to 3D Pipeline Stage +Overview (3D Pipeline) for details on those fields that are common amongst the various pipeline stages. +Patch object vertex (ICP) data can be passed by value (data pushed in the payload) and/or by reference +(URB handle pushed in the payload). + +SINGLE_PATCH HS Thread Payload + + GRF +DWord Bit Description +R0:7 31:0 Reserved + 31 +R0.6 Dereference Thread + This bit is defined to send back the Handle ID back to HS to dereference the input handles for + this thread. + 30:24 Reserved + 23:0 + Thread ID. This field uniquely identifies this thread within the threads spawned by this FF unit, + over some period of time. + Format: Reserved for HW Implementation Use. + 31:10 +R0.5 Scratch Space Pointer. Specifies the location of the scratch space allocated to this thread, + specified as a 1KB-aligned offset from the General State Base Address. + Format = GeneralStateOffset[31:10] + 9.0 Reserved + 8:0 + FFTID. This ID is assigned by the fixed function unit and is relative identifier for the thread. It is + used to free up resources used by the thread upon thread completion. + Format: Reserved for Implementation Use + Format: + U7 + Range: + 0-127 + + 31:5 +R0.4 Binding Table Pointer: Specifies the 32-byte aligned pointer to the Binding Table. It is + specified as an offset from the Surface State Base Address. + Format = SurfaceStateOffset[31:5] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 133 + GRF + DWord Bit Description + 4:0 Reserved + 31:5 +R0.3 Sampler State Pointer. Specifies the location of the Sampler State Table to be used by this + thread, specified as a 32-byte granular offset from the General State Base Address or + Dynamic State Base Address. + Format = DynamicStateOffset[31:5] + 4 Reserved + 3:0 + Per Thread Scratch Space. Specifies the amount of scratch space allowed to be used by + this thread. The value specifies the power that two will be raised to (over determine the amount + of scratch space). + Programming Notes: + This amount is available to the kernel for information only. It will be passed verbatim (if not + altered by the kernel) to the Data Port in any scratch space access messages, but the Data Port + will ignore it. + Format = U4 power of two (in excess of 10) + Range = [0,11] indicating [1K Bytes, 2M Bytes] + 31:24 +R0.2 Semaphore Index. This is a Dword index to be used in URB_ATOMIC commands if the + thread is using data pulled from input handles. This information is only required for pull-model + vertex inputs and InstanceCount>1. + Format = U8 + 23 Reserved + 22:16 + Instance Number. A patch-relative instance number between 0 and InstanceCount-1. + Format = U7 + 15:12 + Barrier Index. This index is to be used in any BarrierMsgs sent by this thread to the Gateway. + Format = U4 + 11:0 + Semaphore Handle: This is the URB handle pointing to the first HS semaphore DWord in the + URB. Software is responsible for statically allocating the semaphore Dwords in the URB. Refer + to Semaphore Handle field in 3DSTATE_HS for size of semaphore allocation. + Format: U12 64B-aligned URB Offset +R0.1 31:0 + Primitive ID. This field contains the Primitive ID associated with the patch. + Format: U32 + 31:16 Reserved +R0.0 + 15:0 + Patch Data Record URB Return Handle. + Format: + U12 64B-aligned URB Offset + +R1 is only included for dispatches that have Include Vertex Handles enabled. + 31:16 ICP 7 Handle ID + R1.7 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 134 + GRF +DWord Bit Description + 15:0 + ICP 7 Handle + Format: + + 31:16 ICP 6 Handle ID +R1.6 + 15:0 ICP 6 Handle + 31:16 ICP 5 Handle ID + R1.5 + 15:0 ICP 5 Handle +R1.4 31:16 ICP 4 Handle ID + 15:0 ICP 4 Handle +R1.3 31:16 ICP 3 Handle ID + 15:0 ICP 3 Handle +R1.2 31:16 ICP 2 Handle ID + 15:0 ICP 2 Handle +R1.1 31:16 ICP 1 Handle ID + 15:0 ICP 1 Handle +R1.0 31:16 ICP 0 Handle ID + 15:0 ICP 0 Handle +R2 is only included for dispatches that have Include Vertex Handles enabled and when ICP Count >7 +R2.7 31:16 ICP 15 Handle ID + 15:0 ICP 15 Handle +R2.6 31:16 ICP 14 Handle ID + 15:0 ICP 14 Handle +R2.5 31:16 ICP 13 Handle ID + 15:0 ICP 13 Handle +R2.4 31:16 ICP 12 Handle ID + 15:0 ICP 12 Handle +R2.3 31:16 ICP 11 Handle ID + 15:0 ICP 11 Handle +R2.2 31:16 ICP 10 Handle ID + 15:0 ICP 10 Handle +R2.1 31:16 ICP 9 Handle ID + 15:0 ICP 9 Handle +R2.0 31:16 ICP 8 Handle ID + 15:0 ICP 8 Handle +R3 is only included for dispatches that have Include Vertex Handles enabled and when ICP Count >15 +R3.7 31:16 ICP 23 Handle ID + 15:0 ICP 23 Handle +R3.6 31:16 ICP 22 Handle ID + 15:0 ICP 22 Handle +R3.5 31:16 ICP 21 Handle ID + 15:0 ICP 21 Handle +R3.4 31:16 ICP 20 Handle ID + 15:0 ICP 20 Handle +R3.3 31:16 ICP 19 Handle ID + 15:0 ICP 19 Handle +R3.2 31:16 ICP 18 Handle ID + 15:0 ICP 18 Handle +R3.1 31:16 ICP 17 Handle ID + 15:0 ICP 17 Handle + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 135 + GRF + DWord Bit Description +R3.0 31:16 ICP 16 Handle ID + 15:0 ICP 16 Handle +R4 is only included for dispatches that have Include Vertex Handles enabled and when ICP Count >23 +R4.7 31:16 ICP 31 Handle ID + 15:0 ICP 31 Handle +R4.6 31:16 ICP 30 Handle ID + 15:0 ICP 30 Handle +R4.5 31:16 ICP 29 Handle ID + 15:0 ICP 29 Handle +R4.4 31:16 ICP 28 Handle ID + 15:0 ICP 28 Handle +R4.3 31:16 ICP 27 Handle ID + 15:0 ICP 27 Handle +R4.2 31:16 ICP 26 Handle ID + 15:0 ICP 26 Handle +R4.1 31:16 ICP 25 Handle ID + 15:0 ICP 25 Handle +R4.0 31:16 ICP 24 Handle ID + 15:0 ICP 24 Handle +[Varies] 255:0 + Constant Data (optional): +optional + Some amount of constant data (possible none) can be extracted from the push constant buffer + (PCB) and passed to the thread following the R0 Header. The amount of data provided is + defined by the sum of the read lengths in the last 3DSTATE_CONSTANT_HS command (taking + the buffer enables into account). + +[Varies] 255:0 + ICP Vertex Data (optional): There can be up to 32 vertices supplied, each with a size defined +optional + by the Vertex URB Entry Read Length state. + Vertex 0 DWord 0 is located at Rn.0, Vertex 0 DWord 1 is located at Rn.1, etc. Vertex 1 DWord + 0 immediately follows the last DWord of Vertex 0, and so on. + + + +4.7 HS Thread Execution +Input to HS threads is comprised of: + +  Input Control Points (incoming patch vertices), pushed into the payload and/or passed + indirectly via URB handles. +  Push Constants (common to all threads) +  Patch Data handle +  Resources available via binding table entries (accessed through shared functions) +  Miscellaneous payload fields (Instance Number, etc.) + +Typically the only output of the HS threads is the Patch URB Entry (patch record). All thread instances for +an input patch are passed the same patch record handle. As the (possibly concurrent) threads can both +read and write the patch record, it is up to the kernels to ensure deterministic results. One approach +would be to use the thread’s Instance Number as an index for URB write destinations. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 136 + 4.7.1 Dispatch Mask +HS threads will be dispatched with the dispatch mask set to 0xFFFF. It is the responsibility of the kernel to +modify the execution mask as required (e.g., if operating in SIMD4x2 mode but only the lower half is +active, as would happen in one thread is the threads were computing an odd number of OCPs via +SIMD4x2 operation). + + +4.8 ICP Dereferencing +If ICPs are only pushed in HS payloads (i.e., the Include Vertex Handles state bit is clear), the ICP +handles will automatically be released after the last instance for the patch is dispatched. +If Include Vertex Handles is set (the HS thread(s) will be reading ICP data in from the URB, it is the +responsibility of the HS thread instances to explicitly dereference all the ICP handles via use of the +Complete bit in URB_READ_xxx commands. + +  If only one instance is used, that instance can dereference the ICP handles as soon as they are no + longer needed, by setting Complete in the last URB_READ from that handle. Otherwise all (or the + remaining) ICP handles need to be explicitly dereferenced via (possibly null-response-length) + URB_READ commands prior to thread EOT. +  If more than one instance is spawned, the last-terminating instance is responsible for dereferencing + all the ICP handles before it terminates. Instances can detect that they are the last-terminating + thread via use of the semaphore allocated to the patch (via the Semaphore Handle and + Semaphore Index payload fields). A URB_ATOMIC_INC operation (URB_ATOMIC command) can + be performed on this semaphore by each instance prior to terminating. Only the last-terminating + thread will observe the value (InstanceCount – 1) as a return value. After dereferencing all the ICPs, + the last-terminating thread must also reset the semaphore to 0 via the URB_ATOMIC_MOV + operation. + + +4.9 Patch URB Entry (Patch Record) Output +For each patch, the HS thread(s) generate a single patch record, starting with a fixed 32B Patch Header . +When the final thread instance terminates, the patch record handle is passed down the pipeline to the +Tessellation Engine (TE). + + +4.9.1 Patch Header +The first 8 DWords of the patch record is defined as a “Patch Header”. The Patch Header is written by an +HS thread and read by the TE stage. It normally contains up to six Tessellation Factors (TFs) that +determine how finely the TE stage needs to tessellate a domain (if at all). In SW Tessellation mode, the +header contains Domain Point Count and Domain Point Buffer Starting Address fields which identify +the domain points generated by an HS thread. The following diagram shows the fixed layouts of the Patch +Header, depending on DomainType and SW Tessellation Mode. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 137 + Patch Header (QUAD Domain) + +DW +ord Bits Description + 7 31:0 + UEQ0 Tessellation Factor + Format: FLOAT32 + 6 31:0 + VEQ0 Tessellation Factor + Format: FLOAT32 + 5 31:0 + UEQ1 Tessellation Factor + Format: FLOAT32 + 4 31:0 + VEQ1 Tessellation Factor + Format: FLOAT32 + + 3 31:0 + Inside U Tessellation Factor + Format: FLOAT32 + 2 31:0 + Inside V Tessellation Factor + Format: FLOAT32 + 1-0 31:0 Reserved : MBZ + +Patch Header (TRI Domain) + +DW Bit +ord s Description + 7 31:0 + UEQ0 Tessellation Factor + Format: FLOAT32 + + 6 31:0 + VEQ0 Tessellation Factor + Format: FLOAT32 + 5 31:0 + WEQ0 Tessellation Factor + Format: FLOAT32 + 4 31:0 + Inside Tessellation Factor + Format: FLOAT32 + 3-0 31:0 Reserved : MBZ + +Patch Header (ISOLINE Domain) + +DW Bit +ord s Description + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 138 + DW Bit +ord s Description + 7 31:0 + Line Detail Tessellation Factor + Format: FLOAT32 + + 6 31:0 + Line Density Tessellation Factor + Format: FLOAT32 + 5-0 31:0 Reserved : MBZ + +Patch Header (SW Tessellation Mode) + +DW Bit +ord s Description + 7 31:0 + Domain Point Count + Specifies the number of DOMAIN_POINT structures in the domain point list in memory. If 0, there + are no domain points defined, the patch will considered “culled”, and the TE stage will discard the + patch. Otherwise the TS stage will send this number of domain points down the pipeline. + Format: U32 + 6 31:6 + Domain Point Buffer Starting Address (DPBSA) + This field specifies the starting memory offset from SW Tessellation Base Address (set by the + SWTESS_BASE_ADDRESS command) at which the HS thread has written a list of + DOMAIN_POINT structures. This field is ignored if Domain Point Count is 0. + Format: 64B-aligned offset from SW Tessellation Base Address + 5:0 Reserved : MBZ + 5-0 31:0 Reserved: MBZ + + +4.9.2 DOMAIN_POINT Structure +In SW Tessellation Mode (i.e., when the TE State is SW_TESS), the TE stage will read a sequence of +DOMAIN_POINT structures from memory, starting at the Domain Point Buffer Starting Address field of +the patch header. (The DPBSA is treated as an offset from the SW Tessellation Base Address as set by +the SWTESS_BASE_ADDRESS command). + +DOMAIN_POINT Memory Structure (SW Tessellation) + + +DW +ord Bit Description + 0 31 + PrimStart + Set on the first domain point of the topology (e.g., first vertex in a TRISTRIP). + 30 + PrimEnd + Set on the last domain point of the topology (e.g., last vertex in a TRISTRIP). + Programming note: Software must ensure that incomplete primitives are not output, or + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 139 + DW +ord Bit Description + behavior is UNDEFINED. + + 29 + PatchEnd + Set on the last domain point for the patch. By definition, PrimEnd must also be set. + Programming Note: Software must ensure that the Domain Point Count coincides with the + domain point marked with PatchEnd. + + 28:24 + PrimType + This is the primitive topology type. + Format: See 3DPRIMITIVE for encodings + Valid values:POINTLIST, LINESTRIP, LINELIST, TRISTRIP, TRISTRIP_REV, TRILIST, + TRIFAN. + 23:19 + Reserved + 18:17 + DS Tag [16:15] + This field provides bits [16:15] of the DS Tag value for this domain point. See DS Tag [14:0]. + Format: U2 + 16:0 + U Coordinate + Format: U1.16 + 1 31:17 + DS Tag [14:0] + This field provides bits [14:0] of the DS Tag value for this domain point. + In order to utilize the DS cache, the 17-bit DS Tag must be unique for the associated U,V + coordinate. If software cannot guarantee this, the DS cache must be disabled when in SW + Tessellation mode. + Format: U15 + + 16:0 + V Coordinate + Format: U1.16 + + + +4.10 Statistics Gathering + +4.10.1 HS Invocations +The HS unit controls the HS_INVOCATIONS counter, which counts the number of patches processed by +the HS stage. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 140 + 5. 3D Pipeline – Tessellation Engine (TE) +When enabled, the Tessellation Engine (TE) stage performs fixed-function domain tessellation +(decomposition into smaller objects) of incoming patches, as referenced by an HS-generated input PDR +handle and as controlled by TE state and Tessellation Factors (TFs) read from the Patch URB Entry +(patch record). The TE stage is entirely fixed-function and does not spawn threads. +The TE stage can also operate in SW Tessellation mode, where it simply reads “pre-tessellated” domain +point topologies from memory and passes them down the pipeline. +The fixed-function tessellation algorithm is considered an implementation detail and is therefore beyond +the scope of this document. That detail includes both the order of output topologies as well as the order of +vertices (domain points) within the output topologies. Only a high-level overview is provided to describe +how the (few) state variables can be used to control aspects of tessellation behavior. The implementation +will generate deterministic results (given the same exact inputs it will produce exactly the same outputs). +Several domain types (QUAD, TRI, and ISOLINE) are supported. Depending on the domain type, the TE +stage outputs the required point/line/triangle topologies including a domain point per vertex. These +topologies will be output to the DS stage, where the domain points will be converted to 3D object vertices, +resulting in 3D objects as typically input to the 3D pipeline when HOS tessellation is not used. +The HS, TE, and DS stages must be enabled and disabled together. When these stages are disabled, all +topologies (including patchlist topologies) simply pass through to the GS stage. When these stages are +enabled, only patchlist topologies should be issued to the pipeline, else behavior is UNDEFINED. The +MI_TOPOLOGY_FILTER command can be used to ensure this happens, i.e., it can be used to have the +Command Stream ignore 3DPRIMITIVE commands that do not match a specific topology type. + + +5.1 3DSTATE_TE + 3DSTATE_TE + + +Source: RenderCS +Length Bias: 2 +The state used by TE is defined with this inline state packet. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 1Ch 3DSTATE_TE + Format: OpCode + 15:8 Reserved + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 141 + 3DSTATE_TE + + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 2h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:14 Reserved + Project: All + Format: MBZ + 13:12 Partitioning + Project: All + Format: U2 + This field specifies how edges are partitioned based on tessellation factor. + Value Name Description Project + 0h INTEGER Outside/inside edges are divided into an integer number of All + equal-sized segments. + 1h ODD_FRACTIONAL Outside/inside edges are divided into an odd number of All + possibly-unequal-sized segments. + 2h EVEN_FRACTIONAL Outside/inside edges are divided into an even number of All + possibly-unequal-sized segments. + 11:10 Reserved + Project: All + Format: MBZ + 9:8 Output Topology + Project: All + Format: U2 + This field specifies which primitive types are to be output. + Value Name Description Project + 0h POINT Points are output (as POINTLIST topologies) All + 1h LINE Lines are output (as LINESTRIP topologies). Only valid if ISOLINE All + domain is selected. + 2h TRI_CW Clockwise-ordered triangles are output (either as TRISTRIP, All + TRISTRIP_REV or TRILIST topologies). Not valid if ISOLINE domain + is selected. + 3h TRI_CCW Count-clockwise-ordered triangles are output (either as TRISTRIP, All + TRISTRIP_REV or TRILIST topologies). Not valid if ISOLINE domain + is selected. + 7:6 Reserved + Project: All + Format: MBZ + 5:4 Domain + Project: All + Format: U2 + This field specifies which type of domain is to be tessellated. + Value Name Description Project + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 142 + 3DSTATE_TE + + 0h QUAD 2D (U,V) domain is tessellated All + 1h TRI Triangular (U,V,W) domain is tessellated All + 2h ISOLINE 2D (U,V) domain is tessellated. All + 3 Reserved + Project: All + Format: MBZ + 2:1 TE Mode + Project: All + Format: U2 + When TE Enable is ENABLED, this field specifies the overall operation of the TE stage.This field is + ignored if TE Enable is DISABLED. + Value Name Description Project + 0h HW_TESS Normal HW Tessellation Mode. The TessFactors are read from the All + patch URB entry, and are used to perform fixed-function hardware + tessellation of the specified domain. + 1h SW_TESS Software Tessellation Mode. The TE unit will pass down HS-thread- All + generated tessellated domain points instead of generating them itself + from TessFactors. The TE unit will read the Domain Point Count and + Domain Point Buffer Starting Address fields from the patch header, + and if the count is 0 it will consider the patch culled and discard it. + Otherwise the address is used to start fetching DOMAIN_POINT + structures from memory and passing them down the pipeline to DS. + 0 TE Enable + Project: All + Format: Enable + If ENABLED, the TE stage will perform tessellation processing on incoming patch primitives. The TE + Mode field determines how this tessellation operation proceeds.If DISABLED, the TE goes into pass- + through mode. All other state fields are ignored. + Programming Notes + The tessellation stages (HS, TE and DS) must be enabled/disabled as a group. I.e., draw commands + can only be issued if all three stages are enabled or all three stages are disabled, otherwise the + behavior is UNDEFINED. +2 31:0 Max TessFactor Odd + Project: All + Format: FLOAT32 + This field specifies the maximum TessFactor for ODD_FRACTIONAL partitioning when in HW_TESS + mode. + Note that ISOLINE’s LineDensity TF is always subjected to INTEGER partitioning regardless + of the Partitioning state.For normal operation (as per API spec) software should set this + value to 63.0. + +3 31:0 Max TessFactor Not Odd + Project: All + Format: FLOAT32 + This field specifies the maximum TessFactor for EVEN_FRACTIONAL or INTEGER partitioning when + in HW_TESS mode. + Note that ISOLINE’s LineDensity TF is always subjected to INTEGER partitioning regardless + of the Partitioning state.For normal operation (as per API spec) software should set this value to + 64.0. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 143 + 5.2 Domain Types and Output Topologies +The major (if only) task of the TE stage is to tessellate a 2D (u,v) domain region—as selected by the +Domain state—into some number of 2D object topologies. (If the patch is culled, that number may be +zero). The options for Domain state are as follows: + +  QUAD: A square 2D region within a u,v Cartesian (rectanguar) space. The region extends from the + origin to u=1 and v=1. Within the region, tessellation domain locations are determined. The possible + output topologies include points, clockwise triangles, and counter-clockwise triangles. +  TRI: A triangular 2D region with u,v,w barycentric (areal) coordinates. The three edges correspond + to u=0, v=0, and w=0 boundaries. In barycentric coordinates, w = 1 – u – v, therefore points within + the region are fully defined as 2D (u,v) coordinates. Within the region, tessellation domain locations + are determined. The possible output topologies include points, clockwise triangles, and counter- + clockwise triangles. +  ISOLINE: A series of points within a QUAD domain, where the points lie on lines parallel to the u + axis and extending from [0,1) in the v direction. Either the segmented lines (linestrips) or individual + point topologies can be output. + + +5.3 QUAD Domain Tessellation +The four “outside” TFs (TF.UEQ0, TF.VEQ0, TF.UEQ1, TF.VEQ1) are used to specify the level of +tessellation along the four corresponding edges of the 2D quad domain. The two “inside” TFs +(TF.InsideU, TF.InsideV) are used to determine the level of tessellation within a 2D “interior” region. +Typically the interior region appears as a “regularly-tessellated 2D grid”, however under certain conditions +the interior region may collapse in which case only the outside TFs are relevant. +In general, a transition region exists between each edge of the interior region and the corresponding +outside edge. The topologies generated for these regions effectively “stitch together” locations along the +outside and inside edges, as each of these edges can contain a different number of tessellated +segments. In the case where all TFs in a given direction (e.g., TF.VEQ0, TF.InsideU, and TF.VEQ1) are +the same value, it appears as if the regularly-tessellated interior region extends all the way to the outside +edges. If this condition simultaneously exists for both u and v directions, the entire domain will appear to +be tessellated into a regular grid, with no noticeable transition regions. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 144 + QUAD Domain + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 145 + 5.3.1 TRI Domain Tessellation +Tessellation of the TRI domain is similar to the QUAD domain, except only three outside edges/TFs are +used, and the tessellation of the interior region is controlled by a single TF. + +TRI Domain + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 146 + 5.4 ISOLINE Domain Tessellation +Tessellation of the ISOLINE domain is different but much simpler than QUAD and TRI domains. The +TF.LineDetail TF controls how finely the U direction is tessellated, while the TF.LineDensity TF controls +how finely the V direction is tessellated. When LINE output topology is selected, a series of segmented +lines parallel to the U axis (constant V) are output. When POINT output topology is selected, only the line +segment endpoints are output (as point objects). In either case there is no topology output for the V=1 +edge, which avoids overlapping lines for adjacent patches. + +ISOLINE Domain + + + + +5.5 Patch Culling +Normally, if any “outside” TF is <= 0.0 or NaN, the entire patch is culled at the TE stage. +Inside TFs are not used to cull patches. +In SW Tessellation mode, a Domain Point Count of 0 indicates that a patch is to be culled. + + +5.6 Tessellation Factor Limits +MinTessFactor and MaxTessFactor state variables are used to perform a floating-point range clamp on +the TessFactors. +See TE_STATE for programming details. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 147 + 5.7 Partitioning +The Partitioning state controls how the TFs are used to divide their corresponding edges. + +  INTEGER: The edge will be divided into an integral number of equal segments (given some fixed- + point tolerance). +After clamping, the TF is rounded up to an integer value. The edge will be divided into that many equal segments. +  EVEN_FRACTIONAL: The edge will be divided into an even number of possibly-unequal segments. + The total number of segments is determined by rounding up the post-clamped TF to an even + number. +More specifically, the edge is divided exactly in half. Like the endpoints of the edge, the midpoint of the edge is by +definition a tessellation point. Each half will contain some number of equal segments and possibly one smaller +segment. The size of the smaller segment is determined by the position of the TF value within the range defined by +the TF rounded down and up to even numbers. The closer the TF is to the smaller value, the smaller the segment +size is. When the TF reaches the smaller even value, the smaller segment disappears. The closer the TF gets to the +larger even value, the closer the smaller segment size approaches the size of the other segments. When the TF +reaches the larger even value, all segments will be equal. The position of the smaller segment along the half edge +varies as a function of the TF value. +  ODD_FRACTIONAL: The edge will be divided into an odd number of possibly-unequal segments. + The tessellation scheme is very similar to EVEN_FRACTIONAL partitioning, except the edge + midpoint is not included as a tessellation point. This, and the fact that the tessellation points are + mirrored about the edge midpoint, causes an “odd” segment (which may or may not be the “smaller” + segment) to straddle the edge midpoint, therefore resulting in the number of segments for the edge + always being odd. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 148 + 6. 3D Pipeline – Domain Shader (DS) + Stage +The DS stage is very similar to the VS stage in that it is responsible for dispatching EU threads to shade +vertices and maintaining a cache (with reference counts) of the shaded vertex outputs of these threads. +Major differences are as follows: + +  The DS receives topologies with “domain points” instead of vertices. The only data specific to a + domain point are its U,V coordinates. These coordinates (plus a default or computed W coordinate) + are passed directly in the DS thread payload. There is no other vertex-specific “input vertex data” +  The concatenation of the domain point U,V coordinates (vs. a vertex index) is used as the cache tag. +  The cache is invalidated between patches. + +The DS stage accepts state information via the inline 3DSTATE_DS command. + + +6.1 3DSTATE_DS + 3DSTATE_DS + + +Source: RenderCS +Length Bias: 2 +The state used by DS is defined with this inline state packet +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 1Dh 3DSTATE_DS + Format: OpCode + 15:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 4h Excludes DWord (0,1) + + Format: =n Total Length - 2 + + + +1 31:6 Kernel Start Pointer + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 149 + 3DSTATE_DS + Format: InstructionBaseOffset[31:6]Kernel + This field specifies the starting location of the kernel program run by threads spawned by this FF unit. + It is specified as a 64-byte-granular offset from the Instruction Base Address. + This field is ignored if DS Function Enable is DISABLED. + + 5:0 Reserved + Project: All + Format: MBZ +2 31 Single Domain Point Dispatch + + Format: U1 Enumerated Type + + + This field can be used to force single domain point SIMD4x2 DS threads. + Value Name Description + 0h Multiple Dual domain point SIMD4x2 thread dispatches are allowed. + 1h Single Single domain point SIMD4x2 thread dispatches are forced. + 30 Vector Mask Enable (VME) + + Format: U1 Enumerated Type + + + When SPF=0, VME specifies which mask to use to initialize the initial channel enables. When SPF=1, + VME specifies which mask to use to generate execution channel enables. + Value Name Description Project + 0h Dmask Channels are enabled based on the dispatch mask + 1h Vmask Channels are enabled based on the vector mask + 29:27 Sampler Count + + Format: U3 + Specifies how many samplers (in multiples of 4) the kernel uses. Used only for prefetching the + associated sampler state entries. + This field is ignored if DS Function Enable is DISABLED. + Value Name Description Project + 0h No Samplers no samplers used All + 1h 1-4 Samplers between 1 and 4 samplers used All + 2h 5-8 Samplers between 5 and 8 samplers used All + 3h 9-12 Samplers between 9 and 12 samplers used All + 4h 13-16 Samplers between 13 and 16 samplers used All + 26 Reserved + + Format: MBZ + 25:18 Binding Table Entry Count + + Format: U8 + When HW Generated Binding Table is disabled: + Specifies how many binding table entries the kernel uses. Used only for prefetching of the binding + table entries and associated surface state. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 150 + 3DSTATE_DS + Note:For kernels using a large number of binding table entries, it may be wise to set this field to zero + to avoid prefetching too many entries and thrashing the state cache. + This field is ignored if DS Function Enable is DISABLED. + Value Name + [0,255] + 17 Reserved + + Format: MBZ + 16 Floating Point Mode + + Format: U1 Enumerated Type + + + Specifies the initial floating point mode used by the dispatched thread.This field is ignored if DS + Function Enable is DISABLED. + Value Name Description + 0h IEEE-754 Use IEEE-754 Rules + 1h Alternate Use alternate rules + 15 Reserved + + Format: MBZ + 14 Reserved + + Format: MBZ + 13 Illegal Opcode Exception Enable + + Format: Enable + This bit gets loaded into EU CR0.1[12] (note the bit # difference). See Exceptions and ISA Execution + Environment.This field is ignored if DS Function Enable is DISABLED. + + 12:8 Reserved + + Format: MBZ + 7 Software Exception Enable + + Format: Enable + This bit gets loaded into EU CR0.1[13] (note the bit # difference). See Exceptions and ISA Execution + Environment. + This field is ignored if DS Function Enable is DISABLED. + + 6:0 Reserved + + Format: MBZ +3 31:10 Scratch Space Base Offset + + Format: GeneralStateOffset[31:10]ScratchSpace + Specifies the starting location of the scratch space area allocated to this FF unit as a 1K-byte aligned + offset from the General State Base Address. If required, each thread spawned by this FF unit will be + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 151 + 3DSTATE_DS + allocated some portion of this space, as specified by Per-Thread Scratch Space. The computed offset + of the thread-specific portion will be passed in the thread payload as Scratch Space Offset. The thread + is expected to utilize “stateless” DataPort read/write requests to access scratch space, where the + DataPort will cause the General State Base Address to be added to the offset passed in the request + header.This field is ignored if DS Function Enable is DISABLED. + + 9:4 Reserved + + Format: MBZ + 3:0 Per-Thread Scratch Space + + Format: U4 power of 2 Bytes over 1K Bytes + + + Specifies the amount of scratch space to be allocated to each thread spawned by this FF unit.The + driver must allocate enough contiguous scratch space, starting at the Scratch Space Base Pointer, to + ensure that the Maximum Number of Threads can each get Per-Thread Scratch Space size without + exceeding the driver-allocated scratch space. + This field is ignored if DS Function Enable is DISABLED. + Value Name + [0,11] indicating [1K Bytes, 2M Bytes] + + + Programming Notes + This amount is available to the kernel for information only. It will be passed verbatim (if not altered by + the kernel) to the Data Port in any scratch space access messages, but the Data Port will ignore it. +4 31:25 Reserved + + Format: MBZ + 24:20 Dispatch GRF Start Register for URB Data + + Format: U5 + Specifies the starting GRF register number for the URB portion (Constant + Vertices) of the thread + payload. This field is ignored if DS Function Enable is DISABLED. + Value Name + [0,31] indicating GRF [R0,R31] + 19:18 Reserved + + Format: MBZ + 17:11 Patch URB Entry Read Length + + Format: U7 + Specifies how much data (in 256-bit units) is to be read from the Patch URB entry and passed in the + DS thread payload. This field is ignored if DS Function Enable is DISABLED. + Value Name + [0, 64] + 10 Reserved + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 152 + 3DSTATE_DS + + Format: MBZ + 9:4 Patch URB Entry Read Offset + + Specifies the offset (in 256-bit units) at which Patch URB data is to be read from the URB before being + included in the thread payload. + This field is ignored if DS Function Enable is DISABLED. + Value Name + [0, 63] + 3:0 Reserved + + Format: MBZ +5 31:25 Maximum Number of Threads + + Format: U7-1 Thread Count + + + s Specifies the maximum number of simultaneous DS threads allowed to be active. Used to avoid + using up the scratch space. Programming the value of the max threads over the number of threads + based off number of threads supported in the execution units may improve performance since the + architecture allows threads to be buffered between the check for max threads and the actual dispatch + into the EU. Programming the max values to a number less than the number of threads supported in + the execution units may reduce performance. + This field is ignored if DS Function Enable is DISABLED. + Value Name Description Project + [0,127] indicating thread count of [1,128] + [0,35] indicating thread count of [1,36] + 24:21 Reserved + + Format: MBZ + 20:11 Reserved + + + 10 Statistics Enable + + Format: Enable + If ENABLED, this FF unit will engage in statistics gathering. If DISABLED, statistics information + associated with this FF stage will be left unchanged. This field is ignored if DS Function Enable is + DISABLED. + + 9:3 Reserved + + + 2 Compute W Coordinate Enable + + Format: Enable + If ENABLED, the DS unit will (for each domain point) compute W = 1 – (U + V) and pass the result as a + floating point value in the DS thread payload. If DISABLED, 0.0 will be passed. This field must only be + ENABLED for the tessellation of TRI domains, where UVW coordinates are required. This field must be + DISABLED for other domains (as they only require UV coordinates) otherwise the computed W + coordinate is UNDEFINED. This field is ignored if DS Function Enable is DISABLED. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 153 + 3DSTATE_DS + + + 1 DS Cache Disable + Project: + Format: Disable + This bit controls the operation of the DS Cache. This field is ignored if DS Function Enable is + DISABLED. + If the DS Cache is DISABLED and the DS Function is ENABLED, the DS Cache is not used and all + incoming domain points will be passed to DS threads. + If the DS Cache is ENABLED and the DS Function is ENABLED, incoming domain points that do not + hit in the DS Cache will be passed to DS threads. The DS Cache is invalidated whenever the DS + Cache becomes DISABLED , whenever the DS Function Enable toggles, and between patches. + + 0 DS Function Enable + + Format: Enable + If ENABLED, DS threads will be spawned to process incoming domain points which miss in the DS + cache. + If DISABLED, the DS stage goes into pass-through mode and performs no specific processing. + This field is always used. + Programming Notes + The tessellation stages (HS, TE and DS) must be enabled/disabled as a group. I.e., draw commands + can only be issued if all three stages are enabled or all three stages are disabled, otherwise the + behavior is UNDEFINED. + + + + + 6.1.1 3DSTATE_PUSH_CONSTANT_ALLOC_DS + 3DSTATE_PUSH_CONSTANT_ALLOC_DS + + + Source: RenderCS + Length Bias: 2 + This command sets up the URB configuration for DS Push Constant Buffer. + Programming Notes + Programming Restriction: + + + + The sum of the Constant Buffer Offset and the Constant Buffer Size may not exceed the maximum value of the + Constant Buffer Size. + + The sum of the constant length programmed in 3DSTATE_CONSTANT_DS must be equal or smaller then the + size of the allocated space in the URB including the buffering for half cachelines. See Push Constant URB + Allocation section for more details. + + The 3DSTATE_CONSTANT_DS must be reprogrammed prior to the next 3DPRIMITIVE command after + programming the 3DSTATE_PUSH_CONSTANT_ALLOC_DS. + + + DWord Bit Description + 0 31:29 Command Type + + + + Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 154 + 3DSTATE_PUSH_CONSTANT_ALLOC_DS + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h GFXPIPE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 14h 3DSTATE_PUSH_CONSTANT_ALLOC_DS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:20 Reserved + + Format: MBZ + 19:16 Constant Buffer Offset + + Format: U4 + Specifies the offset of the DS constant buffer into the URB. + Value Name + [0,15] (0KB - 15KB) + 0h 0KB [Default] + 15:5 Reserved + + Format: MBZ + 4:0 Constant Buffer Size + + Format: U5 + Specifies the size of the DS constant buffer. This value will determine the amount of data the + command stream can pre-fetch before the buffer is full. Value of zero is only valid when constants are + not enabled for DS. + Value Name + [0,15] (0KB – 15KB) Increments of 1KB + 0h 0KB [Default] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 155 + 6.1.2 3DSTATE_CONSTANT_DS + 3DSTATE_CONSTANT_DS + + +Source: RenderCS +Length Bias: 2 +This command sets pointers to the push constants for the DS unit. The constant data pointed to by this command is +loaded into the DS unit’s push constant buffer (PCB). + Programming Notes Project +It is invalid to execute this command more than once between 3D_PRIMITIVE commands. +Constant buffers must be enabled in order from Constant Buffer 0 to Constant Buffer 3 within this command. +For example, It is not allowed to enable Constant Buffer 1 by programming a non-zero value in the DS +Constant Buffer 1 Read Length without a non-zero value in DS Constant Buffer 0 Read Length. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 1Ah 3DSTATE_CONSTANT_DS + Format: OpCode + 15:8 Reserved + + Format: MBZ + 7:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Project + 5h Excludes DWord (0,1) [Default] +1..6 191:0 Constant Body + + Format: 3DSTATE_CONSTANT(Body) + Following table is the shared portion of the 3DSTATE_CONSTANT command for VS, HS, DS, + and GS + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 156 + 3DSTATE_CONSTANT(Body) + +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +DWord Bit Description +0 31:16 Constant Buffer 1 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 1. +  + If disabled, the Pointer to Constant Buffer 1 must be programmed to zero. + + 15:0 Constant Buffer 0 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 0. +  + If disabled, the Pointer to Constant Buffer 0 must be programmed to zero. + +1 31:16 Constant Buffer 3 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes + +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 3. +  + If disabled, the Pointer to Constant Buffer 3 must be programmed to zero. + + 15:0 Constant Buffer 2 Read Length + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 157 + 3DSTATE_CONSTANT(Body) + + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 2. +  + If disabled, the Pointer to Constant Buffer 2 must be programmed to zero. + +2 31:5 Pointer to Constant Buffer 0 + Project: All + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 0. The state of INSTPM determines whether the Dynamic State Base Address is added to this + pointer. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Constant Buffer Object Control State + + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for all constant buffers defined in this command. + +3 31:5 Pointer to Constant Buffer 1 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 1. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Reserved + Project: All + Format: MBZ +4 31:5 Pointer to Constant Buffer 2 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 2. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Reserved + Project: All + Format: MBZ +5 31:5 Pointer to Constant Buffer 3 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 3. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 158 + 3DSTATE_CONSTANT(Body) + 4:0 Reserved + + Format: MBZ + + + + +6.2 Thread Payload +The following tables describe the payload delivered to DS threads. + +DS Thread Payload (SIMD4x2) + +DWord Bit Description +R0.7 31 + Snapshot Flag + 30:0 Reserved +R0.6 31:24 Reserved + 23:0 + Thread ID: This field uniquely identifies this thread within the threads spawned by this FF unit, + over some period of time. + Format: Reserved for HW Implementation Use. + +R0.5 31:10 + Scratch Space Offset: Specifies the of the scratch space allocated to the thread, specified as + a 1KB-granular offset from the General State Base Address. See Scratch Space Base + Offset description in VS_STATE. + (See 3D Pipeline for further description on scratch space allocation). + Format = GeneralStateOffset[31:10] + 9.0 Reserved + 8:0 + FFTID: This ID is assigned by the FF unit and used to identify the thread within the set of + outstanding threads spawned by the FF unit. + Format: Reserved for HW Implementation Use. + Format: + U9 +R0.4 31:5 + Binding Table Pointer. Specifies the 32-byte aligned pointer to the Binding Table. It is + specified as an offset from the Surface State Base Address. + Format = SurfaceStateOffset[31:5] + 4:0 Reserved +R0.3 31:5 + Sampler State Pointer. Specifies the location of the Sampler State Table to be used by this + thread, specified as a 32-byte granular offset from the General State Base Address or + Dynamic State Base Address. + Format = DynamicStateOffset[31:5] + + 4 Reserved + 3:0 + Per Thread Scratch Space: Specifies the amount of scratch space allowed to be used by this + thread. The value specifies the power that two will be raised to (over determine the amount of + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 159 + DWord Bit Description + scratch space). + Format = U4 power of two (in excess of 10) + Range = [0,11] indicating [1K Bytes, 2M Bytes] +R0.2 31:0 Reserved : delivered as zeros (reserved for message header fields) +R0.1 31:26 Reserved + 25:16 + Handle ID 1: This ID is assigned by the FF unit and used to identify the URB Return Handle 1 + to the FF unit (as FF-specific index value, not a URB address). + If only one vertex is to be processed (shaded) by the thread, this field will effectively be ignored + (no results are stored for these channels, as controlled by the thread’s Channel Mask). + Format = Reserved for HW Implementation Use. + 15:14 Reserved + 13:0 + URB Return Handle 1: This is the URB handle where Vertex 1 data (the EU’s upper channels + (DWords 7:4)) results are to be stored. + If only one vertex is to be processed (shaded) by the thread, this field will effectively be ignored + (no results are stored for these channels, as controlled by the thread’s Channel Mask). + Format: + U12 handle (512-bit granular); Bit 13:12 Reserved + +R0.0 31:26 Reserved + 25:16 + Handle ID 0: This ID is assigned by the FF unit and used to identify the URB Return Handle 0 + to the FF unit (as FF-specific index value, not a URB address). + Format = Reserved for HW Implementation Use. + + 15:14 Reserved + 13:0 + URB Return Handle 0: This is the URB handle where Vertex 0 data (the EU’s lower channels + (DWords 3:0)) results are to be stored. + Format: + U12 handle (512-bit granular); Bit 13:12 Reserved +R1.7 31:0 + PrimitiveID: This is the 32-bit PrimitiveID value associated with the patch. It is common to all + output vertices resulting from the tessellation of the patch. + Format: U32 +R1.6 31:0 + Domain Point 1 W Coordinate: (See Domain Point 0 W Coordinate) + Format: FLOAT32 +R1.5 31:0 + Domain Point 1 V Coordinate: (See Domain Point 0 V Coordinate) + Format: FLOAT32 +R1.4 31:0 + Domain Point 1 U Coordinate: (See Domain Point 0 U Coordinate) + Format: FLOAT32 +R1.3 31:14 Reserved + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 160 + DWord Bit Description + 13:0 + Patch URB Handle: This is the URB handle of the Patch Record (common to both vertices). + Format: + U12 handle; Bit 13:12 Reserved +R1.2 31:0 + Domain Point 0 W Coordinate: If Compute W Coordinate Enable is set, this field will + receive the computed value (1 – U – V) for Domain Point 0. Otherwise it is passed as 0.0. + Format: FLOAT32 +R1.1 31:0 + Domain Point 0 V Coordinate: V coordinate associated with Domain Point 0. + Format: FLOAT32 +R1.0 31:0 + Domain Point 0 U Coordinate: U coordinate associated with Domain Point 0. + Format: FLOAT32 +Varies 255:0 + Constant Data (optional) : +[Optional] + Some amount of constant data (possible none) can be extracted from the push constant buffer + (PCB) and passed to the thread following the R0 Header. The amount of data provided is defined + by the sum of the read lengths in the last 3DSTATE_CONSTANT_DS command (taking the + buffer enables into account). + The Constant Data arrives in a non-interleaved format. + + 255:0 + Varies Patch URB Data (optional): Some amount of Patch Data (possible none) can be extracted + from the URB and passed to the thread in this location in the payload. The amount of data + [Optional] + provided is defined by the Patch URB Entry Read Length state (3DSTATE_DS) + The Patch Data arrives in a non-interleaved format. + + +DS Thread Payload (SIMD8) + +DWord Bit Description +R0.7 31 + Snapshot Flag + 30:0 Reserved +R0.6 31:24 Reserved + 23:0 + Thread ID: This field uniquely identifies this thread within the threads spawned by this FF unit, + over some period of time. + Format: Reserved for HW Implementation Use. +R0.5 31:10 + Scratch Space Offset: Specifies the of the scratch space allocated to the thread, specified as a + 1KB-granular offset from the General State Base Address. See Scratch Space Base Offset + description in VS_STATE. + (See 3D Pipeline for further description on scratch space allocation). + Format = GeneralStateOffset[31:10] + + 9.0 Reserved + 8:0 + FFTID: This ID is assigned by the FF unit and used to identify the thread within the set of + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 161 + DWord Bit Description + outstanding threads spawned by the FF unit. + Format: Reserved for HW Implementation Use. + Format: + U9 +R0.4 31:5 + Binding Table Pointer. Specifies the 32-byte aligned pointer to the Binding Table. It is specified as + an offset from the Surface State Base Address. + Format = SurfaceStateOffset[31:5] + 4:0 Reserved +R0.3 31:5 + Sampler State Pointer. Specifies the location of the Sampler State Table to be used by this + thread, specified as a 32-byte granular offset from the General State Base Address or Dynamic + State Base Address. + Format = DynamicStateOffset[31:5] + + 4 Reserved + 3:0 + Per Thread Scratch Space: Specifies the amount of scratch space allowed to be used by this + thread. The value specifies the power that two will be raised to (over determine the amount of + scratch space). + Format = U4 power of two (in excess of 10) + Range = [0,11] indicating [1K Bytes, 2M Bytes] +R0.2 31:0 Reserved : delivered as zeros (reserved for message header fields) +R0.1 31:0 + PrimitiveID: This is the 32-bit PrimitiveID value associated with the patch. It is common to all + output domain points resulting from the tessellation of the patch. + Format: U32 +R0.0 31:27 Reserved + 26:16 + Patch Handle ID: This ID is assigned by the FF unit and used to identify the patch URB entry to + the FF unit (as FF-specific index value, not a URB address). + Format = Reserved for HW Implementation Use. + 15:0 + Patch URB Offset: This is the offset within the URB where the patch data is stored. + Format: U14 64B-granular offset into the URB + +R1.7 31:0 Domain Point 7 U Coordinate. (See Domain Point 0 U Coordinate) +R1.6 31:0 Domain Point 6 U Coordinate. (See Domain Point 0 U Coordinate) +R1.5 31:0 Domain Point 5 U Coordinate. (See Domain Point 0 U Coordinate) +R1.4 31:0 Domain Point 4 U Coordinate. (See Domain Point 0 U Coordinate) +R1.3 31:0 Domain Point 3 U Coordinate. (See Domain Point 0 U Coordinate) +R1.2 31:0 Domain Point 2 U Coordinate. (See Domain Point 0 U Coordinate) +R1.1 31:0 Domain Point 1 U Coordinate. (See Domain Point 0 U Coordinate) +R1.0 31:0 + Domain Point 0 U Coordinate: U coordinate associated with Domain Point 0. + Format: FLOAT32 +R2.7 31:0 Domain Point 7 V Coordinate. (See Domain Point 0 V Coordinate) +R2.6 31:0 Domain Point 6 V Coordinate. (See Domain Point 0 V Coordinate) +R2.5 31:0 Domain Point 5 V Coordinate. (See Domain Point 0 V Coordinate) + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 162 + DWord Bit Description +R2.4 31:0 Domain Point 4 V Coordinate. (See Domain Point 0 V Coordinate) +R2.3 31:0 Domain Point 3 V Coordinate. (See Domain Point 0 V Coordinate) +R2.2 31:0 Domain Point 2 V Coordinate. (See Domain Point 0 V Coordinate) +R2.1 31:0 Domain Point 1 V Coordinate. (See Domain Point 0 V Coordinate) +R2.0 31:0 + Domain Point 0 V Coordinate: V coordinate associated with Domain Point 0. + Format: FLOAT32 +R3.7 31:0 Domain Point 7 W Coordinate. (See Domain Point 0 W Coordinate) +R3.6 31:0 Domain Point 6 W Coordinate. (See Domain Point 0 W Coordinate) +R3.5 31:0 Domain Point 5 W Coordinate. (See Domain Point 0 W Coordinate) +R3.4 31:0 Domain Point 4 W Coordinate. (See Domain Point 0 W Coordinate) +R3.3 31:0 Domain Point 3 W Coordinate. (See Domain Point 0 W Coordinate) +R3.2 31:0 Domain Point 2 W Coordinate. (See Domain Point 0 W Coordinate) +R3.1 31:0 Domain Point 1 W Coordinate. (See Domain Point 0 W Coordinate) +R3.0 31:0 + Domain Point 0 W Coordinate: If Compute W Coordinate Enable is set, this field will receive the + computed value (1 – U – V) for Domain Point 0. Otherwise it is passed as 0.0. + Format: FLOAT32 + +R4.7 31:0 Domain Point 7 URB Return Handle (see R4.0) +R4.6 31:0 Domain Point 6 URB Return Handle (see R4.0) +R4.5 31:0 Domain Point 5 URB Return Handle (see R4.0) +R4.4 31:0 Domain Point 4 URB Return Handle (see R4.0) +R4.3 31:0 Domain Point 3 URB Return Handle (see R4.0) +R4.2 31:0 Domain Point 2 URB Return Handle (see R4.0) +R4.1 31:0 Domain Point 1 URB Return Handle (see R4.0) +R4.0 31:16 Reserved + 15:0 + Domain Point 0 URB Return Handle: This is the offset within the URB where domain point 0 is to + be stored. + Format: U14 64B-granular offset into the URB +Varies 255:0 + Constant Data (optional) : +[Optional] + Some amount of constant data (possible none) can be extracted from the push constant buffer + (PCB) and passed to the thread following the R0 Header. The amount of data provided is defined + by the sum of the read lengths in the last 3DSTATE_CONSTANT_DS command (taking the + buffer enables into account). + 255:0 + Varies Patch URB Data (optional): + [Optional] Some amount of Patch Data (possible none) can be extracted from the URB and passed to the + thread in this location in the payload. The amount of data provided is defined by the Patch URB + Entry Read Length state (3DSTATE_DS) + + + + +6.3 DS Thread Execution +A DS kernel assumes it is to operate on two domain points in parallel using the EU’s SIMD4x2 execution +model . Refer to ISA chapters for specifics on writing kernels that operate in SIMD4x2 fashion. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 163 + DS threads must always write the destination URB handles passed in the payload. DS threads are not +permitted to request additional destination handles. Refer to 3D Pipeline Stage Overview ( 3D Overview) for +details on how destination vertices are written and any required contents/formats. +DS threads must signal thread termination on the last message output to the URB shared function. + + +6.4 Statistics Gathering +The DS stage maintains the DS_INVOCATIONS statistics counter, which counts the number of incoming +domain points, irrespective of cache hit/miss. Note that this is different than VS_INVOCATIONS, which +counts shader invocations and therefore doesn’t count cache hits. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 164 + 7. 3D Pipeline – Geometry Shader (GS) + Stage +7.1 GS Stage Overview +The GS stage of the 3D Pipeline is used to convert objects within incoming primitives into new primitives +through use of a spawned thread. When enabled, the GS unit buffers incoming vertices, assembles the +vertices of each individual object within the primitives, and passes these object vertices (along with other +data) to the subsystem for processing by a GS thread. +When the GS stage is disabled, vertices flow through the unit unmodified. +Refer to the Common 3D FF Unit Functions subsection in the 3D Pipeline chapter for a general +description of a 3D Pipeline stage, as much of the GS stage operation and control falls under these +“common” functions; i.e., most stage state variables and GS thread payload parameters are described in +3D Pipeline, and although they are listed here for completeness, that chapter provides the detailed +description of the associated functions. +Refer to this chapter for an overall description of the GS stage, and any exceptions the GS stage exhibits +with respect to common FF unit functions. + + +7.2 GS Stage Input +As a stage of the 3D pipeline, the GS stage receives inputs from the previous ( DS) stage. Refer to 3D +Pipeline for an overview of the various types of input to a 3D Pipeline stage. The remainder of this +subsection describes the inputs specific to the GS stage. + + +7.2.1 State + +7.2.1.1 3DSTATE_GS +The state used by GS is defined with this inline state packet. + + 3DSTATE_GS + + +Source: RenderCS +Length Bias: 2 +Controls the GS stage hardware. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 165 + 3DSTATE_GS + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 11h 3DSTATE_GS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 5h Excludes DWord (0,1) + Format: =n +1 31:6 Kernel Start Pointer + Project: All + Format: InstructionBaseOffset[31:6]Kernel + This field specifies the starting location (1st core instruction) of the kernel program run by threads + spawned by this FF unit. It is specified as a 64-byte-granular offset from the Instruction Base Address. + + 5:0 Reserved + Project: All + Format: MBZ +2 31 Single Program Flow (SPF) + Project: All + Specifies the initial condition of the kernel program as either a single program flow (SIMDnxm with m = + 1) or as multiple program flows (SIMDnxm with m > 1). See CR0 description in ISA Execution + Environment. + Value Name Description + 0h Disable Single Program Flow disabled + 1h Enable Single Program Flow enabled + 30 Vector Mask Enable (VME) + Project: All + Format: U1 enumerated type + + + When SPF=0, VME specifies which mask to use to initialize the initial channel enables. When SPF=1, + VME specifies which mask to use to generate execution channel enables. + Value Name Description + 0h Dmask Channels are enabled based on the dispatch mask + 1h Vmask Channels are enabled based on the vector mask + 29:27 Sampler Count + Project: All + Format: U3 + Specifies how many samplers (in multiples of 4) the geometry shader kernel uses. Used only for + prefetching the associated sampler state entries. + Value Name Description + 0h No Samplers no samplers used + 1h 1-4 Samplers between 1 and 4 samplers used + 2h 5-8 Samplers between 5 and 8 samplers used + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 166 + 3DSTATE_GS + + 3h 9-12 Samplers between 9 and 12 samplers used + 4h 13-16 Samplers between 13 and 16 samplers used + 5h-7h Reserved Reserved + 26 Reserved + Project: All + Format: MBZ + 25:18 Binding Table Entry Count + Project: All + Format: U8 + When HW Generated Binding Table is disabled: Specifies how many binding table entries the kernel + uses. Used only for prefetching of the binding table entries and associated surface state. + Note: For kernels using a large number of binding table entries, it may be wise to set this field to zero + to avoid prefetching too many entries and thrashing the state cache. + + 17 Thread Priority + Project: All + Specifies the priority of the thread for dispatch + Value Name Description + 0h Normal Priority Normal Priority + 1h High Priority High Priority + 16 Floating Point Mode + Project: All + Specifies the initial floating point mode used by the dispatched thread. + Value Name Description + 0h IEEE-754 Use IEEE-754 Rules + 1h alternate Use alternate rules + 15:14 Reserved + Project: All + Format: MBZ + 13 Illegal Opcode Exception Enable + Project: All + Format: Enable + Double Buffer This bit gets loaded into EU CR0.1[12] (note the bit # difference). See Exceptions + Armed By: and ISA Execution Environment. + 12 Reserved + + Format: MBZ + 11 Mask Stack Exception Enable + Project: All + Format: Enable + Double Buffer Armed This bit gets loaded into EU CR0.1[11]. See Exceptions and ISA Execution + By: Environment. + 10:8 Reserved + Project: All + Format: MBZ + 7 Software Exception Enable + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 167 + 3DSTATE_GS + + Format: Enable + This bit gets loaded into EU CR0.1[13] (note the bit # difference). See Exceptions and ISA Execution + Environment. + + 6 Reserved + Project: All + Format: MBZ + 5:0 Reserved + + Format: MBZ +3 31:10 Scratch Space Base Pointer + Project: All + Format: GeneralStateOffset[31:10] + Specifies the location of the scratch space area allocated to this FF unit, specified as a 1KB-granular + offset from the General State Base Address. If required, each thread spawned by this FF unit will be + allocated some portion of this space, as specified by Per-Thread Scratch Space. + + 9:4 Reserved + Project: All + Format: MBZ + 3:0 Per-Thread Scratch Space + Project: All + Format: U4 Power of 2 Bytes over 1K Bytes + + + Specifies the amount of scratch space to be allocated to each thread spawned by this FF unit.The + driver must allocate enough contiguous scratch space, starting at the Scratch Space Base Pointer, to + ensure that the Maximum Number of Threads can each get Per-Thread Scratch Space size without + exceeding the driver-allocated scratch space. + Value Name + [0,11] indicating [1K Bytes, 2M Bytes] +4 31:29 Reserved + Project: All + Format: MBZ + 28:23 Output Vertex Size + Project: All + Format: U6 + + + [0,62] indicating [1,63] 16B units + Specifies the size of each vertex stored in the GS output entry (following any Control Header data) as + a number of 128-bit units (minus one). + + + Programming Notes + Programming Restrictions: The vertex size must be programmed as a multiple of 32B units with the + following exception: Rendering is disabled (as per SOL stage state) and the vertex size output by the + GS thread is 16B. + If rendering is enabled (as per SOL state) the vertex size must be programmed as a multiple of 32B + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 168 + 3DSTATE_GS + + units. In other words, the only time software can program a vertex size with an odd number of 16B + units is when rendering is disabled. + 22:17 Output Topology + Project: All + Format: 3DPrimType + This field specifies the topology type (3DPrimType) to be associated with GS-thread output vertices (if + any). + + 16:11 Vertex URB Entry Read Length + Project: All + Format: U6 + Specifies the amount of URB data read and passed in the thread payload for each Vertex URB entry, in + 256-bit register increments. + Value Name + [0,63] + + + Programming Notes + Programming Restriction:This field must be a non-zero value if Include Vertex Handles is cleared to + zero. + 10 Include Vertex Handles + Project: All + Format: Boolean + If set, all the input Vertex URB handles are included in the payload. These are referred to as “pull + model” URB handles, as the thread will use them to read from the URB. + Programming Notes + This field must be set if Vertex URB Entry Read Length is cleared to zero. + When this field is set and GS is enabled, only PATCHLIST topologies may be submitted. I.e., pull- + model vertices are only supported for PATCH objects, other object types must completely push all + vertex data into the payload. + 9:4 Vertex URB Entry Read Offset + Project: All + Format: U6 + Double Buffer Specifies the offset (in 256-bit units) at which Vertex URB data is to be read from the + Armed By: URB before being included in the thread payload. This offset applies to all Vertex URB + entries passed to the thread. + + + + Value Name + [0,63] + 3:0 Dispatch GRF Start Register for URB Data + Project: All + Format: U4 + Specifies the starting GRF register number for the URB portion (Constant + Vertices) of the thread + payload. + Value Name + [0,15] indicating GRF [R0,R15] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 169 + 3DSTATE_GS + Programming Notes + If Include Vertex Handles is enabled (pull or hybrid handles case), then + For DUAL_OBJECT dispatch mode this field should be: + (((2*numVerticesPerObject) + 8 – 1)/8) + 1 + For SINGLE and DUAL_INSTANCE dispatch modes this field should be: + ((numVerticesPerObject +8 – 1)/8) + 1 + If Include Primitive ID is set, then add 1 to the value obtained by using the above + +5 31:25 Maximum Number of Threads + + Format: U7-1 thread count + + + Specifies the maximum number of simultaneous threads allowed to be active. Used to avoid using up + the scratch space, or to avoid potential deadlock. + Value Name Project + [0,127] indicating thread count of [1,128] + [0,35] indicating thread count of [1,36] + 24 Control Data Format + + Format: U1 + This field specifies the format of the control data header (if any). + Value Name Description + 0h GSCTL_CUT The control data header contains cut bits. + 1h GSCTL_SID The control data header contains StreamID bits. . Output Topology must be set + to POINTLIST, or behavior is UNDEFINED. + 23:20 Control Data Header Size + Project: All + Format: U4 + Specifies the number of 32B units of control data header located at the start of the GS URB entry. The + value 0 indicates there is no control data header, and Control Data Format is ignored.Software must + ensure that the Control Data Header Size is sufficient to accommodate the maixumum number of + vertices output by the GS thread. It is UNDEFINED for a GS thread to report more output vertices than + can be accomodated in a non-zero-sized header. (If the header size is zero, by definition neither cut + nor StreamID bits are defined. + Value Name + [0,8] 32B units + 19:15 Instance Control + Project: All + Format: U5-1 in #instances + + + + + [0,31] indicating [1,32] instances + Specifies the number of instances (minus one) for each input object. To avoid confusion, this + document uses the term “InstanceCount” to refer to InstanceControl+1, with a range of [1,32]If + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 170 + 3DSTATE_GS + + InstanceCount>1, DUAL_OBJECT mode is invalid. Software will likely want to use DUAL_INSTANCE + mode for higher performance, but SINGLE mode is also supported.When InstanceCount=1 (one + instance per object) software can decide which dispatch mode to use. DUAL_OBJECT mode would + likely be the best choice for performance, followed by SINGLE mode. DUAL_INSTANCE mode is not + recommended but is supported. + 14:13 Default StreamID + Project: All + Format: U2 + When the GS is enabled, unless the GS output entry contains StreamID bits in the control header, this + field specifies the default StreamID associated with any GS-thread output vertices. When the GS is + disabled, StreamID will be output as 0. + + 12:11 Dispatch Mode + Project: All + Format: U2 + This field specifies how the GS unit dispatches multiple instances and/or multiple objects. + Value Name Description + 0h SINGLE Each thread shades a single instance of one object. + 1h DUAL_INSTANCE Each thread shades possibly two instances of one object. If the + InstanceCount is odd, a trailing dispatch of only one instance will be made + for each object received.Not recommended if InstanceCount = 1, + assuming a kernel optimized for SINGLE or DUAL_OBJECT dispatch + would outperform a kernel compiled for DUAL_INSTANCE but only + passed one instance.The GS must be allocated at least two URB handles + or behavior is UNDEFINED. + 2h DUAL_OBJECT Each thread shades one instance of possibly two objects. The GS unit + attempt to pair objects together into one dispatch, but under some + circumstances only one object may be dispatched (as controlled by the + DispatchMask generated by the GS unit).Not valid for objects with more + than 16 vertices per object. Not valid if InstanceCount > 1 (more than one + instance per object).The GS must be allocated at least two URB handles + or behavior is UNDEFINED. + 3h Reserved + 10 GS Statistics Enable + Project: All + This bit controls whether GS-unit-specific statistics register(s) can be incremented. + Value Name Description + 0h Disable GS_INVOCATIONS_COUNT and GS_PRIMITIVES_COUNT cannot increment + 1h Enable GS_INVOCATIONS_COUNT and GS_PRIMITIVES_COUNT can increment + 9:5 GSInvocations Increment Value + Project: All + Format: U5 + Specifies how much to increment the GS_INVOCATIONS_COUNT for each instance of each object. + This control is provided to allow software to process multiple instances (from an API POV) in a single + kernel invocation.In SINGLE dispatch mode, the counter will increment by this value for each dispatch + (as it’s only one instance of one object). In DUAL_INSTANCE mode, the counter will be incremented + by the value if only one instance is included in the dispatch (i.e., the last odd instance), otherwise the + counter will be incremented by twice this value.In DUAL_OBJECT dispatch mode, the counter will be + incremented by the value if only one object is included in the dispatch (i.e., a forced dispatch of one + object), otherwise the counter will be incremented by twice this value. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 171 + 3DSTATE_GS + + Value Name + [0,31] indicating an increment of [1,32] + 4 Include Primitive ID + Project: All + Format: Boolean + If set, R1 of the payload is written with Primitive ID value(s).If clear, these Primitive ID values are not + included in the payload R1. + + 3 Hint + Project: All + Format: U1 + This state bit is simply passed in GS thread payloads for use by the GS kernel – it has no other impact + on hardware operation. + + 2 Reorder Enable + + Format: Enable + This bit controls whether the GS unit reorders TRISTRIP/TRISTRIP_REV vertices passed in the GS + thread payload.If ENABLED, the GS unit will reorder the vertices for “odd-numbered” triangles + originating from TRISTRIP topologies and “even-numbered” triangles originating from TRISTRIP_REV + topologies. (Note that the first triangle is considered “triangle 0”, which is even-numbered).With respect + to the PrimType passed in the GS thread payload, the GS unit passes TRISTRIP when the vertices are + not reordered, and TRISTRIP_REV when the vertices are reordered (regardless of whether a + TRISTRIP or TRISTRIP_REV topology was being processed)If DISABLED, TRISTRIP/TRISTRIP_REV + vertices are not reordered, and always passed in the order they are received from the pipeline. The GS + unit will still toggle PrimType on alternating (as described above) so that the GS thread can perform the + reordering internally (or do whatever is necessary to account for the non-reordering of its input). + + 1 Discard Adjaceny + Project: All + Format: Enable + When set, adjacent vertices will not be passed in the GS payload when objects with adjacency are + processed. Instead, only the non-adjacent vertices will be passed in the same fashion as the without- + adjacency form of the primitive. Software should set this bit whenever a GS kernel is used that does + not expect adjacent vertices. This allows both with-adjacency/without-adjacency variants of the + primitive to be submitted to the pipeline (via 3DPRIMITIVE) – the GS unit will silently discard any + adjacent vertices and present the GS thread with only the internal object. When clear, adjacent vertices + will be passed to the GS thread, as dictated by the incoming primitive type. Software should only clear + this bit when a GS kernel is used that does expect adjacent vertices. E.g., if the GS kernel is compiled + to expect a TRIANGLE_ADJ object, software must clear this bit.Software should also clear this bit if the + GS kernel expects a POINT or PATCHLIST_n object (which don’t have with-adjacency variants).This + bit is used to provide limited compatibility between submitted primitive types and the object type + expected by the GS kernel. The only hardware assistance is to allow the submission of a with- + adjacency variant of a primitive when operating with a GS kernel that expects the without-adjacency + variant of the object. (E.g., when the GS kernel is compiled to expect a TRIANGLE object, software + should set this bit just in case a TRILIST_ADJ is submitted to the pipeline.) Note that the GS unit is + otherwise not aware of the object type that is expected by the GS kernel. It is up to software to ensure + that the submitted primitive type (in 3DPRIMITIVE) is otherwise compatible with the object type + expected by the GS kernel. (E.g., if the GS kernel expects a LINE_ADJ object, only LINELIST_ADJ or + LINESTRIP_ADJ should be submitted, otherwise the GS kernel will produce unpredictable results.)Also + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 172 + 3DSTATE_GS + note that it is possible to craft a GS kernel which can accept any object type that’s thrown at it by first + examining the PrimType passed in the payload and then using this info to correctly interpret the + number of vertices passed in the payload. + + 0 GS Enable + Project: All + Format: Enable + Specifies whether the GS stage is enabled or disabled (pass-through). + +6 31 Reserved + + Format: MBZ + 30:13 Reserved + Project: All + Format: MBZ + 12 Reserved + + Format: MBZ + 11:0 Semaphore Handle + Project: + Format: URBOffset[17:6] + This is the URB offset pointing to the first of the GS semaphore DWords in the URB. The size of the + region is 128 DWs(8 – 512b URB entries). Software is responsible for allocating combined GS and/or + HS semaphore Dwords in a single contiguous region of the URB. Software must also make sure the 3D + pipeline is IDLE prior to allocating or deallocating the region. The semaphores can be located in an + unused area within a FF unit’s URB fenced region or an unused area within the Push Constant region. + + + + +7.2.1.2 3DSTATE_CONSTANT_GS + 3DSTATE_CONSTANT_GS + + +Source: RenderCS +Length Bias: 2 +This command sets pointers to the push constants for the GS unit. The constant data pointed to by this command will +be loaded into the GS unit’s push constant buffer (PCB). + Programming Notes Project +It is invalid to execute this command more than once between 3D_PRIMITIVE commands. +Constant buffers must be enabled in order from Constant Buffer 0 to Constant Buffer 3 within this command. +For example, it is not allowed to enable Constant Buffer 1 by programming a non-zero value in the GS +Constant Buffer 1 Read Length without a non-zero value in GS Constant Buffer 0 Read Length. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 173 + 3DSTATE_CONSTANT_GS + + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 16h 3DSTATE_CONSTANT_GS + Format: OpCode + 15 Reserved + Project: All + Format: MBZ + 14:8 Reserved + + Format: MBZ + 7:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Project + 5h Excludes DWord (0,1) [Default] +1..6 191:0 Constant Body + + Format: 3DSTATE_CONSTANT(Body) + Following table is the shared portion of the 3DSTATE_CONSTANT command for VS, HS, DS, + and GS + + + + + 3DSTATE_CONSTANT(Body) + +Project: All +Source: RenderCS +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +DWord Bit Description +0 31:16 Constant Buffer 1 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 174 + 3DSTATE_CONSTANT(Body) + Setting the value of the register to zero will disable buffer 1. +  + If disabled, the Pointer to Constant Buffer 1 must be programmed to zero. + + 15:0 Constant Buffer 0 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 0. +  + If disabled, the Pointer to Constant Buffer 0 must be programmed to zero. + +1 31:16 Constant Buffer 3 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes + +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 3. +  + If disabled, the Pointer to Constant Buffer 3 must be programmed to zero. + + 15:0 Constant Buffer 2 Read Length + Project: All + Format: U16 read length + + + This field specifies the length of the constant data to be loaded from memory in 256-bit units. + Programming Notes +  + The sum of all four read length fields must be less than or equal to the size of 64 +  + Setting the value of the register to zero will disable buffer 2. +  + If disabled, the Pointer to Constant Buffer 2 must be programmed to zero. + +2 31:5 Pointer to Constant Buffer 0 + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 175 + 3DSTATE_CONSTANT(Body) + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 0. The state of INSTPM determines whether the Dynamic State Base Address is added to this + pointer. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Constant Buffer Object Control State + + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for all constant buffers defined in this command. + +3 31:5 Pointer to Constant Buffer 1 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 1. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Reserved + Project: All + Format: MBZ +4 31:5 Pointer to Constant Buffer 2 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 2. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Reserved + Project: All + Format: MBZ +5 31:5 Pointer to Constant Buffer 3 + + Format: GraphicsAddress[31:5]ConstantBuffer + This field points to the location of Constant Buffer 3. + Programming Notes + Constant buffers must be allocated in linear (not tiled) graphics memory. + 4:0 Reserved + + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 176 + 7.2.1.3 3DSTATE_PUSH_CONSTANT_ALLOC_GS + 3DSTATE_PUSH_CONSTANT_ALLOC_GS + + +Source: RenderCS +Length Bias: 2 +This command sets up the URB configuration for GS Push Constant Buffer. + Programming Notes +  The sum of the Constant Buffer Offset and the Constant Buffer Size may not exceed the maximum value of the + Constant Buffer Size. +  The sum of the constant length programmed in 3DSTATE_CONSTANT_GS must be equal or smaller then the + size of the allocated space in the URB including the buffering for half cachelines. +  The 3DSTATE_CONSTANT_GS must be reprogrammed prior to the next 3DPRIMITIVE command after + programming the 3DSTATE_PUSH_CONSTANT_ALLOC_GS. + + See Push Constant URB Allocation section for more details. + +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h GFXPIPE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 15h 3DSTATE_PUSH_CONSTANT_ALLOC_GS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Format: =n + Total Length - 2 + Value Name Description + 0h 3DSTATE_PUSH_CONSTANT_ALLOC_GS [Default] Excludes DWord (0,1) +1 31:20 Reserved + + Format: MBZ + 19:16 Constant Buffer Offset + + Format: U5 + Specifies the offset of the GS constant buffer into the URB. + Value Name + [0,15] (0KB - 15KB) + 0h 0KB [Default] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 177 + 3DSTATE_PUSH_CONSTANT_ALLOC_GS + 15:5 Reserved + + Format: MBZ + 4:0 Constant Buffer Size + + Format: U5 + Specifies the size of the GS constant buffer. This value will determine the amount of data the command + stream can pre-fetch before the buffer is full. Value of zero is only valid when constants are not enabled + for GS. + Value Name + [0,15] (0KB – 15KB) Increments of 1KB + 0h 0KB [Default] + + + + +7.3 Object Staging +The GS unit’s Object Staging Buffer (OSB) accepts primitive topologies as a stream of incoming vertices, +and spawns a thread for each individual object within the topology. + + +7.4 GS Thread Request Generation + +7.4.1 Object Vertex Ordering +The following table defines the number and order of object vertices passed in the Vertex Data portion of +the GS thread payload, assuming an input topology with N vertices. The ObjectType passed to the thread +is, by default, the incoming PrimTopologyType. Exceptions to this rule (for the TRISTRIP variants) are +called out. +The following table also shows which vertex is selected to provide PrimitiveID (bold, underlined vertex +number). In general, the vertex selected is the last vertex for non-adjacent prims, and the next-to-last +vertex for adjacent prims. Note, however, that there are exceptions: + +  reorder-enabled TRISTRIP[_REV] +  “odd-numbered” objects in TRISTRIP_ADJ + PrimTopologyType Order of Vertices in Payload GS Notes + + [] = (,…); [ + {modified PrimType passed to + (N = # of vertices) thread} ] +POINTLIST + [0] = (0); + + [1] = (1); …; + + [N-2] = (N-2); +POINTLIST_BF N/A + + LINELIST [0] = (0,1); + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 178 + PrimTopologyType Order of Vertices in Payload GS Notes + + [] = (,…); [ + {modified PrimType passed to +(N = # of vertices) thread} ] + +(N is multiple of 2) [1] = (2,3); …; + + [(N/2)-1] = (N-2,N-1) + +LINELIST_ADJ [0] = (0,1,2,3); + +(N is multiple of 4) [1] = (4,5,6,7); …; + + [(N/4)-1)] = (N-4,N-3,N-2,N-1) + +LINESTRIP [0] = (0,1); + +(N >= 2) [1] = (1,2); …; + + [N-2] = (N-2,N-1) + +LINESTRIP_ADJ [0] = (0,1,2,3); + +(N >= 4) [1] = (1,2,3,4); …; + + [N-4] = (N-4,N-3,N-2,N-1) +LINESTRIP_BF N/A +LINESTRIP_CONT Same as LINESTRIP Handled same as LINESTRIP +LINESTRIP_CONT_BF Same as LINESTRIP Handled same as LINESTRIP + Not supported after GS. +LINELOOP [0] = (0,1); + +(N >= 2) [1] = (1,2); + + [N] = (N-1,0); + +TRILIST [0] = (0,1,2); + +(N is multiple of 3) [1] = (3,4,5); …; + + [(N/3)-1] = (N-3,N-2,N-1) +RECTLIST Same as TRILIST Handled same as TRILIST + +TRILIST_ADJ [0] = (0,1,2,3,4,5); + +(N is multiple of 6) [1] = (6,7,8,9,10,11); …; + + [(N/6)-1] = (N-6,N-5,N-4,N-3,N-2,N- + 1) + +TRISTRIP (Reorder [0] = (0,1,2); {TRISTRIP} “Odd” triangles have vertices reordered , +ENABLED) though identified as TRISTRIP_REV so the + [1] = (1,3,2); {TRISTRIP_REV} thread knows this +(N >= 3) + [k even] = (k,k+1,k+2) {TRISTRIP} + + [k odd] = (k,k+2,k+1) + {TRISTRIP_REV} + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 179 + PrimTopologyType Order of Vertices in Payload GS Notes + + [] = (,…); [ + {modified PrimType passed to +(N = # of vertices) thread} ] + + [N-3] = (see above) + +TRISTRIP (Reorder [0] = (0,1,2) {TRISTRIP} “Odd” triangles do not have vertices reordered, +DISABLED) though identified as TRISTRIP_REV so the + [1] = (1,2,3) {TRISTRIP_REV}; … thread knows this +(N >= 3) + [N-3] = (N-3,N-2,N-1) {TRISTRIP or + TRISTRIP_REV} + +TRISTRIP_REV (Reorder [0] = (0,2,1) {TRISTRIP_REV}; “Odd” triangles have vertices reordered , +ENABLED) though identified as TRISTRIP so the thread + [1] = (1,2,3) {TRISTRIP}; …; knows this +(N >= 3) + [k even] = (k,k+2,k+1) + {TRISTRIP_REV} + + [k odd] = (k,k+1,k+2) {TRISTRIP} + + [N-3] = (see above) + +TRISTRIP_REV (Reorder [0] = (0,1,2) {TRISTRIP_REV} “Odd” triangles do not have vertices reordered, +DISABLED) though identified as TRISTRIP so the thread + [1] = (1,2,3) {TRISTRIP}; …; knows this +(N >= 3) + [N-3] = (N-3,N-2,N-1) {TRISTRIP or + TRISTRIP_REV} + +TRISTRIP_ADJ N = 6 or 7: “Odd” objects have vertices reordered . + +(N even, N >= 6) [0] = (0,1,2,5,4,3) + + N = 8 or 9: + + [0] = (0,1,2,6,4,3); + + [1] = (2,5,6,7,4,0); …; + + N > 10: + + [0] = (0,1,2,6,4,3); + + [1] = (2,5,6,8,4,0); …; + + [k>1, even] = (2k,2k-2, 2k+2, + 2k+6,2k+4, 2k+3); + + [k>2, odd] = (2k, 2k+3, 2k+4, 2k+6, + 2k+2, 2k-2);…; + + Trailing object: + + [(N/2)-3, even] = (N-6,N-8,N-4,N- + 1,N-2,N-3); + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 180 + PrimTopologyType Order of Vertices in Payload GS Notes + + [] = (,…); [ + {modified PrimType passed to +(N = # of vertices) thread} ] + + [(N/2)-3, odd] = (N-6,N-3,N-2,N- + 1,N-4,N-8); + Only used by OGL +TRIFAN [0] = (0,1,2); + +(N > 2) [1] = (0,2,3); …; + + [N-3] = (0, N-2, N-1); +TRIFAN_NOSTIPPLE Same as TRIFAN +POLYGON Same as TRIFAN + Not supported after GS. +QUADLIST [0] = (0,1,2,3); + +(N is multiple of 4) [1] = (4,5,6,7); …; + + [(N/4)-1] = (N-4,N-3,N-2,N-1); + Not supported after GS. +QUADSTRIP [0] = (0,1,3,2); + +(N is multiple of 2, N >=4) [1] = (2,3,5,4); … ; + + [(N/2)-2] = (N-4,N-3,N-1,N-2); + +PATCHLIST_1 [0] = (0); + +PATCHLIST_2 [1] = (1); …; + +PATCHLIST_3..32 [N-2] = (N-2); + + [0] = (0,1); + + [1] = (2,3); …; + + [(N/2)-1] = (N-2,N-1) + + similar to above + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 181 + 7.4.2 GS Thread Payload High-Level Layout +GS Thread Payload High-Level Layoutshows the high-level layout of the payload delivered to GS threads. + +GS Dispatch Layouts + + + + +Subsequent sections provide detailed layouts for different processor generations. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 182 + 7.4.3 GS Thread Payload SIMD 4x2 +The table below shows the layout of the payload delivered to GS threads. +Refer to the 3D Pipeline Stage Overview section in vol2a 3D Pipelinefor details on those fields that are +common among the various pipeline stages. + +GS Thread Payload SIMD 4x2 + + GRF +DWord Bits Description + R0.7 31 + 31:0 Reserved. + R0.6 31 Dereference Thread. This bit is defined to send back the Handle ID back to HS to dereference + the input handles for this thread. + 30:24 Reserved. + 23:0 + Thread ID. This field uniquely identifies this thread within the threads spawned by this FF unit, + over some period of time. + + Format: Reserved for HW Implementation Use. + R0.5 31:10 + Scratch Space Pointer.Specifies the location of the scratch space allocated to this thread, + specified as a 1KB-aligned offset from the General State Base Address. + + Format = GeneralStateOffset[31:10] + 9.0 Reserved + 8:0 + FFTID. This ID is assigned by the fixed function unit and is relative identifier for the thread. It is + used to free up resources used by the thread upon thread completion. + + Format: + + U7 + + Range: + + 0-127 + R0.4 31:5 + Binding Table Pointer: Specifies the 32-byte aligned pointer to the Binding Table. It is + specified as an offset from the Surface State Base Address. + + Format = SurfaceStateOffset[31:5] + 4:0 Reserved. + R0.3 31:5 + Sampler State Pointer. Specifies the location of the Sampler State Table used by this thread, + specified as a 32-byte granular offset from the Dynamic State Base Address. + + Format = DynamicStateOffset[31:5] + 4 Reserved. + 3:0 + Per Thread Scratch Space.Specifies the amount of scratch space allowed for this thread. + The value specifies the power that two is raised to (over determine the amount of scratch space). + + Programming Notes: + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 183 + GRF +DWord Bits Description + This amount is available to the kernel for information only. It is passed verbatim (if not altered by + the kernel) to the Data Port in any scratch space access messages, but the Data Port ignores it. + + Format = U4 power of two (in excess of 10) + + Range = [0,11] indicating [1K Bytes, 2M Bytes] + R0.2 31:24 + Semaphore Index. This is a DWord index used in URB_ATOMIC commands if the thread is + using data pulled from input handles. This information is only required for pull-model vertex inputs + and InstanceCount > 1. + + Format = U8 + 23 Reserved. + 22 + Hint. This is a copy of the corresponding 3DSTATE_GS bit. + + Format: U1 + 21:16 + Primitive Topology Type. This field identifies the Primitive Topology Type associated with the + primitive containing this object. It indirectly specifies the number of input vertices included in the + thread payload. Note that the GS unit may toggle this value between TRISTRIP and + TRISTRIP_REV. If the Discard Adjacency bit is set, the topology type passed in the payload + is UNDEFINED. + + Format: See 3D Pipeline. + 15:13 Reserved. + 12:0 + Semaphore Handle. This is the URB offset pointing to the first GS semaphore DWord in the + URB. Software is responsible for statically allocating the semaphore DWords in the URB. Refer to + Semaphore Handle field in 3DSTATE_GS for size of semaphore allocation. + + Format: + + U12 64B-aligned URB offset; bit 12 is reserved + R0:1 31:27 GS Instance ID 1. For each input object, the GS unit can spawn multiple threads (instances). + This field starts at zero for the first instance of an object and increments for subsequent instances. + If “dispatch mode” is DUAL_OBJECT this field is not valid. Format: U5 + 26:16 Reserved + 15:0 + URB Return Handle 1. This is the URB offset where the EU’s upper channels (DWords 7:4) + results are stored. If only one object/instance is processed (shaded) by the thread, this field is + effectively ignored (no results are stored for these channels, as controlled by the thread’s + Channel Mask). + + Format: U12 64B-aligned URB offset; bit 12 is reserved + R0.0 31:27 + GS Instance ID 0. For each input object, the GS unit can spawn multiple threads (instances). + This field starts at zero for the first instance of an object and increments for subsequent + instances. + + If “dispatch mode” is DUAL_OBJECT, this field is not valid. + + Format: U5 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 184 + GRF +DWord Bits Description + 26:16 Reserved. + 15:0 + URB Return Handle 0. This is the URB offset where the EU’s lower channels (DWords 3:0) + results are stored. + + Format: + + U12 64B-aligned URB offset; bit 12 is reserved +The following register is included only if Include PrimitiveID is enabled. +R1.7-R1.5 31:0 Reserved: MBZ. + R1.4 31:0 + Primitive ID 1. This field contains the Primitive ID associated with (all instances) of input object + 1. Only valid in DUAL_OBJECT mode. + + Format: U32 +R1.3-R1.1 31:0 Reserved: MBZ. + R1.0 31:0 + Primitive ID 0. This field contains the Primitive ID associated with (all instances) of input object + 0. + + Format: U32 +The following register is included only if SINGLE or DUAL_INSTANCE mode and Include Vertex Handles is enabled. + Rn.7 31:16 ICP 7 Handle ID + 15:0 ICP 7 Handle + Rn.6 31:16 ICP 6 Handle ID + 15:0 ICP 6 Handle + Rn.5 31:16 ICP 5 Handle ID + 15:0 ICP 5 Handle + Rn.4 31:16 ICP 4 Handle ID + 15:0 ICP 4 Handle + Rn.3 31:16 ICP 3 Handle ID + 15:0 ICP 3 Handle + Rn.2 31:16 ICP 2 Handle ID + 15:0 ICP 2 Handle + Rn.1 31:16 ICP 1 Handle ID + 15:0 ICP 1 Handle + Rn.0 31:16 ICP 0 Handle ID + 15:0 ICP 0 Handle +The following register is included only if SINGLE or DUAL_INSTANCE mode and Include Vertex Handles is enabled +and ICP Count > 7. + Rn+1.7 31:16 ICP 15 Handle ID + 15:0 ICP 15 Handle + Rn+1.6 31:16 ICP 14 Handle ID + 15:0 ICP 14 Handle + Rn+1.5 31:16 ICP 13 Handle ID + 15:0 ICP 13 Handle + Rn+1.4 31:16 ICP 12 Handle ID + 15:0 ICP 12 Handle + Rn+1.3 31:16 ICP 11 Handle ID + 15:0 ICP 11 Handle + Rn+1.2 31:16 ICP 10 Handle ID + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 185 + GRF +DWord Bits Description + 15:0 ICP 10 Handle + Rn+1.1 31:16 ICP 9 Handle ID + 15:0 ICP 9 Handle + Rn+1.0 31:16 ICP 8 Handle ID + 15:0 ICP 8 Handle +The following register is included only if SINGLE or DUAL_INSTANCE mode and Include Vertex Handles is enabled +and ICP Count > 15. + Rn+2.7 31:16 ICP 23 Handle ID + 15:0 ICP 23 Handle + Rn+2.6 31:16 ICP 22 Handle ID + 15:0 ICP 22 Handle + Rn+2.5 31:16 ICP 21 Handle ID + 15:0 ICP 21 Handle + Rn+2.4 31:16 ICP 20 Handle ID + 15:0 ICP 20 Handle + Rn+2.3 31:16 ICP 19 Handle ID + 15:0 ICP 19 Handle + Rn+2.2 31:16 ICP 18 Handle ID + 15:0 ICP 18 Handle + Rn+2.1 31:16 ICP 17 Handle ID + 15:0 ICP 17 Handle + Rn+2.0 31:16 ICP 16 Handle ID + 15:0 ICP 16 Handle +The following register is included only if SINGLE or DUAL_INSTANCE mode and Include Vertex Handles is enabled +and ICP Count > 23. + Rn+3.7 31:16 ICP 31 Handle ID + 15:0 ICP 31 Handle + Rn+3.6 31:16 ICP 30 Handle ID + 15:0 ICP 30 Handle + Rn+3.5 31:16 ICP 29 Handle ID + 15:0 ICP 29 Handle + Rn+3.4 31:16 ICP 28 Handle ID + 15:0 ICP 28 Handle + Rn+3.3 31:16 ICP 27 Handle ID + 15:0 ICP 27 Handle + Rn+3.2 31:16 ICP 26 Handle ID + 15:0 ICP 26 Handle + Rn+3.1 31:16 ICP 25 Handle ID + 15:0 ICP 25 Handle + Rn+3.0 31:16 ICP 24 Handle ID + 15:0 ICP 24 Handle +The following register is included only if DUAL_OBJECT mode and Include Vertex Handles is enabled. + Rn.7 31:16 Object 1 ICP 3 Handle ID + 15:0 Object 1 ICP 3 Handle + Rn.6 31:16 Object 1 ICP 2 Handle ID + 15:0 Object 1 ICP 2 Handle + Rn.5 31:16 Object 1 ICP 1 Handle ID + 15:0 Object 1 ICP 1 Handle + Rn.4 31:16 Object 1 ICP 0 Handle ID + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 186 + GRF +DWord Bits Description + 15:0 Object 1 ICP 0 Handle + Rn.3 31:16 Object 0 ICP 3 Handle ID + 15:0 Object 0 ICP 3 Handle + Rn.2 31:16 Object 0 ICP 2 Handle ID + 15:0 Object 0 ICP 2 Handle + Rn.1 31:16 Object 0 ICP 1 Handle ID + 15:0 Object 0 ICP 1 Handle + Rn.0 31:16 Object 0 ICP 0 Handle ID + 15:0 Object 0 ICP 0 Handle +The following register is included only if DUAL_OBJECT mode and Include Vertex Handles is enabled and ICP Count +> 3. + Rn+1.7 31:16 Object 1 ICP 7 Handle ID + 15:0 Object 1 ICP 7 Handle + Rn+1.6 31:16 Object 1 ICP 6 Handle ID + 15:0 Object 1 ICP 6 Handle + Rn+1.5 31:16 Object 1 ICP 5 Handle ID + 15:0 Object 1 ICP 5 Handle + Rn+1.4 31:16 Object 1 ICP 4 Handle ID + 15:0 Object 1 ICP 4 Handle + Rn+1.3 31:16 Object 0 ICP 7 Handle ID + 15:0 Object 0 ICP 7 Handle + Rn+1.2 31:16 Object 0 ICP 6 Handle ID + 15:0 Object 0 ICP 6 Handle + Rn+1.1 31:16 Object 0 ICP 5 Handle ID + 15:0 Object 0 ICP 5 Handle + Rn+1.0 31:16 Object 0 ICP 4 Handle ID + 15:0 Object 0 ICP 4 Handle +The following register is included only if DUAL_OBJECT mode and Include Vertex Handles is enabled and ICP Count +> 7. + Rn+2.7 31:16 Object 1 ICP 11 Handle ID + 15:0 Object 1 ICP 11 Handle + Rn+2.6 31:16 Object 1 ICP 10 Handle ID + 15:0 Object 1 ICP 10 Handle + Rn+2.5 31:16 Object 1 ICP 9 Handle ID + 15:0 Object 1 ICP 9 Handle + Rn+2.4 31:16 Object 1 ICP 8 Handle ID + 15:0 Object 1 ICP 8 Handle + Rn+2.3 31:16 Object 0 ICP 11 Handle ID + 15:0 Object 0 ICP 11 Handle + Rn+2.2 31:16 Object 0 ICP 10 Handle ID + 15:0 Object 0 ICP 10 Handle + Rn+2.1 31:16 Object 0 ICP 9 Handle ID + 15:0 Object 0 ICP 9 Handle + Rn+2.0 31:16 Object 0 ICP 8 Handle ID + 15:0 Object 0 ICP 8 Handle +The following register is included only if DUAL_OBJECT mode and Include Vertex Handles is enabled and ICP Count +> 11. + Rn+3.7 31:16 Object 1 ICP 15 Handle ID + 15:0 Object 1 ICP 15 Handle + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 187 + GRF +DWord Bits Description + Rn+3.6 31:16 Object 1 ICP 14 Handle ID + 15:0 Object 1 ICP 14 Handle + Rn+3.5 31:16 Object 1 ICP 13 Handle ID + 15:0 Object 1 ICP 13 Handle + Rn+3.4 31:16 Object 1 ICP 12 Handle ID + 15:0 Object 1 ICP 12 Handle + Rn+3.3 31:16 Object 0 ICP 15 Handle ID + 15:0 Object 0 ICP 15 Handle + Rn+3.2 31:16 Object 0 ICP 14 Handle ID + 15:0 Object 0 ICP 14 Handle + Rn+3.1 31:16 Object 0 ICP 13 Handle ID + 15:0 Object 0 ICP 13 Handle + Rn+3.0 31:16 Object 0 ICP 12 Handle ID + 15:0 Object 0 ICP 12 Handle + Varies 31:0 +(optional) Constant Data (optional): + + Some amount of constant data (possibly none) can be extracted from the push constant buffer + (PCB) and passed to the thread following the R0 Header. The amount of data provided is defined + by the sum of the read lengths in the last 3DSTATE_CONSTANT_GS command (taking the + buffer enables into account). + + The Constant Data arrives in a non-interleaved format. + Varies 31:0 + Pushed Vertex Data. There can be up to 32 vertices supplied, each with a size defined by the + Vertex URB Entry Read Length state. The amount of data provided for each vertex is + defined by the Vertex URB Entry Read Length state. + + For SINGLE or DUAL_INSTANCE dispatch modes, the pushed data for Vertex 0 immediately + follows any pushed constant data. The pushed data for Vertex 1 immediately follows Vertex 0, + and so on. There is no upper/lower swizzling of data. + + For DUAL_OBJECT dispatch mode, the pushed vertex data is split into upper and lower halves + with Object 0 input vertices in the lower half, and Object 1 input vertices in the upper half. + + + +7.5 GS Thread Execution +A GS thread is capable of performing arbritrary algorithms given the thread payload (especially vertex) +data and associated data structures (binding tables, sampler state, etc.) as input. Output can take the +form of vertices output to the FF pipeline (at the GS unit) and/or data written to memory buffers via the +DataPort. +The primary usage models for GS threads include (possible combinations of): + +  Compiled application-provided “GS shader” programs, specifying an algorithm to convert the vertices + of an input object into some output primitives. For example, a GS shader may convert lines of a line + strip into polygons representing a corresponding segment of a blade of grass centered on the line. + Or it could use adjacency information to detect silhouette edges of triangles and output polygons + extruding out from the those edges. Or it could output absolutely nothing, effectively terminating the + pipeline at the GS stage. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 188 +  Driver-generated instructions used to write pre-clipped vertices into memory buffers (see Stream + Output below). This may be required whether or not an app-provided GS shader is enabled. +  Driver-generated instructions used to emulate API functions not supported by specialized + hardware. These functions might include (but are not limited to): + o Conversion of API-defined topologies into topologies that can be rendered (e.g., + LINELOOPLINESTRIP, POLYGONTRIFAN, QUADsTRIFAN, etc.) + o Emulation of “Polygon Fill Mode”, where incoming polygons can be converted to + points, lines (wireframe), or solid objects. + o Emulation of wide/sprite points. + +  Things best left to the imagination. +When rendering is required, concurrent GS threads must use the FF_SYNC message (URB shared +function) to request an initial VUE handle and synchronize output of VUEs to the +pipeline (see URB in Shared Functions). Only one GS thread can be outputting VUEs to +the pipeline at a time. In order to achieve parallelism, GS threads should perform the +GS shader algorithm (along with any other required functions) and buffer results +(either in the GRF or scratch memory) before issuing the FF_SYNC message. The issuing +GS thread will be stalled on the FF_SYNC writeback until it is that thread’s turn to +output VUEs. As only one GS thread at a time can output VUEs, the post-FF_SYNC output +portion of the kernel should be optimized as much as possible to maximize parallelism. + + +7.5.1 GS Thread Output + +7.5.1.1 GS URB Entry +All outputs of a GS thread will be stored in the single GS thread output URB entry. Cut (1 bit/vertex) or +StreamID (2 bits/vertex) bits are packed into an optional 1-8 32B header. The Control Data Format and +Control Data Header Size states are used to specify the size and contents of the header data (if any). + + + + +Following the optional header is a variable number of 16B or 32B-aligned/granular vertices: + +  When rendering is DISABLED, typically output vertices are 32B-aligned, with the exception of + 16B-alignment for vertices <= 16B in length. + o The absolute worst case size comes from three DW scalars output per vertex. If these are, + say, three “.x” outputs, you need to store each DW in a 128b (16B) element, plus another pad + 16B to keep the 32B alignment. So you require 4*16B = 64B/vertex. You have to have room + for 1024 scalars / 3 scalar/vtx = 341 vertices. 341*64B = 21,824B. Then add 96B to hold 2b/vtx + streamID and you get 21,920B entries. + +  When rendering is ENABLED, each output vertex is 32B-aligned. Here the vertex header and + vertex ‘position’ is required and therefore the minimum size vertex is 32B. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 189 + o Here the worst case size isn’t as bad as render-disabled, as you have to have a 4DW position + output, plus any additional output. So, say you output 5 DW per vertex. You need 64B/vertex + (16B vtx header, 16B position, 16B for the 2nd element, and 16B of pad). You have to have + room for 1024 scalars / 5 = 204 vertices. 204*64 = 13,056B. Then add 64B to hold 2b/vtx + streamID and you get 13,120B entries. + +The size of the URB entry should be based on the declared maximum # of output vertices and the +declared output vertex size (the union of per-stream vertex structures, if required). + +7.5.1.2 GS Output Topologies +The following table lists which primitive topology types are valid for output by a GS thread. + + PrimTopologyType Supported for GS Thread Output? + LINELIST Yes + LINELIST_ADJ No + LINESTRIP Yes + LINESTRIP_ADJ No + LINESTRIP_BF Yes + LINESTRIP_CONT Yes + LINESTRIP_CONT_BF Yes + LINELOOP No + POINTLIST Yes + POINTLIST_BF Yes + POLYGON Yes + QUADLIST No + QUADSTRIP No + RECTLIST Yes + TRIFAN Yes + TRIFAN_NOSTIPPLE Yes + TRILIST Yes + TRILIST_ADJ No + TRISTRIP Yes + TRISTRIP_ADJ No + TRISTRIP_REV Yes + PATCHLIST_xxx Yes + + +7.5.1.3 GS Output StreamID +When the GS Enable is DISABLED, output vertices will be assigned a StreamID = 0; +When the GS Enable is ENABLED, output vertices will be assigned a StreamID = Default StreamID under +the following conditions: + +  Control Data Format = 0, or +  Control Data Format > 0 and Control Data Format = GSCTL_CUT + +When the GS is enabled, Control Data Format > 0 and Control Data Format = GSCTL_SID, output vertices +will be assigned a StreamID as programmed in the Control Data output by the thread. + + +7.5.2 Stream Output +The final contents of Stream Output buffers must follow the strict pipeline ordering of vertices. Given this +ordering requirement, it will be necessary to run the GS stage in a single-threaded fashion (Maximum + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 190 + Number of Threads == 1). Otherwise concurrent GS threads might append vertices to the output buffer out +of order. +Hardware support for the Stream Output is limited to a special “Streamed Vertex Buffer Write” DataPort +message. (Refer to DataPort chapter). Through use of this message type, the GS thread can write from 1 +to 4 DWords to specified ‘element’ (indexed entry) in a BUFFER surface. The DataPort will inhibit writes +past the end of the buffer. +Software will likely need to define separate surface states for each SEB, and separate surface states for +each element within the MEB structure. The surfaces are selected via the normal binding table +mechanisms. +The need for separate SEB surface states is obvious, as the SEBs are separate buffers in memory. The +MEB surface-per-element allows the GS kernel to address the MEB using an structure index. Here each +surface would be specified as having the same structure pitch, but with different starting addresses +corresponding to the different element offsets within the structure – in effect, defining a set of interleaved +surfaces. The GS kernel would output one write message per element. +(Note that software could, if it wished, treat the MEB as a single 1D array of DWords, though it would then +have to write the buffer one DWord at a time, performing the address calculations within the GS kernel. +This should not be necessary, and is certainly not recommended due to obvious performance and +complexity reasons.) +Programming Note: If the GS stage is enabled, software must always allocate at least one GS URB Entry. +This is true even if the GS thread never needs to output vertices to the pipeline, e.g., when only +performing stream output. This is an artifact of the need to pass the GS thread an initial destination URB +handle. + + +7.5.3 Thread Termination +GS threads must terminate by sending a URB_WRITE_xxx message with the EOT and Complete bits set. +The message header must contain correct values for the GS Number of Output Handles for Slot 0, Handle +ID 0, and URB Handle 0 fields. If in DUAL_INSTANCE or DUAL_OBJECT mode, the corresponding Object +1 fields must also be correct. + + +7.6 Primitive Output +(This section refers to output from the GS unit to the pipeline, not output from the GS thread) +The GS unit will output primitives (either passed-through or generated by a GS thread) in the proper +order. This includes the buffering of a concurrent GS thread’s output until the preceding GS thread +terminates. Note that the requirement to buffer subsequent GS thread output until the preceding GS +thread terminates has ramifications on determining the number of VUEs allocated to the GS unit and the +number of concurrent GS threads allowed. + + +7.7 Other Functionality + +7.7.1 Statistics Gathering +There are a number of GS/StreamOutput pipeline statistics counters associated with the GS stage and +GS threads. This subsection describes these counters and controls depending on device, even in the +cases where functions outside of the GS stage (e.g., DataPort) are involved in the statistics gathering. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 191 + Refer to the Statistics Gathering summary provided earlier in this specification. Refer to the Memory +Interface Registers chapter for details on these MMIO pipeline statistics counter registers, as well as the +chapters corresponding to the other functions involved (e.g., DataPort, URB shared functions). + +7.7.1.1 GS Invocations +The GS_INVOCATIONS counter is incremented by the GSInvocations Increment Value state for +every input object, with the exception of DUAL_OBJECT dispatch where the counter is +incremented by twice that amount. This allows software to (for example) support +multiple instances in the GS kernel. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 192 + 8. 3D Pipeline - Stream Output Logic + (SOL) Stage +The Stream Output Logic (SOL) stage receives 3D topologies originating in the VF or GS stage. If +enabled, the SOL stage uses programmed state information to copy portions of the vertex data +associated with the incoming topologies across one or more Stream Output (SO) Buffers. + + +8.1 Input Buffering +For the purposes of stream output, the SOL stage breaks incoming topologies into independent objects +without adjacency information. In the process, any adjacent-only vertices are ignored. For example, +convert TRISTRIP_ADJ into independent 3-vertex triangles. However, if rendering is enabled, incoming +topologies are passed to the Clip stage unmodified and therefore the Clip unit must be enabled if there is +any possibility of “ADJ” topologies reaching it. +Note that the SOL unit should not see incomplete objects: the VF will remove incomplete input objects, +and the GS will remove GS-generated incomplete objects. +The OSB (Object Staging Buffer) reorders the vertices of odd-numbered triangles in TRISTRIP topologies +to match API requirements. +Incoming topologies are tagged with a 2-bit StreamID. The StreamID is 0 for topologies originating from +the VF stage (i.e., 3DPRIMITIVE_xxx). For topologies output from the GS stage, the StreamID is set by +the GS shader. A Stream n Vertex Length is associated with each stream, and defines how much data is +read from the URB for vertices in that stream. +The following table specifies how the SOL stage streams out object vertices for each incoming topology +type. + Order of Vertices + PrimTopologyType Streamed Out Any SOL Notes + [] = (,…); +(N = # of vertices) +POINTLIST [0] = (0); +POINTLIST_BF [1] = (1); …; + [N-2] = (N-2); +LINELIST [0] = (0,1); +(N is multiple of 2) [1] = (2,3); …; + [(N/2)-1] = (N-2,N-1) +LINELIST_ADJ [0] = (1,2); +(N is multiple of 4) [1] = (5,6); …; + [(N/4)-1)] = (N-3,N-2) +LINESTRIP [0] = (0,1); +LINESTRIP_BF [1] = (1,2); …; +LINESTRIP_CONT [N-2] = (N-2,N-1) +LINESTRIP_CONT_BF +(N >= 2) +LINESTRIP_ADJ [0] = (1,2); +(N >= 4) [1] = (2,3); …; + [N-4] = (N-3,N-2) +LINELOOP N/A Not supported after VF. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 193 + Order of Vertices + PrimTopologyType Streamed Out Any SOL Notes +TRILIST [0] = (0,1,2); +(N is multiple of 3) [1] = (3,4,5); …; + [(N/3)-1] = (N-3,N-2,N-1) +RECTLIST Same as TRILIST Handled same as TRILIST. +TRILIST_ADJ [0] = (0,2,4); +(N is multiple of 6) [1] = (6,8,10); …; + [(N/6)-1] = (N-6,N-4,N-2) +TRISTRIP [0] = (0,1,2); “Odd” triangles have vertices reordered to yield increasing +(N >= 3) [1] = (1,3,2); leading vertices starting with v0. +REORDER_LEADING [k even] = (k,k+1,k+2) + [k odd] = (k,k+2,k+1) + [N-3] = (see above) +TRISTRIP [0] = (0,1,2); “Odd” triangles have vertices reordered to yield increasing +(N >= 3) [1] = (2,1,3); trailing vertices starting with v2. +REORDER_TRAILING [k even] = (k,k+1,k+2) + [k odd] = (k+1,k,k+2) + [N-3] = (see above) +TRISTRIP_REV [0] = (0,2,1) “Even” triangles have vertices reordered to yield +(N >= 3) [1] = (1,2,3);…; increasing leading vertices starting with v0. +REORDER_LEADING [k even] = (k,k+2,k+1) + [k odd] = (k,k+1,k+2) + [N-3] = (see above) +TRISTRIP_REV [0] = (1,0,2) “Even” triangles have vertices reordered to yield +(N >= 3) [1] = (1,2,3);…; increasing trailing vertices starting with v2. +REORDER_TRAILING [k even] = (k+1,k,k+2) + [k odd] = (k,k+1,k+2) + [N-3] = (see above) +TRISTRIP_ADJ N = 6 or 7: “Odd” objects have vertices reordered to yield increasing- +(N even, N >= 6) [0] = (0,2,4) by-2 leading vertices starting with v0. +REORDER_LEADING N = 8 or 9: + [0] = (0,2,4); + [1] = (2,6,4); …; + N > 10: + [0] = (0,2,4); + [1] = (2,6,4); …; + [k>1, even] = (2k, 2k+2, + 2k+4); + [k>2, odd] = (2k, 2k+4, + 2k+2);…; + Trailing object: + [(N/2)-3, even] = (N-6,N-4,N- + 2); + [(N/2)-3, odd] = (N-6,N-2,N- + 4); +TRISTRIP_ADJ N = 6 or 7: “Odd” objects have vertices reordered to yield increasing- +(N even, N >= 6) [0] = (0,2,4) by-2 trailing vertices starting with v4. +REORDER_TRAILING N = 8 or 9: + [0] = (0,2,4); + [1] = (4,2,6); …; + N > 10: + [0] = (0,2,4); + [1] = (4,2,6); …; + [k>1, even] = (2k, 2k+2, + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 194 + Order of Vertices + PrimTopologyType Streamed Out Any SOL Notes + 2k+4); + [k>2, odd] = (2k+2,2k, + 2k+4,);…; + Trailing object: + [(N/2)-3, even] = (N-6,N-4,N- + 2); + [(N/2)-3, odd] = (N-4,N-6,N- + 2); +TRIFAN [0] = (0,1,2); +(N > 2) [1] = (0,2,3); …; + [N-3] = (0, N-2, N-1); +TRIFAN_NOSTIPPLE Same as TRIFAN +POLYGON Same as TRIFAN +QUADLIST N/A Not supported after VF. +QUADSTRIP +: [0] = (0); +PATCHLIST_1 [1] = (1); …; + [N-2] = (N-2); +: [0] = (0,1); +PATCHLIST_2 [1] = (2,3); …; + [(N/2)-1] = (N-2,N-1) +: similar to above +PATCHLIST_3..32 + + + +8.2 Stream Output Buffers +Up to four SO buffers are supported. The SO buffer parameters (start/end address, etc.) are specified by +the 3DSTATE_SO_BUFFER command. +The 3DSTATE_STREAMOUT command specifies an SO Buffer Enable bit for each of the buffers. If a +buffer is disabled, its state is ignored and no output will be attempted for that buffer. Any attempt to output +to that buffer will immediately signal an overflow condition. +The SOL stage maintains a current Write Offset register value for each SO buffer. These registers can be +written via MI_LOAD_REGISTER_MEM or MI_LOAD_REGISTER_IMM commands. The SOL stage will +increment the Write Offsets as a part of the SO function. Software can cause a Write Offset register to be +written to memory via an MI_STORE_REGISTER_MEM command, though a preceding flush operation +may be required to ensure that any previous SO functions have completed. +Project Surface Format Name Security + R32G32B32A32_FLOAT + R32G32B32A32_SINT + R32G32B32A32_UINT + R32G32B32_FLOAT + R32G32B32_SINT + R32G32B32_UINT + R32G32_FLOAT + R32G32_SINT + R32G32_UINT + R32_SINT + R32_UINT + R32_FLOAT + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 195 + 8.3 Stream Output Function +As previously mentioned, incoming 3D topologies are targeted at one of the four streams. The SOL stage +contains state information specific to each of the four streams. +A stream’s list of SO declarations (SO_DECL structures) is used to perform the SO function for objects +targeted to that particular stream. The 3DSTATE_SO_DECL_LIST command is used to specify the list of +SO_DECL structures for all four streams in parallel. Software is required to scan the SO_DECL lists of +streams to determine which SO buffers are targeted. The Stream To Buffer Selects bits in +3DSTATE_SO_DECL_LIST must be programmed accordingly (if the buffer is targeted, the select bit must +set, else it must be cleared). +If a stream has no SO_DECL state defined (NumEntries is 0), incoming objects targeting that stream are +effectively ignored. As there is no attempt to perform stream output, overflow detection is neither required +nor performed. +Otherwise, an overflow check is performed. First any attempt to output to a disabled buffer is detected. +This occurs when the stream has a Stream To Buffer Selects bit set but the corresponding SO Buffer +Enable is clear. Assuming all targeted buffers are enabled, an additional check is made to ensure that +there is enough room in each targeted buffer to hold the number of vertices which be output to it (for the +input object). Here the buffer’s current end address is compared to what the write offset would be if the +output was performed. The latter value is computed as (write_offset + vertex_count * buffer_pitch). If this +value is greater than the end address, an overflow is signalled. This check is performed for each buffer +included in Stream To Buffer Selects. +If an overflow is not signaled, the SO function is performed. The SO_DECL list for the targeted stream is +traversed independently for each object vertex, and the operation specified by the SO_DECL structure is +performed (typically causing data to be appended to an SO buffer). In the process, SO buffer Write +Offsets are incremented. + + +8.4 3DSTATE_STREAMOUT +The 3DSTATE_STREAMOUT command specifies control information for the SOL stage. Included are +enables and sizes for input streams and enables for output buffers. +Anytime the SOL unit MMIO registers or non-pipeline state are written, the SOL unit needs to receive a +pipeline state update with SOL unit dirty state for information programmed in MMIO/NP to get loaded into +the SOL unit. +The SOL unit incorrectly double buffers MMIO/NP registers and only moves them into the design for +usage when control topology is received with the SOL unit dirty state. +If the state does not change, need to resend the same state. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 196 + Because of corruption, software must flush the whole fixed function pipeline when +3DSTATE_STREAMOUT changes state. + + 3DSTATE_STREAMOUT + +Source: RenderCS +Length Bias: 2 +This command contains pipelined state required by the SOL unit. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 1Eh 3DSTATE_STREAMOUT + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 1h + + Format: =n + Total Length – 2 + +1 31 SO Function Enable + Project: All + Format: U1 + If set, the SO function is enabled. Vertex data will be streamed out to memory (subject to overflow + detection) as controlled by the various SO-related state variables. + If clear, the SO function is disabled, and therefore no vertex data will be streamed out to memory. + However, the Rendering Disable and Render Stream Select fields will still be used to determine which + vertices (if any) are forwarded down the pipeline for (possible) rendering. + + 30 Rendering Disable + + Format: U1 + If set, the SO stage will not forward any topologies down the pipeline.If clear, the SO stage will forward + topologies associated with Render Stream Select down the pipeline.This bit is used even if SO + Function Enable is DISABLED. + + 29 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 197 + 3DSTATE_STREAMOUT + 28:27 Render Stream Select + Project: All + Format: U2 + + + Description Project + This field specifies which stream has been selected to be forwarded down the pipeline for + possible rendering. Topologies from other streams will not be passed down the pipeline. If + Rendering Disable is set, this field is ignored, as no topologies are sent down the pipeline. + This bit is used even if SO Function Enable is DISABLED. + 26 Reorder Mode + Project: All + This bit controls how vertices of triangle objects in TRISTRIP[_ADJ] and TRISTRIP_REV are reordered + for the purposes of stream-out only (does not impact rendering). See table in Input Buffering. + Value Name Description Project + 0h REORDER_LEADING Reorder the vertices of alternating triangles of a TRISTRIP[_ADJ] All + such that the leading (first) vertices are in consecutive order + starting at v0. A similar reordering is performed on alternating + triangles in a TRISTRIP_REV. + 1h REORDER_TRAILING Reorder the vertices of alternating triangles of a TRISTRIP[_ADJ] All + such that the trailing (last) vertices are in consecutive order + starting at v2. A similar reordering is performed on alternating + triangles in a TRISTRIP_REV. + 25 SO Statistics Enable + Project: All + Format: Enable + This bit controls whether StreamOutput statistics register(s) can be incremented. + Value Name Description Project + 0h Disable SO_NUM_PRIMS_WRITTEN[0..3] and SO_PRIM_STORAGE_NEEDED[0..3] All + registers cannot increment. + 1h Enable SO_NUM_PRIMS_WRITTEN[0..3] and SO_PRIM_STORAGE_NEEDED[0..3] All + registers can increment. + 24:23 Reserved + + Format: MBZ + 22:12 Reserved + Project: All + Format: MBZ + 11 SO Buffer Enable [3] + + Format: U1 + (See SO Buffer Enable [0] ) + + 10 SO Buffer Enable [2] + + Format: U1 + (See SO Buffer Enable [0] ) + + 9 SO Buffer Enable [1] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 198 + 3DSTATE_STREAMOUT + + Format: U1 + (See SO Buffer Enable [0] ) + + 8 SO Buffer Enable [0] + + Format: U1 + If set, stream output to SO Buffer 0 is enabled. If clear, SO Buffer 0 is considered “not bound” and + effectively treated as a zero-length buffer for the purposes of SO output and overflow detection. If an + enabled stream’s Stream to Buffer Selects includes this buffer it is by definition an overflow condition. + That stream will cause no writes to occur, and only SO_PRIM_STORAGE_NEEDED[] will + increment. This bit is ignored if SO Function Enable is DISABLED. + + 7:0 Reserved + Project: All + Format: MBZ +2 31:30 Reserved + Project: All + Format: MBZ + 29 Stream 3 Vertex Read Offset + Project: All + Format: U1 count of 256-bit units + + + Specifies amount of data to skip over before reading back Stream 3 vertex data. + (See Stream 0 Vertex Read Offset) + + 28:24 Stream 3 Vertex Read Length + Project: All + Format: U5-1 count of 256-bit units + + + (See Stream 0 Vertex Read Length) + + 23:22 Reserved + Project: All + Format: MBZ + 21 Stream 2 Vertex Read Offset + Project: All + Format: U1 count of 256-bit units + + + Specifies amount of data to skip over before reading back Stream 2 vertex data. (See Stream 0 Vertex + Read Offset) + + 20:16 Stream 2 Vertex Read Length + Project: All + Format: U5-1 count of 256-bit units + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 199 + 3DSTATE_STREAMOUT + + 15:14 Reserved + Project: All + Format: MBZ + 13 Stream 1 Vertex Read Offset + Project: All + Format: U1 count of 256-bit units + + + Specifies amount of data to skip over before reading back Stream 1 vertex data. (See Stream 0 Vertex + Read Offset) + + 12:8 Stream 1 Vertex Read Length + Project: All + Format: U5-1 count of 256-bit units + + + (See Stream 0 Vertex Read Length) + + 7:6 Reserved + Project: All + Format: MBZ + 5 Stream 0 Vertex Read Offset + Project: All + Format: U1 count of 256-bit units + + + Specifies amount of data to skip over before reading back Stream 0 vertex data. Must be zero if the GS + is enabled and the Output Vertex Size field in 3DSTATE_GS is programmed to 0 (i.e., one 16B unit). + + 4:0 Stream 0 Vertex Read Length + Project: All + Format: U5-1 count of 256-bit units + + + Specifies amount of vertex data to read back for Stream 0 vertices, starting at the Stream 0 Vertex + Read Offset location. Maximum readback is 17 256-bit units (34 128-bit vertex attributes). Read data + past the end of the valid vertex data has undefined contents, and therefore shouldn’t be used to source + stream out data. + Must be zero (i.e., read length = 256b) if the GS is enabled and the Output Vertex Size field in + 3DSTATE_GS is programmed to 0 (i.e., one 16B unit). + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 200 + 8.5 3DSTATE_SO_DECL_LIST Command +The 3DSTATE_SO_DECL_LIST instruction defines a list of Stream Output (SO) declaration entries +(SO_DECLs) and associated information for all specific SO streams in parallel. +Errata: All 128 decls for all four streams must be included whenever this command is issued. The “Num +Entries [n]” fields still contain the actual numbers of valid decls. + + 3DSTATE_SO_DECL_LIST + +Source: RenderCS +Length Bias: 2 +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 17h 3DSTATE_SO_DECL_LIST + Format: OpCode + 15:9 Reserved + Project: All + Format: MBZ + 8:0 DWord Length + Format: =n Total Length – 2 + + + Format: Q1 + + + + + Value Name Description + 3h Excludes DWord (0,1) [Default] Default value = 2(N-1)+3 h +1 31:16 Reserved + Project: All + Format: MBZ + 15:12 Stream to Buffer Selects [3] + Project: All + Format: U4 bitmask + + + Index of SO Stream + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 201 + 3DSTATE_SO_DECL_LIST + Identifies to which SO Buffers stream 3 outputs. See Stream To Buffer Selects [0] field description. + + 11:8 Stream to Buffer Selects [2] + Project: All + Format: U4 bitmask + + + Identifies to which SO Buffers stream 2 outputs. See Stream To Buffer Selects [0] field description. + + 7:4 Stream to Buffer Selects [1] + Project: All + Format: U4 bitmask + + + Identifies to which SO Buffers stream 1 outputs. See Stream To Buffer Selects [0] field description. + + 3:0 Stream to Buffer Selects [0] + Project: All + Format: U4 bitmask + + + Identifies to which SO Buffers stream 0 outputs (irrespective of whether those buffers are enabled via + 3DSTATE_STREAMOUT). Software is required to scan the SO_DECL list in order to provide this + summary information. + Note: For “inactive” streams, software must program this field to all zero (no buffers written to) and the + corresponding Num Entries field to zero (no valid SO_DECLs). + Value Name + 1xxxb SO Buffer 3 + x1xxb SO Buffer 2 + xx1xb SO Buffer 1 + xxx1b SO Buffer 0 +2 31:24 Num Entries [3] + Project: All + Format: U8 #entries + + + Specifies the number of valid SO_DECL entries for Stream 3. (See notes in Num Entries [0] field + description). + Value Name + [0,128] entries + 23:16 Num Entries [2] + Project: All + Format: U8 #entries + + + Specifies the number of valid SO_DECL entries for Stream 2. (See notes in Num Entries [0] field + description). + Value Name + [0,128] entries + 15:8 Num Entries [1] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 202 + 3DSTATE_SO_DECL_LIST + Project: All + Format: U8 #entries + + + Specifies the number of valid SO_DECL entries for Stream 1. (See notes in Num Entries [0] field + description). + Value Name + [0,128] entries + 7:0 Num Entries [0] + Project: All + Format: U8 #entries + + + Specifies the number of valid SO_DECL entries for Stream 0.Note that the SO_DECLs are + programmed in groups of four (one SO_DECL for each of the four streams). Therefore the number of 2- + DWord groups of SO_DECLs supplied in this command is derived from the stream(s) with the most + valid SO_DECLs. The NumEntries value specific to each stream will indicate how many SO_DECLS + are valid for that particular stream. Any trailing invalid SO_DECLs supplied for streams with fewer valid + SO_DECLs will be ignored. It is legal to specify Num Entries = 0 for all four streams simultaneously. In + this case there will be no SO_DECLs included in the command (only DW 0-2). Note that all Stream to + Buffer Selects bits must be zero in this case (as no streams produce output). + Value Name + [0,128] entries +3..4 63:48 SO_DECL[3,1] + Project: All + Format: SO_DECL + This field contains Stream 3 SO_DECL 0 + + 47:32 SO_DECL[2,1] + Project: All + Format: SO_DECL + This field contains Stream 2 SO_DECL 0 + + 31:16 SO_DECL[1,1] + Project: All + Format: SO_DECL + This field contains Stream 1 SO_DECL 0 + + 15:0 SO_DECL[0,1] + Project: All + Format: SO_DECL + This field contains Stream 0 SO_DECL 0 + +5..6 63:48 SO_DECL[3,1] + Project: All + Format: SO_DECL + This field contains Stream 3 SO_DECL 1 + + 47:32 SO_DECL[2,1] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 203 + 3DSTATE_SO_DECL_LIST + Project: All + Format: SO_DECL + This field contains Stream 2 SO_DECL 1 + + 31:16 SO_DECL[1,1] + Project: All + Format: SO_DECL + This field contains Stream 1 SO_DECL 1 + + 15:0 SO_DECL[0,1] + Project: All + Format: SO_DECL + This field contains Stream 0 SO_DECL 1 + +7..n 63:48 SO_DECL[3,n] + Project: All + Format: SO_DECL + This field contains Stream 3 SO_DECL n + + 47:32 SO_DECL[2,n] + Project: All + Format: SO_DECL + This field contains Stream 2 SO_DECL n + + 31:16 SO_DECL[1,n] + Project: All + Format: SO_DECL + This field contains Stream 1 SO_DECL n + + 15:0 SO_DECL[0,n] + Project: All + Format: SO_DECL + This field contains Stream 0 SO_DECL n + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 204 + 8.5.1 SO_DECL Structure Definition + + SO_DECL + +Source: RenderCS +Default Value: 0x00000000 +A list of SO_DECL structures are passed in the 3DSTATE_SO_DECL_LIST command. Each structure specifies +either (a) the source and destination of an up-to-4-DWord appending write into an SO buffer, or (b) how many +DWords to skip over in the destination SO buffer (i.e., a “hole” where the previous buffer contents are maintained). +Workaround for IVBGT2:A0 (ends IVBGT2:B0): because of corruption in IVBGT2:A0, software needs to put a noop +decl (Hole flag is 0, Component Mask is 0) as the first decl in every decl list. +DWord Bit Description +0 15:14 Reserved + Project: All + Format: MBZ + 13:12 Output Buffer Slot + Project: All + Format: U2 Buffer Index + + + This field selects the destination output buffer slot. + + 11 Hole Flag + Project: All + Format: Flag + If set, the Component Mask field indirectly specifies a number of 32-bit locations to skip over (leave + unmodified in memory) in the selected output buffer. The Register Index field is ignored. The only + permitted Component Mask values are as follows: + 0x0 No Dwords are skipped over (SO_DECL performs no operation) + 0x1 (X) Skip 1 DWord + 0x3 (XY) Skip 2 DWords + 0x7 (XYZ) Skip 3 DWords + 0xF (XYZW) Skip 4 DWords + 10 Reserved + Project: All + Format: MBZ + 9:4 Register Index + Project: All + Format: U6 128-bit granular offset into the source vertex read data + + + + + If Hole Flag is clear, this field specifies the 128-bit offset into the source vertex data which supplies the + source data to be written to the destination buffer, where the individual 32-component destination + locations are selected by Component Mask. e.g., Register Index 0 corresponds with the first 128 bits of + the data read from the vertex URB entry (as per corresponding Vertex Read Offset state) + There is only enough internal storage for the 128-bit vertex header and 32 128-bit vertex attributes. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 205 + SO_DECL + + Value Name + [0,32] + 0h [Default] + + + Programming Notes + It is the responsibility of software to map any API-visible source data specifications (e.g., vertex + register number) into 128-bit granular URB read offsets. + 3:0 Component Mask + Project: All + Format: MASK 4-bit Mask + + + This field is a 4-bit bitmask that selects which contiguous 32-bit component(s) are either written or + skipped-over in the destination buffer. + If this field is zero the SO_DECL operation is effectively a no-op. No data will be appended to the + destination and the destination buffer’s write pointer will not be advanced. + If the Hole Flag is set, this field (if non-zero) indirectly specifies how much the destination buffer’s + write pointer should be advanced.See Hole Flag description above for restrictions on this field. + If the Hole Flag is clear, this field (if non-zero) selects which source components are to be written to + the destination buffer. The components must be contiguous, e.g. YZW is legal, but XZW is not. The + selected source components are written to the destination buffer starting at the current write pointer, + and then the write pointer is advanced past the written data. E.g., if YZW is specified, the three (YZW) + components of the source register will be written to the destination buffer at the current write pointer, + and the write pointer will be advanced by 3 DWords. + Value Name Project + 0h [Default] + xxx1b SO_DECL_COMPMASK_X All + xx1xb SO_DECL_COMPMASK_Y All + x1xxb SO_DECL_COMPMASK_Z All + 1xxxb SO_DECL_COMPMASK_W All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 206 + 8.6 3DSTATE_SO_BUFFER +The 3DSTATE_SO_BUFFER command specifies the location and characteristics of an SO buffer in +memory. + + 3DSTATE_SO_BUFFER + +Source: RenderCS +Length Bias: 2 +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 18h 3DSTATE_SO_BUFFER + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 2h Excludes DWord (0,1) + Format: =n + Total Length - 2 + +1 31 Reserved + Project: All + Format: MBZ + 30:29 SO Buffer Index + Project: All + Format: U2 + Specifies which of the four SO Buffers is being defined. + + 28:25 SO Buffer Object Control State + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for the SO buffer. + + 24:22 Reserved + Format: MBZ + 21:12 Reserved + Project: All + Format: MBZ + 11:0 Surface Pitch + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 207 + 3DSTATE_SO_BUFFER + Project: All + Format: U12 Pitch in Bytes + + + This field specifies the pitch of the SO buffer in #Bytes. + Value Name + [0,2048] Must be 0 or a multiple of 4 Bytes. + + + Programming Notes + A Surface Pitch of 0 indicates an un-bound buffer. No writes are performed. Surface Base Address is + ignored. +2 31:2 Surface Base Address + Project: All + Format: GraphicsAddress[31:2] + This field specifies the starting DWord address LSBs of the buffer in Graphics Memory. + + 1:0 Reserved + Project: All + Format: MBZ +3 31:2 Surface End Address + Format: GraphicsAddress[31:2] + This field specifies the ending DWord address of the buffer in Graphics Memory. + + 1:0 Reserved + Project: All + Format: MBZ + + + + +8.7 Rendering Disable +Independent of SOL function enable, if rendering (i.e, 3D pipeline functions past the SOL stage) is +enabled (via clearing the Rendering Disable bit), the SOL stage will pass topologies for a specific input +stream (as selected by Render Stream Select) down the pipeline, with the exception of PATCHLIST_n +topologies which are never passed downstream. Software must ensure that the vertices exiting the SOL +stage include a vertex header and position value so that the topologies can be correctly processed by +subsequent pipeline stages. Specifically, rendering must be disabled whenever 128-bit vertices are output +from a GS thread. +If Rendering Disable is set, the SOL stage will prevent any topologies from exiting the SOL stage. + + +8.8 Statistics +The SOL stage controls the incrementing of two 64-bit statistics counter registers for each of the four +output buffer slots, SO_NUM_PRIMS_WRITTEN[] and SO_PRIM_STORAGE_NEEDED[]. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 208 + 9. 3D Pipeline – Clip Stage +9.1 3D Pipeline – CLIP Stage Overview +The CLIP stage of the 3D Pipeline is similar to the GS stage in that it can be used to perform general +processing on incoming 3D objects via spawned threads. However, the CLIP stage also includes +specialized logic to perform a ClipTest function on incoming objects. These two usage models of the CLIP +stage are outlined below. +Refer to the Common 3D FF Unit Functions subsection in the 3D Overview chapter for a general +description of a 3D Pipeline stage, as much of the CLIP stage operation and control falls under these +“common” functions. I.e., many of the CLIP stage state variables and CLIP thread payload parameters +are described in 3D Overview, and although they are listed here for completeness, that chapter provides +the detailed description of the associated functions. +Refer to this chapter for an overall description of the CLIP stage, details on the ClipTest function, and any +exceptions the CLIP stage exhibits with respect to common FF unit functions. + + +9.1.1 Clip Stage – General-Purpose Processing +Numerous state variable controls are provided to tailor the ClipTest function as required by the API or +primitive characteristics. These controls allow a mode where all objects are passed to CLIP threads, and +in this regard the CLIP stage can be used as a second GS stage. However, unlike the GS stage, +primitives output by CLIP threads will not be subject to 3D Clipping, and therefore any clip-testing/clipping +of these primitives (if required) would need to be performed by the CLIP thread itself. + + +9.1.2 Clip Stage – 3D Clipping +The ClipTest fixed function is provided to optimize the CLIP stage for support of generalized 3D Clipping. +The CLIP FF unit examines the position of incoming vertices, performs a fixed function VertexClipTest on +these positions, and then examines the results for the vertices of each independent object in +ClipDetermination. +The results of ClipDetermination indicate whether an object is to be processed by a thread (MustClip), +discarded (TrivialReject) or passed down the pipeline unmodified (TrivialAccept). In the MustClip case, +the spawned thread is responsible for performing the actual 3D Clipping algorithm. The CLIP thread is +passed the source object vertex data and is able to output a new, arbitrary 3D primitive (e.g., the clipped +primitive), or no output at all. Note that the output primitive is independent in that it is comprised of newly- +generated VUEs, and does not share vertices with the source primitive or other CLIP-generated +primitives. +New vertices produced by the CLIP threads are stored in the URB. Their Vertex Headers are then read +from the VUEs in order to insert the relevant information into the 3D pipeline. The CLIP unit maintains the +proper ordering of CLIP-generated primitives and any surrounding trivially-accepted primitives. The CLIP +unit also supports multiple concurrent CLIP threads and maintains the proper ordering of the thread +outputs as dictated by the order of the source objects. +The outgoing primitive stream is sent down the pipeline to the Strip/Fan (SF) FF stage (now including the +read-back VUE Vertex Header data such as Vertex Rosition (NDC or screen space), RTAIndex, VPIndex, + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 209 + PointWidth) and control information (PrimType, PrimStart, PrimEnd) while the remainder of the vertex +data remains in the VUE in the URB. + + +9.1.3 Fixed Function Clipper +The GPU supports Fixed Function Clipping. + + +9.2 Concepts +This section provides an overview of 3D clip-testing and clipping concepts. It is provided as background +material: some of the concepts impact HW functionality while others impact CLIP kernel functionality. + + +9.2.1 The Clip Volume +3D objects are optionally clipped to the clip volume. The clip volume is defined as the intersection of a +set of clip half-spaces. Six of these half-spaces define the view volume, while additional, user-defined +half-spaces can be employed to perform clipping (or at least culling) within the view volume. +The CLIP stage design will permit the enable/disable of certain subsets of these clip half-spaces. This +capability can be used, for example, to disable viewport, guardband, and near and far clipping as required +by the API and other conditions. + +9.2.1.1 View Volume +The intersection of the six view half-spaces defines the view volume. The view volume is defined in 4D +clip space coordinates as: + ‘Outside’ Condition + View Clip Plane 4D Clip Space NDC space, positive w + clip.x < -clip.w ndc.x < -1 + XMIN + (NDC Left) + clip.w < clip.x ndc.x > 1 + XMAX + (NDC Right) + clip.y < -clip.w ndc.y < -1 + YMIN + (NDC Bottom) + clip.w < clip.y ndc.y > 1 + YMAX + (NDC top) + + ZMIN OGL: clip.z < -clip.w OGL: ndc.z < -1.0 + (NDC Near) + clip.w < clip.z ndc.z > 1.0 + ZMAX + (NDC Far) + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 210 + Note that, since the 2D (X,Y) extent of the projected view volume is subsequently mapped to the 2D pixel +space viewport, the terms “viewport” and “view volume” are used somewhat interchangeably in this +discussion. +The CLIP unit will perform view volume clip test using NDC coordinates (the results of the speculative +PerspectiveDivide). The treatment of negative ndc.w and invalid (NaN, +/-INF) coordinates is clarified +below. +Negative W Coordinates + +Consider for a moment vertices with a negative clip.w coordinate. Examination of the API definitions for +“outside” shows that it is impossible for that vertex to be considered inside both the XMIN (NDC Left) +and XMAX (NDC Right) planes. The clip.x coordinate would need to be greater than or equal to some +positive value (-clip.w) to be considered inside the XMIN plane, while also being less than or equal to the +negative (clip.w) value to be considered inside the XMAX plane. Obviously both these conditions cannot +be met simultaneously, so a vertex with a negative clip.w coordinate will always appear outside. +Surprisingly, it is possible for a vertex to be outside both the XMIN and XMAX planes (and likewise for +the Y axis). This arises when clip.w is negative and clip.x falls between clip.w and -clip.w. Note, however, +that in NDC space (post perspective-divide), this same vertex would be considered inside. This +disparity arises from the loss of information from the perspective divide operation, specifically the signs of +the input operands. The CLIP stage will avoid this artifact by supporting an additional clip.w=0 clip plane – +a negative ndc.rhw value indicates the point is outside of the clip.w=0 plane. +The assumption made in the Clip stage is that only the w>0 portion of clip space is considered visible. +The VertexClipTest function tests each incoming 1/w value and, if negative, the vertex is tagged as being +outside the w=0 plane. These vertex outcodes are combined in ClipDetermination to determine +TA/TR/MC status. +A negative w coordinate poses an additional issue due to the fact that VertexClipTest is performed using +post-perspection-projection coordinates (NDC or screen space). This disparity arises from the loss of +information from the perspective divide operation, specifically the signs of the input operands. For +example, to test for (x>w) using NDC coordinates, (x/w>1) must be used when w>0, and (x/w<1) must be +used when w<0. The VertexClipTest function therefore uses the sign of the incoming 1/w coordinate to +select the appropriate comparison function for each of the VP and GB clip planes. +As the CLIP thread performs clipping in 4D clip space, only the truly visible portions of objects (i.e, +meeting the 4D clip space visibility criteria) will be considered. The CLIP thread should not output +negative w (clip or NDC) coordinates. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 211 + 9.2.2 User-Specified Clipping +The various APIs define mechanisms by which objects can be clipped or culled according to some user- +specified parameter(s) in addition to the implied viewport clipping. The HW support of these mechanisms +is restricted to use of the 8 UserClipFlags (UCFs) of the VUE Vertex Header. Software is required to +provide the remaining support (e.g., the JITTER including GEN4 instructions to cause a distance value to +be computed, tested for visibility, and generation of the appropriate UCF bit.) + + +9.2.3 Guard Band +Note: Refer to Vertex X,Y Clamping and Quantization in the SF stage section for device-specific +guardband size information. +3DClipping is time consuming. For cases where 2DClipping is sufficient, we are willing to forgo +3DClipping and instead apply 2DClipping during rendering. In the general case, this is possible only + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 212 + when an object is totally within the ZMin and ZMax planes, and only clipping to the view volume X/Y +MIN/MAX clip planes is required, as 2DClipping is restricted to a screen-aligned 2D rectangle. +However, we must ensure that the 2D extent of these objects do not exceed the limitations of the +renderer’s coordinate space (see Vertex X,Y Clamping and Quantization in the SF section). Therefore we +define a 2D guardband region corresponding to (though likely somewhat smaller than) the maximum 2D +extent supported by the renderer. During VertexClipTest, vertices are (optionally) subjected to an +additional visibility test based on the 2D guardband region. +During ClipDetermination, if an object is not trivially-rejected from the 2D viewport, the XMIN_GB, +XMAX_GB, YMIN_GB and YMAX_GB guardband outcodes are used instead of the XMIN, XMAX, YMIN, +YMAX view volume outcodes to determine trivial-accept. This will allow objects that fall within the +guardband and possibly intersect the viewport to be trivially-accepted and passed down the pipeline. +The diagram below shows some examples of objects (triangles) in relation to the viewport and +guardband. The shaded triangles are examples of triangles that are not trivially accepted to the viewport +but trivially accepted to the guardband and therefore passed to down the pipeline. Without the guardband, +these triangles would have to be submitted to a CLIP thread. + +Normal Guardband Operation + + + + +The CLIP stage needs to handle the case where the viewport XY is larger than the screen space +coordinate range supported by the SF and WM units. This condition may arise when the API defines an + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 213 + implicit 2D clip between the viewport XY extent and the rendertarget. In the 3D pipeline, the guardband +must used to force explicit clipping in order to ensure legal coordinates are passed out of the CLIP stage. +Therefore the CLIP unit supports a guardband that can be larger or smaller than the viewport (in any +particular direction). The following diagram illustrates a case with a very large viewport, extending well +beyond the guardband. Note that the only trivial accept case is where objects are completely within the +guardband. + +Very Large Viewport Case + + + + +9.2.3.1 NDC Guardband Parameters +Note: Refer to Vertex X,Y Clamping and Quantization in the SF stage section for device-specific +guardband size information. +When the CLIP unit performs VertexClipTest in NDC space, the guardband limits must be provided as +NDC coordinates. The diagram below shows how the guardband NDC coordinates are derived. +Specifically, the XMIN_GB NDC coordinate is simply the ratio of the (screen space) distance from the +screen space VP center to the screen space GB XMin boundary over the distance from the VP center to +the VP XMin (left) boundary. A similar computation yields the XMAX_GB (right), YMIN_GB (bottom) and +YMAX_GB (top) guardband NDC coordinates. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 214 + As these guardband parameters are defined relative to the viewport, each of the up-to-16 sets of viewport +specifications supported in the 3D pipeline will require a corresponding set of guardband parameters. +These guardband parameters are provided as a separate memory-resident state structure +(CLIP_VIEWPORT), and referenced via the Clipper Viewport State Pointer contained in the +CLIP_STATE structure. Note that the CLIP_VIEWPORT structure has a different definition than the +SF_VIEWPORT structure used by the SF unit. + + +9.2.4 Vertex-Based Clip Testing & Considerations +The CLIP unit performs clip test and determines whether objects need to be clipped based solely on +information (position, UserClipFlags) provided at the vertices of the object as they arrive at the clip +stage. Issues arise if and when the corresponding rendered object is not constrained to the convex hull of +the object. Different APIs impose different treatment of these conditions. +In addition and in the more general case, a CLIP thread could be used to convert the object (as defined +by its vertices) into some arbitrary output primitive. In this case, the CLIP unit’s +ClipTest/ClipDetermination logic may not be suitable for determination of when to reject/accept/clip +objects. In this case the ClipMode can be used to route all (or all non-rejected) objects to CLIP threads, +where the proper clip-test and clipping can occur in the CLIP kernel. +One issue that arises is whether a trivial-reject to the VPXY is suitable. If this were allowed, an object +might be discarded even if it would have been partially visible in the viewport. A second issue is whether +a TA against the GB is suitable. If this were allowed, portions of the rendered object might be visible in +the VP even if the object should have been clipped out of the VP. + +9.2.4.1 Triangle Objects +In the normal processing of triangle-based primitives (tristrip/trilist/polygon/etc.), the footprint of each +triangle is constrained to the 2D convex hull. I.e., the rendering of these triangles will not produce pixels +outside of the triangle. Therefore the normal operation of the CLIP unit functions will support the proper +clip testing and clip determination for triangle objects: + +  Both the VPXY and GB clip boundaries can be utilized (as described above). If the triangle is TR + against the VP, it can be discarded. Otherwise, if the triangle is TA against the GB, it can be passed + down the pipeline (assuming it is TA against VPZ, UCFs, etc.) and properly handled by 2DClipping. +  The GB parameters can be programmed to coincide with the maximum allowable screen space + extent (though making the GB marginally smaller than this max extent is highly recommended). + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 215 + 9.2.4.2 Non-Wide Line Objects +In the normal processing of non-wide, line-based primitives (linestrip/linelist/etc.), the footprint of each line +is constrained to the 2D convex hull. I.e., the rendering of these lines will not produce pixels off of the line. +Therefore the normal operation of the CLIP unit functions will support the proper clip testing and clip +determination for non-wide line objects. (See Triangle Objects above). + +9.2.4.3 + +9.2.4.4 Wide Line Objects +The rendering hardware supports wide lines (solid lines with a line width or anti-aliased lines). When +rendered, pixels outside of the convex hull will be generated. +The following diagram shows an example of a wide line that normally would be TA against the GB. If the +TA is allowed, the partially-visible region of the line would be rendered. + + + + +In general, OpenGL dictates that the partially-visible region must not be rendered. In this case the line +must be clipped-out against the VPXY (not TA against the GB). To accomplish this, SW could disable the +GB when drawing wide lines. + +9.2.4.5 Wide Points +The GEN rendering hardware supports a width parameter for native line objects. When rendered, pixels +surrounding the point (center) vertex will be generated. +The following diagram shows an example wide point that normally would be TR against the VPXY. If the +TR is allowed, the partially-visible region of the point would not be rendered. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 216 + In general, OpenGL dictates that the partially-visible region must not be rendered. In this case the point +must be TR against the VPXY (not TA against the GB). To accomplish this, SW could disable the GB +when drawing wide points. + +9.2.4.6 RECTLIST +The CLIP unit treats RECTLIST exactly like TRILIST. No special consideration is made for the implied 4 th +vertex of each rectangle (although ViewportXY and Guardband VertexClipTest theoretically should be +sufficient to drive ClipDetermination). Given this, and the fact that RECTLIST is primarily intended for +driver-generated “BLT” functions, there are number of restrictions on the use of RECTLIST, especially +regarding the CLIP unit. Refer to the RECTLIST definition in 3D Pipeline. + + +9.2.5 3D Clipping +If an object needs to be clipped, it will be passed to the CLIP thread. The CLIP thread will perform some +(arbitrary) algorithm to clip the primitive, and subsequently output “new” vertices as a primitive defining +the visible region of the input object (assuming there is a visible region). In the process of spawning the +CLIP thread, the input vertices may be considered “consumed” and therefore dereferenced. Therefore the +CLIP thread will need to copy (if required) any input VUE data to a new output VUE – there is no +mechanism to “output” input vertices other than copying. +supports only Fixed function Clipping + + +9.3 CLIP Stage Input +As a stage of the 3D pipeline, the CLIP stage receives inputs from the previous (GS) stage. Refer to 3D +Overview for an overview of the various types of input to a 3D Pipeline stage. The remainder of this +subsection describes the inputs specific to the CLIP stage. + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 217 + 9.3.1 State + +9.3.1.1 3DSTATE CLIP +The state used by the Clip Stage is defined by this inline state packet. + + 3DSTATE_CLIP + +Source: RenderCS +Length Bias: 2 +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINE + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 12h 3DSTATE_CLIP + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 02h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:21 Reserved + Project: All + Format: MBZ + 20 Front Winding + Project: All + Determines whether a triangle object is considered “front facing” if the screen space vertex positions, + when traversed in the order, result in a clockwise (CW) or counter-clockwise (CCW) winding order. + Does not apply to points or lines. + Value Name Description Project + 0h FRONTWINDING_CW All + 1h FRONTWINDING_CCW All + 19 Vertex Sub Pixel Precision Select + Project: All + Format: U1 + Selects the number of fractional bits maintained in the vertex data + Value Name Description Project + 0h 8 sub pixel precision bits maintained All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 218 + 3DSTATE_CLIP + 1h 4 sub pixel precision bits maintained All + 18 EarlyCull Enable + Project: All + Format: Enable + This field is used to enable/disable the EarlyCull function. + Programming Notes Project + Workaround : Due to Hardware issue "EarlyCull" needs to be enabled only for the cases where + the incoming primitive topology into the clipper guaranteed to be Trilist. + 17:16 Cull Mode + Project: All + Format: 3D_CullMode + Controls removal (culling) of triangle objects based on orientation. The cull mode only applies to + triangle objects and does not apply to lines, points or rectangles. + Value Name Description Project + 0h CULLMODE_BOTH All triangles are discarded (i.e., no triangle objects are drawn) All + 1h CULLMODE_NONE No triangles are discarded due to orientation All + 2h CULLMODE_FRONT Triangles with a front-facing orientation are discarded All + 3h CULLMODE_BACK Triangles with a back-facing orientation are discarded All + + + Programming Notes + Orientation determination is based on the setting of the Front Winding state. + 15:11 Reserved + Project: All + Format: MBZ + 10 Clipper Statistics Enable + Project: All + Format: Enable + This bit controls whether Clip-unit-specific statistics register(s) can be incremented. + Value Name Description Project + 0h Disable CL_INVOCATIONS_COUNT cannot increment All + 1h Enable CL_INVOCATIONS_COUNT can increment All + 9:8 Reserved + Project: All + Format: MBZ + 7:0 User Clip Distance Cull Test Enable Bitmask + Project: All + Format: Enable[8] + This 8 bit mask field selects which of the 8 user clip distances against which trivial reject / trivial accept + determination needs to be made (does not cause a must clip).DX10 allows simultaneous use of + ClipDistance and Cull Distance test of up to 8 distances. + +2 31 CLIP Enable + Project: All + Format: Enable + Specifies whether the CLIP function is enabled or disabled (pass-through). + + 30 API Mode + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 219 + 3DSTATE_CLIP + Project: All + Controls the definition of the NEAR clipping plane + Value Name Description Project + 0h APIMODE_OGL NEAR VP boundary == 0.0 (NDC) All + 29 Reserved + Project: All + Format: MBZ + 28 Viewport XY ClipTest Enable + Project: All + Format: Enable + This field is used to control whether the Viewport X,Y extents are considered in VertexClipTest. See + Tristrip Clipping Errata subsection. + + 27 Viewport Z ClipTest Enable + Project: All + Format: Enable + This field is used to control whether the Viewport Z extents (near, far) are considered in VertexClipTest. + + 26 Guardband ClipTest Enable + Project: All + Format: Enable + This field is used to control whether the Guardband X,Y extents are considered in VertexClipTest for + non-point objects. If the Guardband ClipTest is DISABLED but the Viewport XY ClipTest is ENABLED, + ClipDetermination operates as if the Guardband were coincident with the Viewport. If both the + Guardband and Viewport XY ClipTest are DISABLED, all vertices are considered “visible” with respect + to the XY directions. + + 25:24 Reserved + Project: All + Format: MBZ + 23:16 User Clip Distance Clip Test Enable Bitmask + Project: All + Format: Enable[8] + This 8 bit mask field selects which of the 8 user clip distances against which trivial reject / trivial accept + / must clip determination needs to be made.DX10 allows simultaneous use of ClipDistance and Cull + Distance test of up to 8 distances. + + 15:13 Clip Mode + Project: All + This field specifies a general mode of the CLIP unit, when the CLIP unit is ENABLED. + Value Name Description Project + 0h CLIPMODE_NORMAL TrivialAccept objects are passed down the pipeline, MustClip All + objects Clipped in the Fixed Function Clipper HW, + TrivialReject and BAD objects are discarded + 1h Reserved All + 2h Reserved All + 3h CLIPMODE_REJECT_ALL All objects are discarded All + 4h CLIPMODE_ACCEPT_ALL All objects (except BAD objects) are trivially accepted. This All + effectively disables the clip-test/clip-determination function. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 220 + 3DSTATE_CLIP + Note that the CLIP unit will still filter out adacency + information, which may be required since the SF unit does + not accept primitives with adjacency. + 5h-7h Reserved All + 12:10 Reserved + Project: All + Format: MBZ + 9 Perspective Divide Disable + Project: All + Format: Disable + This field disables the Perspective Divide function performed on homogeneous position read from the + URB. This feature can be used by software to submit pre-transformed “screen-space” geometry for + rasterization. This likely requires the W component of positions to contain “rhw” (aka 1/w) in order to + support perspective-correct interpolation of vertex attributes. Likewise, the X,Y,Z components will likely + be required to be X/W, Y/W, Z/W. Note that the device does not support clipping when perspective + divide is disabled. Software must specify CLIPMODE_ACCEPT_ALL whenever it disables perspective + divide. This implies that software must ensure that object positions are completely contained within the + “guardband” screen-space limits imposed by the SF unit (e.g., by clipping in CPU SW before submitting + the objects). + + 8 Non-Perspective Barycentric Enable + Project: All + Format: Enable + This field enables computation of non-perspective barycentric parameters in the clipper, which are sent + to SF unit in the must clip case. This field must be enabled if any non-perspective barycentric + parameters are enabled in the Windower. + + 7:6 Reserved + Project: All + Format: MBZ + 5:4 Triangle Strip/List Provoking Vertex Select + Project: All + Format: U2 enumerated type + + + This field selects which vertex of a triangle (in a triangle strip or list primitive) is considered the + “provoking vertex”. + Value Name Project + 0h Vertex 0 All + 1h Vertex 1 All + 2h Vertex 2 All + 3h Reserved All + 3:2 Line Strip/List Provoking Vertex Select + Project: All + Format: U2 enumerated type + + + This field selects which vertex of a line (in a line strip or list primitive) is considered the “provoking + vertex”. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 221 + 3DSTATE_CLIP + Value Name Project + 0h Vertex 0 All + 1h Vertex 1 All + 2h Reserved All + 3h Reserved All + 1:0 Triangle Fan Provoking Vertex Select + Project: All + Format: U32 enumerated type + + + This field selects which vertex of a triangle (in a triangle fan primitive) is considered the “provoking + vertex”. + Value Name Project + 0h Vertex 0 All + 1h Vertex 1 All + 2h Vertex 2 All + 3h Reserved All +3 31:28 Reserved + Project: All + Format: MBZ + 27:17 Minimum Point Width + Project: All + Format: U8.3 pixels + + + This value is used to clamp read-back PointWidth values. + + 16:6 Maximum Point Width + Project: All + Format: U8.3 pixels + + + This value is used to clamp read-back PointWidth values. + + 5 Force Zero RTAIndex Enable + Project: All + Format: Enable + If set, the Clip unit will ignore the read-back RTAIndex and operate as if the value 0 was read-back. If + clear, the read-back value is used. + + 4 Reserved + Project: All + Format: MBZ + 3:0 Maximum VPIndex + Project: All + Format: U4-1 index value (# of viewports) + + + This field specifies the maximum valid VPIndex value, corresponding to the number of active viewports. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 222 + 3DSTATE_CLIP + If the source of the VPIndex exceeds this maximum value, a VPIndex value of 0 is passed down the + pipeline. Note that this clamping does not affect a VPIndex value stored in the URB. + + + + +9.4 Object Staging +The CLIP unit’s Object Staging Buffer (OSB) accepts streams of input vertex information packets, along +with each vertex’s VertexClipTest result (outCode). This information is buffered until a complete object or +the last vertex of the primitive topology is received. The OSB then performs the ClipDetermination +function on the object vertices, and takes the actions required by the results of that function. + + +9.4.1 Partial Object Removal +The OSB is responsible for removing incomplete LINESTRIP and TRISTRIP objects that it may receive +from the preceding stage (GS). Partial object removal is not supported for other primitive types due to +either (a) the GS is not permitted to output those primitive types (e.g., primitives with adjacency info), and +the VF unit will have removed the partial objects as part of 3DPRIMITIVE processing, or (b) although the +GS thread is allowed to output the primitive type (e.g., LINELIST), it is assumed that the GS kernel will be +correctly implemented to avoid outputting partial objects (or pipeline behavior is UNDEFINED). +An object is considered ‘partial’ if the last vertex of the primitive topology is encountered (i.e., PrimEnd is +set) before a complete set of vertices for that object have been received. Given that only LINESTRIP and +TRISTRIP primitive types are subject to CLIP unit partial object removal, the only supported cases of +partial objects are 1-vertex LINESTRIPs and 1 or 2-vertex TRISTRIPs. + + +9.4.2 ClipDetermination Function +In ClipDetermination, the vertex outcodes of the primitive are combined in order to determine the clip +status of the object (TR: trivially reject; TA: trivial accept; MC: must clip; BAD: invalid coordinate). Only +those vertices included in the object are examined (3 vertices for a triangle, 2 for a line, and 1 for a point). +The outcode bit arrays for the vertices are separately ANDed (intersection) and ORed (union) together +(across vertices, not within the array) to yield objANDCode and objORCode bit arrays. +TR/TA against interesting boundary subsets are then computed. The TR status is computed as the logical +OR of the appropriate objANDCode bits, as the vertices need only be outside of one common boundary +to be trivially rejected. The TA status is computed as the logical NOR of the appropriate objORCode bits, +as any vertex being outside of any of the boundaries prevents the object from being trivially accepted. +If any vertex contains a BAD coordinate, the object is considered BAD and any computed TR/TA results +will effectively be ignored in the final action determination. +Next, the boundary subset TR/TA results are combined to determine an overall status of the object. If the +object is TR against any viewport or enabled UC plane, the object is considered TR. Note that, by +definition, being TR against a VPXY boundary implies that the vertices will be TR agains the +corresponding GB boundary, so computing TR_GB is unnecessary. +The treatment of the UCF outcodes is conditional on the UserClipFlags MustClip Enable state. If +DISABLED, an object that is not TR against the UCFs is considered TA against them. Put another way, +objects will only be culled (not clipped) with respect to the UCFs. If ENABLED, the UCF outcodes are + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 223 + treated like the other outcodes, in that they are used to determine TR, TA or MC status, and an object can +be passed to a CLIP thread simply based on it straddling a UCF. +Finally, the object is considered MC if it is neither TR or TA. +The following logic is used to compute the final TR, TA, and MC status. +// +// ClipDetermination +// +// +// Compute objANDCode and objORCode +// +switch (object type) { +case POINT: +{ +objANDCode[…] = v0.outCode[…] +objORCode[…] = v0.outCode[…] +} break +case LINE: +{ +objANDCode[…] = v0.outCode[…] & v1.outCode[…] +objORCode[…] = v0.outCode[…] | v1.outCode[…] +} break +case TRIANGLE: +{ +objANDCode[…] = v0.outCode[…] & v1.outCode[…] & v2.outCode[…] + +objORCode[…] = v0.outCode[…] | v1.outCode[…] | v2.outCode[…] +} break +// +// Determine TR/TA against interesting boundary subsets +// +TR_VPXY = (objANDCode[VP_L] | objANDCode[VP_R] | objANDCode[VP_T] | +objANDCode[VP_B]) +TR_GB = (objANDCode[GB_L] | objANDCode[GB_R] | objANDCode[GB_T] | +objANDCode[GB_B]) +TA_GB = !(objORCode[GB_L] | objORCode[GB_R] | objORCode[GB_T] | +objORCode[GB_B]) +TA_VPZ = !(objORCode[VP_N] | objORCode[VP_Z]) + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 224 + TR_VPZ = (objANDCode[VP_N] | objANDCode[VP_Z]) +TA_UC = !(objORCode[UC0] | objORCode[UC1] | … | objORCode[UC7]) +TR_UC = (objANDCode[UC0] | objANDCode[UC1] | … | objANDCode[UC7]) +BAD = objORCode[BAD] +TA_NEGW = !objORCode[NEGW] +TR_NEGW = objANDCode[NEGW] +// +// Trivial Reject +// +// An object is considered TR if all vertices are TR against any common +boundary +// Note that this allows the case of the VPXY being outside the GB +// +TR = TR_GB || TR_VPXY || TR_VPZ || TR_UC || TR_NEGW +// +// Trivial Accept +// +// For an object to be TA, it must be TA against the VPZ and GB, not TR, +// and considered TA against the UC planes and NEGW +// If the UCMC mode is disabled, an object is considered TA against the UC +// as long as it isn’t TR against the UC. +// If the UCMC mode is enabled, then the object really has to be TA against +the UC +// to be considered TA +// In this way, enabling the UCMC mode will force clipping if the object is +neither +// TA or TR against the UC +// +TA = !TR && TA_GB && TA_VPZ && TA_NEGW +UCMC = CLIP_STATE.UserClipFlagsMustClipEnable +TA = TA && ( (UCMC && TA_UC) || (!UCMC && !TR_UC) ) +// +// MustClip +// This is simply defined as not TA or TR +// Note that exactly one of TA, TR and MC will be set +// + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 225 + MC = !(TA || TR) + + +9.4.3 ClipMode +The ClipMode state determines what action the CLIP unit takes given the results of ClipDetermination. +The possible actions are: + +  PASSTHRU: Pass the object directly down the pipeline. A CLIP thread is not spawned. +  DISCARD: Remove the object from the pipeline and dereference object vertices as required (i.e., + dereferencing will not occur if the vertices are shared with other objects). +  SPAWN: Pass the object to a CLIP thread. In the process of initiating the thread, the object vertices + may be dereferenced. + +The following logic is used to determine what to do with the object (PASSTHRU or DISCARD or SPAWN). +// +// Use the ClipMode to determine the action to take + // +switch (CLIP_STATE.ClipMode) { +case NORMAL: { +PASSTHRU = TA && !BAD +DISCARD = TR || BAD +SPAWN = MC && !BAD + } + case CLIP_ALL: { +PASSTHRU = 0 +DISCARD = 0 +SPAWN = 1 + } + case CLIP_NOT_REJECT: { +PASSTHRU = 0 +DISCARD = TR || BAD +SPAWN = !(TR || BAD) + } + case REJECT_ALL: { +PASSTHRU = 0 +DISCARD = 1 +SPAWN = 0 + } + case ACCEPT_ALL: { +PASSTHRU = !BAD + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 226 + DISCARD = BAD +SPAWN = 0 + } +} endswitch + +9.4.3.1 NORMAL ClipMode +In NORMAL mode, objects will be discarded if TR or BAD, passed through if TA, and passed to a CLIP +thread if MC. Those mode is typically used when the CLIP kernel is only used to perform 3D Clipping (the +expected usage model). + +9.4.3.2 CLIP_ALL ClipMode +In CLIP_ALL mode, all objects (regardless of classification) will be passed to CLIP threads. Note that this +includes BAD objects. This mode can be used to perform arbritrary processing in the CLIP thread, or as a +backup if for some reason the CLIP unit fixed functions (VertexClipTest, ClipDetermination) are not +sufficient for controlling 3D Clipping. + +9.4.3.3 CLIP_NON_REJECT ClipMode +This mode is similar to CLIP_ALL mode, but TR and BAD objects are discarded an all other (TA, MC) +objects are passed to CLIP threads. Usage of this mode assumes that the CLIP unit fixed functions +(VertexClipTest, ClipDetermination) are sufficient at least in respect to determining trivial reject. + +9.4.3.4 REJECT_ALL ClipMode +In REJECT_ALL mode, all objects (regardless of classification) are discarded. This mode effectively clips +out all objects. + +9.4.3.5 ACCEPT_ALL ClipMode +In ACCEPT_ALL mode, all non-BAD objects are passed directly down the pipeline. This mode partially +disables the CLIP stage. BAD objects will still be discarded, and incomplete primitives (generated by a +GS thread) will be discarded. +Primitive topologies with adjacency are also handled, in that the adjacent-only vertices are dereferenced +and only non-adjacent objects are passed down the pipeline. This condition can arise when primitive +topologies with adjacency are generated but the GS stage is disabled. If this condition is allowed, the +CLIP stage must not be completely disabled – as this would allow adjacent vertices to pass through the +CLIP stage and lead to UNPREDICATBLE results as the rest of the pipeline does not comprehend +adjacency. + + +9.5 Object Pass-Through +Depending on ClipMode, objects may be passed directly down the pipeline. The PrimTopologyType +associated with the output objects may differ from the input PrimTopologyType, as shown in the table +below. +Programming Note: The CLIP unit does not tolerate primitives with adjacency that have “dangling +vertices”. This should not be an issue under normal conditions, as the VF unit will not generate these + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 227 + sorts of primitives and the GS thread is restricted (though by specification only) to not output these sorts +of primitives. + + Input Pass-Through Output + PrimTopologyType PrimTopologyType + Notes +POINTLIST POINTLIST +POINTLIST_BF POINTLIST_BF +LINELIST LINELIST +LINELIST_ADJ LINELIST + Adjacent vertices removed. + +LINESTRIP LINESTRIP +LINESTRIP_ADJ LINESTRIP + Adjacent vertices removed. + +LINESTRIP_BF LINESTRIP_BF +LINESTRIP_CONT LINESTRIP_CONT +LINESTRIP_CONT_BF LINESTRIP_CONT_BF +LINELOOP N/A + Not supported after GS. + +TRILIST TRILIST +RECTLIST RECTLIST +TRILIST_ADJ TRILIST + Adjacent vertices removed. + +TRISTRIP TRISTRIP or + Depends on where the incoming strip is broken (if at all) by + TRISTRIP_REV + discarded or clipped objects + See Tristrip Clipping Errata subsection. + +TRISTRIP_REV TRISTRIP or + Depends on where the incoming strip is broken (if at all) by + TRISTRIP_REV + discarded or clipped objects + See Tristrip Clipping Errata subsection. + +TRISTRIP_ADJ TRISTRIP or + Depends on where the incoming strip is broken (if at all) by + TRISTRIP_REV + discarded or clipped objects + Adjacent vertices removed. + See Tristrip Clipping Errata subsection. + +TRIFAN TRIFAN +TRIFAN_NOSTIPPLE TRIFAN_NOSTIPPLE +POLYGON POLYGON +QUADLIST N/A + Not supported after GS. + +QUADSTRIP N/A + Not supported after GS. + + + +9.6 Primitive Output +(This section refers to output from the CLIP unit to the pipeline, not output from the CLIP thread) +The CLIP unit will output primitives (either passed-through or generated by a CLIP thread) in the proper +order. This includes the buffering of a concurrent CLIP thread’s output until the preceding CLIP thread +terminates. Note that the requirement to buffer subsequent CLIP thread output until the preceding CLIP + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 228 + thread terminates has ramifications on determining the number of VUEs allocated to the CLIP unit and +the number of concurrent CLIP threads allowed. + + +9.7 Other Functionality + +9.7.1 Statistics Gathering +The CLIP unit includes logic to assist in the gathering of certain pipeline statistics, primarily in support of +the Asynchronous Query function of the APIs. The statistics take the form of MI counter registers (see +Memory Interface Registers), where the CLIP unit provides signals causing those counters to increment. +Software is responsible for controlling (enabling) these counters in order to provide the required statistics +at the DDI level. For example, software might need to disable the statistics gathering before submitting +non-API-visible objects (e.g., RECTLISTs) for processing. +The CLIP unit must be ENABLED (via the CLIP Enable bit of PIPELINED_STATE_POINTERS) in order +to it to affect the statistics counters. This might lead to a pathological case where the CLIP unit needs to +be ENABLED simply to provide statistics gathering. If no clipping functionality is desired, Clip Mode can +be set to ACCEPT_ALL to effectively inhibit clipping while leaving the CLIP stage ENABLED. +The two statistics the CLIP unit affects (if enabled) are: + +  CL_INVOCATION_COUNT: +  Incremented for every object received from the GS stage. + +9.7.1.1 CL_INVOCATION_COUNT +If the Statistics Enable bit (CLIP_STATE) is set, the CLIP unit increments the +CL_INVOCATION_COUNT register for every complete object received from the GS stage. +In order to maintain a count of application-generated objects, software will need to clear the CLIP unit’s +Statistic Enable whenever driver-generated objects are rendered. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 229 + 10. 3D Pipeline - Strips and Fans (SF) + Stage +10.1 Overview +The Strips and Fan (SF) stage of the 3D pipeline is responsible for performing “setup” operations required +to rasterize 3D objects. + + +10.1.1 Inputs from CLIP +The following table describes the per-vertex inputs passed to the SF unit from the previous (CLIP) stage +of the pipeline. + +SF’s Vertex Pipeline Inputs + Variable Type Description +primType enum + Type of primitive topology the vertex belongs to. Primitive Assembly for a list of + primitive types supported by the SF unit. See 3D Pipeline for descriptions of these + topologies. + Notes: + The CLIP unit will convert any primitive with adjacency (3DPRIMxxx_ADJ) it + receives from the pipeline into the corresponding primitive without adjacency + (3DPRIMxxx). + QUADLIST, QUADSTRIP, LINELOOP primitives are not supported by the SF unit. + Software must use a GS thread to convert these to some other (supported) + primitive type. + If an object is clipped by the hardware clipper, the CLunit would force this field to + “3DPRIM_POLYGON”. SFunit would process this incoming object just as it would + any other “3DPRIM_POLYGON”. SFunit selects vertex 0 as the provoking vertex. + +primStart,primEnd boolean Indicate vertex’s position within the primitive topology +vInX[] float Vertex X position (screen space or NDC space) +vInY[] float Vertex Y position (screen space or NDC space) +vInZ[] float Vertex Z position (screen space or NDC space) +vInInvW[] float Reciprocal of Vertex homogeneous (clip space) W +hVUE[] URB Points to the vertex’s data stored in the URB (one VUE handle per vertex) + address +renderTargetArrayIndex uint + Index of the render target (array element or 3D slice), clamped to 0 by the GS unit + if the max value was exceeded. + If this vertex is the leading vertex of an object within the primitive topology, this + value will be associated with that object in subsequent processing. + +viewPortIndex uint + Index of a viewport transform matrix within the SF_VIEWPORT structure used to + perform Viewport Transformation on object vertices and scissor operations on an + object. + If this vertex is the leading vertex of an object within the primitive topology, this + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 230 + Variable Type Description + value will be associated with that object in the Viewport Transform and Scissor + subfunctions, otherwise the value is ignored. Note that for primitive topologies with + vertices shared between objects, this means a shared vertex may be subject to + multiple Viewport Transformation operations if the viewPortIndex varies within the + topology. +pointSize uint If this vertex is within a POINTLIST[_BF] primitive topology, this value specifies the + screen space size (width,height) of the square point to be rasterized about the + vertex position. Otherwise the value is ignored. + + +10.1.2 Attribute Setup/Interpolation Process +The following sections describe the Attribute Setup/Interpolation Process. + +10.1.2.1 Attribute Setup/Interpolation Process +Hardware computes all needed parameters, as there is no setup thread. + + +10.1.3 Outputs to WM +The outputs from the SF stage to the WM stage are mostly comprised of implementation-specific +information required for the rasterization of objects. The types of information is summarized below, but as +the interface is not exposed to software a detailed discussion is not relevant to this specification. + +  PrimType of the object +  VPIndex, RTAIndex associated with the object +  Coefficients for Z, 1/W, perspective and non-perspective b1 and b2 per vertex, and attribute vertex + deltas a0, a1, and a2 per attribute. +  Information regarding the X,Y extent of the object (e.g., bounding box, etc.). +  Edge or line interpolation information (e.g., edge equation coefficients, etc.). +  Information on where the WM is to start rasterization of the object. +  Object orientation (front/back-facing). +  Last Pixel indication (for line drawing). + + +10.2 Primitive Assembly +The first subfunction within the SF unit is Primitive Assembly. Here 3D primitive vertex information is +buffered and, when a sufficient number of vertices are received, converted into basic 3D objects which +are then passed to the Viewport Transformation subfunction. +The number of vertices passed with each primitive is constrained by the primitive type. Primitive Assembly. +Passing any other number of vertices results in UNDEFINED behavior. Note that this restriction only +applies to primitive output by GS threads (which is under control of the GS kernel). See the Vertex Fetch +chapter for details on how the VF unit automatically removes incomplete objects resulting from +processing a 3DPRIMITIVE command. + +SF-Supported Primitive Types & Vertex Count Restrictions + primType VertexCount Restriction +3DPRIM_TRILIST nonzero multiple of 3 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 231 + primType VertexCount Restriction + >=3 +3DPRIM_TRISTRIP +3DPRIM_TRISTRIP_REVERSE + >=3 +3DPRIM_TRIFAN +3DPRIM_TRIFAN_NOSTIPPLE +3DPRIM_POLYGON + +3DPRIM_LINELIST nonzero multiple of 2 + >=2 +3DPRIM_LINESTRIP +3DPRIM_LINESTRIP_CONT +3DPRIM_LINESTRIP_BF +3DPRIM_LINESTRIP_CONT_BF +3DPRIM_RECTLIST nonzero multiple of 3 + nonzero +3DPRIM_POINTLIST +3DPRIM_POINTLIST_BF + +Primitive Assembly for a list of the 3D object types. + +3D Object Types + objectType generated by primType Vertices/Object +3DOBJ_POINT 1 + 3DPRIM_POINTLIST + 3DPRIM_POINTLIST_BF + +3DOBJ_LINE 2 + 3DPRIM_LINELIST + 3DPRIM_LINESTRIP + 3DPRIM_LINESTRIP_CONT + 3DPRIM_LINESTRIP_BF + 3DPRIM_LINESTRIP_CONT_BF +3DOBJ_TRIANGLE 3 + 3DPRIM_TRILIST + 3DPRIM_TRISTRIP + 3DPRIM_TRISTRIP_REVERSE + 3DPRIM_TRIFAN + 3DPRIM_TRIFAN_NOSTIPPLE + 3DPRIM_POLYGON +3DOBJ_RECTANGLE 3 (expanded to 4 in RectangleCompletion) + 3DPRIM_RECTLIST + +Primitive Assembly for the outputs of Primitive Decomposition. + +Primitive Decomposition Outputs + Variable Type Description + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 232 + Variable Type Description +objectType enum + Type of object. Primitive Assembly + +nV uint + The number of object vertices passed to Object Setup. Primitive Assembly + +v[0..nV-1]* various + Data arrays associated with object vertices. Data in the array consists of X, Y, Z, invW + and a pointer to the other vertex attributes. These additional attributes are not used by + directly by the 3D fixed functions but are made available to the SF thread. The number of + valid vertices depends on the object type. Primitive Assembly + +invertOrientation enum Indicates whether the orientation (CW or CCW winding order) of the vertices of a triangle + object should be inverted. Ignored for non-triangle objects. +backFacing enum Valid only for points and line objects, indicates a back facing object. This is used later for + culling. +provokingVtx uint + Specifies the index (into the v[] arrays) of the vertex considered the “provoking” vertex + (for flat shading). The selection of the provoking vertex is programmable via SF_STATE + (xxx Provoking Vertex Select state variables.) + +polyStippleEnable boolean TRUE if Polygon Stippling is enabled. FALSE for TRIFAN_NOSTIPPLE. Ignored for non- + triangle objects. +continueStipple boolean Only applies to line objects. TRUE if Line Stippling should be continued (i.e., not reset) + from where the previous line left off. If FALSE, Line Stippling is reset for each line object. +renderTargetIndex uint Index of the render target (array element or 3D slice), clamped to 0 by the GS unit if the + max value was exceeded. This value is simply passed in SF thread payloads and not + used within the SF unit. +viewPortIndex uint Index of a viewport transform matrix within the SF_VIEWPORT structure used to perform + Viewport Transformation on object vertices and scissor operations on an object. +pointSize unit For point objects, this value specifies the screen space size (width,height) of the square + point to be rasterized about the vertex position. Otherwise the value is ignored. + +The following table defines, for each primitive topology type, which vertex’s VPIndex/RTAIndex applies to +the objects within the topology. + +VPIndex/RTAIndex Selection + + PrimTopologyType Viewport Index Usage + +POINTLIST Each vertex supplies the VPIndex for the corresponding point object +POINTLIST_BF +LINELIST + The leading vertex of each line supplies the VPIndex for the corresponding line object. + V0.VPIndex Line(V0,V1) + V2.VPIndex Line(V2,V3) + … + + LINESTRIP The leading vertex of each line segment supplies the VPIndex for the corresponding line + object. + LINESTRIP_BF + V0.VPIndex Line(V0,V1) + LINESTRIP_CONT + V1.VPIndex Line(V1,V2) + LINESTRIP_CONT_BF + … + NOTE: If the VPIndex changes within the topology, shared vertices will be processed + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 233 + (mapped) multiple times. + +TRILIST The leading vertex of each triangle/rect supplies the VPIndex for the corresponding + triangle/rect objects. +RECTLIST + V0.VPIndex Tri(V0,V1,V2) + V3.VPIndex Tri(V3,V4,V5) + … + +TRISTRIP The leading vertex of each triangle supplies the VPIndex for the corresponding triangle + object. +TRISTRIP_REVERSE + V0.VPIndex Tri(V0,V1,V2) + V1.VPIndex Tri(V1,V2,V3) + … + NOTE: If the VPIndex changes within the primitive, shared vertices will be processed + (mapped) multiple times. + The first vertex (V0) supplies the VPIndex for all triangle objects. +TRIFAN +TRIFAN_NOSTIPPLE +POLYGON + + + +10.2.1 Point List Decomposition +The 3DPRIM_POINTLIST and 3DPRIM_POINTLIST_BACKFACING primitives specify a list of +independent points. + +3DPRIM_POINTLIST Primitive + + + + +The decomposition process divides the list into a series of basic 3DOBJ_POINT objects that are then +passed individually and in order to the Object Setup subfunction. The provokingVertex of each object is, by +definition, v[0]. +Points have no winding order, so the primitive command is used to explicitly state whether they are back- +facing or front-facing points. Primitives of type 3DPRIM_POINTLIST_BACKFACING are decomposed +exactly the same way as 3DPRIM_POINTLIST primitives, but the backFacing variable is set for resulting +point objects being passed on to object setup. +PointListDecomposition() { + +objectType = 3DOBJ_POINT + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 234 + nV = 1 + +provokingVtx = 0 +if (primType == 3DPRIM_POINTLIST) + + backFacing = FALSE +else // primType == 3DPRIM_POINTLIST_BACKFACING + + backFacing = TRUE +for each (vertex I in [0..vertexCount-1]) { + +v[0] vIn[i]// copy all arrays (e.g., v[]X, v[]Y, etc.) +ObjectSetup() + +} +} + + +10.2.2 Line List Decomposition +The 3DPRIM_LINELIST primitive specifies a list of independent lines. + +3DPRIM_LINELIST Primitive + + + + +The decomposition process divides the list into a series of basic 3DOBJ_LINE objects that are then +passed individually and in order to the Object Setup stage. The lines are generated with the following +object vertex order: v0, v1; v2, v3; and so on. The provokingVertex of each object is taken from the Line +List/Strip Provoking Vertex Select state variable, as programmed via SF_STATE. +LineListDecomposition() { + +objectType = 3DOBJ_LINE +nV = 2 +provokingVtx = Line List/Strip Provoking Vertex Select +continueStipple = FALSE +for each (vertex I in [0..vertexCount-2] by 2) { + +v[0] arrays vIn[i] arrays +v[1] arrays vIn[i+1] arrays +ObjectSetup() + +} + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 235 + } + + +10.2.3 Line Strip Decomposition +The 3DPRIM_LINESTRIP, 3DPRIM_LINESTRIP_CONT, 3DPRIM_LINESTRIP_BF, and +3DPRIM_LINESTRIP_CONT_BF primitives specify a list of connected lines. + +3DPRIM_LINESTRIP_xxx Primitive + + + + +The decomposition process divides the strip into a series of basic 3DOBJ_LINE objects that are then +passed individually and in order to the Object Setup stage. The lines are generated with the following +object vertex order: v0,v1; v1,v2; and so on. The provokingVertex of each object is taken from the Line +List/Strip Provoking Vertex Select state variable, as programmed via SF_STATE. +Lines have no winding order, so the primitive command is used to explicitly state whether they are back- +facing or front-facing lines. Primitives of type 3DPRIM_LINESTRIP[_CONT]_BF are decomposed exactly +the same way as 3DPRIM_LINESTRIP[_CONT] primitives, but the backFacing variable is set for the +resulting line objects being passed on to object setup. Likewise 3DPRIM_LINESTRIP_CONT[_BF] +primitives are decomposed identically to basic line strips, but the continueStipple variable is set to true so +that the line stipple pattern will pick up from where it left off with the last line primitive, rather than being +reset. +LineStripDecomposition() { + +objectType = 3DOBJ_LINE + +nV = 2 + +provokingVtx = Line List/Strip Provoking Vertex Select +if (primType == 3DPRIM_LINESTRIP) { + + backFacing = FALSE + continueStipple = FALSE +} else if (primType == 3DPRIM_LINESTRIP_BF) { + + backFacing = TRUE + continueStipple = FALSE +} else if (primType == 3DPRIM_LINESTRIP_CONT) { + + backFacing = FALSE + continueStipple = TRUE +} else if (primType == 3DPRIM_LINESTRIP_CONT_BF) { + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 236 + backFacing = TRUE + continueStipple = TRUE + + } + +for each (vertex I in [0..vertexCount-1]) { + +v[0] arrays vIn[i] arrays +v[1] arrays vIn[i+1] arrays +ObjectSetup() +continueStipple = TRUE + + } + +} + + +10.2.4 Triangle List Decomposition +The 3DPRIM_TRILIST primitive specifies a list of independent triangles. + +3DPRIM_TRILIST Primitive + + + + +The decomposition process divides the list into a series of basic 3DOBJ_TRIANGLE objects that are then +passed individually and in order to the Object Setup stage. The triangles are generated with the following +object vertex order: v0,v1,v2; v3,v4,v5; and so on. The provokingVertex of each object is taken from the +Triangle List/Strip Provoking Vertex Select state variable, as programmed via SF_STATE. +TriangleListDecomposition() { + +objectType = 3DOBJ_TRIANGLE + + nV = 3 + +invertOrientation = FALSE +provokingVtx = Triangle List/Strip Provoking Vertex Select +polyStippleEnable = TRUE +for each (vertex I in [0..vertexCount-3] by 3) { + +v[0] arrays vIn[i] arrays +v[1] arrays vIn[i+1] arrays +v[2] arrays vIn[i+2] arrays + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 237 + ObjectSetup() + +} +} + + +10.2.5 Triangle Strip Decomposition +The 3DPRIM_TRISTRIP and 3DPRIM_TRISTRIP_REVERSE primitives specify a series of triangles +arranged in a strip, as illustrated below. + +3DPRIM_TRISTRIP[_REVERSE] Primitive + + + + +The decomposition process divides the strip into a series of basic 3DOBJ_TRIANGLE objects that are +then passed individually and in order to the Object Setup stage. The triangles are generated with the +following object vertex order: v0,v1,v2; v1,v2,v3; v2,v3,v4; and so on. Note that the winding order of the +vertices alternates between CW (clockwise), CCW (counter-clockwise), CW, etc. The provokingVertex of +each object is taken from the Triangle List/Strip Provoking Vertex Select state variable, as +programmed via SF_STATE. +The 3D pipeline uses the winding order of the vertices to distinguish between front-facing and back-facing +triangles (Triangle Orientation Face Culling below). Therefore, the 3D pipeline must account for the +alternation of winding order in strip triangles. The invertOrientation variable is generated and used for this +purpose. +To accommodate the situation where the driver is forced to break an input strip primitive into multiple +tristrip primitive commands (e.g., due to ring or batch buffer size restrictions), two tristrip primitive types +are supported. 3DPRIM_TRISTRIP is used for the initial section of a strip, and wherever a continuation of +a strip starts with a triangle with a CW winding order. 3DPRIM_TRISTRIP_REVERSE is used for a +continuation of a strip that starts with a triangle with a CCW winding order. +TriangleStripDecomposition() { + +objectType = 3DOBJ_TRIANGLE + +nV = 3 + +provokingVtx = Triangle List/Strip Provoking Vertex Select +if (primType == 3DPRIM_TRISTRIP) + + invertOrientation = FALSE +else // primType == 3DPRIM_TRISTRIP_REVERSE + + invertOrientation = TRUE +polyStippleEnable = TRUE + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 238 + for each (vertex I in [0..vertexCount-3]) { + +v[0] arrays vIn[i] arrays +v[1] arrays vIn[i+1] arrays +v[2] arrays vIn[i+2] arrays +ObjectSetup() +invertOrientation = ! invertOrientation + +} +} + + +10.2.6 Triangle Fan Decomposition +The 3DPRIM_TRIFAN and 3DPRIM_TRIFAN_NOSTIPPLE primitives specify a series of triangles +arranged in a fan, as illustrated below. + +3DPRIM_TRIFAN Primitive + + + + +The decomposition process divides the fan into a series of basic 3DOBJ_TRIANGLE objects that are then +passed individually and in order to the Object Setup stage. The triangles are generated with the following +object vertex order: v0,v1,v2; v0,v2,v3; v0,v3,v4; and so on. As there is no alternation in the vertex +winding order, the invertOrientation variable is output as FALSE unconditionally. The provokingVertex of +each object is taken from the Triangle Fan Provoking Vertex state variable, as programmed via +SF_STATE. +Primitives of type 3DPRIM_TRIFAN_NOSTIPPLE are decomposed exactly the same way, except the +polyStippleEnable variable is FALSE for the resulting objects being passed on to object setup. This will +inhibit polygon stipple for these triangle objects. +TriangleFanDecomposition() { + +objectType = 3DOBJ_TRIANGLE + +nV = 3 + +invertOrientation = FALSE +provokingVtx = Triangle Fan Provoking Vertex Select +if (primType == 3DPRIM_TRIFAN) + + polyStippleEnable = TRUE +else // primType == 3DPRIM_TRIFAN_NOSTIPPLE + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 239 + polyStippleEnable = FALSE +v[0] arrays vIn[0] arrays// the 1st vertex is common +for each (vertex I in [1..vertexCount-2]) { + +v[1] arrays vIn[i] arrays +v[2] arrays vIn[i+1] arrays +ObjectSetup() + +} +} + + +10.2.7 Polygon Decomposition +The 3DPRIM_POLYGON primitive is identical to the 3DPRIM_TRIFAN primitive with the exception that +the provokingVtx is overridden with 0. This support has been added specifically for OpenGL support, +avoiding the need for the driver to change the provoking vertex selection when switching between trifan +and polygon primitives. + + +10.2.8 Rectangle List Decomposition +The 3DPRIM_RECTLIST primitive command specifies a list of independent, axis-aligned rectangles. Only +the lower right, lower left, and upper left vertices (in that order) are included in the command – the upper +right vertex is derived from the other vertices (in Object Setup). + +3DPRIM_RECTLIST Primitive + + + + +The decomposition of the 3DPRIM_RECTLIST primitive is identical to the 3DPRIM_TRILIST +decomposition, with the exception of the objectType variable. +RectangleListDecomposition() { + +objectType = 3DOBJ_RECTANGLE + +nV = 3 + +invertOrientation = FALSE +provokingVtx = 0 +for each (vertex I in [0..vertexCount-3] by 3) { + +v[0] arrays vIn[i] arrays + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 240 + v[1] arrays vIn[i+1] arrays +v[2] arrays vIn[i+2] arrays +ObjectSetup() + +} +} + + + +10.3 Object Setup +The Object Setup subfunction of the SF stage takes the post-viewport-transform data associated with +each vertex of a basic object and computes various parameters required for scan conversion. This +includes generation of implied vertices, translations and adjustments on vertex positions, and culling +(removal) of certain classes of objects. The final object information is passed to the Windower/Masker +(WM) stage where the object is rasterized into pixels. + + +10.3.1 Invalid Position Culling (Pre/Post-Transform) +At input the the SF stage, any objects containing a floating-point NaN value for Position X, Y, Z, or RHW +will be unconditionally discarded. Note that this occurs on an object (not primitive) basis. +If Viewport Transformation is enabled, any objects containing a floating-point NaN value for post- +transform Position X, Y or Z will be unconditionally discarded. + + +10.3.2 Viewport Transformation +If the Viewport Transform Enable bit of SF_STATE is ENABLED, a viewport transformation is applied to +each vertex of the object. +The VPIndex associated with the leading vertex of the object is used to obtain the Viewport Matrix +Element data from the corresponding element of the SF_VIEWPORT structure in memory. For each +object vertex, the following scale and translate transformation is applied to the position coordinates: +x’ = m00 * x + m30 +y’ = m11 * y + m31 +z’ = m22 * z + m32 +Software is responsible for computing the matrix elements from the viewport information provided to it +from the API. + + +10.3.3 Destination Origin Bias +The positioning of the pixel sampling grid is programmable and is controlled by the Destination Origin +Horizontal/Vertical Bias state variables (set via SF_STATE). If these bias values are both 0, pixels are +sampled on an integer grid. Pixel (0,0) will be considered inside the object if the sample point at XY +coordinate (0,0) falls within the primitive. +If the bias values are both 0.5, pixels are sampled on a “half” integer grid (i.e., X.5, Y.5). Pixel (0,0) will be +considered inside the object if the sample point at XY coordinate (0.5,0.5) falls within the primitive. This +positioning of the sample grid corresponds with the OpenGL rasterization rules, where “fragment centers” +lay on a half-integer grid. It also corresponds with the Intel740 rasterizer (though that device did not +employ “top left” rules). + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 241 + Note that subsequent descriptions of rasterization rules for the various objects will be with reference to +the pixel sampling grid. + +Destination Origin Bias + + + + +10.3.4 Point Rasterization Rule Adjustment +POINT objects are rasterized as square RECTANGLEs, with one exception: The Point Rasterization +Rule state variable (in SF_STATE) controls the rendering of point object edges that fall directly on pixel +sample points, as the treatment of these edge pixels varies between APIs. +The following diagram shows the rasterization of a 2-pixel wide point centered at (2,2) given current DX +rasterization rules (where changed the rasterization of points to match the rasterization of an identical +(square) polygon). Here the pixel sample grid coincides with the integer pixel coordinates, and the Point +Rasterization Rule is set to RASTRULE_UPPER_LEFT. Note that the pixels which lie only on the upper +and/or left edges are lit. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 242 + RASTRULE_UPPER_LEFT + + + + +10.3.5 Drawing Rectangle Offset Application +The Drawing Rectangle Offset subfunction offsets the object’s vertex X,Y positions by the pixel-exact, +unclipped drawing rectangle origin (as programmed via the Drawing Rectangle Origin X,Y values in the +3DSTATE_DRAWING_RECTANGLE command). The Drawing Rectangle Offset subfunction (at least with +respect to Color Buffer access) is , and therefore to (effectively) turn off the +offset function the origin would need to be set to (0,0). A non-zero offset is typically specified when +window-relative or viewport-relative screen coordinates are input to the device. Here the drawing +rectangle origin would be loaded with the absolute screen coordinates of the window’s or viewport’s +upper-left corner. +Clipping of objects which extend outside of the Drawing Rectangle occurs later in the pipeline. Note that +this clipping is based on the “clipped” draw rectangle (as programmed via the Clipped Drawing +Rectangle values in the 3DSTATE_DRAWING_RECTANGLE command), which must be clamped by +software to the rendertarget boundaries. The unclipped drawing rectangle origin, however, can extend +outside the screen limits in order to support windows whose origins are moved off-screen. This is +illustrated in the following diagrams. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 243 + Onscreen Draw Rectangle + + + + +Partially-offscreen Draw Rectangle + + + + +10.3.5.1 3DSTATE_DRAWING_RECTANGLE + + 3DSTATE_DRAWING_RECTANGLE +Project: All +Source: RenderCS +Length Bias: 2 +The 3DSTATE_DRAWING_RECTANGLE command is used to set the 3D drawing rectangle and related state. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 00h 3DSTATE_DRAWING_RECTANGLE + Format: OpCode + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 244 + 3DSTATE_DRAWING_RECTANGLE + 15:14 Reserved + + Format: MBZ + 13:8 Reserved + Format: MBZ + 7:0 DWord Length + Default Value: 2h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:16 Clipped Drawing Rectangle Y Min + Project: All + Format: U16 in Pixels from Color Buffer origin (upper left corner) + + + Specifies Ymin value of (inclusive) intersection of Drawing rectangle with the Color (Destination) Buffer, + used for clipping. Pixels with Y coordinates less than Ymin will be clipped out. + Value Name Project + [0,16383] Device ignores bits 31:30 + + + Programming Notes Project + This value can be larger than Clipped Drawing Rectangle Y Max. If Ymin>Ymax, the clipped + drawing rectangle is null, all polygons are discarded. If Ymin==Ymax, the clipped drawing + rectangle is 1 pixel wide in the Y direction. + 15:0 Clipped Drawing Rectangle X Min + Project: All + Format: U16 in Pixels from Color Buffer origin (upper left corner) + + + Specifies Xmin value of (inclusive) intersection of Drawing rectangle with the Color (Destination) Buffer, + used for clipping. Pixels with X coordinates less than Xmin will be clipped out. + Value Name Project + [0,16383] Device ignores bits 15:14 + + + Programming Notes Project + This value can be larger than Clipped Drawing Rectangle X Max. If Xmin>Xmax, the clipped + drawing rectangle is null, all polygons are discarded. If Xmin==Xmax, the clipped drawing + rectangle is 1 pixel wide in the X direction. +2 31:16 Clipped Drawing Rectangle Y Max + Project: All + Format: U16 in Pixels from Color Buffer origin (upper left corner) + + + Specifies Ymax value of (inclusive) intersection of Drawing rectangle with the Color (Destination) + Buffer, used for clipping. Pixels with coordinates greater than Ymax will be clipped out. + Value Name Project + [0,16383] Device ignores bits 31:30 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 245 + 3DSTATE_DRAWING_RECTANGLE + + Programming Notes Project + This value can be less than Clipped Drawing Rectangle Y Min. If Ymax xmax or ymin > ymax will cause all polygons to be discarded +for a given viewport (effectively a null scissor rectangle). + + +10.3.12 Line Rasterization +The device supports three styles of line rendering: zero-width (cosmetic) lines, non-antialiased lines, and +antialiased lines. (These rules also satisfy the OpenGL conformance requirements.) Non-antialiased lines +are rendered as a polygon having a specified width as measured parallel to the major axis of the line. +Antialiased lines are rendered as a rectangle having a specified width measured perpendicular to the line +connecting the vertices. +The functions required to render lines is split between the SF and WM units. The SF unit is responsible +for computing the overall geometry of the object to be rendered, including the pixel-exact bounding box, +edge equations, etc., and therefore is provided with the screen-geometry-related state variables. The WM +unit performs the actual scan conversion, determining the exact pixel included/excluded and coverage +value for anti-aliased lines. + +10.3.12.1 Zero-Width (Cosmetic) Line Rasterization +(The specification of zero-width line rasterization would be more correctly included in the WM Unit +chapter, though is being included here to keep it with the rasterization details of the other line types). +When the Line Width is set to zero, the device will use special rules to rasterize zero-width (“cosmetic”) +lines. The Anti-Aliasing Enable state variable is ignored when Line Width is zero. +When the LineWidth is set to zero, the device will use special rules to rasterize “cosmetic” lines. The +rasterization rules also comply with the OpenGL conformance requirements (for 1-pixel wide non-smooth +lines). Refer to the appropriate API specifications for details on these requirements. +The GIQ rules basically intersect the directed, ideal line connecting two endpoints with an array of +diamond-shaped areas surrounding pixel sample points. Wherever the line  a diamond +(including passing through a diamond), the corresponding pixel is lit. Special rules are used to define the +subpixel locations which are considered interior to the diamonds, as a function of the slope of the line. +When a line ends in a diamond (and therefore does not exit that diamond), the corresponding pixel is not +drawn. When a line starts in a diamond and exits that diamond, the corresponding pixel is drawn. + +10.3.12.2 1GIQ (Diamond) Sampling Rules – Legacy Mode +When the Legacy Line Rasterization Enable bit in WM_STATE is , zero-width lines are +rasterized according to the algorithm presented in this subsection. Also note that the Last Pixel Enable +bit of SF_STATE controls whether the last pixel of the last line in a LINESTRIP_xxx primitive or the last +pixel of each line in a LINELIST_xxx primitive is rendered. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 250 + Refer to the following figure, which shows the neighborhood of subpixels around a given pixel sample +point. Note that the device divides a pixel into a 16x16 array of subpixels, referenced by their upper left +corners. + + + + +The solid-colored subpixels are considered “interior” to the diamond centered on the pixel sample point. +Here the Manhattan distance to the pixel sample point (center) is less than ½. +The subpixels falling on the edges of the diamond (Manhattan distance = ½) are exclusive, with the +following exceptions: + 1. The bottom corner subpixel is always inclusive. This is to ensure that lines with slopes in + the open range (-1,1) touch a diamond even when they cross exactly between pixel diamonds. + 2. The right corner subpixel is inclusive as long as the line slope is not exactly one, in + which case the left corner subpixel is inclusive. Including the right corner subpixel ensures + that lines with slopes in the range (1, +infinity] or [-infinity, -1) touch a diamond even when they + cross exactly between pixel diamonds. Including the left corner on slope=1 lines is required for + proper handling of slope=1 lines (see (3) below) – where if the right corner was inclusive, a + slope=1 line falling exactly between pixel centers would wind up lighting pixel on both sides of + the line (not desired). + 3. The subpixels along the bottom left edge are inclusive only if the line slope = 1. This is to + correctly handle the case where a slope=1 line falls enters the diamond through a left or bottom + corner and ends on the bottom left edge. One does not consider this “passing through” the + diamond (where the normal rules would have us light the pixel). This is to avoid the following + case: One slope=1 line segment enters through one corner and ends on the edge, and another + (continuation) line segments starts at that point on the edge and exits through the other corner. + If simply passing through a corner caused the pixel to be lit, this case would case the pixel to + be lit twice – breaking the rule that connected line segments should not cause double-hits or + missing pixels. So, by considering the entire bottom left edge as “inside” for slope=1 lines, we + will only light the pixel when a line passes through the entire edge, or starts on the edge (or the + left or bottom corner) and exits the diamond. + 4. The subpixels along the bottom right edge are inclusive only if the line slope = -1. Similar + case as (3), except slope=-1 lines require the bottom right edge to be considered inclusive. +The following equation determines whether a point (point.x, point.y) is inside the diamond of the pixel +sample point (sample.x, sample.y), given additional information about the slope (slopePosOne, +slopeNegOne). +delta_x = point.x – sample.x + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 251 + delta_y = point.y – sample.y +distance = abs(delta_x) + abs(delta_y) +interior = (distance < 0.5) +bottom_corner = (delta_x == 0.0) && (delta_y == 0.5) +left_corner = (delta_x == –0.5) && (delta_y == 0.0) +right_corner = (delta_x == 0.5) && (delta_y == 0.0) +bottom_left_edge = (distance == 0.5) && (delta_x < 0) && (delta_y > 0) +bottom_right_edge = (distance == 0.5) && (delta_x > 0) && (delta_y > 0) + +inside = interior || + +bottom_corner || + +(slopePosOne ? left_corner : right_corner) || + +(slopePosOne && left_edge) || + +(slopeNegOne && right_edge) + + +10.3.12.3 GIQ (Diamond) Sampling Rules – DX10 Mode +When the Legacy Line Rasterization Enable bit in WM_STATE is , zero-width lines are +rasterized according to the algorithm presented in this subsection. Also note that the Last Pixel Enable +bit of SF_STATE controls whether the last pixel of the last line in a LINESTRIP_xxx primitive or the last +pixel of each line in a LINELIST_xxx primitive is rendered. +Refer to the following figure, which shows the neighborhood of subpixels around a given pixel sample +point. Note that the device divides a pixel into a 16x16 array of subpixels, referenced by their upper left +corners. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 252 + The solid-colored subpixels are considered “interior” to the diamond centered on the pixel sample point. +Here the Manhattan distance to the pixel sample point (center) is less than ½. +The subpixels falling on the edges of the diamond (Manhattan distance = ½) are exclusive, with the +following exceptions: +1. The bottom corner subpixel is always inclusive. This is to ensure that lines with slopes in the +open range (-1,1) touch a diamond even when they cross exactly between pixel diamonds. +2. The right corner subpixel is inclusive as long as the line is not X Major ( X Major is defined as +-1 <= slope <= 1). Including the right corner subpixel ensures that lines with slopes in the range (>1, ++infinity] or [-infinity, <-1) touch a diamond even when they cross exactly between pixel diamonds. +3. The left corner subpixel is never inclusive. For Y Major lines, having the right corner subpixel as +always inclusive requires that the left corner subpixel should never be inclusive, since a line falling exactly +between pixel centers would wind up lighting pixel on both sides of the line (not desired). +4. The subpixels along the bottom left edge are always inclusive. This is to correctly handle the +case where a line enters the diamond through a left or bottom corner and ends on the bottom left edge. +One does not consider this “passing through” the diamond (where the normal rules would have us light +the pixel). This is to avoid the following case: One line segment enters through one corner and ends on +the edge, and another (continuation) line segments starts at that point on the edge and exits through the +other corner. If simply passing through a corner caused the pixel to be lit, this case would case the pixel +to be lit twice – breaking the rule that connected line segments should not cause double-hits or missing +pixels. So, by considering the entire bottom left edge as “inside”, we will only light the pixel when a line +passes through the entire edge, or starts on the edge (or the left or bottom corner) and exits the diamond. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 253 + 5. The subpixels along the bottom right edge are always inclusive. Same as case as (4), except +slope=-1 lines require the bottom right edge to be considered inclusive. +The following equation determines whether a point (point.x, point.y) is inside the diamond of the pixel +sample point (sample.x, sample.y), given additional information about the slope (XMajor). +delta_x = point.x – sample.x +delta_y = point.y – sample.y +distance = abs(delta_x) + abs(delta_y) +interior = (distance < 0.5) +bottom_corner = (delta_x == 0.0) && (delta_y == 0.5) +left_corner = (delta_x == –0.5) && (delta_y == 0.0) +right_corner = (delta_x == 0.5) && (delta_y == 0.0) +bottom_left_edge = (distance == 0.5) && (delta_x < 0) && (delta_y > 0) +bottom_right_edge = (distance == 0.5) && (delta_x > 0) && (delta_y > 0) + +inside = interior || + +bottom_corner || + +(!XMajor && right_corner) || + +( bottom_left_edge) || + +( bottom_right_edge) + + +10.3.12.4 Non-Antialiased Wide Line Rasterization +Non-anti-aliased, non-zero-width lines are rendered as parallelograms that are centered on, and aligned +to, the line joining the endpoint vertices. Pixels sampled interior to the parallelogram are rendered; pixels +sampled exactly on the parallelogram edges are rendered according to the polygon “top left” rules. +The parallelogram is formed by first determining the major axis of the line (diagonal lines are considered +x-major). The corners of the parallelogram are computed by translating the line endpoints by +/-(Line +Width / 2) in the direction of the minor axis, as shown in the following diagram. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 254 + Non-Antialiased Line Rasterization + + + + +10.3.12.5 Anti-aliased Line Rasterization +Anti-aliased lines are rendered as rectangles that are centered on, and aligned to, the line joining the +endpoint vertices. For each pixel in the rectangle, a fractional coverage value (referred to as Antialias +Alpha) is computed – this coverage value will normally be used to attenuate the pixel’s alpha in the pixel +shader thread. The resultant alpha value is therefore available for use in those downstream pixel pipeline +stages in order to generate the desired effect (e.g., use the attenuated alpha value to modulate the pixel’s +color, and add the result to the destination color, etc.). Note that software is required to explicitly program +the pixel shader and pixel pipeline to obtain the desired anti-aliasing effect – the device will simply make +the coverage-attenuated pixel alpha values available for use in the pixel shader. +The dimensions of the rendered rectangle, and the parameters controlling the coverage value +computation, are programmed via the Line Width, Line AA Region, and Line Cap AA Region state +variables, as shown below. The edges parallel to the line are located at the distance ( LineWidth/2) from +the line (measured in screen pixel units perpendicular to the line). The end-cap edges are perpendicular +to the line and located at the distance (LineCapAARegion) from the endpoints. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 255 + Anti-aliased Line Rasterization + + + + +Along the parallel edges, the coverage values ramp from the value 0 at the very edges of the rectangle to +the value 1 at the perpendicular distance (LineAARegion/2) from a given edge (in the direction of the line). +A pixel’s coverage value is computed with respect to the closest edge. In the cases where +(LineAARegion/2) < (LineWidth/2), this results in a region of fractional coverage values near the edges of +the rectangle, and a region of “fully-covered” coverage values (i.e., the value 1) at the interior of the line. +When (LineAARegion/2) == (LineWidth/2), only pixel sample points falling exactly on the line can generate +fully-covered coverage values. If (LineAARegion/2) > (LineWidth/2), no pixels can be fully-covered (it is +expected that this case is not typically desired). +Along the end cap edges, the coverage values ramp from the value 1 at the line endpoint to the value 0 at +the cap edge – itself at a perpendicular distance (LineCapAARegion) from the endpoint. Note that, unlike +the line-parallel edges, there is only a single parameter (LineCapAARegion) controlling the extension of the +line at the end caps and the associated coverage ramp. +The regions near the corners of the rectangle have coverage values influenced by distances from both +the line-parallel and end cap edges – here the two coverage values are multiplied together to provide a +composite coverage value. +The computed coverage value for each pixel is passed through the Windower Thread Dispatch payload. +The Pixel Shader kernel should be passed (unmodified) by the shader to the Render Cache as part of it’s +output message. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 256 + 10.3.13 3DSTATE_SF + + 3DSTATE_SF + +Source: RenderCS +Length Bias: 2 +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 13h 3DSTATE_SF + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 5h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:15 Reserved + + Format: MBZ + 14:12 Depth Buffer Surface Format + Project: All + Format: U3 Enumerated Type + + + Specifies the format of the depth buffer. This must exactly match the Surface Format programmed via + 3DSTATE_DEPTH_BUFFER. The SF requires this information in order to compute Global Depth Bias. + Value Name Description Project + 0h D32_FLOAT_S8X24_UINT D32_FLOAT_S8X24_UINT All + 1h D32_FLOAT D32_FLOAT All + 2h D24_UNORM_S8_UINT D24_UNORM_S8_UINT All + 3h D24_UNORM_X8_UINT D24_UNORM_X8_UINT All + 4h Reserved Reserved All + 5h D16_UNORM D16_UNORM All + 6h-7h Reserved Reserved All + 11 Legacy Global Depth Bias Enable + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 257 + 3DSTATE_SF + Project: All + Format: Enable + Enables the SF to use the Global Depth Offset Constant state unmodified. If this bit is not set, the SF + will scale the Global Depth Offset Constant as described in section Error! Reference source not found. + of this document. + Programming Notes + This bit should be set whenever non zero depth bias (Slope, Bias) values are used. Setting this bit may + have some degradation of performance for some workloads. + 10 Statistics Enable + Project: All + Format: Enable + If ENABLED, this FF unit will increment CL_PRIMITIVES_COUNT on behalf of the CLIP stage. If + DISABLED, CL_PRIMITIVES_COUNT will be left unchanged. + Programming Notes + This bit should be set whenever clipping is enabled and the Statistics Enable bit is set in CLIP_STATE. + It should be cleared if clipping is disabled or Statistics Enable in CLIP_STATE is clear. + 9 Global Depth Offset Enable Solid + Project: All + Format: Enable + Enables computation and application of Global Depth Offset for SOLID objects. + Programming Notes Project + This bit should be set whenever non zero depth bias (Slope, Bias) values are used. Setting this + bit may have some degradation of performance for some workloads. + Due to an HW issue driver needs to send a pipe control with stall when ever there is state + change in depth bias related state + 8 Global Depth Offset Enable Wireframe + Project: All + Format: Enable + Enables computation and application of Global Depth Offset when triangles are rendered in + WIREFRAME mode. + Programming Notes Project + This bit should be set whenever non zero depth bias (Slope, Bias) values are used. Setting this + bit may have some degradation of performance for some workloads. + Due to an HW issue driver needs to send a pipe control with stall when ever there is state + change in depth bias related state + 7 Global Depth Offset Enable Point + Project: All + Format: Enable + Enables computation and application of Global Depth Offset when triangles are rendered in POINT + mode. + Programming Notes Project + This bit should be set whenever non zero depth bias (Slope, Bias) values are used. Setting this + bit may have some degradation of performance for some workloads. + Due to an HW issue driver needs to send a pipe control with stall when ever there is state + change in depth bias related state + 6:5 FrontFace Fill Mode + Project: All + Format: U2 enumerated type + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 258 + 3DSTATE_SF + + This state controls how front-facing triangle and rectangle objects are rendered. + Value Name Description Project + 0h SOLID Any triangle or rectangle object found to be front-facing is rendered as a All + solid object. This setting is required when rendering rectangle (RECTLIST) + objects. + 1h WIREFRAME Any triangle object found to be front-facing is rendered as a series of lines All + along the triangle boundaries (as determined by the topology type and + controlled by the vertex EdgeFlags). + 2h POINT Any triangle object found to be front-facing is rendered as a set of point + primitives at the triangle vertices (as determined by the topology type and + controlled by the vertex EdgeFlags).NOTE: If the triangle is clipped, points + will not be rendered at clip-inserted vertices. Point will only be rendered at + original vertices (if visible). + 3h Reserved + 4:3 BackFace Fill Mode + Project: All + Format: U2 enumerated type + + + This state controls how back-facing triangle and rectangle objects are rendered. + Value Name Description Project + 0h SOLID Any triangle or rectangle object found to be back-facing is rendered as a All + solid object. This setting is required when rendering rectangle (RECTLIST) + objects. + 1h WIREFRAME Any triangle object found to be back-facing is rendered as a series of lines All + along the triangle boundaries (as determined by the topology type and + controlled by the vertex EdgeFlags). + 2h POINT Any triangle object found to be back-facing is rendered as a set of point + primitives at the triangle vertices (as determined by the topology type and + controlled by the vertex EdgeFlags).NOTE: If the triangle is clipped, points + will not be rendered at clip-inserted vertices. Point will only be rendered at + original vertices (if visible). + 3h Reserved + 2 Reserved + Project: All + Format: MBZ + 1 View Transform Enable + Project: All + Format: Enable + This bit controls the Viewport Transform function. + + 0 Front Winding + Project: All + Determines whether a triangle object is considered “front facing” if the screen space vertex positions, + when traversed in the order, result in a clockwise (CW) or counter-clockwise (CCW) winding order. + Does not apply to points or lines. + +2 31 Anti-Aliasing Enable + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 259 + 3DSTATE_SF + Format: Enable + This field enables “alpha-based” line anti-aliasing. + Programming Notes + This field must be disabled if any of the render targets have integer (UINT or SINT) surface format. + 30:29 Cull Mode + Project: All + Format: 3D_CullMode + Controls removal (culling) of triangle objects based on orientation. The cull mode only applies to + triangle objects and does not apply to lines, points or rectangles. + Value Name Description Project + 0h CULLMODE_BOTH All triangles are discarded (i.e., no triangle objects are drawn) All + 1h CULLMODE_NONE No triangles are discarded due to orientation All + 2h CULLMODE_FRONT Triangles with a front-facing orientation are discarded All + 3h CULLMODE_BACK Triangles with a back-facing orientation are discarded All + + + Programming Notes + Orientation determination is based on the setting of the Front Winding state. + 27:18 Line Width + Project: All + Format: U3.7 + + + Range: [0.0, 7.9921875] + Controls width of line primitives.Setting a Line Width of 0.0 specifies the rasterization of the “thinnest” + (one-pixel-wide), non-antialiased lines. Note that this effectively overrides the effect of AAEnable + (though the AAEnable state variable is not modified). Lines rendered with zero Line Width are + rasterized using GIQ (Grid Intersection Quantization) rules as specified by the GDI APIs. + + + Programming Notes + Software must not program a value of 0.0 when running in MSRASTMODE_ON_xxx modes – zero- + width lines are not available when multisampling rasterization is enabled. + 17:16 Line End Cap Antialiasing Region Width + Project: All + Format: U2 + This field specifies the distances over which the coverage of anti-aliased line end caps are computed. + Value Name Description Project + 0h 0.5 pixels All + 1h 1.0 pixels All + 2h 2.0 pixels All + 3h 4.0 pixels All + 15 Reserved + Project: All + Format: MBZ + 14 Reserved + + Format: MBZ + 11 Scissor Rectangle Enable + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 260 + 3DSTATE_SF + Project: All + Format: Enable + Enables operation of Scissor Rectangle. + + 10 Reserved + + Format: MBZ + 9:8 Multisample Rasterization Mode + Project: All + Format: U2 enumerated type + + + This state is duplicated in 3DSTATE_WM and both must be set to the same value. See the field in + 3DSTATE_WM for definition details. + + 7:0 Reserved + Project: All + Format: MBZ +3 31 Last Pixel Enable + Project: All + Format: Enable + If ENABLED, the last pixel of a diamond line will be lit. This state will only affect the rasterization of + Diamond lines (will not affect wide lines or anti-aliased lines). + Programming Notes + Last pixel is applied to all lines of a LINELIST, and only the last line of a LINESTRIP. + 30:29 Triangle Strip/List Provoking Vertex Select + Project: All + Format: 0-based vertex index + Selects which vertex of a triangle (in a triangle strip or list primitive) is considered the “provoking + vertex”. Used for flat shading of primitives.Does current implementation send provoking vertex first? + Value Name Project + 0h Vertex 0 All + 1h Vertex 1 All + 2h Vertex 2 All + 3h Reserved All + 28:27 Line Strip/List Provoking Vertex Select + Project: All + Format: 0-based vertex index + Selects which vertex of a line (in a line strip or list primitive) is considered the “provoking vertex”. + Value Name Description Project + 0h Vertex 0 All + 1h Vertex 1 All + 2h Reserved All + 3h Reserved All + 26:25 Triangle Fan Provoking Vertex Select + Project: All + Format: 0-based vertex index + Selects which vertex of a triangle (in a triangle fan primitive) is considered the “provoking vertex”. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 261 + 3DSTATE_SF + Value Name Project + 0h Vertex 0 All + 1h Vertex 1 All + 2h Vertex 2 All + 3h Reserved All + 24:15 Reserved + Project: All + Format: MBZ + 14 AA Line Distance Mode + Project: All + Format: U1 + This bit controls the distance computation for antialiased lines. + Value Name Description Project + 1h AALINEDISTANCE_TRUE True distance computation. This is the normal setting which All + should yield WHQL compliance. + 13 Reserved + Project: All + Format: MBZ + 12 Vertex Sub Pixel Precision Select + Project: All + Format: U1 + Selects the number of fractional bits maintained in the vertex data + Value Name Description Project + 0h Disable 8 sub pixel precision bits maintained All + 1h Enable 4 sub pixel precision bits maintained All + 11 Use Point Width State + Project: All + Format: U1 + Controls whether the point width passed on the vertex or from state is used for rendering point + primitives. + Value Name Description Project + 0h Use Point Width on Vertex All + 1h Use Point Width from State All + 10:0 Point Width + Project: All + Format: U8.3 + + + Range: [0.125, 255.875] pixels + This field specifies the size (width) of point primitives in pixels. This field is overridden (though not + overwritten) whenever point width information is passed in the FVF +4 31:0 Global Depth Offset Constant + Project: All + Format: IEEE_FP + Specifies the constant term in the Global Depth Offset function. + +5 31:0 Global Depth Offset Scale + Project: All + Format: IEEE_FP + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 262 + 3DSTATE_SF + Specifies the scale term used in the Global Depth Offset function. + +6 31:0 Global Depth Offset Clamp + Project: All + Format: IEEE_FP + Specifies the clamp term used in the Global Depth Offset function. + + + + +10.3.14 3DSTATE_SBE +The state used by “setup backend” is defined by this inline state packet. + + 3DSTATE_SBE + +Source: RenderCS +Length Bias: 2 +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 1Fh 3DSTATE_SBE + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0Ch Excludes DWord (0,1) + Project: All + Format: =n + Total Length - 2 + +1 31:29 Reserved + Project: All + Format: MBZ + 28 Attribute Swizzle Control Mode + + Format: U1 enumerated type + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 263 + 3DSTATE_SBE + + When Attribute Swizzle Enable is ENABLED, this bit controls whether attributes 0-15 or 16-31 + are subject to the following swizzle controls: +  Attribute n Component Override X/Y/Z/W +  Attribute n Constant Source +  Attribute n Swizzle Select +  Attribute n Source Attribute +  Attribute n Wrap Shortest Enables + + Note that the Number of SF Output Attributes field specifies how many attributes are output. + + Note: This field does not impact any functions which provide separate states for all 32 attributes + (e.g., Point sprite, Constant interpolation). + Value Name Description Project + 0h SWIZ_0_15 Attributes 0-15 are subject to swizzling, and attributes 16-31 are not. + 1h SWIZ_16_31 Attributes 16-31 are subject to swizzling, and attributes 0-15 are not. Only + valid when 16 or more attributes are output. + 27:22 Number of SF Output Attributes + + Format: U6 count of attributes + + + Specifies the number of vertex attributes passed from the SF stage to the WM stage (does not include + Position). + Value Name + [0,32] + 21 Attribute Swizzle Enable + Project: All + Format: Enable + Enables the SF to perform swizzling on (up to the first 16) vertex attributes. If DISABLED, all vertex + attributes are passed through. + + 20 Point Sprite Texture Coordinate Origin + Project: All + Format: U1 enumerated type + + + This state controls how Point Sprite Texture Coordinates are generated (when enabled on a per- + attribute basis by Point Sprite Texture Coordinate Enable). + Value Name Description Project + 0h UPPERLEFT Top Left = (0,0,0,1)Bottom Left = (0,1,0,1)Bottom Right = (1,1,0,1) All + 1h LOWERLEFT Top Left = (0,1,0,1)Bottom Left = (0,0,0,1)Bottom Right = (1,0,0,1) All + 19:16 Reserved + Project: All + Format: MBZ + 15:11 Vertex URB Entry Read Length + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 264 + 3DSTATE_SBE + Format: U5 Specifies the amount of URB data read for each Vertex URB entry, in 256-bit register + increments. + + + + + Value Name + [1,16] + + + Programming Notes + It is UNDEFINED to set this field to 0 indicating no Vertex URB data to be read.This field should be set + to the minimum length required to read the maximum source attribute. The maximum source attribute + is indicated by the maximum value of the enabled Attribute # Source Attribute if Attribute Swizzle + Enable is set, Number of Output Attributes-1 if enable is not set. read_length = + ceiling((max_source_attr+1)/2) + 10 Reserved + Project: All + 9:4 Vertex URB Entry Read Offset + Project: All + Format: U6 + Specifies the offset (in 256-bit units) at which Vertex URB data is to be read from the URB. + Value Name + [0,63] + 3:0 Reserved + Project: All + Format: MBZ +2..9 31 Attribute [2n+1] Component Override W + Project: All + Format: Enable + If set, the W component of output Attribute 1 is overridden by the W component of the constant vector + specified by ConstantSource[1]. + + 30 Attribute [2n+1] Component Override Z + Project: All + Format: Enable + If set, the Z component of output Attribute 1 is overridden by the Z component of the constant vector + specified by ConstantSource[1]. + + 29 Attribute [2n+1] Component Override Y + Project: All + Format: Enable + If set, the Y component of output Attribute 1 is overridden by the Y component of the constant vector + specified by ConstantSource[1]. + + 28 Attribute [2n+1] Component Override X + Project: All + Format: Enable + If set, the X component of output Attribute 1 is overridden by the X component of the constant vector + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 265 + 3DSTATE_SBE + specified by ConstantSource[1]. + + 27 Reserved + Project: All + Format: MBZ + 26:25 Attribute [2n+1] Constant Source + Project: All + Format: U2 enumerated type + + + This state selects a constant vector which can be used to override individual components of Attribute 1 + Value Name Description Project + 0h CONST_0000 Constant.xyzw = 0.0,0.0,0.0,0.0 All + 1h CONST_0001_FLOAT Constant.xyzw = 0.0,0.0,0.0,1.0 All + 2h CONST_1111_FLOAT Constant.xyzw = 1.0,1.0,1.0,1.0 All + 3h PRIM_ID Constant.xyzw = PrimID (replicated) All + 24 Reserved + Project: All + Format: MBZ + 23:22 Attribute [2n+1] Swizzle Select + Project: All + Format: U2 enumerated type + + + This state, along with Attribute 1 Source Attribute, specifies the source for output Attribute 1. + Value Name Description Project + 0h INPUTATTR This attribute is sourced from AttrInputReg[SourceAttribute] All + 1h INPUTATTR_FACING If the object is front-facing, this attribute is sourced from All + AttrInputReg[SourceAttribute].If the object is back-facing, this + attribute is sourced from AttrInputReg[SourceAttribute+1]. + 2h INPUTATTR_W This attribute is sourced from AttrInputReg[SourceAttribute]. All + The W component is copied to the X component. + 3h INPUTATTR_FACING_W If the object is front-facing, this attribute is sourced from All + AttrInputReg[SourceAttribute].If the object is back-facing, this + attribute is sourced from AttrInputReg[SourceAttribute+1]. The + W component is copied to the X component. + 21 Reserved + Project: All + Format: MBZ + 20:16 Attribute [2n+1] Source Attribute + Project: All + Format: U5 + This field selects the source attribute for Attribute 1. Source attribute 0 corresponds to the first 128 bits + of data indicated by Vertex URB Entry Read Offset + + 15 Attribute [2n] Component Override W + Project: All + Format: Enable + If set, the W component of output Attribute 0 is overridden by the W component of the constant vector + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 266 + 3DSTATE_SBE + specified by ConstantSource[1]. + + 14 Attribute [2n] Component Override Z + Project: All + Format: Enable + If set, the Z component of output Attribute 0 is overridden by the Z component of the constant vector + specified by ConstantSource[1]. + + 13 Attribute [2n] Component Override Y + Project: All + Format: Enable + If set, the Y component of output Attribute 0 is overridden by the Y component of the constant vector + specified by ConstantSource[1]. + + 12 Attribute [2n] Component Override X + Project: All + Format: Enable + If set, the X component of output Attribute 0 is overridden by the X component of the constant vector + specified by ConstantSource[1]. + + 11 Reserved + Project: All + Format: MBZ + 10:9 Attribute [2n] Constant Source + Project: All + Format: U2 enumerated type + + + This state selects a constant vector which can be used to override individual components of Attribute 0 + Value Name Description Project + 0h CONST_0000 Constant.xyzw = 0.0,0.0,0.0,0.0 All + 1h CONST_0001_FLOAT Constant.xyzw = 0.0,0.0,0.0,1.0 All + 2h CONST_1111_FLOAT Constant.xyzw = 1.0,1.0,1.0,1.0 All + 3h PRIM_ID Constant.xyzw = PrimID (replicated) All + 8 Reserved + Project: All + Format: MBZ + 7:6 Attribute [2n] Swizzle Select + Project: All + Format: U2 enumerated type + + + This state, along with Attribute 0 Source Attribute, specifies the source for output Attribute 0. + Value Name Description Project + 0h INPUTATTR This attribute is sourced from AttrInputReg[SourceAttribute] All + 1h INPUTATTR_FACING If the object is front-facing, this attribute is sourced from All + AttrInputReg[SourceAttribute].If the object is back-facing, this + attribute is sourced from AttrInputReg[SourceAttribute+1]. + 2h INPUTATTR_W This attribute is sourced from AttrInputReg[SourceAttribute]. All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 267 + 3DSTATE_SBE + The W component is copied to the X component. + 3h INPUTATTR_FACING_W If the object is front-facing, this attribute is sourced from All + AttrInputReg[SourceAttribute].If the object is back-facing, this + attribute is sourced from AttrInputReg[SourceAttribute+1]. The + W component is copied to the X component. + 5 Reserved + Project: All + Format: MBZ + 4:0 Attribute [2n] Source Attribute + Project: All + Format: U5 + This field selects the source attribute for Attribute 0. Source attribute 0 corresponds to the first 128 bits + of data indicated by Vertex URB Entry Read Offset + +10 31:0 Point Sprite Texture Coordinate Enable + Project: All + Format: 32-bit bitmask + When processing point primitives, the attributes from the incoming point vertex are typically copied to + the point object corner vertices. However, if a bit is set in this field, the corresponding Attribute is + selected as a Point Sprite Texture Coordinate, in which case each corner vertex is assigned a pre- + defined texture coordinate as defined by the Point Sprite Texture Coordinate Origin state bit. Bit 0 + corresponds to output Attribute 0. + This field must be programmed to 0 when non-point primitives are rendered. + +11 31:0 Constant Interpolation Enable[31:0] + Project: All + This field is a bitmask containing a Constant Interpolation Enable bit for each corresponding attribute. If + a bit is set, that attribute will undergo constant interpolation, and the corresponding WrapShortest + Enable bits (if defined) will be ignored. If a bit is clear, components which are not enabled for + WrapShortest interpolation (if defined) will be linearly interpolated. + +12 31:28 Attribute 7 WrapShortest Enables + Project: All + Format: Enable[4] + This state selects which components (if any) of Attribute 7 are to be interpolated in a “wrap shortest” + fashion. Operation is UNDEFINED if any of these bits are set and the Constant Interpolation Enable bit + associated with this attribute is set. Note that wrap-shortest interpolation is only supported for Attributes + 0-15.Bit 0: WrapShortest X ComponentBit 1: WrapShortest Y ComponentBit 2: WrapShortest Z + ComponentBit 3: WrapShortest W Component + + 27:24 Attribute 6 WrapShortest Enables + Project: All + (See above). + + 23:20 Attribute 5 WrapShortest Enables + Project: All + (See above). + + 19:16 Attribute 4 WrapShortest Enables + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 268 + 3DSTATE_SBE + (See above). + + 15:12 Attribute 3 WrapShortest Enables + Project: All + (See above). + + 11:8 Attribute 2 WrapShortest Enables + Project: All + (See above). + + 7:4 Attribute 1 WrapShortest Enables + Project: All + (See above). + + 3:0 Attribute 0 WrapShortest Enables + Project: All + (See above). + +13 31:28 Attribute 15 WrapShortest Enables + Project: All + Format: Enable[4] + This state selects which components (if any) of Attribute 15 are to be interpolated in a “wrap shortest” + fashion. Operation is UNDEFINED if any of these bits are set and the Constant Interpolation Enable bit + associated with this attribute is set.Bit 0: WrapShortest X ComponentBit 1: WrapShortest Y + ComponentBit 2: WrapShortest Z ComponentBit 3: WrapShortest W Component + + 27:24 Attribute 14 WrapShortest Enables + Project: All + (See above). + + 23:20 Attribute 13 WrapShortest Enables + Project: All + (See above). + + 19:16 Attribute 12 WrapShortest Enables + Project: All + (See above). + + 15:12 Attribute 11 WrapShortest Enables + Project: All + (See above). + + 11:8 Attribute 10 WrapShortest Enables + Project: All + (See above). + + 7:4 Attribute 9 WrapShortest Enables + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 269 + 3DSTATE_SBE + (See above). + + 3:0 Attribute 8 WrapShortest Enables + Project: All + (See above). + + + + +10.3.15 SF_CLIP_VIEWPORT +The viewport-specific state used by both the SF and CL units (SF_CLIP_VIEWPORT) is stored as an +array of up to 16 elements, each of which contains the DWords described below. The start of each +element is spaced 16 DWords apart. The location of first element of the array, as specified by both +Pointer to SF_VIEWPORT and Pointer to CLIP_VIEWPORT, is aligned to a 64-byte boundary. + + SF_CLIP_VIEWPORT + +Source: RenderCS +Default 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000 +DWord Bit Description +0 31:0 Viewport Matrix Element m00 + Format: IEEE_Float +1 31:0 Viewport Matrix Element m11 + Format: IEEE_Float +2 31:0 Viewport Matrix Element m22 + Format: IEEE_Float Total Length - 2 + + +3 31:0 Viewport Matrix Element m30 + Format: IEEE_Float Total Length - 2 + + +4 31:0 Viewport Matrix Element m31 + Format: IEEE_Float +5 31:0 Viewport Matrix Element m32 + Format: IEEE_Float +6 31:0 Reserved +7 31:0 Reserved + Project: All + Format: MBZ +8 31:0 X Min Clip Guardband + Default Value: 0h Excludes DWord (0,1) + Format: FLOAT32 + . This 32-bit float represents the XMin guardband boundary (normalized to Viewport.XMin == -1.0f). + This corresponds to the left boundary of the NDC guardband. + +9 31:0 X Max Clip Guardband + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 270 + SF_CLIP_VIEWPORT + Default Value: 0h Excludes DWord (0,1) + Format: FLOAT32 + This 32-bit float represents the XMax guardband boundary (normalized to Viewport..XMax == 1.0f). + This corresponds to the right boundary of the NDC guardband. + +10 31:0 Y Min Clip Guardband + Format: FLOAT32 + This 32-bit float represents the YMin guardband boundary (normalized to Viewport.YMin == -1.0f). This + corresponds to the bottom boundary of the NDC guardband. + +11 31:0 Y Max Clip Guardband: + Format: FLOAT32 + This 32-bit float represents the YMax guardband boundary (normalized to Viewport.YMax == 1.0f). + This corresponds to the top boundary of the NDC guardband. + +12 +12..15 31:0 Reserved + + Format: MBZ + + + + +10.3.16 SCISSOR_RECT + + SCISSOR_RECT + +Source: RenderCS +Default Value: 0x00000000, 0x00000000 +The viewport-specific state used by the SF unit (SCISSOR_RECT) is stored as an array of up to 16 elements, each +of which contains the DWords described below. The start of each element is spaced 2 DWords apart. The location of +first element of the array, as specified by Pointer to SCISSOR_RECT, is aligned to a 32-byte boundary. +DWord Bit Description +0 31:16 Scissor Rectangle Y Min + Project: All + Format: U16 Pixels from Drawing Rectangle origin (upper left corner) + + + Specifies Y Min coordinate of (inclusive) Scissor Rectangle used for scissor test. Pixels with (Draw + Rectangle-relative) Y coordinates less than Y Min will be clipped out if Scissor Rectangle is enabled. + NOTE: If Y Min is set to a value greater than Y Max, all primitives will be discarded for this viewport. + Value Name Project + [0,16383] + 15:0 Scissor Rectangle X Min + Project: All + Format: U16 Pixels from Drawing Rectangle origin (upper left corner) + + + Specifies X Min coordinate of (inclusive) Scissor Rectangle used for scissor test. Pixels with (Draw + Rectangle-relative) X coordinates less than X Min will be clipped out if Scissor Rectangle is enabled. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 271 + SCISSOR_RECT + NOTE: If X Min is set to a value greater than X Max, all primitives will be discarded for this viewport. + Value Name Project + [0,16383] +1 31:16 Scissor Rectangle Y Max + Project: All + Format: U16 Pixels from Drawing Rectangle origin (upper left corner) + + + Specifies Y Max coordinate of (inclusive) Scissor Rectangle used for scissor test. Pixels with (Draw + Rectangle-relative) Y coordinates greater than Y Max will be clipped out if Scissor Rectangle is + enabled. + Value Name Project + [0,16383] + 15:0 Scissor Rectangle X Max + Project: All + Format: U16 Pixels from Drawing Rectangle origin (upper left corner) + + + Specifies X Max coordinate of (inclusive) Scissor Rectangle used for scissor test. Pixels with (Draw + Rectangle-relative) Y coordinates greater than X Max will be clipped out if Scissor Rectangle is + enabled. + Value Name Project + 0-16383 + + + + +10.4 Attribute Interpolation Setup +With the attribute interpolation setup function being implemented in hardware for, a number of state fields +in 3DSTATE_SF are utilized to control interpolation setup. +Number of SF Output Attributes sets the number of attributes that will be output from the SF stage, not +including position. This can be used to specify up to 32, and may differ from the number of input +attributes. The number of input attributes is derived from the Vertex URB Entry Read Length field. Note +that this field is also used to specify whether swizzling is to be performed on Attributes 0-15 or Attributes +16-32. See the state field definition for details. + + +10.4.1 Attribute Swizzling +The first or last set of 16 attributes can be swizzled according to certain state fields. Attribute Swizzle +Enable enables the swizzling for all 16 of these attributes, and each of the attributes has a 2-bit Swizzle +Select field that controls swizzling with the following settings: + +  INPUTATTR – This attribute is sourced from AttrInputReg[SourceAttribute]. +  INPUTATTR_FACING – This attribute is sourced from AttrInputReg[SourceAttribute] if the object + is front-facing, otherwise it is sourced from AttrInputReg[SourceAttribute+1]. +  INPUTATTR_W – This attribute is sourced from AttrInputReg[SourceAttribute]. WYZW (the W + component of the source is copied to the X component of the destination). +  INPUTATTR_FACING – If the object is front-facing, this attribute is sourced from + AttrInputReg[SourceAttribute]. WYZW (the W component of the source is copied to the X + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 272 + component of the destination). If the object is front-facing, this attribute is sourced from + AttrInputReg[SourceAttribute+1]. WYZW. + +Each of the first or last set of 16 attributes also has a 5-bit Source Attribute field which specify, per +output attribute (not component), which input attribute sources the output attribute when INPUTATTR is +selected for Swizzle Select. A Source Attribute value of 0 corresponds to the 128-bit attribute +immediately following the vertex 4D position. If INPUTATTR_FACING is selected, this specifies the first of +two consecutive (front,back) input attributes, where the SourceAttribute value can be an odd or even +number (just not 31, as that would place the back-face input attribute past the end of the input max +complement of input attributes). +Constant overriding is also available for the first or last set of 16 attributes. Each attribute has a Constant +Source field which specifies the constant values per swizzled attribute, with the following settings +available: + +  XYZW = 0000 +  XYZW = 0001 +  XYZW = 1111 + +Each channel of each attribute has a Component Override field to control whether the corresponding +channel is overridden with the constant value defined in Constant Source. + + +10.4.2 1Interpolation Modes +All 32 attributes have a Constant Interpolation Enable state field bit to specify whether all components +of the attribute are to be interpolated as constant values (not varying over the pixels of the object). If set, +the attribute at the provoking vertex is copied to a0, and a1 and a2 are set to zero – this results in a +constant interpolation of the provoking vertex value. If clear, the attribute is linearly interpolated. Attributes +0-15 are further subjected to Wrap Shortest processing on a per-component basis, via the Attribute +WrapShortest Enables state bitfields. WrapShortest processing modifies the a1 and/or a2 values +depending on attribute deltas. All +The table below indicates the output values of a0, a1, and a2 depending on interpolation mode settings. + a0 a1 a2 + Constant A0 0.0 0.0 + Linear A0 A1-A0 A2-A0 + A0 + (A1-A0)+1 (A1-A0) <= -0.5 (A2-A0)+1 (A2-A0) <= -0.5 + (A1-A0)-1 (A1-A0) >= 0.5 (A2-A0)-1 (A2-A0) >= 0.5 + (A1-A0) otherwise (A2-A0) otherwise +Wrap Shortest + + +10.4.3 Point Sprites +Normally all vertex attributes (including texture coordinates) other than position are simply replicated from +the incoming point center vertex to the generated point object (corner) vertices. However, both DX9 and +OGL support “sprite points”, where some/all texture coordinates are replaced with full-scale 2D texture +coordinates. +A 32-bit PointSprite TextureCoordinate Enable bit mask controls whether the corresponding vertex +attribute is to be replaced by a sprite point texture coordinate. The global (not per-attribute) Point Sprite +TextureCoordinate Origin field controls how the point object vertex (top/bottom, left/right) texture +coordinates are generated: + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 273 + Left Right + UPPERLEFT + Top (0,0,0,1) (1,0,0,1) + Bottom (0,1,0,1) (1,1,0,1) + + + Left Right + LOWERLEFT + Top (0,1,0,1) (1,1,0,1) + Bottom (0,0,0,1) (1,0,0,1) + + + +10.5 Depth Offset +The state for depth offset in 3DSTATE_SF controls the depth offset function. Since this function was +previously contained in the Windower stage, refer to the “Depth Offset” section in the Windower chapter +for more details on this function. + + +10.6 Other SF Functions + +10.6.1 Statistics Gathering +The SF stage itself does not have any associated pipeline statistics; however, it counts the number of +objects being output by the clipper on the clipper’s behalf, since it less feasible to have the CLIP unit +figure out how many objects have been output by a clip thread. It is easy for the SF unit to count the +number of objects it receives from the CLIP stage since it is decomposing the output primitive topologies +into objects anyway. +If the Statistics Enable bit is set in SF_STATE, then SF will increment the CL_PRIMITIVES_COUNT +Register (see Memory Interface Registers in Volume Ia, GPU) once for each object in each primitive +topology it receives from the CLIP stage. This bit should always be set if clipping is enabled and pipeline +statistics are desired. +Software should always clear the Statistics Enable bit in SF_STATE if the clipper is disabled since +objects SF receives are not considered “primitives output by the clipper” unless the clipper is enabled. +Note that the clipper can be disabled either using bypass mode via a PIPELINE_STATE_POINTERS +command with Clip Enable clear or by setting Clip Mode in CLIP_STATE to CLIPMODE_ACCEPT_ALL. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 274 + 11. 3D Pipeline – Windower (WM) Stage +11.1 Overview +As mentioned in the SF Unit chapter, the SF stage prepares an object for scan conversion by the +Window/Masker (WM) unit Refer to the SF Unit chapter for details on the screen-space geometry of +objects to be rendered The WM unit uses the parameters provided by the SF unit in the object-specific +rasterization algorithms. +The WM stage of the 3D pipeline performs the following operations (at a high level) + +  Pre-scan-conversion modification of some primitive attributes, including + o Application of Depth Offset to the position Z attribute + +  Scan-conversion of the various primitive types, including + o 2D clipping to the scissor/draw rectangle intersection + +  Spawning of Pixel Shader (PS) threads to process the pixels resulting from scan-conversion + +The spawned Pixel Shader (PS) threads are responsible for the following (high-level) operations + +  interpolation of vertex attributes (other than X,Y,Z) to the pixel location +  performing any “Pixel Shader” operations dictated by the API PS program + o Using the Sampler shared function to sample data from “texture” surfaces + o Using the DataPort to perform general memory I/O + +  Submitting the shaded pixel results to the DataPort for any subsequent “blending” (aka Output + Merger) operation and write to the RenderCache. + +The WM unit keeps a scoreboard of pixels being processed in outstanding PS threads in order to +guarantee in-order rasterization results This allows the WM unit to overlap processing of several objects. + + +11.1.1 Inputs from SF to WM +The outputs from the SF stage to the WM stage are mostly comprised of implementation-specific +information required for the rasterization of objects The types of information is summarized below, but as +the interface is not exposed to software a detailed discussion is not relevant to this specification. + +  PrimType of the object +  VPIndex, RTAIndex associated with the object +  Handle of the Primitive URB Entry (PUE) that was written by the SF (Setup) thread This handle will + be passed to all WM (PS) threads spawned from the WM’s rasterization process. +  Information regarding the X,Y extent of the object (e.g., bounding box, etc.) +  Edge or line interpolation information (e.g., edge equation coefficients, etc.) +  Information on where the WM is to start rasterization of the object +  Object orientation (front/back-facing) +  Last Pixel indication (for line drawing) + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 275 + 11.2 Windower Pipelined State +{WA}: The driver must make sure a PIPE_CONTROL with the Depth Stall Enable bit set after all the +following states are programmed: + o 3DSTATE_PS + o 3DSTATE_VIEWPORT_STATE_POINTERS_CC + o 3DSTATE_CONSTANT_PS + o 3DSTATE_BINDING_TABLE_POINTERS_PS + o 3DSTATE_SAMPLER_STATE_POINTERS_PS + o 3DSTATE_CC_STATE_POINTERS + o 3DSTATE_BLEND_STATE_POINTERS + o 3DSTATE_DEPTH_STENCIL_STATE_POINTERS + + +11.2.1 3DSTATE_WM + 3DSTATE_WM + + +Source: RenderCS +Length Bias: 2 +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 14h 3DSTATE_WM + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 01h Excludes DWord (0,1) + Project: All + Format: =n + Total Length - 2 + +1 31 Statistics Enable + Project: All + Format: Enable + If ENABLED, the Windower and pixel pipeline will engage in statistics gathering. If DISABLED, + statistics information associated with this FF stage will be left unchanged. See Statistics Gathering. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 276 + 3DSTATE_WM + 30 Depth Buffer Clear + Project: All + Format: Enable + When set, the depth buffer is initialized as a side-effect of rendering pixels. + Programming Notes + If this field is enabled, + + 2. + the Depth Test Enable field in DEPTH_STENCIL_STATE must be disabled. + 3. + 3DSTATE_DEPTH_BUFFER::Depth Write Enable must be set. + 4. + 3DSTATE_DEPTH_BUFFER::Stencil Write Enable must be set if + 3DSTATE_STENCIL_BUFFER::Stencil buffer enable is set. Additionally the following must be set to + the correct values. + + B. + DEPTH_STENCIL_STATE::Stencil Write Mask must be 0xFF + C. + DEPTH_STENCIL_STATE::Stencil Test Mask must be 0xFF + D. + DEPTH_STENCIL_STATE::Back Face Stencil Write Mask must be 0xFF + E. + DEPTH_STENCIL_STATE::Back Face Stencil Test Mask must be 0xFF + + Refer to section 0 "Depth Buffer Clear" for additional restrictions when this field is enabled. If this field + is enabled,Pixel Shader Kill Pixel must be disabled. + 29 Thread Dispatch Enable + Project: All + Format: Enable + This bit, if set, indicates that it is possible for a PS thread to modify a render target, i.e.,at least one + render target is enabled (is not of type SURFTYPE_NULL and has at least one channel enabled for + writes) and the PS kernel contains a code path that may issue a write to that/those enabled RTs. + Programming Notes + This bit is used for performance optimizations and does not directly control writing to render targets. If + this bit is DISABLED, no pixel shader threads will be dispatched.For correct behavior, this bit must be + set consistently with the behavior of the PS kernel, i.e. if this bit is DISABLED the PS kernel must not + write color or depth to any render targets.If this field is disabled, Pixel Shader Kill Pixel must be + disabled. + 28 Depth Buffer Resolve Enable + Project: All + Format: Enable + When set, the depth buffer is made to be consistent with the hierarchical depth buffer as a side-effect + of rendering pixels. This is intended to be used when the depth buffer is to be used as a surface + outside of the 3D rendering operation. + Programming Notes + If this field is enabled, + + 2. + the Depth Buffer Clear and Hierarchical Depth Buffer Resolve Enable fields must both be + disabled. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 277 + 3DSTATE_WM + + 3. + 3DSTATE_DEPTH_BUFFER::Depth Write Enable must be set. + + Refer to section 11.5.4.2 "Depth Buffer Resolve" for additional restrictions when this field is enabled. If + Hierarchical Depth Buffer Enable is disabled, enabling this field will have no effect. + 27 Hierarchical Depth Buffer Resolve Enable + Project: All + Format: Enable + When set, the hierarchical depth buffer is made to be consistent with the depth buffer as a side-effect + of rendering pixels. This is intended to be used when the depth buffer has been modified outside of the + 3D rendering operation. + Programming Notes Project + If this field is enabled, + + 2. + the Depth Buffer Clear and Depth Buffer Resolve Enable fields must both be + disabled. + 3. + 3DSTATE_DEPTH_BUFFER::Depth Write Enable must be set. + + Refer to section 11.5.4.3 "Hierarchical Depth Buffer Resolve" for additional restrictions + when this field is enabled. + If Hierarchical Depth Buffer Enable is disabled, enabling this field will have no effect. + Performance Note: expect the hierarchical depth buffer's impact on performance to be + reduced for some period of time after this operation is performed, as the hierarchical + depth buffer is initialized to a state that makes it ineffective. Further rendering will tend + to bring the hierarchical depth buffer back to a more effective state. + Software needs to do an ambiguate after allocating the surface for the first time if the + depth buffer width and height are NOT aligned to 8 and 4 respectively. + 26 Legacy Diamond Line Rasterization + Project: All + Format: Enable + This bit, if ENABLED, indicates that the Windower will rasterize zero width lines using the DX9 + rasterization rules. If DISABLED, the Windower will rasterize zero width lines using the DX10 + rasterization rules (see Strips Fans chapter). + + 25 Pixel Shader Kill Pixel + Project: All + Format: Enable + This bit, if ENABLED, indicates that the PS kernel or color calculator has the ability to kill (discard) + pixels or samples, other than due to depth or stencil testing. This bit is required to be ENABLED in the + following situations: + + + + +  + The API pixel shader program contains “killpix” or “discard” instructions, or other code in the pixel + shader kernel that can cause the final pixel mask to differ from the pixel mask received on dispatch. +  + A sampler with chroma key enabled with kill pixel mode is used by the pixel shader. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 278 + 3DSTATE_WM +  + Any render target has Alpha Test Enable or AlphaToCoverage Enable enabled. +  + The pixel shader kernel generates and outputs oMask. + + + + + Note: As ClipDistance clipping is fully supported in hardware and therefore not via PS instructions, + there should be no need to ENABLE this bit due to ClipDistance clipping. + + + 24:23 Pixel Shader Computed Depth Mode + + Format: U2 Enumerated Type + + + This field specifies the computed depth mode for the pixel shader. + Value Name Description Project + 0h PSCDEPTH_OFF Pixel shader does not compute depth All + 1h PSCDEPTH_ON Pixel shader computes depth with no guarantee as to its All + value + 2h PSCDEPTH_ON_GE Pixel shader computes depth and guarantees that oDepth All + >= SourceDepth + 3h PSCDEPTH_ON_LE Pixel shader computes depth and guarantees that oDepth All + <= SourceDepth + + + Programming Notes + When bit 5 is set in WM_STATE(i.e. RT independent rasterization is enabled), this field can not be + programmed to values: 2h or 3h. + 22:21 Early Depth/Stencil Control + + Format: U2 Enumerated Type + + + This field specifies the behavior of early depth/stencil test. + Value Name Description Project + 0h EDSC_NORMAL Depth/Stencil Test/Write behaves as if it happens post-shader, All + however the pixel shader is not necessarily executed if the pixel + fails depth or stencil test (this is the legacy behavior) + 1h EDSC_PSEXEC Depth/Stencil Test/Write behaves as if it happens post-shader, All + and the pixel shader is executed if the pixel fails depth or stencil + test (although pre-shader actions such as primitive inclusion, + stipple, etc. will still cause the shader not to execute) + 2h EDSC_PREPS Depth/Stencil Test/Write behaves as if it happens pre-shader. All + The pixel shader is not executed if the pixel fails depth or + stencil test. Depth and stencil writes occur even if the pixel is + killed by the shader or post-shader by alpha test, etc. Depth + output by the pixel shader is ignored. + 3h Reserved All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 279 + 3DSTATE_WM + + + + Programming Notes + If EDSC_PSEXEC mode is selected, Thread Dispatch Enable must be set. + + + Errata Description Project + When value of “2h” is programmed, PS_INVOCATIONs_COUNT may not be accurate. + 20 Pixel Shader Uses Source Depth + Project: All + Format: Enable + This bit, if ENABLED, indicates that the PS kernel requires the source depth value (vPos.z) to be + passed in the payload.The source depth value is interpolated according to the Position ZW + Interpolation Mode state. + + 19 Pixel Shader Uses Source W + Project: All + Format: Enable + This bit, if ENABLED, indicates that the PS kernel requires the interpolated source W value (vPos.w) to + be passed in the payload. The W value is interpolated according to the Position ZW Interpolation Mode + state. + + 18:17 Position ZW Interpolation Mode + Project: All + Format: U2 Enumerated Type + + + This field elects “interpolation mode” associated with the Position Z (source depth) and W coordinates + passed in the PS payload when the PS requires Position as input. This field does not determine + whether these coordinates are actually included in the payload (see Pixel Shader Requires Depth, + Pixel Shader Requires W). + Value Name Description Project + 0h INTERP_PIXEL Evaluate Z & W at the pixel center or UL corner (as All + specified by Pixel Location of 3DSTATE_MULTISAMPLE) + 1h Reserved All + 2h INTERP_CENTROID All + 3h INTERP_SAMPLE All + + + Programming Notes + When bit 5 is set in WM_STATE, value of 3h is not defined for this field. + Programming Note: When bit 5 in dword 1 (RT Independent Rasterization Enable) is set and bit 30 in + dword 2 (PS UAV-only) is not set in WM_STATE, value of 3h is not defined for this field. + 16:11 Barycentric Interpolation Mode + Project: All + Format: Enable[6] + Controls which barycentric interpolation terms must be passed into the pixel shader kernel. + Bit 0: Perspective Pixel Location barycentric is required + Bit 1: Perspective Centroid barycentric is required + Bit 2: Perspective Sample barycentric is required + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 280 + 3DSTATE_WM + Bit 3: Non-perspective Pixel Location barycentric is required + Bit 4: Non-perspective Centroid barycentric is required + Bit 5: Non-perspective Sample barycentric is required + Programming Notes + If contiguous dispatch modes are enabled, only bit 3 (non-perspective pixel location) can be set, all + other bits in this field must be zero.Pixel Location below refers to either the upper left corner or pixel + center depending on the Pixel Location state of 3DSTATE_MULTISAMPLING). + MSDISPMODE_PERSAMPLE is required in order to select Perspective Sample or Non-perspective + Sample barycentric coordinates. + Errata: When Centroid Barycentric mode is required, HW may produce incorrect interpolation results + when a 2X2 pixels have unlit pixels. + 10 Pixel Shader Uses Input Coverage Mask + Project: All + Format: Enable + This bit, if ENABLED, indicates that the PS kernel requires the input coverage mask to be passed in + the payload. + + 9:8 Line End Cap Antialiasing Region Width + Project: All + Format: U2 + This field specifies the distances over which the coverage of anti-aliased line end caps are computed. + Value Name Description Project + 0h 0.5 pixels All + 1h 1.0 pixels All + 2h 2.0 pixels All + 3h 4.0 pixels All + 7:6 Line Antialiasing Region Width + Project: All + Format: U2 + This field specifies the distance over which the anti-aliased line coverage is computed. + Value Name Description Project + 0h 0.5 pixels All + 1h 1.0 pixels All + 2h 2.0 pixels All + 3h 4.0 pixels All + 5 Reserved + + Format: MBZ + 4 Polygon Stipple Enable + Project: All + Format: Enable + Enables the Polygon Stipple function. + + 3 Line Stipple Enable + Project: All + Format: Enable + Enables the Line Stipple function. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 281 + 3DSTATE_WM + 2 Point Rasterization Rule + Project: All + Format: 3D_RasterizationRule + This field specifies the rasterization rules to be applied whenever the edges of a point primitive fall + exactly on a pixel sampling point. + Value Name Description Project + 0h RASTRULE_UPPER_LEFT To match “normal” upper left rules for surface All + primitives + 1h RASTRULE_UPPER_RIGHT To match OpenGL point rasterization rules (round All + to + infinity, where this is the upper right direction + wrt OpenGL screen origin of lower left). + 1:0 Multisample Rasterization Mode + Project: All + Format: U2 enumerated type + + + This field determines whether multisample rasterization is turned on/off, and how the pixel sample + point(s) are defined. Software sets this according to the API, the API's multisample enable state setting + (if any), and whether 1X or 4X MSRTs are bound. This state is duplicated in 3DSTATE_SF and both + must be set to the same value. Refer to the "Multisampling" section for details on the settings of this + field. + Value Name Project + 0h MSRASTMODE_OFF_PIXEL All + 1h MSRASTMODE_OFF_PATTERN All + 2h MSRASTMODE_ON_PIXEL All + 3h MSRASTMODE_ON_PATTERN All +2 31 Multisample Dispatch Mode + Project: All + Format: U1 Enumerated Type + + + This bit, along with Number of Multisamples, determines how PS threads are dispatched. Software + programs this bit depending on the per-pixel v.s per-sample PS execution requirement. + When RT Independent Rasterization Enable = 1, value of 0h for this field is not allowed. + Value Name Description Project + 0h MSDISPMODE_PERSAMPLE This is the high-quality DX10.1 multisample mode All + where (over and above PERPIXEL mode) the PS + is run for each covered sample. This mode is also + used for “normal” non-multisample rendering (aka + 1X), given Number of Multisamples is + programmed to NUMSAMPLES_1. + 1h MSDISPMODE_PERPIXEL This is the classic multisample mode of operation, All + typically used for both antialiasing and + transparency. Setup and rasterization operate in + full multisample mode, testing coverage and + depth/stencil test at the sample level but only + running the PS once per pixel. + 30:0 Reserved + + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 282 + 11.2.2 3DSTATE_PS +This command is used to set state used by the pixel shader dispatch stage. + + 3DSTATE_PS + + +Source: RenderCS +Length Bias: 2 +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 20h 3DSTATE_PS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 06h Excludes DWord (0,1) + Project: All + Format: =n + Total Length - 2 + +1 31:6 Kernel Start Pointer[0] + Project: All + Format: InstructionBaseOffset[31:6]Kernel + Specifies the 64-byte aligned address offset of the first instruction in the kernel[0]. This pointer is + relative to the Instruction Base Address. + + 5:0 Reserved + Project: All + Format: MBZ +2 31 Single Program Flow (SPF) + Project: All + Specifies the initial condition of the kernel program as either a single program flow (SIMDnxm with m = + 1) or as multiple program flows (SIMDnxm with m > 1). See CR0 description in ISA Execution + Environment. + Value Name Description Project + 0h Multiple Multiple Program Flows All + 1h Single Single Program Flows All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 283 + 3DSTATE_PS + 30 Vector Mask Enable (VME) + Project: All + Format: U1 Enumerated Type + + + When SPF=0, VME specifies which mask to use to initialize the initial channel enables. When SPF=1, + VME specifies which mask to use to generate execution channel enables. + Value Name Description Project + 0h Dmask Channels are enabled based on the dispatch mask All + 1h Vmask Channels are enabled based on the vector mask All + 29:27 Sampler Count + Project: All + Format: U3 + Specifies how many samplers (in multiples of 4) the pixel shader 0 kernel uses. Used only for + prefetching the associated sampler state entries. + Value Name Description Project + [0,4] + 0h no samplers used All + 1h between 1 and 4 samplers used All + 2h between 5 and 8 samplers used All + 3h between 9 and 12 samplers used All + 4h between 13 and 16 samplers used All + 5h-7h Reserved All + 26 Denormal Mode + Project: All + Specifies the denornal mode used by the dispatched thread. + Value Name Description Project + 0h FTZ Denormals are flushed to zero All + 1h RET Denormals are retained All + 25:18 Binding Table Entry Count + Project: All + Format: U8 + Specifies how many binding table entries the kernel uses. Used only for prefetching of the binding table + entries and associated surface state.Note: For kernels using a large number of binding table entries, it + may be advantageous to set this field to zero to avoid prefetching too many entries and thrashing the + state cache. + This field is ignored if VS Function Enable is DISABLED. + Value Name + [0,255] + + + Programming Notes + When HW binding table bit is set, it is assumed that the Binding Table Entry Count field will be + generated at JIT time. + 17 Reserved + + Format: MBZ + 16 Floating Point Mode + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 284 + 3DSTATE_PS + + Project: All + Specifies the floating point mode used by the dispatched thread. + Value Name Description Project + 0h IEEE-745 Use IEEE-754 rules All + 1h Alt Use alternate rules All + 15:14 Rounding Mode + Project: All + Specifies the rounding mode used by the dispatched thread. + Value Name Description Project + 0h RTNE Round to Nearest Even All + 1h RU Round toward +infinity All + 2h RD Round toward –infinity All + 3h RTZ Round toward zero All + 13 Illegal Opcode Exception Enable + Project: All + Format: Enable + This bit gets loaded into EU CR0.1[12] (note the bit # difference). See Exceptions and ISA Execution + Environment. + + 12 Reserved + Project: All + Format: MBZ + 11 MaskStack Exception Enable + Project: All + Format: Enable + This bit gets loaded into EU CR0.1[12] (note the bit # difference). See Exceptions and ISA Execution + Environment. + + 10:8 Reserved + Project: All + Format: MBZ + 7 Software Exception Enable + Project: All + Format: Enable + This bit gets loaded into EU CR0.1[13] (note the bit # difference). See Exceptions and ISA Execution + Environment. + + 6:0 Reserved + Project: All + Format: MBZ +3 31:10 Scratch Space Base Pointer + Project: All + Format: GeneralStateOffset[31:10]ScratchSpace + Specifies the 1k-byte aligned address offset to scratch space for use by the kernel. This pointer is + relative to the General State Base Address. + + 9:4 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 285 + 3DSTATE_PS + + Format: MBZ + 3:0 Per Thread Scratch Space + Project: All + Format: U4 + Specifies the amount of scratch space allowed to be used by each thread. The driver must allocate + enough contiguous scratch space, pointed to by the Scratch Space Pointer, to ensure that the + Maximum Number of Threads each get Per Thread Scratch Space size without exceeding the driver- + allocated scratch space. + Value Name + [0,11] indicating [1k bytes, 2M bytes] in powers of two +4 31:24 Maximum Number of Threads + + Format: U8-1 representing thread count + + + + + Description Project + Range: + WIZ Hashing Disable in GT_MODE register enabled: Range = [7,171] --> [8,172] threads. + Only odd values are allowed (resulting in even max number of threads) + WIZ Hashing Disable in GT_MODE register disabled: Range = [3,85] --> [4,86] threads. Only + odd values are allowed (resulting in even max number of threads) + Specifies the maximum number of simultaneous threads allowed to be active. Used to avoid + using up the scratch space, or to avoid potential deadlock. + + + + Value Name Description Project + [3h,2fh] Range [4,48] threads + + + Programming Notes + If this field is changed between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at + Pixel Scoreboard set is required to be issued. This field must have an odd value so that the max + number of PS threads is even. + 23:12 Reserved + + Format: MBZ + 11 Push Constant Enable + Project: All + Format: Enable + This field must be enabled if the sum of the PS Constant Buffer [3:0] Read Length fields in + 3DSTATE_CONSTANT_PS is nonzero, and must be disabled if the sum is zero. + + 10 Attribute Enable + Project: All + Format: Enable + This field must be enabled if the Number of SF Output Attributes field in 3DSTATE_SBE is nonzero, + and must be disabled if that field is zero. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 286 + 3DSTATE_PS + 9 oMask Present to RenderTarget + Project: All + Format: Enable + This bit is inserted in the PS payload header and made available to the DataPort (either via the + message header or via header bypass) to indicate that oMask data (one or two phases) is included in + Render Target Write messages. If present, the oMask data is used to mask off samples. + + 8 Render Target Fast Clear Enable + Project: All + Format: Enable + This field is set to enable fast clear of the bound render targets. See “Render Target Fast Clear” for + restrictions on enabling this field. + + 7 Dual Source Blend Enable + Project: All + Format: Enable + This field is set if dual source blend is enabled. If this bit is disabled, the data port dual source message + reverts to a single source message using source 0. + + 6 Render Target Resolve Enable + Project: All + Format: Enable + This field is set to enable clear value resolve on non-multisampled render targets. See “Render Target + Resolve” for restrictions on enabling this field. + + 5 Reserved + + Format: MBZ + 4:3 Position XY Offset Select + Project: All + Format: U2 Enumerated Type + + + This field specifies if/what Position XY Offset values are passed in the PS payload. Note that these are + per-slot (pixel|sample) offsets, and therefore separate from the subspan XY coordinates passed in R1. + Value Name Description Project + 0h POSOFFSET_NONE No Position XY Offsets are included in the PS All + payload. + 1h Reserved All + 2h POSOFFSET_CENTROID Position XY Offsets will be passed in the PS payload, All + and these will reflect the Centroid position(s). + 3h POSOFFSET_SAMPLE Position XY Offsets will be passed in the PS payload, All + and these will reflect the multisample position(s). + + + Programming Notes + SW Recommendation: If the PS kernel needs the Position Offsets to compute a Position XY value, this + field should match Position ZW Interpolation Mode to ensure a consistent position.xyzw computation + If the PS kernel does not need the Position XY Offsets to compute a Position Value, then this field + should be programmed to POSOFFSET_NONE, as the PS kernel should be using the various + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 287 + 3DSTATE_PS + + barycentric inputs to evaluate other-than-position attributes. However, this field can be used to pass + Centroid or Sample offsets in the payload for special test modes (e.g., where barycentric coordinates + are computed in the PS vs. being HW-generated and passed in the payload). + MSDISPMODE_PERSAMPLE is required in order to select POSOFFSET_SAMPLE. + 2 32 Pixel Dispatch Enable + Project: All + Format: Enable + + + Description Project + Enables the Windower to dispatch 8 subspans in one payload. + + Note: in the table below, the Valid column indicates which products that combination is + supported on. Combinations of dispatch enables not listed in the table are not available on any + product. + A: Valid + B: Valid + D: Valid, except when in non-1x PERSAMPLE mode. + E: Valid, except when in PERSAMPLE mode with number of multisamples >= 8. + F: Valid. + Each of the three KSP values are separately specified. + In addition, each kernel has a separately-specified GRF register count. + Variable Pixel Dispatch Section: Pixel Grouping (Dispatch size) control for valid pixel dispatch + combinations. + 1 16 Pixel Dispatch Enable + Project: All + Format: Enable + + + Description Project + Enables the Windower to dispatch 4 subspans in one payload. + + Note: in the table below, the Valid column indicates which products that combination is + supported on. Combinations of dispatch enables not listed in the table are not available on any + product. + A: Valid + B: Valid + D: Valid, except when in non-1x PERSAMPLE mode. + E: Valid, except when in PERSAMPLE mode with number of multisamples >= 8. + F: Valid. + Each of the three KSP values are separately specified. + In addition, each kernel has a separately-specified GRF register count. + Variable Pixel Dispatch Section: Pixel Grouping (Dispatch size) control for valid pixel dispatch + combinations. + 0 8 Pixel Dispatch Enable + Project: All + Format: Enable + + + Description Project + Enables the Windower to dispatch 2 subspans in one payload. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 288 + 3DSTATE_PS + + + Note: in the table below, the Valid column indicates which products that combination is + supported on. Combinations of dispatch enables not listed in the table are not available on any + product. + A: Valid + B: Valid + D: Valid, except when in non-1x PERSAMPLE mode. + E: Valid, except when in PERSAMPLE mode with number of multisamples >= 8. + F: Valid.. + Each of the three KSP values are separately specified. + In addition, each kernel has a separately-specified GRF register count. + Variable Pixel Dispatch Section: Pixel Grouping (Dispatch size) control for valid pixel dispatch + combinations. +5 31:23 Reserved + Project: All + Format: MBZ + 22:16 Dispatch GRF Start Register for Constant/Setup Data [0] + Project: All + Format: U7 + Specifies the starting GRF register number for the Constant/Setup portion of the thread payload for + kernel[0]. + Value Name + [0,127] + 15 Reserved + Project: All + Format: MBZ + 14:8 Dispatch GRF Start Register for Constant/Setup Data [1] + Project: All + Format: U7 + Specifies the starting GRF register number for the Constant/Setup portion of the thread payload for + kernel[1]. + Value Name + [0,127] + 7 Reserved + Project: All + Format: MBZ + 6:0 Dispatch GRF Start Register for Constant/Setup Data [2] + Project: All + Format: U7 + Specifies the starting GRF register number for the Constant/Setup portion of the thread payload for + kernel[2]. + Value Name + [0,127] +6 31:6 Kernel Start Pointer[1] + Project: All + Format: InstructionBaseOffset[31:6]Kernel + Specifies the 64-byte aligned address offset of the first instruction in kernel[1]. This pointer is relative to + the Instruction Base Address. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 289 + 3DSTATE_PS + + + 5:0 Reserved + Project: All + Format: MBZ +7 31:6 Kernel Start Pointer[2] + Project: All + Format: InstructionBaseOffset[31:6]Kernel + Specifies the 64-byte aligned address offset of the first instruction in kernel[2]. This pointer is relative to + the Instruction Base Address. + + 5:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 290 + 11.2.3 3DSTATE_CONSTANT_PS + 3DSTATE_CONSTANT_PS + + +Source: RenderCS +Length Bias: 2 +This command sets pointers to the push constants for the PS unit. The constant data pointed to by this command is +loaded into the PS unit’s push constant buffer (PCB). + Programming Notes Project +It is invalid to execute this command more than once between 3D_PRIMITIVE commands. +Constant buffers must be enabled in order from Constant Buffer 0 to Constant Buffer 3 within this command. +For example, it is not allowed to enable Constant Buffer 1 by programming a non-zero value in the PS +Constant Buffer 1 Read Length without a non-zero value in PS Constant Buffer 0 Read Length. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 17h 3DSTATE_CONSTANT_PS + Format: OpCode + 15:8 Reserved + + Format: MBZ + 7:0 Dword Length + Project: All + Format: =n Total Length – 2 + + + + + Value Name Project + 5h Excludes DWord (0,1) [Default] +1..6 191:0 Constant Body + + Format: 3DSTATE_CONSTANT(Body) + Following table is the shared portion of the 3DSTATE_CONSTANT command for VS, HS, DS, + and GS + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 291 + 11.2.4 3DSTATE_PUSH_CONSTANT_ALLOC_PS + 3DSTATE_PUSH_CONSTANT_ALLOC_PS + + + Source: RenderCS + Length Bias: 2 + Description Project + This command sets up the URB configuration for PS Push Constant Buffer. + A PIPE_CONTOL command with the CS Stall bit set must be programmed in the ring after this instruction. + Programming Notes + Restriction: + + + + The sum of the Constant Buffer Offset and the Constant Buffer Size may not exceed the maximum value of the + Constant Buffer Size. + + The sum of the constant length programmed in 3DSTATE_CONSTANT_PS must be equal or smaller then the + size of the allocated space in the URB including the buffering for half cachelines. See Push Constant URB + Allocation section for more details. + + The 3DSTATE_CONSTANT_PS must be reprogrammed prior to the next 3DPRIMITIVE command after + programming the 3DSTATE_PUSH_CONSTANT_ALLOC_PS. + + + DWord Bit Description + 0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 16h 3DSTATE_PUSH_CONSTANT_ALLOC_PS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 Dword Length + Default Value: 0h Excludes Dword (0,1) + Project: All + Format: =n Total Length – 2 + + + + 1 31:20 Reserved + + Format: MBZ + + + + + Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 292 + 3DSTATE_PUSH_CONSTANT_ALLOC_PS + 19:16 Constant Buffer Offset + + Format: U5 + Specifies the offset of the PS constant buffer into the URB. + Value Name + [0,15] (0KB - 15KB) + 0h 0KB [Default] + 15:5 Reserved + + Format: MBZ + 4:0 Constant Buffer Size + + Format: U5 + Specifies the size of the PS constant buffer. This value will determine the amount of data the command + stream can pre-fetch before the buffer is full. Value of zero is only valid when constants are not + enabled for PS. + Value Name + [0,15] (0KB – 15KB) Increments of 1KB + 0h 0KB [Default] + + + + +11.2.5 3DSTATE_SAMPLE_MASK +The sample mask state used by the windower stage is defined with this inline state packet. + + 3DSTATE_SAMPLE_MASK + + +Source: RenderCS +Length Bias: 2 +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 18h 3DSTATE_SAMPLE_MASK + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 Dword Length + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 293 + 3DSTATE_SAMPLE_MASK + + Default Value: 0h Excludes Dword (0,1) + Project: All + Format: =n Total Length – 2 + + + +1 31:8 Reserved + + Format: MBZ + 7:0 Sample Mask + + Format: 8 bit mask Right-justified bitmask (Bit 0 = Sample0). Number of bits that are used is + determined by Num Multisamples (3DSTATE_MULTISAMPLE) + + + A per-multisample-position mask state variable that is immediately and unconditionally ANDed with the + sample coverage mask as part of the rasterization process. This mask is applied prior to centroid + selection. + Programming Notes + +  + If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field must be zero. +  + If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field must be zero. + + + + +11.3 Rasterization +The WM unit uses the setup computations performed by the SF unit to rasterize objects into the +corresponding set of pixels Most of the controls regarding the screen-space geometry of rendered objects +are programmed via the SF unit. +The rasterization process generates pixels in 2x2 groups of pixels called subspans (see UNRESOLVED +CROSS REFERENCE, Pixels with a SubSpan) which, after being subjected to various inclusion/discard +tests, are grouped and passed to spawned Pixel Shader (PS) threads for subsequent processing Once +these PS threads are spawned, the WM unit provides only bookkeeping functions on the pixels Note that +the WM unit can proceed on to rasterize subsequent objects while PS threads from previous objects are +still executing. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 294 + Pixels with a SubSpan + + + + +11.3.1 Drawing Rectangle Clipping +The Drawing Rectangle defines the maximum extent of pixels which can be rendered Portions of objects +falling outside the Drawing Rectangle will be clipped (pixels discarded) Implementations will typically +discard objects falling completely outside of the Drawing Rectangle as early in the pipeline as possible +There is no control to turn off Drawing Rectangle clipping – it is unconditional. +For the purposes of clipping, the Drawing Rectangle must itself be clipped to the destination buffer +extents (The Drawing Rectangle Origin, used to offset relative X,Y coordinates earlier in the pipeline, is +permitted to lie offscreen). The Clipped Drawing Rectangle X,Y Min,Max state variables (programmed +via 3DSTATE_DRAWING_RECTANGLE – See SF Unit) defines the intersection of the Drawing +Rectangle and the Color Buffer It is specified with non-negative integer pixel coordinates relative to the +Destination Buffer upper-left origin. +Pixels with coordinates outside of the Drawing Rectangle cannot be rendered (i.e., the rectangle is +inclusive) For example, to render to a full-screen 1280x1024 buffer, the following values would be +required: Xmin=0, Ymin=0, Xmax=1279 and Ymax=1023 +For “full screen” rendering, the Drawing Rectangle coincides with the screen-sized buffer For “front-buffer +windowed” rendering it coincides with the destination “window”. + + +11.3.2 Line Rasterization +See SF Unit chapter for details on the screen-space geometry of the various line types. + +11.3.2.1 Coverage Values for Anti-Aliased Lines +The WM unit is provided with both the Line Anti-Aliasing Region Width and Line End Cap Anti- +aliasing Region Width state variables (in WM_STATE) in order to compute the coverage values for anti- +aliased lines + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 295 + 11.3.2.2 3DSTATE_AA_LINE_PARAMS + 3DSTATE_AA_LINE_PARAMETERS + + +Source: RenderCS +Length Bias: 2 +The 3DSTATE_AA_LINE_PARAMS command is used to specify the slope and bias terms used in the improved +alpha coverage computation (specifically for DX WHQL compliance). Note that in these devices the coverage values +passed to PS threads are full U0.8 values. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 0Ah 3DSTATE_AA_LINE_PARAMS + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 Dword Length + Default Value: 1h Excludes Dword (0,1) + Project: All + Format: =n Total Length – 2 + + + +1 31:24 Reserved + + Format: MBZ + 23:16 AA Coverage Bias + Project: All + Format: U0.8 + This field specifies the bias term to be used in the aa coverage computation for edges 0 and 3. + + 15:8 Reserved + + Format: MBZ + 7:0 AA Coverage Slope + Project: All + Format: U0.8 + This field specifies the slope term to be used in the aa coverage computation for edges 0 and 3.If this + field is zero, the Windower will revert to legacy aa line coverarge computation (though still output + expanded U0.8 coverage values). + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 296 + 3DSTATE_AA_LINE_PARAMETERS + + +2 31:24 Reserved + + Format: MBZ + 23:16 AA Coverage EndCap Bias + Project: All + Format: U0.8 + This field specifies the bias term to be used in the aa coverage computation for edges 1 and 2. + + 15:8 Reserved + + Format: MBZ + 7:0 AA Coverage EndCap Slope + Project: All + Format: U0.8 + This field specifies the slope term to be used in the aa coverage computation for edges 1 and 2. + + + + +The slope and bias values should be computed to closely match the reference rasterizer results Based on +empirical data, the following recommendations are offered: +The final alpha for the center of the line needs to be 148 to match the reference rasterizer In this case, +the Lo to edge 0 and edge 3 will be the same Since the alpha for each edge is multiplied together, we get: +edge0alpha * edge1alpha = 148/255 = 0.580392157 +Since edge0alpha = edge3alpha we get: +(edge0alpha)2 = 0.580392157 +edge0alpha = sqrt(0.580392157) = 0.761834731 at the center pixel +The desired alpha for pixel 1 = 54/255 = 0.211764706 +The slope is (0.761834731 – 0.211764706) = 0.550070025 +Since we are using 8 bit precision, the slope becomes +AA Coverage [EndCap] Slope = 0.55078125 +The alpha value for Lo = 0 (second pixel from center) determines the bias term and is equal to +(0.211764706 – 0.550070025) = -0.338305319 +With 8 bits of precision the programmed bias value +AA Coverage [EndCap] Bias = 0.33984375 + +11.3.2.3 Line Stipple +Line stipple, controlled via the Line Stipple Enable state variable in WM_STATE, discards certain pixels +that are produced by non-AA line rasterization. +The line stipple rule is specified via the following state variables programmed via +3DSTATE_LINE_STIPPLE: the 16-bit Line Stipple Pattern (p), Line Stipple Repeat Count I, and Line + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 297 + Stipple Inverse Repeat Count. Sofware must compute Line Stipple Inverse Repeat Count as 1.0f / +Line Stipple Repeat Count and then converted from float to the required fixed point encoding (see +3STATE_LINE_STIPPLE). +The WM unit maintains an internal Line Stipple Counter state variable (s) The initial value of s is zero; s is +incremented after production of each pixel of a line segment (pixels are produced in order, beginning at +the starting point and working towards the ending point). S is reset to 0 whenever a new primitive is +processed (unless the primitive type is LINESTRIP_CONT or LINESTRIP_CONT_BF), and before every +line segment in a group of independent segments (LINELIST primitive). +During the rasterization of lines, the WM unit computes: + + +A pixel is rendered if the bth bit of p is 1, otherwise it is discarded. The bits of p are numbered with 0 +being the least significant and 15 being the most significant. + +11.3.2.4 3DSTATE_LINE_STIPPLE + 3DSTATE_LINE_STIPPLE + + +Source: RenderCS +Length Bias: 2 +The 3DSTATE_LINE_STIPPLE command is used to specify state variables used in the Line Stipple function. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 08h 3DSTATE_LINE_STIPPLE + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 Dword Length + Default Value: 1h Excludes Dword (0,1) + Project: All + Format: =n Total Length – 2 + + + +1 31 Modify Enable (Current Repeat Counter, Current Stipple Index) + Project: All + Format: Enable + Modify enable for Current Repeat Counter and Current Stipple Index fields. + Programming Notes + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 298 + 3DSTATE_LINE_STIPPLE + Software should never set this field to enabled. It is provided only for HW-generated commands as part + of context save/restore. + 30 Reserved + Project: All + Format: MBZ + 29:21 Current Repeat Counter + Project: All + Format: U9 + This field sets the HW-internal repeat counter state. Note: Software should never attempt to set this + value – this state is only provided for HW-generated commands as part of context save/restore. + + 20 Reserved + Project: All + Format: MBZ + 19:16 Current Stipple Index + Project: All + Format: U4 + This field sets the HW-internal stipple pattern index. + Note: Software should never attempt to set this value – this state is only provided for HW-generated + commands as part of context save/restore. + + 15:0 Line Stipple Pattern + Project: All + Format: 16 bit mask Bit 15 = most significant bit, Bit 0 = least significant bit + + + Specifies a pattern used to mask out bit specific pixels while rendering lines. + +2 31:15 Line Stipple Inverse Repeat Count + Project: All + Format: U1.16 + + + Range: [0.00390625, 1.0] + Specifies the inverse (truncated) of the repeat count for the line stipple function. + 14:9 Reserved + Project: All + Format: MBZ + 8:0 Line Stipple Repeat Count + Project: All + Format: U9 + Specifies the repeat count for the line stipple function. + Value Name + [1, 256] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 299 + 11.3.3 Polygon (Triangle and Rectangle) Rasterization +The rasterization of LINE, TRIANGLE, and RECTANGLE objects into pixels requires a “pixel sampling +grid” to be defined This grid is defined as an axis-aligned array of pixel sample points spaced exactly 1 +pixel unit apart If a sample point falls within one of these objects, the pixel associated with the sample +point is considered “inside” the object, and information for that pixel is generated and passed down the +pipeline +For TRIANGLE and RECTANGLE objects, if a sample point intersects an edge of the object, the +associated pixel is considered “inside” the object if the intersecting edge is a “left” or “top” edge (or, more +exactly, the intersected edge is not a “right” or “bottom” edge) Note that “top” and “bottom” edges are by +definition exactly horizontal. See UNRESOLVED CROSS REFERENCE, TRIANGLE and RECTANGLE +Edge Types, for the edge types for representative TRIANGLE and RECTANGLE objects (solid edges are +inclusive, dashed edges are exclusive). + +TRIANGLE and RECTANGLE Edge Types + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 300 + 11.3.3.1 Polygon Stipple +The Polygon Stipple function, controlled via the Polygon Stipple Enable state variable in WM_STATE, +allows only selected pixels of a repeated 32x32 pixel pattern to be rendered Polygon stipple is applied +only to the following primitive types: + + 3DPRIM_POLYGON + + 3DPRIM_TRIFAN + + 3DPRIM_TRILIST + + 3DPRIM_TRISTRIP + + 3DPRIM_TRISTRIP_REVERSE + +Note that the 3DPRIM_TRIFAN_NOSTIPPLE object is never subject to polygon stipple. +The stipple pattern is defined as a 32x32 bit pixel mask via the 3DSTATE_POLY_STIPPLE_PATTERN +command. This is a non-pipelined command which incurs an implicit pipeline flush when executed. +The origin of the pattern is specified via Polygon Stipple X,Y Offset state variables programmed via the +3DSTATE_POLY_STIPPLE_OFFSET command The offsets are pixel offsets from the Color Buffer origin +to the upper left corner of the stipple pattern. This is a non-pipelined command which incurs an implicit +pipeline flush when executed. + +11.3.3.2 3DSTATE_POLY_STIPPLE_OFFSET + 3DSTATE_POLY_STIPPLE_OFFSET + +Project: All +Source: RenderCS +Length Bias: 2 +The 3DSTATE_POLY_STIPPLE_OFFSET command is used to specify the origin of the repeated screen-space +Polygon Stipple Pattern as an X,Y offset from the Color Buffer origin. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 06h 3DSTATE_POLY_STIPPLE_OFFSET + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 Dword Length + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 301 + 3DSTATE_POLY_STIPPLE_OFFSET + + Default Value: 0h Excludes Dword (0,1) + Project: All + Format: =n Total Length – 2 + + + +1 31:13 Reserved + Project: All + Format: MBZ + 12:8 Polygon Stipple X Offset + Project: All + Format: U5 + Specifies a 5 bit x address offset in the poly stipple pattern + Value Name + [0,31] + 7:5 Reserved + Project: All + Format: MBZ + 4:0 Polygon Stipple Y Offset + Project: All + Format: U5 + Specifies a 5 bit y address offset in the poly stipple pattern + Value Name + [0,31] + + + +11.3.3.3 3DSTATE_POLY_STIPPLE_PATTERN + 3DSTATE_POLY_STIPPLE_PATTERN + +Project: All +Source: RenderCS +Length Bias: 2 +The 3DSTATE_POLY_STIPPLE_PATTERN command is used to specify the 32x32 Polygon Stipple Pattern used in +the Polygon Stipple function of the WM unit. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 07h 3DSTATE_POLY_STIPPLE_PATTERN + Format: OpCode + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 302 + 3DSTATE_POLY_STIPPLE_PATTERN + 15:8 Reserved + Project: All + Format: MBZ + 7:0 Dword Length + Default Value: 1Fh Excludes Dword (0,1) + Project: All + Format: =n Total Length – 2 + + + +1 31:0 Polygon Stipple Pattern Row 1 (top most) + Project: All + Format: 32 bit mask Bit 31 = upper left corner, Bit 0 = upper right corner of first row. + + + Specifies a pattern used by Polygon Stipple to mask out specific pixels of every 32x32 area + rendered. + +2..32 31:0 Polygon Stipple Pattern Rows 2-32 (bottom most) + Project: All + Format: 32 bit mask Bit 31 = upper left corner, Bit 0 = upper right corner of first row. + + + Specifies a pattern used by Polygon Stipple to mask out specific pixels of every 32x32 area + rendered. + + + + +11.4 Multisampling +The multisampling function has two components: + +  Multisample Rasterization: multisample rasterization occurs at a subpixel level, wherein each pixel + consists of a number of “samples” at state-defined positions within the pixel footprint Coverage of the + primitive as well as color calculator operations (stencil test, depth test, color buffer blending, etc.) are + done at the sample level In addition the pixel shader itself can optionally run at the sample level + depending on a separate state field. +  Multisample Render Targets (MSRT): The render targets, as well as the depth and stencil buffers, + now have the ability to store per-sample values When combined with multisample rasterization, color + calculator operations such as stencil test, depth test, and color buffer blending are done with the + destination surface containing potentially different values per sample. + + +11.4.1 Multisample Modes/State +A number of state variables control the operation of the multisampling function. The following list indicates +the state and their location. Refer to the state definition for more details. + +  Multisample Rasterization Mode (3DSTATE_SF and 3DSTATE_WM): controls whether + rasterization of non-lines is performed on a pixel or sample basis (PIXEL vs. PATTERN), and + whether multisample rasterization of lines enabled (OFF vs. ON). + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 303 +  Multisample Dispatch Mode (3DSTATE_WM ): controls whether the pixel shader is executed per + pixel or per sample. +  Number of Multisamples (3DSTATE_MULTISAMPLE and SURFACE_STATE): indicates the + number of samples per pixel contained on the surface. This field in 3DSTATE_MULTISAMPLE must + match the corresponding field in SURFACE_STATE for each render target. The depth, hierarchical + depth, and stencil buffers inherit this field from 3DSTATE_MULTISAMPLE. +  Pixel Location (3DSTATE_MULTISAMPLE): indicates the subpixel location where values specified + as “pixel” are sampled. This is either the upper left corner or the center. +  MSAA Sample Offsets (3DSTATE_MULTISAMPLE ] ): for each of the N samples, specifies the + subpixel location of each sample. + + +11.4.2 3DSTATE_MULTISAMPLE + 3DSTATE_MULTISAMPLE + + +Source: RenderCS +Length Bias: 2 + +The 3DSTATE_MULTISAMPLE command is used to specify multisample state associated with the current render +target/depth buffer. This is non-pipelined state. +Programming Restriction: +Driver must ierarchi that all the caches in the depth pipe are flushed before this command is parsed. This requires +driver to send a PIPE_CONTROL with a CS stall along with a Depth Flush prior to this command. +When this command is issued, the currently active depth buffer, hierarchical depth buffer, stencil buffer, and render +target(s) must be cleared (meaning that every pixel must be overwritten). Alternatively, other surfaces can be +activated before issuing the next 3DPRIMITIVE that were previously rendered with the same values of all state +fields in this command. In other words, it is illegal to render to these surfaces with multiple different values of the +state fields in this command. + Programming Notes +When programming the sample offsets (for NUMSAMPLES_4 or _8 and MSRASTMODE_xxx_PATTERN), + the order of the samples 0 to 3 (or 7 for 8X) must have monotonically increasing distance + from the pixel center. This is required to get the correct centroid computation in the + device. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 0Dh 3DSTATE_MULTISAMPLE + Format: OpCode + 15:8 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 304 + 3DSTATE_MULTISAMPLE + + Format: MBZ + 7:0 Dword Length + Project: All + Format: =n Total Length – 2 + + + Excludes Dword (0,1) + Value Name Project + 2h [Default] +1 31:6 Reserved + Project: All + Format: MBZ + 5 Reserved + + Format: MBZ + 4 Pixel Location + Project: All + Format: U1 + This field specifies where the device evaluates “pixel” (vs. centroid or sample) values/attributes. + Value Name Description Project + 0h PIXLOC_CENTER Use the pixel center (0.5, 0.5 offset) All + 1h PIXLOC_UL_CORNER Use the pixel upper-left corner All + + + Programming Notes + The programming of this field is assumed to be a function of the API being supported. Specifically, it + is expected that OpenGL and DX10+ APIs require CENTER selection, while DX9- APIs require + UL_CORNER selection. + 3:1 Number of Multisamples + Project: All + Format: U3 enumerated value + + + This field specifies how many samples/pixel exist in all RTs and the Depth Buffer, as log2(#samples). + This field is valid regardless of the setting of Multisample Rasterization Mode. + Value Name Description Project + 0h NUMSAMPLES_1 1 sample/pixel All + 1h Reserved All + 2h NUMSAMPLES_4 4 samples/pixel All + 3h NUMSAMPLES_8 8 samples/pixel All + [4h,7h] Reserved All + + + Programming Notes + Setting Multisample Rasterization Mode to MSRASTMODE_xxx_PATTERN when Number of + Multisamples == NUMSAMPLES_1 is UNDEFINED. + The setting of this field must match the Number of Multisamples field in SURFACE_STATE of all + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 305 + 3DSTATE_MULTISAMPLE + bound render targets. + + 0 Reserved + Project: All + Format: MBZ +2 31:28 Sample3 X Offset + Project: All + Format: U0.4 + + + Description Project + Subpixel X offset of Sample 3 relative to the UL pixel origin. Valid only when + NUMSAMPLES_4 or _8. Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Valid when NUMSAMPLES_1 + + + + Value Name + [0,15] [0,0.9375] + 27:24 Sample3 Y Offset + Project: All + Format: U0.4 + + + Description Project + Subpixel Y offset of Sample 3 relative to the UL pixel origin. Valid only when + NUMSAMPLES_4 or _8. Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Valid when NUMSAMPLES_1 + + + + Value Name + [0,15] [0,0.9375] + 23:20 Sample2 X Offset + Project: All + Format: U0.4 + + + Description Project + Subpixel X offset of Sample 2 relative to the UL pixel origin. Valid only when + NUMSAMPLES_4 or _8. Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Valid when NUMSAMPLES_1 + + + + Value Name + [0,15] [0,0.9375] + 19:16 Sample2 Y Offset + Project: All + Format: U0.4 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 306 + 3DSTATE_MULTISAMPLE + Description Project + Subpixel Y offset of Sample 2 relative to the UL pixel origin. Valid only when + NUMSAMPLES_4 or _8. Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Valid when NUMSAMPLES_1 + + + + Value Name + [0,15] [0,0.9375] + 15:12 Sample1 X Offset + Project: All + Format: U0.4 + + + Description Project + Subpixel X offset of Sample 1 relative to the UL pixel origin. Valid only when + NUMSAMPLES_4 or _8. Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Valid when NUMSAMPLES_1 + + + + Value Name + [0,15] [0,0.9375] + 11:8 Sample1 Y Offset + Project: All + Format: U0.4 + + + Description Project + Subpixel Y offset of Sample 1 relative to the UL pixel origin. Valid only when + NUMSAMPLES_4 or _8. Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Valid when NUMSAMPLES_1 + + + + Value Name + [0,15] [0,0.9375] + 7:4 Sample0 X Offset + Project: All + Format: U0.4 + + + Description Project + Subpixel X offset of Sample 0 relative to the UL pixel origin. Valid only when + NUMSAMPLES_4 or _8. Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Valid when NUMSAMPLES_1 + + + + Value Name + [0,15] [0,0.9375] + 3:0 Sample0 Y Offset + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 307 + 3DSTATE_MULTISAMPLE + + Format: U0.4 + + + Description Project + Subpixel Y offset of Sample 0 relative to the UL pixel origin. Valid only when + NUMSAMPLES_4 or _8. Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Valid when NUMSAMPLES_1 + + + + Value Name + [0,15] [0,0.9375] +3 31:28 Sample7 X Offset + + Format: U0.4 + Subpixel X offset of Sample 7 relative to the UL pixel origin. Valid only when NUMSAMPLES_8. + Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Value Name + [0,15] [0,0.9375] + 27:24 Sample7 Y Offset + + Format: U0.4 + Subpixel Y offset of Sample 7 relative to the UL pixel origin. Valid only when NUMSAMPLES_8. + Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Value Name + [0,15] [0,0.9375] + 23:20 Sample6 X Offset + + Format: U0.4 + Subpixel X offset of Sample 6 relative to the UL pixel origin. Valid only when NUMSAMPLES_8. + Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Value Name + [0,15] [0,0.9375] + 19:16 Sample6 Y Offset + + Format: U0.4 + Subpixel Y offset of Sample 6 relative to the UL pixel origin. Valid only when NUMSAMPLES_8. + Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Value Name + [0,15] [0,0.9375] + 15:12 Sample5 X Offset + + Format: U0.4 + Subpixel X offset of Sample 5 relative to the UL pixel origin. Valid only when NUMSAMPLES_8. + Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Value Name + [0,15] [0,0.9375] + 11:8 Sample5 Y Offset + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 308 + 3DSTATE_MULTISAMPLE + + + Format: U0.4 + Subpixel Y offset of Sample 5 relative to the UL pixel origin. Valid only when NUMSAMPLES_8. + Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Value Name + [0,15] [0,0.9375] + 7:4 Sample4 X Offset + + Format: U0.4 + Subpixel X offset of Sample 4 relative to the UL pixel origin. Valid only when NUMSAMPLES_8. + Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Value Name + [0,15] [0,0.9375] + 3:0 Sample4 Y Offset + + Format: U0.4 + Subpixel Y offset of Sample 4 relative to the UL pixel origin. Valid only when NUMSAMPLES_8. + Setting ignored when not in MSRASTMODE_xxx_PATTERN mode. + Value Name + [0,15] [0,0.9375] + + + + +11.5 Early Depth/Stencil Processing +The Windower/IZ unit provides the Early Depth Test function, a major performance-optimization feature +where an attempt is made to remove pixels that fail the Depth and Stencil Tests prior to pixel shading. +This requires the WM unit to perform the interpolation of pixel (“source”) depth values, read the current +(“destination”) depth values from the cached depth buffer, and perform the Depth and Stencil Tests As +the WM unit has per-pixel source and destination Z values, these values are passed in the PS thread +payload, if required. + + +11.5.1 Depth Offset +The depth offset function is contained in SF unit, thus the state to control it is also contained in SF unit. +There are occasions where the Z position of some objects need to be slightly offset in order to reduce +artifacts due to coplanar or near-coplanar primitives A typical example is drawing the edges of triangles +as wireframes – the lines need to be drawn slightly closer to the viewer to ensure they will not be +occluded by the underlying polygon Another example is drawing objects on a wall – without a bias on the +z positions, they might be fully or partially occluded by the wall. +The device supports global depth offset, applied only to triangles, that bases the offset on the object’s z +slope Note that there is no clamping applied at this stage after the Z position is offset – clamping to [0,1] +can be performed later after the Z position is interpolated to the pixel This is preferable to clamping prior +to interpolation, as the clamping would change the Z slope of the entire object. +The Global Depth Offset function is controlled by the Global Depth Offset Enable state variable in +WM_STATE Global Depth Offset is only applied to 3DOBJ_TRIANGLE objects. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 309 + When Global Depth Offset Enable is ENABLED, the pipeline will compute: +MaxDepthSlope = max(abs(dZ/dX),abs(dz/dy)) // approximation of max depth slope for polygon +When UNORM Depth Buffer is at Output Merger (or no Depth Buffer): +Bias = GlobalDepthOffsetConstant * r + GlobalDepthOffsetScale * MaxDepthSlope + + +Where r is the minimum representable value > 0 in the depth buffer format, converted to float32 (note: If +state bit Legacy Global Depth Bias Enable is set, the r term will be forced to 1.0) +When Floating Point Depth Buffer at Output Merger: + Bias = GlobalDepthOffsetConstant * 2^(exponent(max z in primitive) – r) + GlobalDepthOffsetScale + * MaxDepthSlope + + +Where r is the # of mantissa bits in the floating point representation (excluding the hidden bit), e.g. 23 for +float32 (note: If state bit Legacy Global Depth Bias Enable is set, no scaling is applied to the +GobalDepthOffsetConstant). +Adding Bias to z: + if (GlobalDepthOffsetClamp > 0) + Bias = min(DepthBiasClamp, Bias) + else if(GlobalDepthOffsetClamp < 0) + Bias = max(DepthBiasClamp, Bias) + // else if GlobalDepthOffsetClamp == 0, no clamping occurs + z = z + Bias +Biasing is constant for a given primitive The biasing formulas are performed with float32 arithmetic Global +Depth Bias is not applied to any point or line primitives + + +11.5.2 Early Depth Test/Stencil Test/Write +When Early Depth Test Enable is ENABLED, the WM unit will attempt to discard depth-occluded pixels +during scan conversion (before processing them in the Pixel Shader) Pixels are only discarded when the +WM unit can ensure that they would have no impact to the ColorBuffer or DepthBuffer This function is +therefore only a performance feature. +Note: The Early Depth Test Enable bit is no longer present. This function is always enabled. +If some pixels within a subspan are discarded, only the pixel mask is affected indicating that the +discarded pixels are not active If all pixels within a subspan are discarded, that subspan will not even be +dispatched. + +11.5.2.1 Software-Provided PS Kernel Info +In order for the WM unit to properly perform Early Depth Test and supply the proper information in the PS +thread payload (and even determine if a PS thread needs to be dispatched), it requires information +regarding the PS kernel operation This information is provided by a number of state bits in WM_STATE, +as summarized in the following table. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 310 + State Bit Description + +Pixel Shader This must be set when there is a chance that valid pixels passed to a PS thread may be discarded. +Kill Pixel This includes the discard of pixels by the PS thread resulting from a “killpixel” or “alphatest” function + or as dictated by the results of the sampling of a “chroma-keyed” texture The WM unit needs this + information to prevent early depth/stencil writes for pixels which might be killed by the PS thread, + etc. + + See WM_STATE/3DSTATE_WM for more information. +Pixel Shader This must be set when the PS thread computes the “source” depth value (i.e., from the API POV, +Computed writes to the “oDepth” output) In this case the WM unit can’t make any decisions based on the WM- +Depth interpolated depth value. + + See WM_STATE/3DSTATE_WM for more information. +Pixel Shader Must be set if the PS thread requires the WM-interpolated source depth value This will force the +Uses Source source depth to be passed in the thread payload where otherwise the WM unit would not have seen +Depth it as required. + + See WM_STATE/3DSTATE_WM for more information. + + +11.5.3 Hierarchical Depth Buffer +A hierarchical depth buffer is supported beginning with to reduce memory traffic due to depth buffer +accesses This buffer is supported only in Tile Y memory. +The Surface Type, Height, Width, Depth, Minimum Array Element, Render Target View Extent, and +Depth Coordinate Offset X/Y of the hierarchical depth buffer are inherited from the depth buffer The +height and width of the hierarchical depth buffer that must be allocated are computed by the following +formulas, where HZ is the hierarchical depth buffer and Z is the depth buffer The Z_Height, Z_Width, and +Z_Depth values given in these formulas are those present in 3DSTATE_DEPTH_BUFFER incremented +by one. : The value of Z_Height and Z_Width must each be multiplied by 2 before being applied to the +table below if Number of Multisamples is set to NUMSAMPLES_4. The value of Z_Height must be +multiplied by 2 and Z_Width must be multiplied by 4 before being applied to the table below if Number of +Multisamples is set to NUMSAMPLES_8.. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 311 + Since Hierarchical Depth Buffer supports multiple LODs. The HZ_height is different as shown in the table +below: + +Surface Type HZ_Width (bytes) HZ_Height (rows) +SURFTYPE_1D ceiling(Z_Width / 16) * 16 + Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 +SURFTYPE_2D ceiling(Z_Width / 16) * 16 + Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 +SURFTYPE_3D ceiling(Z_Width / 16) * 16 see below +SURFTYPE_CUBE ceiling(Z_Width / 16) * 16 + Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 + +where, Qpitch is computed using vertical alignment j=8, please refer to the GPU overview volume for +Qpitch definition. +The minimum HZ_Height required for a 3D surface must be computed based on hL parameters +documented in the GPU Overview volume, and the maximum LOD m: + + + + +In order to compute the minimum QPitch for the HZ surface, the height of each LOD in pixels is +determined using the equations for hL in the GPU Overview volume, using a vertical alignment j=8. The +following equation gives the minimum HZ_QPitch based on largest LOD m defined in the surface: + + + + +If m is less than 2, treat all hL with L > m as zero and use the above equation. +The minimum HZ_Height required for a 3D surface must be computed based on hL parameters +documented in the GPU Overview volume, and the maximum LOD m: + + + + +The format of the data in the hierarchical depth buffer is not documented here, as this surface needs only +to be allocated by software Hardware will read and write this surface during operation and its contents are +discarded once the last primitive is rendered that uses the hierarchical depth buffer. +The hierarchical depth buffer can be enabled whenever a depth buffer is defined, with its effect being +invisible other than generally higher performance The only exception is the hierarchical depth buffer must +be disabled when using software tiled rendering. +If HiZ is enabled, you must initialize the clear value by either +a.Perform a depth clear pass to initialize the clear value. +b.Send a 3dstate_clear_params packet with valid = 1 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 312 + Without one of these events, context switching will fail, as it will try to save off a clear value even though +no valid clear value has been set When context restore happens, HW will restore an uninitialized clear +value. + +11.5.3.1 Depth Buffer Clear +With the hierarchical depth buffer enabled, performance is generally improved by using the special clear +mechanism described here to clear the hierarchical depth buffer and the depth buffer This is enabled +though the Depth Buffer Clear field in WM_STATE or 3DSTATE_WM This bit can be used to clear the +depth buffer in the following situations: + +  Complete depth buffer clear +  Partial depth buffer clear with the clear value the same as the one used on the previous clear +  Partial depth buffer clear with the clear value different than the one used on the previous clear can + use this mechanism if a depth buffer resolve is performed first. + +The following is required when performing a depth buffer clear with this field: + +  If other rendering operations have preceded this clear, a PIPE_CONTROL with depth cache flush + enabled, Depth Stall bit enabled must be issued before the rectangle primitive used for the depth + buffer clear operation. +  The fields in 3DSTATE_CLEAR_PARAMS are set to indicate the source of the clear value and (if + source is in this command) the clear value itself. +  A rectangle primitive representing the clear area is delivered. The primitive must adhere to the + following restrictions on size: + o If Number of Multisamples is NUMSAMPLES_1, the rectangle must be aligned to an + 8x4 pixel block relative to the upper left corner of the depth buffer, and contain an + integer number of these pixel blocks, and all 8x4 pixels must be lit. + o If Number of Multisamples is NUMSAMPLES_4, the rectangle must be aligned to a + 4x2 pixel block (8x4 sample block) relative to the upper left corner of the depth buffer, + and contain an integer number of these pixel blocks, and all samples of the 4x2 pixels + must be lit. + o If Number of Multisamples is NUMSAMPLES_8, the rectangle must be aligned to a + 2x2 pixel block (8x4 sample block) relative to the upper left corner of the depth buffer, + and contain an integer number of these pixel blocks, and all samples of the 2x2 pixels + must be list. + +  Depth Test Enable must be disabled and Depth Buffer Write Enable must be enabled (if depth is + being cleared). +  Stencil buffer clear can be performed at the same time by enabling Stencil Buffer Write Enable + Stencil Test Enable must be enabled and Stencil Pass Depth Pass Op set to REPLACE, and the + clear value that is placed in the stencil buffer is the Stencil Reference Value from + COLOR_CALC_STATE. +  Note also that stencil buffer clear can be performed without depth buffer clear For stencil only clear, + Depth Test Enable and Depth Buffer Write Enable must be disabled. +  Pixel Shader Dispatch, Alpha Test, Pixel Shader Kill Pixel and Pixel Shader Computed Depth + must all be disabled. + +Several cases exist where Depth Buffer Clear cannot be enabled (the legacy method of clearing must be +performed): + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 313 +  If the depth buffer format is D32_FLOAT_S8X24_UINT or D24_UNORM_S8_UINT. +  If stencil test is enabled but the separate stencil buffer is disabled. + +11.5.3.2 Depth Buffer Resolve +If the hierarchical depth buffer is enabled, the depth buffer may contain incorrect results after rendering is +complete If the depth buffer is retained and used for another purpose (i.e as input to the sampling engine +as a shadow map), it must first be “resolved” This is done by setting the Depth Buffer Resolve Enable +field in WM_STATE or 3DSTATE_WM and rendering a full render target sized rectangle Once this is +complete, the depth buffer will contain the same contents as it would have had the rendering been +performed with the hierarchical depth buffer disabled. In a typical usage model, depth buffer needs to be +resolved after rendering on it and before using a depth buffer as a source for any consecutive operation. +Depth buffer can be used as a source in three different cases: using it as a texture for the nest rendering +sequence, honoring a lock on the depth buffer to the host OR using the depth buffer as a blit source. +The following is required when performing a depth buffer resolve: + +  A rectangle primitive of the same size as the previous depth buffer clear operation must be + delivered, and depth buffer state cannot have changed since the previous depth buffer clear + operation. +  Depth Test Enable must be enabled with the Depth Test Function set to NEVER Depth Buffer + Write Enable must be enabled Stencil Test Enable and Stencil Buffer Write Enable must be + disabled. +  Pixel Shader Dispatch, Alpha Test, Pixel Shader Kill Pixel and Pixel Shader Computed Depth + must all be disabled. + +11.5.3.3 Hierarchical Depth Buffer Resolve +If the hierarchical depth buffer is enabled, the hierarchical depth buffer may contain incorrect results if the +depth buffer is written to outside of the 3D rendering operation If this occurs, the hierarchical depth buffer +must be “resolved”to avoid incorrect device behavior This is done by setting the Hierarchical Depth Buffer +Resolve Enable field in WM_STATE or 3DSTATE_WM and rendering a full render target sized rectangle +Once this is complete, the hierarchical depth buffer will contain contents such that rendering will give the +same results as it would have had the rendering been performed with the hierarchical depth buffer +disabled. +The following is required when performing a hierarchical depth buffer resolve: + +  A rectangle primitive covering the full render target must be delivered. +  Depth Test Enable must be disabled Depth Buffer Write Enable must be enabled Stencil Test + Enable and Stencil Buffer Write Enable must be disabled. + +  Pixel Shader Dispatch, Alpha Test, Pixel Shader Kill Pixel and Pixel Shader Computed Depth + must all be disabled. + + +11.5.4 Separate Stencil Buffer +The separate stencil buffer is always enabled, thus the field in 3DSTATE_DEPTH_BUFFER to explicitly +enable the separate stencil buffer has been removed Surface formats with interleaved depth and stencil +are no longer supported + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 314 + The stencil buffer has a format of S8_UINT, and shares Surface Type, Height, Width, and Depth, +Minimum Array Element, Render Target View Extent, Depth Coordinate Offset X/Y, LOD, and Depth +Buffer Object Control State fields of the depth buffer. + + +11.5.5 Depth/Stencil Buffer State + +11.5.5.1 3DSTATE_DEPTH_BUFFER + 3DSTATE_DEPTH_BUFFER + + +Source: RenderCS +Length Bias: 2 +The depth buffer surface state is delivered as a pipelined state packet. However, the state change pipelining isn’t +completely transparent (see restriction below). + Programming Notes Project +Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any combination of +3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER, +3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall (PIPE_CONTROL with +Depth Stall bit set), followed by a pipelined depth cache flush (PIPE_CONTROL with Depth Flush Bit set, +followed by another pipelined depth stall (PIPE_CONTROL with Depth Stall Bit set), unless SW can +otherwise guarantee that the pipeline from WM onwards is already flushed (e.g., via a preceding +MI_FLUSH). +3DSTATE_DEPTH_BUFFER must always be programmed along with the other Depth/Stencil state +commands(i.e. 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER, or +3DSTATE_HIER_DEPTH_BUFFER). +Driver must send a least one PIPE_CONTROL command with CS Stall and a post sync operation prior to the +group of depth commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, +3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER). +The depth buffer is always Tile-Y +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 05h 3DSTATE_DEPTH_BUFFER + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 Dword Length + Default Value: 0h Excludes Dword (0,1) + Project: All + Format: =n Total Length – 2 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 315 + 3DSTATE_DEPTH_BUFFER + + + +1 31:29 Surface Type + Project: All + This field defines the type of the surface. + Value Name Description Project + 0h SURFTYPE_1D Defines a 1-dimensional map or array of maps All + 1h SURFTYPE_2D Defines a 2-dimensional map or array of maps All + 2h SURFTYPE_3D Defines a 3-dimensional (volumetric) map All + 3h SURFTYPE_CUBE Defines a cube map All + 4h-6h Reserved All + 7h SURFTYPE_NULL Defines a null surface All + + + Programming Notes + The Surface Type of the depth buffer must be the same as the Surface Type of the render target(s) + (defined in SURFACE_STATE), unless either the depth buffer or render targets are SURFTYPE_NULL + 28 Depth Write Enable + Project: All + Format: Enable + This field enables depth writes to the depth buffer surface. Both this field and the Depth Buffer Write + Enable field in DEPTH_STENCIL_STATE must be enabled in order for depth writes to occur. + + 27 Stencil Write Enable + Project: All + Format: Enable + This field enables stencil writes to the depth buffer or stencil buffer surface, depending on where stencil + is located. Both this field and the Stencil Buffer Write Enable field in DEPTH_STENCIL_STATE must + be enabled in order for stencil writes to occur. + + 26:23 Reserved + Project: All + Format: MBZ + 22 Hierarchical Depth Buffer Enable + Project: All + Format: Enable + If enabled, indicates that a hierarchical depth buffer is defined. + Programming Notes + If this field is enabled, the Software Tiled Rendering Mode must be NORMAL.This field must be + disabled if Early Depth Test Enable is disabled. + 21 Reserved + Project: All + Format: MBZ + 20:18 Surface Format + Project: All + Specifies the format of the depth buffer. See Stencil Test Enable field in DEPTH_STENCIL_STATE + field for restrictions on the use of some of these formats. + Value Name Description Project + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 316 + 3DSTATE_DEPTH_BUFFER + + 0h Reserved Reserved All + 1h D32_FLOAT D32_FLOAT All + 2h Reserved Reserved All + 3h D24_UNORM_X8_UINT D24_UNORM_X8_UINT All + 4h Reserved Reserved All + 5h D16_UNORM D16_UNORM All + 6h-7h Reserved Reserved All + 17:0 Surface Pitch + Project: All + Format: U18-1 Pitch in Bytes + + + This field specifies the pitch of the depth buffer in (#Bytes – 1). + Value Name Description + [127, 3FFFFh] corresponding to [128B, 256KB] also restricted to a multiple of 128B + + + Programming Notes + The pitch specified must be a multiple of the tile pitch, in the range [128B, 128KB]. +2 31:0 Surface Base Address + Project: All + Format: GraphicsAddress[31:0]Depth_Buffer + This field specifies the starting Dword address of the buffer in mapped Graphics Memory. + Programming Notes + The Depth Buffer can only be mapped to Main Memory (uncached).If the surface is tiled, the base + address must conform to the Per-Surface Tiling Alignment Rules. If the buffer is linear, the surface + must be 64-byte aligned. +3 31:18 Height + Project: All + Format: U14 + + + Range: SURFTYPE_1D: must be zeroSURFTYPE_2D: height of surface – 1 (y/v dimension) + [0,16383]SURFTYPE_3D: height of surface – 1 (y/v dimension) [0,2047]SURFTYPE_CUBE: height of + surface – 1 (y/v dimension) [0, 16383] + This field specifies the height of the surface. If the surface is MIP-mapped, this field contains the height + of the base MIP level. + + + Programming Notes + The Height of the depth buffer must be the same as the Height of the render target(s) (defined in + SURFACE_STATE), unless Surface Type is SURFTYPE_1D or SURFTYPE_2D with Depth = 0 (non- + array) and LOD = 0 (non-mip mapped). + 17:4 Width + Project: All + Format: U14-1 + + + Range: SURFTYPE_1D: width of surface – 1 (x/u dimension) [0, 16383]SURFTYPE_2D: width of + surface – 1 (x/u dimension) [0, 16383]SURFTYPE_3D: width of surface – 1 (x/u dimension) + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 317 + 3DSTATE_DEPTH_BUFFER + + [0,2047]SURFTYPE_CUBE: width of surface – 1 (x/u dimension) [0, 16383] + This field specifies the width of the surface. If the surface is MIP-mapped, this field specifies the width + of the base MIP level. The width is specified in units of pixels. + + + Programming Notes + The Width specified by this field must be less than or equal to the surface pitch (specified in bytes via + the Surface Pitch field).For cube maps, Width must be set equal to Height.The Width of the depth + buffer must be the same as the Width of the render target(s) (defined in SURFACE_STATE), unless + Surface Type is SURFTYPE_1D or SURFTYPE_2D with Depth = 0 (non-array) and LOD = 0 (non-mip + mapped). + 3:0 LOD + Project: All + Format: U4 in LOD units + + + This field defines the MIP level that is currently being rendered into. + Value Name + [0, 14] + + + Programming Notes + The LOD of the depth buffer must be the same as the LOD of the render target(s) (defined in + SURFACE_STATE) +4 31:21 Depth + Project: All + Format: U11-1 + This field specifies the total number of levels for a volume texture or the number of array elements + allowed to be accessed starting at the Minimum Array Element for arrayed surfaces. If the volume + texture is MIP-mapped, this field specifies the depth of the base MIP level. + Value Name + [0, 2047] SURFTYPE_1D number of array elements – 1 + [0, 2047] SURFTYPE_2D number of array elements – 1 + [0, 2047] SURFTYPE_3D depth of surface – 1 (r/z dimension) + 0 SURFTYPE_CUBE (must be zero) + + + Programming Notes + The Depth of the depth buffer must be the same as the Depth of the render target(s) (defined in + SURFACE_STATE). + 20:10 Minimum Array Element + Project: All + Format: U11 + For 1D and 2D Surfaces: + This field indicates the minimum array element that can be accessed as part of this surface. The + delivered array index is added to this field before being used to address the surface. + For 3D Surfaces: + This field indicates the minimum ‘R’ coordinate on the LOD currently being rendered to. This field is + added to the delivered array index before it is used to address the surface. + For Other Surfaces: + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 318 + 3DSTATE_DEPTH_BUFFER + This field is ignored. + Value Name + [0, 2047] SURFTYPE_1D/2D + [0, 2047] SURFTYPE_3D + 9:4 Reserved + Project: All + Format: MBZ + 3:0 Depth Buffer Object Control State + Project: All + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for the depth buffer. + +5 31:16 Depth Coordinate Offset Y + Format: S15 in Screen Space (pixels)(3 LSBs MBZ) + + + + + Range: [-8192,8191] Bits 31:30 should be a sign extension + Specifies a signed pixel offset to be added to the RenderTarget Y coordinate in order to generate a + DepthBuffer Y coordinate. (See Depth Coordinate in Windower). + + + Programming Notes + The 3 LSBs of both offsets must be zero to ensure correct alignmentSoftware must ensure that the + resulting (sum) coordinate value is non-negative + This field must be zero when rendering to field-mode (interlaced) Color Buffers (i.e., when Surface + State’s VerticalLineStride==1). + This field can only be nonzero when rendering to surfaces of type SURFTYPE_1D and + SURFTYPE_2D with Depth = 0 (non-array) and LOD = 0 (non-mip mapped). + The offsets need to be aligned to the hashing mode set for WM in the GT_MODE register (0x7008) + bits[12:10]. + For eg if the hashing mode is set to 16x16, the Depth Coordinate Y offset needs to be aligned to the + 16x16 pixel block. + 15:0 Depth Coordinate Offset X + Format: S15 in Screen Space (pixels)(3 LSBs MBZ) + + + + + Range: [-8192,8191] Bits 15:14 should be a sign extension + Specifies a signed pixel offset to be added to the RenderTarget X coordinate in order to generate a + DepthBuffer X coordinate. (See Depth Coordinate in Windower). + + + Programming Notes + The 3 LSBs of both offsets must be zero to ensure correct alignmentSoftware must ensure that the + resulting (sum) coordinate value is non-negative. + This field must be zero when rendering to field-mode (interlaced) Color Buffers (i.e., when Surface + State’s VerticalLineStride==1). + This field can only be nonzero when rendering to surfaces of type SURFTYPE_1D and + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 319 + 3DSTATE_DEPTH_BUFFER + + SURFTYPE_2D with Depth = 0 (non-array) and LOD = 0 (non-mip mapped). + The offsets need to be aligned to the hashing mode set for WM in the GT_MODE register (0x7008) + bits[12:10]. + For eg if the hashing mode is set to 16x16, the Depth Coordinate X offset needs to be aligned to the + 16x16 pixel block. +6 31:21 Render Target View Extent + Project: All + Format: U11 + + + Range: SURFTYPE_1D/2D: same value as Depth field + Range: SURFTYPE_3D: [0, 2047] to indicate extent of [1, 2048] + For 3D Surfaces: + This field indicates the extent of the accessible ‘R’ coordinates minus 1 on the LOD currently being + rendered to. + For 1D and 2D Surfaces: + This field must be set to the same value as the Depth field. + For Other Surfaces: + This field is ignored. + 20:0 Reserved + Project: All + Format: MBZ + + + +11.5.5.2 3DSTATE_STENCIL_BUFFER + 3DSTATE_STENCIL_BUFFER + + +Source: RenderCS +Length Bias: 2 +This command sets the surface state of the separate stencil buffer, delivered as a pipelined state command. +However, the state change pipelining isn’t completely transparent (see restriction below). + Programming Notes Project +Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any combination of +3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER, +3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall (PIPE_CONTROL with +Depth Stall bit set, followed by a pipelined depth cache flush (PIPE_CONTROL with Depth Flush Bit set, +followed by another pipelined depth stall (PIPE_CONTROL with Depth Stall Bit set), unless SW can +otherwise guarantee that the pipeline from WM onwards is already flushed (e.g., via a preceding +MI_FLUSH). +3DSTATE_STENCIL_BUFFER must always be programmed in the along with the other Depth/Stencil state +commands(i.e. 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, or +3DSTATE_HIER_DEPTH_BUFFER) +Driver must send a least one PIPE_CONTROL command with CS Stall and a post sync operation prior to the +group of depth commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, +3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER). +The stencil buffer is always Tile-Y + DWord Bit Description +0 31:29 Command Type + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 320 + 3DSTATE_STENCIL_BUFFER + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 06h 3DSTATE_STENCIL_BUFFER + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 Dword Length + Project: All + Format: =n Total Length – 2 + + + + + Value Name Project + 1h Excludes Dword (0,1) [Default] +1 31 Reserved + + Format: MBZ + 30:29 Reserved + Project: All + Format: MBZ + 28:25 Stencil Buffer Object Control State + + Format: MEMORY_OBJECT_CONTROL_STATE + + + Description Project + Specifies the memory object control state for the stencil buffer. + Stencil Buffer Object Control State [3:0] + This field is not context save and restored by hardware. If this field is programmed to any + value other than zero, it must be programmed after the following commands or events: +  MI_SET_CONTEXT +  MI_WAIT_FOR_EVENT (Specifically waits on vblank or display flip) +  Render engine goes IDLE due to head point equal to tail pointer + + 24:22 Reserved + + Format: MBZ + 21:17 Reserved + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 321 + 3DSTATE_STENCIL_BUFFER + + Project: All + Format: MBZ + 16:0 Surface Pitch + Project: All + Format: U17-1 Pitch in Bytes + + + This field specifies the pitch of the stencil buffer in (#Bytes – 1). + Value Name Description + [127, 3FFFFh] corresponding to [128B, 128KB]also restricted to a multiple of 128B + + + Programming Notes + Since this surface is tiled, the pitch specified must be a multiple of the tile pitch, in the range [128B, + 128KB]. +2 31:0 Surface Base Address_low + Project: All + Format: GraphicsAddress[31:0]Stencil_Buffer + This field specifies the starting Dword address of the buffer in mapped Graphics Memory. + Programming Notes + The Stencil Buffer can only be mapped to Main Memory (uncached). + Since this surface is tiled, the base address must conform to the Per-Surface Tiling Alignment Rules. + + + +11.5.5.3 3DSTATE_HIER_DEPTH_BUFFER + 3DSTATE_HIER_DEPTH_BUFFER + + +Source: RenderCS +Length Bias: 2 +This command sets the surface state of the hierarchical depth buffer, delivered as a pipelined state command. +However, the state change pipelining isn’t completely transparent (see restriction below). + Programming Notes Project +Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any combination of +3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER, +3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall (PIPE_CONTROL with +Depth Stall bit set, followed by a pipelined depth cache flush (PIPE_CONTROL with Depth Flush Bit +set, followed by another pipelined depth stall (PIPE_CONTROL with Depth Stall Bit set), unless SW +can otherwise guarantee that the pipeline from WM onwards is already flushed (e.g., via a preceding +MI_FLUSH). +3DSTATE_HIER_DEPTH_BUFFER must always be programmed in the along with the other Depth/Stencil +state commands(i.e. 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, or +3DSTATE_STENCIL_BUFFER) +Driver must send a least one PIPE_CONTROL command with CS Stall and a post sync operation prior to the +group of depth commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, +3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER). +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 322 + 3DSTATE_HIER_DEPTH_BUFFER + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 07h 3DSTATE_HIER_DEPTH_BUFFER + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 Dword Length + Project: All + Format: =n Total Length – 2 + + + + + Value Name Project + 1h Excludes Dword (0,1) [Default] +1 31:29 Reserved + + Format: MBZ + 28:25 Hierarchical Depth Buffer Object Control State + + Format: MEMORY_OBJECT_CONTROL_STATE + + + Description Project + Specifies the memory object control state for the hierarchical depth buffer. + This field is not context save and restored by hardware. If this field is programmed to any + value other than zero, it must be programmed after the following commands or events: +  MI_SET_CONTEXT +  MI_WAIT_FOR_EVENT (Specifically waits on vblank or display flip) +  Render engine goes IDLE due to head point equal to tail pointer + + 24:17 Reserved + Project: All + Format: MBZ + 16:0 Surface Pitch + Project: All + Format: U17-1 Pitch in Bytes + + + This field specifies the pitch of the hierarchical depth buffer in (#Bytes – 1). + Value Name + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 323 + 3DSTATE_HIER_DEPTH_BUFFER + + [127, 3FFFFh] corresponding to [128B, 128KB] also restricted to a multiple of 128B + + + Programming Notes + Since this surface is tiled, the pitch specified must be a multiple of the tile pitch, in the range [128B, + 128KB]. +2 31:0 Surface Base Address [31:0] + Project: All + Format: GraphicsAddress[31:0]HierarchicalDepthBuffer + This field specifies the starting Dword address of the buffer in mapped Graphics Memory. + Programming Notes + The Hierarchical Depth Buffer can only be mapped to Main Memory (uncached). + Since this surface is tiled, the base address must conform to the Per-Surface Tiling Alignment Rules. + + + +11.5.5.4 3DSTATE_CLEAR_PARAMS + 3DSTATE_CLEAR_PARAMS + + +Source: RenderCS +Length Bias: 2 +This command defines the depth clear value delivered as a pipelined state command. However, the state change +pipelining isn’t completely transparent (see restriction below). + Programming Notes Project + Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any combination of +3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER, +3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall (PIPE_CONTROL with +Depth Stall bit set), followed by a pipelined depth cache flush (PIPE_CONTROL with Depth Flush Bit set, +followed by another pipelined depth stall (PIPE_CONTROL with Depth Stall Bit set), unless SW can +otherwise guarantee that the pipeline from WM onwards is already flushed (e.g., via a preceding +MI_FLUSH). +3DSTATE_CLEAR_PARAMS must always be programmed in the along with the other Depth/Stencil state +commands(i.e. 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER, or +3DSTATE_HIER_DEPTH_BUFFER) +Driver must send a least one PIPE_CONTROL command with CS Stall and a post sync operation prior to the +group of depth commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, +3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER). +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 0h 3DSTATE_PIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 324 + 3DSTATE_CLEAR_PARAMS + + Default Value: 04h 3DSTATE_CLEAR_PARAMS + Format: OpCode + 15:8 Reserved + Format: MBZ + 7:0 Dword Length + Default Value: 1h Excludes Dword (0,1) + Format: =n Total Length – 2 + + + +1 31:0 Depth Clear Value + + + Format: for Surface Format of depth buffer:D32_FLOAT_S8X24_UINT: IEEE_FloatD32_FLOAT: + IEEE_FloatD24_UNORM_S8_UINT: U24 UNORM in bits [23:0]D24_UNORM_X8_UINT: U24 UNORM + in bits [23:0]D16_UNORM: U16 UNORM in bits [15:0] + This field defines the clear value that will be applied to the depth buffer if the Depth Buffer Clear field + is enabled. It is valid only if Depth Buffer Clear Value Valid is set. +2 31:1 Reserved + Format: MBZ + 0 Depth Clear Value Valid + Format: Boolean + This field enables the Depth Clear Value. If clear, the depth clear value is obtained from interpolated + depth of an arbitrary pixel of the primitive rendered with Depth Buffer Clear set in WM_STATE or + 3DSTATE_WM. If set, the depth clear value is obtained from the Depth Clear Value field of this + command. + + + + +11.6 Barycentric Attribute Interpolation +Given hardware clipper and setup, some of the previous flexibility in the algorithm used to interpolate +attributes is no longer available Hardware uses barycentric parameters to aid in attribute interpolation, +and these parameters are computed in hardware per-pixel (or per-sample) and delivered in the thread +payload to the pixel shader Also delivered in the payload are a set of vertex deltas (a0, a1, and a2) per +channel of each attribute. +There are six different barycentric parameters that can be enabled for delivery in the pixel shader payload +These are enabled via the Barycentric Interpolation Mode bits in 3DSTATE_WM. +In the pixel shader kernel, the following computation is done for each attribute channel of each +pixel/sample given the corresponding attribute channel a0/a1/a2 and the pixel/sample’s b1/b2 barycentric +parameters, where A is the value of the attribute channel at that pixel/sample: +A = a0 + (a1 * b1) + (a2 * b2) + + +11.7 MCS Buffer for Render Target(s) +MCS buffer can be enabled for two purposes described below. MCS buffer can be controlled using two +mechanisms: 1) MMIO bit Cache Mode 1 (0x2124) register bit 5 and 2) RT surface state. Following table +summarizes modes of operation related to MCS buffer. + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 325 + Operation + Cache MSC + Mode Enable + MMIO Bit + (Surface + (Please State) + refer to Vol + 1c) + 1 (feature disable) X Normal mode of operation i.e. no + MSAA compression and no color + clear + 0 0 Normal mode of operation i.e. no + MSAA compression and no color + clear + 0 1 Depending on the Number of multi- + samples, either MSAA compression + OR color clear is enabled +  MSAA Compression: Multi-sample render target is bound to the pipeline and MSAA compression + feature is enabled. In this case, MCS buffer stores the information required for MSAA compression + algorithm. The size and layout of the MCS buffer is based on per-pixel RT. For 4X and 8X MSAA, + MCS buffer element is 8bpp and 32bpp respectively. Height, width and layout of MCS buffer in this + case needs must match with Render Target height, width and layout. MCS buffer is tiledY. When + MCS buffer is enabled and bound to MSRT, it is required that it is cleared prior to any rendering. A + clear value can be specified optionally in the surface state of the corresponding RT. Clear pass for + this case requires that scaled down primitive is sent down with upper left co-ordinate to coincide with + actual rectangle being cleared. For MSAA, clear rectangle’s height and width need to as show in the + following table in terms of (width,height) of the RT. + + Width of Clear + MSAA Rect Height of Clear Rect + 4X Ceil(1/8*width) Ceil(1/2*height) + 8X Ceil(1/2*width) Ceil(1/2*height) + +  Fast Color Clear: When non multi-sample render target is bond to the pipeline and MSC buffer is + enabled, MCS buffer is used as an intermediate (coarse granular) buffer per RT. Hence, MCS buffer + is used to improve render target clear. When MCS is buffer is used for color clear of non- + multisampler render target, the following restrictions apply. + +  Support is limited to tiled render targets. +  Support is for non-mip-mapped and non-array surface types only. + +  Clear is supported only on the full RT; i.e., no partial clear or overlapping clears. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 326 + The following table describes the RT alignment + + Pixels Lines + TiledY RT CL + bpp + 32 8 4 + 64 4 4 + 128 2 4 + TiledX RT CL + + bpp + 32 16 2 + 64 8 2 + 128 4 2 +  MCS buffer for non-MSRT is supported only for RT formats 32bpp, 64bpp and 128bpp. + +  Clear pass must have a clear rectangle that must follow alignment rules in terms of + pixels and lines as shown in the table below. Further, the clear-rectangle height and + width must be multiple of the following dimensions. If the height and width of the + render target being cleared do not meet these requirements, an MCS buffer can be + created such that it follows the requirement and covers the RT. + + Pixels Lines + TiledY RT + bpp + 32 128 128 + 64 64 128 + 128 32 128 + TiledX RT + + bpp + 32 256 64 + 64 128 64 + 128 64 64 + + + + In order to optimize the performance MCS buffer (when bound to 1X RT) clear similarly to + MCS buffer clear for MSRT case, clear rect is required to be scaled by the following factors in + the horizontal and vertical directions: + + Horizontal scale Vertical scale + down factor + down factor + + +MCS CL for TiledY + RCC + bpp + 32 64 64 + 64 32 64 + 128 16 64 + MCS CL for TiledX + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 327 + RCC + + bpp + 32 128 32 + 64 64 32 + 128 32 32 + + + + Following are the SW requirements for MCS buffer clear functionality: + +  At the time of Render Target creation, SW needs to create clear-buffer; i.e., MCS + buffer. +  At the clear time, clear value for that RT must be programmed and clear enable bit + must be set in the surface state of the corresponding RT. +  SW must clear the RT with setting a RT clear bit set in the PS state during the clear + pass as described in the following sub-section. +  Since only one RT is bound with a clear pass, only one RT can be cleared at a time. In + order to clear multiple RTs, multiple clear passes are required. +  Before binding the “cleared” RT to texture OR honoring a CPU lock OR submitting for + flip, SW must ensure a resolve pass. Such a resolve pass is described in the following + sub-section. + + +11.8 Render Target Fast Clear +Fast clear of the render target is performed by setting the Render Target Fast Clear Enable field in +3DSTATE_PS and rendering a rectangle The size of the rectangle is related to the size of the MCS. +The following is required when performing a render target fast clear: + +  The render target(s) is/are bound as they normally would be, with the MCS surface defined in + SURFACE_STATE. +  A rectangle primitive of the same size as the MCS surface is delivered. +  The pixel shader kernel requires no attributes, and delivers a value of 0xFFFFFFFF in all channels + of the render target write message The replicated color message should be used. + +  Depth Test Enable, Depth Buffer Write Enable, Stencil Test Enable, Stencil Buffer Write + Enable, and Alpha Test Enable must all be disabled. +  After Render target fast clear, pipe-control with color cache write-flush must be issued before + sending any DRAW commands on that render target. + + +11.9 Render Target Resolve +If the MCS is enabled on a non-multisampled render target, the render target must be resolved before +being used for other purposes (display, texture, CPU lock) The clear value from SURFACE_STATE is +written into pixels in the render target indicated as clear in the MCS. This is done by setting the Render +Target Resolve Enable field in 3DSTATE_PS and rendering a full render target sized rectangle. Once +this is complete, the render target will contain the same contents as it would have had the rendering been +performed with MCS surface disabled. In a typical usage model, the render target(s) need to be resolved +after rendering and before using it as a source for any consecutive operation. +The following is required when performing a render target resolve: + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 328 +  PIPE_CONTROL with end of pipe sync must be delivered. +  A rectangle primitive must be scaled down by the following factors with respect to render target + being resolved. +Resolve rectangle scaling for TiledY RCC + width scale down factor height scale down factor + bpp + 32 4 2 + 64 2 2 + 128 1 2 +Resolve rectangle scaling for TiledX RCC + bpp + 32 8 1 + 64 4 1 + 128 2 1 +  : The pixel shader kernel requires no attributes, but must deliver a render target write message + covering all pixels and all render targets desired to be resolved The color data in these messages is + ignored (the replicated color message is required). +  Depth Test Enable, Depth Buffer Write Enable, Stencil Test Enable, Stencil Buffer Write + Enable, and Alpha Test Enable must all be disabled. + +Note that this render target resolve procedure is not supported on multisampled render targets. +Unresolved multisampled render targets are directly supported by the sampling engine, which resolves +clear values in addition to decompressing the surface This applies to both ld2dms and sample2dms +messages. + + +11.10 Pixel Shader Thread Generation +After a group of object pixels have been rasterized, the Pixel Shader function is invoked to further +compute pixel color/depth information and cause results to be written to rendertargets and/or depth +buffers For each pixel, the Pixel Shader calculates the values of the various vertex attributes that are to +be interpolated across the object using the interpolation coefficients It then executes an API-supplied +Pixel Shader Program Instructions in this program permit the accessing of texture map data, where +Texture Samplers are employed to sample and filter texture maps (see the Shared Functions chapter) +Arithmetic operations can be performed on the texture data, input pixel information and Pixel Shader +Constants in order to compute the resultant pixel color/depth The Pixel Shader program also allows the +pixel to be discarded from further processing For pixels that are not discarded, the pixel shader must +send messages to update one or more render targets with the pixel results. + + +11.10.1 Pixel Grouping (Dispatch Size) Control +The WM unit can pass a grouping of 2 subspans (8 pixels), 4 subspans (16 pixels) or 8 subspans (32 +pixels) to a Pixel Shader thread Software should take into account the following considerations when +determining which groupings to support/enable during operation This determination involves a tradeoff of +these likely conflicting issues Note that the size of the dispatch has significant impact on +the kernel program (it is certainly not transparent to the kernel) Also note that there is no implied +spatial relationship between the subspans passed to a PS thread, other than the fact that they come from +the same object. + 1. Thread Efficiency: In general, there is some amount of overhead involved with PS thread + dispatch, and if this can be amortized over a larger number of pixels, efficiency will likely + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 329 + increase This is especially true for very short PS kernels, as may be used for desktop + composition, etc. + 2. GRF Consumption: Processing more pixels per thread will require a larger thread payload + and likely more temporary register usage, both of which translate into a requirement for a + larger GRF register allocation for the threads. If this increased GRF usage could lead to + increased use of scratch space (for spill/fill, etc.) and possibly less efficient use of the Eus (as + it would be less likely to find an EU with enough free physical GRF registers to service the + thread). + 3. Object Size: If the number of very small objects (e.g., covering 2 subspans or fewer) is + expected to comprise a significant portion of the workload, supporting the 8-pixel dispatch + mode may be advantageous Otherwise there could be a large number of 16-pixel dispatches + with only 1 or 2 valid subspans, resulting in low efficiency for those threads. + 4. Intangibles: Kernel footprint & Instruction Cache impact; Complexity; …. +The groupings of subspans that the WM unit is allowed to include in a PS thread payload is controlled by +the 32,16,8 Pixel Dispatch Enable state variables programmed in WM_STATE. Using these state +variables, the WM unit will attempt to dispatch the largest allowed grouping of subspans The following +table lists the possible combinations of these state variables. +Please note that, the valid column in table indicates which products supports the combination dispatch. +Combinations that are not listed in the table are not available on any product. +A: Valid on all products +B: Valid only on Not valid on if 4x PERPIXEL mode with pixel shader computed depth. +D: Valid on all products, except when in non-1x PERSAMPLE mode (applies to only) . +F: Valid on all products. + +Variable Pixel Dispatch + + IP for n-pixel Dispatch + IP for n-pixel (KSP offsets are in +Contiguous Contiguous Contiguous 128-bit instruction + units) + 64 Pixel 32 Pixel 32 Pixel 16 Pixel 8 Pixel Dispatch + Dispatch Dispatch Dispatch Dispatch Dispatch + Enable Enable Enable Enable Enable Valid n=64 n=32 n=32 n=16 n=8 + 0 0 0 0 1 A KSP[0] + 0 0 0 1 0 F KSP[0] + 0 0 0 1 1 D KSP[2] KSP[0] + 0 0 1 0 0 B KSP[0] + 0 0 1 1 0 E KSP[1] KSP[2] + 0 0 1 1 1 D KSP[1] KSP[2] KSP[0] + 0 1 0 0 0 C KSP[0] + 0 1 1 0 0 C KSP[1] KSP[0] + 0 1 1 1 0 D KSP[2] KSP[1] KSP[0] + 1 0 0 0 0 C KSP[0] + 1 0 1 0 0 C KSP[1] KSP[0] + 1 0 1 1 0 D KSP[2] KSP[1] KSP[0] + 1 1 0 0 0 C KSP[1] KSP[0] + 1 1 1 0 0 C KSP[2] KSP[1] KSP[0] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 330 + : + Each of the four KSP values is separately specified (three for ). In addition, each kernel has a separately- +specified GRF register count, whereas on , all kernels share the same GRF register count field, with the +one with the maximum register count required applying to all + + +Depending on the subspan grouping selected, the WM unit will modify the starting PS Instruction Pointer +(derived from the Kernel Start Pointer in WM_STATE) as a means to inform the PS kernel of the number +of subspans included in the payload. The modified IP is a function of the enabled modes and the dispatch +size, as shown in the table below. +The driver must ensure that the PS kernel begins with a corresponding jump table to properly handle the +number of subspans dispatched. The WM unit will “OR” in the two lsbs of the Kernel Pointer (bits 5:4) to +create an instruction level address (note that the pointer from WM_STATE is 64 byte aligned which +ierarchica to four instructions). +If only one dispatch mode is enabled, the Jitter should not include any jump table entries at the beginning +of the PS kernel If multiple dispatch modes are enabled, a two entry jump table should always be +inserted, regardless of which modes are enabled (jump table entry for 8 pixel dispatch, followed by jump +table entry for 32 pixel dispatch). +Note that for a 32 pixel dispatch, the Windower will ierarch the Dispatch GRF Start Register for URB +Data state by 2 to account for the extra payload data required. The Pixel Shader kernel needs to +comprehend this modification for the 32 pixel kernel code. +if (32PixelDispatchEnable && n>7) +Dispatch 32 Pixels +else if (16PixelDispatchEnable && (n>2 || !8PixelDispatchEnable)) +Dispatch 16 Pixels +else +Dispatch 8 Pixels + +11.10.1.1 Contiguous Dispatch Modes +There are three cases to consider depending on which dispatch modes are enabled based on the legal +combinations in the table above: +Only normal dispatch modes are enabled. This is the normal operating mode in which all features are +supported. +Only contiguous dispatch modes are enabled. In this case, software must ensure that the fast +composite restrictions are met. +Both normal and contiguous dispatch modes are enabled In this case, a combination of software and +the setup kernel must check all of the restrictions required by the contiguous dispatch pixel shader code +The result of the check in the setup kernel is indicated in the message descriptor of the URB write +message The windower then chooses a dispatch mode from either the normal category or the contiguous +category depending on whether the restriction check fails or passes, respectively. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 331 + If both the 32- and 64-pixel contiguous dispatch modes are enabled together, the windower will choose +which one to use based on whether at least one pixel from the upper and lower 8x4 halves of the 8x8 +block is active If one half has no pixel active, the half that does have pixels active will be dispatched as a +32-pixel thread. +The following logic describes how the windower chooses the dispatch mode based on which modes are +enabled: +d32 = normal 32-pixel dispatch mode enabled +d16 = normal 16-pixel dispatch mode enabled +d8 = normal 8-pixel dispatch mode enabled +c64 = contiguous 64-pixel dispatch mode enabled +c32 = contiguous 32-pixel dispatch mode enabled +ContiguousSelect = (c64 || c32) && + [!(d32 || d16 || d8) || RestrictionCheckPass] +For ContiguousSelect true: + +contiguous area available first priority second priority + + both superspan halves c64 c32 + + one superspan half c32 c64 + +For ContiguousSelect false: + + subspans available first priority second priority third priority + + s >= 4 d32 d16 d8 + + 4 > s >= 2 d16 d8 d32 + + 2 > s >= 1 d8 d16 d32 + + +11.10.2 Multisampling Effects on Pixel Shader Dispatch +The pixel shader payloads are defined in terms of subspans and pixels The slots in the pixel shader +thread previously mapped 1:1 with pixels With multisampling, a slot could contain a pixel or may just +contain a single sample, depending on the mode Payload definitions now refer to “slot” to make the +definition independent of multisampling mode. + +11.10.2.1 MSDISPMODE_PERPIXEL Thread Dispatch +In PERPIXEL mode, the pixel shader kernel still works on 2/4/8 separate subspans, depending on +dispatch mode. The fact that rasterization and the depth/stencil tests are being performed on a per- +sample (not per-pixel) basis is transparent to the pixel shader kernel. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 332 + 11.10.2.2 MSDISPMODE_PERSAMPLE Thread Dispatch +In PERSAMPLE mode, the pixel shader needs to operate on a sample vs. pixel basis (although this +collapses in NUMSAMPLES_1 mode) Instead of processing strictly different subspans in parallel , +the PS kernel processes different sample indices of one or more subspans in parallel For +example, a SIMD16 dispatch in PERSAMPLE/NUMSAMPLES_4 mode would operate on a single +subspan, with the usual “4 Subspan0 pixel slots” used for the “4 Sample0 locations of the (single) +subspan” Subspan1 slots would be used for the Sample1 locations, and so on This layout allows the pixel +shader to compute derivatives/LOD based on deltas between corresponding sample locations in the +subspan in the same fashion as LEGACY pixel shader execution, and as required by DX10.1. +Depending on the dispatch mode (8/16/32 pixels) and multisampling mode (1X/4X), there are different +mappings of subspans/samples onto dispatches and slots-within-dispatch In some cases, more than one +subspan may be included in a dispatch, while in other cases multiple dispatches are be required to +process all samples for a single subspan In the latter case, the StartingSamplePairIndex value is +included in the payload header so the Render Target Write message will access the correct samples with +each message. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 333 + PERSAMPLE SIMD16 4X Dispatch + + + + + PERSAMPLE SIMD8 4X Dispatch +The following table provides the complete dispatch/slot mappings for all the MS/Dispatch combinations. + + Dispatch Size Num Samples Slot Mapping + (SSPI = Starting Sample Pair Index) + + SIMD32 1X Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[1].Pixel[3:0].Sample[0] + Slot[11:8] = Subspan[2].Pixel[3:0].Sample[0] + Slot[15:12] = Subspan[3].Pixel[3:0].Sample[0] + Slot[19:16] = Subspan[4].Pixel[3:0].Sample[0] + Slot[23:20] = Subspan[5].Pixel[3:0].Sample[0] + Slot[27:24] = Subspan[6].Pixel[3:0].Sample[0] + Slot[31:28] = Subspan[7].Pixel[3:0].Sample[0] + + 2X Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[1] + Slot[11:8] = Subspan[1].Pixel[3:0].Sample[0] + Slot[15:12] = Subspan[1].Pixel[3:0].Sample[1] + Slot[19:16] = Subspan[2].Pixel[3:0].Sample[0] + Slot[23:20] = Subspan[2].Pixel[3:0].Sample[1] + Slot[27:24] = Subspan[3].Pixel[3:0].Sample[0] + Slot[31:28] = Subspan[3].Pixel[3:0].Sample[1] + + 4X Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 334 + Dispatch Size Num Samples Slot Mapping + (SSPI = Starting Sample Pair Index) + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[1] + Slot[11:8] = Subspan[0].Pixel[3:0].Sample[2] + Slot[15:12] = Subspan[0].Pixel[3:0].Sample[3] + Slot[19:16] = Subspan[1].Pixel[3:0].Sample[0] + Slot[23:20] = Subspan[1].Pixel[3:0].Sample[1] + Slot[27:24] = Subspan[1].Pixel[3:0].Sample[2] + Slot[31:28] = Subspan[1].Pixel[3:0].Sample[3] + + 8X Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[1] + Slot[11:8] = Subspan[0].Pixel[3:0].Sample[2] + Slot[15:12] = Subspan[0].Pixel[3:0].Sample[3] + Slot[19:16] = Subspan[0].Pixel[3:0].Sample[4] + Slot[23:20] = Subspan[0].Pixel[3:0].Sample[5] + Slot[27:24] = Subspan[0].Pixel[3:0].Sample[6] + Slot[31:28] = Subspan[0].Pixel[3:0].Sample[7] + + SIMD16 1X Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[1].Pixel[3:0].Sample[0] + Slot[11:8] = Subspan[2].Pixel[3:0].Sample[0] + Slot[15:12] = Subspan[3].Pixel[3:0].Sample[0] + + 2X Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[1] + Slot[11:8] = Subspan[1].Pixel[3:0].Sample[0] + Slot[15:12] = Subspan[1].Pixel[3:0].Sample[1] + + 4X Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[1] + Slot[11:8] = Subspan[1].Pixel[3:0].Sample[0] + Slot[15:12] = Subspan[1].Pixel[3:0].Sample[1] + + 8X Dispatch[i]: (i=0, 2) + SSPI = i + Slot[3:0] = Subspan[0].Pixel[3:0].Sample[SSPI*2+0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[SSPI*2+1] + Slot[11:8] = Subspan[0].Pixel[3:0].Sample[SSPI*2+2] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 335 + Dispatch Size Num Samples Slot Mapping + (SSPI = Starting Sample Pair Index) + Slot[15:12] = Subspan[0].Pixel[3:0].Sample[SSPI*2+3] + + 16X Dispatch[i]: (i=0, 2, 4, 6) + SSPI = i + Slot[3:0] = Subspan[0].Pixel[3:0].Sample[SSPI*2+0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[SSPI*2+1] + Slot[11:8] = Subspan[0].Pixel[3:0].Sample[SSPI*2+2] + Slot[15:12] = Subspan[0].Pixel[3:0].Sample[SSPI*2+3] + + SIMD8 1X Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[1].Pixel[3:0].Sample[0] + + 2X Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[1] + + 4X Dispatch[i]: (i=0..1) + SSPI = i + Slot[3:0] = Subspan[0].Pixel[3:0].Sample[SSPI*2+0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[SSPI*2+1] + + 8X Dispatch[i]: (i=0, 1, 2, 3) + SSPI = i + Slot[3:0] = Subspan[0].Pixel[3:0].Sample[SSPI*2+0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[SSPI*2+1] + + 16X Dispatch[i]: (i=0, 1, 2, 3, 4, 5, 6, 7) + SSPI = i + Slot[3:0] = Subspan[0].Pixel[3:0].Sample[SSPI*2+0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[SSPI*2+1] + + + +11.10.3 PS Thread Payload for Normal Dispatch +The following table lists all possible contents included in a PS thread payload, in the order they are +provided Certain portions of the payload are optional, in which case the corresponding phase is skipped. +This payload does not apply to the contiguous dispatch modes on The payload for these modes are +documented in the section titled PS Thread Payload for Contiguous Dispatch. + +11.10.3.1 PS Thread Payload for Normal Dispatch +The following payload (UNRESOLVED CROSS REFERENCE, PS Thread Payload for Normal Dispatch) +applies to All registers are numbered starting at 0, but many registers are skipped depending on + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 336 + configuration This causes all registers below to be renumbered to fill in the skipped locations The only +case where actual registers may be skipped is immediately before the constant data and again before the +setup data. + +PS Thread Payload for Normal Dispatch + + Dword + Bit Description + R0.7 31 + Reserved + 30:24 + 23:0 + Primitive Thread ID: This field contains the primitive thread count passed to the Windower + from the Strips Fans Unit. + + Format: Reserved for HW Implementation Use. + R0.6 Reserved + 31:24 + 23:0 + Thread ID: This field contains the thread count which is incremented by the Windower for every + thread that is dispatched. + + Format: Reserved for HW Implementation Use. + R0.5 31:10 + Scratch Space Pointer: Specifies the 1K-byte aligned pointer to the scratch space available + for this PS thread This is specified as an offset to the General State Base Address. + + Format = GeneralStateOffset[31:10] + Reserved + 9:8 + + 7:0 + FFTID: This ID is assigned by the WM unit and is a identifier for the thread It is used to free up + resources used by the thread upon thread completion. + + Format: Reserved for HW Implementation Use. + R0.4 31:5 + Binding Table Pointer: Specifies the 32-byte aligned pointer to the Binding Table It is + specified as an offset from the Surface State Base Address. + + Format = SurfaceStateOffset[31:5] + Reserved + 4:0 + + R0.3 31:5 + Sampler State Pointer: Specifies the 32-byte aligned pointer to the Sampler State table It is + specified as an offset from the Dynamic State Base Address. + + Format = DynamicStateOffset[31:5] + Reserved + 4 + 3:0 + Per Thread Scratch Space: Specifies the amount of scratch space allowed to be used by this + thread. + Programming Notes: +  This amount is available to the kernel for information only It will be passed verbatim + (if not altered by the kernel) to the Data Port in any scratch space access + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 337 + Dword + Bit Description + messages, but the Data Port will ignore it + + Format = U4 + + Range = [0,11] indicating [1k bytes, 2M bytes] in powers of two + R0.2 Reserved : delivered as zeros (reserved for message header fields) + 31:0 + R0.1 31:6 + Color Calculator State Pointer:Specifies the 64-byte aligned pointer to the Color Calculator + state (COLOR_CALC_STATE structure in memory) It is specified as an offset from the + Dynamic State Base Address This value is eventually passed to the ColorCalc function in the + DataPort and is used to fetch the corresponding CC_STATE data. + + Format = DynamicStateOffset[31:5] + Reserved + 5:0 + R0.0 Reserved + 31 + 30:27 + Viewport Index Specifies the index of the viewport currently being used. + + Format = U4 + + Range = [0,15] + 26:16 + Render Target Array Index:Specifies the array index to be used for the following surface + types: + + SURFTYPE_1D: specifies the array index Range = [0,2047] + + SURFTYPE_2D: specifies the array index Range = [0,2047] + + SURFTYPE_3D: specifies the “r” coordinate Range = [0,2047] + + SURFTYPE_CUBE: specifies the face identifier Range = [0,5] + face Render Target Array Index + +x 0 + -x 1 + +y 2 + -y 3 + +z 4 + -z 5 + + Format = U11 + + 15 + Front/Back Facing Polygon: Determines whether the polygon is front or back facing Used by + the render cache to determine which stencil test state to use. + + 0: Front Facing + + 1: Back Facing + Reserved + 14 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 338 + Dword + Bit Description + 13 + Source Depth to Render Target: Indicates that source depth will be sent to the render target + 12 + oMask to Render Target: Indicates that oMask will be sent to the render target + Reserved + 11:9 + + 8 Reserved for expansion of Starting Sample Pair Index + 7:6 + Starting Sample Pair Index: indicates the index of the first sample pair of the dispatch + + Format = U2 + + Range = [0,3] + Reserved + 5 + 4:0 + Primitive Topology Type: This field identifies the Primitive Topology Type associated with the + primitive spawning this object The WM unit does not modify this value (e.g., objects within + POINTLIST topologies see POINTLIST). + + Format: (See 3DPRIMITIVE command in 3D Pipeline) + R1.7 31:16 + Pixel/Sample Mask (SubSpan[3:0]) : Indicates which pixels within the four subspans are lit If + 32 pixel dispatch is enabled, this field contains the pixel mask for the first four subspans. + + Note: This is not a duplicate of the Dispatch Mask that is delivered to the thread The dispatch + mask has all pixels within a subspan as active if any of them are lit to enable LOD calculations + to occur correctly. + + This field must not be modified by the Pixel Shader kernel. + 15:0 + Pixel/Sample Mask Copy (SubSpan[3:0]) : This is a duplicate copy of the pixel mask This + copy can be modified as the pixel shader thread executes in order to turn off pixels based on + kill instructions. + R1.6 Reserved + 31:0 + R1.5 31:16 + Y3: Y coordinate (screen space) for upper-left pixel of subspan 3 (slot 12) + + Format = U16 + 15:0 + X3: X coordinate (screen space) for upper-left pixel of subspan 3 (slot 12) + + Format = U16 + R1.4 31:16 + Y2 : Y coordinate (screen space) for upper-left pixel of subspan 2 (slot 8) + + Format = U16 + 15:0 + X2 : X coordinate (screen space) for upper-left pixel of subspan 2 (slot 8) + + Format = U16 + R1.3 31:16 + Y1 : Y coordinate (screen space) for upper-left pixel of subspan 1 (slot 4) + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 339 + Dword + Bit Description + Format = U16 + 15:0 + X1 : X coordinate (screen space) for upper-left pixel of subspan 1 (slot 4) + + Format = U16 + R1.2 31:16 + Y0 : Y coordinate (screen space) for upper-left pixel of subspan 0 (slot 0) + + Format = U16 + 15:0 + X0 : X coordinate (screen space) for upper-left pixel of subspan 0 (slot 0) + + Format = U16 + R1.1 Reserved + 31:0 + + R1.0 Reserved + 31:16 + + 15:12 Slot 3 SampleID + + Format = U4 + + 1X MSAA range: [0] + + 2X MSAA range [0,1] + + 4X MSAA range [0..3] + + 8X MSAA range [0..7] + + 16X MSAA range [0..15] + 11:8 Slot 2 SampleID + + Format = U4 + + 1X MSAA range: [0] + + 2X MSAA range [0,1] + + 4X MSAA range [0..3] + + 8X MSAA range [0..7] + + 16X MSAA range [0..15] + 7:4 Slot 1 SampleID + + Format = U4 + + 1X MSAA range: [0] + + 2X MSAA range [0,1] + + 4X MSAA range [0..3] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 340 + Dword + Bit Description + 8X MSAA range [0..7] + + 16X MSAA range [0..15] + 3:0 Slot 0 SampleID + + Format = U4 + + 1X MSAA range: [0] + + 2X MSAA range [0,1] + + 4X MSAA range [0..3] + + 8X MSAA range [0..7] + + 16X MSAA range [0..15] + + R2: delivered only if this is a 32-pixel dispatch. + R2.7 31:16 + Pixel/Sample Mask (SubSpan[7:4]) : Indicates which pixels within the upper four subspans + are lit This field is valid only when the 32 pixel dispatch state is enabled This field must not be + modified by the pixel shader thread. + + Note: This is not a duplicate of the dispatch mask that is delivered to the thread The dispatch + mask has all pixels within a subspan as active if any of them are lit to enable LOD calculations + to occur correctly. + + This field must not be modified by the Pixel Shader kernel. + 15:0 + Pixel/Sample Mask Copy (SubSpan[7:4]) : This is a duplicate copy of pixel mask for the + upper 16 pixels This copy will be modified as the pixel shader thread executes to turn off pixels + based on kill instructions. + R2.6 Reserved + 31:0 + R2.5 31:16 + Y7: Y coordinate (screen space) for upper-left pixel of subspan 7 (slot 28) + + Format = U16 + 15:0 + X7: X coordinate (screen space) for upper-left pixel of subspan 7 (slot 28) + + Format = U16 + R2.4 31:16 Y6 + 15:0 X6 + R2.3 31:16 Y5 + 15:0 X5 + R2.2 31:16 Y4 + 15:0 X4 + R2.1 Reserved + 31:0 + R2.0 Reserved + 31:15 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 341 + Dword + Bit Description + 15:12 Slot 7 SampleID + + Format = U4 + + 1X MSAA range: [0] + + 2X MSAA range [0,1] + + 4X MSAA range [0..3] + + 8X MSAA range [0..7] + + 16X MSAA range [0..15] + 11:8 Slot 6 SampleID + + Format = U4 + + 1X MSAA range: [0] + + 2X MSAA range [0,1] + + 4X MSAA range [0..3] + + 8X MSAA range [0..7] + + 16X MSAA range [0..15] + 7:4 Slot 5 SampleID + + Format = U4 + + 1X MSAA range: [0] + + 2X MSAA range [0,1] + + 4X MSAA range [0..3] + + 8X MSAA range [0..7] + + 16X MSAA range [0..15] + 3:0 Slot 4 SampleID + + Format = U4 + + 1X MSAA range: [0] + + 2X MSAA range [0,1] + + 4X MSAA range [0..3] + + 8X MSAA range [0..7] + + 16X MSAA range [0..15] + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 342 + Dword + Bit Description + R3-R26: delivered only if the corresponding Barycentric Interpolation Mode bit is set + Register phases containing Slot 8-15 data are not delivered in 8-pixel dispatch mode. + R3.7 31:0 + Perspective Pixel Location Barycentric[1] for Slot 7 + + This and the next register phase is only included if the corresponding enable bit in Barycentric + Interpolation Mode is set. + + Format = IEEE_Float + R3.6 31:0 Perspective Pixel Location Barycentric[1] for Slot 6 + R3.5 31:0 Perspective Pixel Location Barycentric[1] for Slot 5 + R3.4 31:0 Perspective Pixel Location Barycentric[1] for Slot 4 + R3.3 31:0 Perspective Pixel Location Barycentric[1] for Slot 3 + R3.2 31:0 Perspective Pixel Location Barycentric[1] for Slot 2 + R3.1 31:0 Perspective Pixel Location Barycentric[1] for Slot 1 + R3.0 31:0 Perspective Pixel Location Barycentric[1] for Slot 0 + R4 Perspective Pixel Location Barycentric[2] for Slots 7:0 + R5.7 31:0 Perspective Pixel Location Barycentric[1] for Slot 15 + R5.6 31:0 Perspective Pixel Location Barycentric[1] for Slot 14 + R5.5 31:0 Perspective Pixel Location Barycentric[1] for Slot 13 + R5.4 31:0 Perspective Pixel Location Barycentric[1] for Slot 12 + R5.3 31:0 Perspective Pixel Location Barycentric[1] for Slot 11 + R5.2 31:0 Perspective Pixel Location Barycentric[1] for Slot 10 + R5.1 31:0 Perspective Pixel Location Barycentric[1] for Slot 9 + R5.0 31:0 Perspective Pixel Location Barycentric[1] for Slot 8 + R6 Perspective Pixel Location Barycentric[2] for Slots 15:8 + R7:10 Perspective Centroid Barycentric + R11:14 Perspective Sample Barycentric + R15:18 Linear Pixel Location Barycentric + R19:22 Linear Centroid Barycentric + R23:26 Linear Sample Barycentric + + R27: delivered only if Pixel Shader Uses Source Depth is set. + R27.7 31:0 + Interpolated Depth for Slot 7 + + Format = IEEE_Float + + This and the next register phase is only included if Pixel Shader Uses Source Depth + (WM_STATE) is set. + R27.6 31:0 Interpolated Depth for Slot 6 + R27.5 31:0 Interpolated Depth for Slot 5 + R27.4 31:0 Interpolated Depth for Slot 4 + R27.3 31:0 Interpolated Depth for Slot 3 + R27.2 31:0 Interpolated Depth for Slot 2 + R27.1 31:0 Interpolated Depth for Slot 1 + R27.0 31:0 Interpolated Depth for Slot 0 + + R28: delivered only if Pixel Shader Uses Source Depth is set and this is not an 8-pixel + dispatch. + R28.7 31:0 Interpolated Depth for Slot 15 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 343 + Dword + Bit Description + R28.6 31:0 Interpolated Depth for Slot 14 + R28.5 31:0 Interpolated Depth for Slot 13 + R28.4 31:0 Interpolated Depth for Slot 12 + R28.3 31:0 Interpolated Depth for Slot 11 + R28.2 31:0 Interpolated Depth for Slot 10 + R28.1 31:0 Interpolated Depth for Slot 9 + R28.0 31:0 Interpolated Depth for Slot 8 + + R29: delivered only if Pixel Shader Uses Source W is set. + R29.7 31:0 + Interpolated W for Slot 7 + + Format = IEEE_Float + + This and the next register phase is only included if Pixel Shader Uses Source W + (WM_STATE) is set + R29.6 31:0 Interpolated W for Slot 6 + R29.5 31:0 Interpolated W for Slot 5 + R29.4 31:0 Interpolated W for Slot 4 + R29.3 31:0 Interpolated W for Slot 3 + R29.2 31:0 Interpolated W for Slot 2 + R29.1 31:0 Interpolated W for Slot 1 + R29.0 31:0 Interpolated W for Slot 0 + + R30: delivered only if Pixel Shader Uses Source W is set and this is not an 8-pixel dispatch. + R30.7 31:0 Interpolated W for Slot 15 + R30.6 31:0 Interpolated W for Slot 14 + R30.5 31:0 Interpolated W for Slot 13 + R30.4 31:0 Interpolated W for Slot 12 + R30.3 31:0 Interpolated W for Slot 11 + R30.2 31:0 Interpolated W for Slot 10 + R30.1 31:0 Interpolated W for Slot 9 + R30.0 31:0 Interpolated W for Slot 8 + + R31: delivered only if Position XY Offset Select is either POSOFFSET_CENTROID or + POSOFFSET_SAMPLE + R31.7 31:24 + Position Offset Y for Slot 15 + + This field contains either the CENTROID or SAMPLE position offset for Y, depending on the + state of Position XY Offset Select. + + Format = U4.4 + + Range = [0.0,1.0) + 23:16 + Position Offset X for Slot 15 + + This field contains either the CENTROID or SAMPLE position offset for X, depending on the + state of Position XY Offset Select. + + Format = U4.4 + + Range = [0.0,1.0) + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 344 + Dword + Bit Description + 15:8 Position Offset Y for Slot 14 + 7:0 Position Offset X for Slot 14 + R31.6 31:24 Position Offset Y for Slot 13 + 23:16 Position Offset X for Slot 13 + 15:8 Position Offset Y for Slot 12 + 7:0 Position Offset X for Slot 12 + R31.5:4 Position Offset X/Y for Slot[11:8] + R31.3:2 Position Offset X/Y for Slot[7:4] + R31.1:0 Position Offset X/Y for Slot[3:0] + + R32: delivered only if Pixel Shader Uses Input Coverage Mask is set. + R32.7 31:0 + Input Coverage Mask for Slot 7 + + Format = U32 + + This and the next register phase is only included if Pixel Shader Uses Input Coverage Mask + (3DSTATE_PS) is set. + R32.6 31:0 Input Coverage Mask for Slot 6 + R32.5 31:0 Input Coverage Mask for Slot 5 + R32.4 31:0 Input Coverage Mask for Slot 4 + R32.3 31:0 Input Coverage Mask for Slot 3 + R32.2 31:0 Input Coverage Mask for Slot 2 + R32.1 31:0 Input Coverage Mask for Slot 1 + R32.0 31:0 Input Coverage Mask for Slot 0 + + R33: delivered only if Pixel Shader Uses Input Coverage Mask is set and this is not an 8- + pixel dispatch. + R33.7 31:0 Input Coverage Mask for Slot 15 + R33.6 31:0 Input Coverage Mask for Slot 14 + R33.5 31:0 Input Coverage Mask for Slot 13 + R33.4 31:0 Input Coverage Mask for Slot 12 + R33.3 31:0 Input Coverage Mask for Slot 11 + R33.2 31:0 Input Coverage Mask for Slot 10 + R33.1 31:0 Input Coverage Mask for Slot 9 + R33.0 31:0 Input Coverage Mask for Slot 8 + + R34-R57: delivered only if the corresponding Barycentric Interpolation Mode bit is set and + this is a 32-pixel dispatch. + R34.7 31:0 + Perspective Pixel Location Barycentric[1] for Slot 23 + + This and the next register phase is only included if the corresponding enable bit in Barycentric + Interpolation Mode is set. + + Format = IEEE_Float + R34.6 31:0 Perspective Pixel Location Barycentric[1] for Slot 22 + R34.5 31:0 Perspective Pixel Location Barycentric[1] for Slot 21 + R34.4 31:0 Perspective Pixel Location Barycentric[1] for Slot 20 + R34.3 31:0 Perspective Pixel Location Barycentric[1] for Slot 19 + R34.2 31:0 Perspective Pixel Location Barycentric[1] for Slot 18 + R34.1 31:0 Perspective Pixel Location Barycentric[1] for Slot 17 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 345 + Dword + Bit Description + R34.0 31:0 Perspective Pixel Location Barycentric[1] for Slot 16 + R35 Perspective Pixel Location Barycentric[2] for Slots 23:16 + R36.7 31:0 Perspective Pixel Location Barycentric[1] for Slot 31 + R36.6 31:0 Perspective Pixel Location Barycentric[1] for Slot 30 + R36.5 31:0 Perspective Pixel Location Barycentric[1] for Slot 29 + R36.4 31:0 Perspective Pixel Location Barycentric[1] for Slot 28 + R36.3 31:0 Perspective Pixel Location Barycentric[1] for Slot 27 + R36.2 31:0 Perspective Pixel Location Barycentric[1] for Slot 26 + R36.1 31:0 Perspective Pixel Location Barycentric[1] for Slot 25 + R36.0 31:0 Perspective Pixel Location Barycentric[1] for Slot 24 + R37 Perspective Pixel Location Barycentric[2] for Slots 31:24 + R38:41 Perspective Centroid Barycentric + R42:45 Perspective Sample Barycentric + R46:49 Linear Pixel Location Barycentric + R50:53 Linear Centroid Barycentric + R54:57 Linear Sample Barycentric + + R58-R59: delivered only if Pixel Shader Uses Source Depth is set and this is a 32-pixel + dispatch. + R58.7 31:0 + Interpolated Depth for Slot 23 + + Format = IEEE_Float + + This and the next register phase is only included if Pixel Shader Uses Source Depth + (WM_STATE) bit is set. + R58.6 31:0 Interpolated Depth for Slot 22 + R58.5 31:0 Interpolated Depth for Slot 21 + R58.4 31:0 Interpolated Depth for Slot 20 + R58.3 31:0 Interpolated Depth for Slot 19 + R58.2 31:0 Interpolated Depth for Slot 18 + R58.1 31:0 Interpolated Depth for Slot 17 + R58.0 31:0 Interpolated Depth for Slot 16 + R59.7 31:0 Interpolated Depth for Slot 31 + R59.6 31:0 Interpolated Depth for Slot 30 + R59.5 31:0 Interpolated Depth for Slot 29 + R59.4 31:0 Interpolated Depth for Slot 28 + R59.3 31:0 Interpolated Depth for Slot 27 + R59.2 31:0 Interpolated Depth for Slot 26 + R59.1 31:0 Interpolated Depth for Slot 25 + R59.0 31:0 Interpolated Depth for Slot 24 + + R60-R61: delivered only if Pixel Shader Uses Source W is set and this is a 32-pixel dispatch. + R60.7 31:0 + Interpolated W for Slot 23 + + Format = IEEE_Float + + This and the next register phase is only included if Pixel Shader Uses Source W + (WM_STATE) bit is set. + R60.6 31:0 Interpolated W for Slot 22 + R60.5 31:0 Interpolated W for Slot 21 + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 346 + Dword + Bit Description + R60.4 31:0 Interpolated W for Slot 20 + R60.3 31:0 Interpolated W for Slot 19 + R60.2 31:0 Interpolated W for Slot 18 + R60.1 31:0 Interpolated W for Slot 17 + R60.0 31:0 Interpolated W for Slot 16 + R61.7 31:0 Interpolated W for Slot 31 + R61.6 31:0 Interpolated W for Slot 30 + R61.5 31:0 Interpolated W for Slot 29 + R61.4 31:0 Interpolated W for Slot 28 + R61.3 31:0 Interpolated W for Slot 27 + R61.2 31:0 Interpolated W for Slot 26 + R61.1 31:0 Interpolated W for Slot 25 + R61.0 31:0 Interpolated W for Slot 24 + + R62: delivered only if Position XY Offset Select is either POSOFFSET_CENTROID or + POSOFFSET_SAMPLE and this is a 32-pixel dispatch. + R62.7 31:24 + Position Offset Y for Slot 31 + + This field contains either the CENTROID or SAMPLE position offset for Y, depending on the + state of Position XY Offset Select. + + Format = U4.4 + + Range = [0.0,1.0) + 23:16 + Position Offset X for Slot 31 + + This field contains either the CENTROID or SAMPLE position offset for X, depending on the + state of Position XY Offset Select. + + Format = U4.4 + + Range = [0.0,1.0) + 15:8 Position Offset Y for Slot 30 + 7:0 Position Offset X for Slot 30 + R62.6 31:24 Position Offset Y for Slot 29 + 23:16 Position Offset X for Slot 29 + 15:8 Position Offset Y for Slot 28 + 7:0 Position Offset X for Slot 28 + R62.5:4 Position Offset X/Y for Slot[27:24] + R62.3:2 Position Offset X/Y for Slot[23:20] + R62.1:0 Position Offset X/Y for Slot[19:16] + + R63-R64: delivered only if Pixel Shader Uses Input Coverage Mask is set and this is a 32- + pixel dispatch. + R63.7 31:0 + Input Coverage Mask for Slot 23 + + Format = U32 + + This and the next register phase is only included if Pixel Shader Uses Input Coverage Mask + (3DSTATE_PS) is set. + R63.6 31:0 Input Coverage Mask for Slot 22 + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 347 + Dword + Bit Description + R63.5 31:0 Input Coverage Mask for Slot 21 + R63.4 31:0 Input Coverage Mask for Slot 20 + R63.3 31:0 Input Coverage Mask for Slot 19 + R63.2 31:0 Input Coverage Mask for Slot 18 + R63.1 31:0 Input Coverage Mask for Slot 17 + R63.0 31:0 Input Coverage Mask for Slot 16 + R64.7 31:0 Input Coverage Mask for Slot 31 + R64.6 31:0 Input Coverage Mask for Slot 30 + R64.5 31:0 Input Coverage Mask for Slot 29 + R64.4 31:0 Input Coverage Mask for Slot 28 + R64.3 31:0 Input Coverage Mask for Slot 27 + R64.2 31:0 Input Coverage Mask for Slot 26 + R64.1 31:0 Input Coverage Mask for Slot 25 + R64.0 31:0 Input Coverage Mask for Slot 24 + + Optional Padding before the Start of Constant/Setup Data + + The locations between the end of the Optional Payload Header and the location programmed + via Dispatch GRF Start Register for Constant/Setup Data are considered “padding” and + Reserved (see below) + optional, Reserved + 31:0 +multiple of 8 + DWs + + The Dispatch GRF Start Register for Constant/Setup Data state variable in 3DSTATE_WM + is used to define the starting location of the constant and setup data within the PS thread + payload This control is provided to allow this data to be located at a fixed location within thread + payloads, regardless of the amount of data in the Optional Payload Header This permits the + kernel to use direct GRF addressing to access the constant/setup data, regardless of the + optional parameters being passed (as these are determined on-the-fly by the WM unit) + + Constant Data (optional) : + + Some amount of constant data (possible none) can be extracted from the push constant buffer + (PCB) and passed to the thread following the R0 Header The amount of data provided is + defined by the sum of the read lengths in the last 3DSTATE_CONSTANT_PS command (taking + the buffer enables into account). + + The Constant Data arrives in a non-interleaved format. + 31:0 + Optional, Constant Data + multiple of 8 + DWs + + + Setup Data (Attribute Vertex Deltas) + + Output data from the SF stage is delivered in the PS thread payload The amount of data is + determined by the Number of Output Attributes field Each register contains two channels of + one attribute Thus, the total number of registers sent is equal to 2 * Number of Output + Attributes. + Rp.7 31:0 + a0[0].y – a0 vertex delta for Attribute0.y + + Format = IEEE_Float + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 348 + Dword + Bit Description + Rp.6 Reserved + 31:0 + Rp.5 31:0 + a2[0].y – a2 vertex delta for Attribute0.y + + Format = IEEE_Float + Rp.4 31:0 + a1[0].y – a1 vertex delta for Attribute0.y + + Format = IEEE_Float + Rp.3 31:0 + a0[0].x – a0 vertex delta for Attribute0.x + Rp.2 Reserved + 31:0 + Rp.1 31:0 + a2[0].x – a2 vertex delta for Attribute0.x + Rp.0 31:0 + a1[0].x – a1 vertex delta for Attribute0.x + R(p+1).7 31:0 + a0[0].w – a0 vertex delta for Attribute0.w + R(p+1).6 Reserved + 31:0 + R(p+1).5 31:0 + a2[0].w – a2 vertex delta for Attribute0.w + R(p+1).4 31:0 + a1[0].w – a1 vertex delta for Attribute0.w + R(p+1).3 31:0 + a0[0].z – a0 vertex delta for Attribute0.z + R(p+1).2 Reserved + 31:0 + R(p+1).1 31:0 + a2[0].z – a2 vertex delta for Attribute0.z + R(p+1).0 31:0 + a1[0].z – a1 vertex delta for Attribute0.z + R(p+2):Rq + Vertex deltas for additional attributes in numerical order + + See definition of Rp and R(p+1) for formats. + + + +11.11 Other WM Functions + +11.11.1 Statistics Gathering +If Statistics Enable is set in WM_STATE or 3DSTATE_WM, the Windower increments the +PS_INVOCATIONS_COUNT register once for each unmasked pixel (or sample) that is dispatched to a +Pixel Shader thread. +PS_INVOCATIONS_COUNT register counts all the pixels/samples present in a 2X2 dispatched to Pixel +Shader. +If Early Depth Test Enable is set it is possible for pixels or samples to be discarded prior to reaching the +Pixel Shader due to failing the depth or stencil test PS_INVOCATIONS_COUNT will still be incremented +for these pixels or samples since the depth test occurs after the pixel shader from the point of view of SW. + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 349 + A0 Erratum BWT004 states that there is no way to indicate a true “null” pixel shader (in the sense that +the pixel shader dispatch will be skipped). The “dummy” PS thread required for a “null” pixel shader will +still cause PS_INVOCATIONS_COUNT to increment on pixel dispatches; if the “null” pixel dispatches are +not to be counted , Statistics Enable must be cleared when changing to a “null” pixel shader Clearing +Statistics Enable may also prevent PS_DEPTH_COUNT from incrementing properly Therefore, in +certain pipeline configurations, it may be impossible to maintain both PS_INVOCATIONS_COUNT and +PS_DEPTH_COUNT accurately. +When Early Depth Test is forced and when Statistics Enable is set, PS_INVOCATIONS_COUNT register +may not have the correct value. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 350 + 12. 3D Pipeline – Color Calculator + (Output Merger) +12.1 Overview +Note:The Color Calculator logic resides in the Render Cache backing Data Port (DAP) shared +function. It is described in this chapter as the Color Calc functions are naturally an extension of the 3D +pipeline past the WM stage. See the DataPort chapter for details on the messages used by the Pixel +Shader to invoke Color Calculator functionality. +The Color Calculator (referred to as “Output Merger in the DX Spec) function within the Data Port +shared function completes the processing of rasterized pixels after the pixel color and depth have been +computed by the Pixel Shader. This processing is initiated when the pixel shader thread sends a Render +Target Write message (see Shared Functions) to the Render Cache. (Note that a single pixel shader +thread may send multiple Render Target Write messages, with the result that multiple render targets get +updated). The pixel variables pass through a pipeline of fixed (yet programmable) functions, and the +results are conditionally written into the appropriate buffers. +The word “pixel” used in this section is effectively replaced with the word “sample” if multisample +rasterization is enabled. + Pipeline Stage Description + Alpha Coverage It generates coverage masks using AlphaToCoverage AND/OR AlphaToOne functions based on + src0.alpha. +Alpha Test Compare pixel alpha with reference alpha and conditionally discard pixel +Stencil Test Compare pixel stencil value with reference and forward result to Buffer Update stage +Depth Test Compare pix.Z with corresponding Z value in the Depth Buffer and forward result to Buffer Update + stage +Color Blending Combine pixel color with corresponding color in color buffer according to programmable function +Gamma Adjust pixel’s color according to gamma function for SRGB destination surfaces. +Correction +Color Convert “full precision” pixel color values to fixed precision of the color buffer format +Quantization +Logic Ops Combine pixel color logically with existing color buffer color (mutually exclusive with Color + Blending) +Buffer Update Write final pixel values to color and depth buffers or discard pixel without update + +The following logic describes the high-level operation of the Pixel Processing pipeline: +PixelProcessing() { +AlphaCoverage() +AlphaTest() +DepthBufferCoordinateOffsetDisable +StencilTest() +DepthTest() +ColorBufferBlending() + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 351 + GammaCorrection() +ColorQuantization() +LogicalOps() +BufferUpdate() +} + + +12.1.1 Alpha Coverage +Alpha coverage logic is supported and can be controlled using three state variables: + +  AlphaToCoverage Enable, when enabled Color Calculator modifies the sample mask. This + function (along with AlphaToOne) come at the top of the pixel pipeline. The sample’s + Source0.Alpha value (possibly being replicated from the pixel’s Source0.Alpha) is used to + compute a (optionally dithered) 1/2/4-bit mask (depending on NumSamples). +  The AlphaToCoverage Dither Enable SV is used to control the dithering of the + AlphaToCoverage mask. The bit corresponding to the sample# is then ANDed with the sample’s + incoming mask bits – allowing the sample to be masked off depending on alpha. +  AlphaToOne Enable, when enabled, Color Calculator must replace Source0.Alpha (if present) + with 1.0f. +  If AlphaToCoverage is disabled, AlphaToCoverage Dither does not have any impact. + +NOTE: + +  Src0.alpha needs to be first multiplied with AA alpha before applying AlphaToCoverage and + AlphaToOne functions. +  An alpha value of NaN results in a no coverage (zero) mask. +  Alpha values from the pixel shader are treated as FLOAT32 format for computing the + AlphaToCoverage Mask. + + +12.1.2 Alpha Test +The Alpha Test function can be used to discard pixels based on a comparison between the incoming +pixel’s alpha value and the Alpha Test Reference state variable in COLOR_CALC_STATE. This +operation can be used to remove transparent or nearly-transparent pixels, though other uses for the alpha +channel and alpha test are certainly possible. +This function is enabled by the Alpha Test Enable state variable in COLOR_CALC_STATE. If +ENABLED, this function compares the incoming pixel’s alpha value (pixColor.Alpha) and the reference +alpha value specified by via the Alpha Test Reference state variable in COLOR_CALC_STATE. The +comparison performed is specified by the Alpha Test Function state variable in COLOR_CALC_STATE. +The Alpha Test Format state variable is used to specify whether Alpha Test is performed using fixed- +point (UNORM8) or FLOAT32 values. Accordingly, it determines whether the Alpha Reference Value is +passed in a UNORM8 or FLOAT32 format. If UNORM8 is selected, the pixel’s alpha value will be +converted from floating-point to UNORM8 before the comparison. +Pixels that pass the Alpha Test proceed for further processing. Those that fail are discarded at this point +in the pipeline. +If Alpha Test Enable is DISABLED, this pipeline stage has no effect. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 352 + The Alpha Test function is supported in conjunction with Multiple Render Targets (MRTs). If delivered in +the incoming render target write message, source 0 alpha is used to perform the alpha test. If source 0 +alpha is not delivered, the normal alpha value is used to perform the alpha test. + + +12.1.3 Depth Coordinate Offset +The Depth Coordinate Offset function applies a programmable constant offset to the RenderTarget X,Y +screen space coordinates in order to generate DepthBuffer coordinates. +The function has been specifically added to allow the OpenGL driver to deal with a RenderTarget and +DepthBuffer of differing sizes. +In contrast, OpenGL defines a lower-left screen coordinate origin. This requires the driver to incorporate a +“Y coordinate flipping” transformation into the viewport mapping function. The Y extent of the RT is used +in this flipping transformation. If the DepthBuffer extent is different, the wrong pixel Y locations within the +DepthBuffer will be accessed. +The least expensive solution is to provide a translation offset to be applied to the post-viewport-mapped +DepthBuffer Y pixel coordinate, effectively allowing the alignment of the lower-left origins of the RT and +DepthBuffer. [Note that the previous DBCOD feature performed an optional translation of post-viewport- +mapping RT pixel (screen) coordinates to generate DepthBuffer pixel (window) coordinates. Specifically, +the Draw Rect Origin X,Y state could be subtracted from the RT pixel coordinates.] +This function uses Depth Coordinate Offset X,Y state (signed 16-bit values in +3DSTATE_DEPTH_RECTANGLE) that is unconditionally added to the RT pixel coordinates to +generate DepthBuffer pixel coordinates. +The previous DBCOB feature can be supported by having the driver program Depth Coordinate X,Y +Offset to the two’s complement of the the Draw Rect Origin. By programming Depth Coordinate X,Y +Offset to zeros, the current “normal” operation (DBCOD disabled) can be achieved. +Programming Restrictions: + +  Only simple 2D RTs are supported (no mipmaps) +  Software must ensure that the resultant DepthBuffer Coordinate X,Y values are non-negative. +  There are alignment restrictions – see 3DSTATE_DEPTH_BUFFER command. + + +12.1.4 Stencil Test +The Stencil Test function can be used to discard pixels based on a comparison between the [Backface] +Stencil Test Reference state variable and the pixel’s stencil value. This is a general purpose function +used for such effects as shadow volumes, per-pixel clipping, etc. The result of this comparison is used in +the Stencil Buffer Update function later in the pipeline. +This function is enabled by the Stencil Test Enable state variable. If ENABLED, the current stencil buffer +value for this pixel is read. +Programming Note: + +  If the Depth Buffer is either undefined or does not have a surface format of + D32_FLOAT_S8X24_UINT or D24_UNORM_S8_UINT and separate stencil buffer is disabled, + Stencil Test Enable must be DISABLED. + +A 2nd set of the stencil test state variables is provided so that pixels from back-facing objects, assuming +they are not culled, can have a stencil test performed on them separate from the test for normal front- +facing objects. The separate stencil test for back-facing objects can be enabled via the Double Sided + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 353 + Stencil Enable state variable. Otherwise, non-culled back-facing objects will use the same test function, +mask and reference value as front-facing objects. The 2nd stencil state for back-facing objects is most +commonly used to improve the performance of rendering shadow volumes which require a different +stencil buffer operation depending on whether pixels rendered are from a front-facing or back-facing +object. The backface stencil state removes the requirement to render the shadow volumes in 2 passes or +sort the objects into front-facing and back-facing lists. +The remainder of this subsection describes the function in term of [Backface] . +The Backface set of state variables are only used if Double Sided Stencil Enable is ENABLED and the +object is considered back-facing. Otherwise the normal (front-facing) state variables are used. +This function then compares the [Backface] Stencil Test Reference value and the pixel’s stencil value +value after logically ANDing both values by [Backface] Stencil Test Mask. The comparison performed is +specified by the [Backface] Stencil Test Function state variable. The result of the comparison is passed +down the pipeline for use in the Stencil Buffer Update function. The Stencil Test function does not in itself +discard pixels. +If Stencil Test Enable is DISABLED, a result of “stencil test passed” is propagated down the pipeline. + + +12.1.5 Depth Test +The Depth Test function can be used to discard pixels based on a comparison between the incoming +pixel’s depth value and the current depth buffer value associated with the pixel. This function is typically +used to perform the “Z Buffer” hidden surface removal. The result of this pipeline function is used in the +Stencil Buffer Update function later in the pipeline. +This function is enabled by the Depth Test Enable state variable. If enabled, the pixel’s (“source”) depth +value is first computed. After computation the pixel’s depth value is clamped to the range defined by +Minimum Depth and Maximum Depth in the selected CC_VIEWPORT state. Then the current +(“destination”) depth buffer value for this pixel is read. +This function then compares the source and destination depth values. The comparison performed is +specified by the Depth Test Function state variable. +The result of the comparison is propogated down the pipeline for use in the subsequent Depth Buffer +Update function. The Depth Test function does not in itself discard pixels. +If Depth Test Enable is DISABLED, a result of “depth test passed” is propagated down the pipeline. +Programming Note: + +  Enabling the Depth Test function without defining a Depth Buffer is UNDEFINED. + + +12.1.6 Pre-Blend Color Clamping +Pre-Blend Color Clamping, controlled via Pre-Blend Color Clamp Enable OR Pre-Blend Source Only +Clamp Enable and Color Clamp Range states in COLOR_CALC_STATE, is affected by the enabling of +Color Buffer Blend as described below. +The following table summarizes the requirements involved with Pre-/Post-Blend Color Clamping. + Blending RT Format Pre-Blend Color Clamp Post-Blend Color Clamp + Off UNORM, Must be enabled with range = RT n/a, state ignored + UNORM_SRGB,YCRCB range or [0,1] (same function) + SNORM Must be enabled with range = RT n/a, state ignored + range or [-1,1] (same function) + FLOAT (except for Must be enabled (with any desired n/a, state ignored + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 354 + Blending RT Format Pre-Blend Color Clamp Post-Blend Color Clamp + R11G11B10_FLOAT) range) + R11G11B10_FLOAT Must be enabled with either [0,1] n/a, state ignored + or RT range + UINT, SINT State ignored, implied clamp to n/a, state ignored + RT range + UNORM, UNORM_SRGB Must be enabled with range = RT Must be enabled with range = RT + On range or [0,1] (same function) range or [0,1] (same function) + (where + permitted) + SNORM Must be enabled with range = RT Must be enabled with range = RT + range or [-1,1] (same function) range or [-1,1] (same function) + FLOAT (except for Can be disabled or enabled (with Must be enabled (with any desired + R11G11B10_FLOAT) any desired range) range) + R11G11B10_FLOAT Can be disabled or enabled (with Must be enabled with either [0,1] + any desired range) or RT range + + +12.1.6.1 Pre-Blend Color Clamping when Blending is Disabled +The clamping of source color components is controlled by Pre-Blend Color Clamp Enable. If ENABLED, +all source color components are clamped to the range specified by Color Clamp Range. If DISABLED, +no clamping is performed. + Programming Notes: + +  Given the possibility of writing UNPREDICTABLE values to the Color Buffer, it is expected and + highly recommended that, when blending is disabled, software set Pre-Blend Color Clamp Enable + to ENABLED and select an appropriate Color Clamp Range. +  When using SINT or UINT rendertarget surface formats, Blending must be DISABLED. The Pre- + Blend Color Clamp Enable and Color Clamp Range fields are ignored, and an implied clamp to + the rendertarget surface format is performed. + +12.1.6.2 Pre-Blend Color Clamping when Blending is Enabled +The clamping of source, destination and constant color components is controlled by Pre-Blend Color +Clamp Enable. If ENABLED, all these color components are clamped to the range specified by Color +Clamp Range. If DISABLED, no clamping is performed on these color components prior to blending. + + +12.1.7 Color Buffer Blending +The Color Buffer Blending function is used to combine one or two incoming “source” pixel color+alpha +values with the “destination” color+alpha read from the corresponding location in a RenderTarget. +Blending is enabled on a global basis by the Color Buffer Blend Enable state variable (in +COLOR_CALC_STATE). If DISABLED, Blending and Post-Blend Clamp functions are disabled for all +RenderTargets, and the pixel values (possibly subject to Pre-Blend Clamp) are passed through +unchanged. +. +The Color Buffer Blend Enable is in the per-render-target BLEND_STATE, and the field in +SURFACE_STATE is no longer supported. +Programming Notes: + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 355 +  Color Buffer Blending and Logic Ops must not be enabled simultaneously, or behavior is + UNDEFINED. +  Dual source blending: + +  Only certain surface formats support Color Buffer Blending. Refer to the Surface Format tables in + Sampling Engine. Blending must be disabled on a RenderTarget if blending is not supported. + +The incoming “source” pixel values are modulated by a selected “source” blend factor, and the possibly +gamma-decorrected “destination” values are modulated by a “destination” blend factor. These terms are +then combined with a “blend function”. In general: + +src_term = src_blend_factor * src_color + +dst_term = dst_blend_factor * dst_color + +color output = blend_function( src_term, dst_term) +If there is no alpha value contained in the Color Buffer, a default value of 1.0 is used and, +correspondingly, there is no alpha component computed by this function. +Dual Source Blending: When using “Dual Source” Render Target Write messages, the Source1 pixel +color+alpha passed in the message can be selected as a src/dst blend factor. See Color Buffer Blending. +In single-source mode, those blend factor selections are invalid. If SRC1 is included in a src/dst blend +factor and a DualSource RT Write message is not utilized, results are UNDEFINED. (This reflects the +same restriction in DX APIs, where undefined results are produced if “o1” is not written by a PS – there +are no default values defined). If SRC1 is not included in a src/dst blend factor, dual source blending must +be disabled. +The blending of the color and alpha components is controlled with two separate (color and alpha) sets of +state variables. However, if the Independent Alpha Blend Enable state variable in +COLOR_CALC_STATE is DISABLED, then the “color” (rather than “alpha”) set of state variables is used +for both color and alpha. Note that this is the only use of the Independent Alpha Blend Enable state – it +does not control whether Blending occurs, only how. +Per Render Target Blend State: Blend state is selected based on Render Target Index contained in the +message header, and appropriate blend state is applied to Render Target Write messages. +The following table describes the color source and destination blend factors controlled by the Source +[Alpha] Blend Factor and Destination [Alpha] Blend Factor state variables in COLOR_CALC_STATE. +Note that the blend factors applied to the R,G,B channels are always controlled by the +Source/Destination Blend Factor, while the blend factor applied to the alpha channel is controlled either +by Source/Destination Blend Factor or Source/Destination Alpha Blend Factor. + +Color Buffer Blend Color Factors + + Blend Factor Applied for R,G,B,A channels + (oN = output from PS to RT#N) + (o1 = 2nd output from PS in Dual-Souce mode only) + (rtN = destination color from RT#N) + (CC = Constant Color) + Blend Factor Selection +BLENDFACTOR_ZERO 0.0, 0.0, 0.0, 0.0 +BLENDFACTOR_ONE 1.0, 1.0, 1.0, 1.0 +BLENDFACTOR_SRC_COLOR oN.r, oN.g, oN.b, oN.a +BLENDFACTOR_INV_SRC_COLOR 1.0-oN.r, 1.0-oN.g, 1.0-oN.b, 1.0-oN.a +BLENDFACTOR_SRC_ALPHA oN.a, oN.a, oN.a, oN.a +BLENDFACTOR_INV_SRC_ALPHA 1.0-oN.a, 1.0-oN.a, 1.0-oN.a, 1.0-oN.a + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 356 + Blend Factor Applied for R,G,B,A channels + (oN = output from PS to RT#N) + (o1 = 2nd output from PS in Dual-Souce mode only) + (rtN = destination color from RT#N) + (CC = Constant Color) + Blend Factor Selection +BLENDFACTOR_SRC1_COLOR o1.r, o1.g, o1.b, o1.a +BLENDFACTOR_INV_SRC1_COLOR 1.0-o1.r, 1.0-o1.g, 1.0-o1.b, 1.0-o1.a +BLENDFACTOR_SRC1_ALPHA o1.a, o1.a, o1.a, o1.a +BLENDFACTOR_INV_SRC1_ALPHA 1.0-o1.a, 1.0-o1.a, 1.0-o1.a, 1.0-o1.a +BLENDFACTOR_DST_COLOR rtN.r, rtN.g, rtN.b, rtN.a +BLENDFACTOR_INV_DST_COLOR 1.0-rtN.r, 1.0-rtN.g, 1.0-rtN.b, 1.0-rtN.a +BLENDFACTOR_DST_ALPHA rtN.a, rtN.a, rtN.a, rtN.a +BLENDFACTOR_INV_DST_ALPHA 1.0-rtN.a, 1.0-rtN.a, 1.0-rtN.a, 1.0-rtN.a +BLENDFACTOR_CONST_COLOR CC.r, CC.g, CC.b, CC.a +BLENDFACTOR_INV_CONST_COLOR 1.0-CC.r, 1.0-CC.g, 1.0-CC.b, 1.0-CC.a +BLENDFACTOR_CONST_ALPHA CC.a, CC.a, CC.a, CC.a +BLENDFACTOR_INV_CONST_ALPHA 1.0-CC.a, 1.0-CC.a, 1.0-CC.a, 1.0-CC.a +BLENDFACTOR_SRC_ALPHA_SATURATE f,f,f,1.0 where f = min(1.0 – rtN.a, oN.a) + +The following table lists the supported blending operations defined by the Color Blend Function state +variable and the Alpha Blend Function state variable (when in independent alpha blend mode). + +Color Buffer Blend Functions + + Operation (for each color component) + Blend Function +BLENDFUNCTION_ADD SrcColor*SrcFactor + DstColor*DstFactor +BLENDFUNCTION_SUBTRACT SrcColor*SrcFactor - DstColor*DstFactor +BLENDFUNCTION_REVERSE_SUBTRACT DstColor*DstFactor - SrcColor*SrcFactor +BLENDFUNCTION_MIN + min (SrcColor*SrcFactor, DstColor*DstFactor) + Programming Note: This is a superset of the OpenGL “min” function. + +BLENDFUNCTION_MAX + max (SrcColor*SrcFactor, DstColor*DstFactor) Programming Note: + This is a superset of the OpenGL “max” function. + + + +12.1.8 Post-Blend Color Clamping +(See Pre-Blend Color Clamping above for a summary table regarding clamping) +Post-Blend Color clamping is available only if Blending is enabled. +If Blending is enabled, the clamping of blending output color components is controlled by Post-Blend +Color Clamp Enable. If ENABLED, the color components output from blending are clamped to the range +specified by Color Clamp Range. If DISABLED, no clamping is performed at this point. +Regardless of the setting of Post-Blend Color Clamp Enable, when Blending is enabled color +components will be automatically clamped to (at least) the rendertarget surface format range at this stage +of the pipeline. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 357 + 12.1.9 Dithering +Dithering is used to give the illusion of a higher resolution when using low-bpp channels in color buffers +(e.g., with 16bpp color buffer). By carefully choosing an arrangement of lower resolution colors, colors +otherwise not representable can be approximated, especially when seen at a distance where the viewer’s +eyes will average adjacent pixel colors. Color dithering tends to diffuse the sharp color bands seen on +smooth-shaded objects. +A four-bit dither value is obtained from a 4x4 Dither Constant matrix depending on the pixel’s X and Y +screen coordinate. The pixel’s X and Y screen coordinates are first offset by the Dither Offset X and +Dither Offset Y state variables (these offsets are used to provide window-relative dithering). Then the two +LSBs of the pixel's screen X coordinate are used to address a column in the dither matrix, and the two +LSBs of the pixel's screen Y coordinate are used to address a row. This way, the matrix repeats every +four pixels in both directions. +The value obtained is appropriately shifted to align with (what would be otherwise) truncated bits of the +component being dithered. It is then added with the component and the result is truncated to the bit depth +of the component given the color buffer format. + + + + +Dithering Process (5-Bit Example) + + +12.1.10 Logic Ops +The Logic Ops function is used to combine the incoming “source” pixel color/alpha values with the +corresponding “destination” color/alpha contained in the ColorBuffer, using a logic function. +The Logic Op function is enabled by the LogicOp Enable state variable. If DISABLED, this function is +ignored and the incoming pixel values are passed through unchanged. + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 358 + Programming Notes: + +  Color Buffer Blending and Logic Ops must not be enabled simultaneously, or behavior is + UNDEFINED. +  Logic Ops are only supported on *_UNORM surfaces, otherwise Logic Ops must be DISABLED. + +The following table lists the supported logic ops. The logic op is selected using the Logic Op Function +field in COLOR_CALC_STATE. + +Logic Ops + LogicOp Function Definition (S=Source, D=Destination) +LOGICOP_CLEAR all 0’s +LOGICOP_NOR NOT (S OR D) +LOGICOP_AND_INVERTED (NOT S) AND D +LOGICOP_COPY_INVERTED NOT S +LOGICOP_AND_REVERSE S AND NOT D +LOGICOP_INVERT NOT D +LOGICOP_XOR S XOR D +LOGICOP_NAND NOT (S AND D) +LOGICOP_AND S AND D +LOGICOP_EQUIV NOT (S XOR D) +LOGICOP_NOOP D +LOGICOP_OR_INVERTED (NOT S) OR D +LOGICOP_COPY S +LOGICOP_OR_REVERSE S OR NOT D +LOGICOP_OR S OR D +LOGICOP_SET all 1’s + + +12.1.11 Buffer Update +The Buffer Update function is responsible for updating the pixel’s Stencil, Depth and Color Buffer contents +based upon the results of the Stencil and Depth Test functions. Note that Kill Pixel and/or Alpha Test +functions may have already discarded the pixel by this point. + +12.1.11.1 Stencil Buffer Updates +If and only if stencil testing is enabled, the Stencil Buffer is updated according to the Stencil Fail Op, +Stencil Pass Depth Fail Op, and Stencil Pass Depth Pass Op state (or their backface counterparts if +Double Sided Stencil Enable is ENABLED and the pixel is from a back-facing object) and the results of +the Stencil Test and Depth Test functions. +Stencil Fail Op and Backface Stencil Fail Op specify how/if the stencil buffer is modified if the +stencil test fails. Stencil Pass Depth Fail Op and Backface Stencil Pass Depth Fail Op specify +how/if the stencil buffer is modified if the stencil test passes but the depth test fails. +Stencil Pass Depth Pass Op and Backface Stencil Pass Depth Pass Op specify how/if the stencil +buffer is modified if both the stencil and depth tests pass. The operations (on the stencil buffer) +that are to be performed under one of these (mutually exclusive) conditions is summarized in the +following table. + +Stencil Buffer Operations + Stencil Operation Description +STENCILOP_KEEP Do not modify the stencil buffer + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 359 + Stencil Operation Description +STENCILOP_ZERO Store a 0 +STENCILOP_REPLACE + Store the StencilTestReference reference value + +STENCILOP_INCRSAT Saturating increment (clamp to max value) +STENCILOP_DECRSAT Saturating decrement (clamp to 0) +STENCILOP_INCR Increment (possible wrap around to 0) +STENCILOP_DECR Decrement (possible wrap to max value) +STENCILOP_INVERT Logically invert the stencil value + +Any and all writes to the stencil portion of the depth buffer are enabled by the Stencil Buffer Write +Enable state variable. +When writes are enabled, the Stencil Buffer Write Mask and Backface Stencil Buffer Write Mask state +variables provide an 8-bit mask that selects which bits of the stencil write value are modified. Masked-off +bits (i.e., mask bit == 0) are left unmodified in the Stencil Buffer. +Programming Notes: + +  The Stencil Buffer can be written even if depth buffer writes are disabled via Depth Buffer Write + Enable. + +12.1.11.2 Depth Buffer Updates +Any and all writes to the Depth Buffer are enabled by the Depth Buffer Write Enable state variable. If +there is no Depth Buffer, writes must be explicitly disabled with this state variable, or operation is +UNDEFINED. +If depth testing is disabled or the depth test passed, the incoming pixel’s depth value is written to the +Depth Buffer. If depth testing is enabled and the depth test failed, the pixel is discarded – with no +modification to the Depth or Color Buffers (though the Stencil Buffer may have been modified). + +12.1.11.3 Color Gamma Correction +Computed RGB (not A) channels can be gamma-corrected prior to update of the Color Buffer. +This function is automatically invoked whenever the destination surface (render target) has an SRGB +format (see surface formats in Sampling Engine). For these surfaces, the computed RGB values are +converted from gamma=1.0 space to gamma=2.4 space by applying a ^(2.4) exponential function. + +12.1.11.4 Color Buffer Updates +Finally, if the pixel has not been discarded by this point, the incoming pixel color is written into the Color +Buffer. The Surface Format of the color buffer indicates which channel(s) are written (e.g., +R8G8_UNORM are written with the Red and Green channels only). The Color Buffer Component Write +Disables from the Color Buffer’s SURFACE_STATE provide an independent write disable for each +channel of the Color Buffer. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 360 + 12.2 Pixel Pipeline State Summary + +12.2.1 COLOR_CALC_STATE + + COLOR_CALC_STATE + +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +This register is pointed to by a field in 3DSTATE_CC_STATE_POINTERS, and stored at a 64-byte aligned boundary. +DWord Bit Description +0 31:24 Stencil Reference Value + + Format: U8.0 + This field specifies the stencil reference value to compare against in the (front face) StencilTest + function. + + 23:16 BackFace Stencil Reference Value + + Format: U8.0 + This field specifies the stencil reference value to compare against in the StencilTest function. + + 15 Round Disable Function Disable + Project: All + Format: U8.0 + Disables the round-disable function of the color calculator. If this bit is zero, dithering is cancelled + based on the data used by blend to avoid drift. If this bit is one, this is not done. + + 14:1 Reserved + Project: All + Format: MBZ + 0 Alpha Test Format + Project: All + This field selects the format for Alpha Reference Value and the format in which Alpha Test is + performed. + Value Name Description Project + 0h ALPHATEST_UNORM8 UNorm8 All + 1h ALPHATEST_FLOAT32 Float32 All + + + Programming Notes + Alpha-test format is independent of RT format. When PS outputs UNIT/SINT alpha-value, it will be + treated as IEEE 32bit float number for the purpose of alpha-test. +1 31:0 Alpha Reference Value + Project: All + Exists If: Alpha Test Format == ALPHATEST_ FLOAT32 + Format: IEEE_Float + This field specifies the alpha reference value to compare against in the Alpha Test function. + + 31:0 Alpha Reference Value + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 361 + COLOR_CALC_STATE + Project: All + Exists If: Alpha Test Format == ALPHATEST_UNORM8 + Format: UNORM8 Upper 24 bits MBZ + + + This field specifies the alpha reference value to compare against in the Alpha Test function. + +2 31:0 Blend Constant Color Red + Format: IEEE_Float + This field specifies the Red channel of the Constant Color used in Color Buffer Blending. + +3 31:0 Blend Constant Color Green + Format: IEEE_Float + This field specifies the Green channel of the Constant Color used in Color Buffer Blending. + +4 31:0 Blend Constant Color Blue + Format: IEEE_Float + This field specifies the Blue channel of the Constant Color used in Color Buffer Blending. + +5 31:0 Blend Constant Color Alpha + Format: IEEE_Float + This field specifies the Alpha channel of the Constant Color used in Color Buffer Blending. + + + + +12.2.2 DEPTH_STENCIL_STATE + + DEPTH_STENCIL_STATE + +Default Value: 0x00000000, 0x00000000, 0x00000000 +The DEPTH_STENCIL_STATE is pointed to by a field in 3DSTATE_CC_STATE_POINTERS. It is stored at a 64- +byte aligned boundary. +DWord Bit Description +0 31 Stencil Test Enable + Project: All + Format: Enable + Enables StencilTest function of the Pixel Processing pipeline. + Programming Notes + If any of the render targets are YUV format, this field must be disabled. + 30:28 Stencil Test Function + Project: All + Format: 3D_CompareFunction + This field specifies the comparison function used in the (front face) StencilTest function. + Value Name Project + 0h COMPAREFUNCTION_ALWAYS All + 1h COMPAREFUNCTION_NEVER All + 2h COMPAREFUNCTION_LESS All + 3h COMPAREFUNCTION_EQUAL All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 362 + DEPTH_STENCIL_STATE + 4h COMPAREFUNCTION_LEQUAL All + 5h COMPAREFUNCTION_GREATER All + 6h COMPAREFUNCTION_NOTEQUAL All + 7h COMPAREFUNCTION_GEQUAL All + 27:25 Stencil Fail Op + Project: All + Format: 3D_StencilOperation + This field specifies the operation to perform on the Stencil Buffer when the (front face) stencil test fails. + Note: if all three stencil ops (Stencil Fail, Stencil Pass Depth Fail, and Stencil Pass Depth Pass) are + KEEP, ZERO, or REPLACE, the stencil buffer is not read. + Value Name Project + 0 STENCILOP_KEEP All + 1 STENCILOP_ZERO All + 2 STENCILOP_REPLACE All + 3 STENCILOP_INCRSAT All + 4 STENCILOP_DECRSAT All + 5 STENCILOP_INCR All + 6 STENCILOP_DECR All + 7 STENCILOP_INVERT All + 24:22 Stencil Pass Depth Fail Op + Project: All + Format: 3D_StencilOperation see Stencil Fail Op + + + This field specifies the operation to perform on the Stencil Buffer when the (front face) stencil test + passes but the depth pass fails. + + 21:19 Stencil Pass Depth Pass Op + Project: All + Format: 3D_StencilOperation see Stencil Fail Op + + + This field specifies the operation to perform on the Stencil Buffer when the (front face) stencil test + passes and the depth pass passes (or is disabled). + + 18 Stencil Buffer Write Enable + Project: All + Format: Enable + Enables writes to the Stencil Buffer. + Programming Notes + If this field is enabled, Stencil Test Enable must also be enabled. + 17:16 Reserved + Project: All + Format: MBZ + 15 Double Sided Stencil Enable + Project: All + Format: Enable + Enable doubled sided stencil operations. + Value Name Description Project + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 363 + DEPTH_STENCIL_STATE + 1 Enable Double Sided Stencil Enabled All + 0 Disable Double Sided Stencil Disabled All + + + Programming Notes + Back-facing primitives have a vertex winding order opposite to the currently selected Front Winding + state.Culling of primitives is not affected by the double sided stencil stateBack-facing primitives will be + rendered, honoring all current device state, as though it were a front-facing primitive with no implicitly + overloaded state. + 14:12 BackFace Stencil Test Function + Project: All + Format: 3D_CompareFunction + This field specifies the comparison function used in the StencilTest function. + Value Name Project + 0h COMPAREFUNCTION_ALWAYS All + 1h COMPAREFUNCTION_NEVER All + 2h COMPAREFUNCTION_LESS All + 3h COMPAREFUNCTION_EQUAL All + 4h COMPAREFUNCTION_LEQUAL All + 5h COMPAREFUNCTION_GREATER All + 6h COMPAREFUNCTION_NOTEQUAL All + 7h COMPAREFUNCTION_GEQUAL All + 11:9 Backface Stencil Fail Op + Project: All + Format: 3D_StencilOperation + This field specifies the operation to perform on the Stencil Buffer when the stencil test fails. + Value Name Description Project + 0 STENCILOP_KEEP STENCILOP_KEEP All + 1 STENCILOP_ZERO STENCILOP_ZERO All + 2 STENCILOP_REPLACE STENCILOP_REPLACE All + 3 STENCILOP_INCRSAT STENCILOP_INCRSAT All + 4 STENCILOP_DECRSAT STENCILOP_DECRSAT All + 5 STENCILOP_INCR STENCILOP_INCR All + 6 STENCILOP_DECR STENCILOP_DECR All + 7 STENCILOP_INVERT STENCILOP_INVERT All + 8:6 Backface Stencil Pass Depth Fail Op + Project: All + Format: 3D_StencilOperation see Stencil Fail Op + + + This field specifies the operation to perform on the Stencil Buffer when the stencil test passes but the + depth pass fails. + + 5:3 Backface Stencil Pass Depth Pass Op + Project: All + Format: 3D_StencilOperation see Stencil Fail Op + + + This field specifies the operation to perform on the Stencil Buffer when the stencil test passes and the + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 364 + DEPTH_STENCIL_STATE + depth pass passes (or is disabled). + + 2:0 Reserved + Project: All + Format: MBZ +1 31:24 Stencil Test Mask + Project: All + Format: U8 + This field specifies a bit mask applied to stencil test values. Both the stencil reference value and value + read from the stencil buffer will be logically ANDed with this mask before the stencil comparison test is + performed. + + 23:16 Stencil Write Mask + Project: All + Format: U8 + This field specifies a bit mask applied to stencil buffer writes. Only those stencil buffer bits + corresponding to bits set in this mask will be modified. + + 15:8 Backface Stencil Test Mask + Project: All + Format: U8 + This field specifies a bit mask applied to backface stencil test values. Both the stencil reference value + and value read from the stencil buffer will be logically ANDed with this mask before the stencil + comparison test is performed. + + 7:0 Backface Stencil Write Mask + Project: All + Format: U8 + This field specifies a bit mask applied to backface stencil buffer writes. Only those stencil buffer bits + corresponding to bits set in this mask will be modified. + +2 31 Depth Test Enable + Project: All + Format: Enable + Enables the DepthTest function of the Pixel Processing pipeline. + Programming Notes + If any of the render targets are YUV format, this field must be disabled. + 30 Reserved + Project: All + Format: MBZ + 29:27 Depth Test Function + Project: All + Format: 3D_DepthTestFunction + Specifies the comparison function used in DepthTest function. + Value Name Project + 0h COMPAREFUNCTION_ALWAYS All + 1h COMPAREFUNCTION_NEVER All + 2h COMPAREFUNCTION_LESS All + 3h COMPAREFUNCTION_EQUAL All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 365 + DEPTH_STENCIL_STATE + 4h COMPAREFUNCTION_LEQUAL All + 5h COMPAREFUNCTION_GREATER All + 6h COMPAREFUNCTION_NOTEQUAL All + 7h COMPAREFUNCTION_GEQUAL All + + + Programming Notes + if the Depth Test Function is ALWAYS or NEVER, the depth buffer is not read. + 26 Depth Buffer Write Enable + Project: All + Format: Enable + Enables writes to the Depth Buffer. + Programming Notes + A Depth Buffer must be defined before enabling writes to it, or operation is UNDEFINED. + 25:0 Reserved + Project: All + Format: MBZ + + + + +12.2.3 BLEND_STATE + + BLEND_STATE + +Default Value: 0x00000000, 0x00000000 +The blend state is stored as an array of up to 8 elements, each of which contains the DWords described here. The +start of each element is spaced 2 DWords apart. The first element of the blend state array is aligned to a 64-byte +boundary, which is pointed to by a field in 3DSTATE_CC_STATE_POINTERS. The 3-bit Render Target Index field in +the Render Target Write data port message header is used to select which of the 8 elements from BLEND_STATE +that is used on the current message. +DWord Bit Description +0 31 Color Buffer Blend Enable + Project: All + Format: Enable + Enables the ColorBufferBlending (nee “alpha blending”) function of the Pixel Processing Pipeline for + this render target. + Programming Notes + Enabling LogicOp and ColorBufferBlending at the same time is UNDEFINED + 30 Independent Alpha Blend Enable + Project: All + Format: Enable + When enabled, the other fields in this instruction control the combination of the alpha components in + the Color Buffer Blend stage. When disabled, the alpha components are combined in the same fashion + as the color components. + + 29 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 366 + BLEND_STATE + 28:26 Alpha Blend Function + Project: All + Format: 3D_ColorBufferBlendFunction + This field specifies the function used to combine the alpha components in the Color Buffer blend stage + of the Pixel Pipeline when the IndependentAlphaBlend state is enabled. + Value Name Project + 0 BLENDFUNCTION_ADD All + 1 BLENDFUNCTION_SUBTRACT All + 2 BLENDFUNCTION_REVERSE_SUBTRACT All + 3 BLENDFUNCTION_MIN All + 4 BLENDFUNCTION_MAX All + 5-7 Reserved All + 25 Reserved + Project: All + Format: MBZ + 24:20 Source Alpha Blend Factor + Project: All + Format: 3D_ColorBufferBlendFactor + Controls the “source factor” in alpha Color Buffer Blending stage.Note: For the source/destination alpha + blend factors, the encodings indicating “COLOR” are the same as the encodings indicating “ALPHA”, + as the alpha component of the color is selected. + Value Name Project + 00h Reserved All + 01h BLENDFACTOR_ONE All + 02h BLENDFACTOR_SRC_COLOR All + 03h BLENDFACTOR_SRC_ALPHA All + 04h BLENDFACTOR_DST_ALPHA All + 05h BLENDFACTOR_DST_COLOR All + 06h BLENDFACTOR_SRC_ALPHA_SATURATE All + 07h BLENDFACTOR_CONST_COLOR All + 08h BLENDFACTOR_CONST_ALPHA All + 09h BLENDFACTOR_SRC1_COLOR All + 0Ah BLENDFACTOR_SRC1_ALPHA All + 0Bh-10h Reserved All + 11h BLENDFACTOR_ZERO All + 12h BLENDFACTOR_INV_SRC_COLOR All + 13h BLENDFACTOR_INV_SRC_ALPHA All + 14h BLENDFACTOR_INV_DST_ALPHA All + 15h BLENDFACTOR_INV_DST_COLOR All + 16h Reserved All + 17h BLENDFACTOR_INV_CONST_COLOR All + 18h BLENDFACTOR_INV_CONST_ALPHA All + 19h BLENDFACTOR_INV_SRC1_COLOR All + 1Ah BLENDFACTOR_INV_SRC1_ALPHA All + 19:15 Destination Alpha Blend Factor + Project: All + Format: 3D_ColorBufferBlendFactor + Controls the “destination factor” in alpha Color Buffer Blending stage. Refer to Source Alpha Blend + Factor for encodings. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 367 + BLEND_STATE + + 14 Reserved + Project: All + Format: MBZ + 13:11 Color Blend Function + Project: All + Format: 3D_ColorBufferBlendFunction + This field specifies the function used to combine the color components in the ColorBufferBlending + function of the Pixel Processing Pipeline. If Independent Alpha Blend Enable is disabled, this field will + also control the blending of the alpha components in the ColorBufferBlending function. + Value Name Project + 0 BLENDFUNCTION_ADD All + 1 BLENDFUNCTION_SUBTRACT All + 2 BLENDFUNCTION_REVERSE_SUBTRACT All + 3 BLENDFUNCTION_MIN All + 4 BLENDFUNCTION_MAX All + 10 Reserved + Project: All + Format: MBZ + 9:5 Source Blend Factor + Project: All + Format: 3D_ColorBufferBlendFactor + Controls the “source factor” in the ColorBufferBlending function.Refer to Source Alpha Blend Factor for + encodings. + + 4:0 Destination Blend Factor + Project: All + Format: 3D_ColorBufferBlendFactor + Controls the “destination factor” in the ColorBufferBlending function. Refer to Source Alpha Blend + Factor for encodings. + +1 31 AlphaToCoverage Enable + Project: All + Format: Enable + If set, Source0 Alpha is converted to a temporary 1/2/4-bit coverage mask and the mask bit + corresponding to the sample# ANDed with the sample mask bit. If set, sample coverage is computed + based on src0 alpha value. Value of 0 disables all samples and value of 1 enables all samples for that + pixel. The same coverage needs to apply to all the RTs in MRT case. Further, any value of src0 alpha + between 0 and 1 monotonically increases the number of enabled pixels.The same coverage needs to + be applied to all the RTs in MRT case. + + 30 AlphaToOne Enable + Project: All + Format: Enable + If set, Source0 Alpha is set to 1.0f after (possibly) being used to generate the AlphaToCoverage + coverage mask.The same coverage needs to be applied to all the RTs in MRT case.If Dual Source + Blending is enabled, this bit must be disabled. + Errata Description Project + This bit must be disabled. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 368 + BLEND_STATE + 29 AlphaToCoverage Dither Enable + Project: All + Format: Enable + If set, sample coverage is computed based on src0 alpha value and it modulates the sample coverage + based on screen coordinates. Value of 0 disables all samples and value of 1 enables all samples for + that pixel. The same coverage needs to apply to all the RTs in MRT case. Further, any value of src0 + alpha between 0 and 1 monotonically increases the number of enabled pixels. The same coverage + needs to be applied to all the RTs in MRT case.If AlphaToCoverage is disabled, AlphaToCoverage + Dither does not have any impact. + + 28 Reserved + Project: All + Format: MBZ + 27 Write Disable Alpha + Project: All + Format: Disable + This field controls the writing of the alpha component into the Render Target. + Value Name Description Project + 0b Enabled Alpha component can be overwritten All + 1b Disabled Writes to the color buffer will not modify Alpha. All + + + Programming Notes + For YUV surfaces, this field must be set to 0B (enabled). + + + Errata Description Project + This field should not be set to 0 if the alpha component is not present in the Render + Target surface format. + 26 Write Disable Red + Project: All + Format: Disable + This field controls the writing of the red component into the Render Target. + Value Name Description Project + 0b Enabled Red component can be overwritten All + 1b Disabled Writes to the color buffer will not modify Red. All + + + Programming Notes + For YUV surfaces, this field must be set to 0B (enabled). + + + Errata Description Project + This field should not be set to 0 if the Red component is not present in the Render + Target surface format. + 25 Write Disable Green + Project: All + Format: Disable + This field controls the writing of the green component into the Render Target. + Value Name Description Project + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 369 + BLEND_STATE + 0b Enabled Green component can be overwritten All + 1b Disabled Writes to the color buffer will not modify Green. All + + + Programming Notes + For YUV surfaces, this field must be set to 0B (enabled). + + + Errata Description Project + This field should not be set to 0 if the Green component is not present in the Render + Target surface format + 24 Write Disable Blue + Project: All + Format: Disable + This field controls the writing of the Blue component into the Render Target. + Value Name Description Project + 0b Enabled Blue component can be overwritten All + 1b Disabled Writes to the color buffer will not modify Blue. All + + + Programming Notes + For YUV surfaces, this field must be set to 0B (enabled). + + + Errata Description Project + This field should not be set to 0 if the Red component is not present in the Render + Target surface format + 23 Reserved + Project: All + Format: MBZ + 22 Logic Op Enable + Project: All + Format: Enable + Enables the LogicOp function of the Pixel Processing pipeline. + Programming Notes + Enabling LogicOp and Color Buffer Blending at the same time is UNDEFINED + 21:18 Logic Op Function + Project: All + Format: 3D_LogicOpFunction + This field specifies the function to be performed (when enabled) in the Logic Op stage of the Pixel + Processing pipeline. Note that the encoding of this field is one less than the corresponding “R2_” ROP + code defined in WINGDI.H, and is a rather contorted mapping of the OpenGL LogicOp encodings. + However, this field was defined such that, when the 4 bits are replicated to 8 bits, they coincide with the + ROP codes used in the Blter. Note: if the Logic Op Function does not depend on “D”, the dest buffer is + not read. + Value Name Description Project + 0h LOGICOP_CLEAR BLACK; all 0’s All + 1h LOGICOP_NOR NOTMERGEPEN; NOT (S OR D) All + 2h LOGICOP_AND_INVERTED MASKNOTPEN; (NOT S) AND D All + 3h LOGICOP_COPY_INVERTED NOTCOPYPEN; NOT S All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 370 + BLEND_STATE + 4h LOGICOP_AND_REVERSE MASKPENNOT; S AND NOT D All + 5h LOGICOP_INVERT NOT; NOT D All + 6h LOGICOP_XOR XORPEN; S XOR D All + 7h LOGICOP_NAND NOTMASKPEN; NOT (S AND D) All + 8h LOGICOP_AND MASKPEN; S AND D All + 9h LOGICOP_EQUIV NOTXORPEN; NOT (S XOR D) All + Ah LOGICOP_NOOP NOP; D All + Bh LOGICOP_OR_INVERTED MERGENOTPEN; (NOT S) OR D All + Ch LOGICOP_COPY COPYPEN; S All + Dh LOGICOP_OR_REVERSE MERGEPENNOT; S OR NOT D All + Eh LOGICOP_OR MERGEPEN; S OR D All + Fh LOGICOP_SET WHITE; all 1’s All + 17 Reserved + Project: All + Format: MBZ + 16 Alpha Test Enable + Project: All + Format: Enable + Enables the AlphaTest function of the Pixel Processing pipeline. + Programming Notes Project + Alpha Test can only be enabled if Pixel Shader outputs a float alpha value. Alpha Test is + applied independently on each render target by comparing that render target’s alpha value + against the alpha reference value. If the alpha test fails, the corresponding pixel write will be + supressed only for that render target. The depth/stencil update will occur if alpha test passes + for any render target. + When Alpha Test is disabled, Alpha Test Function must be COMPAREFUNCTION_ALWAYS. + 15:13 Alpha Test Function + Project: All + Format: 3D_CompareFunction + This field specifies the comparison function used in the AlphaTest function + Value Name Description Project + 0h COMPAREFUNCTION_ALWAYS Always pass All + 1h COMPAREFUNCTION_NEVER Never pass All + 2h COMPAREFUNCTION_LESS Pass if the value is less than the reference All + 3h COMPAREFUNCTION_EQUAL Pass if the value is equal to the reference All + 4h COMPAREFUNCTION_LEQUAL Pass if the value is less than or equal to the All + reference + 5h COMPAREFUNCTION_GREATER Pass if the value is greater than the reference All + 6h COMPAREFUNCTION_NOTEQUAL Pass if the value is not equal to the reference All + 7h COMPAREFUNCTION_GEQUAL Pass if the value is greater than or equal to the All + reference + 12 Color Dither Enable + Project: All + Format: Enable + Enables dithering of colors (including any alpha component) before they are written to the Color Buffer. + + 11:10 X Dither Offset + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 371 + BLEND_STATE + Format: U2 + Specifies offset to apply to pixel X coordinate LSBs when accessing dither table. + + 9:8 Y Dither Offset + Project: All + Format: U2 + Specifies offset to apply to pixel Y coordinate LSBs when accessing dither table. + + 7:4 Reserved + Project: All + Format: MBZ + 3:2 Color Clamp Range + Project: All + Specifies the clamped range used in Pre-Blend and Post-Blend Color Clamp functions if one or both of + those functions are enabled. Note that this range selection is shared between those functions. This + field is ignored if both of the Color Clamp Enables are disabled + Value Name Description Project + 0 COLORCLAMP_UNORM Clamp Range [0,1] All + 1 COLORCLAMP_SNORM Clamp Range [-1,1] All + 2 COLORCLAMP_RTFORMAT Clamp to the range of the RT surface format (Note: The All + Alpha component is clamped to FLOAT16 for + R11G11B10_FLOAT format). + 3 Reserved Reserved All + 1 Pre-Blend Color Clamp Enable + Project: All + Format: Enable + This field specifies whether the source, destination and constant color channels are clamped prior to + blending, regardless of whether blending is enabled.If DISABLED, no clamping is performed prior to + blending.If ENABLED, all inputs to the blend function are clamped prior to the blend to the range + specified by Color Clamp Range. + Value Name Description Project + 0 Disabled No clamping is performed prior to blending. All + 1 Enabled All inputs to the blend function are clamped prior to the blend to the range All + specified by Color Clamp Range. + + + Programming Notes + See table in Pre-Blending Color Clamp subsection for programming restrictions as a function of RT + format. This field is ignored (treated as DISABLED) for UINT and SINT RT surface formats. Blending is + not supported for those RT surface formats. The device will automatically clamp source color channels + to the respective RT surface range. + 0 Post-Blend Color Clamp Enable + Project: All + Format: Enable + If blending is enabled, this field specifies whether the blending output channels are first clamped to the + range specified by Color Clamp Range. Regardless of whether this clamping is enabled, the blending + output channels will be clamped to the RT surface format just prior to being written. + Programming Notes + See table in Pre-Blending Color Clamp subsection for programming restrictions as a function of RT + format. This field is ignored (treated as DISABLED) for UINT and SINT RT surface formats. Blending is + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 372 + BLEND_STATE + not supported for those RT surface formats. The device will automatically clamp source color channels + to the respective RT surface range. + + + +Programming Note: CC Unit also receives 3DSTATE_WM_HZ_OP and 3DSTATE_PS_EXTRA. + + +Description AlphaTestEnable +Formula + = BLEND_STATE::AlphaTestEnable && + !3DSTATE_WM_HZ_OP::DepthBufferResolveEnable && + !3DSTATE_WM_HZ_OP::DepthBufferClear && + !3DSTATE_WM_HZ_OP::StencilBufferClear + + + + +Description AlphaToCoverageEnable +Formula + = BLEND_STATE::AlphaToCoverageEnable && + !3DSTATE_PS_EXTRA::PixelShaderDisableAlphaToCoverage + + + +12.2.4 CC_VIEWPORT + + CC_VIEWPORT + +Default Value: 0x00000000, 0x00000000 +The viewport state is stored as an array of up to 16 elements, each of which contains the DWords described here. +The start of each element is spaced 2 DWords apart. The first element of the viewport state array is aligned to a 32- +byte boundary.The Minimum Depth field in CC_Viewport state must be be greater than or equal to zero on +D16_UNORM, D24_UNORM_X8_UINT, or D24_UNORM_S8_UINT depth formats + DWord Bit Description +0 31:0 Minimum Depth + Project: All + Format: IEEE_Float + Indicates the minimum depth. The interpolated or computed depth is clamped to this value prior to + the depth test. + +1 31:0 Maximum Depth + Project: All + Format: IEEE_Float + Indicates the maximum depth. The interpolated or computed depth is clamped to this value prior to + the depth test. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 373 + 12.3 Other Pixel Pipeline Functions + +12.3.1 Statistics Gathering +If Statistics Enable is set in 3DSTATE_WM, the PS_DEPTH_COUNT register (see Memory Interface +Registers in Volume Ia, GPU) will be incremented once for each pixel (or sample) that passes the depth, +stencil and alpha tests. Note that each of these tests is treated as passing if disabled. This count is +accurate regardless of whether Early Depth Test Enable is set. In order to obtain the value from this +register at a deterministic place in the primitive stream without flushing the pipeline, however, the +PIPE_CONTROL command must be used. See the 3D Pipeline chapter in this volume for details on +PIPE_CONTROL. + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 374 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V2 Pt 1 – 05 12 6/21/2012 375 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol2_part2.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol2_part2.txt new file mode 100644 index 0000000..738174b --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol2_part2.txt @@ -0,0 +1,3652 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 2 Part 2: Media and General Purpose +Pipeline +(Ivy Bridge) + + + ® +For the 2012 Intel Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S +TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY +WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO +SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO +FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY +PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. + +A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly +or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 + Contents +1. Media and General Purpose Pipeline .................................................................................................. 4 + 1.1 Introduction .......................................................................................................................................... 4 + 1.1.1 Terminologies ................................................................................................................................. 4 + 1.1.2 Hardware Feature Map in Products ............................................................................................... 5 + 1.2 Media Pipeline Overview...................................................................................................................... 6 + 1.2.1 GPGPU Media Pipe Differences .................................................................................................... 7 + 1.3 Programming Media Pipeline ............................................................................................................... 8 + 1.3.1 Command Sequence ...................................................................................................................... 8 + 1.3.2 Interrupt Latency ........................................................................................................................... 10 + 1.3.3 Programming the GPGPU Pipeline .............................................................................................. 10 + 1.3.4 GPGPU Indirect Thread Dispatch ................................................................................................ 11 + 1.3.5 GPGPU Context Switch ................................................................................................................ 12 + 1.3.6 Media GPGPU Payload Limitations.............................................................................................. 13 + 1.3.7 Synchronization of the Media/GPGPU Pipeline ........................................................................... 14 + 1.4 Video Front End Unit .......................................................................................................................... 14 + 1.4.1 Interfaces ...................................................................................................................................... 15 + 1.4.2 Mode of Operations ...................................................................................................................... 16 + 1.4.3 Parameterized Media Walker ....................................................................................................... 24 + 1.5 Thread Spawner Unit ......................................................................................................................... 32 + 1.5.1 Basic Functions ............................................................................................................................ 33 + 1.5.2 Interfaces ...................................................................................................................................... 39 + 1.6 Media State Model ............................................................................................................................. 39 + 1.7 Media Messages ................................................................................................................................ 40 + 1.7.1 Thread Payload Messages ........................................................................................................... 40 + 1.7.2 Thread Spawn Message ............................................................................................................... 47 + 1.8 Media State and Primitive Commands............................................................................................... 50 + 1.8.1 MEDIA_VFE_STATE Command .................................................................................................. 50 + 1.8.2 MEDIA_CURBE_LOAD ................................................................................................................ 55 + 1.8.3 MEDIA_INTERFACE_DESCRIPTOR_LOAD Command ............................................................ 57 + 1.8.4 INTERFACE_DESCRIPTOR_DATA ............................................................................................ 58 + 1.8.5 MEDIA_STATE_FLUSH command .............................................................................................. 61 + 1.8.6 MEDIA_OBJECT Command ........................................................................................................ 64 + 1.8.7 MEDIA_OBJECT_PRT Command ............................................................................................... 67 + 1.8.8 MEDIA_OBJECT_WALKER Command ....................................................................................... 69 + 1.8.9 GPGPU_OBJECT ........................................................................................................................ 75 + 1.8.10 GPGPU_WALKER Command .................................................................................................... 77 + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 3 + 1. Media and General Purpose Pipeline +1.1 Introduction +This section covers the programming details for the media (general purpose) fixed function pipeline. The +media pipeline is positioned in parallel with the 3D fixed function pipeline. It provides media +functionalities and has media specific fixed function capability. However, the fixed functions are designed +to have the general capability of controlling the shared functions and resources, feeding generic threads +to the Execution Units to be executed, and interacting with these generic threads during run time. The +media pipeline can be used for non-media applications, and therefore, can also be referred to as the +general purpose pipeline. For the rest of this chapter, we refer to this fixed function pipeline as the +media pipeline, keeping in mind its general purpose capability. +Concurrency of the media pipeline and the 3D pipeline is not supported. In other words, only one pipeline +can be activated at a given time. Switching between the two pipelines within a single context is supported +using the MI_PIPELINE_SELECT command. +Following are some media application examples that can be mapped onto the media pipeline. All these +applications are functional; however, the level of performance that can be achieved depends on the +hardware configuration and is beyond the scope of this document. + +  MPEG-2 decode acceleration with HWMC (e.g. DXVA HWMC interface) +  MPEG-2 decode acceleration with IS/IDCT and forward (e.g. DXVA IDCT interface) +  MPEG-2 decode acceleration with VLD and forward (e.g. DXVA VLD interface) +  AVC decode acceleration with HWMC and forward including Loop Filter +  AVC decode acceleration with IT and forward including Loop Filter (with hardware IT) +  VC1 decode acceleration with HWMC and forward including Loop Filter +  VC1 decode acceleration with IT and forward including Loop Filter (with hardware IT and overlap + filter) +  Advanced deinterlace filter (motion detected or motion compensated deinterlace filter) +  Video encode acceleration (with various level of hardware assistant) + + +1.1.1 Terminologies +AVC Advanced Video Coding. An international video coding standard jointly + developed by MPEG and ITU. It is also known as H.264 (ITU), or MPEG-4 Part + 10 (MPEG). +Child Thread A thread corresponding to a leaf-node or a branch-node in a thread generation + hierarchy. All thread originated from kernels running on the execution units are + child threads. +EOB End of Block. It is a 1-bit flag in the non-zero DCT coefficient data structure + indicating the end of an 8x8 block in a DCT coefficient data buffer. +IDCT Inverse Discrete Cosine Transform. It is the stage in the video decoding pipe + between IQ and MC. +ILDB In-loop Deblocking Filter – the deblocking filter operation in the decoding loop. It + is a stage after MC in the video decoding pipe. +IQ Inverse Quantization. It is a stage in the video decoding pipe between IS and + IDCT. + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 4 + IS Inverse Scan. It is a stage in the video decoding pipe between VLD and IQ. In + this stage, a sequence of none-zero DCT coefficients are converted into a block + (e.g. an 8x8 block) of coefficients. VFE unit has fixed functions to support IS. +IT Inverse Integer Transform. It is the stage in AVC or VC1 video decoding pipe + between IQ and MC. +MPEG Motion Picture Expert Group. MPEG is the international standard body + JTC1/SC29/WG11 under ISO/IEC that has defined audio and video + compression standards such as MPEG-1, MPEG-2, and MPEG-4, etc. +MC Motion Compensation. It is part of the video decoding pipe. +MVFS Motion Vector Field Selection – a four-bit field selecting reference fields for the + motion vectors of the current macroblock. +PRT A persistent root thread in general stays in the system for a long period of time. + It is normally a parent thread. Only one PRT is allowed in the system. + Hardware is responsible of re-dispatching the incomplete PRT at context + restore, and a PRT can continue operations from that previously left-over state. +Parent Thread A thread corresponding to a root-node or a branch-node in thread generation + hierarchy. A parent thread may be a root thread or a child thread depending on + its position in the thread generation hierarchy. +Root Thread A thread corresponding to a root-node in a thread generation hierarchy. In the + general-purpose pipeline, all threads originated from VFE unit are root threads. +Synchronized Root Thread A root thread that is dispatched by TS upon a ‘dispatch root thread’ message. +TS Thread Spawner. It is the second (and the last) fixed function in the general- + purpose pipeline. +Unsynchronized Root Thread A root thread that is automatically dispatched by TS. +VFE Video Front End. It is the first fixed function in the general-purpose pipeline. +VLD Variable Length Decode. It is the first stage of the video decoding pipe that + consists mainly of bit-wide operations. The architecture supports hardware + MPEG-2 VLD acceleration in the VFE fixed function stage. + + +1.1.2 Hardware Feature Map in Products +The following table lists the hardware features in the media pipe. + +Video Front End Features in Device Hardware + + Features + + Generic Mode + Y + + Root Threads + Y + + Parent/Child Threads + Y + +SRT (Synchronized Root Threads) + Y + + PRT (Persistent Root Thread) + Y + + Interface Descriptor Remapping + N + IS Mode (HW Inverse Scan) + N + VLD Mode (HW MPEG2 VLD) + N + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 5 + Features + + AVC MC Mode + N + AVC IT Mode (HW AVC IT) + N + + AVC ILDB Filter (in Data Port) + N + VC1 MC Mode + N + VC1 IT Mode (HW VC1 IT) + N + Stalling HW Scoreboard + Y + + Non-stalling HW Scoreboard + Y + + HW Walker + Y + + HW Timer + Y + + Pipelined State Flush + Y + + HW Barrier + Y + + + +1.2 Media Pipeline Overview +The media (general purpose) pipeline consists of two fixed function units: Video Front End (VFE) unit and +Thread Spawner (TS) unit. VFE unit interfaces with the Command Streamer (CS), writes thread payload +data into the Unified Return Buffer (URB), and prepares threads to be dispatched through TS unit. VFE +unit also contains a hardware Variable Length Decode (VLD) engine for MPEG-2 video decode. TS unit is +the only unit of the media pipeline that interfaces to the Thread Dispatcher (TD) unit for new thread +generation. It is responsible for spawning root threads (short for the root-node parent threads) originated +from VFE unit and for spawning child threads (can be either a leaf-node child thread or a branch-node +parent thread) originated from the Execution Units (EU) by a parent thread (can be a root-node or a +branch-node parent thread). +The fixed functions, VFE and TS, in the media pipeline, in most cases, share the same basic building +blocks as the fixed functions in the 3D pipeline. However, there are some unique features in media fixed +functions as highlighted by the followings. + +  VFE manages URB and only has write access to URB; TS does not interface to URB. +  When URB Constant Buffer is enabled, VFE forwards TS the URB Handler for the URB Constant + Buffer received from CS. +  TS interfaces to TD; VFE does not. +  TS can have a message directed to it like other shared functions (and thus TS has a shared function + ID), and it does not snoop the Output Bus as some other fixed functions in the 3D pipeline do. +  A root thread generated by the media pipeline can only have up to one URB return handle. +  If a root thread has a URB return handle, VFE creates the URB handle for the payload to initiating + the root thread and also passes it alone to the root thread as the return handle. The root thread then + uses the same URB handle for child thread generation. + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 6 +  If URB Constant Buffer is enabled and an interface descriptor indicates that it is also used for the + kernel, TS requests TD to load constant data directly to the thread’s register space. For root thread, + constant data are loaded after R0 and before the data from the other URB handle. For child thread, + as the R0 header is provided by the parent thread, Thread Spawner splits the URB handles from the + parent thread into two and inserts the constant data after the R0 header. +  A root thread must terminate with a message to TS. A child thread should also terminate with a + message to TS. +  High streaming performance of indirect media object load is achieved by utilizing the large vertex + cache available in the Vertex Fetch unit (of the 3D pipeline). + +Top level block diagram of the Media Pipeline + + + + +1.2.1 GPGPU Media Pipe Differences +You can access the GPGPU pipe with the GPGPU_OBJECT and GPGPU_WALKER commands. A +thread group id is associated with every dispatch, which is used to allocate and track barriers and Shared +Local Memory. The GPGPU pipe has access to all the shared functions. The GPGPU pipe does not use +the Scoreboard and should not dispatch child threads. +You can access the Media pipe with the various MEDIA_OBJECT* commands. Barriers and Shared Local +Memory are not allocated for them. All shared functions are available. The Scoreboard is available to +control dispatch depending on the completion of neighboring blocks. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 7 + 1.3 Programming Media Pipeline + +1.3.1 Command Sequence +Media pipeline uses a simple programming model. Unlike the 3D pipeline, it does not support pipelined +state changes. Any state change requires an MI_FLUSH or PIPE_CONTROL command. When +programming the media pipeline, it should be cautious to not use the pipelining capability of the +commands described in the Graphics Processing Engine chapter. +To emphasize the non-pipeline nature of the media pipeline programming model, the programmer should +note that if any one command is issued in the “Primitive Command” step, none of the state commands +described in the previous steps cannot be issued without preceding with a MI_FLUSH or +PIPE_CONTROL command. +With the addition of MEDIA_STATE_FLUSH command, pipelined state changes are allowed on the +media pipeline. The MEDIA_STATE_FLUSH serves as a fence for state change by flushing the VFE/TS +front ends but not waiting for threads to retire. +The basic steps in programming the media pipeline are listed below. Some of the steps are optional; +however, the order must be followed strictly. Some usage restrictions are highlighted for illustration +purpose. For details, refer to the respective chapters for these commands. + +1.3.1.1 Command Sequence +For, the media pipeline is further simplified with fixed functions like MPEG2 VLD and AVC/VC1 IT +removed. The addition includes (1) CURBE command is now unique to the media pipeline and (2) the +interface descriptors are delivered directly as a media state command instead of being loaded through +indirect state. +The programming model is listed as the following. + +  Step1: MI_FLUSH/PIPE_CONTROL + o This step is mandatory. + o Multiple such commands in step 1 are allowed, but not recommended for performance + reason. + +  Step2: State command PIPELINE_ SELECT + o This step is optional. This command can be omitted if it is known that within the same + context media pipeline was selected before Step 1. + o Multiple such commands in step 2 are allowed, but not recommended for performance + reason. + +  Step3: State commands configuring pipeline states + o STATE_BASE_ADDRESS +  This command is mandatory for this step (i.e. at least one). +  Multiple such commands in this step are allowed. The last one overwrites + previous ones. +  This command must precede any other state commands below. +  Particularly, the fields Indirect Object Base Address and Indirect Object + Access Upper Bound are used to control indirect Media object load in VF. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 8 +  The fields Dynamics Base Address and Dynamics Base Access Upper + Bound are used to control indirect Curbe and Interface Descriptor object load + in VF. +  Note: This command may be inserted before (and after) any commands listed + in the previous steps (Step 1 to 3). For example, this command may be placed + in the ring buffer while the others are put in a batch buffer. + o STATE_SIP +  This command is optional for this step. It is only required when SIP is used by + the kernels. + o MEDIA_VFE_STATE +  This command is mandatory for this step (i.e. at least one). +  This command cause destruction of all outstanding URB handles in the + system. A new set of URB handles will be generated based on state + parameters, no. of URB and URB length, programmed in VFE FF state. +  Multiple such commands in this step are allowed. The last one overwrites + previous ones. + o MEDIA_CURBE_LOAD +  This command is optional. +  Multiple such commands in this step are allowed. The last one overwrites + previous ones. + o MEDIA_INTERFACE_DESCRIPTOR_LOAD +  This command is mandatory for this step (i.e. at least one). +  Multiple such commands in this step are allowed. The last one overwrites + previous ones. + +  Step4: Primitive commands + o MEDIA_OBJECT +  This step is optional, but it doesn’t make practical sense not issuing media + primitive commands after being through previous steps to set up the media + pipeline. +  Multiple such commands in step 4 can be issued to continue processing + media primitives. + +With the addition of MEDIA_STATE_FLUSH command, pipelined state changes are allowed on the +media pipeline. In order to support context switch for barrier groups, watermark and barrier dependencies +are added to the MEDIA_STATE_FLUSH command. The usage of barrier group may have strict +restriction that all threads belonging to a barrier group must all be present in order to avoid deadlock +during context switch. Here are the example programming sequences to allow context switch. Note that +the use of MEDIA_OBJECT_PRT and MI_ARB_ON_OFF are optional. + +  MEDIA_VFE_STATE +  MEDIA_INTERFACE_DESCRIPTOR_LOAD +  MEDIA_CURBE_LOAD (optional) +  MEDIA_GATEWAY_STATE (for example for barrier group 1) + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 9 +  MEDIA_OBJECT_PRT (with VFE_STATE_FLUSH set and PRT NEEDED set.) +  MEDIA_STATE_FLUSH (with watermark set for group 1) +  MI_ARB_ON_OFF (OFF)// Arbitration must be turned off while sending objects for group 1 +  Several MEDIA_OBJECT command (for barrier group 1) +  MI_ARB_ON_OFF (ON)// Arbitration is allowed +  MEDIA_STATE_FLUSH (optional, only if barrier dependency is needed) +  MEDIA_INTERFACE_DESCRIPTOR_LOAD (optional) +  MEDIA_CURBE_LOAD (optional) +  MEDIA_GATEWAY_STATE (for example for barrier group 2) +  MEDIA_STATE_FLUSH (with watermark set for group 1) +  MI_ARB_ON_OFF (OFF)// Arbitration must be turned off while sending objects for group 2 +  Several MEDIA_OBJECT command (for barrier group 2) +  MI_ARB_ON_OFF (ON)// Arbitration is allowed +  … +  MI_FLUSH + +Commands for the GPGPU pipe (GPGPU_OBJECT and GPGPU_WALKER) should be separated from +commands for the Media pipe (MEDIA_OBJECT*) by an MI_FLUSH. + + +1.3.2 Interrupt Latency +Command Streamer is capable of context switching between primitive commands. +For all independent threads, it is not much a problem. The interrupt latency is dictated by the longest +command that is likely to have the largest number of threads. For VLD mode, such a command may be +corresponding to a largest slice in a high definition video frame. This is application dependent, there are +not much host software can do. For Generic mode, programmer should consider to constrain the compute +workload size of each thread. +In modes with child threads, a root thread may persist in the system for long period of time – staying until +its child threads are all created and terminated. Therefore, the corresponding primitive command may +also last for long time. The Software designer should partition the workload to restrict the duration of each +root thread. For example, this may be achieved by partitioning a video frame and assigning separate +primitive commands for different data partitions. +In modes with synchronized root threads, a synchronized root thread is dependent on a previous root or +child thread. This means context switch is not allowed between the primitive command for the +synchronized root thread and the one for the depending thread. So no command queue arbitration should +be allowed between them. Software designer should also restrict the duration of such non-interruptible +primitive command segments. + + +1.3.3 Programming the GPGPU Pipeline + 1. In MEDIA_VFE_STATE choose whether to set DW2.6 Bypass Gateway Control. Usually this + will be set, allowing the gateway to be used without OpenGateway/CloseGateway. + 2. Set up interface descriptor with # of threads in barrier. The barrier id is not specified here + because can Gen7 automatically assigns barriers to thread groups when they are free. The + amount of CURBE data to deliver per thread dispatch is set in the interface descriptor. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 10 + 3. Set up CURBE with thread ids and common data for all thread dispatches in the thread group. + 4. Set up a GPGPU_WALKER command or a set of GPGPU_OBJECT commands with the + thread group ids to dispatch the threads. The CURBE data is sent in sections for each thread + dispatch in the thread group; a new thread group starts sending the CURBE data from the + beginning of the buffer. +Note: Gen7 can either have the barriers and SLM automatically managed by hardware or specified by +software. Mixing software managed and hardware managed in the same set of threads is allowed, but +may cause stalls if there is an allocation conflict. +Note: When using GPGPU_OBJECT, finish dispatching a thread group before starting a different one. +The kernel should handle the barriers as follows: +The BarrierMsg message contains the barrier id and a way to reprogram the barrier count. The barrier +count reprogram is not normally used for GPGPU workloads. When all threads in the group have reached +the barrier, the gateway returns a notification bit 0. +The kernel must wait for the barrier to finish with a WAIT N0. + + +1.3.4 GPGPU Indirect Thread Dispatch +Indirect thread dispatch allows one thread group to control the group size of a following thread group. +This is the sequence of commands in the ring buffer: +GPGPU_OBJECT/WALKER // Either a set of objects or a walker to dispatch a thread group which will write the + next groups properties to memory +MI_FLUSH // Make sure the thread group has finished executing +MEDIA_CURBE_LOAD // Load the thread ids for new group + // Load the indirect MMIO GPGPU registers from the mem written by the previous +MI_LOAD_REGISTER_MEMORY group +GPGPU_WALKER (indirect) // A walker with the indirect bit set. + +The first thread group writes this data to memory: + 1) The thread ids delivered in the CURBE - written where the following MEDIA_CURBE_LOAD + will read them. + 2) The GPGPU_WALKER parameters are written to memory where the + MI_LOAD_REGISTER_MEMORY will read them. + a. GPGPU_DISPATCHDIMX - the X dimension of the number of thread groups to dispatch in + dword 4. + b. GPGPU_DISPATCHDIMY - the Y dimension of the number of thread groups to dispatch in + dword 6. + c. GPGPU_DISPATCHDIMZ - the Z dimension of the number of thread groups to dispatch in + dword 8. +See vol1c Memory Interface and Command Stream for the MMIO register addresses and formats. + The indirect registers are not supposed to be set to 0, but sometimes the kernel computing the value +wants no work done and sets them to 0. This does not work correctly, so a work-around in the command +stream is needed: +GPGPU_WALKER // The thread group which writes the indirect values to memory locations +MI_CONDITIONAL_BATCH_BUFFER_END DIMX 0 // End batch buffer if X dim in memory = 0 +MI_CONDITIONAL_BATCH_BUFFER_END DIMY 0 // End batch buffer if Y dim in memory = 0 + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 11 + MI_CONDITIONAL_BATCH_BUFFER_END DIMZ 0 // End batch buffer if Z dim in memory = 0 +MI_LOAD_REGISTER_MEM GPGPU_DISPATCHDIMX DIMX // Normal load of register from memory +MI_LOAD_REGISTER_MEM GPGPU_DISPATCHDIMY DIMY +MI_LOAD_REGISTER_MEM GPGPU_DISPATCHDIMZ DIMZ +GPGPU_WALKER // The thread groups which depend on the indirect dimensions + + +1.3.5 GPGPU Context Switch +The GPGPU pipeline supports interruption of GPGPU workloads on thread group boundaries. This is +needed for GPGPU workloads that are so large that there is a risk of the display becoming n on- +responsive if the work cannot be interrupted for other jobs. +A workload is interrupted with the MI_ARB_CHECK command with the UHPTR register. The +MI_ARB_CHECK command is placed throughout the command buffer. The driver updates the UHPTR +register when a new context is needed; MI_ARB_CHECK checks for this and reprograms the head and +tail pointers to the new batch of commands. The driver waits for the pre-emption to occur without going +into RS2. +The GPGPU needs to modify this to allow a GPGPU_WALKER command to be interrupted. This is done +by following each GPGPU_WALKER command with a MEDIA_STATE_FLUSH. This causes the CS to +stop fetching commands until either the command completes or until the UHPTR valid bit is set. +GPGPU workloads can be dispatched with either GPGPU_OBJECT commands or GPGPU_WALKER +commands. In the case of GPGPU_OJBECT, the MEDIA_STATE_FLUSH/ MI_ARB_CHECK pair must +be placed in the batch buffer at thread group boundaries, since preemption cannot occur with a thread +group partially dispatched. GPGPU_WALKER commands can dispatch multiple thread groups, in this +case the MEDIA_STATE_FLUSH/ MI_ARB_CHECK follows each GPGPU_WALKER and the hardware +takes care of noticing the UHPTR update and stopping at the next thread group boundary. +The commands in the batch buffer will look something like this: + Command Ring Comments +MI_SET_CONTEXT Go to GPGPU context +MI_BATCH_BUFFER_START If new context, set address to top of batch. Otherwise, address needs to be set to the + command preempted (given in the HWSP). + + + Command Batch Comments +GPGPU_OBJECT +GPGPU_OBJECT +... (more threads forming a complete thread group) +MEDIA_STATE_FLUSH Check for preemption at thread group boundary. “Preemption” defined by the UHPTR valid + bit set. +MI_ARB_CHECK Move the head only if UHPTR valid bit is set. +… +GPGPU_WALKER +MEDIA_STATE_FLUSH Check for preemption at thread group boundary internal to GPGPU_WALKER command. + “Preemption” defined by the UHPTR valid bit set. +MI_ARB_CHECK Move the head only if UHPTR valid bit is set. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 12 + The context saved will consist of the state commands for VFE and a modified GPGPU_WALKER +command with a new starting thread group id. On context restore, the commands are executed to start +the GPGPU_WALKER where it left off before continuing with the rest of the command buffer. +An example software model for starting a preemption goes like this: +1. The UHPTR is reprogrammed to point to the current tail of the ring buffer. +2. Insert new commands: + a. LRI to UHPTR to clear valid. + b. Store Register to mem the preempted batch offset. + c. Store Register to mem the preempted ring offset. + d. Pipe_control notification. + e. An MI_SET_CONTEXT to the new context is put into the ring. +3. Insert commands for new context. i.e. batch buffers. +4. Update Tail Pointer. +Note: 2-3 items above could happen during execution of a thread group so the HW may see the tail +pointer updated before preemption starts. +Note: The driver needs to turn off RC6 during items 1 and 4. + + +1.3.6 Media GPGPU Payload Limitations +There are 3 types of payload that the media/GPGPU instructions can have, but not all of them are +allowed. The following table lists the legal combinations: + WorkLoad Commands Data Stored +GPGPU GPGPU_WALKER CURBE + GPGPU_WALKER INDIRECT + GPGPU_OBJECT CURBE +Media(Legacy) Media_Object CURBE + Media_Object INDIRECT + Media_Object INLINE + Media_Object CURBE+INLINE + Media_Object CURBE+INDIRECT + Media_Object INLINE+INDIRECT + Media_Object CURBE+ INLINE+INDIRECT + Media_Object_Walker CURBE + Media_Object_Walker INLINE + Media_Object_Walker CURBE+INLINE +Media using Barrier/SLM Media_Object_GRPID CURBE + Media_Object_GRPID INDIRECT + Media_Object_GRPID INLINE + Media_Object_Walker (with group id) CURBE + Media_Object_Walker (with group id) INLINE + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 13 + 1.3.7 Synchronization of the Media/GPGPU Pipeline +The Media/GPGPU Pipeline is synchronized in the same way as the 3D pipeline using the +PIPE_CONTROL command. +See the Bspec section on 3d pipe synchronization: vol2a 3D Pipeline - Overview [SNB+] > 3D Pipeline > +Synchronization of the 3D Pipeline. + + +1.4 Video Front End Unit +The Video Front End unit is the first fixed function unit in the media pipeline. It processes +MEDIA_OBJECT commands to generate root threads by preparing the control (including interface +descriptor pointers) and payload (data pushed into the GRF) for the root threads. +VFE supports three modes of operation: Generic mode, Inverse Scan mode and VLD mode. + +  Generic mode: In the Generic mode, VFE serves as a conduit for general-purpose kernels fully + configured by the host software. There is no application specific hardware enabled in this mode. +  IS (Inverse Scan) mode: The IS mode is a special mode for video decoding when off-host IDCT + acceleration is supported by kernels running on execution units. +  VLD mode: It is a special mode for video decoding when MPEG-2 off-host VLD acceleration is + supported by hardware. +  AVC-IT (AVC Inverse Integer Transform) mode: The AVC-IT mode is a special mode for AVC + video decoding when off-host IDCT acceleration is supported by VFE hardware and MC and Loop + Filter are supported by kernels running on execution units. +  AVC-MC (AVC Motion Compensation) mode: The AVC-MC mode is a special mode for AVC video + decoding with host-based IDCT and MC and Loop Filter are supported by kernels running on + execution units. +  VC1-IT (VC1 Inverse Integer Transform) mode: The VC1-IT mode is a special mode for VC1 + video decoding when off-host IDCT acceleration is supported by VFE hardware and MC and Loop + Filter are supported by kernels running on execution units. + +The following figure illustrates the three modes of operation. The details can be found in the rest of the +sections. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 14 + VFE Functional Blocks and Modes of Operations + + + + +MEDIA_STATE_POINTERS command configures VFE in one of the three modes using. Mode switching +requires media pipeline state change. + + +1.4.1 Interfaces +VFE unit acquires its states from Sate Variable Manager, accesses URB handles from the Global URB +Manager, receives state and primitive commands from CS unit, writes thread payloads to URB, and +sends new thread to TS unit. It does not directly interface to Thread Dispatcher. When VFE is ready for a +thread, it sends the interface descriptor pointer for the thread to TS. + +1.4.1.1 Interface to Command Streamer +VFE interfaces to CS to acquire the control data, inline data and indirect data of MEDIA_OBJECT +commands. The interface supports the throughput of a given mode of operation of VFE. For example, in +VLD mode and IS mode, VFE consumes one dword at a time, one dword to the variable length decoder +or one dword to the inverse-scan operator. In Generic mode, VFE is capable of a much higher throughput +to push indirect data (as thread payload data) into URB. As throughput for indirect data is much higher +than that of inline data, when large amount of user data need to be passed through VFE unit, if +applicable, it is encouraged to use indirect object load. + +1.4.1.2 Interface to Thread Spawner +VFE also transmits scratch memory base address received from State Variable Manager to TS, and +passes on the Constant URB handle received from CS. +VFE receives URB handle dereference signal from TS. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 15 + 1.4.1.3 Interface to State Variable Manager +State Variable Manager is responsible of fetching media state structure from memory. VFE only acquires +its state variable upon the first primitive command. Therefore, host software is allowed to change media +states before issuing primitive commands. As media pipeline does not support pipelined state change, a +pipeline flush is required before any state change to make sure that there are no outstanding primitive +commands in the pipeline. + +1.4.1.4 Interface to Global URB Manager +VFE is responsible for managing URB handles for all root threads. Upon state change, VFE allocates +URB handles through the Global URB Manager. VFE manages the URB handles in a circular buffer. URB +handle referencing is in a strict order (taking from the head of the circular buffer), even though the handle +dereferencing may occur out of order. +When starting a root thread, VFE reference one and only one URB handle, forwarding it to TS. TS then +forwards this handle to TD for thread dispatching. +The URB handle for a root thread is used in two ways: (1) serving as buffer space for VFE to assemble +thread payload, and (2) serving as the return URB buffer for the root thread to assemble child threads and +their payload. +TS sends an indication to VFE when it is safe to dereference the URB handle, and VFE dereferences it. +After a URB handle has been dereferenced, VFE can assign it to a new thread. + +1.4.1.5 Interface to URB +VFE sends the assembled root thread payload to URB via a wide data bus. In Generic mode, the data +comes from the command as inline or indirect data objects. In IS mode, the inline data is directly +assembled as URB register wide payloads, and the indirect data are assembled through the Inverse Scan +logic. In VLD mode, the data is decoded from the indirect object (i.e. bitstream data). + + +1.4.2 Mode of Operations + +1.4.2.1 Generic Mode +In the Generic mode, VFE serves as a conduit for general-purpose kernels fully configured by the host +software. As there is no special fixed function logic used, the Generic mode can also be viewed as a +‘pass-through’ mode. In this mode, VFE generates a new thread for each MEDIA_OBJECT command. +The payload contained in the MEDIA_OBJECT command (inline and/or indirect) is streamed into URB. +The interface descriptor pointer is computed by VFE based on the interface descriptor offset value and +the interface descriptor base pointer stored in the VFE state. VFE then forwards the interface descriptor +pointer and the URB handle to TS to generate a new root thread. Many media processing applications +can be supported using the Generic mode: MPEG-2 HWMC, frame rate conversion, advanced +deinterface filter, to name a few. + +1.4.2.2 Interface Descriptor Selection +After populating the URB with the data, VFE notifies TS to initiate the thread. TS needs an interface +descriptor pointer to fetch the information for thread initiation. A list of interface descriptors is arranged by +the host software as a descriptor array in memory, as shown in the media state model in the Media State +Model Figure. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 16 + VFE obtains the interface descriptor base pointer from the VFE state structure. The offset into the list of +interface descriptors comes from MEDIA_OBJECT command. Each interface descriptor has a fixed size. +VFE uses a multiple of the fixed size and the offset to add to the base pointer, and creates the final +interface descriptor pointer to be sent to TS. +TS fetches the interface descriptor through the Instruction State Cache (ISC) using the interface +descriptor pointer. TS then initializes the thread through the Thread Dispatcher. The interface descriptor +pointer is given to TS by VFE for a root thread and by a thread for a child thread. The R0 header is +formed by TS for a root thread and is stored in URB by the parent thread for a child thread. + +1.4.2.3 Scratch Space Allocation +TS handles the allocation of scratch space. Since TS does not have a normal state interface, VFE +receives the scratch space configuration with the VFE state, then forwards the configuration to TS with +the interface descriptor pointer. + +1.4.2.4 GPGPU Mode +The general purpose (GPGPU) mode allows the Gen7 architecture to be used by general purpose +parallel APIs such as . This is similar to the Generic mode with additional support for automatic +generation of threads, Shared Local Memory and Barriers. + +1.4.2.4.1 Automatic Thread Generation +A single GPGPU job may require thousands or even millions of GPU_OBJECT commands. Rather than +create them separately, it would be better to generate them algorithmically. To do this a +GPGPU_WALKER command is created. +Rather than modifying the Media Walker, a simple Thread Group Walker is created instead: + + + + +The X/Y/Z counters for the thread group will have an initial and maximum value. The thread group id sent +with each dispatch consists of these 3 numbers. These counters are 32-bits since the spec does not give +a limit to the size of the thread id. +The 3 thread counters count the number of dispatches in a single thread group – up to 32 dispatches for +SIMD32 or 64 dispatches for SIMD16/8. There are 3 of them in order to select the execution masks +correctly – see section Execution Masks on execution masks. Each one is 6-bits in order to allow full +flexibility of any dimension going to 64 while the rest do not increment. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 17 + A thread is generated each time one of the thread counters increment. When all the counters reach their +maximum values, the thread group is done and the thread group counter can increment and start a new +thread group. When the thread group X counter reaches its maximum it is reset to 0, and the Y counter is +incremented. +The compiler determines how many SIMD channels are needed per thread group, and then decides how +these will be split among EU threads. The number of threads is programmed in the thread counter, and +the SIMD mode (SIMD8/SIMD16/SIMD32) is specified in the GPGPU_WALKER command. + +1.4.2.4.2 Thread Payload +The payload to each thread dispatched is: + 1. A thread group id which identifies the group the set of threads belong to. This is in the form of + a set of 3, 32-bit X/Y/Z values. + 2. The set of X/Y/Z that form the thread id for each channel. If Z is not used then only X/Y are + needed. + 3. The execution mask which indicates which channels are active. +Thread ids form a 2D or 3D surface which has to be mapped into SIMD32, SIMD16 or SIMD8 dispatches. +Rather than have the hardware force a particular mapping of thread ids to channels, the mapping will be +supplied by the compiler. The VFE will receive a simple count of the number of threads per thread group +which will be used to count the number of dispatches. The thread ids for all threads in a thread group are +put in a constant buffer with the MEDIA_CURBE_LOAD command. A single set of thread ids can be used +repeatedly for all thread groups, since the thread ids are the same for each thread group id output by the +GPGPU_WALKER. +The data required is up to the compiler, but here is an example set of payloads for a 2 Z x 2Y x 12 X and +a SIMD16 dispatch. This thread group requires 3 dispatches: + + + + +In this case the thread counter width would be programmed with a maximum value of 3 (since all the +execution masks are all F, it doesn’t matter how the thread counters are programmed as long as they +count to 3 before finishing the thread group). +The first dispatch would tell the TS (who would tell the TD) that the payload starts at the beginning of the +constant buffer and has a length of 3. The next dispatch would have a payload starting at +constant_buffer_start + 3. The final dispatch payload starts at constant_buffer_start + 6. If there are more +thread groups in the command they would get exactly the same payload – the only difference is the +thread group id (as well as a different barrier and shared local memory space). + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 18 + 1.4.2.4.3 Execution Masks +The number of channels required by the GPGPU job may not evenly fit into the number of SIMD +channels. That can leave some channels idle. The execution mask is used to tell the hardware which +channels are to be used. +A thread group is modeled as a 3D solid with each channel acting as one X/Y/Z point in the solid. This +can take the form of a line with 1024 channels with X from 0 to 1023 and constant Y/Z, a square with X=0 +to 32 and Y=0 to 32, or a cube with X=0 to 9, Y=0 to 9, Z=0 to 9. Software needs to determine how these +shapes are mapped onto the 32 SIMD32 channels per dispatch (or 16 SIM16, etc). The mapping per +thread is assumed to be a 2D square of channels such as 8x4, 16x2, 32x1. Below is a diagram of a 22x6 +thread group that is mapped onto a set of 8x4 SIMD32 channels: + + + + +Note that the dispatches to the top and left have execution masks of all-F, while all the right edge +dispatches have the same execution mask; likewise all the bottom edge dispatches have the same +execution mask. The bottom right is the logical-AND of the right and bottom edge dispatches. +A 32-bit right and bottom mask is sent with the GPGPU_WALKER command, and the thread width, height +and depth counters are used to determine when they are used (width, height and depth are used instead +of X/Y/Z, since it is not required that width = X – width and height are the two variables that are changing +in a single SIMD dispatch even if they are Y and Z). +For each dispatch the width counter is incremented until it reaches the maximum – the dispatch with +width=max will use the right execution mask. The height counter is then incremented and process +repeated. If at any time the height counter = max then the execution mask is the bottom execution mask. +When the height and width counters are both max then the dispatch will be the AND of the right and +bottom and the depth counter will increment. +The same 2Z x 2Y x 12X thread group described above dispatched as SIMD32 with each dispatch +delivering a 16X x 2Y shape would require 2 dispatches with empty bits in the right execution mask and +all F in the bottom. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 19 + The width and height counter would have a maximum of 1, and the depth counter would have a maximum +of 2. The two dispatches would use the AND of the two masks, but since the bottom mask is F it would be +the same as just the right mask. +The execution masks can also be used when the software wants to pack the channels rather than lay +them out in a regular pattern: + + + + +In this case the width counter can have a maximum of 2, and the height and depth counters with a +maximum of 1. The first dispatch will use the bottom mask only (all-F) and the second will use the right +AND bottom mask to remove the channels that are not used. + +1.4.2.4.4 Payload Storage +The MEDIA_CURBE_LOAD constant data is stored in the URB by CS and read out by TDL when the +dispatch occurs. The inline payload with the execution counts is sent to VFE from CS. The execution +counts are stored internal to VFE. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 20 + Only 32 threads are allowed for SIMD32 to match the 1024 thread limit, requiring 32 execution count +bytes, or 8 DW payload. SIMD16 and SIMD8 allow the full 64 thread per half-slice, and so require as +much as 16 DWords. +The X/Y/Z payload size per dispatch is specified in the command, but a maximum size is 3 16-bit +numbers per 1024 SIMD channels, or 6 kbytes. + +1.4.2.4.5 URB Management +The VFE manages the URB in GPGPU and generic/media modes. The first 32 URB entries are reserved +for the interface descriptor, and CURBE data is placed after the IDs. URB handles are needed for indirect +data and parent/child communication; when the VFE starts up it creates up to 64 handles by partitioning +the remaining URB space into evenly spaced addresses and saving the resulting handles in a FIFO. The +handles can then be treated just like ones created by the URBM – send to TD on dispatch and recovered +on the handle return bus. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 21 + MEDIA_VFE_STATE specifies the amount of CURBE space, the URB handle size and the number of +URB handles. The driver must ensure that ((URB_handle_size * URB_num_handle) – CURBE – 32) <= +URB_allocation_in_L3. + +1.4.2.4.6 AVC-Style Dependency Example +For AVD decoding, dependencies for a given macroblock may be set based on the availability of neighbor +macroblocks, namely A, B, C, D and left-bottom neighbors (left-bottom only if MbAff = 1), as well as the +current macroblock’s address, MbAff flag and FieldMbFlag. For a macroblock in a progressive frame +picture or a field picture, one macroblock may depend on up to four neighbors, A, B, C and D as shown in +AVC Style Dependency Example. For a macroblock in a MbAff pair, it may depend on up to three, five or +eight neighbors as shown in AVC Style Dependency Example and AVC Style Dependency Example, +based on the current macroblock’s address and FieldMbFlag. +The neighbor’s availability depends on the corresponding IntraPredAvailFlagA|B|C|D|E flags for the +macroblock (or the macroblock pair). Hardware assumes that the flags are set correctly in the +MEDIA_OBJECT_EX command as shown in Macroblock indices for field picture destination. For +simplicity, the left neighbor pair (A0 and A1) availability for a MbAff macroblock can be determined as a +group by IntraPredAvailFlagA | IntraPredAvailFlagE. For the second macroblock in a ‘frame’ MbAff +pair, it depends on the first macroblock in the pair and it is always available. + +Neighbor addresses of a macroblock in a progressive frame picture (MbAff = 0) or a field picture +with up to 4 dependencies + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 22 + Neighbor addresses of the first macroblock in a MbAff frame picture (MbAff = 1) with up to 8 +dependencies + + + + +Neighbor addresses of the second macroblock in a MbAff frame picture (MbAff = 1) with up to 8 +dependencies + + + + +Neighbor Availability +MbAff FieldMbFlag VertOrigin[0] A B C D LB Comments +0 0/1 0/1 Progressive or Field picture +     +1 0 0 +      1st Frame MbAff macroblock + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 23 + MbAff FieldMbFlag VertOrigin[0] A B C D LB Comments +1 0 1 na 0 na +   2 Frame MbAff macroblock + nd + + + +1 1 0 +      1st Field MbAff macroblock + +1 1 1 +      2nd Field MbAff macroblock + + +1.4.2.5 VC1-Style Dependency Example +For VC1, only one dependency may be set depending on the availability of the upper neighbor +macroblock. + +Macroblock sequence order in a VC-1 picture with WidthInMblk = 5 and HeightInMblk = 6 + + 0 1 2 3 4 + + 0 1 2 3 4 +0 + + 5 6 7 8 9 +1 + + 10 11 12 13 14 +2 + + 15 16 17 18 19 +3 + + 20 21 22 23 24 +4 + + 25 26 27 28 29 +5 + + + +1.4.3 Parameterized Media Walker +The Parameterized Media Walker is a hardware thread generation mechanism that creates threads +associated with units in a generalized 2-dimensional space, for example, blocks in a 2D image. With a +small number of unit step vectors, the walker can implement a large number of walking patterns as +described hereafter. This command may provide functions that are normally handled by the host +software, thus, may be used to simplify the host software and GPU interface. +The walker described herein is doubly nested, where essentially a “local” walker can perform a variety of +2-dimensional walking patterns and a “global” walker can perform similar 2-dimensional walking patterns +upon many local walkers. The local walker has 3 levels (outer, middle, and inner) while the global walker +has 2 levels (outer and inner). Thus, the algorithm has 5-nested loops that modify local state based on +user-defined unit step vectors. +The Walker’s programmability is derived from: + +  The walker traverses a unit-normalized surface. Some example unit sizes: + o 1x1: Walking pixels + o 4x4: Walking sub-blocks + o 16x16: Walking macro-blocks + o 32x16: Walking macro-block-pairs + +  The use of unit step vectors to describe the motion at each of level of nesting + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 24 +  Starting locations for the local and global walkers +  Block sizes of the local and global walker +  And a small number of special mode controls for the inner-most loop which are aimed at efficiently + dividing an image into two balanced workloads for dual-slice designs. + +1.4.3.1 Walker Parameter Description +The global and local loops are both described by the same four parameters: + +  Resolution, +  Starting location, +  Outer unit vector, +  Inner unit vector + +The local inner loop has some special modes that will be described later. A table of the user inputs and +some example values are given below: + + + + +It should be emphasized that the value of what a “unit” represents is implicitly defined by the user. In +other words, the walker traverses a “unit normalized space” that is not inherently bound to pixel walking. If +the smallest unit of work the user wants to walk is a 4x3 block of pixels, you can program the inner loop to +step (4,3) or (1,1): + +  In the first case (4,3) the user is walking in units of pixels +  In the second case (1,1) the user is walking in units of 4x3 blocks of pixels. + +It should be noted that hardware doesn’t contain enough bits for pixel walking for pixel resolution like +1920x1088. The intended usage of the walker is for block walking whereas the block size is not relevant +to the walker parameters. + +1.4.3.2 Basic Parameters for the Local Loop +The local inner and outer loop xy-pair parameters alone can describe a large variety of primitive walking +patterns. Below are 9 primitive walking patterns generated by varying only the inner and outer unit step +vectors of the local loop: + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 25 +  The top row shows the outer unit vector pointing down (+Y) and the inner unit vector pointing right + (+X). Rows and columns can easily be skipped by increasing the unit step vectors above one. +  The middle row the outer unit vector pointing right (+X) and the inner unit vector pointing down (+Y). + Again, rows and columns are skipped by increasing the unit step vectors beyond one. +  The last row shows the capability to walk angles not perpendicular to the edge. The 1 st shows a 45º + walking pattern by setting the inner unit vector to (-1,1). The 2nd shows a checkerboard pattern by + skipping every other outer loop and retaining the inner unit vector of (-1,1). The 3rd shows a 26.5º + walking pattern by setting the inner unit vector to (-2,1). + +The block resolution, shown as [8,8], and the starting location, currently [0,0], can be varied and the +above patterns can be stretched and rotated many ways. The diagram below shows an example of where +the start position and unit step vectors can be set to achieve a full rotation of the same pattern: + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 26 + 1.4.3.3 Dual Mode of Local Loop +The local Inner Loop Special mode selects are included to aid in the distribution of work, specifically with +two slices in mind. Essentially, the local inner loop can be bisected and each half-walk can be directed +inward towards the center of the image (dual). The local inner loop need not be bisected, and can either +move away from the outer loop (repel) or move towards it (attract) when an even split is not desired: + + + + +In Dual mode, the sequence will alternate between two half-walks such that every-other output would go +to the same slice. This effect will produce a more balanced workload to two slices as shown in the +example below where the color of the block represents which slice it was dispatched to. This is the +walker’s approach to fine-grained parallelism. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 27 + 1.4.3.4 MbAff-Like Special Case in Local Loop +The local loop has an additional middle loop that is used to achieve some specific walking patterns, with +MBAFF mode especially in mind. A pattern to handle MBAFF AVC content is to walk the top macroblocks +of all macroblock pairs (MB-pairs) on a wavefront followed by the respective bottom macroblocks. The +pattern is shown below. + + + + +The outer loop unit step vector would be [1, 0] and the inner loop unit step vector would be [-2, 2]. A third +loop is necessary to repeat the inner loop, only shifted down a unit before restarting. Thus, a middle loop +with a unit step vector of [0,1] would achieve this MBAFF pattern. Additionally, the number of “extra steps” +taken by the middle loop would be 1 in this case. +The addition of a middle loop also creates more overall flexibility, which seems necessary due to the +integer-based unit step vector solution proposed (Manhattan distance issues etc.). + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 28 + 1.4.3.5 Global Loop +The same set of general parameters is used to describe the global loop as well. Thus, a global loop that +is walking a raster-scan pattern can be combined with a local loop that is walking a 26.5º pattern (or vice- +versa). As shown in the example below, if the local block size [8,8] is not an even multiple of the global +resolution [20,20], the slack is still processed by dynamically changing the local block resolution. + + + + +The global loop will always resolve to be the upper-left corner of the local loop, shown above black +circles. Note that local loop can still start in any corner of the local block, but the local (0,0) will always be +the location where global loop begins the local loop, hence the upper-left corner. +The user can specify where the staring location of the global loop as with the local loop. If the user were +to set the global starting location to (16,16) in the previous example, after inverting the global outer and +global inner unit step vectors the same pattern would be achieved in the reverse order. Note that the +slack would still be handled along the right and bottom edge of the global image in that case. The user +could have also started at (12,12) in which case the slack would be handled on the left and top faces. + +1.4.3.6 Walker Algorithm Description +The walker algorithm has been tested and optimized in software. A high-level pseudo-code description is +given below: + Walker(){ //C-Style Pseudo-Code of Walker Algorithm + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 29 + Load_Inputs_And_Initialize(); + While (Global_Outer_Loop_In_Bounds()){ + Global_Inner_Loop_Intialization(); + While (Global_Inner_Loop_In_Bounds()){ + Local_Block_Boundary_Adjustment(); + Local_Outer_Loop_Initialization(); + While (Local_Outer_Loop_In_Bounds()){ + Local_Middle_Loop_Initialization(); + While (Local_Middle_Steps_Remaining()){ + Local_Inner_Loop_Initialization(); + While (Local_Inner_Loop_Is_Shrinking()){ + Execute(); + Calculate_Next_Local_Inner_X_Y(); + } //End Local Inner Loop + Calculate_Next_Local_Middle_X_Y(); + } //End Local Middle Loop + Calculate_Next_Local_Outer_X_Y(); + Calculate_Next_Local_Inverse_Outer_X_Y(); + } //End Local Outer Loop + Calculate_Next_Global_Inner_X_Y(); + } //End Global Inner Loop + Calculate_Next_Global_Outer_X_Y(); + } //End Global Outer Loop + } //End Walker +The pseudo-code has the following characteristics: + +  There are 5 levels of iteration +  The highest 2 levels are called “global” and the lowest 3 levels are called “local” + o The global loop is split into an outer and an inner loop. + o The local loop is split into an outer, a middle, and an inner loop. + o A bounding box for the global and local resolution is defined by the user. + o The starting location within each bounding box is also specified by the user. + +  Each of the 5 loops has its own persistent + o Current position (x,y) + o Unit step vector (x,y) + +  The final output (x,y) is a summation of the global x,y and the local x,y. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 30 +  The next (x,y) for given level can be calculated while the next lower level is still executing. + Additionally, the result can be used to check to see if the current level will execute again once + control is returned. + +The flow of the global outer and inner loops is: + 1. Check a bound condition + 2. Initialize the next level loop + 3. Execute the next level loop + 4. When the next level loop fails its condition, calculate the next position for the current loop + level and repeat. + +Walker algorithm flowchart for the Global Loop + + + + +Take note of the grey box “Local Block Boundary Adjustment”. This logic is necessary to adjust the local +block size when the distance between the current global position to the edge of the image is less than the +local resolution. Additionally, the local starting positions might be modified here as well if the defined +starting position is larger than the new local block size. +The flow of the 3 local loops does not vary much from the 2 global loops. The differences are: + +  In addition to a boundary check, the local middle loop also ensures the number of middle steps is + less than or equal to the user defined “number of extra steps”. +  The local inner loop only checks to see if the prior distance between the x,y starting and ending + points are greater than their current distance. If this is true, it implies that the two inner loops are + converging towards each other. +  When the middle loop check fails, both the starting points (local outer) and ending points (local + inner) are updated. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 31 + Walker algorithm flowchart for the Local Loop + + + + +1.5 Thread Spawner Unit +The Thread Spawner (TS) unit is responsible for making thread requests (root and child) to the Thread +Dispatcher, managing scratch memory, maintaining outstanding root thread counts, and monitoring the +termination of threads. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 32 + Thread Spawner block diagram + + + + +1.5.1 Basic Functions + +1.5.1.1 Root Threads Lifecycle +Thread requests sourced from VFE are called root threads, since these threads may be creating +subsequent (child) threads. A root thread may a macroblock thread created by VFE as in VLD mode, or +may be a general-purpose thread assembled by VFE according to full description provided by host +software in Generic mode. +Thread requests are stored in the Root Thread Queue. TS keeps everything needed to get the root +threads ready for dispatch and then tracks dispatched threads until their retirement. +TS arbitrates between root thread and child thread. The root thread request queue is in the arbitration +only if the number of outstanding threads does not exceed the maximum root thread state variable. +Otherwise, the root thread request queue is stalled until some other root threads retire/terminate. +Once a root thread is selected to be dispatched, its lifecycle can be described by the following steps: + 1. TS forwards the interface descriptor pointer to the L1 interface descriptor cache (a small fully + associated cache containing up to 4 interface descriptors). The interface descriptor is either + found in the cache or a corresponding request is forwarded to the L2 cache. Interface + descriptors return back to TS in requesting order. + +  Once TS receives the interface descriptor, it checks whether maximum concurrent root + thread number has reached to determine whether to make a thread dispatch request or to + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 33 + stall the request until some other root threads retire. If the thread requests the use of + scratch memory, it also generates a pointer into the scratch space. + 2. TS then builds the transparent header and the R0 header. + 3. Finally, TS makes a thread request to the Thread Dispatcher. + 4. TS keeps track of dispatched thread, and monitors messages from the thread (resource + dereference and/or thread termination). When it receives a root thread termination message, it + can recover the scratch space and thread slot allocated to it. The URB handle may also be + dereferenced for a terminated root thread for future reuse. It should be noted that URB handle + dereference may occur before a root thread terminates. See detailed description in the Media + Message section. + +  It is the root thread’s responsibility (software) to guarantee that all its children have retired + before the root thread can retire. + +1.5.1.2 URB Handles +VFE is in charge of allocating URB handles for root threads. One URB handle is assigned to each root +thread. The handle is used for the payload into the root thread. +If Children Present is not set (root-without-child case), TS signals VFE to dereference the URB handle +immediately after it receives acknowledgement from TD that the thread is dispatched. +If Children Present is set (root-with-child case), the URB handle is forwarded to the root thread and +serves as the return URB handle for the root thread. TS does not signal deference at the time of dispatch. +TS signals URB handle deference only when it receives a resource dereference message from the +thread. +Children Present is a command variable in the _OBJECT command. + +1.5.1.3 Root to Child Responsibilities +Any thread created by another thread running in an EU is called a child thread. Child threads can create +additional threads, all under the tree of a root which was requested via the VFE path. +A root thread is responsible of managing pre-allocated resources such as URB space and scratch space +for its direct and indirect child threads. For example, a root thread may split its URB space into sections. It +can use one section for delivering payload to one child thread as well as forwarding the section to the +child thread to be used as return URB space. The child thread may further subdivide the URB section into +subsections and use these subsections for its own child threads. Such process may be iterated. Similarly, +a root thread may split its scratch memory space into sections and give one scratch section for one child +thread. +TS unit only enforces limitation on number of outstanding root threads. It is the root threads’ responsibility +to limit the number of child threads in their respected trees to balance performance and avoid deadlock. + +1.5.1.4 Multiple Simultaneous Roots +Multiple root threads are allowed concurrently running in execution units. As there is only one scratch +space state variable shared for all root threads, all concurrent root thread requiring scratch space share +the same scratch memory size. Multiple Simultaneous Roots depicts two examples of thread-thread +relationship. The left graph shows one single tree structure. This tree starts with a single root thread that +generates many child threads. Some child threads may create subsequent child threads. The right graph +shows a case with multiple disconnected trees. It has multiple root threads, showing sibling roots of +disconnected trees. Some roots may have child threads (branches and leafs) and some may not. + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 34 + There is another case (as shown in Multiple Simultaneous Roots) where multiple trees may be +connected. If a root is a synchronized root thread, it may be dependent on a preceding sibling root thread +or on a child thread. + +Examples of thread relationship + + + + +A example of thread relationship with root sibling dependency + + + + +1.5.1.5 Synchronized Root Threads +A synchronized root thread (SRT) originates from a MEDIA_OBJECT command with Thread +Synchronization field set. Synchronized root threads share the same root thread request queue with the +non-synchronized roots. A SRT is not automatically dispatched. Instead, it stays in the root thread request +queue until a spawn-root message is at the head of the child thread request queue. Conversely, a spawn- +root message in the child thread request queue will block the child thread request queue until the head of +root thread request queue is a SRT. When they are both at the head of queues, they are taken out from +the queue at the same time. +A spawn-root message may be issued by a root thread or a child thread. There is no restriction. However, +the number of spawn-root messages and the number of SRT must be identical between state changes. +Otherwise, there can be a deadlock. Furthermore, as both requests are blocking, synchronized root +threads must be used carefully to avoid deadlock. +When Scoreboard Control is enabled, the dispatch of a SRT originated from a MEDIA_OBJECT_EX +command is still managed by the same way in addition to the hardware scoreboard control. + +1.5.1.6 Deadlock Prevention +Root threads must control deadlock within their own child set. Each root is given a set of preallocated +URB space; to prevent deadlock it must make sure that all the URB space is not allocated to intermediate +children who must create more children before they can exit. + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 35 + There are limits to the number of concurrent threads. The upper bound is determined by the number of +execution units and the number of threads per EU. The actual upper bound on number of concurrent +threads may be smaller if the GRF requirement is large. Deadlock may occur if a root or intermediate +parent cannot exit until it has started its children but there is no space (for example, available thread slot +in execution units) for its children to start. +To prevent deadlock, the maximum number of root threads is provided in VFE state. The Thread +Spawner keeps track of how many roots have been spawned and prevents new roots if the maximum has +been reached. When child threads are present, it is software’s responsibility to constrain child thread +generation, particularly the generation of child threads that may also spawn more child threads. +Child thread dispatch queue in TS is another resource that needs to be considered in preventing +deadlock. The child thread dispatch queue in TS is used for (1) message to spawn a child thread, (2) +message to spawn a synchronized root thread, and (3) thread termination message. If this queue is full, it +will prevent any thread to terminate, causing deadlock. +For example, if an application only has one root thread (max # of root threads is programmed to be one). +This root thread spawns child threads. In order to avoid deadlock, the maximum number of outstanding +child thread that this root thread can spawn is the sum of the maximum available thread slots plus the +depth of the child thread dispatch queue minus one. + Max_Outstanding_Child_Threads = (Thread Slot Number – 1) + (TS Child Queue Depth – 1) +Adding other root threads (synchronized and/or non-synchronized) to the above example, the situation is +more complicated. A conservative measure may have to use to prevent deadlock. For example, the root +thread spawning child threads may have to exclude the max number of root threads as in the following +equation to compute the maximum number of outstanding child threads to be dispatched. + Max_Outstanding_Child_Threads = (Thread Slot Number – 1) + (TS Child Queue Depth – 1) – + (Max Root Threads-1) + +1.5.1.7 Child Thread Lifecycle +When a (parent) thread creates a child thread, the parent thread behaves like a fixed function. It provides +all necessary information to start the child thread, by assembling the payload in URB (including R0 +header) and then sending a spawn thread message to TS with following data: + +  An interface descriptor pointer for the child thread. +  A pointer for URB data + +The interface descriptor for a child may be different from the parent – how the parent determines the child +interface descriptor is up to the parent, but it must be one from the interface descriptor array on the same +interface descriptor base address. +The URB pointer is not the same as a URB handle. It does not have an URB handle number and does +not appear in any handle table. This is acceptable because the URB space is never reclaimed by TS after +a child is dispatched, but rather when the parent releases its original handles and/or retires. +The child request is stored in the child thread queue. The depth of the queue is limited to 8, overrun is +prevented by the message bus arbiter which controls the message bus. The arbiter knows the depth of +the queue and will only allow 8 requests to be outstanding until the TS signals an entry has been +removed. +As mentioned previously, child threads have higher priority over root threads. Once TS selects a child +thread to dispatch, it follows these steps: + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 36 + 1. TS forwards the interface descriptor pointer to the L1 interface descriptor cache (a small fully + associated cache containing up to 4 interface descriptors). The interface descriptor is either + found in the cache or a corresponding request is forwarded to the L2 cache. Interface + descriptors return back to TS in requesting order. + 2. TS then builds the transparent header but not the R0 header. + 3. Finally, TS makes a thread request to the Thread Dispatcher. + 4. Once the dispatch is done, TS can forget the child – unlike roots, no bookkeeping is done that + has to be updated when the child retires. +If more data needs to be transferred between a parent thread and its child thread than that can fit in a +single URB payload, extra data must be communicated via shared memory through data port. + +1.5.1.8 Arbitration between Root and Child Threads +When both root thread queue and child thread queue are both non-empty, TS serves the child thread +queue. In other words, child threads have higher priority over root threads. The only condition that the +child thread queue is stalled by the root thread queue is that the head of child thread queue is a root- +synchronization message and the head of root thread queue is not a synchronized root thread. + +1.5.1.9 Persistent Root Thread +A persistent root thread in general stays in the system for a long period of time. It is normally a parent +thread, and only one PRT is allowed in the system at a time. The PRT can be restarted later, even if it +had completed normally the last time it was executed. Therefore, the PRT must always save enough +context (via data port messages to a predefined surface) to allow it to restart from where it left off +(including determining that it has nothing left to do). However, since only one PRT can execute at a time, +once the next PRT starts, the previous one will never be restarted, thus the context save surface can be +reused from one PRT to the next. +A PRT may check the Thread Restart Enable bit in the R0 header to find out whether it is a fresh start or +resumed from a previous interrupt and then can continue operations from that previously saved context. +PRT can be interleaved with other root (such as parent root thread, or synchronized root thread) and child +threads. A parent root thread is not necessarily a PRT, and doesn’t have to be as long as it can be +finished in deterministic time that is shorter than required for fine-grain context switch interrupt. +Use of PRT must follow the following rules: + +  There can only be one PRT in the media pipeline at a given time. That means, there shall not be any + other media primitive commands (MEDIA_OBJECT or MEDIA_OBJECT_EX) between it and the + previous MI_FLUSH command. In other words, when multiple such PRTs are used in a sequence of + media primitive commands, MI_FLUSH must be inserted. + +1.5.1.10 GPGPU Functions +In GPGPU mode, the Thread Spawner allocate and track the barriers and shared local memory per +thread group. + +1.5.1.10.1 Thread Group Tracking +The TSG needs to keep track of the threads outstanding in a group to know when the thread group +barrier and Shared Local Memory can be reclaimed. This can be done by keeping a counter per active +thread group (up to 16 per half-slice) which increments when a new thread is sent out and decremented + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 37 + when the thread retires. The assigned barrier ID (with half-slice bit) is unique per thread group and much +smaller than the thread group id and so will be used to keep track of the thread group instead. +Since TSL sends the thread retirement via the Message Channel rather thant the thread retirement bus, +the barrier ID used to identify the thread group can be sent at the same time. A CAM will then match the +ID with the counter to decrement. +There is a potential corner case of a thread group without barriers being partly dispatched, then retiring +before the rest of the thread group is sent. This should be OK, since the lack of barriers means that there +is no dependencies between threads. + +1.5.1.10.2 Shared Local Memory Allocation +The Shared Local Memory is a 64k block per half-slice in the L3 that must be shared between all thread +groups on that half-slice. A new memory manager simular to the Scratch Space memory manager is used +to allocate this space. +We are only dispatching threads from a single Interface Descriptor at a time. If a new Interface Descriptor +is requested the pipe is drained and all shared memory recovered before starting to allocate new shared +memory. This means that only a single size of shared memory needs to be supported at once. +For simplicity, only power-of-2 sizes from 4k to 64k are allowed. The thread request will specify how much +is needed. The first thread of a Thread Group is marked as requiring a new shared local memory – if not +the old Shared Local Memory offset is sent with the dispatch. +A simple set of 16-bits is used to allocate 4k shared memory, with fewer bits used for larger sizes. A +priority encoder finds the first unused bit and the offset remembered as being associated with a particular +barrier id. The barrier id is then used to track the thread group. +When the Thread Group Tracking indicates that a thread group is completely retired, that section of +shared local memory can be reclaimed. + +1.5.1.10.3 Software Managed Shared Local Memory +Software can optionally manage shared local memory. In this case, each thread command or thread +group command will have the shared memory offset included – each command in a thread group must +have the same offset, of couse. If the offset requested is still being used then the command is stalled until +the thread group using that offset is done. +Hardware will track the usage of this section of shared memory as before, recording the offset as being +used and recording it as being available after the thread group is done. + +1.5.1.10.4 Automatic Barrier Management +Since we have an automatic shared memory allocation it makes sense to make barrier management +automatic too. +Instead of the barrier id in the Interface Descriptor, there is now a thread count per thread group. If a new +thread group id comes in without a barrier allocated (checked with a CAM match across> 16 barriers), the +TSG picks an unused barrier and sends this count in a message to GWunit. It then needs to wait for an +accept message back from GW before sending the dispatch to ensure that a barrier message doesn’t +arrive at the GW before the barrier is programmed. The barrier id picked is sent with every dispatch from +this thread group. +When the thread group tracker determines that a thread group has finished, the barrier becomes +available to new thread groups. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 38 + 1.5.1.10.5 Local Memory / Scratch Space +The Local Memory (not to be confused with Shared Local Memory, which is shared by all thread in a +thread group) is allocated per thread dispatched to the EU. +The existing Scratch Space manager is used to provide between 1k and 12k bytes memory per thread. A +small change to the kernel can be used to provide more scratch space – the pointer that TSG provides is +simply: +Scratch Space Pointer = Scratch Space Base Pointer + FFTID * Per Thread Scratch Space +To increase the amount of scratch space per thread, each kernel needs to do this operation on its +Scratch Space Pointer: +New Scratch Space Pointer = Old Scratch Space Pointer + FFTID * (New Per Thread Scratch Space +– Old Per Thread Scratch Space) +The old Scratch Space Pointer and FFTID are available in the R0 header. The driver needs to allocate +enough memory for the total number of threads in the system * the new per thread scratch space. + +1.5.1.10.6 Dispatch Payload +The payload for a general purpose thread will have to include the execution mask with a bit per 32- +channel. SIMD16 and SIMD8 use the LSB bits of the execution mask. The 5-bit number transferred from +VFE will be expanded to produce the 32-bit mask. This will use the Dmask currently used by the pixel +shader dispatch in the transparent header. + + +1.5.2 Interfaces + +1.5.2.1 Interface to VFE +TS receives an interface descriptor pointer and a URB handle from VFE. It uses the interface descriptor +pointer to fetch the interface descriptor. TS uses the information in the interface descriptor along with the +URB handle to fill out the transparent header in the message to TD for all threads. For root thread, TS +also generate the R0 header. +TS transmits URB handle dereference signal to VFE. As described previously, the derefernce signal may +be at dispatch time or at later time depending on Children Present. No matter which case, there is one +and only one URB handle dereference for a thread. + +1.5.2.2 Interface to Thread Dispatcher +TS creates the transparent header, assembles the URB handles and calls TD to dispatch a new thread. +For an unsynchronized root thread, there is one URB handle managed by VFE and optionally one +Constant URB handle managed by CS. For a synchronized root thread, there is one URB handle +managed by VFE, a URB handle created by the synchronizing thread (the one that sends the ‘spawn root +thread’ message, and optionally one Constant URB handle managed by CS. For a child thread, there is +one URB handle managed by the parent thread plus an optional Constant URB handle. + + +1.6 Media State Model +The media state model is based on in-line state load mechanism. VFE state, URB configuration and +Interface Descriptors are loaded to VFE hardware through state commands. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 39 + All Interface Descriptors have the same size and are organized as a contiguous array in memory. They +can be selected by Interface Descriptor Index for a given kernel. This allows different kinds of kernels to +coexist in the system. + + Pipeline Opcode Sub Command + Opcode + + (Media) + Bits Bits Bits + [28:27] [26:24] [23:16] + + 2h 0h 00h MEDIA_VFE_STATE + 2h 0h 01h MEDIA_CURBE_LOAD + 2h 0h 02h MEDIA_INTERFACE_DESCRIPTOR_LOAD + + + +1.7 Media Messages +All message formats are given in terms of dwords (32 bits) using the following conventions. +Dispatch Messages: Rp.d +SEND Instruction Messages: Mp.d + + +1.7.1 Thread Payload Messages +The root thread’s register contents differ from that of child threads, as shown in Thread Payload +Messages. The register contents for a synchronized root thread (also referred to as ‘spawned root +thread’) and an unsynchronized one are also different. Whether the URB Constant data field is present or +not is determined by the interface descriptor of a given thread. This applies to both root and child threads. +When URB Constant data field is present for a synchronized root thread, URB constant data field is +before the data field received from the spawning thread, which is also before the URB payload data. + +Thread payload message formats for root and child threads + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 40 + 1.7.1.1 Generic Mode Root Thread +The following table shows the R0 register contents for a Generic mode root thread, which is generated by +TS. The remaining payloads are application dependent. + +R0 Header of a Generic Mode Root Thread +DWord Bit Description + R0.7 31:0 + 31:0 + R0.6 Reserved + + 31:10 + R0.5 Scratch Space Pointer. Specifies the 1k-byte aligned pointer to + the scratch space. This field is only valid when Scratch Space is + enabled. + Format = GeneralStateOffset[31:10] + + 9:8 + Reserved: MBZ. + 9:0 + FFTID. This ID is assigned by TS and is a unique identifier for the + thread in comparison to other concurrent root threads. It is used to + free up resources used by the thread upon thread completion. + Format = U8. Bits 9:8 are Reserved, MBZ. + 31:5 + R0.4 Binding Table Pointer: Specifies the 32-byte aligned pointer to + the Binding Table. It is specified as an offset from the Surface + State Base Address. + Format = SurfaceStateOffset[31:5] + 4:0 Reserved : MBZ + 31:5 + R0.3 Sampler State Pointer. Specifies the 32-byte aligned pointer to + the sampler state table. + Format = GeneralStateOffset[31:5] + + 4 Reserved : MBZ + 3:0 + Per Thread Scratch Space. Specifies the amount of scratch + space, in 16-byte quantities, allowed to be used by this thread. + The value specifies the power that two will be raised to, to + determine the amount of scratch space. + Format = U4 + Range = [0,11] indicating [1k bytes, 2M bytes] in powers of two + R0.2 31:28 Reserved : MBZ + 27:24 + BarrierID. This field indicates which one from the 16 Barriers this + kernel is associated. + Format: U4 + 23:16 + Barrier.Offset. This is the offset for the Barrier to indicate the + offset from the requester's RegBase (which may be 0 if Bypass + Gateway Control is set to 1) for the broadcast barrier message. + Barrier.Offset + RegBase must be in the valid GRF range. + Otherwise, hardware behavior is undefined. + It is in unit of 256-bit GRF register. + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 41 + DWord Bit Description + The most significant bit of this field must be zero. + Format = U8 + Range = [0,127] + 15:9 Reserved : MBZ + 8:4 + Interface Descriptor Offset. This field + specifies the offset from the interface + descriptor base pointer to the interface + descriptor which will be applied to this + object. It is specified in units of interface + descriptors. + Format = U5 + + 3:0 + Scoreboard Color (only with MEDIA_OBJECT_EX): This field + specifies which dependency color the current thread belongs to. It + affects the dependency scoreboard control. + Format = U4 + R0.2 31:10 Reserved: MBZ + 9:4 + Interface Descriptor Offset. This field specifies the offset from + the interface descriptor base pointer to the interface descriptor + which will be applied to this object. It is specified in units of + interface descriptors. + Format = U5 + 3:0 + Scoreboard Color (only with MEDIA_OBJECT_EX): This field + specifies which dependency color the current thread belongs to. It + affects the dependency scoreboard control. + Format = U4 + + R0.1 31:28 + Scoreboard Mask 4-7 (only with MEDIA_OBJECT_EX): Each bit + indicates the corresponding dependency scoreboard is dependent + on. This field is AND’d with the corresponding Scoreboard Mask + field in the VFE_STATE_EX. + Bit n (for n = 4…7): Scoreboard n is dependent, where bit 28 + maps to n = 4. + Format = TRUE/FALSE + Reserved : MBZ + 27:26 + Reserved : MBZ + 25 + Reserved. MBZ + + 24:16 + Scoreboard Y + This field provides the Y term of the scoreboard value of the + current thread. + Format = U9 + only with MEDIA_OBJECT_EX. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 42 + DWord Bit Description + Reserved : MBZ + 15:12 + Reserved : MBZ + + 11:9 + Reserved. MBZ + + 8:0 + Scoreboard X + This field provides the X term of the scoreboard value of the + current thread. + Format = U9 + only with MEDIA_OBJECT_EX. + Reserved : MBZ + R0.0 31:24 + Scoreboard Mask: Each bit indicates the corresponding + dependency scoreboard is dependent on. This field is AND’d with + the corresponding Scoreboard Mask field in the + MEDIA_VFE_STATE. + Bit n (for n = 0…7): Scoreboard n is dependent, where bit 24 + maps to n = 0. + Format = TRUE/FALSE + 23:16 Reserved : MBZ + 15:0 + URB Handle. This is the URB handle where indicating the URB + space for use by the root thread and its children. + + +1.7.1.2 Root Thread from MEDIA_OBJECT_PRT +The root thread payload message for an MEDIA_OBJECT_PRT command has a fixed format +independent of the VFE mode (e.g. Generic mode or AVC-IT mode). One example GRF register location +is given for the condition that CURBE is disabled. + +Root thread payload layout for a MEDIA_OBJECT_PRT command +GRF Register Example Description + R0 R0 + R0 header + + R1 – R(m) n/a + Constants from CURBE when CURBE is enabled + m is a non-negative value + + R(m+1) R1 + In-line Data block. + +The R0 header field is as the following, which is the same as in other modes except the Thread Restart +Enable bit (bit 0 of R0.2). + +R0 header of the thread payload of a MEDIA_OBJECT_PRT command +DWord Bit Description + R0.7 31 + 27:24 + 23:0 + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 43 + DWord Bit Description + R0.6 31:24 + 23:0 + R0.5 31:10 + Scratch Space Pointer. Specifies the 1k-byte aligned pointer to the scratch space. This field is only + valid when Scratch Space is enabled. + Format = GeneralStateOffset[31:10] + 9:8 Reserved : MBZ + 7:0 + FFTID. This ID is assigned by TS and is a unique identifier for the thread in comparison to other + concurrent root threads. It is used to free up resources used by the thread upon thread completion. + + R0.4 31:5 + Binding Table Pointer: Specifies the 32-byte aligned pointer to the Binding Table. It is specified as an + offset from the Surface State Base Address. + Format = SurfaceStateOffset[31:5] + 4:0 Reserved : MBZ + R0.3 31:5 + Sampler State Pointer. Specifies the 32-byte aligned pointer to the sampler state table. + Format = GeneralStateOffset[31:5] + 4 Reserved : MBZ + 3:0 + Per Thread Scratch Space. Specifies the amount of scratch space, in 16-byte quantities, allowed to + be used by this thread. The value specifies the power that two will be raised to, to determine the + amount of scratch space. + Format = U4 + Range = [0,11] indicating [1k bytes, 2M bytes] in powers of two + R0.2 31:4 + Interface Descriptor Pointer. Specifies the 16-byte aligned pointer to this thread’s interface + descriptor. Can be used as a base from which to offset child thread’s interface descriptor pointers from. + Format = GeneralStateOffset[31:4] + + 3:1 Reserved : MBZ + 0 + Thread Restart Enable. If set, indicates that the persistent root thread (PRT) is being restarted, and + context should be restored from the context save area before executing. + Format = Enable + R0.1 31:0 Reserved : MBZ + R0.0 31:16 Reserved : MBZ + 15:0 + URB Handle. This is the URB handle where indicating the URB space for use by the root thread and + its children. + +The inline data block field is the same as in the MEDIA_OBJECT_EX command with zero-filled partial +GRF. + +1.7.1.3 Root Thread from MEDIA_OBJECT_WALKER +The root thread payload message for an MEDIA_OBJECT_WALKER command, which must be in +Generic mode, has the same format as that of the generic mode root thread format. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 44 + Root thread payload layout for a MEDIA_OBJECT_WALKER command +GRF Register Example Description + R0 R0 + R0 header + + R1 – R(m) n/a + Constants from CURBE when CURBE is enabled + m is a non-negative value + R(m+1) R1 + In-line Data block. + +The R0 header field is identical to that of Generic Mode Root Thread. +The inline data block field is the same as in the MEDIA_OBJECT command with zero-filled partial GRF. +There is no indirect data block field. + +1.7.1.4 Child Thread +The tread initiation for the child thread is determined by the data stored in the URB by the parent that +spawns it. No hardware-defined header is generated. However, software should follow the header field +definition similar to that for a root thread, when the same fields are used, to be consistent and to reduce +message header assemble overhead. + The Parent Thread Count field should be the Thread Count field of the parent thread itself (e.g. copying +R0.6[23:0] to R0.7[23:0]. The Thread Count field should have a unique value for each child thread and +the unique value should not be dependent on the execution order. This is mostly important for the cases +when the child thread generation order may vary depending on the thread completion order. For example, +when generating child threads for macroblock-based processing, the Thread Count field for a child thread +should be deterministic for a macroblock position. +The following table shows the R0 register contents for a child thread, which is generated by its parent +thread. The remaining payloads are application dependent. + DWord Bit Description + 31 + R0.7 + 27:24 + 23:0 + 31:24 + R0.6 + 23:0 +R0.5-R0.0 31:0 + Software defined + + + +1.7.1.5 GPGPU Thread +The RO header of the Thread Dispatch Payload for the GPGPU thread: +DWord Bit Description + R0.7 31:0 + Thread Group ID Z: This field identifies the Z component of the thread group. That this thread + belongs to. + R0.6 31:0 + Thread Group ID Y: This field identifies the Y component of the thread group that this thread belongs + to. + R0.5 31:10 + Scratch Space Pointer. Specifies the 1k-byte aligned pointer to the scratch space (used for the + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 45 + DWord Bit Description + GPGPU local memory space). + Format = GeneralStateOffset[31:10] + 9:8 + Reserved: MBZ. + + 9:0 + FFTID. This ID is assigned by TS and is a unique identifier for the thread in comparison to other + concurrent threads (of any thread group). It is used to free up resources used by the thread upon + thread completion. + Format = U8. Bits 9:8 are Reserved, MBZ. + R0.4 31:5 + Binding Table Pointer. Specifies the 32-byte aligned pointer to the Binding Table. It is specified as + an offset from the Surface State Base Address. + Format = SurfaceStateOffset[31:5] + 4 Reserved + 3:0 + Range = [0,11] indicating [1K Bytes, 2M Bytes] + R0.3 31:5 + Sampler State Pointer. Specifies the 32-byte aligned pointer to the sampler state table. + Format = GeneralStateOffset[31:5] + + 4 Reserved : MBZ + 3:0 + Per Thread Scratch Space. Specifies the amount of scratch space, in 16-byte quantities, allowed to + be used by this thread. The value specifies the power that two will be raised to, to determine the + amount of scratch space. + Format = U4 + Range = [0,11] indicating [1k bytes, 12k bytes] + R0.2 31 + Reserved: MBZ + + 30 + Reserved: MBZ + + 29 + Barrier Enable: This field indicates that a barrier has been allocated for this kernel + Reserved: MBZ + 28 + SLM Enable: This field indicates that Shared Local Memory has been allocated for this kernel + Reserved: MBZ + 27:24 + BarrierID: This field indicates the barrier that this kernel is associated with. + Format: U4 + 23:15 + 23:16 + This key is a free running count of the number of dispatches. + + Reserved: MBZ + 14:10 + 9:4 + Interface Descriptor Offset. This field specifies the offset from the interface descriptor base pointer + to the interface descriptor which will be applied to this object. It is specified in units of interface + descriptors. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 46 + DWord Bit Description + Format = U5 + 3:0 + Reserved. MBZ + + R0.1 31:0 + Thread Group ID X: This field identifies the X component of the thread group that this thread belongs + to. + 30:28 Reserved: MBZ + 27:24 + Shared Local Memory Index: Indicates the starting index for the shared local memory for the thread + group. Each index points to the start of a 4k memory block, 16 possibilities cover the entire 64k + shared memory per half-slice. + Format = U4 + 23:16 + Reserved: MBZ + + 15:0 + URB Handle. This is the URB handle where indicating the URB space for use by the thread. + +Cross-thread CURBE if present is in R1 and above, followed by the X/Y/Z thread id values for each +channel in the thread. + + +1.7.2 Thread Spawn Message +The thread spawn message is issued to the TS unit by a thread running on an EU. This message +contains only one 8-DW register. The thread spawn message may be used to + +  Spawn a child thread +  Spawn a root thread (start dispatching a synchronized root thread) +  Dereference URB handle +  Indicate a thread termination, dereference other TS managed resource and may or may not + dereference URB handle +  Release a PRT_Fence () + +In order to end a root thread, the end of thread message must be targeted at the thread spawner. In this +case, the root thread sends a message with a “dereference resource” in the Opcode field. The thread +spawner does not snoop the messages sideband to determine when a root thread has ended. Thread +Spawner does not track when a child thread terminates, to be consistent a child thread should also +terminate with a “dereference resource” message to the Thread Spawner. Software must set the +Requester Type (root or child thread) field correctly. +As TS dispatches one synchronized root thread upon receiving a ‘spawn root thread’ message (from a +synchronization thread). The synchronizing thread must send the number of ‘spawn root thread’ message +exactly the same as the subsequent ‘synchronized root thread’. No more, no less. Otherwise, hardware +behavior is undefined. +URB Handle Offset field in this message (in M0.4) has 10 bits, allowing addressing of a large URB space. +However, when a parent thread writes into the URB, it subjects to the maximum URB offset limitation of +the URB write message, which is only 6 bits (see Unified Return Buffer Chapter for details). In this case, +the parent thread may have to modify the URB Return Handle 0 field of the URB write message in order +to subdivide the large URB space that the thread manages. +Only a persistent root thread can use this message to dispatch a root thread if preemption exceptions are +possible. The root thread requested by this message is not guaranteed to dispatch, and the persistent + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 47 + root thread must handle the case where it does not dispatch. When a context switch interrupt is +recognized by the persistent root thread, all other root threads that had been dispatched have completed +and no more will be dispatched. Child threads requested by this message are guaranteed to dispatch in +all cases, so long as the persistent root thread does not also dispatch synchronized root threads. A child +thread will not dispatch if it is behind a synchronized root thread that is not dispatched due to preemption +exception. +In a system running child threads, a parent thread is monitoring the status of the child threads by +communications through Message Gateway. When a child thread is about to terminate, it sends a +message to the parent through Message Gateway and then sends a second message of EOT (end of +thread) to TS. +There is a latency between sending a message to parent thread and the EOT to TS due to message bus +arbitration. The parent thread may acknowledge the GW message and issue a new child dispatch before +the EOT was processed; basically threads are issued faster than retired. +Because the messages for new child dispatch and EOT go to the same queue in TS, if the queue gets +full, EOTs will get blocked. In the case when all the EUs/Threads are full, this will create a system +deadlock: no EOTs can be acknowledged by TS (to free up EU resource) and no child threads can be +dispatched (to free up TS queue to receive EOT message). + +1.7.2.1 Message Descriptor +The following table shows the lower 16 bits of the message descriptor (lower 20 bits for ) within the SEND +instruction for a thread spawn message. +Bit Description +19 + Header Present + This bit must be set to zero for all Thread Spawner messages. + :this bit is not part of the shared function specific message descriptor. + +18:5 + Reserved: MBZ + Bits 18:16 are not part of the shared function specific message descriptor. + 4 + Resource Select. This field specifies the resource associated with the action taken by the Opcode. + If Opcode is “Spawn thread”, this field selects whether it is a child thread or a root thread. + 0: spawn a child thread + 1: spawn a root thread or (only) release a PRT_Fence + If Opcode == “Dereference Resource”, this field indicates whether the URB handle is to be dereferenced. The + URB handle can only be dereferenced once. + 0: The URB handle is dereferenced + 1: The URB handle is NOT dereferenced +3:2 + Reserved: MBZ + + 1 + Requester Type. This field indicates whether the requesting thread is a root thread or a child thread. If it is a + root thread, when Opcode is 0, FF managed resources will be dereferenced. If it is a child thread and Opcode is + 0, no resource will be dereferenced – basically no action is required by the TS. + 0: Root thread + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 48 + Bit Description + 1: Child thread + 0 + Opcode. Indicates the operation performed by the message. A root thread must terminate with a message to + TS (Opcode == 0 and EOT == 1). A child thread should also terminate with such a message. A thread cannot + terminate with an Opcode of “spawn thread”. + 0: dereference resource (also used for end of thread) + 1: spawn thread + + +1.7.2.2 Message Payload +DWord Bit Description + M0.7 31:0 + M0.6 31:0 + M0.5 31:8 Ignored + 7:0 + FFTID. This ID is assigned by TS and is a unique identifier for the thread in comparison to other + concurrent root threads. It is used to free up resources used by a root thread upon thread completion. + This field is valid only if the Opcode is “dereference resource”, and is ignored by hardware otherwise. + + M0.4 31:16 Ignored + 15:10 + Dispatch URB Length. Indicates the number of 8-DW URB entries contained in the Dispatch URB + Handle that will be dispatched. When spawning a child thread, the URB handle contains most of the + child thread's payload including R0 header. When spawning a root thread, the URB handle contains + the message passed from the requesting thread to the spawned "peer" root thread. The number of + GRF registers that will be initialized at the start of the spawned child thread is the addition of this field + and the number of URB constants if present. The number of GRF registers that will be initialized at the + start of a spawned root thread is the addition of this field, the number of URB constants if present, and + the URB handle received from VFE. + This field is ignored if the Opcode is "dereference resource". + Length of 0 can be used while spawning child threads to indicate that there is no payload beyond the + required R0 header. Length of 0 while spawning a root thread indicates that there is no payload at all + from the parent thread. A spawned root has R0 supplied by the Media_Object command indirect/inline + data. + Format = U6 + Range = [0,63] for child threads + 9:0 + URB Handle Offset. Specifies the 8-DW URB entry offset into the URB handle that determines where + the associated dispatch payload will be retrieved from when the spawned child or root thread is + dispatched. + This field is ignored if the Opcode is “dereference resource”. + Format = U10 + Range = [0,1023] + + M0.3 31:0 Ignored + M0.2 31:28 Ignored + 27:24 + BarrierID. This field indicates which one from the 16 Barriers this kernel is associated. + Format: U4 + 23:16 + Ignored + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 49 + DWord Bit Description + 15:10 Ignored + 9:4 + Interface Descriptor Offset. This field specifies the offset from the interface descriptor base pointer to + the interface descriptor which will be applied to this object. It is specified in units of interface + descriptors. + Format = U5 + 3:0 + Scoreboard Color (only with MEDIA_OBJECT_EX): This field specifies which dependency color the + current thread belongs to. It affects the dependency scoreboard control. + Format = U4 + + M0.1 31:0 Ignored + M0.0 31:28 Ignored + 27:24 + Shared Local Memory Index: Indicates the starting index for the shared local memory for the thread + group. Each index points to the start of a 4k memory block, 16 possibilities cover the entire 64k shared + memory per half-slice. + + + Format = U4 + 23:16 Reserved : MBZ + 15:0 + Dispatch URB Handle + If Opcode (and Requester Type) is “spawn a child thread”: Specifies the URB handle for the child + thread. + If Opcode (and Requester Type) is “spawn a root thread”: Specifies the URB handle containing + message (e.g. requester’s gateway information) from the requesting thread to the spawned root thread. + If Opcode is “dereference resource”: This field is required on end of thread messages if the Children + Present bit is set, as the handle must be dereferenced, otherwise this field is ignored. + + + + 1.8 Media State and Primitive Commands + + 1.8.1 MEDIA_VFE_STATE Command + + MEDIA_VFE_STATE + + Length Bias: 2 + An MI_FLUSH is required before MEDIA_VFE_STATE unless the only bits that are changed are scoreboard related: + Scoreboard Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For these scoreboard related states, a + MEDIA_STATE_FLUSH is sufficient. + + + + MEDIA_STATE_FLUSH (optional, only if barrier dependency is needed) + + MEDIA_INTERFACE_DESCRIPTOR_LOAD (optional) + + DWord Bit Description + 0 31:29 Command Type + + + + Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 50 + MEDIA_VFE_STATE + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h Media + Format: OpCode + 26:24 Media Command Opcode + Default Value: 0h + Format: OpCode + 23:16 SubOpcode + Default Value: 0h MEDIA_VFE_STATE + Format: OpCode + 15:0 DWord Length + Format: =n Total Length - 2 + + + + + Value Name Description + 06h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 31:10 Scratch Space Base Pointer + Format: GeneralStateOffset[31:10] + Specifies the 1k-byte aligned address offset to scratch space for use by the kernel. This pointer is + relative to the General State Base Address. + + 9:8 Reserved + Format: MBZ + 7:4 Reserved + + Format: MBZ + 3:0 Per Thread Scratch Space + Format: U4 + Specifies the amount of scratch space allowed to be used by each thread. The driver must allocate + enough contiguous scratch space, pointed to by the Scratch Space Pointer, to ensure that the + maximum threads in the device each get Per Thread Scratch Space size without exceeding the driver- + allocated scratch space.. + Value Name Description Project + [0,11] Indicating [1k bytes, 12k bytes] : 0->1k, 1->2k, 2->3k … 11->12k +2 31:16 Maximum Number of Threads + Format: U16-1 representing thread count + + + + + Specifies the maximum number of simultaneous root threads allowed to be active. Used to avoid + potential deadlock. + Note that MSB will be zero due to the range limit below. + Range: [0, n-1] where n = (# EUs) * (# threads/EU). See Graphics Processing Engine for listing of + #EUs and #threads in each device. + 15:8 Number of URB Entries + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 51 + MEDIA_VFE_STATE + Format: U8 + Specifies the number of URB entries that are used by the unit. + Value Name Description Project + [0,64] [0,64] Entries + 7 Reset Gateway Timer + This field controls the reset of the timestamp counter maintained in Message Gateway. + Value Name + 0h Maintaining the existing timestamp state + 1h Resetting relative timer and latching the global timestamp + 6 Bypass Gateway Control + This field configures Gateway to use a simple message protocol. + Value Name + 0h Maintaining OpenGateway/ForwardMsg/CloseGateway protocol (legacy mode) + 1h Bypassing OpenGateway/CloseGateway protocol + 5 Reserved + + + 4:3 Gateway MMIO Access Control + + The Gateway allows messages from EUs to read and write MMIO registers. This field limits this feature + for security reasons + Value Name + 0h No MMIO read/write allowed + 2h MMIO read/write to any address +3 7:2 Reserved + Format: MBZ + 1:0 Reserved + + Format: MBZ +4 31:16 URB Entry Allocation Size + Format: U16 + + + Description Project + Specifies the length of each URB entry used by the unit, in 256-bit register increments - 1. + ROB address for URB starts after CURBE Allocated region. + (URB Entry Allocation Size * Number of URB Entries) + CURBE Allocation Size + Interface + Descriptor Entries) must be less than or equal to the number of entries in the URB as + described in vol5c.5 Shared Functions Unified Return Buffer, under the section “URB Size”. + Interface Descriptor Entires is 32 + + + Programming Notes + When Inline data is used with MEDIA_OBJECT or MEDIA_OBJECT_WALKER, then the URB entry + allocation size must match the Inline data size. + If Indirect data is being used with MEDIA_OBJECT then the allocation size does not matter, but the + total Allocation Size * Number of URB Entries should be sufficient for the Indirect data. + If both Inline and Indirect are being used, then the allocation size must match the Inline and the total + space must be enough for both the Indirect and Inline. + 15:0 CURBE Allocation Size + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 52 + MEDIA_VFE_STATE + Format: U16 + + + Description Project + Specifies the total length allocated for CURBE, in 256-bit register increments. ROB address for + CURBE starts at address 32 . (URB Entry Allocation Size * Number of URB Entries) + CURBE + Allocation Size + Interface Descriptor Entries) must be less than or equal to the number of + entries in the URB as described in vol5c.5 Shared Functions Unified Return Buffer, under the + section “URB Size”. + Interface Descriptor Entires is 32 + There are additional restrictions on CURBE Allocation: + + + + + Value Name Project + [0,480] + [0,2016] +5 31 Scoreboard Enable + This field enables and disables the hardware scoreboard in the Media Pipeline. If this field is cleared, + hardware ignores the following scoreboard state fields. + Value Name + 0h Scoreboard disabled + 1h Scoreboard enabled + 30 Scoreboard Type + This field selects the type of scoreboard in use. + Value Name Project + 0h Stalling Scoreboard + 1h Non-Stalling Scoreboard + 29:8 Reserved + Format: MBZ + 7:0 Scoreboard Mask + Format: Enable[8] + Each bit indicates the corresponding dependency scoreboard is enabled. The scoreboard is based on + the relative (X, Y) distance from the current threads’ (X, Y) position. + Bit n (for n = 0…7): Score n is enabled. + +6 31:28 Scoreboard 3 Delta Y + Format: S3 + Relative vertical distance of the dependent instance assigned to scoreboard 3, in the form of 2’s + compliment. + + 27:24 Scoreboard 3 Delta X + Format: S3 + Relative horizontal distance of the dependent instance assigned to scoreboard 3, in the form of 2’s + compliment. + + 23:20 Scoreboard 2 Delta Y + Format: S3 + Relative vertical distance of the dependent instance assigned to scoreboard 2, in the form of 2’s + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 53 + MEDIA_VFE_STATE + compliment. + + 19:16 Scoreboard 2 Delta X + Format: S3 + Relative horizontal distance of the dependent instance assigned to scoreboard 2, in the form of 2’s + compliment. + + 15:12 Scoreboard 1 Delta Y + Format: S3 + Relative vertical distance of the dependent instance assigned to scoreboard 1, in the form of 2’s + compliment. + + 11:8 Scoreboard 1 Delta X + Format: S3 + Relative horizontal distance of the dependent instance assigned to scoreboard 1, in the form of 2’s + compliment. + + 7:4 Scoreboard 0 Delta Y + Format: S3 + Relative vertical distance of the dependent instance assigned to scoreboard 0, in the form of 2’s + compliment. + + 3:0 Scoreboard 0 Delta X + Format: S3 + Relative horizontal distance of the dependent instance assigned to scoreboard 0, in the form of 2’s + compliment. + +7 31:28 Scoreboard 7 Delta Y + Format: S3 + Relative vertical distance of the dependent instance assigned to scoreboard 7, in the form of 2’s + compliment. + + 27:24 Scoreboard 7 Delta X + Format: S3 + Relative horizontal distance of the dependent instance assigned to scoreboard 7, in the form of 2’s + compliment. + + 23:20 Scoreboard 6 Delta Y + Format: S3 + Relative vertical distance of the dependent instance assigned to scoreboard 6, in the form of 2’s + compliment. + + 19:16 Scoreboard 6 Delta X + Format: S3 + Relative horizontal distance of the dependent instance assigned to scoreboard 6, in the form of 2’s + compliment. + + 15:12 Scoreboard 5 Delta Y + Format: S3 + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 54 + MEDIA_VFE_STATE + Relative vertical distance of the dependent instance assigned to scoreboard 5, in the form of 2’s + compliment. + + 11:8 Scoreboard 5 Delta X + Format: S3 + Relative horizontal distance of the dependent instance assigned to scoreboard 5, in the form of 2’s + compliment. + + 7:4 Scoreboard 4 Delta Y + Format: S3 + Relative vertical distance of the dependent instance assigned to scoreboard 4, in the form of 2’s + compliment. + + 3:0 Scoreboard 4 Delta X + Format: S3 + Relative horizontal distance of the dependent instance assigned to scoreboard 4, in the form of 2’s + compliment. + + + + +1.8.2 MEDIA_CURBE_LOAD + + MEDIA_CURBE_LOAD + +Length Bias: 2 +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h Media + Format: OpCode + 26:24 Media Command Opcode + Default Value: 0h + Format: OpCode + 23:16 SubOpcode + Default Value: 1h Media_CURBE_LOAD + Format: OpCode + 15:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Description + 2h DWORD_COUNT_n [Default] Excludes DWord (0,1) + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 55 + MEDIA_CURBE_LOAD +1 31:0 Reserved + Project: All + Format: MBZ +2 31:17 Reserved + Project: All + Format: MBZ + 16:0 CURBE Total Data Length + Project: All + Format: U17 In Bytes + + + + + Description Project + This field provides the length in bytes of the CURBE data. + This field must have the same alignment as the Curbe Object Data Start Address.As the + CURBE data are sent directly to ROB, range is limited to CURBE Allocation Size. + This field must be DWord (32-byte) aligned. +3 31:0 CURBE Data Start Address + Project: All + Format: DynamicStateOffset[31:0] CURBE + + + Description Project + Specifies the 32-byte (DWord) aligned address of the CURBE data. This pointer is relative to + the Dynamics Base Address. + + + Value Name + [0,FFFFFFFFh] + + + Programming Notes Project + Driver must invalidate the vertex fetch cache thru the VF(address based) Cache Invalidation P + Enable thru a PIPE_CONTROL command prior to reusing the same graphics memory space. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 56 + 1.8.3 MEDIA_INTERFACE_DESCRIPTOR_LOAD Command + + MEDIA_INTERFACE_DESCRIPTOR_LOAD + +Length Bias: 2 +A Media_State_Flush should be used before this command to ensure that the temporary Interface Descriptor storage +is cleared. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h Media + Format: OpCode + 26:24 Media Command Opcode + Default Value: 0h + Format: OpCode + 23:16 SubOpcode + Default Value: 2h MEDIA_INTERFACE_DESCRIPTOR_LOAD + Format: OpCode + 15:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Description + 2h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 31:5 Reserved + Project: All + Format: MBZ + 4:0 Reserved + Project: All + Format: MBZ +2 31:17 Reserved + Project: All + Format: MBZ + 16:0 Interface Descriptor Total Length + Project: All + Format: U17 In bytes + + + This field provides the length in bytes of the Interface Descriptor data. This field must have the same + alignment as the Interface Descriptor Data Start Address.It must be DQWord (32-byte) aligned. As the + Interface Descriptor data are sent directly to ROB, range is limited to CURBE Allocation Size. + Value Name Project + [32,1024] [1,32] interface descriptor entries +3 31:0 Interface Descriptor Data Start Address + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 57 + MEDIA_INTERFACE_DESCRIPTOR_LOAD + Project: All + Format: DynamicStateOffset[31:0]INTERFACE_DESCRIPTOR_DATA*32 + + + Description Project + This bit specifies the 32-byte aligned address of the Interface Descriptor data. This pointer is + relative to the Dynamics Base Address. + + + Value Name + [0,FFFFFFFFh] + + + Programming Notes Project + Driver must invalidate the vertex fetch cache thru the VF(address based) Cache Invalidation + Enable thru a + PIPE_CONTROL command prior to reusing the same graphics memory space. + + + + +1.8.4 INTERFACE_DESCRIPTOR_DATA +Interface Descriptor Data payload as pointed to by the Interface Descriptor Data Start Address: + + INTERFACE_DESCRIPTOR_DATA + +Default 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x00000000 +DWord Bit Description +0 31:6 Kernel Start Pointer + Project: All + Format: InstructionBaseOffset[31:6]Kernel + Specifies the 64-byte aligned address offset of the first instruction in the kernel. This pointer is relative + to the Instruction Base Address. + + 5:0 Reserved + Project: All + Format: MBZ +1 31:19 Reserved + Project: All + Format: MBZ + 18 Single Program Flow (SPF) + Specifies whether the kernel program has a single program flow (SIMDnxm with m = 1) or multiple + program flows (SIMDnxm with m > 1). + Value Name + 0h Multiple Program Flow + 1h Single Program Flow + 17 Thread Priority + Specifies the priority of the thread for dispatch. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 58 + INTERFACE_DESCRIPTOR_DATA + Value Name + 0h Normal Priority + 1h High Priority + 16 Floating Point Mode + Specifies the floating point mode used by the dispatched thread. + Value Name + 0h Use IEEE-754 Rules + 1h Use alternate rules + 15:14 Reserved + Format: MBZ + 13 Illegal Opcode Exception Enable + Project: All + Format: Enable + This bit gets loaded into EU CR0.1[12] (note the bit # difference). See Exceptions and ISA Execution + Environment. + + 12 Reserved + Format: MBZ + 11 MaskStack Exception Enable + Project: + Format: Enable + This bit gets loaded into EU CR0.1[11]. See Exceptions and ISA Execution Environment. + + 10:8 Reserved + Format: MBZ + 7 Software Exception Enable + Format: Enable + This bit gets loaded into EU CR0.1[13] (note the bit # difference). See Exceptions and ISA Execution + Environment. + + 6:0 Reserved + Format: MBZ +2 31:5 Sampler State Pointer + Format: DynamicStateOffset[31:5]SAMPLER_STATE + Specifies the 32-byte aligned address offset of the sampler state table. This pointer is relative to the + Dynamic State Base Address. + This field is ignored for child threads. + + 4:2 Sampler Count + Format: U3 + Specifies how many samplers (in multiples of 4) the kernel uses. Used only for prefetching the + associated sampler state entries. + This field is ignored for child threads. + If this field is not zero, sampler state is prefetched for the first instance of a root thread upon the startup + of the media pipeline. + Value Name + [0,4] + 0h No samplers used + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 59 + INTERFACE_DESCRIPTOR_DATA + 1h Between 1 and 4 samplers used + 2h Between 5 and 8 samplers used + 3h Between 9 and 12 samplers used + 4h Between 13 and 16 samplers used + 1:0 Reserved + Format: MBZ +3 31:16 Reserved + Project: + Format: MBZ + 15:5 Binding Table Pointer + Project: + Format: SurfaceStateOffset[15:5]BINDING_TABLE_STATE*256 + Specifies the 32-byte aligned address of the binding table. This pointer is relative to the Surface State + Base Address. + This field is ignored for child threads. + + 4:0 Binding Table Entry Count + Format: U5 + Specifies how many binding table entries the kernel uses. Used only for prefetching of the binding table + entries and associated surface state. + Note: The maximum number of prefetched binding table entries is limited to 31. For kernels using a + large number of binding table entries, it may be wise to set this field to zero to avoid prefetching too + many entries and thrashing the state cache. + This field is ignored for child threads. + If this field is not zero, binding table and surface state are prefetched for the first instance of a root + thread upon the startup of the media pipeline. + Value Name + [0,31] +4 31:16 Constant URB Entry Read Length + Format: U16 + Specifies the amount of URB data read and passed in the thread payload for the Constant or Indirect + URB entry, in 8-DW register increments. + A value 0 means that no Constant or Indirect URB Entry will be loaded. The Constant URB Entry Read + Offset field will then be ignored. + Value Name + [0,63] + 15:0 Constant URB Entry Read Offset + + Format: U16 + Specifies the offset (in 8-DW units) at which Constant URB data is to be read from the URB before + being included in the thread payload. + Value Name Description Project + [0,2015] indicating [0,2015] 256-bit register increments. ROB has 64KB of storage; 2048 + entries. However, lowest 32 entries are reserved for VFE/TS to store interface + descriptor data. Hence, URB Entry Read Offset plus Read Length shall not + exceed 2016. + [0, 479] +5 31:24 Reserved + Project: + Format: MBZ + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 60 + INTERFACE_DESCRIPTOR_DATA + 31:24 Barrier Return GRF Offset + Project: + Format: U8 + This field specifies the offset into the GRF that the barrier return byte will be written to. + Value Name + 0,127 + 23:22 Rounding Mode + Project: + Format: U2 + + + Value Name Description + 00b RTNE [Default] Round to Nearest Even + 01b RU Round toward +Infinity + 10b RD Round toward –Infinity + 11b RTZ Round toward Zero + 21 Barrier Enable + + Format: Enable + This field specifies whether the thread group requires a barrier. If not, it can be dispatched without + allocating one. + + 20:16 Shared Local Memory Size + + Format: U5 + This field indicates how much shared local memory the thread group requires. The amount is specified + in 4k blocks, but only powers of 2 are allowed: 0, 4k, 8k, 16k, 32k and 64k per half-slice. + Value Name Description + [0,16] Encodes 0k to 64k in powers of 2 + 15:8 Reserved + Project: + Format: MBZ + 15:8 Barrier Return Byte + Project: + Format: U8 + This field specifies the byte that will be returned by the gateway when the barrier is reached. + +6 31:0 Reserved + Project: + Format: MBZ +7 31:0 Reserved + Format: MBZ + + + + +1.8.5 MEDIA_STATE_FLUSH command +The MEDIA_STATE_FLUSH command is updated to specify all the resources required for the next thread +group via an interface descriptor – if the resources are not available the group cannot start. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 61 + Two MEDIA_STATE_FLUSH commands need to be used to ensure that the flush is complete. + + MEDIA_STATE_FLUSH + +Length Bias: 2 +This command updates the Message Gateway state. In particular, it updates the state for a selected Interface +Descriptor. + This command can be considered same as a MI_Flush except that only media parser will get flushed instead of the +entire 3D/media render pipeline. The command should be programmed prior to new Media state, curbe and/or +interface descriptor commands when switching to a new context or programming new state for the same context. + With this command, pipelined state change is allowed for the media pipe. + It should be cautious when using this command when child_present flag in the media state is enabled. This is +because that CURBE state as well as Interface Descriptor state are shared between root threads and child threads. +Changing these states while child threads are generated on the fly may cause unexpected behavior. + Combining with MI_ARB_ON/OFF command, it is possible to support interruptability with the following command +sequence where interrupt may be allowed only when MI_ARB_ON_OFF is ON: + MEDIA_STATE_FLUSH + VFE_STATE // VFE will hold CS if watermark isn't met + MI_ARB_OFF // There must be at least one VFE command before this one + MEDIA_OBJECT …. MI_ARB_ON +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h Media + Format: OpCode + 26:24 Media Command Opcode + Default Value: 0h + Format: OpCode + 23:16 SubOpcode A + Default Value: 4h MEDIA_STATE_FLUSH + Format: OpCode + 15:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Description + 0h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 31:9 Reserved + Project: All + Format: MBZ + 8 Disable Pre-emption + Project: + Format: Enable + This bit causes the video front-end to ignore pre-emption requests if set. If this bit is set then + ARB_CHECK commands should not be used with it. + A subsequent MEDIA_STATE_FLUSH command with this bit cleared will honor previous pre-emption + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 62 + MEDIA_STATE_FLUSH + requests. + + 7 Reserved + + Format: MBZ + 6 Watermark Required + Project: All + This is a single bit specifying if the MEDIA_STATE_FLUSH should stall further commands until there is + enough room in a half-slice for the following thread group. The characteristics of the thread group are + specified in the Interface Descriptor Offset. + If set, the MEDIA_STATE_FLUSH stalls CS until there are enough threads in a half-slice, and enough + SLM available in the same half-slice, and a free barrier if one is required. An Interface Descriptors can + be updated after a Watermarked MEDIA_STATE_FLUSH only if it has not been used in the current + context. Reusing an interface desciptor requires that this bit is clear to ensure the ID cache is reloaded. + If clear, the MEDIA_STATE_FLUSH stalls CS until the TDL has dispatched the last thread, allowing + the CURBE and Interface Descriptors to be updated by following commands. + Programming Notes Project + + + 5:0 Interface Descriptor Offset + Format: U5 + This field specifies the offset from the interface descriptor base pointer to the interface descriptor which + describes what resources are required to meet the watermark. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 63 + 1.8.6 MEDIA_OBJECT Command +The MEDIA_OBJECT command is the basic media primitive command for the media pipeline. It supports +loading of inline data as well as indirect data. At least one form of payload (either inline, indirect or +CURBE) must be sent with the MEDIA_OBJECT. + + MEDIA_OBJECT + +Length Bias: 2 +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Media Command Pipeline + Default Value: 2h Media + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h MEDIA_OBJECT + Format: OpCode + 23:16 Media Command Sub-Opcode + Default Value: 0h MEDIA_OBJECT + Format: OpCode + 15:0 DWord Length + Default Value: 4h DWORD_COUNT_n + Format: =n Total Length - 2 + + + Excludes DWords 0,1 + + Generic Mode: DWord Length = N+4, where N is in the range of [0,504]. The maximum is 504 DW + (equivalent to 63 8-DW registers). + When both inline and indirect data are fetched for this command, the total size in 8-DW registers must + be less than 112 + (with both inline data length N and indirect data length rounded up to 8-DW aligned individually). The + minimal inline data length is 0. + +1 7:6 Reserved + Format: MBZ + 5:0 Interface Descriptor Offset + Format: U5 + This field specifies the offset from the interface descriptor base pointer to the interface descriptor which + will be applied to + this object. It is specified in units of interface descriptors. + +2 31 Children Present + Format: Enable + Indicates that the root thread may send spawn messages to spawn child threads and/or synchronized + root threads. + If Children Present is not set, TS signals VFE to dereference the URB handle immediately after it + receives acknowledgement from TD that the thread is dispatched. + If Children Present is set, the URB handle is forwarded to the root thread and serves as the return + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 64 + MEDIA_OBJECT + URB handle for the root thread. TS does not signal deference at the time of dispatch. TS signals URB + handle deference only when it receives a resource dereference message from the thread. + In order avoid deadlock, such dereference must be issued once and only once for each URB handle. + + 30:25 Reserved + Format: MBZ + 24 Thread Synchronization + This field when set indicates that the dispatch of the thread originated from this command is based on + the “spawn root thread” message. + Value Name + 0 No thread synchronization + 1 Thread dispatch is synchronized by the “spawn root thread” message + 23 Reserved + Format: MBZ + 22 Reserved + + Format: MBZ + 21 Use Scoreboard + This field specifies whether the thread associated with this command uses hardware scoreboard. Only + when this field is set, the scoreboard control fields in the VFE Dword are valid. If this field is cleared, + the thread associated with this command bypasses hardware scoreboard. + Value Name + 0 Not using scoreboard + 1 Using scoreboard + 20 Reserved + + Format: MBZ + 19 Reserved + + Format: MBZ + 18:17 Half-Slice Destination Select + + This field selects the half slice that this thread must be sent to. + Value Name Description + 10b Half-Slice 1 Cannot be used in products without a Half-Slice 1. + 01b Half-Slice 0 + 00b Either half-slice Hardware will choose the slice based on load. + + + Programming Notes + If "Either half-slice" is selected then the Slice Destination Select must also specify "Either slice". + 16:0 Indirect Data Length + Format: U17 In bytes + + + This field provides the length in bytes of the indirect data. A value zero indicates that indirect data + fetching is disabled – subsequently, the Indirect Data Start Address field is ignored. + This field must have the same alignment as the Indirect Object Data Start Address. + It must be DQWord (32-byte) aligned. As the indirect data are sent directly to URB, range is limited to + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 65 + MEDIA_OBJECT + 496 DW. When both inline and indirect data are fetched for this command, the total size in 8-DW + registers must be less than 112 (with both inline data length and indirect data length rounded up to 8- + DW aligned). + +3 31:0 Indirect Data Start Address + Description Project + This field specifies the Graphics Memory starting address of the data to be loaded into the + kernel for processing. This pointer is relative to the Indirect Object Base Address. + + + Hardware ignores this field if indirect data is not present. + + + Alignment of this address depends on the mode of operation. + This field specifies the DWord aligned address of the indirect data. + + + Value Name + [0,512MB] + + + Programming Notes Project + Driver must invalidate the vertex fetch cache through the VF(address based) Cache + Invalidation Enable through a PIPE_CONTROL command prior to reusing the same graphics + memory space. + Bits 31:29 MBZ +4 31:25 Reserved + Format: MBZ + 24:16 Scoredboard Y + Format: U9 + This field provides the Y term of the scoreboard value of the current thread. + + 15:9 Reserved + Format: MBZ + 8:0 Scoreboard X + Format: U9 + This field provides the X term of the scoreboard value of the current thread. + +5 31:20 Reserved + Format: MBZ + 19:16 Scoreboard Color + Format: U4 + This field specifies which dependency color the current thread belongs to. It affects the dependency + scoreboard control. + + 15:8 Reserved + Format: MBZ + 7:0 Scoreboard Mask + Format: Boolean + Each bit indicates the corresponding dependency scoreboard is dependent on. This field is AND’d with + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 66 + MEDIA_OBJECT + the corresponding Scoreboard Mask field in the MEDIA_VFE_STATE command. + + Bit n (for n = 0…7): Scoreboard n is dependent, where bit 0 maps to n = 0. + +6..n 31:0 Inline Data + Generic Mode: The format of this data is specified by software. Hardware does not interpret this data; it + merely passes it to the kernel for processing. The total size for the inline data and indirect data must + not exceed 112 registers. + + + + +1.8.7 MEDIA_OBJECT_PRT Command + + MEDIA_OBJECT_PRT + +Length Bias: 2 +command is for generating Persistent Root Thread for the media pipeline. It only supports loading of inline data but +not indirect data. + This command should be used for a root thread that might have to be present in the system for a period longer than +the certain minimal context-switch interrupt latency. It has to honor the context interrupt signal to terminate upon +request. It should also handle replay from theinterrupted point upon context restore (the same thread being +dispatched more than once). In contrary, if a thread is not a Persistent Root Thread, if dispatched, it must run to +completion. + The command can be used in all VFE modes, except VLD mode. +For simplification, _PRT command has a fixed size of 16 DWORD +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h Media + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h + Format: OpCode + 23:16 SubOpcode + Default Value: 2h MEDIA_OBJECT_PRT + Format: OpCode + 15:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + Note: Regardless of the mode, inline data must be present in this command. The command size must + fit within 16 dwords. + Value Name Description + 14h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 31:6 Reserved + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 67 + MEDIA_OBJECT_PRT + Project: All + Format: MBZ + 5:0 Interface Descriptor Offset + Project: All + Format: U5 + This field specifies the offset from the interface descriptor base pointer to the interface descriptor which + will be applied to this object. It is specified in units of interface descriptors. + +2 31 Children Present + Project: All + Format: Enable + Indicates that the root thread may send spawn messages to spawn child threads and/or synchronized + root threads. + If Children Present is not set, TS signals VFE to dereference the URB handle immediately after it + receives acknowledgement from TD that the thread is dispatched. + If Children Present is set, the URB handle is forwarded to the root thread and serves as the return + URB handle for the root thread. TS does not signal deference at the time of dispatch. TS signals URB + handle deference only when it receives a resource dereference message from the thread. + In order avoid deadlock, such de-reference must be issued once and only once for each URB handle. + + 30:24 Reserved + Project: All + Format: MBZ + 23 PRT_Fence Needed + Project: All + Format: Enable + This field specifies that a PRT_Fence is generated after dispatching the thread associated with this + MEDIA_OBJECT_PRT. The PRT_Fence prevents additional threads following this persistent root + thread until a thread spawn message is sent. The PRT_Fence is generated on first dispatch of the + persistent root, as well as on re-dispatches of the persistent root after context restore. + + 22 PRT_FenceType + Project: All + This field specifies the type of fence the PRT thread uses. If this field is set to 0, the fence is set at the + end of the root thread queue. It will block the dispatch of the next root thread, but allowed these root + threads to be populated through VFE to the root thread queue in TS. If this field is set to 1, the fence is + set at the entry of VFE, similar to the fence set by the MEDIA_STATE_FLUSH command. No more + command can go into the media pipe until a thread spawn message is sent (by the PRT). + This field is only valid when PRT_Fence Needed is set to 1. Otherwise, it is ignored by hardware. + Value Name Description Project + 0h Root thread queue Root thread queue fence All + 1h VFE state flush VFE state flush fence All + 21:0 Reserved + Project: All + Format: MBZ +3 31:0 Reserved + Format: MBZ +4..15 31:0 Inline Data + Project: All + Format: U32 + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 68 + 1.8.8 MEDIA_OBJECT_WALKER Command +The MEDIA_OBJECT_WALKER command uses the hardware walker in VFE for generating threads +associated with a rectangular shaped object. It only supports loading of inline data or CURBE but not +indirect data. At least one form of payload must be sent. Control of scoreboards (up to 8) is implicit based +on the (X, Y) address of the generated thread and the scoreboard control state. +The command can be used only in Generic modes. +When Use Scoreboard field is set, the (X, Y) address and the Color field of the generated thread are +used in the hardware scoreboard and the thread dependencies are set by states from the +MEDIA_VFE_STATE command. +One or more threads may be generated by this command. This command doesn’t support indirect object +load. When inline data is present, it is repeated for all threads it generates. Unlike CURBE, which requires +pipeline flush for change, continued change of this kind of ‘global’ (in the sense of shared by multiple +threads from this command) data is supported when MEDIA_OBJECT_WALKER commands are issued +without a pipeline flush in between. + + MEDIA_OBJECT_WALKER + +Length Bias: 2 +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h Media + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h + Format: OpCode + 23:16 SubOpcode + Default Value: 03h MEDIA_OBJECT_WALKER + Format: OpCode + 15:0 DWord Length + Default Value: Eh DWORD_COUNT_n + Project: All + Format: =n Total Length - 2 + + + Note: If this field is greater than 15, it indicates that inline data is present. If present, inline data is + common for all threads generated from this command, If this field is 15, it indicates that inline data is + not present. It should be noted that unlike other media object command, inline data is optional for this + command. + +1 7:6 Reserved + Format: Reserved + 5:0 Interface Descriptor Offset + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 69 + MEDIA_OBJECT_WALKER + Format: U5 + This field specifies the offset from the interface descriptor base pointer to the interface descriptor which + will be applied to this object. It is specified in units of interface descriptors. + +2 31 Children Present + Format: Enable + Indicates that the root thread may send spawn messages to spawn child threads and/or synchronized + root threads. + If Children Present is not set, TS signals VFE to dereference the URB handle immediately after it + receives acknowledgement from TD that the thread is dispatched. + If Children Present is set, the URB handle is forwarded to the root thread and serves as the return + URB handle for the root thread. TS does not signal deference at the time of dispatch. TS signals URB + handle deference only when it receives a resource dereference message from the thread. + In order avoid deadlock, such dereference must be issued once and only once for each URB handle. + + 30:25 Reserved + Format: MBZ + 24 Thread Synchronization + This field when set indicates that the dispatch of the thread originated from this command is based on + the “spawn root thread” message. + Value Name + 0 No thread synchronization + 1 Thread dispatch is synchronized by the “spawn root thread” message + 23:22 Reserved + + Format: MBZ + 21 Use Scoreboard + This field specifies whether the thread associated with this command uses hardware scoreboard. Only + when this field is set, the scoreboard control fields in the VFE Dword are valid. If this field is cleared, + the thread associated with this command bypasses hardware scoreboard. + Value Name + 0 Not using scoreboard + 1 Using scoreboard + 20:17 Reserved + Format: MBZ + 16:0 Indirect Data Length + Format: U17 in bytes + + + This field provides the length in bytes of the indirect data. A value zero indicates that indirect data + fetching is disabled – subsequently, the Indirect Data Start Address field is ignored. + This field must have the same alignment as the Indirect Object Data Start Address. + It must be DQWord (32-byte) aligned. As the indirect data are sent directly to URB, range is limited to + 496 DW. When both inline and indirect data are fetched for this command, the total size in 8-DW + registers must be less than or equal to 63 (with both inline data length and indirect data length rounded + up to 8-DW aligned). + +3 31:0 Indirect Data Start Address + Description Project + This field specifies the Graphics Memory starting address of the data to be loaded into the + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 70 + MEDIA_OBJECT_WALKER + kernel for processing. This pointer is relative to the Indirect Object Base Address. + Hardware ignores this field if indirect data is not present. + Alignment of this address depends on the mode of operation. + It is the DWord aligned address of the indirect data. + + + Value Name Description + [0 - 512MB] (Bits 31:29 MBZ) +4 31:0 Reserved + Format: MBZ +5 7:0 Scoreboard Mask + Format: Boolean + Each bit indicates the corresponding dependency scoreboard is dependent on. This field is AND’d with + the corresponding Scoreboard Mask field in the MEDIA_VFE_STATE. All threads generated by this + walker command share the same dynamic mask. + Bit n (for n = 0…7): Scoreboard n is dependent, where bit 0 maps to n = 0. + +6 31 Dual Mode + Project: + Format: Boolean + + + Programming Notes Project + Dual mode should be used in products that have 2 half-slices. + 30 Repel + + Format: Boolean + + + Programming Notes + Repel should not be combined with either Dual Mode or Quad Mode. + 29 Reserved + + Format: MBZ + 28 Reserved + Format: MBZ + 27:24 Color Count Minus One + Format: U4 + This field specifies the number of repeat of the inner most loop of the walker. Each repeated walk + position is assigned with an incremental Color number. The Color number together with the X and Y + position of the thread is used for dependency scoreboard control. + Usage Example: This allows multiple sets of dependency threads to be dispatched. + + 23:21 Reserved + Format: MBZ + 20:16 Middle Loop Extra Steps + Format: U5 + 15:14 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 71 + MEDIA_OBJECT_WALKER + 13:12 Local Mid-Loop Unit Y + Format: S1 + 11:10 Reserved + Format: MBZ + 9:8 Mid-Loop Unit X + Format: S1 + 7:0 Reserved + Format: MBZ +7 31:26 Reserved + Format: MBZ + 25:16 Global Loop Exec Count + Format: U10 + 15:10 Reserved + Format: MBZ + 9:0 Local Loop Exec Count + Format: U10 +8 31:25 Reserved + Format: MBZ + 24:16 Block Resolution Y + Format: U9 + Vertical resolution of the local loop. + + 15:9 Reserved + Format: MBZ + 8:0 Block Resolution X + Format: U9 + Horizontal resolution of the local loop. + +9 31:25 Reserved + Format: MBZ + 24:16 Local Start Y + Format: U9 + Starting vertical position of the local loop. + + 15:9 Reserved + Format: MBZ + 8:0 Local Start X + Format: U9 + Starting horizontal position of the local loop. + +10 31:25 Reserved + Format: MBZ + 24:16 Local End Y + + Format: U9 + Ending vertical position of the local loop. + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 72 + MEDIA_OBJECT_WALKER + 15:9 Reserved + Format: MBZ + 8:0 Local End X + + Format: U9 + Ending horizontal position of the local loop. + +11 31:26 Reserved + Format: MBZ + 25:16 Local Outer Loop Stride Y + Format: S9 + Vertical stride of the local outer loop, in 2’s complement. + + 15:10 Reserved + Format: MBZ + 9:0 Local Outer Loop Stride X + Format: S9 + Horizontal stride of the local outer loop, in 2’s complement. + +12 31:26 Reserved + Format: MBZ + 25:16 Local Inner Loop Unit Y + Format: S9 + Vertical stride of the local inner loop, in 2’s complement. + + 15:10 Reserved + Format: MBZ + 9:0 Local Inner Loop Unit X + Format: S9 + Horizontal stride of the local inner loop, in 2’s complement. + +13 31:25 Reserved + Format: MBZ + 24:16 Global Resolution Y + Format: U9 + Vertical resolution of the global loop. + + 15:9 Reserved + Format: MBZ + 8:0 Global Resolution X + Format: U9 + Horizontal resolution of the global loop. + +14 31:26 Reserved + Format: MBZ + 25:16 Global Start Y + Format: S9 + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 73 + MEDIA_OBJECT_WALKER + Starting vertical location of the global loop, in 2’s complement. + + 15:10 Reserved + Format: MBZ + 9:0 Global Start X + Format: S9 + Starting horizontal location of the global loop, in 2’s complement. + +15 31:26 Reserved + Format: MBZ + 25:16 Global Outer Loop Stride Y + Format: S9 + Vertical stride of the global outer loop, in 2’s complement. + + 15:10 Reserved + Format: MBZ + 9:0 Global Outer Loop Stride X + Format: S9 + Horizontal stride of the global outer loop, in 2’s complement. + +16 31:26 Reserved + Format: MBZ + 25:16 Global Inner Loop Unit Y + Format: S9 + Vertical stride of the global inner loop, in 2’s complement. + + 15:10 Reserved + Format: MBZ + 9:0 Global Inner Loop Unit X + Format: S9 + Horizontal stride of the global inner loop, in 2’s complement. + +17..n 31:0 Inline Data + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 74 + 1.8.9 GPGPU_OBJECT +This command is modified from the MEDIA_OBJECT command. + + GPGPU_OBJECT + +Length Bias: 2 + Programming Notes +If the threads spawned by this command are required to observe memory writes performed by threads spawned +from a previous command, software must precede this command with a command that performs a memory flush +(e.g., MI_FLUSH). +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h Media + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h + Format: OpCode + 23:16 SubOpcode + Default Value: 04h MEDIA_ + Format: OpCode + 15:9 Reserved + Project: All + Format: MBZ + 8 Predicate Enable + Project: All + Format: U1 + If set, this command is executed (or not) depending on the current value of the MI Predicate internal + state bit. This command is ignored only if PredicateEnable is set and the Predicate state bit is 0. + + 7:0 DWord Length + Format: =n Total Length -2 + + + There are 4 DW needed to specify the Thread Group ID and the execution mask. + Value Name Description + 6h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 7 Shared Local Memory Fixed Offset + This bit, if set, specifies that the offset into the 64k Shared Local Memory for the current thread group is + specified by software in the Shared Local Memory Offset field. + Value Name Description + 0 Thread Groups Offset Offset to start of segment determined by hardware based on concurrently + running thread groups. + 1 Shared Local Memory Offset to start of the Shared Local Memory segment supplied in Shared + Offset Local Memory Offset + 6 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 75 + GPGPU_OBJECT + Format: MBZ + 5:0 Interface Descriptor Offset + Format: U5 + This field specifies the offset from the interface descriptor base pointer to the interface descriptor which + will be applied to this object. It is specified in units of interface descriptors.In VLD mode, this field is + ignored by hardware. + +2 31:28 Shared Local Memory Offset + Format: U4 + + + Description Project + If the Shared Local Memory Fixed Offset is set, this field provides the offset to the start of the + Shared Local Memory for this thread group. The value of this field is multiplied by 4k to get the + starting address. All threads in the thread group must have the same value. + Offset must be aligned with Shared Local Memory Size of the thread group. + 27:25 Reserved + Project: All + Format: MBZ + 24 End of Thread Group + Project: + This bit indicates that this dispatch is the last for the current thread group. + + 23:20 Reserved + Project: All + Format: MBZ + 19 Reserved + Project: + Format: MBZ + 18:17 Half-Slice Destination Select + This field selects the half slice that this thread must be sent to. + Value Name Description + 10b Half-Slice 1 Cannot be used in products without a Half-Slice 1. + 01b Half-Slice 0 + 00b Either Half-Slice Hardware will choose the slice based on load. + 16:0 Indirect Data Length + Format: U17 in bytes + + + This field provides the length in bytes of the indirect data. A value zero indicates that indirect data + fetching is disabled – subsequently, the Indirect Data Start Address field is ignored. Thread IDs + This field must have the same alignment as the Indirect Object Data Start Address. + It must be DQWord (32-byte) aligned. As the indirect data are sent directly to URB, range is limited to + 496 DW. When both inline and indirect data are fetched for this command, the total size in 8-DW + registers must be less than or equal to 63 (with both inline data length and indirect data length rounded + up to 8-DW aligned). + +3 31:0 Indirect Data Start Address + This field specifies the Graphics Memory starting address of the data to be loaded into the kernel for + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 76 + GPGPU_OBJECT + processing. This pointer is relative to the Indirect Object Base Address. + Hardware ignores this field if indirect data is not present. + The start address is a 64-byte aligned address. + (Bits 31:29 MBZ) + Value Name + [0,512MB) +4 31:0 Thread Group ID X + This is the X coordinate of the group id. +5 31:0 Thread Group ID Y + This is the Y coordinate of the group id for all channels generated by this command. +6 31:0 Thread Group ID Z + This is the Z coordinate of the thread group id. +7 31:0 Execution Mask + This provides a bit per channel enable for the SIMD32 dispatch. The LSB of the Mask enables the + execution of SIMD32 channel 0; the remaining bits enable the corresponding channel numbers. + SIMD16 and SIMD8 dispatches should use the LSB bits of the mask. Any disabled channel will not + read or write data to memory. + + + + +1.8.10 GPGPU_WALKER Command + + GPGPU_WALKER + +Length Bias: 2 + Programming Notes +If the threads spawned by this command are required to observe memory writes performed by threads spawned +from a previous command, software must precede this command with a command that performs a memory flush +(e.g., MI_FLUSH). +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h Media + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h + Format: OpCode + 23:16 SubOpcode A + Default Value: 05h + Format: OpCode + 15:11 Reserved + Project: All + Format: MBZ + 10 Indirect Parameter Enable + Project: All + Format: U1 + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 77 + GPGPU_WALKER + If set, the values in DW 4, 6, 8 are ignored and replaced by the current values of the corresponding + GPGPU_xxx MMIO registers: + + +  + GPGPU_DISPATCHDIMX (instead of DW4) +  + GPGPU_DISPATCHDIMY (instead of DW6) +  + GPGPU_DISPATCHDIMZ (instead of DW8) + + + 9 Reserved + Project: All + Format: MBZ + 8 Predicate Enable + Project: All + Format: U1 + If set, this command is executed (or not) depending on the current value of the MI Predicate internal + state bit. This command is ignored only if PredicateEnable is set and the Predicate state bit is 0. + + 7:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Description + 9h DWORD_COUNT_n [Default] Allowed value is 9 +1 7:6 Reserved + Project: All + Format: MBZ + 5:0 Interface Descriptor Offset + Format: U5 + This field specifies the offset from the interface descriptor base pointer to the interface descriptor which + will be applied to this object. It is specified in units of interface descriptors. + +2 31:30 SIMD Size + This field determines the size of the payload and the number of bits of the execution mask that are + expected. The kernel pointed to by the interface descriptor should match the SIMD declared here. + Value Name Description + 0 SIMD8 8 LSBs of the execution mask are used + 1 SIMD16 16 LSBs used in execution mask + 2 SIMD32 32 bits of execution mask used + 29:22 Reserved + Project: All + Format: MBZ + 21:16 Thread Depth Counter Maximum + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 78 + GPGPU_WALKER + The maximum value of the thread depth counter. + Thread_Depth_Max*Thread_Height_Max*Thread_Width_Max <= 32 for SIMD32, <= 64 for SIMD16 + and SIMD8 + 15:14 Reserved + Project: All + Format: MBZ + 13:8 Thread Height Counter Maximum + The maximum value of the thread height counter + 7:6 Reserved + Project: All + Format: MBZ + 5:0 Thread Width Counter Maximum + The maximum value of the thread width counter +3 31:0 Thread Group ID Starting X + This is the initial value of the X component of the thread group. When X reaches the maximum value it + rolls around to 0, not to this value. +4 31:0 Thread Group ID X Dimension + The X dimension of the thread group (maximum X is dimension -1) +5 31:0 Thread Group ID Starting Y + This is the initial value of the Y component of the thread group. When Y reaches the maximum value it + rolls around to 0, not to this value. +6 31:0 Thread Group ID Y Dimension + The Y dimension of the thread group (maximum Y is dimension -1) +7 31:0 Thread Group ID Starting Z + This is the initial value of the Z component of the thread group +8 31:0 Thead Group ID Z Dimension + The Z dimension of the thread group (maximum Z is dimension -1) +9 31:0 Right Execution Mask +10 31:0 Bottom Execution Mask + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 79 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V2 Pt 2 – 05 12 5/31/2012 80 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol2_part3.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol2_part3.txt new file mode 100644 index 0000000..12b95c9 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol2_part3.txt @@ -0,0 +1,11351 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 2 Part 3: Multi-Format Transcoder – MFX +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.1 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. 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Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 2 + Contents +1. MFX Introduction ................................................................................................................................... 5 + 1.1 MFD Overview ..................................................................................................................................... 5 + 1.1.1 MFD Memory Interface ................................................................................................................... 8 + 1.1.2 MFD Codec-Specific Commands ................................................................................................... 9 + 1.2 MFC Overview ..................................................................................................................................... 9 + 1.2.1 Example Usage Model ................................................................................................................. 10 + 1.2.2 Sample Algorithmic Flow .............................................................................................................. 11 + 1.2.3 Synchronization Mechanism......................................................................................................... 13 + 1.2.4 Restrictions ................................................................................................................................... 14 + 1.3 MFX State Model ............................................................................................................................... 14 + 1.4 MFX Interruptability Model ................................................................................................................. 15 + 1.5 MFX Programming Restrictions ......................................................................................................... 15 + 1.5.1 All Codecs..................................................................................................................................... 15 + 1.6 MFX Codec Commands Summary .................................................................................................... 16 + 1.6.1 MFX Decoder Commands Sequence ........................................................................................... 19 + 1.7 MFX Pipe Common Commands ........................................................................................................ 22 + 1.7.1 MFX_WAIT Command ................................................................................................................. 22 + 1.7.2 MFX_STATE_POINTER Command ............................................................................................. 23 + 1.7.3 MFX_PIPE_MODE_SELECT ....................................................................................................... 25 + 1.7.4 MFX_SURFACE_STATE Command ........................................................................................... 30 + 1.7.5 MFX_PIPE_BUF_ADDR_STATE Command ............................................................................... 37 + 1.7.6 MFX_IND_OBJ_BASE_ADDR_STATE Command...................................................................... 44 + 1.7.7 MFX_PAK_INSERT_OBJECT ..................................................................................................... 50 + 1.7.8 MFX_STITCH_OBJECT ............................................................................................................... 53 + 1.7.9 MFX_QM_STATE Command ....................................................................................................... 55 + 1.7.10 MFX_FQM_STATE Command ................................................................................................... 57 +2. AVC (H.264) .......................................................................................................................................... 60 + 2.1 AVC Common Commands ................................................................................................................. 60 + 2.1.1 MFX_AVC_IMG_STATE Command ............................................................................................ 60 + 2.1.2 MFX_AVC_DIRECTMODE_STATE Command ........................................................................... 73 + 2.1.3 MFX_AVC_SLICE_STATE Command ......................................................................................... 77 + 2.1.4 MFX_AVC_REF_IDX_STATE Command .................................................................................... 87 + 2.1.5 MFX_AVC_WEIGHTOFFSET_STATE Command....................................................................... 89 + 2.2 AVC Decoder Commands .................................................................................................................. 91 + 2.2.1 MFD_AVC_DPB_STATE Command ............................................................................................ 91 + 2.2.2 MFD_AVC_SLICEADDR Command ............................................................................................ 93 + 2.2.3 MFD_AVC_BSD_OBJECT Command ......................................................................................... 94 + 2.3 AVC Encoder PAK Commands ........................................................................................................ 100 + 2.3.1 MFC_AVC_PAK_OBJECT Command ....................................................................................... 100 + 2.4 AVC Encoder MBAFF Support ........................................................................................................ 139 +3. MPEG-2 ............................................................................................................................................... 141 + 3.1 MPEG2 Common Commands ......................................................................................................... 141 + 3.1.1 MFX_MPEG2_PIC_STATE Command ...................................................................................... 141 + 3.2 MPEG2 Decoder Commands .......................................................................................................... 150 + 3.2.1 MFD_MPEG2_BSD_OBJECT Command (pipeline) .................................................................. 150 +4. JPEG ................................................................................................................................................... 154 + 4.1 JPEG Decoder Commands .............................................................................................................. 154 + 4.1.1 MFD_JPEG_BSD_OBJECT Command ..................................................................................... 154 + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 3 + 4.1.2 MFX_JPEG_PIC_STATE Decoder ............................................................................................ 156 + 4.1.3 MFX_JPEG_HUFF_TABLE_STATE .......................................................................................... 160 +5. More Decoder and Encoder.............................................................................................................. 162 + 5.1 MFD IT Mode Decode Commands .................................................................................................. 162 + 5.1.1 MFD_IT_OBJECT Command ..................................................................................................... 162 + 5.2 Session Decoder StreamOut Data Structure ................................................................................... 183 + 5.3 Decoder Input Bitstream Formats .................................................................................................... 192 + 5.3.1 AVC Bitstream Formats – DXVA Short ...................................................................................... 192 + 5.3.2 AVC Bitstream Formats – DXVA Long ....................................................................................... 192 + 5.3.3 AVC Bitstream Formats – Intel Long .......................................................................................... 192 + 5.3.4 VC1 Bitstream Formats – Intel Long .......................................................................................... 192 + 5.3.5 MPEG2 Bitstream Formats – DXVA1 ......................................................................................... 192 + 5.3.6 JPEG Bitstream Formats – Intel ................................................................................................. 192 + 5.4 Concurrent, Multiple Video Stream Decoding Support .................................................................... 193 +6. Encoder StreamOut Mode Data Structure Definition .................................................................... 194 + 6.1 PAK Multi-Pass ................................................................................................................................ 195 + 6.2 Driver Usage .................................................................................................................................... 196 +7. Programming Reference................................................................................................................... 197 + 7.1 Monochrome Picture Processing ..................................................................................................... 197 + 7.2 Context Switch ................................................................................................................................. 197 + 7.3 Pipeline Flush ................................................................................................................................... 197 + 7.4 MMIO Interface ................................................................................................................................ 197 + 7.4.1 Decoder Registers ...................................................................................................................... 199 + 7.4.2 Encoder Registers ...................................................................................................................... 211 + 7.4.3 MFC_BITSTREAM_BYTECOUNT_FRAME — Reported Bitstream Output Byte Count per + Frame 212 + 7.4.4 MFC_BITSTREAM_SE_BITCOUNT_FRAME (Reported Bitstream Output Bit Count for + Syntax Elements Only) ........................................................................................................................... 212 + 7.4.5 MFC_AVC_CABAC_BIN_COUNT_FRAME (Reported Bitstream Output CABAC Bin Count) . 213 + 7.4.6 MFC_AVC_CABAC_INSERTION_COUNT — Reported Bitstream Output CABAC Insertion + Count 214 + 7.4.7 MFC_AVC_MINSIZE_PADDING_COUNT — Reported Bitstream Output Minimal Size + Padding Count ........................................................................................................................................ 214 + 7.5 MFC_IMAGE_STATUS_MASK ....................................................................................................... 215 + 7.5.1 MFC_IMAGE_STATUS_CONTROL .......................................................................................... 215 + 7.5.2 MFC_QUP_CT - MFC QP Status Count .................................................................................... 216 + 7.5.3 MFC_BITSTREAM_BYTECOUNT_SLICE — Bitstream Output Byte Count per Slice.............. 217 + 7.5.4 MFC_BITSTREAM_SE_BITCOUNT_SLICE — Bitstream Output Bit Count for the last Syntax + Element ................................................................................................................................................... 217 + 7.6 Row Store Sizes and Allocations ..................................................................................................... 218 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 4 + 1. MFX Introduction + + + + +Multi-Format Codec (MFX) Engine is the hardware fixed function pipeline for decode and encoding. It +includes multi-format decoding (MFD) and multi-format encoding (MFC). + + +1.1 MFD Overview +When used for decoding, we refer to the MFX Engine also as the MFD Engine. +The Multi-Format Decoder (MFD) is a hardware fixed function pipeline for decoding the three video codec +formats and one image compression codec format : AVC (H.264), VC-1, MPEG2 and JPEG. + + • Compliant to next generation high definition optical video disc requirements (e.g. ) with sufficient + performance headroom + o Support AVC 4:2:0 Main and High (8-bit only) Profile only (no support for Baseline, + Extended and High-10 Profiles), up to Level 5.1 (max 983,040 MB/s, max 36,864 + MB/frame, and at most one dimension can reach 4K pixel) resolution and up to 40 + mbps bitstream. With sufficient duty cycles, higher bit rate contents can also be + decoded. +  Allow a B-picture (frame or field) as a reference picture +  MVC is supported by AVC Long Format. All MVC specific functions are taken + care of by the Application. + o Support VC1 4:2:0 Simple, Main and Advanced Profiles, up to Level 4 (max 491,520 + MB/s and max 16,384 MB/frame; max only one dimension will be at 4K pixel) + resolution and up to 40 mbps bitstream. With sufficient duty cycles, higher bit rate + contents can also be decoded. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 5 +  Allow a B-field as a reference picture only in interlaced field decoding, no + other modes. + o Support MPEG2 HD Main Profile (4:2:0), up to High Level (1920x1152 pixels) and up + to 80 mbps bitstream. With sufficient duty cycles, higher bit rate contents can also be + decoded. No support for SNR and spatial-scalability. +  Does not support B-picture as a reference picture. + o Support Baseline JPEG with five choma types (4:0:0, 4:1:1, 4:2:2, 4:2:0, and 4:4:4. No + support for Extended DCT-based mode, Progressive mode, Loseless mode, nor + Hierarchical mode +  H/W support 64Kx64K, but Surface State can support only up to 16kx16k + + Features Supported Unsupported + +Coding + Baseline sequential mode: Extended DCT-based mode, Lossless, +processes + Hierarchical modes: + • 8-bit pixel precision of source images + • loadable 2 AC and 2 DC Huffman tables More than 8 bit pixel resolution, progressive + mode, arithmetic coding, 4 AC and 4 DC Huffman + • 3 loadable quantization matrix for Y, U, V tables (extended mode), predictive process + • Interleaved and non-interleaved Scans (lossless), multiple frames (hierarchical) + • Single and multiple Scans + + 4-th channel (usually alpha blending image) +Number of 1 for grey image +image 3 for Y, Cb, Cr color image +channels +Image Arbitrary image size up to 16K * 16K Larger than 16K * 16K (64K * 64K is max. in the +resolution JPEG standard) +Chroma Any other arbitrary ratio, e.g., 3:1 subsampled + Chroma 4:0:0 (grey image) +subsampling chroma +ratio Chroma 4:1:1 + Chroma 4:2:0 + Chroma horizontal 4:2:2 + Chroma vertical 4:2:2 + Chroma 4:4:4 +Additional Image rotation: 90/180/270 degrees +feature (post- +processing) + o H/W does not impose restriction on picture frame aspect ratio, but is bounded by a + max 256 MBs (4096 pixels) per dimension programmable at the H/W interface + specifications. +  For example, supporting HD video resolution 1920x1080/60i, 1920x1080/24p, + 1280x720/60p + + • Performance requirements with MFX core frequency above 1GHz + o Real-time performance around 10% duty cycle + o Support concurrently decoding of at least two active HD bitstreams of different formats + (For example, one AVC and one VC1 HD bitstream) + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 6 + • The parsing of transport layer and sequence layer is not performed in this hardware, and is required + to be done in the host software. We have added the parsing of Slice Header for AVC and the + Picture+Slice Header for VC1. + • The MFD hardware pipeline is operated concurrently with and independently from the Graphics + (3D/Media) pipeline with separate command streamer. The two parallel engines are designed with + the similar command protocol. They can be executed in parallel with different context. + • Local storages and buffers along the hardware pipeline are kept at minimum. For example, there is + no on-die row-store memory. They are resided on the system memory. MFD is designed to hide the + memory access latency (in both the row stores and in the motion compensation units) in maximizing + its decoding throughput. + • Support the following operating modes + o VLD mode – operation starts from entropy decoding of the compressed bit stream + (parsing Slice Header and Slice Data Layer in AVC, Picture layer, Slice layer and MB + Layer in VC-1, and MB-layer in MPEG2), all the way, to the reconstruction of display + picture, including in-loop , if any. +  Streamout mode – a new feature of the VLD mode in assisting transcoding + during decoding. Selected uncompressed data (e.g. per MB MV information) + will be sent out to the EU and the ME engine (resided on the Sampler of the + 3D Gx Pipeline) for encoding into a different format or for the purpose of + transcaling and transrating. In addition, the uncompressed result may + continue to be processed by the rest of pipeline as in VLD mode to generate + the display picture for transcoding. That is, while intermediate data are + streaming out to the memory, the MFD Engine continues its decoding as + ususal. +  For JPEG, only VLD mode is supported (No IT mode). Host software decodes + Frame and Scan layers (down to Scan header in the JPEG bit stream syntax) + and sends all the corresponding information and Scan payload to the MFD + hardware pipeline. + o IT mode – when host software has already performed all the bit stream parsing of the + compressed data and packaging the uncompressed result into a specific format (as a + sequence of per-MB record) stored in memory. The hardware pipeline will fetch one + MB record at a time and perform the rest of the decoding process as in VLD mode + o Host software (Application) is responsible for parsing and decoding all the transport + and program layers, and all sequence layers. These parameters are passed to Driver + and forwarded to H/W as needed through different STATE commands. Host software + is also responsible for separating non-video data (audio, meta and user data) from + sending to H/W. +  MFD Engine is only responsible for macro-block and block layers decoding, + plus certain level of header decoding. For AVC MFD starts decoding from + Slice Header; for VC1, MFD starts decoding from Picture Header, and for + MPEG2 decoding starts from MB Layer only. +  For JPEG, MFD is responsible for ECS and block layers decoding. + + • Support bitstream formats (compressed video data) for each codec + o AVC – 2 formats +  DXVA2 AVC Short Slice Format Specification (new in) +  DXVA2 AVC Long Slice Format Specification + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 7 + o MVC – 2 formats +  DXVA2 AVC Long Slice Format Specification (exactly the same as AVC) + o VC1 – 2 formats +  DXVA2 VC1 Specification (new in) + + • Fully compliant to Picture Parameter and Slice Control Parameter + interface definition + o MPEG2 +  MB Layer only, according to DXVA 1 Specification + o JPEG +  Intel proprietary format (new in) this generation. +  ECS Layer + + • The MFX codec is designed to be a stateless engine, that it does not retain any history of settings + (states) for the encoding/decoding process of a picture. Hence, driver must issue the full set of MFX + picture state command sequence prior to process each new picture. In addition, driver must issue + the full set of Slice state command sequence prior to process a slice. + o In particularly, RC6 always happens between frame boundaries. So at the beginning + of every frame, all state information needs to be programmed. There is no state + information as part of media context definition. + + • To activate the AVC deblocker logic for incoming uncompressed 4:2:0-only video stream, one can + pack the uncompressed video stream to compliant with the IPCM MB data format (including ILDB + control information) and feed them into the MFD engine in IT mode. Since the MFD Engine is in + IPCM mode, transformation, inter and intra processing are all inactive. + +Start Code Detection and removal are done in the CPU, but the Start Code Emulation Prevention Byte is +detected and removed by the front end logic in the MFD. The bitstream format for each codec and for +each mode is specified in this document. +Codec specific information are based on the following released documents from third parties : + + • Draft of Version 4 of H.264/AVC (ITU-T Recommendation H.264 and ISO/IEC 14496-10 (MPEG-4 + part 10) Advanced Video Coding); JVT-O205d1.doc; dated 2005-05-30 + • Final Draft SMPTE Standard : VC1 Compressed Video Bitstream Format and Decoding Process, + SMPTE 421M, dated 2006-1-6; PDF file. + • MPEG2 Recommendation ITU T H.262 (1995 E), ISO/IEC 13818-2: 1995 (E); doc file. + • Digital Compression and Coding of Continuous-tone Still Images, ITU-T Rec. T.81 and ISO/IEC + 10918-1: Requirements and guidelines September 18 1992; itu-t81[1].pdf + + +1.1.1 MFD Memory Interface +The Memory Arbitrator follows the pre-defined arbitration policy (as indicated in the following listing P0 to +P11, in which P0 is the highest priority) to select the next memory request to service, then it will perform +the TLB translation (translation to physical address in memory), and make the actual request to memory. +The Memory Arbitration unit is also responsible for capturing the return data from memory (read request) +and forward it to the appropriate unit along the MFD Engine. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 8 + • Read streams: (all 64B requests) + o Commands for BSD : linear ( including indirect data) (P0) + o Indirect DMA (P1) + o Row store for BSD: linear (P5) + o Row store for MPR: linear (P6) + o MC ref cache fetch : tiled (P2) + o Intra row store: linear (P9) + o ILDB row store: linear (P10) + + • Write streams: (all 64B requests) + o Row store write for BSD: linear and can avoid partial writes (P3) + o Row store write for MPR: linear and can avoid partial writes (P4) + o Intra row store write: linear and can avoid partial writes (P7) + o ILDB row store write: linear and can avoid partial writes (P8) + o Final dest writes: tiled and can potentially be partial, two ways to avoid these + partials: 1) either write garbage and buffers are aligned or 2) read-modify + writes for dribble end of line cases (P11) + + +1.1.2 MFD Codec-Specific Commands +MFD hardware pipeline supports 3 different codec standards : AVC, VC1 and MPEG2. To make the +interface flexible, each codec is designed with its own set of commands. +There are two categories of commands for each codec format : one set for VLD mode and one set for IT +mode. + + +1.2 MFC Overview +Multi-Format Codec (MFX) Engine is the hardware fixed function pipeline for decode and encoding. It +includes multi-format decoding (MFD) and multi-format encoding (MFC). Many decoding function blocks +in MFD such as VIP, VMC, IQT, etc, are also used in encoding mode. Two blocks FTQ and BSE are +encoding only. +The encoding process is partitioned across host software, GPE engine and the MFX engine. The +generation of transport layer, sequence layer, picture layer and slice header layer is required to be done +in the host software. GP hardware is responsible for compressing from Slice Data Layer down to all +macro-block and block layers. Specifically, GPE w/ VME acceleration is for motion vector estimation, +motion estimation, and code decision. The VME(>Video Motion Estimation) is located next to all image +processing units, such as DN (denoise) and DI (deinterlace) in sampler in GPE. MFX is for final bit +packing and reconstructed picture generation. +MFC is operated concurrently with and independently from the GPE (3D/Media) pipeline with separate +command streamer. The two parallel engines have similar command protocol. They can be executed in +parallel with different context. For encoding, motion search, MB mode decision and rate control are +performed using GPE pipeline resources. +MFC is implemented to achieve the following objectives. + + • Compliant to next generation high definition optical video disc requirements (e.g. ) with sufficient + performance headroom + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 9 + o Support AVC 4:2:0 Main Profile and High Profile only (8-bit only), up to Level 4.1 + resolution and up to 40 mbps bitstream. With sufficient duty cycles, higher bit rate + contents can also be encoded. There is no support for Baseline, Extended and High- + 10 Profiles. + + • Performance requirements with MFX core frequency above 667MHz + o Real-time performance with 20% duty cycle or less + o Support concurrently decoding of two active HD bitstreams of different formats (For + example, one AVC and one VC1 HD bitstream) and one active HD encoding. + +As the result of this hardware partitioning, VPP and ENC are always running in GPE, and PAK is what +runs exactly in MFC. +PAK – residue packing and entropy coding, including block transformation, quantization, data prediction, +bitrate tuning and reference decoding. It delivers final packed bitstream and decoded key-frame +reference. + + • As the same as ENC, PAK is invoked on a Slice boundary; a single call of + VPP can lead to multiple calls for PAK. + • Rate control is inside ENC and PAK only, not in VPP + • PAK must always perform with reconstructed reference picture + +There is a general dependency of the three operation pipelines. Semaphores are inserted either +according to frames or slices. The main CS will also be notified when the decoded reference is ready for +the next frame set to be encoded. The detailed discussion will be found in a later section. +Host software is responsible for encoding the transport stream and all the sequence, picture and slice +layer/header in the bit-stream; the MFC system is responsible for compressing from Slice Data Layer +down to all macro-block and block layers. + + +1.2.1 Example Usage Model +Encoding flow described here assumes that input stream is a series of uncompressed video frames that +will be converted into YUV (4:2:0) for encoding. Depending upon how this stream is derived, application +usage may be listed as below: + + • Single video stream encoder, video capture+encode, home movie making (SD/HD) + • PVR usage: Decode the incoming stream to generate YUV ( uncompressed ) frames and then + encode to have a compressed file size storage ( also transcoding) + • The HW asset needs to support single stream decode (SD+HD) and independent stream encode + (HD). This usage can be enabled by scheduling HW decoder at command stream level instead of + HW managed time-slicing. +For illustration purpose only, here are two possible usage modes: user-friendlymode and professional +mode. +  Professionalmode (PFM): + Application does the picture order sequencing and submit the picture + frame-by-frame to VPP as IN coded order with specified frame coding + type, and it has the full custom control of the GOP structure + + • no restriction on numbers of I, P and B + • no restriction on individual interlace and progressive picture + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 10 +  User-friendlymode (UFM): + Application presents video in display order. In this case, the application + can only specify two pre-defined parameters: NumP and NumB, for the + underlining pre-defined GOP structure. + + • Where NumP is the number of P (or P/P) -frames in a GOP, + and NumB is the number of B (or B/B) frames between two + consecutive key (I, P, I/I, I/P, or P/P) frames. + +In this case, the driver will need to composite the final GOP structure based on the application +parameters, and need to perform the proper sequencing of picture to the VPP in the coding order (i.e. it +will hold the pictures in the memory and submit the correct picture buffer address only in coding order), +then pass the data in as the same as in PFM. +A GOP (group of pictures) is a complete encoding unit consisting of a number of video frames. In general +a GOP structure has the following form: +I0, B-B1, K1, B-B2, K2, B-B3, K3, … , B-BN, KN +in display order, or equivalently +I¬0, K1, B-B1, K2, B-B2, K3, B-B3, … , KN, B-BN +in coded storage/transmission order. Where K is a key (i.e. I or P) frame, and B-Bi is a set of Mi +consecutive B frames. Thus, there are 1+N+(M1+…+MN) frames in a GOP. +In the UFM, we have N = NumP, and Mk = NumB for all k. Where NumB must be an number from 0, 1, 2, +or 3. For examples: + + • NumP = 5, NumB = 2: GOP = I0 P3 B1 B2 P6 B4 B5 P9 B7 B8 P12 B10 B11 P15 B13 B14 I16 … + • NumP = 7, NumB = 0: GOP = I0 P1 P2 P3 P4 P5 P6 P7 I8 P9 … + • NumP = 0, NumB = 0: GOP = I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 … + +As a result, a unified hardware interface is given. +All frame/slice type determination/specifications are performed prior to the hardware interface in coded +order. + + +1.2.2 Sample Algorithmic Flow +Assuming all the hardware components are given, there are infinite usage possibilities left with intention +for software to decide according to its own application needs depending upon the balanced requirement +of coding speed, frame latency, power-consumption, and video quality, and depending upon the usage +modes and user preferences (such as low-frame-rate-high-frame-quality vs. high-frame-rate-low-frame- +quality). +The last part of this chapter, we illustrate a generic sample to show how a compression algorithm can be +implemented to use our hardware. +Step 1. Application or driver initializes the encoder with desired configuration, including speed, quality, +targeted bit-rate, input video info, and output format and restrictions. +Step 2. VPP – Application or diver feeds VPP one frame at a time in coded order with specified frame or +field type, as well as transcoding informations: motion vectors, coded complexity (i.e. bit size). +It will perform denoising and deblocking based on original and targeted bit-rate, and output additional +4 spatial variances and 2 temporal variances for each macroblock as well as the whole frame. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 11 + Step 3. ENC – Application or diver feeds ENC one coding slice buffer at a time including all VPP output. +The frame level data is accessible to all slices. + a. Encoding setup unit (ESE) will set picture level quality parameters (including LUTs, + and othe costing functions) and set target bit-budget (TBB) and maximal bit-budget + (MBB) to each macroblock based on rate-control (RC) scheme implemented. For B- + frames, it wll also make ME searching mode decision (either Fast, Slow or Uni- + directional). + b. Loop over all macroblocks: calculate searching center (MVP) perform individual ME + and IE (MEE). Multi-thread may be designed for HW according to a zigzag order for + minimal dependency issue. + c. ENC make microblock level code decision (CD) outputs macroblock type, intra-mode, + motion-vectors, distortions, as well as TBBs and MBBs. +Step 4. PAK – Application or diver feeds PAK one array of coded macroblocks covering a slice at a time, +including all ENC output. Original frame buffer and reconstructed reference frame buffers are also +available for PAK to access. + a. PAK may create bitstreams for all sequence, gop, picture, and slice level headers prior + the first macroblock. + b. Loop over all macroblocks, accurate prediction block is constructed for either inter- or + intra- predictions (VMC & VIP). If MB distortion is less than some predetermined + threshold, for a B slice this step can be skiped as well as the Steps (c)-(e) and jump + directly to Step (f); for a key slice the prediction calculated here will be directly used as + the reference thus it jump to Step (e) after this step. + c. Differencing the predicted block from the original block derives the residue block. + Forward transformation and quantization (FTQ) is performed. For B slice, it will jump + to Step (f) right after. For other types of slice, Steps (d) and (e) can be performed in a + thread in parallel with Step (f) and beyond. + d. This is for accurate construction of reference pictures. Inverse quantizationnd inverse + transformation (IQT) are performed and added to the predictions to have the decoded + blocks. + e. ILDB is applied accordingly to the reconstructed blocks. + f. Meanwhile macroblock codes: including its configuration info (types and modes), + motion info (motion vectors and reference ids), and residual info (quantized + coefficients), are collected for packing (BSE) in the following sub-steps: + i. Code clean-up (in MPR). Check and verify Mbtype and + Cbps, use Skip or Zero respectively if one can. In principal, + when there are equivalent codes, use the simple one. + ii. Drop dependency (in MPR). Calculate relative codes from + the absolute codes by associate thm with neighborhood + information. All neighborhood correlations are solved in this + step. + iii. Unify symbols (in SEC). Translate relative codes into + symbols, and table or context indices that are independent of + the concept of syntax type. + iv. Entropy coding (VLE) on symbols. + g. Parsing bitstream data in RBSP form (in VLE), and output to application or driver. + h. By the end of each picture, write out the accurate actual data size to designate buffer + for ENC to access. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 12 + 1.2.3 Synchronization Mechanism +Encoding of a video stream can be broken down to three major steps (as explained in the previous +section): + 1. VPP: video-stream pre-processing. + 2. ENC: encoding, i.e. code decision of inter-MVs and intra-modes. And + 3. PAK: bit-stream packing, + a) residual calculation, transformation, and quantization, + b) code bit-stream packing, and + c) refenrece generation of keyframes. +This section describes an architectural solution to map first two steps in the GFX engine and the last step +in the MFX engine. Since this involves two OS visible engines, managing them using in parallel under one +application is similar to the solution in BLC/CTG implementations. Each engine has its own command +streamers and has mechanisms to synchronize at required level as described in the next sub-section. +Above three steps of encoding have dependencies in processing based on + i. functional pipeline order, i.e. on a given frame, VPP needs to be performed first, then + ENC, then PAK and finally MFD (Multi-Format Decoding) for key reference frame + generation. + ii. I-frames are key frames for P and B, they have to be first in every pipe-stage. + iii. P-frames are key frames for B frames and therefore P frames are processed first before + the dependent B frames + iv. GFX Engine is time slice to work on either VPP or ENC frame as we discussed in the + previous chapter. + v. PAK + MFD are executed on the same frame in the MFX engine by macro-block level + pipelining within a slice. It should be noted that for the sake of simplicity, an entire frame + (potentially multiple slices) are processed in the corresponding engine and no smaller + granularity of switching is allowed between the functional pipeline stages. +Three steps of the encoding can be interleaved on two engines in the following way on a frame by frame +basis. + + + + +Command Stream Synchronization + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 13 + 1.2.4 Restrictions +MFC implementation is subject to the following limitations. + + • Context switching within MFC and with Graphics Engine occurs only at frame boundary to minimize + the amount of information need to be tracked and maintained. + + +1.3 MFX State Model +The parallel video engine (PVE) supports two state delivery models: inline state model and indirect state +model. For inline state model, the state commands (*_STATE) can be issued in batch buffers or ring +buffers directly preceding object commands (*_OBJECT). In the indirect state model, the state commands +are not placed in the batch buffers or ring buffers. Instead Indirect State Buffers provide state information +(in the form of the above mentioned state commands) for the MFX pipeline. The MFX_STATE_POINTER +command provides the memory pointer to a indirect state buffer. +VCS (aka BCS) handles the difference of the two state delivery models. Therefore, the MFX pipeline +always sees the state commands in both models. However, MFX hardware supports additional context +save/restore of ‘dynamic states’. Dynamic states are the internal signals that are persistent. This could be +the CABAC context for macroblock encoding. + + + + +MFX State Model +The MFX codec is designed to be a stateless engine, that it does not retain any history of settings (states) +for the encoding/decoding process of a picture. Hence, driver must issue the full set of MFX picture state +command sequence prior to process each new picture. In addition, driver must issue the full set of Slice +state command sequence prior to process a slice. + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 14 + • In particular, RC6 always happens between frame boundaries. So at the beginning of every frame, + all state information needs to be programmed. There is no state information as part of media context + definition. + + +1.4 MFX Interruptability Model +MFX encoding and the encoding pipeline do not support interruption. All operations are frame based. +Interrupts can only occur between frames; the driver will submit all the states at the beginning of each +frame. Any state kept across frames is in MMIO registers that should be read between frames. +Software submits without any knowledge of where the parser head pointer is located. Also there is a non- +deterministic amount of time for the new context to reach the command streamer. However, the state +model for the MFX engine requires software to know exactly what state the pipeline is in at all times. This +introduces cases where a preemption could occur during or after a state change without software ever +knowing the state saved out to memory on the context switch. +Also, preemption is only allowed during the last macroblock in a row. Hardware cannot always perform a +context switch when the new context is seen by the hardware. To avoid a switch during an invalid +macroblock and to keep the state synchronized with software, there are two commands available that are +used. MI_ARB_ON_OFF disables and enables preemption while MFX_WAIT ensures the context switch, +if needed, preempts during macroblock execution. Below illustrates an example assuming VC1 VLD +mode. + Command Ring/Batch Notes +MI_ARB_ON_OFF = OFF Disable preemption +S1 Inline or indirect state cmd 1 +S2 Inline or indirect state cmd 2 +S3 Inline or indirect state cmd 3 +XXXX_OBJECT Slice +MI_ARB_ON_OFF = ON Enable preemption +MFX_WAIT Allow preemption to occur while XXXX_OBJECT executes +MI_ARB_ON_OFF = OFF Since arbitration is off again, state commands are allowed below +S4 Inline or indirect state cmd 4 +S5 Inline or indirect state cmd 5 +S6 Inline or indirect state cmd 6 +XXXX_OBJECT Slice +MI_ARB_ON_OFF = ON Enable preemption +MFX_WAIT Allow preemption to occur while XXXX_OBJECT executes +MI_ARB_ON_OFF = OFF Since arbitration is off again, state commands are allowed below + +Note that store DW commands may execute inside the preemption enabling window if needed. + + +1.5 MFX Programming Restrictions + +1.5.1 All Codecs +There is a hardware issue to switch to JPEG decode if the last MB of the previous video frame +(AVC/VC1/MPEG decode or AVC encode) has no coefficients coded (CBP equals 0). +To resolve the above issue, an AVC frame with only 1x1 intra-coded MB must be issued before JPEG +frame. Both AVC frame and JPEG frame must be placed in the same batch buffer to ensure JPEG frame +is executed immediately after the added AVC frame. + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 15 + The alternate WA is to place the AVC 1x1 intra-coded MB frame immediately after any AVC/VC1/MPEG +decode or AVC encode frame. + + +1.6 MFX Codec Commands Summary +DWord Bit Description + 31:29 + 0 Instruction Type = GFXPIPE = 3h + + 28:16 + 3D Instruction Opcode = PIPELINE_SELECT + GFXPIPE[28:27 = 1h, 26:24 = 1h, 23:16 = 04h] (Single DW, Non-pipelined) + 15:1 + Reserved: MBZ + + 0 + Pipeline Select + 0: 3D pipeline is selected + 1: Media pipeline is selected + + + + + Pipeline Type Opcode Sub Opcode Command Definition + (28:27) (26:24) (23:16) Chapter + + VC1 State + + 2h 5h 0h VC1_BSD_PIC_STATE VC1 BSD + 2h 5h 1h Reserved n/a + 2h 5h 2h Reserved n/a + 2h 5h 3h VC1_BSD_BUF_BASE_ST VC1 BSD + ATE + 2h 5h 4h Reserved n/a + 2h 5h 5h-7h Reserved n/a + VC1 Object + + 2h 5h 8h VC1_BSD_OBJECT VC1 BSD + 2h 5h 9h-FFh Reserved n/a + + + + Pipeline Type (28:27) Opcode (26:24) Sub Opcode (23:16) Command Definition + Chapter + + State + + 2h 6h 0h GPU Overview + 2h 6h 9h GPU Overview + 2h 6h 2h-7h Reserved n/a + Object + + 2h 6h 8h GPU Overview + 2h 6h 9h-FFh Reserved n/a + + Note that it is possible for a command to appear in both IMAGE and SLICE state buffer, e.g. QM_STATE +for JPEG can be issued at frame level or scan/slice level. + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 16 + Recommende +Pipelin Subop d Indirect +e Type Opcode SubopA B Chapte State Pointer Interruptable +(28:27) (26:24) (23:21) (20:16) Command r Map ? + MFX + Commo + n Common +2h 0h 0h 0h MFX_PIPE_MODE_SELECT MFX IMAGE No +2h 0h 0h 1h MFX_SURFACE_STATE MFX IMAGE No +2h 0h 0h 2h MFX_PIPE_BUF_ADDR_STATE MFX IMAGE No +2h 0h 0h 3h MFX_IND_OBJ_BASE_ADDR_STATE MFX IMAGE No +2h 0h 0h 4h MFX_BSP_BUF_BASE_ADDR_STATE MFX IMAGE No +2h 0h 0h 6h MFX_ STATE_POINTER MFX IMAGE No +2h 0h 0h 7h MFX_QM_STATE MFX IMAGE/SLICE No +2h 0h 0h 8h MFX_FQM_STATE MFX IMAGE No +2h 0h 0h A-1Eh Reserved n/a n/a No +2h 0h 0h 1FH MFX_muC_IND_OBJ_BASE_ADDR_STA MFX IMAGE No + TE + MFX + Commo + n Dec +2h 0h 1h 0-8h Reserved n/a n/a n/a +2h 0h 1h 9h MFD_ IT_OBJECT MFX n/a No +2h 0h 1h A-1Fh Reserved n/a n/a n/a + MFX + Commo + n Enc +2h 0h 2h 0-7Fh Reserved n/a n/a n/a +2h 0h 2h 8h MFX_PAK_INSERT_OBJECT MFX n/a No +2h 0h 2h 9h Reserved n/a n/a n/a +2h 0h 2h Ah MFX_STITCH_OBJECT MFX n/a No +2h 0h 2h B-1Fh Reserved n/a n/a n/a + AVC/ Common + MVC (State) +2h 1h 0h 0h MFX_AVC_IMG_STATE MFX IMAGE n/a +2h 1h 0h 1h Reserved n/a n/a n/a +2h 1h 0h 2h MFX_AVC_DIRECTMODE_STATE MFX SLICE n/a +2h 1h 0h 3h MFX_AVC_SLICE_STATE MFX SLICE n/a +2h 1h 0h 4h MFX_AVC_REF_IDX_STATE MFX SLICE n/a +2h 1h 0h 5h MFX_AVC_WEIGHTOFFSET_STATE MFX SLICE n/a + AVC/ + MVC Dec +2h 1h 1h 0-5h Reserved MFX n/a n/a +2h 1h 1h 6h MFD_AVC_DPB_STATE MFX IMAGE n/a +2h 1h 1h 7h MFD_AVC_SLICEADDR_OBJECT MFX n/a n/a +2h 1h 1h 8h MFD_AVC_BSD_OBJECT MFX n/a No +2h 1h 1h 9-1Fh Reserved n/a n/a n/a + AVC/ + MVC Enc +2h 1h 2h 0-8h Reserved n/a n/a n/a +2h 1h 2h 9h MFC_AVC_PAK_OBJECT MFX n/a No +2h 1h 2h A-1Fh Reserved n/a n/a n/a + AVC/ Extensio + MVC n + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 17 + Commo + n + (State) + VC1 +2h 2h 0h 0h Reserved n/a n/a n/a +2h 2h 0h 1h MFX_VC1_PRED_PIPE_STATE MFX IMAGE n/a +2h 2h 0h 2h MFX_VC1_DIRECTMODE_STATE MFX SLICE n/a +2h 2h 0h 3-1Fh Reserved n/a n/a n/a + VC1 Dec +2h 2h 1h 0h MFD_VC1_SHORT_PIC_STATE MFX IMAGE n/a +2h 2h 1h 1h MFD_VC1_LONG_PIC_STATE MFX IMAGE n/a +2h 2h 1h 2-7h Reserved n/a n/a n/a +2h 2h 1h 8h MFD_VC1_BSD_OBJECT MFX n/a No +2h 2h 1h 9-1Fh Reserved n/a n/a n/a + VC1 Enc +2h 2h 2h 0-1Fh Reserved n/a n/a n/a + Commo + n + (State) + MPEG2 +2h 3h 0h 0h MFX_MPEG2_PIC_STATE MFX IMAGE n/a +2h 3h 0h 1-1Fh Reserved n/a n/a n/a + MPEG2 Dec +2h 3h 1h 1-7h Reserved n/a n/a n/a +2h 3h 1h 8h MFD_MPEG2_BSD_OBJECT MFX n/a No +2h 3h 1h 9-1Fh Reserved n/a n/a n/a + MPEG2 Enc +2h 3h 2h 0-2h Reserved n/a n/a n/a +2h 3h 2h 3-8h Reserved +2h 3h 2h 9h MFC_MPEG2_SLICEGROUP_STATE +2h 3h 2h A-1Fh Reserved + Common + MuC (State) +2h 5h 0h Reserved + MuC Enc +2h 5h 2h Reserved + JPEG Common +2h 7h 0h 0h MFX_JPEG_PIC_STATE MFX IMAGE No +2h 7h 0h 1h Reserved n/a n/a n/a +2h 7h 0h 2h MFX_JPEG_HUFF_TABLE_STATE MFX IMAGE No +2h 7h 0h 3-1Fh Reserved n/a n/a n/a + JPEG Dec +2h 7h 1h 1-7h Reserved MFX n/a n/a +2h 7h 1h 8h MFD_JPEG_BSD_OBJECT MFX MCU No +2h 7h 1h 9-1Fh Reserved MFX n/a n/a + JPEG Enc +2h 7h 2h 0-1Fh Reserved MFX n/a n/a + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 18 + MMIO Space Registers +Range Start Range End Unit owner +00002000 00002FFF Render/Generic Media Engine +00004000 00004FFF Render/Generic Media Graphics Memory Arbiter +00006000 00007FFF +00012000 000123FF MFX Control Engine (Video Command Streamer) +00012400 00012FFF Media Units (VIN unit) +00014000 00014FFF MFX Memory Arbiter +00022000 00022FFF Blitter Engine +00024000 00024FFF Blitter Memory Arbiter +00030000 0003FFFF +00100000 00107FFF Fence Registers +00140000 0017FFFF MCHBAR (SA) + + + +Memory Interface Command Map +04h Opcode (28:23) MI_FLUSH + + +1.6.1 MFX Decoder Commands Sequence +The MFX codec is designed to be a stateless engine, that it does not retain any history of settings (states) +for the encoding/decoding process of a picture. Hence, driver must issue the full set of MFX picture state +command sequence prior to process each new picture. In addition, driver must issue the full set of Slice +state command sequence prior to process a slice. +In particular, RC6 always happens between frame boundaries. So at the beginning of every frame, all +state information needs to be programmed. There is no state information as part of media context +definition + +1.6.1.1 Examples for AVC +The following gives a sample command sequence programmed by a driver +a) For Intel or DXVA2 AVC Long Slice Bitstream Format + MFX_PIPE_MODE_SELECT + MFX_SURFACE_STATE + MFX_PIPE_BUF_ADDR_STATE + MFX_IND_OBJ_BASE_ADDR_STATE + MFX_BSP_BUF_BASE_ADDR_STATE + MFX_QM_STATE + VLD mode: MFX_AVC_PICID_STATE + MFX_AVC_IMG_STATE + MFX_AVC_DIRECTMODE_STATE + MFX_AVC_REF_IDX_STATE + MFX_AVC_WEIGHTOFFSET_STATE + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 19 + MFX_AVC_SLICE_STATE + VLD mode: MFD_AVC_BSD_OBJECT + IT mode: MFD_IT_OBJECT + MI_FLUSH +b) For DXVA2 AVC Short Slice Bitstream Format (for VLD mode only) + MFX_PIPE_MODE_SELECT + MFX_SURFACE_STATE + MFX_PIPE_BUF_ADDR_STATE + MFX_IND_OBJ_BASE_ADDR_STATE + MFX_BSP_BUF_BASE_ADDR_STATE + MFD_AVC_DPB_STATE + VLD mode: MFX_AVC_PICID_STATE + MFX_AVC_IMG_STATE + MFX_QM_STATE + MFX_AVC_DIRECTMODE_STATE + MFX_AVC_REF_IDX_STATE + MFX_AVC_WEIGHTOFFSET_STATE + VLD mode : MFD_AVC_SLICEADDR_OBJECT + VLD mode: MFD_AVC_BSD_OBJECT + VLD mode : MFD_AVC_BSD_SLICEADDR_OBJECT + VLD mode: MFD_AVC_BSD_OBJECT + … repeat these four commands N-1 times for a N-slice picture + VLD mode: MFD_AVC_BSD_OBJECT (for the last slice of the picture) + MI_FLUSH + +1.6.1.2 Examples for VC1 +The following gives a sample command sequence programmed by a driver +a) For Intel Proprietary Long Bitstream Format + MFX_VC1_DIRECTMODE_STATE + MFX_VC1_PRED_PIPE_STATE + MFX_VC1_LONG_PIC_STATE + VLD mode: MFD_VC1_BSD_OBJECT + IT mode: MFD_IT_OBJECT + MI_FLUSH +b) For DXVA2 VC1 Compliant Bitstream Format (for VLD mode only) + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 20 + MFX_VC1_DIRECTMODE_STATE + MFX_VC1_PRED_PIPE_STATE + MFX_VC1_SHORT_PIC_STATE + VLD mode: MFD_VC1_BSD_OBJECT + MI_FLUSH +c) For DXVA2 VC1 Compliant Bitstream Format (for VLD mode only), and field pair picture + Batch buffer for top-field + states.... + Slice_objs... + MI_flush + store register immediate (if VC1 short format with interlaced field pic) + MI_flush + Batch buffer for bottom field + load register immediate (if VC1 short format with interlaced field pic) + MI_flush + states.... + Slice_objs... + MI_flush + +1.6.1.3 Examples for JPEG +The following gives a sample command sequence programmed by a driver +Programmed once at the start of decoding + MFX_PIPE_MODE_SELECT + MFX_PIPE_SURFACE_STATE + MFX_IND_OBJ_BASE_ADDR_STATE + MFX_PIPE_BUF_ADDR_STATE + MFX_JPEG_PIC_STATE +Programmed at the start of Frame or Scan (These commands can be sent multiple times either before +MFX_JPEG_PIC_STATE or before MFD_JPEG_BSD_OBJECT) + MFX_JPEG_HUFF_TABLE + MFX_QM_STATE +Programmed per Scan (These commands can be sent multiple times depending on each bit stream) +MFD_JPEG_ BSD_OBJECT + MI_FLUSH + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 21 + 1.7 MFX Pipe Common Commands + +1.7.1 MFX_WAIT Command +This is a VCS Command to synchronize the two concurrent pipeline (one is VCR and one if MFX). It is +included here, because it is only used by MFX pipeline. It defines the usage model for pre-emption which +makes it very easy to do any ring buffer programming. +VCS Command engine services both VCR and MFX pipelines. If VCR takes many clock to initialize , and +if no WAIT command, MFX Object Command can start sending data to VCR before it is initialized. Hence, +this command effective causes a flush in the selected pipeline (VCR or MFX). + + MFX_WAIT + +Source: VideoCS +Length Bias: 1 + +This command can be considered the same as an MI_NOOP except that the command parser will not parse the +next command until the following happens + • AVC or VC1 BSD mode: The command will stall the parser until completion of the BSD object + • IT, encoder, and MPEG2 BSD mode: The command will stall the parser until the object package is sent down + the pipelineThis command should be used to ensure the preemption enable window occurs during the time the + object command is being executed down the pipeline. + + DWord Bit Description +0 31:29 Command Type + Default Value: 03h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Command Subtype + Default Value: 01h MFX_SINGLE_DW + Format: OpCode + 26:16 Sub-Opcode + Default Value: 0h MFX_WAIT + Format: OpCode + 15:10 Reserved + Project: All + Format: MBZ + 8 MFX Sync Control Flag + If set, VCS will stall the parser until all prior MFX objects are completed down the MFX pipeline + 7:6 Reserved + Project: All + Format: MBZ + 5:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Project: All + Format: =n + Total Length - 2 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 22 + 1.7.2 MFX_STATE_POINTER Command + + MFX_STATE_POINTER +Project: All +Source: VideoCS +Length Bias: 2 + +The MFX_STATE_POINTER command, issued at picture level, is used to set up the indirect pointers for VCS to +fetch all the MFX states (Image state, Slice state, etc.) needed for the encoding/decoding process in PAK/IT mode. +The encoding/decoding states are presented by state commands, which are grouped into separate sets (picture +level, slice level, etc.), and each is stored in its own memory buffer referred by an indirect state pointer. The content +of each indirect state buffer is a list of MFX state commands with no special format requirements. The sequence of +commands in each indirect state buffer is terminated by a MI_BATCH_BUFFER_END command (acts as the last +command marker). Therefore, indirect state buffers can have different and variable length of command sequences. + +The indirection is designed to facilitate context switching in the middle of a codec operation. The smallest granularity +of interruption is designed to be at a completed MB row in AVC/VC1/MPEG2 IT and AVC PAK operating modes as +well as in VC1/MPEG2 VLD mode. There is no support for context switch in AVC VLD mode. + +Hardware supports up to 4 separate indirect state pointers, allowing software to manage the grouping of state +commands. During context switch, hardware restores (re-issues) the latest version of each indirect state pointer, if +present. + + MFX_STATE_POINTER command can only program one indirect state pointer at a time. MI_FLUSH will invalidate + all indirect state buffer pointers inside VCS. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFX_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h Media + Format: OpCode + 26:24 Media Command Opcode + Default Value: 0h MFX_COMMON_STATE + Format: OpCode + 23:21 SubOpcode A + Default Value: 0h + Format: OpCode + 20:16 SubOpcode B + Default Value: 6h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 0h DWORD_COUNT_n + Project: All + Format: =n Total Length - 2 + + + +1 31:5 State Pointer + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 23 + MFX_STATE_POINTER + Format: GeneralStateOffset[31:5]Indirect State Buffer + Specifies the 32-byte aligned address of an Indirect State Buffer. This pointer is relative to the + General State Base Address. + + 4:2 Reserved + Project: All + Format: MBZ + 1:0 State Pointer Index + Specifies one of the four indirect state pointers to program. + Value Name Description Project + 00b indirect state pointer 0 (image state) All + 01b indirect state pointer 1 (slice state)sc All + 10b indirect state pointer 2 + 11b indirect state pointer 3 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 24 + 1.7.3 MFX_PIPE_MODE_SELECT + + MFX_PIPE_MODE_SELECT + +Source: VideoCS +Length Bias: 2 + +Specifies which codec and hardware module is being used to encode/decode the video data, on a per-frame basis. + + The MFX_PIPE_MODE_SELECT command specifies which codec and hardware module is being used to + encode/decode the video data, on a per-frame basis. It also configures the hardware pipeline according to the + active encoder/decoder operating mode for encoding/decoding the current picture. Commands issued specifically + for AVC and MPEG2 are ignored when VC1 is the active codec. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_COMMON + Format: OpCode + 26:24 Opcode + Default Value: 0h MFX_COMMON_STATE + Format: OpCode + 23:21 SubOpA + Default Value: 0h + Format: OpCode + 20:16 SubOpB + Default Value: 0h MFX_PIPE_MODE_SELECT + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Description + 2h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 26:25 Reserved + Project: All + Format: MBZ + 23:18 Reserved + Project: All + Format: MBZ + 17 Decoder Short Format Mode + For IT mode, this bit must be 0. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 25 + MFX_PIPE_MODE_SELECT + Value Name Description + 1 Long Format Driver Interface AVC/VC1/MVC Long Format Mode is in use + 0 Short Format Driver Interface [Default] + AVC/VC1/MVC Short Format Mode is in use + + + + 16:15 Decoder Mode select + Each coding standard supports two entry points: VLD entry point and IT (IDCT) entry point. This field + selects which one is in use.This field is only valid if Codec Select is 0 (decoder). + Value Name Description + 0h VLD Mode All codec minimum must support this modeConfigure the MFD Engine for VLD Mode + Note: All codec minimum must support this mode + 1h IT Mode Configure the MFD Engine for IT Mode + Note: Only VC1 and MPEG2 support this mode + 14:13 Reserved + Project: All + Format: MBZ + 12 Reserved + + Format: MBZ + 11 Pic Error/Status Report Enable. + + This field control whether the error/status reporting is enable or not.0: Disable1: EnableIn decoder + modes: Error reporting is written out once per frame. The Error Report frame ID listed in DW3 along + with the VLD/IT error status bits are packed into one cache and written to the “Decoded Picture + Error/Status Buffer address” listed in the MFX_PIPE_BUF_ADDR_STATE Command. Note: driver shall + program different error buffer addresses between pictrues; otherwise, hardware might overwrite + previous written data if driver does not read it fast enough.In encoder modes: Not used + Value Name + 0h Disable + 1h Enable + 10 Stream-Out Enable + This field controls whether the macroblock parameter stream-out is enabled during VLD decoding for + transcoding purpose. + Value Name + 0h Disable + 1h Enable + + + Programming Notes + In decoder modes: The Stream-Out feature is added to support transcoding. While decoding the input + compressed stream, selected decoded information may be used by the encoder for re-compression.In + encoder modes: This feature used to perform dynamic Multipass of PAK for conformance pupose. Also + it provides feedback to host (ENC) for future needs. Software can use this bit to disable writing PAK + steam data to the streamout buffer for last pass of frame in PAK. Thus, save memory bandwidth. + 9 Post Deblocking Output Enable (PostDeblockOutEnable) + Project: All + This field controls the output write for the reconstructed pixels AFTER the deblocking filter.In MPEG2 + decoding mode, if this is enabled, VC1 deblocking filter is used. + Value Name + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 26 + MFX_PIPE_MODE_SELECT + 0h Disable + 1h Enable + 8 Pre Deblocking Output Enable (PreDeblockOutEnable) + Project: All + This field controls the output write for the reconstructed pixels BEFORE the deblocking filter. + Value Name + 0h Disable + 1h Enable + 7:6 Reserved + Format: MBZ + 5 Stitch Mode + Project: All + Exists If: CodecSel=Encode and StandardSel=AVC + + + Value Name Description + 0h Not in stitch mode + 1h In the special stitch This mode can be used for any Codec as long as bitfield conditions are + mode met. + 4 Codec Select + Value Name Description + 0h Decode + 1h Encode Valid only if StandardSel is AVC, MPEG2) + 3:0 Standard Select + Value Name Description + 0000b MPEG2 + 0001b VC1 + 0010b AVC Covers both AVC and MVC + 0011b JPEG + 0110b Reserved + 0111b Reserved +2 31:11 Reserved + Format: MBZ + 10 MPC pref08x8_disable Flag (Default 0) + BitFieldDesc + Value Name Project + 0h Disable All + 1h Enable All + 9:8 Reserved + Format: MBZ + 6 Clock gate Enable at Slice-level + BitFieldDesc: + Value Name Description + 0h Disable Disable Slice-level Clock gating, Unit-level Clock gating will apply + 1h Enable Enable Slice-level Clock gating, overrides any Unit level Clock gating + 4 AVC Motion Vector/POC Table Error Disable Flag + This bit disable termination due to any errors resulting from Motion Vector and POC Table + Value Name Description + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 27 + MFX_PIPE_MODE_SELECT + 0h Terminates Motion Vector/POC Table Error will terminate the current slice decoding + 1h Will not terminate Motion Vector/POC Table Error will not terminate the current slice decoding + 3 AVC Mbdata Error Disable Flag + This bit disable termination due to any errors resulting from any Mbdata (QP delta range) + Value Name Description + 0h Enable Mbdata Error will terminate the current slice decoding + 1h Disable Mbdata Error will not terminate the current slice decoding + 2 AVC CABAC/CAVLC Decode Error Disable Flag + This bit disable termination due to any errors resulting from CABAC/CAVLC decoding engine + Value Name Description + 0h Terminate CABAC/CAVLC Decoder Error will terminate the current slice decoding + 1h Will not terminate CABAC/CAVLC Decoder Error will not terminate the current slice decoding + 1 Reserved + Format: MBZ + 0 Reserved + Format: MBZ +3 31:0 Pic Status/Error Report ID + Format: U32 + In decoder modes: Error reporting is written out once per frame. This field along with the VLD error + status bits are packed into one cache and written to the memory location specified by “Decoded Picture + Error/Status Buffer address” listed in the MFX_PIPE_BUF_ADDR_STATE Command. + In encoder modes: Not used + Value Name Description + 0h 32-bit unsigned Unique ID Number + 1h Reserved +4 31:0 Reserved + + Format: MBZ + + + +The Encoder Pipeline Modes of Operation (Per Frame): + 1. PAK Mode: VCS-command driven, setup by driver. Like the IT mode of decoder, it is executed + on a per-MB basis. Hence, each PAK Object command corresponds to coding of only one + MB. + a. Normal Mode (including transcoding): receive per-MB control and data (MV, mb_type, + cbp, etc.). It generates the output compressed bitstream as well as the reconstructed + reference pictures, one MB at a time, for later use. + b. Encoder StreamOut Mode: to provide per-MB, per-Slice and per-Frame coding result + and information (statistics) to the Host, Video Preprocessing Unit and ENC Unit to + enhance their operations. +The Decoder Pipeline Modes of Operation (Per Frame): + 1. VLD Mode: The output from the BSD (weight&offset/coeff/motion vectors record) can be sent + in part (as specified) and to the remaining fixed function hardware pipeline to complete the + decoding processing. The driver specifies through MFD commands of what to send out from + the BSD unit and where to send the BSD output. + a. For transcoding (including transrating and transcaling), part of the BSD output (a + series of per-MB record) can be sent to memory for further processing to encode into + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 28 + a difference output format. This function is named as StreamOut. When StreamOut is + active, not all MB information needs to be sent, only MVs and selective MB coding + information. + 2. IT Mode: In this mode, the BSD is not invoked. Instead host performs all the bitstream + decoding and parsing; and the result are saved into memory in a specific per-MB record + format. The MFD Engine VCS reads in these records one at time and finish the rest of the + decoding (IT, MC, IntraPred and ILDB). + a. MB information is organized into two indirect data buffers, one for MVs and one for + residue coefficients. As such, two indirect base address pointers are defined. +Programming Restriction: + + • Software must ensure the current pipeline is flushed via an MI_FLUSH prior to the execution of + MFX_PIPE_MODE_SELECT in switching the MFX Engine to encode/decode a different codec + format (AVC, VC1 or MPEG2). + • MFX_PIPE_MODE_SELECT is issued per picture (frame or field). + +Emulation Prevention Byte Removal is handled in 2 different ways that affects the definition of the Slice +Data Buffer and H/W behavior. A control mode bit is defined to switch between these 2 methods. + 1. Application is required to remove any emulation prevention byte straddling across the Slice + Header and Slice Data boundary in the bitstream + a. As such, application will pass to the driver the exact starting location of Slice Data + (Byte Offset and Bit Offset) in the Slice buffer and gurantee there is no Emulation + Prevention Byte at the beginning of Slice Data. So H/W does not need to do any + before the Slice Data. + 2. Application does not remove any emulation prevention byte straddling across the Slice Header + and Slice Data boundary in the bitstream + a. As such application will pass to the driver the same set of information as above, but + H/W is now required to scan the Emulation Prevention Byte from the beginning of + Slice Header through to Slice Data, in order to locate the exact starting point of the + Slice Data. + i. This is because the Slice Header Byte Offset, as defined in DXVA2 interface, + does not include any emulation bytes found in the Slice Header. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 29 + 1.7.4 MFX_SURFACE_STATE Command + + MFX_SURFACE_STATE + +Source: VideoCS +Length Bias: 2 + +This command is common for all encoding/decoding modes, to specify the uncompressed YUV picture (i.e. +destination surface) or intermediate streamout in/out surface (e.g. coefficient/residual) (field, frame or interleaved +frame) format for reading and writing: + • Uncompressed, original input picture to be encoded + • Reconstructed non-filtered/filtered display picturec(becoming reference pictures as well for subsequent + temporal inter-prediction) + +Since there is only one media surface state being active during the entire encoding/decoding process, all the +uncompressed/reconstructed pictures are defined to have the same surface state. The primary difference among +picture surface states is their individual programmed base addresses, which are provided by other state commands +and not included in this command. MFX engine is making the association of surface states and corresponding buffer +base addresses. + +MFX engine currently supports only one media surface type for video and that is the NV12 (Planar YUV420 with +interleaved U (Cb) and V (Cr). For optimizing memory efficiency based on access patterns, only TileY is supported. +For JPEG decoder, only IMC1 and IMC3 are supported. Pitch can be wider than the Picture Width in pixels and +garbage will be there at the end of each line. The following describes all the different formats that are supported and +not supported in Gen7 MFX : + • NV12 – 4:2:0 only; UV interleaved; Full Pitch, U and V offset is set to 0 (the only format supported for video + codec); vertical UV offset is MB aligned; UV xoffsets = 0. JPEG does not support NV12 format because non- + interleave JPEG has performance issue with partial write (in interleaved UV format) + • IMC 1 & 3 – Full Pitch, U and V are separate plane; (JPEG only; U plane + garbage first in full pitch followed by + V plane + garbage in full pitch). U and V vertical offsets are block aligned; U and V xoffset = 0; there is no gap + between Y, U and V planes. IMC1 and IMC3 are different by a swap of U and V. This is the only format + supported in JPEG for all video subsampling types (4:4:4, 4:2:2 and 4:2:0) + • We are not supporting IMC 2 & 4 – Full Pitch, U and V are separate plane (JPEG only; U plane first in full pitch + followed by V plane in full pitch – U and V plane are side-by-side). U and V vertical offsets are 16-pixel aligned; + V xoffset is half-pitch aligned; U xoffset is 0; there is no gap between Y, U and V planes. IMC2 and IMC4 are + different by a swap of U and V. + • We are not supporting YV12 – half pitch for each U and V plane, and separate planes for Y, U and V (U plane + first in half pitch followed by V plane in half pitch). For YV12, U and V vertical offsets are block aligned; U and V + xoffset = 0; there is no gap between Y, U and V planes + +Note that the following data structures are not specified through the media surface state + • 1D buffers for row-store and other miscellaneous information. + • 2D buffers for per-MB data-structures (e.g. DMV biffer, MB info record, ILDB Control and Tcoeff/Stocoeff). + +This surface state here is identical to the Surface State for deinterlace and sample_8x8 messages described in the +Shared Function Volume and Sampler Chapter. + +For non pixel data, such as row stores, indirect data (Compressed Slice Data, AVC MV record, Coeff record and +AVC ILDB record) and streamin/out and output compressed bitstream, a linear buffer is employed. For row stores, +the H/W is designed to guarantee legal memory accesses (read and write). For the remaining cases, indirect object +base address, indirect object address upper bound, object data start address (offset) and object data length are +used to fully specified their corresponding buffer. This mechanism is chosen over the pixel surface type because of +their variable record sizes. + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 30 + MFX_SURFACE_STATE + All row store surfaces are linear surface. Their addresses are programmed in Pipe_Buf_Base_State or + Bsp_Buf_Base_Addr_State + + Programming Notes +VC1 I picture scaling: Even though VC1 allows I reconstructed picture scaling (via RESPIC), as such scaling is only +allowed at I picture. All subsequent P (and B) pictures must have the same picture dimensions with the preceding I +picture. Therefore, all reference pictures for P or B picture can share the same surface state with the current P and B +picture. Note : H/W is not processing RESPIC. Application is no longer expecting intel decoder pipelineand kernel to +perform this function, it is going to be done in the video post-processing scaler or display controller scale as a +separate step and controller. +All video codec surfaces must be NV12 Compliant, except JPEG. U/V vertical must be MB aligned for all video +codec (further contrained for field picture), but JPEG can be block aligned. All video codec and JPEG uses Tiled – Y +format only, for uncompressed pixel surfaces. +Even for JPEG planar 420 surface, application may provide only 1 buffers, but there is still only one single surface +state for all of them. If IMC equal to 1, 2, 3 or 4, U and V have the pitch same as Y. And U and V will have different +offset, each offset is block aligned. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_COMMON + Format: OpCode + 26:24 Opcode + Default Value: 0h MFX_COMMON_STATE + Format: OpCode + 23:21 SubOpA + Default Value: 0h + Format: OpCode + 20:16 SubOpB + Default Value: 1h + Format: OpCode + 15:12 Reserved + Format: MBZ + 11:0 DWord Length + Format: =n Total Length - 2 + + + + + Value Name Description + 4h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 31:2 Reserved + Format: MBZ + 1:0 Reserved + + Format: MBZ +2 31:18 Height + Format: U14-1 Height + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 31 + MFX_SURFACE_STATE + + This field specifies the height of the Picture in units of pixels/residuals. For PLANAR surface formats, + this field indicates the height of the Y (luma) plane. Note : Gen7 Video Codecs must program less than + and equal to 4K.(In future, it will be ideal to have this field define in a WORD boundary.)AVC – multiple + of 2 MB rows for field pictureVC1 – mulitple of 4 pixels for field pictureMPEG2 - multiple of 2 MB rows + for field picJPEG – mulitple of integral MCU (8 or 16 pixels) per picture + Value Name Description + [0,16383] representing heights [1,16384] + + + Programming Notes Project + + + For AVC : For frame picture is a multiple of 16; for field picture is a multiple of 32 + + + For VC1 : For progressive frames, the frame height and frame width is a multiple of 2 pixels. + For interlaced frames, the frame height shall be a multiple of 4 pixels, and its width is a + multiple of 2 pixels, based on a PLANAR_420 surface. + + + + Video Codecs must program less than and equal to 4K. + In future, it will be ideal to have this field define in a WORD boundary. + 17:4 Width + Format: U14-1 Width + + + This field specifies the width of the Picture in units of pixels/residuals. For PLANAR surface formats, + this field indicates the width of the Y (luma) plane. + Value Name Description + [0,16383] representing widths [1,16384] + + + Programming Notes Project + + + The Width specified by this field multiplied by the pixel size in bytes must be less than or + equal to the surface pitch (specified in bytes via the Surface Pitch field). + + + Width (field value + 1) must be a multiple of 2 for PLANAR_420, + + + MFX HW does not use this field, the picture width is read from IMG State instead, because + this field may not equal to the actual picture width. This field is used by the KMD to allocate + surface in GTT. + + Video Codecs must program less than and equal to 4K. + In future, it will be ideal to have this field define in a WORD boundary. + 3:2 Reserved + Format: MBZ + 1:0 Cr(V)/Cb(U) Pixel Offset V Direction + Project: All + Format: U0.2 exactly as shown in the original spec + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 32 + MFX_SURFACE_STATE + + + Specifies the distance to the U/V values with respect to the even numbered Y channels in the V + direction + Programming Notes + This field is ignored for all formats except PLANAR_420_8 +3 31:28 Surface Format + Specifies the format of the surface. All of the Y and G channels will use table 0 and all of the Cr/Cb/R/B + channels will use table 1.Usage: For 420 planar YUV surface, use 4; for monochrome surfaces, use 12. + For monochrome surfaces, hardware ignores control fields for Chroma planes.This field must be set to + 4 - PLANAR_420_8, or 12 – Y8_UNORMNot used for MFX, and is ignored. But for JPEG decoding, + this field should be programmed to the same format as JPEG_PIC_STATE. For video codec, it should + set to 4 always. + Value Name Description + 0 YCRCB_NORMAL + 1 YCRCB_SWAPUVY + 2 YCRCB_SWAPUV + 3 YCRCB_SWAPY + 4 PLANAR_420_8 (NV12, IMC1,2,3,4, YV12) + 5 PLANAR_411_8 Deinterlace Only + 6 PLANAR_422_8 Deinterlace Only + 7 STMM_DN_STATISTICS Deinterlace Only + 8 R10G10B10A2_UNORM Sample_8x8 Only + 9 R8G8B8A8_UNORM Sample_8x8 Only + 10 R8B8_UNORM (CrCb Sample_8x8 Only + 11 R8_UNORM (Cr/Cb) Sample_8x8 Only + 12 Y8_UNORM Sample_8x8 Only + 13,15 Reserved + 27 Interleave Chroma + Format: Enable + This field indicates that the chroma fields are interleaved in a single plane rather than stored as two + separate planes. This field is only used for PLANAR surface formats.For AVC/VC1/MPEG VLD and IT + modes : set to Enable to support interleave U/V only.For JPEG : set to Disable for all formats (including + 4:2:0) – because JPEG does not support NV12. (This field is needed only if JPEG will support NV12; + otherwise is ignored.) + Value Name + 1 Enable + 0 Disable + 26 Reserved + Format: MBZ + 25:22 Surface Object Control State (MEMORY_OBJECT_CONTROL_STATE) + + This 4-bit field is used in various state commands and indirect state objects to define LLC cacheability + including graphics data type attributes for memory objects. + Value Name Description + 2 Graphics Data This field contains the GFDT bit for this surface when writes occur. GFDT can + Type (GFDT) also be set by the GTT. The effective GFDT is the logical OR of this field with + the GFDT from the GTT entry. This field is ignored for reads.Format = U1 + 1 Cacheability This field controls cacheability in the last-level cache (LLC).Format = U2 + Control enumerated type00: use cacheability control bits from GTT entry01: data is not + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 33 + MFX_SURFACE_STATE + cached in LLC 1x: data is cached in LLC + + + Programming Notes + This field is ignored; H/W uses those values programmed in each of the Buf Address State entries + instead. + 21:20 Reserved + + Format: MBZ + 19:3 Surface Pitch + Format: U17-1 pitch in Bytes + + + This field specifies the surface pitch in (#Bytes). + Value Name Description + [0,2047] to [1B, 2048B] + + + Programming Notes + For tiled surfaces, the pitch must be a multiple of the tile width (i.e.128 bytes aligned). If Half Pitch for + Chroma is set, this field must be a multiple of two tile widths for tiled surfaces, or a multiple of 2 bytes + for linear surfaces.For Y-tiled surfaces: Range = [127, 524287] to [128B,256KB] = [1 tile, 2048 tiles] + + + 2 Half Pitch for Chroma + Format: Enable + (This field must be set to Disable)This field indicates that the chroma plane(s) will use a pitch equal to + half the value specified in the Surface Pitch field. This field is only used for PLANAR surface + formats.This field is igored by MFX (unless we support YV12) + + 1 Tiled Surface + Format: Boolean + (This field must be set to TRUE: Tiled)This field specifies whether the surface is tiled.This field is + ignored by MFX + Value Name Description + 0 False Linear + 1 True Tiled + + + Programming Notes + Linear surfaces can be mapped to Main Memory (uncached) or System Memory (cacheable, + snooped). Tiled surfaces can only be mapped to Main Memory.The corresponding cache(s) must be + invalidated before a previously accessed surface is accessed again with an altered state of this bit. + 0 Tile Walk + Format: 3D_Tilewalk + (This field must be set to 1: TILEWALK_YMAJOR)This field specifies the type of memory tiling (XMajor + or YMajor) employed to tile this surface. See Memory Interface Functions for details on memory tiling + and restrictions.This field is ignored when the surface is linear.This field is ignored by MFX. Internally + H/W is always treated this set to 1 for all video codec and for JPEG. + Value Name Description + 0h XMAJOR TILEWALK_XMAJOR + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 34 + MFX_SURFACE_STATE + 1h YMAJOR TILEWALK_YMAJOR + + + Programming Notes + The corresponding cache(s) must be invalidated before a previously accessed surface is accessed + again with an altered state of this bit +4 31 Reserved + Format: MBZ + 30:16 X Offset for U(Cb) + Project: All + Format: U15 Pixel Offset + + + This field specifies the horizontal offset in pixels from the Surface Base Address to the start (origin) of + the U(Cb) plane or the interleaved UV plane if Interleave Chroma is enabled. This field is only used for + PLANAR surface formats. This field must be set to zero.X Offset for U(Cb) in pixel (This field must be + zero for NV12 and IMC 1 and 3) + Programming Notes + For PLANAR_420 and PLANAR_422 surface formats, this field must be zero. + 15 Reserved + Project: All + Format: MBZ + 14:0 Y Offset for U(Cb) + Project: All + Format: U15 Pixel Row Offset + + + This field specifies the veritical offset in rows from the Surface Base Address to the start (origin) of the + U(Cb) plane or the interleaved UV plane if Interleave Chroma is enabled. This field is only used for + PLANAR surface formats. + Programming Notes + For PLANAR_420 and PLANAR_422 surface formats, this field must be multiple of 16 pixels – i.e. + multiple MBs. For JPEG, it is block aligned +5 31:29 Reserved + Format: MBZ + 28:16 X Offset for V(Cr) + Format: U13 Offset in Pixels + + + + + This field must be zero for NV12 and IMC 1 and 3 + This field specifies the horizontal offset in pixels from the Surface Base Address to the start (origin) of + the V(Cr) plane. This field is only used for PLANAR surface formats with Interleave Chroma disabled. + + + Programming Notes + For PLANAR_420 and PLANAR_422 surface formats, this field must indicate an even number of + pixels. + 15:0 Y Offset for V(Cr) + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 35 + MFX_SURFACE_STATE + Format: U16 Row Offset in Pixels + + + This field specifies the veritical offset in rows from the Surface Base Address to the start (origin) of the + V(Cr) plane. This field is only used for PLANAR surface formats with Interleave Chroma disabled. This + field is ignored by all video codec, only used by JPEG. + Programming Notes + For PLANAR_420 surface formats, this field must be multiple of 16 pixels – i.e. multiple MBs. For + JPEG, it is block aligned + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 36 + 1.7.5 MFX_PIPE_BUF_ADDR_STATE Command + + MFX_PIPE_BUF_ADDR_STATE + +Source: VideoCS +Length Bias: 2 +This state command provides the memory base addresses for all row stores, StreamOut buffer and reconstructed +picture output buffers required by the MFD or MFC Engine (that are in addition to the row stores of the Bit Stream +Decoding/Encoding Unit (BSD/BSE) and the reference picture buffers). This is a picture level state command and is +common among all codec standards and for both encoder and decoder operating modes. However, some fields may +only applicable to a specific codec standard.All Pixel Surfaces (original, reference frame and reconstructed frame) in +the Encoder are programmed with the same surface state (NV12 and TileY format), except each has its own frame +buffer base address. In the tile format, there is no need to provide buffer offset for each slice; since from each MB +address, the hardware can calculated the corresponding memory location within the frame buffer directly. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_PIPE_BUF_ADDR_STATE + Format: OpCode + 26:24 Common Opcode + Default Value: 0h MFX_PIPE_BUF_ADDR_STATE + Format: OpCode + 23:21 SubOpcode A + Default Value: 0h MFX_PIPE_BUF_ADDR_STATE + Format: OpCode + 20:16 SubOpcode B + Default Value: 2h MFX_PIPE_BUF_ADDR_STATE + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Project: All + Format: =n + + + Total Length + Fixed Length + + + Value Name Description + 16h DWORD_COUNT_n [Default] Excludes DWord (0,1) +1 31:6 Pre Deblocking - Destination Address + Specifies the 4K byte aligned frame buffer address for outputting the non-filtered reconstructed YUV + picture (i.e. output of final adder in each codec standard, and prior to the deblocking filter unit).This field + is ignored if PreDeblockOutEnable is set to 0 (disable). + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 37 + MFX_PIPE_BUF_ADDR_STATE + 5:0 Reserved + Format: MBZ +2 31:6 Post Deblocking - Destination Address + Specifies the 4K byte aligned frame buffer address for outputting the post-loop filtered reconstructed + YUV picture (i.e. output of the deblocking filter unit)This field is ignored if PostDeblockOutEnable is set + to 0 (disable). + 5:4 Post Deblocking – Arbitration Priority Control + Format: U2 Enumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + 00b Highest priority + 01b Second highest priority + 10b Third highest priority + 11b Lowest priority + 2 Post Deblocking - Graphics Data Type (GFDT) + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + + 1:0 Post Deblocking - Cacheability Control + Format: U2 Enumerated type + + + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description + 00b GTT entry Use cacheability control bits from GTT entry + 01b not LLC or MLC Data is not cached in LLC or MLC + 10b in LLC but not MLC Data is cached in LLC but not MLC + 11b both LLC and MLC Data is cached in both LLC and MLC +3 31:6 Original Uncompressed Picture - Source Address (CurSrcAddr) + Exists If: Encoding + Format: Address[31:6] + Specifies the 64 byte aligned frame buffer address for fetching YUV pixel data from the original + uncompressed input picture for encoding. + + 5:4 Original Uncompressed Picture – Arbitration Priority Control + Format: U2 Enyumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + 00b Highest priority + 01b Second highest priority + 10b Third highest priority + 11b Lowest priority + 2 Original Uncompressed Picture - Graphics Data Type (GFDT) + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 38 + MFX_PIPE_BUF_ADDR_STATE + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + + 1:0 Original Uncompressed Picture - Cacheability Control + Format: U2 Enumerated Type + + + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description + 00b GTT entry use cacheability control bits from GTT entry + 01b not in LLC or MLC data is not cached in LLC or MLC + 10b in LLC but not MLC data is cached in LLC but not MLC + 11b both LLC and MLC data is cached in both LLC and MLC +4 31:6 StreamOut Data Destination - Base Address (StreamOutAddr) + Format: StreamOutAddress[31:6] 64 byte aligned buffer + + + Specifies the address for outputting the per-MB indirect data to memory when StreamOutEnable is set + in the MFX_PIPE_MODE_SELECT command. + For decoder : this field is used for transcoding purpose. + For encoder : this field is used for dynamic repeat of frame in PAK for Rate Control. Also used for + feeding coding information back to the Host, Video Preprocessing Unit and ENC Unit.All data are + written in fixed formats, and therefore all record sizes are known in the hardware. Hardware can + calculate the offset into this base address for per-MB data. + + 5:4 StreamOut Data Destination – Arbitration Priority Control + Project: All + Format: U2 Enumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + 00b Highest priority + 01b Second highest priority + 10b Third highest priority + 11b Lowest priority + 2 StreamOut Data Destination - Graphics Data Type (GFDT) + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + + 1:0 StreamOut Data Destination - Cacheability Control + Format: U2 Enumerated Type + + + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 39 + MFX_PIPE_BUF_ADDR_STATE + 00b GTT entry use cacheability control bits from GTT entry + 01b Not in LLC or MLC data is not cached in LLC or MLC + 10b In LLC but not MLC data is cached in LLC but not MLC + 11b Both LLC and MLC data is cached in both LLC and MLC +5 31:6 Intra Row Store Scratch Buffer - Base Address (IntraOSRowStoreAddr) + Format: GraphicsAddress[31:6] + This field provides the base address of the scratch buffer (read/write) used by the AVC IntraPrediction + unit to store MB information of the previous row for processing of each macroblock in the current row. + The Intra Row Store buffer must be 64-byte cacheline aligned.Hardware uses the horizontal address of + the current macroblock to address the Intra Row Store.This field is ignored in MPEG2 and VC1 + mode.Max 256 cachelines for 4K pixels (1 cacheline for either MBAFF or non-MBAFF) + + 5:4 Intra/Overlap Smoothing Row Store Scratch Buffer – Arbitration Priority Control + Format: U2 Enumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + 00b Highest priority + 01b Second highest priority + 10b Third highest priority + 11b Lowest priority + 2 Intra/Overlap Smoothing Row Store Scratch Buffer - Graphics Data Type (GFDT) + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + + 1:0 Intra/Overlap Smoothing Row Store Scratch Buffer - Cacheability Control + Format: U2 Enumerated Type + + + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description + 00b GTT entry use cacheability control bits from GTT entry + 01b Not in LLC or MLC data is not cached in LLC or MLC + 10b In LLC but not MLC data is cached in LLC but not MLC + 11b Both LLC and MLC data is cached in both LLC and MLC +6 31:6 Deblocking Filter Row Store Scratch Buffer - Base Address (DeblockRowStoreAddr + Format: GraphicsAddress[31:6] + Deblocking Filter Row Store is needed for + + VC1 Overlap-smoothing Filter + + This field provides the base address of the scratch buffer (read and write) used by the deblocking filter + unit to store MB information of the previous row for filtering of each macroblock in the current row. The + Deblocking Filter Row Store buffer must be 64-byte cacheline aligned. + Hardware uses the horizontal address of the current macroblock to address the Deblocking Filter Row + Store. Max 6 cachelines for VC1 and MPEG2, and max 4 for AVC (for MBAFF, 2 for non-MBAFF). + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 40 + MFX_PIPE_BUF_ADDR_STATE + 5:4 Deblocking Filter Row Store Scratch Buffer – Arbitration Priority Control + Format: U2 Enumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + 0h Highest priority + 1h Second highest priority + 1h Third highest priority + 1h Lowest priority + 2 Deblocking Filter Row Store Scratch Buffer - Graphics Data Type (GFDT) + Project: All + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + + 1:0 Deblocking Filter Row Store Scratch Buffer - Cacheability Control + Project: All + Format: U2 Enumerated Type + + + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description + 00b GTT entry use cacheability control bits from GTT entry + 01b Not in LLC or MLC data is not cached in LLC or MLC + 10b LLC but not MLC data is cached in LLC but not MLC + 11b both LLC and MLC data is cached in both LLC and MLC +7..22 31:6 Reference Picture (RefAddr[0-15]) - Addresses + Format: GraphicsAddress[31:6] + Specifies the 64 byte aligned reference frame buffer addresses for the motion compensation operation + in AVC/VC1/MPEG2. AVC can specify up to 16 YUV frame-based surfaces for both forward and + backward references, i.e. L0+L1 total = 16 max. Any entry can be assigned to L0 or L1 or both lists.But + VC1 and MPEG2, worst case, can use up to 2 YUV frame-based surfaces for both forward and + backward references:P-MB : RefAddr[0] – temporal closest previous field of a reference frame (can be + the current frame)RefAddr[1] – next temporal closest previous field of a reference frame (must be + different from the current frame)It is a variant (without the LongTermRefPic specification) of the + RefFrameList[16] defined in AVC DXVA Spec. RefAddr[0-15] is indexed by frame_storeID >>1. It is not + a packed list, i.e. invalid entries can scatter among the list. All invalid addresses must be set to a valid + address RefAddr[0] by the driver. The same applies to VC1 and MPEG2. + Programming Notes + AVC: Always specifies all 16 addresses even some of them are not needed as indicated by the max + num of active reference pictures. This is done for preventing data corruption (error, fault condition, etc.) + by having all the references being set to a legal location. + 5:4 Reference Picture (RefAddr[0-15]) – Arbitration Priority Control + Format: U2 Enumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 41 + MFX_PIPE_BUF_ADDR_STATE + 00b Highest priority + 01b Second highest priority + 10b Third highest priority + 11b Lowest priority + 2 Reference Picture (RefAddr[0-15]) - Graphics Data Type (GFDT) + Project: All + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads.H/W only reads this bit from the very first RefAddr[0][bit 3:0], all other RefAddr[i][bit + 3:0] are ignored by H/W and are assumed to have the same values as that of RefAddr[0]. + + 1:0 Reference Picture (RefAddr[0-15]) - Cacheability Control + Project: All + Format: U2 Enumerated Type + + + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC).H/W only reads + this bit from the very first RefAddr[0][bit 3:0], all other RefAddr[i][bit 3:0] are ignored by H/W and are + assumed to have the same values as that of RefAddr[0]. + Value Name Description + 00b GTT entry use cacheability control bits from GTT entry + 01b not in LLC or MLC data is not cached in LLC or MLC + 10b in LLC but not MLC data is cached in LLC but not MLC + 11b both LLC and MLC data is cached in both LLC and MLC +23 31:6 Macroblock Status Buffer Base Address (MacroblockStatAddr) + Project: All + Format: MacroblockStatusAddress[31:6] 64 byte aligned buffer + + + Specifies the address for reading the per-MB indirect data from memory when MacroblockStatEnable is + set in the MFX_AVC_IMG_STATE Command.For decoder : this field is ignored by hardware.For + encoder: this field is used for dynamic repeat of frame in PAK for Rate Control. Also used for feeding + coding information back to the Host, Video Preprocessing Unit and ENC Unit.All data are written in + fixed formats, and therefore all record sizes are known in the hardware. Hardware can calculate the + offset into this base address for per-MB data. + + 5:4 Arbitration Priority Control + Project: All + Format: U2 Enumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + 00b Highest priority + 01b Second highest priority + 10b Third highest priority + 11b Lowest priority + 2 Graphics Data Type (GFDT + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 42 + MFX_PIPE_BUF_ADDR_STATE + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + + 1:0 Cacheability Control + Project: All + Format: U2 Enumerated Type + + + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description + 00b GTT use cacheability control bits from GTT entry + 01b Not in LLC or MLC data is not cached in LLC or MLC + 10b In LLC but not MLC data is cached in LLC but not MLC + 11b both LLC and MLC data is cached in both LLC and MLC +24 31:1 Reserved + + Format: MBZ + 0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 43 + 1.7.6 MFX_IND_OBJ_BASE_ADDR_STATE Command + + MFX_IND_OBJ_BASE_ADDR_STATE + +Source: VideoCS +Length Bias: 2 +This state command provides the memory base addresses for all row stores, StreamOut buffer and reconstructed +picture output buffers required by the MFD or MFC Engine (that are in addition to the row stores of the Bit Stream +Decoding/Encoding Unit (BSD/BSE) and the reference picture buffers). This is a picture level state command and is +common among all codec standards and for both encoder and decoder operating modes. However, some fields may +only applicable to a specific codec standard. All Pixel Surfaces (original, reference frame and reconstructed frame) in +the Encoder are programmed with the same surface state (NV12 and TileY format), except each has its own frame +buffer base address. In the tile format, there is no need to provide buffer offset for each slice; since from each MB +address, the hardware can calculated the corresponding memory location within the frame buffer directly. +The MFX_IND_OBJ_BASE_ADDR command sets the memory base address pointers for the corresponding Indirect +Object Data Start Addresses (Offsets) specified in each OBJECT commands. The characteristic of these indirect +object data is their variable size (per MB or per Slice). Hence, each OBJECT command must specify the indirect +object data offset from the base address to start fetching or writing object data. While the use of base address is +unconditional, the indirection can be effectively disabled by setting the base address to zero. For decoder, there are +only 1 read-only per-slice indirect object in the BSD_OBJECT Command, and2 read-only per-MB indirect objects in +the IT_OBJECT CommandFor decoder : the Video Command Streamer (VCS) will perform the memory access +bound check automatically using the corresponding MFC Indirect Object Access Upper Bound specification. If any +access is at or beyond the upper bound, zero value is returned. The request to memory is still being sent, but the +corresponding codec’s BSD unit will detect this condition and perform the zeroing return. If the Upper Bound is +turned off, the beyond bound request will return whatever on the bus (invalid data).For encoder, there are 1 read- +only per-MB indirect object in the PAK_OBJECT Command, and1 write-only per-slice indirect object in the PAK +Slice_State CommandFor encoder : whenever an out of bound address accessing request is generated, VMX will +detect such requests and snap the address to the corresponding [indirect object base address + indirect data start +address]. VMX will return all 0s as the data to the requestor. NotationDefinitionPhysicalAddress[n:m]Corresponding +bits of a physical graphics memory byte address (not mapped by a GTT)GraphicsAddress[n:m]Corresponding bits of +an absolute, virtual graphics memory byte address (mapped by a GTT). +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_IND_OBJ_BASE_ADDR_STATE + Format: OpCode + 26:24 Common Opcode + Default Value: 0h MFX_IND_OBJ_BASE_ADDR_STATE + Format: OpCode + 23:21 Sub OpcodeA + Default Value: 0h MFX_IND_OBJ_BASE_ADDR_STATE + Format: OpCode + 20:16 SubOpcodeB + Default Value: 3h MFX_IND_OBJ_BASE_ADDR_STATE + Format: OpCode + 15:12 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 44 + MFX_IND_OBJ_BASE_ADDR_STATE + Format: MBZ + 11:0 DWord Length + Default Value: 0009h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:12 MFX Indirect Bitstream Object - Base Address (Decoder and Stitch Modes) + Project: All + Format: GraphicsAddress[31:12] + Specifies the 4K-byte aligned memory base address for the read-only indirect data object pointed in the + MFD_XXX_BSD_OBJECT command for fetching (reading) the compressed Slice Data.This field is only + valid in MPEG2, AVC and VC1 decoder VLD mode. + + 11:6 Reserved + Project: All + Format: MBZ + 5:4 MFX Indirect BSD Object – Arbitration Priority Control + Project: All + Format: U2 Enumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + 00b Highest priority + 01b Second highest priority + 10b Third highest priority + 11b Lowest priority + 2 MFX Indirect Bitstream Object - Graphics Data Type (GFDT) + Project: All + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + + 1:0 MFX Indirect Bitstream Object - Cacheability Control + Project: All + Format: U2 Enumerated Type + + + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description + 00b GTT entry use cacheability control bits from GTT entry + 01b not in LLC or MLC data is not cached in LLC or MLC + 10b in LLC but not MLC data is cached in LLC but not MLC + 11b both LLC and MLC data is cached in both LLC and MLC +2 31:12 MFX Indirect Bitstream Object - Access Upper Bound (Decoder and Stitch Modes) + Project: All + Format: GraphicsAddress[31:12] + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 45 + MFX_IND_OBJ_BASE_ADDR_STATE + This field specifies the 4K-byte aligned (exclusive) maximum Graphics Memory address access by the + indirect data object in the MFD_XXX_BSD_OBJECT command for the compressed Slice Data. Indirect + data accessed at this address and beyond will return as 0 by the hardware. Setting this field to 0 will + cause this range check to be ignored.If non-zero, this address must be greater than the MFX Indirect + Bitstream ObjectBase Address state.Hardware ignores this field if indirect data is not present, i.e. the + Indirect Data Length field of the MFD_XXX_BSD_OBJECT command is set to 0.This field is only valid + in MPEG2, AVC and VC1 decoder VLD mode. + + 11:0 Reserved + Project: All + Format: MBZ +3 31:12 MFX Indirect MV Object - Base Address + Project: All + Format: GraphicsAddress[31:12] + Specifies the 4K-byte aligned memory base address for the read-only indirect data object pointed in the + encoder MFC_AVC_PAK_OBJECT command or the decoder MFD_IT_OBJECT command for fetching + the per-MB MV data.This field is only valid in AVC encoder mode or in AVC decoder IT mode + + 11:6 Reserved + Project: All + Format: MBZ + 5:4 MFX Indirect MV Object - Arbitration Priority Control + Project: All + Format: U2 Enumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + 00b Highest priority + 01b Second highest priority + 10b Third highest priority + 11b Lowest priority + 2 MFX Indirect MV Object - Graphics Data Type (GFDT) + Project: All + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + + 1:0 MFX Indirect MV Object - Cacheability Control + Project: All + Format: U2 + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description + 00b From GTT entry use cacheability control bits from GTT entry + 01b Not cached in LLC or MLC data is not cached in LLC or MLC + 10b In LLC but not MLC data is cached in LLC but not MLC + 11b Both LLC and MLC data is cached in both LLC and MLC +4 31:12 MFX Indirect MV Object Access Upper Bound + Project: All + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 46 + MFX_IND_OBJ_BASE_ADDR_STATE + Format: GraphicsAddress[31:12] + This field specifies the 4K-byte aligned (exclusive) maximum Graphics Memory address access by the + indirect data object in the MFC_AVC_PAK_OBJECT / MFD_IT_OBJECT command for the per-MB MV + data. Indirect data accessed at this address and beyond will return as 0 by the hardware. Setting this + field to 0 will cause this range check to be ignored.If non-zero, this address must be greater than the + MFX Indirect MV Object Base Address state.Hardware ignores this field if indirect data is not present, + i.e. the Indirect Data Length field of the MFC_AVC_PAK_OBJECT / MFD_IT_OBJECT command is set + to 0.This field is only valid in AVC encoder mode or in AVC decoder IT mode. + + 11:0 Reserved + Project: All + Format: MBZ +5 31:12 MFD Indirect IT-COEFF Object - Base Address (Decoder Only) + Project: All + Format: GraphicsAddress[31:12] + Specifies the 4K-byte aligned memory base address for the read-only indirect data object pointed in the + MFD_IT_OBJECT command for fetching (reading) the per-MB non-scaled coefficient data (all inverse + scaling and quantization are done in hardware).This field is only valid in MPEG2, AVC and VC1 + decoder IT mode. + + 11:6 Reserved + Project: All + Format: MBZ + 5:4 MFD Indirect IT-COEFF Object - Arbitration Priority Control + Project: All + Format: U2 Enumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + 00b Highest priority + 01b Second highest priority + 10b Third highest priority + 11b Lowest priority + 2 MFD Indirect IT-COEFF Object - Graphics Data Type (GFDT) + Project: All + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + + 1:0 MFD Indirect IT-COEFF Object - Cacheability Control + Project: All + Format: U2 Enumerated type + + + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description + 00b From GTT entry use cacheability control bits from GTT entry + 01b Not in LLC or MLC data is not cached in LLC or MLC + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 47 + MFX_IND_OBJ_BASE_ADDR_STATE + 10b In LLC but not MLC data is cached in LLC but not MLC + 11b Both LLC and MLC data is cached in both LLC and MLC +6 31:12 MFD Indirect IT-COEFF Object - Access Upper Bound (Decoder Only) + Project: All + Format: GraphicsAddress[31:12] + This field specifies the 4K-byte aligned (exclusive) maximum Graphics Memory address access by the + indirect data object in the MFD_IT_OBJECT command for the per-MB non-scaled coefficient data. + Indirect data accessed at this address and beyond will return as 0 by the hardware. Setting this field to + 0 will cause this range check to be ignored.If non-zero, this address must be greater than the MFD + Indirect IT-COEFF Object Base Address state.Hardware ignores this field if indirect data is not present, + i.e. the Indirect COEFF Data Length field of the MFD_IT_OBJECT command is set to 0.This field is + only valid in MPEG2, AVC and VC1 decoder IT mode. + + 11:0 Reserved + Project: All + Format: MBZ +7 31:12 MFD Indirect IT-DBLK Object - Base Address (Decoder Only) + Project: All + Format: GraphicsAddress[31:12] + Specifies the 4K-byte aligned memory base address for the read-only indirect data object pointed in the + MFD_IT_OBJECT command for fetching (reading) the per-MB Deblocking filter control data.This field is + only valid in AVC decoder IT mode. + + 11:6 Reserved + Project: All + Format: MBZ + 5:4 MFD Indirect IT-DBLK Object - Arbitration Priority Control + Project: All + Format: U2 Enumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + 00b Highest priority + 01b Second highest priority + 10b Third highest priority + 11b Lowest priority + 2 MFD Indirect IT-DBLK Object - Graphics Data Type (GFDT) + Project: All + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + + 1:0 MFD Indirect IT-DBLK Object - Cacheability Control + Project: All + Format: U2 Enumerated Type + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 48 + MFX_IND_OBJ_BASE_ADDR_STATE + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description Project + 00b From GTT entry use cacheability control bits from GTT entry All + 01b Not cached in LLC or MLC data is not cached in LLC or MLC All + 10b In LLC but not MLC data is cached in LLC but not MLC All + 11b Both LLC and MLC data is cached in both LLC and MLC All +8 31:12 MFD Indirect IT-DBLK Object Access Upper Bound (Decoder Only) + Project: All + Format: GraphicsAddress[31:12] + Format: GraphicsAddress[31:12] + This field specifies the 4K-byte aligned (exclusive) maximum Graphics Memory address access by the + indirect data object in the MFD_IT_OBJECT command for the per-MB Deblocking filter control data. + Indirect data accessed at this address and beyond will return as 0 by the hardware. Setting this field to + 0 will cause this range check to be ignored.If non-zero, this address must be greater than the MFD + Indirect IT-DBLK Object Base Address state.Hardware ignores this field if indirect data is not present, + i.e. the Indirect Deblocking Control Data Length field of the MFD_IT_OBJECT command is set to 0.This + field is only valid in AVC decoder IT mode. + + 11:0 Reserved + Project: All + Format: MBZ +9 31:12 MFC Indirect PAK-BSE Object - Base Address (Encoder Only) + Project: All + Format: GraphicsAddress[31:12] + Specifies the 4K-byte aligned memory base address for the write-only indirect data object pointed in + the PAK_SLICE_STATE command for writing out the compressed bitstream.This field is only valid in + AVC encoder mode. + + 11:6 Reserved + Project: All + Format: MBZ + 5:4 MFC Indirect PAK-BSE Object - Arbitration Priority Control + Project: All + Format: U2 Enumerated Type + + + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name + 00b Highest priority + 01b Second highest priority + 10b Third highest priority + 11b Lowest priority + 2 MFC Indirect PAK-BSE Object - Graphics Data Type (GFDT) + Project: All + Format: U1 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 49 + MFX_IND_OBJ_BASE_ADDR_STATE + 1:0 MFC Indirect PAK-BSE Object - Cacheability Control + Project: All + Format: U2 Enumerated Type + + + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description + 00b GTT entry use cacheability control bits from GTT entry + 01b Not in LLC or MLC data is not cached in LLC or MLC + 10b In LLC but not MLC data is cached in LLC but not MLC + 11b Both LLC and MLC data is cached in both LLC and MLC +10 31:12 MFC Indirect PAK-BSE Object - Access Upper Bound (Encoder Only) + Project: All + Format: GraphicsAddress[31:12] + This field specifies the 4K-byte aligned (exclusive) maximum Graphics Memory address access by the + indirect data object in the PAK_SLICE_STATE command for the per-slice output bitstream. Indirect + data accessed at this address and beyond will be blocked by the hardware and ignored. Setting this + field to 0 will cause this range check to be ignoredIf non-zero, this address must be greater than the + MFC Indirect PAK-BSE Object Base Address state.This field is only valid in AVC encoder mode. + + 11:0 Reserved + Project: All + Format: MBZ + + + + +1.7.7 MFX_PAK_INSERT_OBJECT + + MFX_PAK_INSERT_OBJECT + +Source: VideoCS +Length Bias: 2 + Description Project +The MFX_PAK_INSERT_OBJECT command is the first primitive command for the AVC and MPEG2 +Encoding Pipeline. +This command is issued to setup the control and parameters of inserting a chunk of compressed/encoded +bits into the current bitstream output buffer starting at the specified bit locationto perform the actual insertion +by transferring the command inline data to the output buffer max, 32 bits at a time. + + It is a variable length command as the data to be inserted are presented as inline data of this command. It + is a multiple of 32-bit (1 DW), as the data bus to the bitstream buffer is 32-bit wide. + + Multiple insertion commands can be issued back to back in a series. It is host software’s responsibility to + make sure their corresponding data will properly stitch together to form a valid H.264 bitstream. + + Internally, MFX hardware will keep track of the very last two bytes’ (the very last byte can be a partial byte) + values of the previous insertion. It is required that the next Insertion Object Command or the next PAK + Object Command to perform the start code emulation sequence check and prevention 0x03 byte insertion + with this end condition of the previous insertion. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 50 + MFX_PAK_INSERT_OBJECT + Hardware will keep track of an output bitstream buffer current byte position and the associated next bit + insertion position index. Data to be inserted can be a valid H.264 NAL units or a partial NAL unit. Certain + NAL unit has a minimum byte size requirement. As such the hardware will optionally (enabled by STATE + Command) determines the number of CABAC_ZERO_WORD to be inserted to the end of the current NAL, + based on the minimum byte size of a NAL and the actual bin count of the encoded Slice. Since prior to the + CABAC_ZERO_WORD insertion, the RBSP or EBSP is already byte-aligned, so each + CABAC_ZERO_WORD insertion is actually a 3-byte sequence 0x00 00 03. The inline data may have + already been processed for start code emulation byte insertion, except the possibility of the last 2 bytes plus + the very last partial byte (if any). Hence, when hardware performing the concatenation of multiple + consecutive insertion commands, or concatenation of an insertion command and a PAK object command, it + must check and perform the necessary start code emulation byte insert at the junction.The inline data is + required to be byte aligned on the left (first transmitted bit order) and may or may not be byte aligned on the + right (last transmitted bits). + + The command will specify the bit offset of the last valid DW.Each insertion state command defines a chunk + of bits (compressed data) to be inserted at a specific location of the output compressed bitstream in the + output buffer.Depend on CABAC or CAVLC encoding mode (from Slice State), PAK Object Command is + always ended in byte aligned output bitstream except for CABAC header insertion which is bit aligned. In + the aligned cases, PAK will perform 0 filling in CAVLC mode, and 1 filling in CABAC mode. + + Insertion data can include:any encoded syntax elements bit data before the encoded Slice Data (PAK + Object Command) of the current SliceSPS NALPPS NALSEI NALOther Non-Slice + NALLeading_Zero_8_bits (as many bytes as there is)Start Code PrefixNAL Header ByteSlice HeaderAny + encoded syntax elements bit data after the encoded Slice Data (PAK Object Command) of the current Slice + and prior to the next encoded Slice Data of the next Slice or prior to the end of the bistream, whichever + comes firstCabac_Zero_Word or Trailing_Zero_8bits (as many bytes as there is). + + Anything listed above before a Slice DataContext switch interrupt is not supported by this command. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_PAK_INSERT_OBJECT + Format: OpCode + 26:24 Media Command Opcode + Default Value: 0h MFX_COMMON + Format: OpCode + 23:21 SubOpcode A + Default Value: 2h + Format: OpCode + 20:16 SubOpcode B + Default Value: 8h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 0h Excludes DWord (0,1) = Variable Length in DW + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 51 + MFX_PAK_INSERT_OBJECT + Format: =n Total Length - 2 + + + +1 31:18 Reserved + Format: MBZ + 17:16 DataByteOffset – SrcDataStartingByteOffset[1:0] + Source Data Starting Byte Position within the very first inline DW. + 15:14 Reserved + Format: MBZ + 13:8 DataBitsInLastDW – SrCDataEndingBitInclusion[5:0] + Source Data to be included in the very last inline DW. Follows the MSBit is the upper bit of each byte + within the DW. The lower byte is actually processed first.For example, SrCDataEndingBitInclusion = 9, + bit 7:0 and bit 15 are included as valid header data. + Value Name + [1,32] + 7:4 SkipEmulByteCnt – Skip Emulation Byte Count + Skip emulation check for number of starting bytesIt can be programmed from 0 to 15 bytes.For + example, to skip the start code that has already prefixed in the bitstream. + 3 EmulationFlag – EmulationByteBitsInsertEnable + Value Name + 1 instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and + Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that + hardware will handle a start code prefix crossing the boundary between + 2 insertion commands, or an insertion command followed by a PAK Object command. + 2 LastHeaderFlag – LastSrcHeaderDataInsertCommandFlag + To process a series of consecutive insertion commands, this flag (=1) indicates the current command + is the last ‘header’ insertion in the series.In CABAC, hardware must perform the “1” insert for byte align + for Slice Header before Slice Data comes in in the next PAK-OBJECT command.In CAVLC, hardware + ignores this bit + 1 EndOfSliceFlag – LastDstDataInsertCommandFlag + No more insertion command and no more PAK-OBJECT command follows.Flush data out to memory + 0 BitstreamStartReset – ResetBitStreamStartingPos + Value Name + 1 Reset the bitstream buffer insertion position to the bitstream buffer starting position. + 0 Insert the current command inline data starting at the current bitstream buffer insertion position +2..n 31:0 Insert Data PayLoad + Actual Data to be inserted to the output bitstream buffer. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 52 + 1.7.8 MFX_STITCH_OBJECT + + MFX_STITCH_OBJECT +Project: All +Source: VideoCS +Length Bias: 2 +The MFC_STITCH_OBJECT command is used when stitch-enabled is set to 1, while CodecSel and StandardSel are +set to ENCODE and AVC, respectively.This command is used, for example, to stitch multiple bitstreams to form a +transport stream. . It is a variable length command as the data to be inserted are presented as either inline data +and/or indirect data of this command. Multiple insertion commands can be issued back to back in a series. It is host +software’s responsibility to make sure their corresponding data will properly stitch together to form a valid output. +Hardware keeps track of an output bitstream buffer current byte position and the associated next bit insertion position +index. Context switch interrupt is not supported by this command. In order to support interrupt, it is software’s +responsibility to set up ARB_ON/OFF commands at the proper position to allow interrupt. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFC_STITCH_OBJECT + Format: OpCode + 26:24 Media Command Opcode + Default Value: 0h MFX_COMMON + Format: OpCode + 23:21 SubOpcode A + Default Value: 2h + Format: OpCode + 20:16 SubOpcode B + Default Value: Ah + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 0h Excludes DWord (0,1) = Variable Length in DW (>= 3) + Format: =n Total Length - 2 + + + If it is 3, it indicates the absent of inline data. + +1 31:18 Reserved + Format: MBZ + 17:16 Source Data Starting Byte Offset + Source Data Starting Byte Position within the very first inline DW. + 15:14 Reserved + Format: MBZ + 13:8 Source Data Ending Bit Inclusion + Source Data to be included in the very last inline DW. Follows the MSBit is the upper bit of each byte + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 53 + MFX_STITCH_OBJECT + within the DW. The lower byte is actually processed first.For example, SrCDataEndingBitInclusion =9, + bit 7:0 and bit 15 are included as valid header data. + Value Name + [1,32] + 2 Last Source Header Data Insert Command Flag + To process a series of consecutive insertion commands, this flag (=1) indicates the current command + is the last ‘header’ insertion in the series.In CABAC, hardware must perform the “1” insert for byte align + for Slice Header before Slice Data comes in in the next PAK-OBJECT command.In CAVLC, hardware + ignores this bit. + 1 Last Destination Data Insert Command Flag + THIS FIELD MUST BE THE SAME AS Last Source Header Data Insert Command Flag + No more insertion command and no more PAK-OBJECT command follows.Flush data out to memory +2 31:19 Reserved + Project: All + Format: MBZ + 18:0 Indirect Data Length + + Format: U19 + This field provides the length in bytes of the indirect data. A value zero indicates that indirect data + fetching is disabled – subsequently, the Indirect Data Start Address field is ignored. This field must + have the same alignment as the Indirect Object Data Start Address. + +3 31:0 Indirect Data Start Address + Format: MfxIndirectBitstreamObjectAddress[31:0] + This field specifies the Graphics Memory starting address of the data to be loaded into the kernel for + processing. This pointer is relative to the MFX Indirect Bitstream Object Base Address. + Hardware ignores this field if indirect data is not present. + Value Name + [0,FFFFFFFFh] +4..n 31:0 Insert Data PayLoad + Inline data to be inserted to the output bitstream buffer + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 54 + 1.7.9 MFX_QM_STATE Command + + MFX_QM_STATE + +Source: VideoCS +Length Bias: 2 +This is a common state command for AVC encoder modes. For encoder, it represents both the forward QM matrices +as well as the decoding QM matrices.This is a Frame-level state. Only Scaling Lists specified by an application are +being sent to the hardware. The driver is responsible for determining the final set of scaling lists to be used for +decoding the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A and B).In MFX AVC PAK mode, +PAK needs both forward Q scaling lists and IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan +order. But the Forward Q scaling lists are sent in column-wise raster order (column-by-column) to simplify the H/W. +Driver will perform all the scan order conversion for both ForwardQ and IQ. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_MULTI_DW + Format: OpCode + 26:24 Media Command Opcode + Default Value: 0h MFX_COMMON_STATE + Format: OpCode + 23:21 SubOpcode A + Default Value: 0h + Format: OpCode + 20:16 SubOpcode B + Default Value: 8h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 20h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:2 Reserved + Format: MBZ + 1:0 AVC or MPEG2 or JPEG + For AVC QM Type: This field specifies which Quantizer Matrix is loaded. + For MPEG2 QM Type: This field specifies which Quantizer Matrix is loaded. + + + Value Name Exists If + 0 AVC_4x4_Intra_MATRIX, (Y-4DWs, Cb-4DWs, Cr-4DWs, reserved- AVC- Decoder Only + 4DWs) + 1 AVC_4x4_Inter_MATRIX, (Y-4DWs, Cb-4DWs, Cr-4DWs, reserved- AVC- Decoder Only + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 55 + MFX_QM_STATE + 4DWs) + 2 AVC_8x8_Intra_MATRIX AVC- Decoder Only + 3 AVC_8x8_Inter_MATRIX AVC- Decoder Only + + 0 MPEG_INTRA_QUANTIZER_MATRIX MPEG2- Decoder + Only + 1 MPEG_NON_INTRA_QUANTIZER_MATRIX MPEG2- Decoder + Only + 2-3 Reserved MPEG2- Decoder + Only + + + + + Programming Notes + For JPEG encoder, each quantization element presents 16-bit 1/QM[i][j]. +2..33 31:0 Forward Quantizer Matrix + Project: All + Format: U32 + The format of a Quantizer Matrix is an 8x8 matrix in raster order. Each element is an unsigned + byte. + + + + + Bits 31:24 23:16 15:8 7:0 + Dword 1 QuantMatrix[0][3] QuantMatrix[0][2] QuantMatrix[0][1] QuantMatrix[0][0] + Dword 2 QuantMatrix[0][7] QuantMatrix[0][6] QuantMatrix[0][5] QuantMatrix[0][4] + Dword 3 QuantMatrix[1][3] QuantMatrix[1][2] QuantMatrix[1][1] QuantMatrix[1][0] + … … … … … +Dword 16 QuantMatrix[7][7] QuantMatrix[7][6] QuantMatrix[7][5] QuantMatrix[7][4] + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 56 + 1.7.10 MFX_FQM_STATE Command + + MFX_QM_STATE + +Source: VideoCS +Length Bias: 2 +This is a common state command for AVC encoder modes. For encoder, it represents both the forward QM matrices +as well as the decoding QM matrices.This is a Frame-level state. Only Scaling Lists specified by an application are +being sent to the hardware. The driver is responsible for determining the final set of scaling lists to be used for +decoding the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A and B).In MFX AVC PAK mode, +PAK needs both forward Q scaling lists and IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan +order. But the Forward Q scaling lists are sent in column-wise raster order (column-by-column) to simplify the H/W. +Driver will perform all the scan order conversion for both ForwardQ and IQ. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_MULTI_DW + Format: OpCode + 26:24 Media Command Opcode + Default Value: 0h MFX_COMMON_STATE + Format: OpCode + 23:21 SubOpcode A + Default Value: 0h + Format: OpCode + 20:16 SubOpcode B + Default Value: 8h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 20h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:2 Reserved + Format: MBZ + 1:0 AVC or MPEG2 or JPEG + For AVC QM Type: This field specifies which Quantizer Matrix is loaded. + For MPEG2 QM Type: This field specifies which Quantizer Matrix is loaded. + + + Value Name Exists If + 0 AVC_4x4_Intra_MATRIX, (Y-4DWs, Cb-4DWs, Cr-4DWs, reserved- AVC- Decoder Only + 4DWs) + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 57 + MFX_QM_STATE + 1 AVC_4x4_Inter_MATRIX, (Y-4DWs, Cb-4DWs, Cr-4DWs, reserved- AVC- Decoder Only + 4DWs) + 2 AVC_8x8_Intra_MATRIX AVC- Decoder Only + 3 AVC_8x8_Inter_MATRIX AVC- Decoder Only + + 0 MPEG_INTRA_QUANTIZER_MATRIX MPEG2- Decoder + Only + 1 MPEG_NON_INTRA_QUANTIZER_MATRIX MPEG2- Decoder + Only + 2-3 Reserved MPEG2- Decoder + Only + + + + + Programming Notes + For JPEG encoder, each quantization element presents 16-bit 1/QM[i][j]. +2..33 31:0 Forward Quantizer Matrix + Project: All + Format: U32 + The format of a Quantizer Matrix is an 8x8 matrix in raster order. Each element is an unsigned + byte. + + + + +This is a frame-level state. Reciprocal Scaling Lists are always sent from the driver regardless whether +they are specified by an application or the default/flat lists are being used. This is done to save the ROM +(to store the default matrices) inside the PAK Subsystem. Hence, the driver is responsible for determining +the final set of scaling lists to be used for encoding the current slice, based on the AVC Spec (Fall-Back +Rules A and B). For encoding, there is no need to send the qm_list_flags[i], i=0 to7 and qm_present_flag +to the PAK, since Scaling Lists syntax elements are encoded above Slice Data Layer. +FQM Reciprocal Scaling Lists elements are 16-bit each, conceptually equal to 1/ScaleValue. QM matrix +elements are 8-bit each, equal to ScaleValue. However, in AVC spec., the Reciprocal Scaling Lists +elements are not exactly equal to one-over of the corresponding Scaling Lists elements. The numbers are +adjusted to simplify hardware implementation. +For all the description below, a scaling list set contains 6 4x4 scaling lists (or forward scaling lists) and 2 +8x8 scaling lists (or forward scaling lists). +In MFX PAK mode, PAK needs both forward Q scaling lists and IQ scaling lists. The IQ scaling lists are +sent as in MFD in raster scan order as shown in MFX_AVC_QM_STATE. But the Forward Q scaling lists +are sent in transport form, i.e. column-wise raster order (column-by-column) to simplify the H/W. Driver +will perform all the scan order conversion for both ForwardQ and IQ. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 58 + Precisely, if the reciprocal forward scaling matrix is F[4][4], then the 16 word of the matrix will be set as +the following: + bits 0-15 bits 16-31 +DW0 F[0][0] F[1][0] +DW1 F[2][0] F[3][0] +DW2 F[0][1] F[1][1] +DW3 F[2][1] F[3][1] +DW4 F[0][2] F[1][2] +DW5 F[2][2] F[3][2] +DW6 F[0][3] F[1][3] +DW7 F[2][3] F[3][3] + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/18/2012 59 + 2. AVC (H.264) +2.1 AVC Common Commands +The following commands are common for AVC decode and AVC encode. + + +2.1.1 MFX_AVC_IMG_STATE Command + + MFX_AVC_IMG_STATE + +Source: VideoCS +Length Bias: 2 +This must be the very first command to issue after the surface state, the pipe select and base address setting +commands. This command supports both Long and Short VLD and IT DXVA2 AVC Decoding Interface. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_AVC_IMG_STATE + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h AVC_COMMON + Format: OpCode + 23:21 SubOpcode A + Default Value: 0h + Format: OpCode + 20:16 SubOpcode B + Default Value: 0h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default 0h Excludes DWord (0,1) + Value: + Project: All + Format: =n 00Eh, used for normal decode and encode mode000h, a special case to provide + a dummy image state for stitch mode operation. In this case, fields in DW1 which is + part of the dummy image state command are ignored by hardware. + + + +1 31:16 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 60 + MFX_AVC_IMG_STATE + 15:0 Frame Size + Project: All + Format: U16-1 in MB unit + + + The value for FrameSizeInMBs must match the product of FrameWidthInMBs and + FrameHeightInMBs.Max. Screen resolution is therefore limited to 256 x 256 in MB unit. This + parameter is specified for Intel interface only, not present in the DXVA. + Value Name Description + [0,16383] representing Number of MBs [1,16384] +2 31:24 Reserved + Project: All + Format: MBZ + (bit[31:24] must be zero to match the DXVA 16-bit definition for FrameHeightInMBsMinus1) + + 23:16 Frame Height + Project: All + Format: U8-1 in MB unit + + + It is set to the value of (FrameHeightInMBsMinus1+ 1). Since the max value for + FrameHeightInMBs is 255, the max allowed value for FrameHeightInMBsMinus1 is only 254. + The min value for FrameHeightInMBs is 1.Although the max. value that can be specified for + FrameHeightInMBs is 255 (in the current implementation), FrameWidthInMBs * + FrameHeightInMBs must not exceed the max value of FrameSizeInMBs[14:0].e.g. for + 1920x1080, FrameHeightInMBs[7:0] is equal to 68 (1080 divided by 16, and rounded up, i.e. + effectively specified as 1088 instead).It is derived from FrameHeightInMbs = ( 2 – + frame_mbs_only_flag ) * PicHeightInMapUnits and PicHeightInMbs = FrameHeightInMbs / ( 1 + + field_pic_flag ) internally done. For MBAFF, PicHeightInMapUnits is in MB pair unit, so the + bitstream sends only half frame height. + Value Name Description + [0,255] representing height [1,256] + 15:8 Reserved + Project: All + Format: MBZ + (bit[15:8] must be zero to match the DXVA 16-bit definition for FrameWidthInMBsMinus1) + + 7:0 Frame Width + Project: All + Format: U8-1 in MB unit + + + It is set to the value of (FrameWidthInMBsMinus1+ 1). Since the max value for + FrameWidthInMBs is 255, the max allowed value for FrameWidthInMBsMinus1 is only 254. + The min value for FrameWidthInMBs is 1.Although the max. value that can be specified for + FrameWidthInMBs is 255 (in the current implementation), FrameWidthInMBs * + FrameWidthInMBs must not exceed the max value of FrameSizeInMBs[14:0].e.g. for + 1920x1080, FrameHeightInMBs[7:0] is equal to 68 (1080 divided by 16, and rounded up, i.e. + effectively specified as 1088 instead).It is derived from FrameWidthInMbs = ( 2 – + frame_mbs_only_flag ) * PicWidthInMapUnits and PicWidthInMbs = FrameWidthInMbs / ( 1 + + field_pic_flag ) internally done. For MBAFF, PicWidthInMapUnits is in MB pair unit, so the + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 61 + MFX_AVC_IMG_STATE + bitstream sends only half frame width. + Value Name Description + [0,255] representing width [1,256] +3 31:29 Reserved + Project: All + Format: MBZ + (bit[31:29] must be zero to match the DXVA2 8-bit definition for InitQpChroma[1]) + + 28:24 Second Chroma QP Offset + Project: All + Signed integer value. It should be in the range of -12 to +12 (according to AVC spec).It + specifies the offset for determining QP Cr from QP Y. It is set to the upper 5 bits of the value + of the syntax element (Chroma_qp_offset[9:0]) read from the current active + PPS.Chroma_qp_offset [4:0] – chroma_qp_offset_bits (from the current active + PPS)Chroma_qp_offset [9:5] – second_chroma_qp_offset_bits + + 23:21 Reserved + Project: All + Format: MBZ + (bit[23:21] must be zero to match the DXVA2 8-bit definition for InitQpChroma[1]) + + 20:16 First Chroma QP Offset + Project: All + Signed integer value. It should be in the range of -12 to +12 (according to AVC spec).It + specifies the offset for determining QP Cb from QP Y. It is set to the lower 5 bits of the value + of the syntax element (Chroma_qp_offset[9:0]) read from the current active + PPS.Chroma_qp_offset [4:0] – chroma_qp_offset_bits (from the current active + PPS)Chroma_qp_offset [9:5] – second_chroma_qp_offset_bits + + 15:13 Reserved + Project: All + Format: MBZ + 12 Weighted_Pred_Flag + Project: All + (This field is defined differently from Gen6, Gen7 follows strictly DXVA2 AVC interface.) + Value Name + 0 specifies that weighted prediction is not used for P and SP slices [Default] + 1 specifies that weighted prediction is used for P and SP slices + + + Programming Notes + This field must set to '0' for B and I pictures. + 11:10 Weighted_BiPred_Idc + Project: All + (This field follows strictly DXVA2 AVC interface.) + Value Name + 0 Specifies that the default weighted prediction is used for B slices [Default] + 1 Specifies that explicit weighted prediction is used for B slices + 2 Specifies that implicit weighted prediction is used for B slices. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 62 + MFX_AVC_IMG_STATE + 3 Illegal value + + + Programming Notes + This field must set to 0 for P and I pictures. + 9:8 ImgStruct – Image Structure, img_structure[1:0] + Project: All + The current encoding picture structure can only takes on 3 possible values + Value Name + 00b Frame Picture + 01b Top Field Picture + 11b Bottom Field Picture + 10b Invalid, not allowed. + + + Programming Notes + img_structure[0] can be used as a flag to distinguish between frame and field structure. It + must be consistent with the field_pic_flag setting in the Slice Header.This parameter is + specified for Intel interface only, not present in the DXVA as a separate state (instead the + img_structure[1] is embedded inside the DXVA picture definition). + 7:0 Reserved + Project: All + Format: MBZ +4 31:16 MinFrameWSize + Default Value: 0h + Project: All + Format: U16 + + Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder Only)Mininum Frame Size is + specified to compensate for intel Rate Control Currently zero fill (no need to perform + emulation byte insertion) is done only to the end of the CABAC_ZERO_WORD insertion (if + any) at the last slice of a picture. Intel encoder parameter, not part of DXVA. The caller + should always make sure that the value, represented by Mininum Frame Size, is always less + than maximum frame size FrameBitRateMax (DWORD 10 bits 29:16).This field is reserved + in Decode mode. + + The programmable range 0…2^18-1 + + When MinFrameWSizeUnits is 00. + + Programmable range is 0…2^20-1 when MinFrameWSizeUnits is 01. + + Programmable range is 0…2^26-1 when MinFrameWSizeUnits is 10. + + Programmable range is 0…2^32-1 when MinFrameWSizeUnits is 11. + + 15 MbStatEnabled + Project: All + Enable reading in MB status buffer (a.k.a. encoding stream-out buffer) Note: For multi-pass + encoder, all passes except the first one need to set this value to 1. By setting the first pass to + 0, it does save some memory bandwidth. + Value Name Description Project + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 63 + MFX_AVC_IMG_STATE + 0 Disable Disable Reading of Macroblock Status Buffer All + 1 Enable Enable Reading of Macroblock Status Buffer All + 14 LoadSlicePointerFlag + Project: All + LoadBitStreamPointerPerSlice (Encoder-only)To support multiple slice picture and additional + header/data insertion before and after an encoded slice.When this field is set to 0, bitstream + pointer is only loaded once for the first slice of a frame. For subsequent slices in the frame, + bitstream data are stitched together to form a single output data stream.When this field is set + to 1, bitstream pointer is loaded for each slice of a frame. Basically bitstream data for different + slices of a frame will be written to different memory locations. + Value Name Description Project + 0 Disable Load BitStream Pointer only once for the first slice of a frame All + 1 Enable Load/reload BitStream Pointer only once for the each slice, reload the All + start location of the bitstream buffer from the Indirect PAK-BSE Object + Data Start Address field + 12 MvUnpackedFlag + Project: All + MVUnPackedEnable (Encoder Only)This field is reserved in Decode mode. + Value Name Description Project + 0 use packed MV format (compliant to DXVA) Desc All + 1 use unpacked 8MV/32MV format only Desc All + 11:10 ChromaFormatIdc + Project: All + Chroma Format IDC, ChromaFormatIdc[1:0]It specifies the sampling of chroma component + (Cb, Cr) in the current picture as follows : + Value Name Description Project + 00b monochrome picture Desc All + 01b 4:2:0 picture Desc All + 10b 4:2:2 picture (not supported) + 11b 4:4:4 picture (not supported) + + + Programming Notes + It is set to the value of the syntax element read from the current active SPS.The + corresponding Monochrome Flag (monochrome_flag) can be derived from this field. + 9 Reserved + Project: All + Format: MBZ + 8 MbMvFormatFlag + Project: All + Use MB level MvFormat flag (Encoder Only)(This bit must be set to zero in IVB:GT2:A0) + Value Name Description Project + 0 HW PAK ignore MvFormat When bit 12 == 0, all MBs use packed MV All + in the MB data. formatWhen bit 12 == 1, each MB data must use + unpacked MV format, 8MV when there is no minor + MV involved, and 32MV if there are some minor + MVs. + 1 (not for [SNB], [IVB] only) All + HW PAK will follow + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 64 + MFX_AVC_IMG_STATE + MvFormat value set within + each MB data. + + + Programming Notes + They must take one of the two values: the 8MV unpacked format (MvFormat =101b), and the + 32MV unpacked format (MvFormat =110b).This bit can be set only when MvUnpackedFlag + (bit 12 of this register) is set otherwise system could hang. + 7 EntropyCodingFlag + Project: All + Entropy Coding Flag, entropy_coding_flag + Value Name Description Project + 0 CAVLC bit-serial encoding mode Desc All + 1 CABAC bit-serial encoding mode. Desc All + + + Programming Notes + It specifies one of the two possible bit stream encoding modes in the AVC. It is set to the + value of the syntax element read from the current active PPS. + 6 ImgDisposableFlag + Project: All + Current Img Disposable Flag or Non-Reference Picture Flag + Value Name Description Project + 0 the current decoding picture may be used as a reference picture Desc All + for others + 1 the current decoding picture is not used as a reference picture Desc All + (e.g. a B-picture cannot be a reference picture for any subsequent + decoding) + + + Programming Notes + It is derived from ImgDisposableFlag = (nal_ref_idc == 0). nal_ref_idc is a syntax element + from a NAL unit. When this flag is set, no reference picture and DMV are written out.This field + is only valid for VLD decoding mode. + 5 ConstrainedIPredFlag + Project: All + Constrained Intra Prediction Flag, constrained_ipred_flagIt is set to the value of the syntax + element in the current active PPS. + Value Name Description Project + 0 allows both intra and inter neighboring MB to be used in the intra- Desc All + prediction encoding of the current MB. + 1 allows only to use neighboring Intra MBs in the intra-prediction Desc All + encoding of the current MB. If the neighbor is an inter MB, it is + considered as not available. + 4 Direct8x8InfFlag + Project: All + Direct 8x8 Inference Flag, direct_8x8_inference_flagIt is set to the value of the syntax + element in the current active SPS.It specifies the derivation process for luma motion vectors + in the Direct MV coding modes (B_Skip, B_Direct_16x16 and B_Direct_8x8). When + frame_mbs_only_flag is equal to 0, direct_8x8_inference_flag shall be equal to 1.It must be + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 65 + MFX_AVC_IMG_STATE + consistent with the frame_mbs_only_flag and transform_8x8_mode_flag settings. + Value Name Description Project + 0 allows subpartitioning to go below 8x8 block size (i.e. 4x4, 8x4 or Desc All + 4x8) + 1 allows processing only at 8x8 block size. MB Info is stored for 8x8 Desc All + block size. + 3 Transform8x8Flag + Project: All + 8x8 IDCT Transform Mode Flag, trans8x8_mode_flagSpecifies 8x8 IDCT transform may be + used in this pictureIt is set to the value of the syntax element in the current active PPS. + Value Name Description Project + 0 no 8x8 IDCT Transform, only 4x4 IDCT transform blocks are Desc All + present + 1 8x8 Transform is allowed Desc All + 2 FrameMbOnlyFlag + Project: All + Frame MB only flag, frame_mbs_only_flagIt is set to the value of the syntax element in the + current active SPS. + Value Name Description Project + 0 not true ; effectively enables the possibility of MBAFF mode. Desc All + 1 true, only frame MBs can occur in this sequence, hence disallows Desc All + the MBAFF mode and field picture. + 1 MbaffFlameFlag + Project: All + MBAFF mode is active, mbaff_frame_flag.It is derived from MbaffFrameFlag = + (mb_adaptive_frame_field_flag && ! field_pic_flag ). mb_adaptive_frame_field_flag is a + syntax element in the current active SPS and field_pic_flag is a syntax element in the current + Slice Header. They both are present only if frame_mbs_only_flag is 0. Although + mbaff_frame_flag is a Slice Header parameter, its value is expected to be the same for all the + slices of a picture.It must be consistent with the mb_adaptive_frame_field_flag, the + field_pic_flag and the frame_mbs_only_flag settings.This bit is valid only when the + img_structure[1:0] indicates the current picture is a frame. + Value Name Description Project + 0 not in MBAFF mode Desc All + 1 in MBAFF mode Desc All + 0 FieldPicFlag + Project: All + Field picture flag, field_pic_flag, specifies the current slice is a coded field or not.It is set to the + same value as the syntax element in the Slice Header. It must be consistent with the + img_structure[1:0] and the frame_mbs_only_flag settings.Although field_pic_flag is a Slice + Header parameter, its value is expected to be the same for all the slices of a picture. + Value Name Project + 0h a slice of a coded frame All + 1h a slice of a coded field All +5 31:17 Reserved + 16 NonFirstPassFlag +[ExistsIf]Encode This signals the current pass is not the first pass. It will imply designate HW behavior: e.g +Only Value Name Description Project + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 66 + MFX_AVC_IMG_STATE + 0h Disable Always use the MbQpY from initial PAK inline object for all passes of All + PAK + 1h Enable Use MbQpY from stream-out buffer if MbRateCtrlFlag is set to 1 All + 15:13 Reserved + Project: All + Format: MBZ + 12 InterMbZeroCbpFlag – InterMB Force CBP to Zero Control Flag + + Inter MB Force CBP ZERO mask. + Value Name Description + 0h Disable No Effect + 1h Enable Zero out all A/C coefficients for the inter MB violating Inter Confirmance + 11:10 MinFrameWSizeUnits + This field is the Minimum Frame Size Units + Value Name Description Project + 00b compatibility mode Minimum Frame Size is in old mode (words, 2bytes) All + 01b 16 byte Minimum Frame Size is in 16bytes All + 10b 4Kb Minimum Frame Size is in 4Kbytes All + 11b 16Kb Minimum Frame Size is in 16Kbytes All + 9 MbRateCtrlFlag – MB level Rate Control Enabling Flag + MB Rate Control conformance mask + Value Name Description Project + 0h Disable Apply accumulative delta QP for consecutive passes on top of the All + macroblock QP values in inline data + 1h Enable Apply RC QP delta to suggested QP values in Macroblock Status All + Buffer except the first pass. + + + Programming Notes + This field is ignored when MacroblockStatEnable is disabled or MB level Rate control flag for + the current MB is disable in Macroblock Status Buffer. + 8 Reserved + Project: All + Format: MBZ + 7 Intra/InterMbIpcmFlag – ForceIPCMControlMask + This field is to Force IPCM for Intra or Inter Macroblock size conformance mask. + Value Name Description Project + 0h Disable Do not change intra macroblocks even. + 1h Enable Change intra macroblocks MB_type to IPCM. + + + Programming Notes + This field is ignored when MacroblockStatEnable is disabled or MB level Intra MB + conformance flag for the current MB is disable in Macroblock Status Buffer. + 6:4 Reserved + Project: All + Format: MBZ + 3 FrameSzUnderFlag – FrameBitRateMinReportMask + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 67 + MFX_AVC_IMG_STATE + This is a mask bit controlling if the condition of frame level bit count is less than + FrameBitRateMin + Value Name Description Project + 0h Disable Do not update bit0 of MFC_IMAGE_STATUS control register. All + 1h Enable set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total All + frame level bit counter is less than or equal to Frame Bit rate Minimum + limit. + 2 FrameSzOverFlag – FrameBitRateMaxReportMask + This is a mask bit controlling if the condition of frame level bit count exceeds + FrameBitRateMax. + Value Name Description Project + 0 Disable Do not update bit0 of MFC_IMAGE_STATUS control register. All + 1 Enable Set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total All + frame level bit counter is greater than or equal to Frame Bit rate + Maximum limit. + 1 InterMbMaxBitFlag – InterMBMaxSizeReportMask + This is a mask bit controlling if the condition of any inter MB in the frame exceeds + InterMBMaxSize. + Value Name Description Project + 0 Disable Do not update bit0 of MFC_IMAGE_STATUS control register. All + 1 Enable Set bit0 of MFC_IMAGE_STATUS control register if the total bit counter All + for the current MB is greater than the Inter MB Conformance Max size + limit. + 0 IntraMbMaxBitFlag – IntraMBMaxSizeReportMask + This is a mask bit controlling if the condition of any intra MB in the frame exceeds + IntraMBMaxSize. + Value Name Description Project + 0h Disable Do not update bit0 of MFC_IMAGE_STATUS control register. All + 1 Enable set bit0 of MFC_IMAGE_STATUS control register if the total bit counter All + for the current MB is greater than the Intra MB Conformance Max size + limit. +6 31:28 Reserved + 27:16 InterMbMaxSz +[ExistsIf]Encode Project: All +Only Format: U12 + This field, Inter MB Conformance Max size limit,indicates the allowed max bit count size for + Inter MB + + 15:12 Reserved + Project: All + Format: MBZ + 11:0 IntraMbMaxSz + Project: All + Exists If: Intra Only + Format: U12 + + + This field, Intra MB Conformance Max size limit,indicates the allowed max bit count size for + Intra MB + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 68 + MFX_AVC_IMG_STATE + All IPCM MBs should ignore this Max size limit. +7 31:0 Reserved +8 31:24 SliceDeltaQpMax[3] + Format: S7 +[ExistsIf]Encode +Only + Range: [0:MAX_QP_DELTA] + This field is the Slice level delta QP for total bit-count above FrameBitRateMax - first 1/8 + regionThis field is used to calculate the suggested slice QP into the MFC_IMAGE_STATUS + control register when total bit count for the entire frame exceeds FrameBitRateMax but is + within 1/8 of FrameBitRateMaxDelta above FrameBitRateMax, i.e., in the range of + (FrameBitRateMax, (FrameBitRateMax+ FrameBitRateMaxDelta>>3). + 23:16 SliceDeltaQpMax[2] + Project: All + Format: U8 + + + Range: [0:MAX_QP_DELTA] + This field is the Slice level delta QP for bit-count above FrameBitRateMax - above 1/8 and + below 1/ 4 This field is used to calculate the suggested slice QP into the + MFC_IMAGE_STATUS control register when total bit count for the entire frame is between + 1/8 and ¼ of FrameBitRateMaxDelta above FrameBitRateMax, i.e., in the range of + ((FrameBitRateMax+ FrameBitRateMaxDelta>>3), (FrameBitRateMax+ + FrameBitRateMaxDelta>>2). + 15:8 SliceDeltaQpMax[1] + Format: S7 + + + Range: [0:MAX_QP_DELTA] + This field is the Slice level delta QP for bit-count above FrameBitRateMax – above1/ 4 and + below 1/2 This field is used to calculate the suggested slice QP into the + MFC_IMAGE_STATUS control register when total bit count for the entire frame is between ¼ + and ½ of FrameBitRateMaxDelta above FrameBitRateMax, i.e., in the range of + ((FrameBitRateMax+ FrameBitRateMaxDelta>>2), (FrameBitRateMax+ + FrameBitRateMaxDelta>>1). + 7:0 SliceDeltaQpPMax[0] + Format: S7 + + + Range: [0:MAX_QP_DELTA] + This field is the Slice level delta QP for bit-count above FrameBitRateMax - above 1/ 2This + field is used to calculate the suggested slice QP into the MFC_IMAGE_STATUS control + register when total bit count for the entire frame is above FrameBitRateMax by more than half + the distance of FrameBitRateMaxDelta , i.e., in the range of ((FrameBitRateMax+ + FrameBitRateMaxDelta>>1), infinite). +9 31:24 SliceDeltaQpMin[3] + Format: S7 +[ExistsIf]Encode +Only + Range: [0:MAX_QP_DELTA] + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 69 + MFX_AVC_IMG_STATE + This field is the Slice level delta QP for total bit-count below FrameBitRateMin - first 1/8 + regionThis field is used to calculate the suggested slice QP into the MFC_IMAGE_STATUS + control register when total bit count for the entire frame is less than FrameBitRateMin and + greater than or equal to 1/8 the distance of FrameBitRateMinDelta from FrameBitRateMin, + i.e., in the range of [(FrameBitRateMin- FrameBitRateMinDelta>>3), FrameBitRateMin). + 23:16 SliceDeltaQpMin[2] + Format: S7 + + + Range: [0:MAX_QP_DELTA] + This field is the Slice level delta QP for bit-count below FrameBitRateMin – below 1/ 8 and + above 1/ 4This field is used to calculate the suggested slice QP into the + MFC_IMAGE_STATUS control register when total bit count for the entire frame is between + one-eighth and quarter the distance of FrameBitRateMinDelta from FrameBitRateMin, i.e., in + the range of [(FrameBitRateMin- FrameBitRateMinDelta>>2), (FrameBitRateMin- + FrameBitRateMinDelta>>3)). + 15:8 SliceDeltaQpMin[1] + Format: S7 + + + Range: [0:MAX_QP_DELTA] + This field is the Slice level delta QP for bit-count below FrameBitRateMin– below 1/4 and + above 1/ 2This field is used to calculate the suggested slice QP into the + MFC_IMAGE_STATUS control register when total bit count for the entire frame is between + quarter and half the distance of FrameBitRateMinDelta from FrameBitRateMin, i.e., in the + range of [(FrameBitRateMin- FrameBitRateMinDelta>>1), (FrameBitRateMin- + FrameBitRateMinDelta>>2)). + 7:0 SliceDeltaQpMin[0] + Format: S7 + + + Range: [0:MAX_QP_DELTA] + This field is the Slice Level Delta QP for bit-count below FrameBitRateMin – below 1/ 2This + field is used to calculate the suggested slice QP into the MFC_IMAGE_STATUS control + register when total bit count for the entire frame is below FrameBitRateMin by more than half + the distance of FrameBitRateMinDelta , i.e., in the range of [0, (FrameBitRateMin- + FrameBitRateMinDelta>>1). +10 31 FrameBitrateMaxUnit + This field is the Frame Bitrate Maximum Limit Units. +[ExistsIf]Encode Value Name Description Project +Only 0 Byte FrameBitRateMax is in units of 32 Bytes when All + FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if + FrameBitrateMaxUnitMode is 0 + 1 Kilo FrameBitRateMax is in units of 4KBytes Bytes when All + Byte FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if + FrameBitrateMaxUnitMode is 0 + 30 FrameBitrateMaxUnitMode + This field is the Frame Bitrate Maximum Limit Units. + Value Name Description Project + 0h compatibility mode FrameBitRateMaxUnit is in old mode (128b/16Kb) All + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 70 + MFX_AVC_IMG_STATE + 1h New mode FrameBitRateMaxUnit is in new mode (32byte/4Kb) All + 29:16 FrameBitRateMax + This field is the Frame Bitrate Maximum Limit. This field along with FrameBitrateMaxUnit + determines maximum allowed bits in a frame before multi-pass gets triggered (when + enabled). In other words, multi-pass is triggered when the actual frame byte count exceeds + this value. When FrameBitrateMaxUnitMode is 0(compatibility mode) bits 16:27 should be + used, bits 28 and 29 should be 0.. + Value Name Description + 0-512KB The programmable range is 0-512KB when FrameBitrateMaxUnit is 0. + 0-8190KB The programmable range is 0-8190KB when FrameBitrateMaxUnit is 1. + 15 FrameBitrateMinUnit + This field is the Frame Bitrate Minimum Limit Units. + Value Name Description Project + 0 Byte FrameBitRateMax is in units of 32 Bytes when All + FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if + FrameBitrateMinUnitMode is 0 + 1 Kilo FrameBitRateMax is in units of 4KBytes Bytes when All + Byte FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if + FrameBitrateMaxUnitMode is 0 + 14 FrameBitrateMinUnitMode + This field is the Frame Bitrate Minimum Limit Units. + Value Name Description Project + 0h Compatibility mode FrameBitRateMaxUnit is in old mode (128b/16Kb) All + 1h New mode FrameBitRateMaxUnit is in new mode (32byte/4Kb) All + 13:0 FrameBitRateMin + RangeThe programmable range 0-512KB When FrameBitrateMinUnit is in 0.Programmable + range is 0–8190 KB when FrameBitrateMinUnit is in 1.This field is the Frame Bitrate Minimum + Limit ()This field along with FrameBitrateMinUnit determines minimum allowed bits in a Frame + before Multi-Pass gets triggered (when enabled). In other words, multi-pass is triggered when + the actual frame byte count is less than this value. When FrameBitrateMinUnitMode is 0 + (compatibility mode) bits 0:11 should be used, bits 12 and 13 should be 0. +11 31 Reserved + 30:16 FrameBitRateMaxDelta +[ExistsIf]Encode Project: All +Only Exists If: Always + Format: U15 + This field is used to select the slice delta QP when FrameBitRateMax Is exceeded. It shares + the same FrameBitrateMaxUnit. When FrameBitrateMaxUnitMode is 0(compatibility mode) + bits 16:27 should be used, bits 28, 29 and 30 should be 0. + Value Name Description + 0-1024KB The Programmable range 0-1024KB when FrameBitRateMaxUnit is 0. + 0- The Programmable range is 0–16380KB when FrameBitRateMaxUnit is + 16380KB 1. + 0h [Default] + 15 Reserved + Project: All + Format: MBZ + 14:0 FrameBitRateMinDelta + Range: The programmable range 0-1024KB When FrameBitrateMinUnit is in + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 71 + MFX_AVC_IMG_STATE + 32Bytes.Programmable range is 0–16380KB when FrameBitrateMinUnit is in 4Kbytes. + This field is used to select the slice delta QP + when FrameBitRateMin Is exceeded. It shares the same FrameBitrateMinUnit. When + FrameBitrateMinUnitMode is 0(compatibility mode) bits 0:11 should be used, bits + 12, 13 and 14 should be 0.Note: HW requires the following condition + FrameBitRateMinDelta <= 2*FrameBitRateMinMust be true, otherwise it may cause + unpredicted behavior. +12 31:0 Reserved + Project: All + Format: MBZ +13 31:30 Reserved + Project: All + Format: MBZ + 29 Current Picture Has Performed MMCO5 + Set to 1 if the current Pic has performed the memory_management_control_operation = = 5. + 28:24 Number of Reference Frames + Format: U5 + + + Range: Range 0 to MaxDpbSize (=16 for Level 4.1) + Specifies the maximum number of reference frames (frames, field pairs, unpaired field) + existed in the current DBP for decoding the current picture. + 23:22 Reserved + Project: All + Format: MBZ + 21:16 Number of Active Reference Pictures from L1 + Format: U6-1 + Specifies the initial maximum reference index value minus 1 to access the L1 Reference List. + It is extracted from PPS. It corresponds to the number of active reference pictures from L1 to + decode the current picture. It can be modified by the slice header if + num_ref_idx_active_override_flag is set. Only valid for B picture. + Value Name + [0,31] + 15:14 Reserved + Project: All + Format: MBZ + 13:8 Number of Active Reference Pictures from L0 + Format: U6-1 + Specifies the initial maximum reference index value minus 1 to access the L0 Reference List. + It is extracted from PPS. It corresponds to the number of active reference pictures from L0 to + decode the current picture. It can be modified by the slice header if + num_ref_idx_active_override_flag is set. Valid for both P and B pictures. + Value Name + [0,31] + 7:0 Initial QP Value + Format: S7 + + + Description Project + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 72 + MFX_AVC_IMG_STATE + Range: [-26,25] + Short Format Only + Initial QP value for a Slice, extracted from PPS. It may further get modified by + slice_qp_delta in slice header and mb_qp_delta in MB header. + + + +MAX_QP_DELTA : Maximum QP delta is the Magnitude of QP delta between passes. +MAX_QP_DELTA is selected such that cumulative QP over all possible passes shouldn’t exceed 51. +Example Configurations: +MAX Number of Passes MAX_QP_DELTA + 4 0xc + 5 0xa + 6 0x8 + 7 0x7 + + +2.1.2 MFX_AVC_DIRECTMODE_STATE Command + + MFX_AVC_DIRECTMODE_STATE + +Source: VideoCS +Length Bias: 2 +This is a slice level command and can be issued multiple times within a picture that is comprised of multiple slices. +All DMV buffers are treated as standard media surfaces, in which the lower 6 bits are used for conveying surface +states.Current Pic POC number is assumed to be available in POCList[32 and 33] of the +MFX_AVC_DIRECTMODE_STATE Command.This command is only valid in the AVC decoding in VLD and IT +modes, and AVC encoder mode. The same command supports both Long and Short DXVA2 AVC Interface. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_SINGLE_DW + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h AVC + Format: OpCode + 23:21 SubOpcodeA + Default Value: 0h MEDIA_ + Format: OpCode + 20:16 SubOpcodeB + Default Value: 2h Desc + Format: OpCode + 15:12 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 73 + MFX_AVC_DIRECTMODE_STATE + Format: MBZ + 11:0 DWord Length + Default Value: 0043h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:6 Direct MV Buffer Base Address for Picture 0 (current or reference top field) + This field provides the base address of the DMV write buffer to store motion vectors decoded in the + current picture (top field), which may be used later as a collocated motion information read buffer of the + associated reference picture in decoding subsequent B-pictures that have MB coded in direct mode. It + is a private buffer used by the MPR hardware only. Its content is not accessed by software.This buffer + must be 64-byte cacheline aligned.The write buffer size is 557,056 bytes for 1 frame. Scalable with + frame height, but do not scale with frame width as the hardware assumes frame width (in MBs) fixed at + 128 (smallest power of 2 value larger than 120 – 1920x1088 screen resolution)It is only valid if the + current picture is a progressive frame, MbAff frame, or a top field.There are a total of 32 reference + picture (previously decoded) Direct MV Buffers (0 to 31, not including the DMV write buffer 32 and 33 + of the current picture) to read in the corresponding collocated DMV and motion information. For + reference picture, these 32 DMV read Buffers can be indexed by the frame_store_ID[4:0], which is + obtained from RefPicList L0/L1[RefPicIdx]. frame_Store_IDbit[0] (indicator for Top/Bottiom Field).For + writing out motion information during the decoding of the current picture, all 34 DMV buffers can be + addressed by [ img_dec_fs_idc[4:0]<<1 + img_structure[1] ]. + 5:4 Direct MV Buffer – Arbitration Priority Control + This field controls the priority of arbitration used in the GAC/GAM pipeline for this surface. + Value Name Description Project + 00b Highest priority Desc All + 01b Second highest priority Desc All + 10b Third highest priority + 11b Lowest priority + + + Programming Notes + This field of Picture 0 DMV Buffer must always be programmed, regardless if this buffer is active or + not, exist or not. H/W only reads this bit to determine the arbitration priority control for all 34 possible + DMV buffers. This field is ignored in all the other DMV buffers 1 to 33. + 2 Direct MV Buffer - Graphics Data Type (GFDT) for Picture 0 + This field contains the GFDT bit for this surface when writes occur. GFDT can also be set by the GTT. + The effective GFDT is the logical OR of this field with the GFDT from the GTT entry. This field is + ignored for reads. + Value Name Description Project + 0h Disable Desc All + 1h Enable Desc All + + + Programming Notes + This field of Picture 0 DMV Buffer must always be programmed, regardless if this buffer is active or + not, exist or not. H/W only reads this bit to determine the GFDT for all 34 possible DMV buffers. This + field is ignored in all the other DMV buffers 1 to 33. + 1:0 Direct MV Buffer - Cacheability Control for Picture 0 + Format: U2 Enumerated Type + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 74 + MFX_AVC_DIRECTMODE_STATE + + This field controls cacheability in the mid-level cache (MLC) and last-level cache (LLC). + Value Name Description Project + 00b Use cacheability control bits from GTT entry Desc All + 01b Data is not cached in LLC or MLC Desc All + 10b Data is cached in LLC but not MLC + 11b Data is cached in both LLC and MLC + + + Programming Notes + This field of Picture 0 DMV Buffer must always be programmed, regardless if this buffer is active or + not, exist or not. H/W only reads this bit to determine the cacheability control for all 34 possible DMV + buffers. This field is ignored in all the other DMV buffers 1 to 33. +2 31:6 Direct MV Buffer Base Address for Picture 1 (current or reference bottom field) + This field provides the base address of the DMV read/write buffer for the current or reference picture + (bottom field). It is paired with the DMV Buffer of Picture 0 for MB pair retrieval during read.It follows the + same format specification as DMV buffer for Picture 0It is only valid if the current picture is a bottom + field. It is also valid + 5:4 Direct MV Buffer – Arbitration Priority Con + Project: All + Format: U2 + This field is ignored in H/W, and assumes the same value as of Picture 0 DMV Buffer specification + bit[5:4] above. + + 2 Direct MV Buffer - Graphics Data Type (GFDT) for Picture 1 + Project: All + Format: U1 + This field is ignored in H/W, and assumes the same value as of Picture 0 DMV Buffer specification + bit[2] above. + + 1:0 Direct MV Buffer -Cacheability Control for Picture 1 + Project: All + Format: U2 + This field is ignored in H/W, and assumes the same value as of Picture 0 DMV Buffer specification + bit[1:0] above. + +3..32 31:6 Direct MV Buffer Base Address for Reference Frame 2 to 31 + This field provides the base address of the DMV buffer for reference frame 2 to 31. They are needed if + the current B-Picture has MBs coded in direct mode. It is a private buffer used by the MPR hardware + only. Its content is not accessed by software.All these buffers must be 64-byte cacheline aligned.There + are a total of 32 possible Direct MV Read Buffers (not including the current write buffer of the current + picture) to read in the corresponding DMV. Each read buffer size is 557,056 bytes for 1 frame (the + selected colPic). Scalable with frame height, but do not scale with frame width as the hardware + assumes frame width (in MBs) fixed at 128 (smallest power of 2 value larger than 120 – 1920x1088 + screen resolution).The adjacent DMV buffers are paired ([2 and 3], [4 and 5], [N and N+1], ..[30 and + 31]). + 5:4 Direct MV Buffer – Arbitration Priority Control + Project: All + Format: U2 + This field is ignored in H/W, and assumes the same value as of Picture 0 DMV Buffer specification + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 75 + MFX_AVC_DIRECTMODE_STATE + bit[5:4] above. + + 2 Direct MV Buffer - Graphics Data Type (GFDT) for Reference Frame 2 to 31 + Project: All + Format: U1 + This field is ignored in H/W, and assumes the same value as of Picture 0 DMV Buffer specification + bit[2] above. + + 1:0 Direct MV Buffer - Cacheability Control for Reference Frame 2 to 31 + Project: All + Format: U2 + This field is ignored in H/W, and assumes the same value as of Picture 0 DMV Buffer specification + bit[1:0] above. + +33..34 31:6 Direct MV Buffer Base Addresses 32 and 33 (Write-Only Buffer), for Current Decoding + Frame/Field + This field provides the base address of the DMV write-only buffer for the current decoding frame/field.It + is a private buffer used by the MPR hardware only. Its content is not accessed by software.All these + buffers must be 64-byte cacheline aligned, i.e. the same as the above DMV read/write buffers.These 2 + buffers can only be addressed by [img_dec_fs_idc[4:0]<<1 + img_structure[1]] for the current picture + being decoded.Each write buffer size is 557,056 bytes for 1 frame (the selected colPic). Scalable with + frame height, but do not scale with frame width as the hardware assumes frame width (in MBs) fixed at + 128 (smallest power of 2 value larger than 120 – 1920x1088 screen resolution).DMV write buffer 32 is + valid only if the current picture is a progressive frame, MbAff frame, or a top field.DMV write buffer 33 is + valid only if the current picture is a bottom field. + 5:4 Direct MV Buffer 32 and 33 (Write-only Buffer) – Arbitration Priority Control + Project: All + Format: U2 + This field is ignored in H/W, and assumes the same value as of Picture 0 DMV Buffer specification + bit[5:4] above. + + 3 Reserved + This field is ignored for writes. + 2 Direct MV Buffer 32 and 33 (Write-only Buffer) - Graphics Data Type (GFDT) for Current + Frame/Field + Project: All + Format: U1 + This field is ignored in H/W, and assumes the same value as of Picture 0 DMV Buffer specification + bit[2] above. + + 1:0 Direct MV Buffer 32 and 33 (Write-only Buffer) - Cacheability Control for Current Frame/Field + Project: All + Format: U2 + This field is ignored in H/W, and assumes the same value as of Picture 0 DMV Buffer specification + bit[1:0] above. + +35..68 31:0 POC List, POCList[34][31:0] + Each POC value is a signed 32-bit number.One-to-one correspondence with the 34 Direct MV Buffer + Address for Reference and Currrent Frames/FieldsThere are 34 POC entries in the list. For reference + picture, only the lower 32 POC [0-31] entries can be used, and POCList[ ] is indexed by the + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 76 + MFX_AVC_DIRECTMODE_STATE + frame_store_ID[4:0], which is obtained from RefPicList L0/L1[RefPicIdx]. frame_Store_IDbit[0] + (indicator for Top/Bottiom Field).For current picture, all 34 POC entries [0-33] can be addressed by + POCList[ img_dec_fs_idc[4:0]<<1 + img_structure[1] ].For frame-only mode, every other entry is + skipped. For MBAFF and field-only picture, each entry is a field POC, and every two entries are paired. + + + + +2.1.3 MFX_AVC_SLICE_STATE Command + + MFX_AVC_SLICE_STATE + +Source: VideoCS +Length Bias: 2 +This is a slice level command and can be issued multiple times within a picture that is comprised of multiple slices. +The same command is used for AVC encoder (PAK mode) and decoder (VLD and IT modes). + Programming Notes +MFX_AVC_SLICE_STATE command is not issued for AVC DXVA2 Short Format Bitstream decode, instead +MFD_AVC_SLICEADDR command is executed to retrieve the next slice MB Start Address X and Y by H/W itself. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_AVC_SLICE_STATE + Format: OpCode + 26:24 Command Opcode + Default Value: 1h AVC + Format: OpCode + 23:21 SubOpcodeA + Default Value: 0h MFX_AVC_SLICE_STATE + Format: OpCode + 20:16 Command SubOpcodeB + Default Value: 3h MFX_AVC_SLICE_STATE + Format: OpCode + 15:12 Reserved + Format: MBZ + 11:0 DWord Length + Default Value: 8h DWORD_COUNT_n + Excludes DWords 0,1 + +1 31:4 Reserved + Format: MBZ + 3:0 Slice Type + It is set to the value of the syntax element read from the Slice Header. + Value Name + 0000b P Slice + 0001b B Slice + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 77 + MFX_AVC_SLICE_STATE + 0010b I Slice + 0011b-1111b Reserved + + + Programming Notes + Bits[3:2] must be 0 +2 31:30 Reserved + Format: MBZ + 29:24 Number of Reference Pictures in Inter-prediction List 1 + Format: U6 + This field is valid only for encoding a B Slice, for which it is expected to have at least one entry in the + reference list L1; otherwise (if Slice Type is not a B Slice ), this field must be set to 0. + This field can be derived for a B Slice from the Slice Header syntax element + NumRefIdxActiveMinus1 as, Num_Ref_Idx_L1 = NumRefIdxActiveMinus1[1] + 1. + Value Name + 0-32 + 23:22 Reserved + Format: MBZ + 21:16 Number of Reference Pictures in Inter-prediction List 0 + Format: U6 + This field is valid for encoding a P or B Slice, for which it is expected to have at least one entry in the + reference list L0; otherwise (if Slice Type is not a P or B Slice ), this field must be set to 0. + This field can be derived for a P or B Slice from the Slice Header syntax element + NumRefIdxActiveMinus1 as, Num_Ref_Idx_L0 = NumRefIdxActiveMinus1[0] + 1. + Value Name + 0-32 + 15:11 Reserved + Format: MBZ + 10:8 Log 2 Weight Denom Chroma + Format: U3 + + + Value Name + 0-7 + 7:3 Reserved + Format: MBZ + 2:0 Log 2 Weight Denom Luma + Format: U3 + It is the base 2 logarithm of the denominator for all Luma weighting factors. + It is set to the value of the syntax element read from the Slice Header Pred_Weight_Table(). + Value Name + 0-7 +3 31:30 Weighted Prediction Indicator + This field indicates the Weighted Prediction mode for a P or B Slice. It is a combined field + corresponding to the syntax element WeightedBiPredIdc or WeightedPredFlag read from the current + active PPS. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 78 + MFX_AVC_SLICE_STATE + If it is a B-Slice, these bits are interpreted as: + + + 00b – Specifies the default weighted inter-prediction to be applied + 01b – Specifies the explicit weighted inter-prediction to be applied + 10b – Specifies the implicit weighted inter-prediction to be applied + 11b – Reserved (not allowed) + + + + If it is a P Slice, these bits are interpreted as: + + + 00b – Disables weighted inter-prediction (Default weighted) + 01b – Enables weighted inter-prediction (Explicit weighted) + 10b - 11b – Reserved + Programming Notes + Only when in B Slice with Weighted_Pred_Idc = 1 (explicit weighted prediction), will there be a L1 + and/or a L0 weight+offset tables being sent to the BSD unit through the Slice_State command. + Only when in P Slice with Weighted_Pred_Idc = 1, will there be a L0 weight+offset table being sent + to the BSD. + If Weighted_Pred_Idc != 1 for B Slice or Weighted_Pred_Idc =0 for P Slice, no Slice_State command + should be issued to send these tables. If still being issued, the data is read but ignored. + DXVA specifies Weighted_Bipred and Weighted_Pred in frame-level state. However, these two flags + are combined and specified in slice level for both P and B slice type. + 29 Direct Prediction Type + Type of direct prediction used for B Slices. This field is valid only for Slice_Type = B Slice; otherwise, + it must be set to 0. + Value Name + 0 Temporal + 1 Spatial + 28:27 Disable Deblocking Filter Indicator + Value Name Description + 00b FilterInternalEdgesFlag is set equal to 1 + 01b Disable all deblocking operation, no deblocking parameter syntax element is read; + filterInternalEdgesFlag is set equal to 0 + 10b Macroblocks in different slices are considered not available; filterInternalEdgesFlag + is set equal to 1 + 11b Reserved Not defined in AVC + 26 Reserved + Format: MBZ + 25:24 Cabac Init Idc[1:0] + Specifies the index for determining the initialization table used in the context variable initialization + process. + Value Name + 0-2 + + + Programming Notes + Cabac initialization is also dependent on the field/frame picture type, Slice type, and the current + SliceQP value. + 23:22 Reserved + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 79 + MFX_AVC_SLICE_STATE + Format: MBZ + 21:16 Slice Quantization Parameter + Quantization Parameter for current slice. Derived from PPS and slice_delta_qp syntax element in + Slice Header. + It is needed for CABAC context initialization and deblocking filter control. And it is also used as the + starting QP value in the very first MB of a slice. + It is in the range of unsigned integer 0 to 51, for 8-bit pixel bit-depth. + 15:12 Reserved + Format: MBZ + 11:8 Slice Beta Offset Div2 + Format: S3 2's Complement + + + + + Range: [-6, 6] Inclusive + Specifies the offset used in accessing the deblocking filter strength tables. + 7:4 Reserved + Format: MBZ + 3:0 Slice Alpha C0 Offset Div2 + Format: S3 2's Complement + + + + + Range: [-6, 6] Inclusive + Specifies the offset used in accessing the deblocking filter strength tables. +4 31:24 Slice Vertical Position + This field specifies the position in y-direction of the first macroblock in the Slice in unit of + macroblocks. + The fields (Slice_MB_Start_Hor_Pos, Slice_MB_Start_Vert_Pos) are valid in VLD (decoding) mode + only. They are ignored by hardware in decoding IT mode and encoding mode (whereas the position + is provided by the per-macroblock object command). + Derived + Programming Notes + Error Handling: Driver needs to check if FirstMbY starts at 0 on the first slice of frame. If not, driver + needs to add a phantom slice with FirstMbX and FirstMbY set to 0. + 23:16 Slice Horizontal Position + This field specifies the position in x-direction of the first macroblock in the Slice in unit of + macroblocks. + Derived + Programming Notes + Error Handling: Driver needs to check if FirstMbY starts at 0 on the first slice of frame. If not, driver + needs to add a phantom slice with FirstMbX and FirstMbY set to 0. + 15 Reserved + Format: MBZ + 14:0 Slice Start Mb Num + Exists If: Decoder Only + The MB number (linear MB address in a picture) at the start of a Slice, it must match with the Slice + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 80 + MFX_AVC_SLICE_STATE + Horizontal Position (Slice_MB_Start_Hor_Pos) and Vertical Position (Slice_MB_Start_Vert_Pos) in + the picture. + Programming Notes + In creating the Phantom Slice for error concealment, this field should set to the total number of MB in + the current picture + 1. +5 31:24 Reserved + Format: MBZ + 23:16 Next Slice Vertical Position + This field specifies the position in y-direction of the first macroblock in the next Slice in unit of + macroblocks. + This field is primarily used for error concealment. In the case that current slice is the last slice, this + field should set to the height of picture (since y-direction is zero-based numbering). + 15:8 Reserved + Format: MBZ + 7:0 Next Slice Horizontal Position + This field specifies the position in x-direction of the first macroblock in the next Slice in unit of + macroblocks. + This field is primarily used for error concealment. In the case that current slice is the last slice, this + field should set to 0. +6 31 Rate Control Counter Enable + To enable the accumulation of bit allocation for rate control +Encoder This field enables hardware Rate Control logic. The rest of the RC control fields are only valid when +Only this field is set to 1. Otherwise, hardware ignores these fields. + Value Name + 0 Disable + 1 Enable + 30 ResetRateControlCounter + To reset the bit allocation accumulation counter to 0 to restart the rate control. + Value Name + 0 Not Reset + 1 Reset + 29:28 RC Triggle Mode + Value Name Description + 00b Always Rate Whereas RC becomes active if sum_act > sum_target or sum_act < + Control sum_target + 01b Gentle Rate whereas RC becomes active if sum_act > upper_midpt or sum_act < + Control lower_midpt + 10b Loose Rate Control whereas RC becomes active if sum_act > sum_max or sum_act < + sum_min + 11b Reserved + 27:24 RC Stable Tolerance + Format: U4 + This field specifies the tolerance required to deactivate RC once it has been triggered. + Value Name + 0-15 + 23 RC Panic Enable + If this field is set to 1, RC enters panic mode when sum_act > sum_max. RC Panic Type field + controls what type of panic behavior is invoked. + Value Name + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 81 + MFX_AVC_SLICE_STATE + 0 Disable + 1 Enable + 22 RC Panic Type + This field selects between two RC Panic methods + Value Name + 0 QP Panic + 1 CBP Panic + + + Programming Notes + If it is set to 0, in panic mode, the macroblock QP is maxed out, setting to requested QP + + QP_max_pos_mod. + If it is set to 1, for an intra macroblock, AC CBPs are set to zero (note that DC CBPs are not + modified). + For inter macroblocks, AC and DC CBPs are forced to zero. + 21 MB Type Direct Conversion Disable + Exists If: B-Slice + For all Macroblock type conversions in different slices, refer to Section "Macroblock Type Conversion + Rules" in the same volume. + Value Name + 0 Enable direct mode conversion + 1 Disable direct mode conversion + + + Programming Notes + This field is zero for all other slices other than B-Slice. + 20 MB Type Skip Conversion Disable + Exists If: P-Slice or B-Slice + For all Macroblock type conversions in different slices, refer to Section "Macroblock Type Conversion + Rules" in the same volume. + Value Name + 0 Enable skip type conversion + 1 Disable skip type conversion + + + Programming Notes + This field is zero for all other slices other than P_Slice or B-Slice. \ + 19 Is Last Slice + It is used by the zero filling in the Minimum Frame Size test. + Value Name Description + 1 Current slice is the last slice of a picture + 0 Current slice is NOT the last slice of a picture + 17 Header Insertion Present in Bitstream + Value Name Description + 0 No header insertion into the output bitstream buffer, in front of the current slice encoded + bits. + 1 Header insertion into the output bitstream buffer is present, and is in front of the current + slice encoded bits. + 16 SliceData Insertion Present in Bitstream + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 82 + MFX_AVC_SLICE_STATE + Value Name Description + 0 No Slice Data insertion into the output bitstream buffer + 1 Slice Data insertion into the output bitstream buffer is present. + 15 Tail Insertion Present in bitstream + Value Name Description + 0 No tail insertion into the output bitstream buffer, after the current slice encoded bits + 1 Tail insertion into the output bitstream buffer is present, and is after the current slice + encoded bits. + 14 Reserved + Format: MBZ + 13 EmulationByteSliceInsertEnable + To have PAK outputting SODB or EBSP to the output bitstream buffer + Value Name Description + 0 outputting RBSP + 1 outputting EBSP + 12 CabacZeroWordInsertionEnable + To pad the end of a SliceLayer RBSP to meet the encoded size requirement. + Value Name Description + 0 No Cabac_Zero_Word Insertion + 1 Allow internal Cabac_Zero_Word generation and append to the end of RBSP + (effectively can be used as an indicator for last slice of a picture, if the assumption is + only the last slice of a picture needs to insert CABAC_ZERO_WORDs. + 11:8 Reserved + Format: MBZ + 7:4 Slice ID [3:0] + To identify the output data (coding information record) returned for rate control from PAK to ENC and + VPP. + 3:2 Reserved + Format: MBZ + 1:0 Stream ID [1:0] + To identify the output data (coding information record) returned for rate control from PAK to ENC and + VPP. +7 31:29 Reserved + Format: MBZ +Encoder 28:0 Indirect PAK-BSE Data Start Address (Write) +Only Exists If: AVC Encode Mode + This field specifies the memory starting address (offset) to write out the compressed bitstream data + from the BSE processing. This pointer is relative to the MFC Indirect PAK-BSE Object Base Address. + It is a byte-aligned address for the AVC bitstream data in both CABAC/CAVLC Modes. + For Write, there is no need to have a data length field. It is assumed the global memory bound check + specified in the IND_OBJ_BASE_ADDRESS command (Indirect PAK-BSE Object Access Upper + Bound) will take care of any illegal write access. + Value Name + 0 - 512MB +8 31:24 Magnitude of QP Max Negative Modifier + Format: U8 +Encoder This field specifies the lower limit of the QP modifier. +Only Value Name + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 83 + MFX_AVC_SLICE_STATE + 0-51 + 23:16 Magnitude of QP Max Positive Modifier + Format: U8 + This field specifies the upper limit of the QP modifier. + Value Name + 0 - 15 + 15:12 Shrink Param - Shrink Resistance + Format: U4 + This field specifies the additional points added each time decreased correction is invoked. + Value Name + 0 - 15 + 11:8 Shrink Param – Shrink Init + Format: U4 + This field specifies the initial points required to trip decreased control. + Value Name + 0 - 15 + 7:4 Grow Param – Grow Resistance + Format: U4 + This field specifies the additional points added each time increased correction is invoked. + Value Name + 0 - 15 + 3:0 Grow Param – Grow Init + Format: U4 + This field specifies the initial points required to trip increased control. + Value Name + 0 - 15 +9 31:24 Reserved + Format: MBZ +Encoder 23:20 Correct 6 +Only Format: U4 + This field specifies the points used in the lowermost RC region when sum_act <= sum_min. + Value Name + 0 - 15 + 19:16 Correct 5 + Format: U4 + This field specifies the points used in the fifth RC region when sum_act > sum_min but <= + lower_midpt. + Value Name + 0 - 15 + 15:12 Correct 4 + Format: U4 + This field specifies the points used in the fourth RC region when sum_act > lower_midpt but <= + sum_target. + Value Name + 0 - 15 + 11:8 Correct 3 + Format: U4 + This field specifies the points used in the third RC region when sum_act > sum_target but <= + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 84 + MFX_AVC_SLICE_STATE + upper_midpt. + Value Name + 0 - 15 + 7:4 Correct 2 + Format: U4 + This field specifies the points used in the second RC region when sum_act > upper_midpt but <= + sum_max. + Value Name + 0 - 15 + 3:0 Correct 1 + Format: U4 + This field specifies the points used in the topmost RC region when sum_act > sum_max. + Value Name + 0 - 15 +10 31:28 ClampValues – CV7 + 27:24 CV6 +Encoder + 23:20 CV5 +Only + 19:16 CV4 + 15:12 CV3 + 11:8 CV2 + 7:4 CV1 + 3:0 CV0 - Clamp Value 0 + Format: U4 + + If the magnitude of coefficients at locations assigned with CV0 (mapping shown below) exceeds + 2CV0–1, they are replaced with 2CV0–1. For coefficients at locations marked as ‘none’, no clamping is + performed. The following mappings are only applied to luma and chroma blocks\subblocks + containing AC coefficiencts (blocks\sublocks with only DC coeffs will not be clamped). + + For 4x4 frame block, each coefficient is mapped to one of the eight CV values as following: + none CV7 CV5 CV4 + CV7 CV6 CV4 CV3 + CV5 CV4 CV2 CV1 + CV4 CV3 CV1 CV0 + + For 8x8 frame block, each coefficient is mapped to one of the eight CV values as following: + none none CV7 CV6 CV5 CV4 CV3 CV3 + none CV7 CV6 CV5 CV4 CV3 CV3 CV2 + CV7 CV6 CV5 CV4 CV3 CV3 CV2 CV2 + CV6 CV5 CV4 CV3 CV3 CV2 CV2 CV1 + CV5 CV4 CV3 CV3 CV2 CV2 CV1 CV1 + CV4 CV3 CV3 CV2 CV2 CV1 CV1 CV0 + CV3 CV3 CV2 CV2 CV1 CV1 CV0 CV0 + CV3 CV2 CV2 CV1 CV1 CV0 CV0 CV0 + + For 4x4 field block, each coefficient is mapped to one of the eight CV values as following: + none CV6 CV3 CV1 + CV7 CV6 CV3 CV1 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 85 + MFX_AVC_SLICE_STATE + CV5 CV4 CV2 CV0 + CV5 CV4 CV2 CV0 + + For 8x8 field block, each coefficient is mapped to one of the eight CV values as following: + none none CV6 CV5 CV4 CV3 CV2 CV1 + none CV7 CV6 CV5 CV4 CV3 CV2 CV1 + CV7 CV6 CV5 CV4 CV3 CV3 CV2 CV1 + CV7 CV6 CV5 CV4 CV3 CV2 CV2 CV1 + CV6 CV5 CV4 CV4 CV3 CV2 CV1 CV0 + CV6 CV5 CV4 CV3 CV2 CV2 CV1 CV0 + CV5 CV5 CV4 CV3 CV2 CV1 CV1 CV0 + CV5 CV5 CV4 CV3 CV2 CV1 CV1 CV0 + + + Value Name + 0 - 15 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 86 + 2.1.4 MFX_AVC_REF_IDX_STATE Command + + MFX_AVC_REF_IDX_STATE + +Source: VideoCS +Length Bias: 2 +This is a slice level command and can be issued multiple times within a picture that is comprised of multiple slices. +The same command is used for AVC encoder (PAK mode) and decoder (VLD mode); it is not need in decoder IT +mode. + +The inline data of this command is interpreted differently for encoder as for decoder. For decoder, it is interpreted as +RefIdx List L0/L1 as in AVC spec., and it matches with the DXVA2 AVC API data structure for decoder in VLD mode : +RefPicList[2][32] (L0:L1, 0:31 RefPic). But for encoder, it is interpreted as a Reference Index Mapping Table for L0 +and L1 reference pictures. For packing the bits at the output of PAK, the syntax elements must follow the definition of +RefIdxL0/L1 list according to the AVC spec. However, the decoder pipeline was designed to use a variation of that +standard definition, as such a conversion (mapping) is needed to support the hardware design. + +The Reference lists are needed in processing both P and B slice in AVC codec. For P-MB, only L0 list is used; for B- +MB both L0 and L1 lists are needed. For a B-MB that is coded in L1-only Prediction, only L1 list is used. + Programming Notes +DXVA2 specifies that an application will create the RefPicList L0 and L1 and pass onto the driver. The content of +each entry of RefPicList L0/L1[ ] is a 7-bit picture index. This picture index is the same as that of RefFrameList[ ] +content. This picture index, however, is not defined the same as the frame store ID (0 to 16, 5-bits) we have +implemented in H/W. Hence, driver is required to manage a table to convert between DXVA2 picture index and intel +frame store ID. As such, the final RefPicList L0/L1[ ] that the driver passes onto the H/W is not the same as that +defined in the DXVA2. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_AVC_REF_IDX_STATE + Format: OpCode + 26:24 Command Opcode + Default Value: 1h AVC + Format: OpCode + 23:21 SubOpcodeA + Default Value: 0h MFX_AVC_REF_IDX_STATE + Format: OpCode + 20:16 SubOpcodeB + Default Value: 4h MFX_AVC_REF_IDX_STATE + Format: OpCode + 15:12 Reserved + Format: MBZ + 11:0 DWord Length + Default Value: 0008h + Excludes DWords 0,1 + +1 31:1 Reserved + Format: MBZ + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 87 + MFX_AVC_REF_IDX_STATE + 0 RefPicList Select + + Num_ref_idx_l1_active is resulted from the specifications in both PPS and Slice Header for the + current slice. However, since the full reference list L0 and/or L1 are always sent, only present flags + are specified instead. + + This parameter is specified for Intel interface only, not present in the DXVA. + Value Name Description + 0 RefPicList The list that followed represents RefList L0 (Decoder VLD mode) or Ref Idx + 0 Mapping Table L0 (Encoder PAK mode) + 1 RefPicList1 The list that followed represents RefList L1 (Decoder VLD mode) or Ref Idx + Mapping Table L1 (Encoder PAK mode) +2..9 31:0 Reference List Entry + This set of fields is always present whenever this command is issued. + + + It always specifies the full 32 reference pictures in the selected list, regardless they are “existing + picture” or not. If a picture is non-existing, the corresponding entry should be set to all ones. + Each list entry is 1 byte. A 32-bit DW can hold 4 list entries in the following format + + + + 31:24 entry X+3 (e.g. listY_3) + + + 23:16 entry X+2 (e.g. listY_2) + + + 15:8 entry X+1 (e.g. listY_1) + + + 7:0 entry X (e.g. listY_0) + + + + + X is replaced by the paddr[2:0] * 4 ; paddr[5:0] with 0x20 and 0x27, and Y is replaced by 0 or 1. + The byte definition for a reference picture : + + + + Bit 7 : Non-Existing – indicates that frame store index that should have been at this entry did not + exist and was replaced by an index 0 (a valid entry) for error concealment + + + Bit 6 : Long term bit – set this reference picture to be used as long term reference + + + Bit 5 : Field picture flag – indicates frame/field + + + Bit 4:0 : Frame store index or Frame Store ID (Bit 4:1 is used to form the binding table index in intel + implementation) + + + This is the final Reference List L0 or L1 after any reordering specified in the Slice Header as well as + modified by the driver, and its indices values are all translated to the intel specification. + If the reference picture is a frame (Bit5 = 1), frame store ID is always an even number. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 88 + MFX_AVC_REF_IDX_STATE + This list is used in outputting MV information by the BSD unit in VLD mode. DMV access also reads + and writes Mvlist0 using this frame store ID. + If this set of fields is interpreted as Reference Index Mapping Table L0/L1, the same field alignment is + followed, i.e. 4 mapping entries per DW. Each mapping entry is one byte in size, but only the least + significant 5 bits [4:0] is relevant. Driver should zero all the upper bits [7:5] for each entry. + + + + +2.1.5 MFX_AVC_WEIGHTOFFSET_STATE Command + + MFX_AVC_WEIGHTOFFSET_STATE + +Source: VideoCS +Length Bias: 2 +This is a slice level command and can be issued multiple times within a picture that is comprised of multiple slices. +The same command is used for AVC encoder (PAK mode) and decoder (VLD and IT modes). However, since for +AVC decoder VLD and IT modes, and AVC encoder mode, the implicit weights are computed in hardware, this +command is not issued. For encoder, regardless of the type of weight calculation is active for the current slice +(default, implicit or explicit), they are all sent to the PAK as if they were all in explicit mode. However, for implicit +weight and offset, each entry contains only a 16-bit weight and no offset (offset = 0 always in implicit mode and can +be hard-coded inside the hardware).The weights (and offsets) are needed in processing both P and B slice in AVC +codec. For P-MB, at most only L0 list is used; for B-MB both L0 and L1 lists may be needed. For a B-MB that is +coded in L1-only Prediction, only L1 list is sent.The content of this command matches with the DXVA2 AVC API data +structure for explicit prediction mode only : Weights[2][32][3][2] (L0:L1, 0:31 RefPic, Y:Cb:Cr, W:0) +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_ AVC_ WEIGHTOFFSET_STATE + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h AVC_COMMON + Format: OpCode + 23:21 SubOpcode A + Default Value: 0h + Format: OpCode + 20:16 SubOpcode B + Default Value: 5h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 0h Excludes DWord (0,1) = 0030h + Project: All + Format: =n Total Length - 2 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 89 + MFX_AVC_WEIGHTOFFSET_STATE + + +1 31:1 Reserved + Project: All + Format: MBZ + 0 Weight and Offset Select + It must be set in consistent with the WeightedPredFlag and WeightedBiPredIdc in the Img_State + command. + This parameter is specified for Intel interface only, not present in the DXVA. + For implicit even though only one entry may be used, still loading the whole 32-entry table. + Value Name Description Project + 0 Weight and Offset L0 The list that followed is associated with the weight and offset for All + table RefPicList L0 + 1 Weight and Offset L1 The list that followed is associated with the weight and offset for All + table RefPicList L1 +2..97 31:0 WeightOffset + WeightOffset[L=L0=0 or L1=1][i=0 to 31][Y=0/Cb=1/Cr=2][weight=0/offset=1] + WeightOffset[L][ i=0][Y=0][Weight=0], WeightOffset[L][i=0][Y=0][Offset=1] + WeightOffset[L][ i=0][Cb=1][Weight=0], WeightOffset[L][ i=0][Cb=1][Offset=1] + WeightOffset[L][ i=0][Cr=2][Weight=0], WeightOffset[L][ i=0][Cr=2][Offset=1]: + WeightOffset[L][ i=31][Y=0][Weight=0], WeightOffset[L][ i=31][Y=0][Offset=1] + WeightOffset[L][ i=31][Cb=1][Weight=0], WeightOffset[L][ i=31][Cb=1][Offset=1] + WeightOffset[L][ i=31][Cr=2][Weight=0], WeightOffset[L][ i=31][Cr=2][Offset=1] + Format for explicit: Both Weight and Offset are S15 in two’s compliment, with a valid range from -128 + to 128 + Format for implicit: S15 + This set of fields is always present whenever this command is issued. The full table, one entry for each + reference picture, is always specified. Any reference list L0/L1[i] that does not exist, the corresponding + weight and offset are set to 0. + + Weight and Offset are 2 byte each. Apair of Weight and Offset forms a dword, with Weight in the + LOWER word and Offset in the HIGHER word. + + WeightOffset[L0=0][i=0 to 31][Y=0] (i.e. luma_weight_l0[ i ]) are specified for the weighting and offset + factors applied to the luma prediction value for list 0 prediction using RefPicList0[ i ] (one-to-one + correspondence in i). When luma_weight_l0_flag (Slice Header syntax element) is equal to 1, the + value of luma_weight_l0[ i ] shall be in the range of –128 to 127. When luma_weight_l0_flag is equal to + 0, luma_weight_l0[ i ] shall be inferred to be equal to 2luma_log2_weight_denom for RefPicList0[ i ]. + luma_log2_weight_denom is a Slice Header syntax element. + + WeightOffset[L0=0][i=0 to 31][Cb=1] (i.e. chromaCb_weight_l0[ i ]) are specified for the weighting and + offset factors applied to the chroma Cb prediction values for list 0 prediction using RefPicList0[ i ] (one- + to-one correspondence in i). When chroma_weight_l0_flag (Slice Header syntax element) is equal to 1, + the value of chromaCb_weight_l0[ i ] shall be in the range of –128 to 127. When + chroma_weight_l0_flag is equal to 0, chromaCb_weight_l0[ i ] shall be inferred to be equal to + 2chroma_log2_weight_denom for RefPicList0[ i ]. chroma_log2_weight_denom is a Slice Header + syntax element. + + WeightOffset[L0=0][i=0 to 31][Cr=2] (i.e. chromaCr_weight_l0[ i ]) are specified for the weighting and + offset factors applied to the chroma Cr prediction values for list 0 prediction using RefPicList0[ i ] (one- + to-one correspondence in i). When chroma_weight_l0_flag (Slice Header syntax element) is equal to 1, + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 90 + MFX_AVC_WEIGHTOFFSET_STATE + the value of chromaCr_weight_l0[ i ] shall be in the range of –128 to 127. When + chroma_weight_l0_flag is equal to 0, chromaCr_weight_l0[ i ] shall be inferred to be equal to + 2chroma_log2_weight_denom for RefPicList0[ i ]. + + + + +2.2 AVC Decoder Commands + +2.2.1 MFD_AVC_DPB_STATE Command + + MFD_AVC_DPB_STATE +Project: All +Source: VideoCS +Length Bias: 2 +This is a frame level state command used only in DXVA2 AVC Short Slice Bitstream Format VLD mode. + RefFrameList[16] of DXVA2 interface is replaced with intel Reference Picture Addresses[16] of +MFX_PIPE_BUF_ADDR_STATE command. The LongTerm Picture flag indicator of all reference pictures are +collected into LongTermPic_Flag[16]. + FieldOrderCntList[16][2] and CurrFieldOrderCnt[2] of DXVA2 interface are replaced with intel POCList[34] of +MFX_AVC_DIRECTMODE_STATE command. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_MULTI_DW + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h AVC_DEC + Format: OpCode + 23:21 SubOpcode A + Default Value: 1h + Format: OpCode + 20:16 SubOpcode B + Default Value: 6h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 0h Excludes DWord (0,1) =0009h + Project: All + Format: =n Total Length - 2 + + + +1 31:16 LongTermFrame_Flag[16][1 bit] + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 91 + MFD_AVC_DPB_STATE + One-to-one correspondence with the entries of the Intel RefFrameList[16]. 1 bit per reference frame. + Value Name Project + 1 the picture is a long term reference picture + 0 the picture is a short term reference picture + 15:0 Non-ExistingFrame_Flag[16][1 bit] + One-to-one correspondence with the entries of the Intel RefFrameList[16]. 1 bit per reference frame. + Value Name Project + 1 the reference picture in that entry of RefFrameList[] does not exist anymore. + 0 the reference picture in that entry of RefFrameList[] is a valid reference + + + Programming Notes + When an element of the list of frames is not relevant (e.g., due to the corresponding reference entry + being empty or being marked as "not used for reference"), the value of the corresponding bit of + NonExistingFrameFlags shall be set to 0. +2 31:0 UsedForReference_Flag[16][2 bits] + One-to-one correspondence with the entries of the Intel RefFrameList[16]. 2 bits per reference frame. + Value Name + 0 indicates a frame is “not used for reference”. + 1 bit[0] indicates that the top field of a frame is marked as "used for reference". + 2 bit[1] indicates that the bottom field of a frame is marked as "used for reference". + 3 bit[1:0] indicates that a frame (or field pair) is marked as “used for reference”. +3..10 31:0 LTSTFrameNumList[16][16 bits] + + One-to-one correspondence with the entries of the Intel RefFrameList[16]. 16 bits per reference + frame.Depending on the corresponding LongTermFrame_Flag[], the content of this field is interpreted + differently. + Value Name Description + 1 LongTermFrame_Flag[i] LTSTFrameNumList[i] represent LongTermFrameIdx. + 0 LongTermFrame_Flag[i] LTSTFrameNumList[i]represent Short Term Picture + FrameNum. + + + Programming Notes + When an element of the list of frames is not relevant (e.g., due to the corresponding reference entry + being empty or being marked as "not used for reference"), the value of the LTSTFrameNumList entry + shall be set to 0. + + + +NOTE modified from DXVA2 – The values in RefFrameList and UsedForReference_Flag are the primary +means by which the H/W can determine whether the corresponding entries in RefFrameList, POCList, +LTSTFrameNumList, and Non-ExistingFrame_Flag should be considered valid for use in the decoding +process of the current picture or not. When RefFrameList[i] is marked to be invalid, the values of +POCList[i][0], POCList[i][1], LTSTFrameNumList[i], UsedForReference_Flag[i], and Non- +ExistingFrame_Flag[i] must all be equal to 0. When UsedForReference_Flag[i] = 0, the value of +RefFrameList[i] must be marked invalid. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 92 + 2.2.2 MFD_AVC_SLICEADDR Command + + MFD_AVC_SLICEADDR +Project: All +Source: VideoCS +Length Bias: 2 +This is a Slice level command used only for DXVA2 AVC Short Slice Bitstream Format VLD mode.When decoding a +slice, H/W needs to know the last MB of the slice has reached in order to start decoding the next slice. It also needs +to know if a slice is terminated but the last MB has not reached, error conealment should be invoked to generate +those missing MBs. For AVC DXVA2 Short Format, the only way to know the last MB position of the current slice, +H/W needs to snoop into the next slice’s start MB address (a linear address encoded in the Slice Header). Since +each BSD Object command can have only one indirect bitstream buffer address, this command is added to help H/W +to snoop into the next slice’s slice header and retrieve its Start MB Address. This command will take the next slice’s +bitstream buffer address as input (exactly the same way as a BSD Object command), and parse only the +first_mb_in_slice syntax element. The result will stored inside the H/W, and will be used to decode the current slice +specified in the BSD Object command.Only the very first few bytes (max 5 bytes for a max 4K picture) of the Slice +Header will be decoded, the rest of the bitstream are don’t care. This is because the first_mb_in_slice is encoded in +Exponential Golomb, and will take 33 bits to represent the max 256 x 256 = 64K-1 value. The indirect data of +MFD_AVC_SLICEADDR is a valid BSD object and is decoded as in BSD OBJECT command.The next Slice Start +MB Address is also exposed to the MMIO interface.The Slice Start MB Address (first_mb_in_slice) is a linear MB +address count; but it is translated into the corresponding 2D MB X and Y raster position, and are stored internally as +NextSliceMbY and NextSliceMbX. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFD_AVC_ SLICEADDR + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h AVC_DEC + Format: OpCode + 23:21 SubOpcode A + Default Value: 1h + Format: OpCode + 20:16 SubOpcode B + Default Value: 7h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 0h Excludes DWord (0,1) =0001h + Project: All + Format: =n Total Length - 2 + + + +1 31:24 Reserved + Project: All + Format: MBZ + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 93 + MFD_AVC_SLICEADDR + 23:0 Indirect BSD Data Length + + Format: U24 in bytes + + + This field provides the length in bytes of the indirect data. A value zero indicates that indirect data + fetching is disabled – subsequently, the Indirect Data Start Address field is ignored. Driver always + programs this up to 5 bytes; for bitstream less than 5 bytes, driver program the lesser value. (Emulation + Prevention Byte should never happen for the first 5 bytes when the max picture size can only be + 4Kx4K)It is the length in bytes of the bitstream data for the current slice, including Slice Header + Slice + Data + Emulation Prevention Bytes + any filling trailing zeros after the last MB. Hardware ignores the + contents after the last non-zero byte. Trailing zero is allowed and handled correctly in both CABAC and + CAVLC modes. + +2 31:29 Reserved + Project: All + Format: MBZ + 28:0 Indirect BSD Data Start Address + + This field specifies the Graphics Memory starting address of the data to be fetched into BSD Unit for + processing. This pointer is relative to the MFD Indirect Object Base Address.Hardware ignores this field + if indirect data is not present. It is a byte-aligned address for the AVC bitstream data in both + CABAC/CAVLD Modes.In implementing a phantom slice at the end of a picture for automatic error + concealment, this field should set to 0.It includes the NAL Header Byte. (but does not perform EMU + detection).Must provide a valid MB address, even if error. MB must be clamped to within a pic + boundary. + Value Name + [0,512MB) + + + + +2.2.3 MFD_AVC_BSD_OBJECT Command + + MFD_AVC_BSD_OBJECT + +Source: VideoCS +Length Bias: 2 +The MFD_AVC_BSD_OBJECT command is the only primitive command for the AVC Decoding Pipeline. The same +command is used for both CABAC and CAVLD modes. + The Slice Data portion of the bitstream is loaded as indirect data object.Before issuing a MFD_AVC_BSD_OBJECT +command, all AVC states of the MFD Engine need to be valid. Therefore the commands used to set these states +need to have been issued prior to the issue of a MFD_AVC_BSD_OBJECT command.Context switch interrupt is not +supported by this command. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFD_AVC_BSD_OBJECT + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 94 + MFD_AVC_BSD_OBJECT + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h AVC_DEC + Format: OpCode + 23:21 SubOpcode A + Default Value: 1h + Format: OpCode + 20:16 SubOpcode B + Default Value: 8h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 0h Excludes DWord (0,1) = 0004 + Project: All + Format: =n Total Length - 2 + + + +1 31:24 Reserved + Format: MBZ + 23:0 Indirect BSD Data Length + Format: U24 + This field provides the length in bytes of the indirect data. A value zero indicates that indirect data + fetching is disabled – subsequently, the Indirect Data Start Address field is ignored. + This field must have the same alignment as the Indirect Object Data Start Address. + AVC Short Format : It is the length in bytes of the bitstream data for the current slice, including Slice + Header + Slice Data + Emulation Prevention Bytes + any filling trailing zeros after the last MB. + Hardware ignores the contents after the last non-zero byte. Trailing zero is allowed and handled + correctly in both CABAC and CAVLC modes. + +2 31:29 Reserved + Project: All + Format: MBZ + 28:0 Indirect BSD Data Start Address + Project: All + Format: U29 + This field specifies the Graphics Memory starting address of the data to be fetched into BSD Unit for + processing. This pointer is relative to the MFD Indirect Object Base Address. + Hardware ignores this field if indirect data is not present. + It is a byte-aligned address for the AVC bitstream data in both CABAC/CAVLD Modes. + In implementing a phantom slice at the end of a picture for automatic error concealment, this field + should set to 0. + It includes the NAL Header (the NAL Header does not need to perform EMU detection). For AVC + Base Layer, it is a single byte. But for MVC, the NAL Header is 4 Bytes long. These NAL Header Unit + must be passed to HW in the compressed bitstream buffer. + Value Name + [0,512MB) +3..5 31:0 Inline Data + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 95 + MFD_AVC_BSD_OBJECT + All the required Slice Header parameters and error handling settings are captured as InLine Data of + the AVC_BSD_OBJECT command. It has a fixed size of 4 DWs. Its definition is described in the + follwoing section: Inline Data Description. + + + +2.2.3.1 Inline Data Description + + Inline Data Description + +Source: VideoCS +Default Value: 0x00000000, 0x00000000 +This structure includes all the required Slice Header parameters and error handling settings for AVC_BSD_OBJECT +command. +DWord Bit Description +3 31 Concealment Method + This field specifies the method used for concealment when error is detected. If set, a copy from + collocated macroblock location is performed from the concealment reference indicated by the + ConCeal_Pic_Id field. If it is not set, a copy from the current picture is performed using Intra 16x16 + Prediction method. + Value Name Description + 0 Intra 16x16 Prediction + 1 Inter P Copy + 30 Init Current MB Number + When set, the current Slice_Start_MB_Num, Slice_MB_Start_Hor_Pos and Slice_MB_Start_Vert_Pos + fields will be used to initialize the Current_MB_Number register. + This effectively disables the concealment capability. + 29 Reserved + + Format: MBZ + 28:27 MB Error Concealment B Temporal Prediction mode + These two bits control how the reference L0/L1 are overridden in B temporal slice. + Value Name Description + 00b [Default] Both Reference Indexes L0/L1 are forced to 0 during Concealment + 01b Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 + 10b Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 + 11b Reserved Invalid + 26 MB Error Concealment B Temporal Reference Index Override Enable Flag + + During MB Error Concealment on B slice with Temporal Direct Prediction, either L0 or L1 or both can be + forced to 0 (MB Error Concealment B Temporal Reference Index Override Mode from above will control + which one) + This bit can be set to use the predicted reference indexes instead. + Value Name Description + 0 [Default] Predicted Reference Indexes L0/L1 are used during MB Concealment. + 1 Reference Indexes L0/L1 are overridden to 0 during MB Concealment. + 25 MB Error Concealment B Temporal Motion Vectors Override Enable Flag + During MB Error Concealment on B slice with Temporal Direct Prediction, motion vectors are forced to + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 96 + Inline Data Description + 0 to improve image quality. + This bit can be set to preserve the original weight prediction. + Value Name Description + 0 [Default] Predicted Motion Vectors are used during MB Concealment + 1 Motion Vectors are Overridden to 0 during MB Concealment + 24 MB Error Concealment B Temporal Weight Prediction Disable Flag + During MB Error Concealment on B slice with Temporal Direct Prediction, weight prediction is disabled + to improve image quality. + This bit can be set to preserve the original weight prediction. + Value Name Description + 0 [Default] Weight Prediction is Disabled during MB Concealment + 1 Weight Prediction will not be overridden during MB Concealment + 23:22 Reserved + Format: MBZ + 21:16 Concealment Picture ID + This field identifies the picture in the reference list to be used for concealment. This field is only valid if + Concealment Method is Inter P Copy. + Bit Filed Value Defenition + 21 0 Frame Picture + 21 1 Field picture + 20:16 All Frame Store Index[4:0] + 15 Reserved + Format: MBZ + 14 BSD Premature Complete Error Handling + BSD Premature Complete Error occurs in situation where the Slice decode is completed but there are + still data in the bitstream. + Value Name Description + 1 Set the interrupt to the driver (provide MMIO registers for MB address R/W) + 0 Ignore the error and continue (masked the interrupt), assume the hardware automatically + performs the error handling + 13 Reserved + Format: MBZ + 12 MPR Error (MV out of range) Handling + Software must follow the action for each Value as follow: + Value Name Description + 1 Set the interrupt to the driver (provide MMIO registers for MB address R/W) + 0 Ignore the error and continue (masked the interrupt), assume the hardware automatically + performs the error handling + 11 Reserved + Format: MBZ + 10 Entropy Error Handling + Software must follow the action for each Value as follow: + Value Name Description + 1 Set the interrupt to the driver (provide MMIO registers for MB address R/W). + 0 Ignore the error and continue (masked the interrupt), assume the hardware automatically + perform the error handling. + 9 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 97 + Inline Data Description + 8 MB Header Error Handling + Software must follow the action for each Value as follow: + Value Name Description + 1 Set the interrupt to the driver (provide MMIO registers for MB address R/W). + 0 Ignore the error and continue (masked the interrupt), assume the hardware automatically + perform the error concealment. + 7:6 MB Error Concealment B Spatial Prediction mode + These two bits control how the reference L0/L1 are overridden in B spatial slice. + Value Name Description + 00b [Default] Both Reference Indexes L0/L1 are forced to 0 during Concealment + 01b Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 + 10b Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 + 11b Reserved Invalid + 5 MB Error Concealment B Spatial Reference Index Override Disable Flag + + During MB Error Concealment on B slice with Spatial Direct Prediction, either L0 or L1 or both can be + forced to 0 (MB Error Concealment B Spatial Reference Index Override Mode from above will control + which one) + This bit can be set to use the predicted reference indexes instead. + Value Name Description + 0 [Default] Reference Indexes L0/L1 are overridden during MB Concealment + 1 Predicted Reference Indexes L0/L1 are used during MB Concealment + 4 MB Error Concealment B Spatial Motion Vectors Override Disable Flag + During MB Error Concealment on B slice with Spatial Direct Prediction, motion vectors are forced to 0 + to improve image quality. + This bit can be set to use the predicted motion vectors instead. + This bit does not affect normal decoded MB. + Value Name Description + 0 [Default] Motion Vectors are Overridden to 0 during MB Concealment + 1 Predicted Motion Vectors are used during MB Concealment + 3 MB Error Concealment B Spatial Weight Prediction Disable Flag + During MB Error Concealment on B slice with Spatial Direct Prediction, weight prediction is disabled to + improve image quality. + This bit can be set to preserve the original weight prediction. + This bit does not affect normal decoded MB. + Value Name Description + 0 [Default] Weight Prediction is Disabled during MB Concealment. + 1 Weight Prediction will not be overridden during MB Concealment. + 2 MB Error Concealment P Slice Reference Index Override Disable Flag + + During MB Error Concealment on P slice reference index L0 is forced to 0. + This bit can be set to use the predicted reference indexes instead. + This bit does not affect normal decoded MB. + Value Name Description + 0 [Default] Reference Indexes L0 are force to 0 + 1 Predicted Reference Indexes L0 are used during MB Concealment. + 1 MB Error Concealment P Slice Motion Vectors Override Disable Flag + During MB Error Concealment on P slice, motion vectors are forced to 0 to improve image quality. + This bit can be set to use the predicted motion vectors instead. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 98 + Inline Data Description + This bit does not affect normal decoded MB. + Value Name Description + 0 [Default] Motion Vectors are Overridden to 0 during MB Concealment + 1 Predicted Motion Vectors are used during MB Concealment + 0 MB Error Concealment P Slice Weight Prediction Disable Flag + During MB Error Concealment on P slice, weight prediction is disabled to improve image quality. + This bit can be set to preserve the original weight prediction. + This bit does not affect normal decoded MB. + Value Name Description + 0 [Default] Weight Prediction is Disabled during MB Concealment. + 1 Weight Prediction will not be overridden during MB Concealment. +4 31:16 First MB Byte Offset of Slice Data or Slice Header + Description Project + Long Format:It gives the byte offset to locate the Slice Header in the bitstream for a slice, + provided by the Indirect BSD Data Start Address. + It does not include any Emulation Byte count present in the Slice Header. HW will take care of + the Emulation Byte adjustment to this offset. + Short Format: it should be programmed to be 0. HW will parse the Slice Header. + + + Programming Notes Project + MFX supports only DXVA2 Long and Short Format. + 15:8 Reserved + Format: MBZ + 7 Fix Prev Mb Skipped + Enables an alternative method for decoding mb_skipped, to cope with an encoder that codes a skipped + MB as a direct MB with no coefficient. + 6:5 Reserved + Format: MBZ + + + Programming Notes + Please note that the field MUST be set to '0' at this time. + 4 Emulation Prevention Byte Present + Value Name Description + 0 H/W needs to perform Emulation Byte Removal + 1 H/W does not need to perform Emulation Byte Removal + 3 LastSlice Flag + It is needed for both error concealment at the end of a picture. It is also needed to know to set the last + MB in a picture correctly. + Value Name Description + 1 If the current Slice to be decoded is the very last slice of the current picture. + 0 If the current Slice to be decoded is any slice other than the very last slice of the current + picture + 2:0 First Macroblock (MB)Bit Offset + Exists If: AVC Long Format Only + Format: U3 + This field provides the bit offset of the first macroblock of the Slice in the first byte of the input + compressed bitstream. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 99 + Inline Data Description + + + +2.3 AVC Encoder PAK Commands +Each PAK Commands is composed of a command op-code DW and one or more command data DWs +(inline data). The size of each command is specified as part of the op-code DW. Most of the commands +have fixed size, except some are allowed to be of variable length. +There is an inherent order of executing MFC PAK commands that driver must follow. + + +2.3.1 MFC_AVC_PAK_OBJECT Command + + MFC_AVC_PAK_OBJECT + +Source: VideoCS +Length Bias: 2 +The MFC_AVC_PAK_OBJECT command is the second primitive command for the AVC Encoding Pipeline. The +same command is used for both CABAC and CAVLC modes. The MV Data portion of the bitstream is loaded as +indirect data object.Before issuing a MFC_AVC_PAK_OBJECT command, all AVC MFX states need to be valid. +Therefore the commands used to set these states need to have been issued prior to the issue of this command.MB +record must be consecutive with no gaps, hence we do not need MB(x,y) in each MB command. Internal counter will +keep track of the current MB address, starting from the Start_MB_In_Slice loaded at the beginning of each slice. +MFC_AVC_PAK_OBJECT command follows the MbType definition like MFD. Many fields in this command are +identical to that in VME output. This is intended to reduce software converting overhead from VME to PAK. Encoding +statistical data such as the total size of the output bitstream are provided through MMIO registers. Software may +access these registers through MI_STORE_REGISTER_MEM command. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFC_AVC_PAK_OBJECT + Format: OpCode + 26:24 Media Command Opcode + Default Value: 1h AVC_ENC + Format: OpCode + 23:21 SubOpcode A + Default Value: 2h + Format: OpCode + 20:16 SubOpcode B + Default Value: 9h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 100 + MFC_AVC_PAK_OBJECT + 11:0 DWord Length + Default Value: 000Ah DWORD_COUNT_n + Project: All + Format: =n Length -2 + + + +1 31:10 Reserved + Project: All + Format: MBZ + 9:0 Indirect PAK-MV Data Length + Format: U10 + This field provides the length in bytes of the indirect data, which contains all the MVs for the current MB + (in any partitioning and subpartitioning form). A value zero indicates that indirect data fetching is + disabled – subsequently, the Indirect PAK-MV Data Start Address field is ignored. This field must have + the same alignment as the Indirect PAK-MV Data Start Address. This field must be DW aligned (since + each MV is 4 bytes in size).Driver has to derived this field from MVsize (MVquantity in DXVA, exact + size) *4 bytes per MV. + +2 31:29 Reserved + Format: MBZ + 28:0 Indirect PAK-MV Data Start Address Offset. + This field specifies the memory starting address (offset) of the MV data to be fetched into PAK + Subsystem for processing. This pointer is relative to the MFC Indirect PAK-MV Object Base + Address.Hardware ignores this field if indirect data is not present, i.e. the Indirect PAK-MV Data Length + is set to 0. It is a Dword aligned address in all AVC encoding configuration, since each MV is 4 bytes in + size. + Value Name + [0,512MB) +3..10 31:0 Inline Data + All the required MB level controls and parameters for encoding are captured as inline data of the + MFC_AVC_PAK_OBJECT command. It has a fixed size of 8 DWs. Its definition is described in the next + section. + + + +2.3.1.1 PAK Object Inline Data Description +The Inline Data includes all the required MB encoding states, constitute part of the Slice Data syntax +elements, MB Header syntax elements and their derivatives. It provides information for the following +operations: + 1. Forward and Inverse Transform + 2. Forward and Inverse Quantization + 3. Advanced Rate Control (QRC) + 4. MB Parameter Construction (MPC) + 5. CABAC/CAVLC encoding + 6. Bit stream packing + 7. Intra and inter-Prediction decoding loop + 8. Internal error handling + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 101 + These state/parameter values may subject to change on a per-MB basis, and must be provided in each +MFC_AVC_PAK_OBJECT command. The values set for these variables are retained internally, until they +are reset by hardware Asynchronous Reset or changed by the next MFC_AVC_PAK_OBJECT command. +The inline data has been designed to match the DXVA 2.0, with the exception of the starting byte +(DW0:0-7) and the ending dword (DW7:0-31). +The Deblocker Filter Control flags (FilterInternalEdgesFlag, FilterTopMbEdgeFlag and +FilterLeftMbEdgesFlag) are generated by H/W, which are depending on MbaffFrameFlag, CurrMbAddr, +PicWidthInMbs and disable_deblocking_filter_idc states. +Current MB [x,y] address is not sent, it is assumed that the H/W will keep track of the MB count and +current MB position internally. +DWord Bit Description +3 31 + ExtendedForm + This field specifies that LumaIntraMode and RefPicSelect are fully replicated in 4x4 and + 8x8 sub-blocks respectively. This non-DXVA form is used for optimal kernel performance. + + 30:24 Reserved: MBZ + + 23 Reserved : MBZ + + + 22:20 + MvFormat (Motion Vector Size). This field specifies the size and format of the output + motion vectors. + This field is reserved (MBZ) when the IntraMbFlag = 1. + The valid encodings are: + 000 = 0: No motion vector + 100 = 8MV: Four 8x8 motion vector pairs + 110 = 32MV: 16 4x4 motion vector pairs + Others are reserved. + (The following encodings are intended for future usages: + 001 = 1MV: one 16x16 motion vector + 010 = 2MV: One 16x16 motion vector pair + 011 = 4MV: Four 8x8 motion vectors + 101 = 16MV: 16 4x4 motion vectors + 111 = Packed, number of MVs is given by PackedMvNum.) + Note: + This field is fully supported for 100 (8MV) and 110 (32MV) + 19 + CbpDcY. This field specifies if the Luma DC sub-block is coded. Setting it to 0 will force PAK + to zero out the Luma sub-block. Otherwise, whether the sub-block is coded will be + determined by the quantization process. + 1 – the 4x4 DC-only Luma sub-block of the Intra16x16 coded MB is present; it is still possible + that all DC coefficients are zero. + 0 – no 4x4 DC-only Luma sub-block is present; either not in Intra16x16 MB mode or all DC + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 102 + DWord Bit Description + coefficients are zero. + Programming Note: when Reference Mb: IPCM or inferred IPCM, current mb: base mode + flag = 1; all bits in CbpDcY, CbpDcU, CbpDcV, Cbp4x4Y[15:0], Cbp4x4V[15:0] and + Cbp4x4U[15:0] must set to 1’s. + 18 + CbpDcU. This field specifies if the Chroma Cb DC sub-block is coded. Setting it to 0 will + force PAK to zero out the Luma sub-block. Otherwise, whether the sub-block is coded will be + determined by the quantization process. + 1 – the 2x2 DC-only Chroma Cb sub-block of all coded MB (any type) is present; it is still + possible that all DC coefficients are zero. + 0 – no 2x2 DC-only Chroma Cb sub-block is present; all DC coefficients are zero. + Programming Note: when Reference Mb: IPCM or inferred IPCM, current mb: base mode + flag = 1; all bits in CbpDcY, CbpDcU, CbpDcV, Cbp4x4Y[15:0], Cbp4x4V[15:0] and + Cbp4x4U[15:0] must set to 1’s. + 17 + CbpDcV. This field specifies if the Chroma Cb DC sub-block is coded. Setting it to 0 will + force PAK to zero out the Luma sub-block. Otherwise, whether the sub-block is coded will be + determined by the quantization process. + 1 – the 2x2 DC-only Chroma Cr sub-block of all coded MB (any type) is present; it is still + possible that all DC coefficients are zero. + 0 – no 2x2 DC-only Chroma Cr sub-block is present; all DC coefficients are zero. + Programming Note: when Reference Mb: IPCM or inferred IPCM, current mb: base mode + flag = 1; all bits in CbpDcY, CbpDcU, CbpDcV, Cbp4x4Y[15:0], Cbp4x4V[15:0] and + Cbp4x4U[15:0] must set to 1’s. + + 16 Reserved: MBZ + (reserved for future use as ExternalResidBufFlag for turbo mode) + + 15 + Transform8x8Flag + This field indicates that 8x8 transform is used for the macroblock. + When it is set to 0, the current MB uses 4x4 transform. When it is set to 1, the current MB + uses 8x8 transform. The transform_size_8x8_flag syntax element, if present in the output + bitstream, is the same as this field. However, whether transform_szie_8x8_flag is present or + not in the output bitstream depends on several other conditions. + This field is only allowed to be set to 1 for two conditions: + It must be 1 if IntraMbFlag = INTRA and IntraMbMode = INTRA_8x8 + It may be 1 if IntraMbFlag = INTER and there is no sub partition size less than 8x8 + + Otherwise, this field must be set to 0. + 0: 4x4 integer transform + 1: 8x8 integer transform + 14 + FieldMbFlag + This field specifies the field polarity of the current macroblock, as the mb_field_decoding_flag + syntax element in AVC spec. + This field specifies whether current macroblock is coded as a field or frame macroblock in + MBAFF mode. It is exactly the same as FIELD_PIC_FLAG syntax element in non-MBAFF + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 103 + DWord Bit Description + mode. + 0 = Frame macroblock + 1 = Field macroblock + 13 + IntraMbFlag + This field specifies whether the current macroblock is an Intra (I) macroblock. I_PCM is + considered as Intra MB. + For I-picture MB (IntraPicFlag =1), this field must be set to 1. + This flag must be set in consistent with the interpretation of MbType (inter or intra modes). + 0: INTER (inter macroblock) + 1: INTRA (intra macroblock) + 12:8 + MbType5Bits + This field is encoded to match with the best macroblock mode determined as described in + the next section. It follows an unified encoding for inter and intra macroblocks according to + AVC Spec. + 7 + FieldMbPolarityFlag + This field indicates the field polarity of the current macroblock. + Within an MbAff frame picture, this field may be different per macroblock and is set to 1 only + for the second macroblock in a MbAff pair if FieldMbFlag is set. Otherwise, it is set to 0. + Within a field picture, this field is set to 1 if the current picture is the bottom field picture. + Otherwise, it is set to 0. It is a constant for the whole field picture. + This field is reserved and MBZ for a progressive frame picture. + 0 = Current macroblock is a field macroblock from the top field + 1 = Current macroblock is a field macroblock from the bottom field + Programming Note: Here bits [26:24] (MbAffFieldFlag and FiedlMbPolarityFlag) match with + bits [10:8] of the Media Block Read message descriptor, simplifying the programming for + message generation, as when MbAffFieldFlag is “1”, kernels need to override the original + “frame” surface state set for MBAFF frame picture. + + 6 MB Reserved: Inter MB converted to IPCM + This field is used for HW purpose only + SW should not use it. + + 5:4 + IntraMbMode + This field is provided to carry information partially overlapped with MbType. + This field is only valid if IntraMbFlag = INTRA, otherwise, it is ignored by hardware.. + + Reserved: MBZ + 3 + 2 + SkipMbFlag + By setting it to 1, this field forces an inter macroblock to be encoded as a skipped + macroblock. It is equivalent to mb_skip_flag in AVS spec, indicating that a macroblock is + inferred as a P_Skip (or B_Skip) in a P Slice (or B Slice). Hardware honors input MVs for + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 104 + DWord Bit Description + motion prediction and forces CBP to zero. + By setting it to 0, an inter macroblock will be coded as a normal inter macroblock. The + macroblock may still be coded as a skipped macroblock, according to the macroblock type + conversion rules described in the later sub sections. + This field can only be set to 1 for certain values of MbType. See details later. + This field is only valid for an inter macroblock. For intra MB (bit 13 of this DW set to one), this + bit must be set to zero. + 0 = not a skipped macroblock + 1 = is coded as a skipped macroblock + 1:0 + InterMbMode + This field is provided to carry redundant information as that encoded in MbType. + This field is only valid if IntraMbFlag =0, otherwise, it is ignored by hardware. + + 4 31:16 + Cbp4x4Y[bit 15:0] (Coded Block Pattern Y) + For 4x4 sub-block (when Transform8x8flag = 0 or in intra16x16) : + 16-bit cbp, one bit for each 4x4 Luma sub-block (not including the DC 4x4 Luma block in + intra16x16) in a MB. The 4x4 Luma sub-blocks are numbered as + blk0 1 4 5 + bit15 14 11 10 + lk2 36 7 + bit13 12 9 8 + blk8 9 12 13 + bit7 6 3 2 + blk10 11 14 15 + bit5 4 1 0 + The cbpY bit assignment is cbpY bit [15 - X] for sub-block_num X. + + + For 8x8 block (when Transform8x8flag = 1) + Only the lower 4 bits [3:0] are valid; the remaining upper bits [15:4] are ignored. The 8x8 + Luma blocks are numbered as + blk0 1 bit3 2 + blk2 3 bit1 0 + The cbpY bit assignment is cbpY bit [3 - X] for block_num X. + 0 in a bit - indicates the corresponding 8x8 block or 4x4 sub-block is not present (because all + coefficient values are zero), or force to zero for PAK. + 1 in a bit - indicates the corresponding 8x8 block or 4x4 sub-block is present (although it is + still possible to have all its coefficients be zero - bad coding). + Programming Note: when Reference Mb: IPCM or inferred IPCM, current mb: base mode + flag = 1; all bits in CbpDcY, CbpDcU, CbpDcV, Cbp4x4Y[15:0], Cbp4x4V[15:0] and + Cbp4x4U[15:0] must set to 1’s. + 15:8 + MbYCnt (Vertical Origin). This field specifies the vertical origin of current macroblock in the + destination picture in units of macroblocks. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 105 + DWord Bit Description + Format = U8 in unit of macroblock. + 7:0 + MbXCnt (Horizontal Origin). This field specifies the horizontal origin of current macroblock in + the destination picture in units of macroblocks. + Format = U8 in unit of macroblock. + + 5 31:16 + Cbp4x4V (Coded Block Pattern Cr) + Only the lower 4 bits [3:0] are valid for 4:2:0. The 4x4 Cr sub-blocks are numbered as + blk0 1 bit3 2 + blk2 3 bit1 0 + The cbpCr bit assignment is cbpCr bit [3 - X] for sub-block_num X. + 0 in a bit - indicates the corresponding 4x4 sub-block is not present (because all coefficient + values are zero), or force to zero for PAK. + 1 in a bit - indicates the corresponding 4x4 sub-block is present (although it is still possible to + have all its coefficients be zero - bad coding). + For monochrome, this field is ignored. + Programming Note: when Reference Mb: IPCM or inferred IPCM, current mb: base mode + flag = 1; all bits in CbpDcY, CbpDcU, CbpDcV, Cbp4x4Y[15:0], Cbp4x4V[15:0] and + Cbp4x4U[15:0] must set to 1’s. + 15:0 + Cbp4x4U (Coded Block Pattern Cb) + Only the lower 4 bits [3:0] are valid for 4:2:0. The 4x4 Cb sub-blocks are numbered as + blk0 1 bit3 2 + blk2 3 bit1 0 + The cbpCb bit assignment is cbpCb bit [3 - X] for sub-block_num X. + 0 in a bit - indicates the corresponding 4x4 sub-block is not present (because all coefficient + values are zero), or force to zero for PAK. + 1 in a bit - indicates the corresponding 4x4 sub-block is present (although it is still possible to + have all its coefficients be zero - bad coding). + For monochrome, this field is ignored. + Programming Note: when Reference Mb: IPCM or inferred IPCM, current mb: base mode + flag = 1; all bits in CbpDcY, CbpDcU, CbpDcV, Cbp4x4Y[15:0], Cbp4x4V[15:0] and + Cbp4x4U[15:0] must set to 1’s. + 6 31:28 + Skip8x8Pattern + This field indicates whether each of the four 8x8 sub macroblocks is using the predicted MVs + and will not be explicitly coded in the bitstream (the sub macroblock will be coded as direct + mode). It contains four 1-bit subfields, corresponding to the 4 sub macroblocks in sequential + order. The whole macroblock may be actually coded as B_Direct_16x16 or B_Skip, + according to the macroblock type conversion rules described in a later sub section. + This field is only valid for a B slice. It is ignored by hardware for a P slice. Hardware also + ignores this field for an intra macroblock. + 0 in a bit – Corresponding MVs are sent in the bitstream + 1 in a bit – Corresponding MVs are not sent in the bitstream + 27 + EnableCoeffClamp + 1 = the magnitude of coefficients of the current MB will be clamped based on the clamping + matrix after quantization + 0 = no clamping + 26 + LastMbFlag + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 106 + DWord Bit Description + 1 – the current MB is the last MB in the current Slice + 0 – the current MB is not the last MB in the current SliceReserved MBZ. + 25 + SkipMbConvDisable + This is a per-MB level control to enable and disable skip conversion. This field is ORed with + SkipConvDisable field. This field is only valid for a P or B slice. It must be zero for other slice + types. Rules are provided in Section Macroblock Type Conversion Rules + 0 - Enable skip type conversion for the current macroblock + 1 - Disable skip type conversion for the current macroblock + 24:8 Reserved MBZ. + 7:0 + QpPrimeY + This is the per-MB QP value specified for the current MB. + For 8-bit pixel data, QpY is the same as QpPrimeY, and it takes on a value in the range of 0 + to 51, positive integer. + Note: This value may differ from the actual codes, when HW QRC is on + + 7 .. 9 + 31:0 For intra macroblocks, definition of these fields are specified in PAK Object Inline Data + Description + Each + For inter macroblocks, definition of these fields are specified in PAK Object Inline Data + Description + 10 31:24 + MaxSizeInWord + PAK should not exceed this budget accumulatively, otherwise it will trickle the PANIC mode. + + 23:16 + TargetSizeInWord + PAK should use this budget accumulatively to decide if it needs to limit the number of non- + zero coefficients. + 15:0 + Reserved : MBZ + + +Inline data for LumaIntraMode + +ExtendedForm 0 or 1 0 0 1 1 + + Intra4x4 Intra8x8 Intra16x16 Intra8x8 Intra16x16 + DW4 – 31:28 Block 7 - - - Block 0 + DW4 – 27:24 Block 6 - - - Block 0 + DW4 – 23:20 Block 5 - - - Block 0 + DW4 – 19:16 Block 4 - - - Block 0 + DW4– 15:12 Block 3 - - - Block 0 + DW4 – 11:8 Block 2 - - - Block 0 + DW4 – 7:4 Block 1 - - - Block 0 + DW4 – 3:0 Block 0 - - - Block 0 + DW5 – 31:28 Block 15 - - - Block 0 + DW5 – 27:24 Block 14 - - - Block 0 + DW5 – 23:20 Block 13 - - - Block 0 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 107 + ExtendedForm 0 or 1 0 0 1 1 + DW5 – 19:16 Block 12 - - - Block 0 + DW5 – 15:12 Block 11 - - - Block 0 + DW5– 11:8 Block 10 - - - Block 0 + DW5 – 7:4 Block 9 - - - Block 0 + DW5 – 3:0 Block 8 - - - Block 0 + + +vctrl_pred_mode[63:0] + (vctrl_it_lumaintrapredmode3[15:0] & vctrl_it_lumaintrapredmode2[15:0] & + vctrl_it_lumaintrapredmode1[15:0] & vctrl_it_lumaintrapredmode0[15:0] ) : + vctrl_pred_mode_noextend[63:0] +vctrl_pred_mode_noextend[63:0] + (vctrl_INTRA_vld_16x16mode & vctrl_it_Transform8x8Flag) ? + vctrl_pred_mode_noextend_4x4[63:0] : + vctrl_pred_mode_noextend_16x16[63:0] : + vctrl_pred_mode_noextend_8x8[63:0] : + vctrl_pred_mode_noextend_4x4[63:0] +vctrl_pred_mode_noextend_16x1 + vctrl_it_lumaintrapredmode0[3:0] & vctrl_it_lumaintrapredmode0[3:0] & +6[63:0] + vctrl_it_lumaintrapredmode0[3:0] & vctrl_it_lumaintrapredmode0[3:0] & + vctrl_it_lumaintrapredmode0[3:0] & vctrl_it_lumaintrapredmode0[3:0] & + vctrl_it_lumaintrapredmode0[3:0] & vctrl_it_lumaintrapredmode0[3:0] & + vctrl_it_lumaintrapredmode0[3:0] & vctrl_it_lumaintrapredmode0[3:0] & + vctrl_it_lumaintrapredmode0[3:0] & vctrl_it_lumaintrapredmode0[3:0] & + vctrl_it_lumaintrapredmode0[3:0] & vctrl_it_lumaintrapredmode0[3:0] & + vctrl_it_lumaintrapredmode0[3:0] & vctrl_it_lumaintrapredmode0[3:0] +vctrl_pred_mode_noextend_8x8[6 + “h000” & vctrl_it_lumaintrapredmode0[15:12] & +3:0] + “h000” & vctrl_it_lumaintrapredmode0[11:8] & + “h000” & vctrl_it_lumaintrapredmode0[7:4] & + “h000” & vctrl_it_lumaintrapredmode0[3:0] +vctrl_pred_mode_noextend_4x4[6 vctrl_it_lumaintrapredmode3[15:0] & vctrl_it_lumaintrapredmode2[15:0] & +3:0] vctrl_it_lumaintrapredmode1[15:0] & vctrl_it_lumaintrapredmode0[15:0] + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 108 + Inline data for RefPicSelect + +Extende 0 0 0 0 or 1 1 1 1 +dForm + + 16x16 16x8 8x16 8x8 16x16 16x8 8x16 + + DW8 – - - - L0 blk3 L0 blk0 - L0 blk1 + 31:24 + DW8 – - - - L0 blk2 L0 blk0 - L0 blk0 + 23:16 + DW8 – - L0 blk1 L0 blk1 L0 blk1 L0 blk0 - L0 blk1 + 15:8 + DW8 – L0 blk0 L0 blk0 L0 blk0 L0 blk0 L0 blk0 - L0 blk0 + 7:0 + DW9 – - - - L1 blk3 L1 blk0 - L1 blk1 + 31:24 + DW9 – - - - L1 blk2 L1 blk0 - L1 blk0 + 23:16 + DW9 – - L1 blk1 L1 blk1 L1 blk1 L1 blk0 - L1 blk1 + 15:8 + DW9 – L1 blk0 L1 blk0 L1 blk0 L1 blk0 L1 blk0 - L1 blk0 + 7:0 + +The inline data content of Dwords 4 to 6 is defined either for intra prediction or for inter prediction, but not +both. + +Inline data subfields for an Intra Macroblock + +Dword Bit Description + 7 31:16 + LumaIntraMode[1] + Specifies the Luma Intra Prediction mode for four 4x4 sub-block of a MB, 4-bit each. + See the bit assignment table later in this section. + + 15:0 + LumaIntraMode[0] + Specifies the Luma Intra Prediction mode for four 4x4 sub-block, four 8x8 block or one + intra16x16 of a MB. + 4-bit per 4x4 sub-block (Transform8x8Flag=0, Mbtype=0 and intraMbFlag=1) or 8x8 block + (Transform8x8Flag=1, Mbtype=0, MbFlag=1), since there are 9 intra modes. + 4-bit for intra16x16 MB (Transform8x8Flag=0, Mbtype=1 to 24 and intraMbFlag=1), but only + the LSBit[1:0] is valid, since there are only 4 intra modes. + See the bit assignment table later in this section. + 8 31:16 + LumaIntraMode[3] + Specifies the Luma Intra Prediction mode for four 4x4 sub-block of a MB, 4-bit each. + See the bit assignment table later in this section. + 15:0 + LumaIntraMode[2] + Specifies the Luma Intra Prediction mode for four 4x4 sub-block of a MB, 4-bit each. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 109 + Dword Bit Description + See the bit assignment later in this section. + 9 + 31:8 Reserved : MBZ + (Reserved for encocder turbo mode IntraResidueDataSize, when this is not 0, optional + residue data are provided to the PAK; Reserved for decoder) + 7:0 + IntraStruct + This field contains 6 bits for IntraPredAvailFlags[5:0] and 2 bits for ChromaIntraPredMode. + The IntraPredAvailFlags[4:0] (the lower 5 bits) have already included the effect of the + constrained_intra_pred_flag. See the diagram later for the definition of neighbor position + around the current MB or MB pair (in MBAFF mode). + 1 – IntraPredAvailFlagY, indicates the values of samples of neighbor Y can be used in intra + prediction for the current MB. + 0 – IntraPredAvailFlagY, indicates the values of samples of neighbor Y is not available for + intra prediction of the current MB. + IntraPredAvailFlag-A and -E can only be different from each other when + constrained_intra_pred_flag is equal to 1 and mb_field_decoding_flag is equal to 1 and the + value of the mb_field_decoding_flag for the macroblock pair to the left of the current + macroblock is equal to 0 (which can only occur when MbaffFrameFlag is equal to 1). + IntraPredAvailFlag-F is used only if + it is in MBAFF mode, i.e. MbaffFrameFlag = 1, + the current macroblock is of frame type, i.e. MbFieldFag = 0, and + the current macroblock type is Intra8x8, i.e. IntraMbFlag = INTRA, IntraMbMode + = INTRA_8x8, and Transform8x8Flag = 1. + + In any other cases IntraPredAvailFlag-A shall be used instead. + Bits IntraPredAvailFlags Definition + 7 + IntraPredAvailFlagF – F (Left 8th row + (-1,7) neighbor) + 6 + IntraPredAvailFlagA – A (Left + neighbor top half) + 5 + IntraPredAvailFlagE – E (Left + neighbor bottom half) + 4 + IntraPredAvailFlagB – B (Top + neighbor) + 3 + IntraPredAvailFlagC – C (Top right + neighbor) + 2 + IntraPredAvailFlagD – D (Top left + corner neighbor) + 1:0 + ChromaIntraPredMode – 2 bits to + specify 1 of 4 chroma intra prediction + modes, see the table in later section. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 110 + Inline data subfields for an Inter Macroblock +DWord Bit Description +7 31:16 Reserved : MBZ + 15:8 + SubMbPredMode (Sub-Macroblock Prediction Mode): If InterMbMode is INTER8x8, this + field describes the prediction mode of the sub-partitions in the four 8x8 sub-macroblock. It + contains four subfields each with 2-bits, corresponding to the four 8x8 sub-macroblocks in + sequential order. + This field is derived from sub_mb_type for a BP_8x8 macroblock. + This field is derived from MbType for a non-BP_8x8 inter macroblock, and carries redundant + information as MbType). + If InterMbMode is INTER16x16, INTER16x8 or INTER8x16, this field carries the prediction + modes of the sub macroblock (one 16x16, two 16x8 or two 8x16). The unused bits are set to + zero. + Bits [1:0]: SubMbPredMode[0] + Bits [3:2]: SubMbPredMode[1] + Bits [5:4]: SubMbPredMode[2] + Bits [7:6]: SubMbPredMode[3] + 7:0 + SubMbShape (Sub Macroblock Shape) + This field describes the sub-block partitioning of each sub macroblocks (four 8x8 blocks). It + contains four subfields each with 2-bits, corresponding to the 4 fixed size 8x8 sub + macroblocks in sequential order. + This field is provided for MB with sub_mb_type equal to BP_8x8 only (B_8x8 and P_8x8 as + defined in DXVA). Otherwise, this field is ignored by hardware + Bits [1:0]: SubMbShape[0] – for 8x8 Block 0 + Bits [3:2]: SubMbShape[1] – for 8x8 Block 1 + Bits [5:4]: SubMbShape[2] – for 8x8 Block 2 + Bits [7:6]: SubMbShape[3] – for 8x8 Block 3 + Blocks of the MB is numbered as follows : + 01 + 23 + Each 2-bit value [1:0] is defined as : + 00 – SubMbPartWidth=8, SubMbPartHeight=8 + 01 – SubMbPartWidth=8, SubMbPartHeight=4 + 10 – SubMbPartWidth=4, SubMbPartHeight=8 + 11 – SubMbPartWidth=4, SubMbPartHeight=4 + 31:24 +8 RefPicSelect[0][3] + Support up to 4 reference pictures per L0 direction, one per MB partition, if exists. See + details in later section. This field specifies the reference index into the Reference Picture + List0 Table. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 111 + DWord Bit Description + 23:16 + RefPicSelect[0][2] + Support up to 4 reference pictures per L0 direction, one per MB partition, if exists. See + details in later section. This field specifies the reference index into the Reference Picture + List0 Table. + 15:8 + RefPicSelect[0][1] + Support up to 4 reference pictures per L0 direction, one per MB partition, if exists. See + details in later section. This field specifies the reference index into the Reference Picture + List0 Table. + + 7:0 + RefPicSelect[0][0] + Support up to 4 reference pictures per L0 direction, one per MB partition, if exists. See + details in later section. This field specifies the reference index into the Reference Picture + List0 Table. + 31:24 +9 RefPicSelect[1] [3] + Support up to 4 reference pictures per L1 direction, one per MB partition, if exists. See + details in later section. This field specifies the reference index into the Reference Picture + List1 Table. + For P- picture these bits must be set to zero. + 23:16 + RefPicSelect[1][2] + Support up to 4 reference pictures per L1 direction, one per MB partition, if exists. See + details in later section. This field specifies the reference index into the Reference Picture + List1 Table. + For P- picture these bits must be set to zero. + + 15:8 + RefPicSelect[1][1] + Support up to 4 reference pictures per L1 direction, one per MB partition, if exists. See + details in later section. This field specifies the reference index into the Reference Picture + List1 Table. + For P- picture these bits must be set to zero. + 7:0 + RefPicSelect[1][0] + Support up to 4 reference pictures per L1 direction, one per MB partition, if exists. See + details in later section. This field specifies the reference index into the Reference Picture + List1 Table. + For P- picture these bits must be set to zero. + + +2.3.1.1.1 Luma Intra Prediction Modes +Luma Intra Prediction Modes (LumaIntraPredModes) is defined in Luma Intra Prediction Modes. It is +further categorized as Intra16x16PredMode (Luma Intra Prediction Modes), Intra8x8PredMode (Luma +Intra Prediction Modes) and Intra4x4PredMode (Luma Intra Prediction Modes), operating on 16x16, 8x8 +and 4x4 block sizes, respectively. illustrates the intra prediction directions geometrically for the Intra4x4 +prediction. When a macroblock is subdivided, the intra prediction is performed for the subdivision in a +predetermined order. For example, Luma Intra Prediction Modes shows the block order for Intra4x4 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 112 + prediction. And Luma Intra Prediction Modes shows the block order of Block8x8 in a 16x16 region or +Block4x4 in an 8x8 region. + +Definition of LumaIntraPredModes + +LumaIntraPredModes + [index] + Intra16x16PredMode Intra8x8PredMode Intra4x4PredMode + MbType = [1…24] MbType = 0 MbType = 0 + Transform8x8Flag = 0 Transform8x8Flag = 1 Transform8x8Flag = 0 + Index Bit + 0 15:12 MBZ + Block8x8 3 Block4x4 3 (0_0) + + 11:8 MBZ + Block8x8 2 Block4x4 2 (0_1) + + 7:4 MBZ + Block8x8 1 Block4x4 1 (0_2) + + 3:0 + Block16x16 Block8x8 0 Block4x4 0 (0_3) + + 1 15:12 MBZ MBZ + Block4x4 7 (1_0) + + 11:8 MBZ MBZ + Block4x4 6 (1_1) + + 7:4 MBZ MBZ + Block4x4 5 (1_2) + + 3:0 MBZ MBZ + Block4x4 4 (1_3) + + 2 15:12 MBZ MBZ + Block4x4 11 (2_0) + + 11:8 MBZ MBZ + Block4x4 10 (2_1) + + 7:4 MBZ MBZ + Block4x4 9 (2 2) + + 3:0 MBZ MBZ + Block4x4 8 (2_3) + + 3 15:12 MBZ MBZ + Block4x4 15 (3_0) + + 11:8 MBZ MBZ + Block4x4 14 (3_1) + + 7:4 MBZ MBZ + Block4x4 13 (3_2) + + 3:0 MBZ MBZ + Block4x4 12 (3_3) + + +Definition of Intra16x16PredMode +Intra16x16PredMode Description + 0 + Intra_16x16_Vertical + + 1 + Intra_16x16_Horizontal + + 2 + Intra_16x16_DC + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 113 + Intra16x16PredMode Description + 3 + Intra_16x16_Plane + + 4 – 15 Reserved + +Definition of Intra8x8PredMode +Intra8x8PredMode Description + 0 + Intra_8x8_Vertical + + 1 + Intra_8x8_Horizontal + + 2 + Intra_8x8_DC + + 3 + Intra_8x8_Diagonal_Down_Left + + 4 + Intra_8x8_Diagonal_Down_Right + + 5 + Intra_8x8_Vertical_Right + + 6 + Intra_8x8_Horizontal_Down + + 7 + Intra_8x8_Vertical_Left + + 8 + Intra_8x8_Horizontal_Up + + 9 – 15 Reserved + +Definition of Intra4x4PredMode +Intra4x4PredMode Description + 0 + Intra_4x4_Vertical + + 1 + Intra_4x4_Horizontal + + 2 + Intra_4x4_DC + + 3 + Intra_4x4_Diagonal_Down_Left + + 4 + Intra_4x4_Diagonal_Down_Right + + 5 + Intra_4x4_Vertical_Right + + 6 + Intra_4x4_Horizontal_Down + + 7 + Intra_4x4_Vertical_Left + + 8 + Intra_4x4_Horizontal_Up + + 9 – 15 Reserved + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 114 + Intra_4x4 prediction mode directions + + + + +Numbers of Block4x4 in a 16x16 region + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 115 + Numbers of Block4x4 in an 8x8 region or numbers of Block8x8 in a 16x16 region + + + + +Definition of Chroma Intra Prediction Mode + + ChromaIntraPredMode Name of intra_chroma_pred_mode +(intra_chroma_pred_mode) + + 0 Intra_Chroma_DC (prediction mode) + 1 Intra_Chroma_Horizontal (prediction mode) + 2 Intra_Chroma_Vertical (prediction mode) + 3 Intra_Chroma_Plane (prediction mode) + + +2.3.1.1.1 Reference Indices defined for each MB partition type and Bit Assignment + + + + frame/field + MB/Picture + + MB 16x16 16x8 8x16 8x8 + partitioning + + RefIdxL0/1[0] blk0 blk0 blk0 blk0 Bit 7:0 + RefIdxL0/1[1] x blk1 blk1 blk1 Bit 15:8 + RefIdxL0/1[2] x x x blk2 Bit 23:16 + RefIdxL0/1[3] x x x blk3 Bit 31:24 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 116 + 2.3.1.1.2 MB Neighbor Availability in Intra-Prediction Modes (IntraPredAvailFlags) +Current MB is labelled as X. For non-MBAFF mode, 4 neighbors, A, B, C, D, are depicted in the following +picture and are defined as the following. + + • MB D: top left neighbor of current MB X + • MB C: top right neighbor of current MB X + • MB B: top neighbor of current MB X + • MB A: left neighbor of the current MB X + + mbAddrD mbAddrB mbAddrC + D B C + (top-left) (top) (top-right) + + +mbAddrA X N/A + A CurrMbAddrX + (left) + + + N/A N/A N/A + +For MBAFF mode, the current MB is labelled as X0 or X1, 4 neighbor pairs, A0/A1, B0/B1, C0/C1, D0/D1, +are depicted in the following picture and are defined as the following. + + • MB D0: first MB of top left neighbor MB pair of current MB pair X0/X1 + • MB D1: second MB of top left neighbor MB pair of current MB pair X0/X1 + • MB C0: first MB of top right neighbor MB pair of current MB pair X0/X1 + • MB C1: second MB of top right neighbor MB pair of current MB pair X0/X1 + • MB B0: first MB of top neighbor MB pair of current MB pari X0/X1 + • MB B1: second MB of top neighbor MB pair of current MB pari X0/X1 + • MB A0: first MB of left neighbor MB pair of the current MB pair X0/X1 + • MB A1: second MB of left neighbor MB pair of the current MB pair X0/X1 + + mbAddrD mbAddrB mbAddrC + D0 B0 C0 + +mbAddrD+1 mbAddrB+1 mbAddrC+1 + D1 B1 C1 + + N/A + mbAddrA CurrMbAddrX + A0 X0 + or + N/A +mbAddrA+1 CurrMbAddrX + A1 X1 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 117 + For a given macroblock X (or X0/X1), the 6 neighbor availability signals, namely, A, B, C, D, E, F, are +defined as the following. + + • IntraPredAvailFlagF – F: (Single neighbor pixel at the left 8th row (-1,7) + • IntraPredAvailFlagA – A (Left neighbor top half pixel group) + • IntraPredAvailFlagE – E (Left neighbor bottom half pixel group) + • IntraPredAvailFlagB – B (Top neighbor pixel group) + • IntraPredAvailFlagC – C (Top right neighbor pixel group) + • IntraPredAvailFlagD – D (Top left corner neighbor pixel) + +The following table depicts the generation of IntraPredAvailFlags[5:0] signals in a condensed form. It +should note that for most cases only one input neighbor signal is assigned for each condition. The +exception is in the four places for deriving left neighbor A and E where the neighbor is only available if left +neighbors (A0 and A1) are both available (A0&A1). Also note that F takes output value very similar to that +for A except the two “AND” conditions, where F is assigned to A1 instead of (A0&A1). + +Definition of intra-prediction neighbor availability calculation in MBAFF mode + + Output  D B C A E F + +Current X \ Y- Y- Y- Y- + Y-Frame Y- Y-Frame Y-Field Y-Frame Y-Field Y- Y- +Neighbor Y Frame Field Frame Field + Field Frame Field + X- + X0 D1 D1 B1 B1 C1 C1 A0 A0 & A1 A0 A0 & A1 A0 A1 + Frame + (Top) X- + D1 D0 B1 B0 C1 C0 A0 A0 A1 A0 A0 A0 + Field + X- + X1 A0 A1 X0 N/A 0 0 A1 A0 & A1 A1 A0 & A1 A1 A1 + Frame + (Bottom) X- + D1 D1 B1 B1 C1 C1 A0 A1 A1 A1 A0 A1 + Field + +In MB Neighbor Availability in Intra Prediction Modes IntraPredAvailFlags, X-Frame or X-Field indicates +the frame/field mode of the current MB; and Y-Frame or Y-Field indicates the corresponding neighbor MB +for the given neighbor location, being upper left (D) or left (A) for example. Therefore, “Y-” takes the +selected neighbor MB name as in the output cell in the same column. For example, for output D, if X1 is a +frame MB, Y = A, if X1 is a field MB, Y = D. +For non-MBAFF mode, as A0=A1, B0=B1, C0=C1 and D0=D1, the neighbor assignment is degenerated +into the following simple table. Here, E is assigned to the same as A and F is forced to 0. + +Definition of intra-prediction neighbor availability calculation in non-MBAFF mode + + Output  D B C A E F + + X + D0 B0 C0 A0 A0 0 + +To further explain the neighbor assignment rules in MB Neighbor Availability in Intra Prediction Modes +IntraPredAvailFlags, the following table provides description for each condition. Please note that this table +is informative as it provides redundant information as in MB Neighbor Availability in Intra Prediction +Modes IntraPredAvailFlags. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 118 + Detailed explanation of intra-prediction neighbor availability calculation in MBAFF mode + Neighbor Avail +Current Current Neighbor Neighbor MB Result + MB MB Field MB Field Select (Y=?) (OUTPUT) Description + D + X0 X-Frame Y-Frame D D1 + Top Frame MB uses [-1,-1] = D_31, thus D1 only, + (Top) X-Frame Y-Field D D1 regardless D frame or field pair + X-Field Y-Frame D D1 + Top Field MB uses [-1,-2] = D_30, thus if D is + X-Field Y-Field D D0 frame pair, takes D1 (D1_14 pixel), and if D is + field pair, takes D0 (D0_15 pixel) + X1 X-Frame Y-Frame A A0 + Bottom Frame MB uses [-1,15] = A_15, thus A0 +(Bottom) X-Frame Y-Field A A1 (A0_15 pixel) if A is a frame pair, or A1 (A1_7 + pixel), if A is a field pair + X-Field Y-Frame D D1 + Bottom Field MB uses [-1,-1] = D_31, thus D1 + X-Field Y-Field D D1 only, regardless D frame or field pair + B + X0 X-Frame Y-Frame B B1 + Top Frame MB uses [0…15,-1] = B_31, thus B1 + (Top) X-Frame Y-Field B B1 only, regardless B frame or field pair + X-Field Y-Frame B B1 + Top Field MB uses [0…15,-2] = B_30, thus if B is + X-Field Y-Field B B0 frame pair, takes B1 (B1_14 row), and if B is field + pair, takes B0 (B0_15 row) + X1 X-Frame Y-Frame X X0 Bottom Frame MB uses [0…15,15], thus X0 + (X0_15 row) +(Bottom) X-Frame Y-Field X n/a + Note: X0 and X1 must have the same field type, + this row is n/a. + X-Field Y-Frame B B1 + Bottom Field MB uses [0…15,-1] = B_31, thus B1 + X-Field Y-Field B B1 only, regardless B frame or field pair + C + X0 X-Frame Y-Frame C C1 Top Frame MB uses [16…23,-1] = C_31, thus C1 + (Top) X-Frame Y-Field C C1 only, regardless C frame or field pair + X-Field Y-Frame C C1 Top Field MB uses [16…23,-2] = C_30, thus if C is + X-Field Y-Field C C0 frame pair, takes C1 (C1_14 row), and if C is field + pair, takes C0 (C0_15 row) + X1 X-Frame Y-Frame n/a 0 Bottom Frame MB doesn’t have left-top neighbor +(Bottom) X-Frame Y-Field n/a 0 by definition, thus forced to 0 + X-Field Y-Frame C C1 Bottom Field MB uses [16…23,-1] = C_31, thus C1 + X-Field Y-Field C C1 only, regardless C frame or field pair + A + X0 X-Frame Y-Frame A A0 First Half of Top Frame MB uses [-1,0…7], thus A0 + (Top) X-Frame Y-Field A A0&A1 if A is a frame pair; but is only avail if both A0 and + A1 are avail if A is a field pair due to the mix + X-Field Y-Frame A A0 First Half of Top Field MB uses [-1,0..2..4..14], thus + X-Field Y-Field A A0 take A0 (if A is frame pair, takes A0 even lines, and + if A is field pair, takes A0 first half) + X1 X-Frame Y-Frame A A1 First Half of Bottom Frame MB uses [-1,16…23], +(Bottom) X-Frame Y-Field A A0&A1 thus A1 if A is a frame pair; but is only avail if both + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 119 + Neighbor Avail +Current Current Neighbor Neighbor MB Result + MB MB Field MB Field Select (Y=?) (OUTPUT) Description + D + A0 and A1 are avail if A is a field pair due to the + mix + X-Field Y-Frame A A0 First Half of Bottom Field MB uses [-1,1..3..15], + X-Field Y-Field A A1 thus take A0 (if A is frame pair, takes A0 odd lines, + and if A is field pair, takes A1 first half) + E + X0 X-Frame Y-Frame A A0 Second Half of Top Frame MB uses [-1,8…15], + (Top) X-Frame Y-Field A A0&A1 thus A0 if A is a frame pair; but is only avail if both + A0 and A1 are avail if A is a field pair due to the + mix + X-Field Y-Frame A A1 Second Half of Top Field MB uses [-1,16..18..30], + X-Field Y-Field A A0 thus take A1 (if A is frame pair, takes A1 even + lines, and if A is field pair, takes A0 second half) + X1 X-Frame Y-Frame A A1 Second Half of Bottom Frame MB uses [- +(Bottom) X-Frame Y-Field A A0&A1 1,24…31], thus A1 if A is a frame pair; but is only + avail if both A0 and A1 are avail if A is a field pair + due to the mix + X-Field Y-Frame A A1 Second Half of Bottom Field MB uses [- + X-Field Y-Field A A1 1,17..19..31], thus takes A1 (if A is frame pair, + takes A1 odd lines, and if A is field pair, takes A1 + second half) + F + X0 X-Frame Y-Frame A A0 Top Frame MB uses [-1,7] = A_7 (odd location), + (Top) X-Frame Y-Field A A1 thus A0 if A is frame pair and A1 if field pair + X-Field Y-Frame A A0 Top Field MB uses [-1,14] = A_14 (even location), + X-Field Y-Field A A0 thus A0 regardless A frame or field pair + X1 X-Frame Y-Frame A A1 Bottom Frame MB uses [-1,23] = A_23 (odd +(Bottom) X-Frame Y-Field A A1 location), thus A1 regardless A frame or field pair + X-Field Y-Frame A A0 Bottom Field MB uses [-1,15] = A_15 (odd + X-Field Y-Field A A1 location), thus A0 if A is frame pair and A1 if A is + field pair + + +2.3.1.1.3 Macroblock Type for Intra Cases +MbType follows two different tables according to whether the macroblock is an inter or intra macroblock +according to IntraMbFlag. +For an intra macroblock, MbType, as defined in Macroblock Type for Intra Cases, carries redundant +information as IntraMbMode. The notation I_16x16_x_y_z used in the table, ‘x’ is +Intra16x16LumaPredMode, ‘y’ is ChromaCbpInd, and ‘z’ is LumaCbpInd, as defined in Macroblock Type +for Intra Cases. + +MbType definition for Intra Macroblock + + Macroblock Type MbType + + I_4x4 + 0 + + I_8x8 + 0 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 120 + Macroblock Type MbType + + I_16x16_0_0_0 + 1 + + I_16x16_1_0_0 + 2 + + I_16x16_2_0_0 + 3 + + I_16x16_3_0_0 + 4 + + I_16x16_0_1_0 + 5 + + I_16x16_1_1_0 + 6 + + I_16x16_2_1_0 + 7 + + I_16x16_3_1_0 + 8 + + I_16x16_0_2_0 + 9 + + I_16x16_1_2_0 + Ah + + I_16x16_2_2_0 + Bh + + I_16x16_3_2_0 + Ch + + I_16x16_0_0_1 + Dh + + I_16x16_1_0_1 + Eh + + I_16x16_2_0_1 + Fh + + I_16x16_3_0_1 + 10h + + I_16x16_0_1_1 + 11h + + I_16x16_1_1_1 + 12h + + I_16x16_2_1_1 + 13h + + I_16x16_3_1_1 + 14h + + I_16x16_0_2_1 + 15h + + I_16x16_1_2_1 + 16h + + I_16x16_2_2_1 + 17h + + I_16x16_3_2_1 + 18h + + I_PCM + 19h (used by HW) + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 121 + Note: MbType here is identical as specified in DXVA 2.0. +For Intra_16x16 modes, the 5 bits of value (MbType – 1) have the following meanings. + +Sub field definition used by MbType for a macroblock with Intra16x16 prediction + Bits Description + 4 + LumaCbpInd – Luma Coded Block Pattern Indicator + 0 means none of the luma blocks are coded. 1 means that at least one luma block is coded. + 0 = SUBMODE_I16_L_0 + 1 = SUBMODE_I16_L_NZ + In VME output, this field is forced to be 1 before adding 1 in Intra_16x16 mode. + 3:2 + ChromaCbpInd – Chroma Coded Block Pattern Indicator + 00 means none of chroma blocks are coded. 01 means that only the chroma DC block is coded, but + all AC blocks are not coded. 10 means that at least one AC chroma block is coded. + 00 = SUBMODE_I16_C_0 + 01 = SUBMODE_I16_C_DC + 10 = SUBMODE_I16_C_NZ + 11 = Reserved + In VME output, this field is forced to be 10 before adding 1 in Intra_16x16 mode. + Programming Note: Adding 1 to MbType by VME hardware may have carry in to this field. But as + ‘11’ is reserved, the carry-in doesn’t propagate into bit 4 or higher. This allows software to update + MbType, if desired, using the redundant LumaIntraPredModes information. + 1:0 + Intra16x16PredMode – Intra16x16 Prediction Mode + These two bits carries redundant (identical) information as that in LumaIntraPredModes[0][0]. + 0 = SUBMODE_I16_VER + 1 = SUBMODE_I16_HOR + 2 = SUBMODE_I16_DC + 3 = SUBMODE_I16_PLANE + + +IntraMbMode definition +IntraMbMode [1:0] Description Supported by VME? Used by PAK? + 0 Yes Ignored + INTRA_16x16 (redundant with MbType) + + 1 Yes Yes + INTRA_8x8 + + 2 Yes Yes + INTRA_4x4 + + 3 No Ignored + IPCM (redundant with MbType) + +As an alternative representation, MbType is logically the same as the following, except the I_PCM and +I_NxN (i.e. I_4x4 and I_8x8) cases: + + • 24 types of 16x16 intra modes: A+B+C+D: (1h – 18h) + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 122 + MBTYPE_INTRA_16x16 1h A + o 4 Intra16x16 modes: + SUBMODE_I16_VER 0 B + SUBMODE_I16_HOR 1 B + SUBMODE_I16_DC 2 B + SUBMODE_I16_PLN 3 B + + + + o 3 Chroma Cbp indices: + SUBMODE_I16_C_0 0 C + SUBMODE_I16_C_DC 4 C + SUBMODE_I16_C_NZ 8 C + o 2 Luma Cbp indices: + SUBMODE_I16_L_0 0 D + SUBMODE_I16_L_NZ Ch D + + +2.3.1.1.4 Macroblock Type for Inter Cases +Sub-Macroblock Prediction Mode, SubMbPredMode, indicates the prediction mode for the sub-partitions. +Prediction mode specifies prediction direction being forward (from L0), backward (from L1) or bi- +directional (from both L0 and L1). Its meaning depends on InterMbMode. Macroblock Type for Inter +Cases provides the definition of the field. + + • If InterMbMode is INTER16x16, only SubMbPredMode[0] is valid, it describes the prediction mode of + the 16x16 macroblock. The other entries are set to zero by hardware. + o For AVC, SubMbPredMode[0] contains redundant information as encoded in MbType + parameter. + o Note: SubMbPredMode[1]-[3] are intentionally set to zero to allow a simple LUT to + derive MbType as described later. + + • If InterMbMode is INTER16x8, and INTER8x16, only the first two entries SubMbPredMode[0] and + SubMbPredMode[1] are valid, describing the sub-macroblock prediction mode. + o For AVC, SubMbPredMode[0]/[1] contains redundant information as encoded in + MbType parameter. + o Note: SubMbPredMode[2]-[3] are intentionally set to zero to allow a simple LUT to + derive MbType as described later. + + • If InterMbMode is INTER8x8, each entry of SubMbPredMode describes the prediction mode of the + sub-partition of an 8x8 sub-macroblock. + o For AVC, SubMbPredMode can be derived from sub_mb_type field for BP_8x8 + macroblocks as defined in AVC spec. + o Note on Direct Sub-macroblock Prediction Mode: Direct prediction is not conveyed + through SubMbPredMode, instead, it is carried through Direct8x8Pattern. + +InterMbMode definition +MbSkipFlag InterMbMode Description + 0 0 + INTER16x16 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 123 + MbSkipFlag InterMbMode Description + 0 1 + INTER16x8 + + 0 2 + INTER8x16 + + 0 3 + INTER8x8 + + 1 0 + PSKIP/BSKIP16x16* + + 1 3 + BSKIP + + 1 1, 2 Reserved +Used by PAK Ignored by PAK + +* BSKIP16x16 is an optional non-standard but equivalent optimization. + +Definition of SubMbPredMode based on InterMbMode +SubMbPredMode INTER16x16 INTER16x8 INTER8x16 INTER8x8 + Bit MbType = [1…3] MbType = [16h] MbType = [4…15h] MbType = [16h] + 7:6 MBZ MBZ MBZ + Block8x8 3 + + 5:4 MBZ MBZ MBZ + Block8x8 2 + + 3:2 MBZ + Block16x8 1 Block8x16 1 Block8x8 1 + + 1:0 + Block16x16 Block16x8 0 Block8x16 0 Block8x8 0 + + Ignored by PAK Ignored by PAK Ignored by PAK Used by PAK + + +Definition of SubMbPredMode[i] +SubMbPredMode Description InterMbMode VME Output MvCountPred Notes + Pred_L0 All Yes 1 P or B Slice + 0 + Pred_L1 All Yes 1 B Slice Only +1 + BiPred All Yes 2 B Slice Only +2 + 3 Reserved Reserved Reserved Reserved Reserved + +Sub-Macroblock Shape, SubMbShape[i], for i = 0…3, describes the shape of the sub partitions of the 8x8 +sub-macroblock of a BP_8x8 macroblock. This field is only valid if InterMBMode is INTER8x8. They are +defined in Macroblock Type for Inter Cases. The parameters can be derived from sub_mb_type field as +defined in AVC spec. +Note: These fields must be correctly set even for Direct or Skip 8x8 cases, the individual B_Direct_8x8 +block is flagged by the Direct8x8Pattern variable. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 124 + Definition of SubMbShape for an 8x8 region of a BP_8x8 macroblock (including BSKIP, BDIRECT) + Description +SubMbShape NumSubMbPart SubMbPartWidth SubMbPartHeight MvCountShape + 1 8 8 1 + 0 + 2 8 4 2 +1 + 2 4 8 2 +2 + 4 4 4 4 +3 + +For an inter macroblock, MbType, carries redundant information as InterMbMode and SubMbPredMode. +Macroblock Type for Inter Cases provides the typical inter macroblock types and Macroblock Type for +Inter Cases provides that with skip and direct modes. The definition of MbType for both P slice and B +slice is the same and is equivalent to that for mb_type of a B slice in the AVC spec. As direct mode is +indicated using a separate field Direct8x8Pattern, 0 is reserved for MbType. +Here, MVCount is the number of motion vectors actually encoded in the bitstream. It is informative. For a +BP_8x8 or equivalent Skip/Direct macroblock, MVCount is the sum of the following term for the four 8x8 +sub macroblock (with i = 0…3): + MvCountShape[i] * MvCountPred[i] * MvCountDirect[i] +where MvCountShape[i] is block count for sub macroblock [i], MvCountPred[i] is the motion vector count +for each block of sub macroblock[i], and MvCountDirect[i] is the multipler for direct mode for B Slice, +indicating whether motion vectors are coded or not. It must be set to 1 for P slice. For B Slice, +MvCountDirect[i] = !Direct8x8Pattern[i], which is 0 for a sub macroblock coded as direct mode and 1 +otherwise. +In the tables, “DC” stands for “Don’t Care” as PAK hardware ignores these fields. + +MbType definition for Inter Macroblock (and MbSkipflag = 0) +Macroblock Type MbType MbSkipFlag Direct8x8Pattern SubMbShape SubMbPredMode MVCount +Reserved 0 - - - - - + +BP_L0_16x16 1 0 0 DC DC 1 + +B_L1_16x16 + 2 0 0 DC DC 1 + +B_Bi_16x16 + 3 0 0 DC DC 2 + +BP_L0_L0_16x8 4 0 0 DC DC 2 + +BP_L0_L0_8x16 5 0 0 DC DC 2 + +B_L1_L1_16x8 + 6 0 0 DC DC 2 + +B_L1_L1_8x16 + 7 0 0 DC DC 2 + +B_L0_L1_16x8 + 8 0 0 DC DC 2 + +B_L0_L1_8x16 + 9 0 0 DC DC 2 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 125 + Macroblock Type MbType MbSkipFlag Direct8x8Pattern SubMbShape SubMbPredMode MVCount +B_L1_L0_16x8 + 0Ah 0 0 DC DC 2 + +B_L1_L0_8x16 + 0Bh 0 0 DC DC 2 + +B_L0_Bi_16x8 0Ch 0 0 DC DC 3 + +B_L0_Bi_8x16 0Dh 0 0 DC DC 3 + +B_L1_Bi_16x8 0Eh 0 0 DC DC 3 + +B_L1_Bi_8x16 0Fh 0 0 DC DC 3 + +B_Bi_L0_16x8 + 10h 0 0 DC DC 3 + +B_Bi_L0_8x16 + 11h 0 0 DC DC 3 + +B_Bi_L1_16x8 + 12h 0 0 DC DC 3 + +B_Bi_L1_8x16 + 13h 0 0 DC DC 3 + +B_Bi_Bi_16x8 + 14h 0 0 DC DC 4 + +B_Bi_Bi_8x16 + 15h 0 0 DC DC 4 + +BP_8x8 16h 0 != Fh vary vary Sum + +Reserved 17h-1Fh - - - - - + + +Additional MbType definition with Direct/Skip for Inter Macroblock + + Mb Xfrm MbSkip Direct8x8 SubMb SubMb +Macroblock Type 8x8 Flag Pattern Shape PredMode + Type MvCount Notes +P_Skip_16 1 - 1 DC DC DC 0 Skipped macroblock. +x16 Motion compensation like + P_L0_16x16 + +B_Skip_16 16h Vary 1 Fh 0 vary 0 Skipped macroblock. +x16_4MVP Motion compensation like +air B_8x8 with 8x8 subblocks, + when + direct_8x8_inference_flag + is set to 1 + +B_Skip_16 16h 0 1 Fh FFh vary 0 Skipped macroblock. +x16_16MV Motion compensation like +Pair B_8x8 with 4x4 subblocks, + when + direct_8x8_inference_flag + is set to 0 + +B_Direct_1 16h vary 0 Fh 0 vary 0 MbType coded as + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 126 + Mb Xfrm MbSkip Direct8x8 SubMb SubMb +Macroblock Type 8x8 Flag Pattern Shape PredMode + Type MvCount Notes +6x16_4MV B_Direct_16x16. Motion +Pair compensation like B_8x8 + with 8x8 subblocks, when + direct_8x8_inference_flag + is set to 1 + +B_Direct_1 16h 0 0 Fh FFh vary 0 MbType coded as +6x16_16MV B_Direct_16x16. Motion +Pair compensation like B_8x8 + with 4x4 subblocks, when + direct_8x8_inference_flag + is set to 0 + +People might notice that B_DIRECT_16x16 and B_SKIP are mapped on BP_8x8 for AVC decoding +interface in IT mode as the motion compensation operation for both modes are the same as BP_8x8. +According to AVC Spec, motion vectors for B_DIRECT_16x16 and B_SKIP are derived from temporally +co-located macroblock on an 8x8 sub macroblock basis if direct_8x8_inference_flag is set to 1 or on a +4x4 block basis if it is set to 0. For each sub macroblock or block, SubMbPredMode is derived, thus can +any of the valid numbers. Motion vectors may also be different. In spatial direct mode, the motion vectors +are subject to spatial neighbor macroblocks as well as co-located macroblock. The spatial prediction is +based on the neighbor macroblocks, so the same spatial predicted motion vector applies to all sub +macroblocks or blocks. However, under certain conditions, temporal predictor may replace (colZeroFlag) +the spatial predictor for a given sub macroblock or block. Thus the motion vectors may differ. +In Macroblock Type for Inter Cases, the macroblock type names for major partitions nicely follow forms +BP_MbPredMode_MbShape (like BP_L0_16x16) and B_MbPredMode0_MbPredMode1_MbShape (like +B_L0_Bi_16x8). For minor partitions it is fixed as BP_MbShape as BP_8x8. +However, in Macroblock Type for Inter Cases the macroblock types for Skip and Direct modes does not +follow the same rule. The third field in P_Skip_16x16 or B_Direct_16x16_x indicates that “Skip” or “Direct” +applies to the entire 16x16 macroblock, even though MbShape is 8x8 as that in BP_8x8. In order to +distinguish the SubMbShape being 8x8 or 4x4 for B_Skip and B_Direct, the fourth field is added. +4MVPair indicates upto 4 MV pairs are presented with SubMbShape equals to 0; and 16MVPair indicates +up to 16 MV pairs are presented with SubMbShape equals to FFh.Also note that P_8x8ref0 is not +specified in PAK input interface, it is up to hardware to detect and choose its packing format based on +number of reference indices and reference index for the given macroblock. + +2.3.1.1.5 Macroblock Type Conversion Rules +For improved coding efficiency the PAK hardware has the capability to convert macroblock types to use +more efficiency coding modes such as DIRECT and SKIP. For an inter macroblock or a sub macroblock +coded as DIRECT, no motion vector is needed in the bitstream for the macroblock or sub macroblock. If a +macroblock is coded as SKIP, it only consumes one SKIP bit (no motion vector, no coefficients are +coded). And infomaton about the macroblock is ‘inferred’ according to the rules stated in the AVC Spec. +As the input to PAK, the following signals can convey the information regarding DIRECT and SKIP: + + • MbSkipFlag + • Direct8x8Pattern + • CodecBlockPattern (CbpY, CbpCb, CbpCr) + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 127 + Such conversion can be enabled or disabled through the SLICE_STATE fields DirectConvDisable and +SkipConvDisable as well as the in line command field MbSkipConvDisable. +A P slice doesn’t support direct mode, it only supports P_Skip, which is equivalent to a 16_16_L0 +prediction. Other prediction types cannot be converted to P_Skip. The following table describes the +macroblock type conversion rules for a P slice. Here CBP = CbpY/CbpCb/CbpCr are the final computed +results after quantization by the hardware. Note that hardware honors the input CbpY/CbpCb/CbpCr +fields – if the value corresponding to a block is set to zero, the resulting CBP is also zero. The output +mb_skip_flag and mb_type are the symbols coded in the bitstream as defined in the AVC spec. “DC” +stands for “Don’t care”, “T” for “True”. +Note that the internal condition of MV==MVP is subject to the precise rules stated in the AVC Spec as +quoted below. Note that there are exceptions for P_Skip from the normal motion vector prediction rules. +Derivation process for luma motion vectors for skipped macroblocks in P and SP slices +This process is invoked when mb_type is equal to P_Skip. +Outputs of this process are the motion vector mvL0 and the reference index refIdxL0. +The reference index refIdxL0 for a skipped macroblock is derived as follows. +refIdxL0 = 0. (8-168) +For the derivation of the motion vector mvL0 of a P_Skip macroblock type, the following applies. +– The process specified in subclause 8.4.1.3.2 is invoked with mbPartIdx set equal to 0, subMbPartIdx +set equal to 0, currSubMbType set equal to "na", and listSuffixFlag set equal to 0 as input and the output +is assigned to mbAddrA, mbAddrB, mvL0A, mvL0B, refIdxL0A, and refIdxL0B. +– The variable mvL0 is specified as follows. +– If any of the following conditions are true, both components of the motion vector mvL0 are set equal to +0. +– mbAddrA is not available +– mbAddrB is not available +– refIdxL0A is equal to 0 and both components of mvL0A are equal to 0 +– refIdxL0B is equal to 0 and both components of mvL0B are equal to 0 +– Otherwise, the derivation process for luma motion vector prediction as specified in subclause 8.4.1.3 is +invoked with mbPartIdx = 0, subMbPartIdx = 0, refIdxL0, and currSubMbType = "na" as inputs and the +output is assigned to mvL0. +NOTE – The output is directly assigned to mvL0, since the predictor is equal to the actual motion vector. + +Macroblock type conversion rule for an inter macroblock in a P slice + Input Internal Output Notes + SkipConvDisable MV mb_s +Macroblock || == kip_fl mb_ + Type SkipConvDisable CBP MVP MbAffSkipAllowed ag type +P_Skip_16x + DC DC DC 1 1 - Forced to P_Skip; Hardware will +16 + force CBP to zero and also + ignore SkipConvDisable control. + Hardware doesn’t check for + MV==MVP error condition + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 128 + Input Internal Output Notes + SkipConvDisable MV mb_s +Macroblock || == kip_fl mb_ + Type SkipConvDisable CBP MVP MbAffSkipAllowed ag type +P_Skip_16x + DC DC DC 0 0 0 Reverse convert to +16 + P_L0_16x16; Hardware will force + CBP to zero but reversely + convert MbType as P_L0_16x16 + once it determines that Skip is + not allowed. +BP + 0 0 T 1 1 - Converted to P_Skip. Even +_16x16_L0 + input doesn’t provide skip hint, + hardware can performance the + optimization by detecting CBP + and MV==MVP condition. +BP + 0 0 T 0 0 0 Reverse back to P_L0_16x16; +_16x16_L0 + Hardware will reverse back to + P_L0_16x16 even Skip + conditions are met once it + determines that Skip is not + allowed. +BP Still coded as P_L0_16x16 = 0. + 1 0 T T 0 0 +_16x16_L0 + +A B slice supports both direct and skip modes. The following table describes the macroblock type +conversion rules for a B slice. Hardware does not verify MV==MVP condition for a Skip/Direct macroblock +in a B Slice as no DMV is performed by hardware. + +Macroblock type conversion rule for an inter macroblock in a B slice + Input Internal Output Notes + Macroblock SkipConvDisable DirectConv MV MbAffSkip + Type || Disable == Allowed mb_sk mb_t + SkipConvDisable CBP MVP ip_flag ype +B_Skip_8x8 DC DC DC n/a 1 1 - Forced to + B_Skip; +B_Skip_4x4 Hardware will + force CBP to + zero and also + ignore + SkipConvDisabl + e control. + +B_Skip_8x8 DC DC DC n/a 0 0 0 REVERSE + convert to +B_Skip_4x4 B_Direct_16x16 + ; Hardware + will force CBP + to zero and + also reverse + convert to + B_Direct_16x16 + when it + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 129 + Input Internal Output Notes + Macroblock SkipConvDisable DirectConv MV MbAffSkip + Type || Disable == Allowed mb_sk mb_t + SkipConvDisable CBP MVP ip_flag ype + discovers Skip + is not + allowed. + +B_Direct_16x16_4M + 0 0 0 n/a 1 1 - Converted to +VPair/16MVPair B_Skip. + Hardware first + converts to + B_Direct_16x16 + and then + further to + B_Skip if CBP + = 0. + +B_Direct_16x16_4M + 0 0 0 n/a 0 0 0 Converted to +VPair/16MVPair B_Direct_16x16 + . Hardware + first converts + to + B_Direct_16x16 + and stop there + as it + discovers Skip + is not allowed + even CBP=0. + +B_Direct_16x16_4M + 1 0 0 n/a DC 0 0 Converted to +VPair/16MVPair B_Direct_16x16 + . Hardware + converts to + B_Direct_16x16 + and stops + there even + though CBP = 0 + as input + disallows Skip + conversion. + +B_Direct_16x16_4M + DC 0 NZ n/a DC 0 0 Converted to +VPair/16MVPair B_Direct_16x16 + . Hardware + converts to + B_Direct_16x16 + and stops + there because + CBP != 0. + +B_Direct_16x16_4M + DC 1 DC n/a DC 0 16h +VPair/16MVPair + +The internal signal MbAffSkipAllowed is added to deal with a restriction on the frame/field flag +(MbFieldFlag) which is unique to MBAFF. MbAffSkipAllowed is always set to 1 in non-MBAFF modes. +In MBAFF mode, a macroblock pair may be both skipped only if its MbFieldFlag is the same as its + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 130 + available neighbor macroblock pair A or B if A or B is available (in that order), or is not 0 if A/B are both +not available. Otherwise, one of the macroblocks in the pair must be coded. +To reduce the burden on software, PAK hardware handles the above restriction correctly. For the first MB +in a pair, MbAffSkipAllowed is always set to 1. Therefore, hardware allows converting the first MB to +Skip if skip conversion is enabled. For the second MB in a pair, hardware sets MbAffSkipAllowed to 0 if +the following is true: + + • The current MB Pair has different MbFieldFlag than its available neighbor A or B if A or B is + available, or is not 0 if A/B are both not available + • And the first MB is coded as a SKIP (could be forced or converted) + +Otherwise, it sets MbAffSkipAllowed to 1. As MbAffSkipAllowed is to 0 for the above condition, +hardware will disallow Skip mode for the second MB. If the input signal forces it to Skip, hardware +performs reverse-convertion to code it as P_L0_16x16 or B_Direct_16x16 with CBP = 0 for a macroblock +in a P or B Slice. This means that hardware is able to correct the programming mistake by software. If the +macroblock is not forced to skip, hardware simply disallows Skip conversion. +Software still has an option to disallow Skip Conversion on a per-MB basis using the +MbSkipConvDisable control field in the inline command. + +2.3.1.2 Indirect Data Description +For each macroblock, an ENC-PAK data set consists of two types of data blocks: indirect MV data block +and inline MB information. +The indirect MV data block may be in two modes: unpackedmode and packed-size mode. + +2.3.1.2.1 Unpacked Motion Vector Data Block +In the unpacked mode, motion vectors are expanded (or duplicated) to either bidirectional 8x8 8MV +major partition format, or bidirectional 4x4 32MV format. Thus either 32 bytes or 128 bytes is assigned to +each MB. +Motion Vector block contains motion vectors in an intermediate format that is partially expanded +according to the sub- macroblock size. During the expansion, a place that does not contain a motion +vector is filled by replicating the relevant motion vector according to the following motion vector replication +rules. If the relevant motion vector doesn’t exist (for the given L0 or L1), it is zero filled. +Motion Vector Replication Rules: + + • Rule #1 + o #1.1: For L0 MV, for any sub-macroblock or sub-partition where there is at least one + motion vector +  If L0 inter prediction exists, the corresponding L0 MV is used +  Else it must be zero + o #1.2: For L1 MV, for any sub-macroblock or sub-partition where there is at least one + motion vector +  If L1 inter prediction exists, the corresponding L1 MV is used +  Else it must be zero + + • For a macroblock with a 16x16, 16x8 or 8x16 sub-macroblock, MvSize = 8. The eight MV fields + follow Rule #1. + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 131 + o The 16x16 is broken down into 4 8x8 sub-macroblocks. The 16x16 MVs (after rule #1) + are replicated into all 8x8 blocks. + o For an 8x16 partition, each 8x16 is broken down into 2 8x8 stacking vertically. The + 8x16 MVs (after rule #1) are replicated into both 8x8 blocks. + o For a 16x8 partition, each 16x8 is broken down into 2 8x8 stacking horizontally. The + 16x8 MVs (after rule #1) are replicated into both 8x8 blocks. + + • For macroblock with sub-macroblock of 8x8 without minor partition (SubMbShape[0…3] = 0), MvSize + = 8, (e.g. mb_type equal to P_8x8, P_8x8ref0, or B_8x8) + o There is no motion vector replication + + • For macroblock with sub-macroblock of 8x8 with at least one minor partition (if any SubMbShape[i] + != 0), MvSize = 32, (e.g. mb_type equal to P_8x8, P_8x8ref0, or B_8x8) + o For an 8x8 sub-partition, the 8x8 MVs (after rule #1) is replicated into all the four 4x4 + blocks. + o For an 4x8 sub-partition within an 8x8 partition, each 4x8 is broken down into 2 4x4 + stacking vertically. The 4x8 MVs (after rule #1) are replicated into both 4x4 blocks. + o For an 8x4 sub-partition within an 8x8 partition, each 8x4 is broken down into 2 4x4 + stacking horizontally. The 8x4 MVs (after rule #1) are replicated into both 4x4 blocks. + o For a 4x4 sub-partition within an 8x8 partition, each 4x4 has its own MVs (after rule + #1). + +Motion Vector block and MvSize + MvSize + DWord Bit 8 32 + 31:16 + W1.0 MV_Y0_L0.y MV_Y0_0_L0. + y + + 15:0 + MV_Y0_L0.x MV_Y0_0_L0. + x + + 31:16 + W1.1 MV_Y0_L1.y MV_Y0_0_L1. + y + + 15:0 + MV_Y0_L1.x MV_Y0_0_L1. + x + + 31:0 + W1.2 MV_Y1_L0 MV_Y0_1_L0 + + 31:0 + W1.3 MV_Y1_L1 MV_Y0_1_L1 + + 31:0 + W1.4 MV_Y2_L0 MV_Y0_2_L1 + + 31:0 + W1.5 MV_Y2_L1 MV_Y0_2_L0 + + 31:0 + W1.6 MV_Y3_L0 MV_Y0_3_L0 + + 31:0 + W1.7 MV_Y3_L1 MV_Y0_3_L1 + + 31:0 + W2.0 n/a MV_Y1_0_L1 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 132 + MvSize + DWord Bit 8 32 + 31:0 + W2.1 n/a MV_Y1_0_L0 + + 31:0 + W2.2 n/a MV_Y1_1_L1 + + 31:0 + W2.3 n/a MV_Y1_1_L0 + + 31:0 + W2.4 n/a MV_Y1_2_L1 + + 31:0 + W2.5 n/a MV_Y1_2_L0 + + 31:0 + W2.6 n/a MV_Y1_3_L0 + + 31:0 + W2.7 n/a MV_Y1_3_L1 + + 31:0 + W3.0 n/a MV_Y2_0_L1 + + 31:0 + W3.1 n/a MV_Y2_0_L0 + + 31:0 + W3.2 n/a MV_Y2_1_L1 + + 31:0 + W3.3 n/a MV_Y2_1_L0 + + 31:0 + W3.4 n/a MV_Y2_2_L1 + + 31:0 + W3.5 n/a MV_Y2_2_L0 + + 31:0 + W3.6 n/a MV_Y2_3_L0 + + 31:0 + W3.7 n/a MV_Y2_3_L1 + + 31:0 + W4.0 n/a MV_Y3_0_L1 + + 31:0 + W4.1 n/a MV_Y3_0_L0 + + 31:0 + W4.2 n/a MV_Y3_1_L1 + + 31:0 + W4.3 n/a MV_Y3_1_L0 + + 31:0 + W4.4 n/a MV_Y3_2_L1 + + 31:0 + W4.5 n/a MV_Y3_2_L0 + + 31:0 + W4.6 n/a MV_Y3_3_L0 + + 31:0 + W4.7 n/a MV_Y3_3_L1 + +The motion vector(s) for a given sub-macroblock or a sub-partition are uniquely placed in the output +message as shown by the non-duplicate fields in Unpacked Motion Vector Data Block and Unpacked +Motion Vector Data Block. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 133 + MV_Yx_L0 and MV_Yx_L1 may be present individually or both. If one is not present, the corresponding +field must be zero. Subsequently, the duplicated fields will be zero as well. + +Motion Vector duplication by sub-macroblocks for a 16x16 macroblock, whereas the 8x8 column +is for 4x(8x8) partition without minor shape + + DWord Bit 16x16 16x8 8x16 8x8 + 31:16 + W1.0 MV_Y0_L1 MV_Y0_L1 (A) MV_Y0_L1 MV_Y0_L + (A) 1 + + 15:0 + MV_Y0_L0 MV_Y0_L0 (A) MV_Y0_L0 MV_Y0_L + (A) 0 + + 31:16 + W1.1 Duplicate (A) Duplicate (A) MV_Y1_L1 MV_Y1_L + 1 + + 15:0 + Duplicate (A) Duplicate (A) MV_Y1_L0 MV_Y1_L + 0 + + 31:16 + W1.2 Duplicate (A) MV_Y2_L1 (B) Duplicate (A) MV_Y2_L + 1 + + 15:0 + Duplicate (A) MV_Y2_L0 (B) Duplicate (A) MV_Y2_L + 0 + + 31:16 + W1.3 Duplicate (A) Duplicate (B) Duplicate (B) MV_Y3_L + 1 + + 15:0 + Duplicate (A) Duplicate (B) Duplicate (B) MV_Y3_L + 0 + + +Motion Vector duplication by sub-partitions for the first 8x8 sub-macroblock Y0 if any Y0-Y3 +contains minor shape (Y1_ to Y3_ have the same format in W2 to W4) + +DWord Bit 8x8 8x4 4x8 4x4 + 31:16 + W1.0 MV_Y0_L1 MV_Y0_0_L1 (A) MV_Y0_0_L1 (A) MV_Y0_0_L1 + + 15:0 + MV_Y0_L0 MV_Y0_0_L0 (A) MV_Y0_0_L0 (A) MV_Y0_0_L0 + + 31:16 + W1.1 Duplicate (A) Duplicate (A) MV_Y0_1_L1 (B) MV_Y0_1_L1 + + 15:0 + Duplicate (A) Duplicate (A) MV_Y0_1_L0 (B) MV_Y0_1_L0 + + 31:16 + W1.2 Duplicate (A) MV_Y0_2_L1 (B) Duplicate (A) MV_Y0_2_L1 + + 15:0 + Duplicate (A) MV_Y0_2_L0 (B) Duplicate (A) MV_Y0_2_L0 + + 31:16 + W1.3 Duplicate (A) Duplicate (B) Duplicate (B) MV_Y0_3_L0 + + 15:0 + Duplicate (A) Duplicate (B) Duplicate (B) MV_Y0_3_L1 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 134 + 2.3.1.2.2 Packed-size Motion Vector Data Block +In the packed case, no redundant motion vectors are sent. So the number of motion vectors sent, as +specified by MvQuantity is the same as the motion vectors that will be packed (MvPacked). +The following tables are for information only. Fields like MvQuantity and MvPacked are not required +interface fields. + + MbSkipFlag MbType Description Mv MvSize (Minimal MvSize) + Quantity + + 1 1 P_Skip_16x16 0 8 1 + 0 1 BP_L0_16x16 1 8 1 + 0 2 B_L1_16x16 1 8 1 + 0 3 B_Bi_16x16 2 8 2 + 0 4 BP_L0_L0_16x8 2 8 4 + 0 5 BP_L0_L0_8x16 2 8 4 + 0 6 B_L1_L1_16x8 2 8 8 + 0 7 B_L1_L1_8x16 2 8 8 + 0 8 B_L0_L1_16x8 2 8 8 + 0 9 B_L0_L1_8x16 2 8 8 + 0 0Ah B_L1_L0_16x8 2 8 8 + 0 0Bh B_L1_L0_8x16 2 8 8 + 0 0Ch B_L0_Bi_16x8 3 8 8 + 0 0Dh B_L0_Bi_8x16 3 8 8 + 0 0Eh B_L1_Bi_16x8 3 8 8 + 0 0Fh B_L1_Bi_8x16 3 8 8 + 0 10h B_Bi_L0_16x8 3 8 8 + 0 11h B_Bi_L0_8x16 3 8 8 + 0 12h B_Bi_L1_16x8 3 8 8 + 0 13h B_Bi_L1_8x16 3 8 8 + 0 14h B_Bi_Bi_16x8 4 8 8 + 0 15h B_Bi_Bi_8x16 4 8 8 + 0 16h 8 or 32 8 or 32 + BP_8x8 ≥4 + +When MbType = 22, BP_8x8, take the sum of four individual 8x8 subblocks + + Direct8x8Pattern SubMb SubMb Description Mv Mv (Min MvSize) + Shape PredMode Quantity Size + + OR OR OR ADD ADD ADD + + 1 0 0 0 2 1 + P_Skip_8x8 + B_Direct_L0_8x8 + (B-Skip_ L0_8x8) + 1 0 1 0 2 1 + B_Direct_L1_8x8 + (B-Skip_ L1_8x8) + 1 0 2 0 2 2 + B_Direct_Bi_8x8 + (B-Skip_ Bi_8x8) + 1 3 0 0 8 4 + P_Skip_4x4 + B_Direct_L0_4x4 + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 135 + (B-Skip_ L0_4x4) + 1 3 1 0 8 4 + B_Direct_L1_4x4 + (B-Skip_ L1_4x4) + 1 3 2 0 8 8 + B_Direct_Bi_4x4 + (B-Skip_ Bi_4x4) + + 0 0 0 BP_L0_8x8 1 2 1 + 0 0 1 B_L1_8x8 1 2 1 + 0 0 2 B_BI_8x8 2 2 2 + 0 1 0 BP_L0_8x4 2 8 4 + 0 1 1 B_L1_8x4 2 8 4 + 0 1 2 B_BI_8x4 4 8 8 + 0 2 0 BP_L0_4x8 2 8 4 + 0 2 1 B_L1_4x8 2 8 4 + 0 2 2 B_BI_4x8 4 8 8 + 0 3 0 BP_L0_4x4 4 8 4 + 0 3 1 B_L1_4x4 4 8 4 + 0 3 2 B_BI_4x4 8 8 8 + + +2.3.1.3 Macroblock Level Rate Control +The QRC (Qauntization Rate Control) unit receives data from BSP (Bit Serial Packer) and VIN (Video In) +and generates adjustments to QP values across macroblocks. + + + + +QRC can be logically partitioned into two units as shown below. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 136 + Macroblock level rate control is handled by the RC logic and the quantization logic. + + + + +The signals QPmod and panic are generated by the RC logic based on data feedback from BSP. A +flowchart of the RC logic is given below. + + + + +2.3.1.3.1 Theory of Operation Overview +BSP will generate a byte estimate for each macroblock packed. Additionally, the user will specify a target +and max size per macroblock. The running sum of these signals (actual, target, max) creates “curves” +which are used to identify when QP adjustments are necessary (see figure below). Three more curves are +symmetrically generated by QRC (upper_midpt, lower_midpt, sum_min) from target and max. The values +of target and max are specified by the user will dictate the shape of these curves. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 137 + The difference between sum_actual and sum_target (called ‘bytediff’) identifies the margin of error +between the target and actual sizes. The difference between the current bytediff and the previously +calculated bytediff represents the rate of change in this margin over time. The sign of this rate is used to +identify if the correction is trending in the appropriate direction (towards bytediff = 0). + + + + +QPmod +Each macroblock will have a requested QP (which could vary across macroblocks or remain constant). +QPmod is to be added to the QP requested. QPmod will be positive when the target was under-predicted +and negative when the target is over-predicted. +QPmod is incremented or decremented when internal counters (called ‘over’ and ‘under’) reach tripping +points (called ‘grow’ and ‘shrink’). For each MB processed and based on which region (1-6) sum_actual +falls in, various amounts of points are added to either counters. If over exceeds grow, QPmod is +incremented whereas if under exceeds shrink, QPmod is decremented. +To dampen the effect of repeated changes in the same direction, an increase in resistance for that +direction and decrease in resistance for the complementary direction occurs (called ‘grow_resistance’ and +‘shrink_resistance’). This resistance is added to grow or shrink, which then requires more points to trip the +next correction in that direction. +The user can specify guard-bands that limit the amount QPmod can be modified. QPmod cannot exceed +QPmax_pos_mod or become less than -QPmax_neg_mod_abs. +Triggering +The RC unit begins to modify QPmod occurs only when it is triggered. +Three levels of triggering exist: always, gentle, loose. Always means that RC will be active once +sum_actual reaches regions 3 or 4. Gentle will trigger RC once sum_actual reaches regions 2 or 5. Loose +waits to trigger RC when sum_actual reaches regions 1 or 6. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 138 + RC will deactivate (triggered = false) once sum_actual begins to track sum_target over a series of +macroblocks. Specifically, the sign of the rate of change for bytediff is monitored over a window of +macroblocks. When the sum of these signs over the window falls within a tolerance value (called ‘stable’), +triggered will reset to false. +Panic +When enabled, panic mode will occur whenever sum_actual reaches region 1 and will remain so until +sum_actual reaches region 4. When panicking, all macroblocks will be quantized with QP = MB(n).QP + +QPmax_pos_mod, clamped to 51. +User Controls +This unit achieves a large flexibility by allowing the user to define various key parameters. At the per- +macroblock level, the values of target and max are specifed and will create various shapes of curves that +sum_actual will be compared against. +Per-slice, the user can specify the triggering sensitivity and the tolerance required to disable the trigger. +Additionally, the user can enable panic detection. +The point values assigned to each of the 6 regions are exposed to the user which allow for asymmetrical +control for over and under predictions amongst other things. Additionally, the user can specify the initial +values of grow and shrink along with the resistance values applied when correction is invoked. +Lastly, the maximum and minimum values for QPmod are also exposed to the user. + + +2.4 AVC Encoder MBAFF Support + 1. Algorithm +Prediction of current macroblock motion vector is possible from neighboring macroblocks +mbAddrA/mbAddrD/mbAddrB/mbAddrC/mbAddrA+1/mbAddrD+1/mbAddrB+1/mbAddrC+1. The selection +of these macroblocks depends on coding type(field/frame) of current macroblock pair and the coding of +neighbouring macroblock pair. Following is a generic diagram depicting naming conventions used for +neighbouring macroblocks. Selction of these mb pairs desrcibed in detail in following sections. + 1.1 Selection of Top LeftMB pair: The selection of Top Left MB pair depends on coding type of + current and also top left macroblock pair. Following diagram shows the mapping to be used in + MPC unit for the selection of the Top Left MB ( D or D+1 macroblock). + 1.2 Selection of LeftMB pair The selection of Left MB pair depends on coding type of current + and also left macroblock pair. Following diagram shows the mapping to be used in MPC unit for + the selection of the Left MB ( A or A+1 macroblock). + 1.3 Selection of Top MB pair The selection of Top MB pair depends on coding type of + current and also top macroblock pair. Following diagram shows the mapping to be used + in MPC unit for the selection of the Top MB ( B or B+1 macroblock). + 1.4 Selection of Top RightMB pair The selection of Top Right MB pair depends on coding type + of current and also top right macroblock pair. Following diagram shows the mapping to be used + in MPC unit for the selection of the Top Right MB ( C or C+1 macroblock). + 1.5 Motion Vector and refIdx Scaling Motion vectors and refence index of neighbouring + macroblocks (mbAddrA/mbAddrB/mbAddrC/mbAddrD) should be scaled before using + them into prediction equations. Again the scaling depends on coding type of current and + neighbouring macroblock pair which is described as follows, + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 139 +  If the current macroblock is a field macroblock and the macroblock mbAddrN is a frame + macroblock + mvLXN[ 1 ] = mvLXN[ 1 ] / 2 (8-214) + refIdxLXN = refIdxLXN * 2 (8-215) +  Otherwise, if the current macroblock is a frame macroblock and the macroblock + mbAddrN is a field macroblock + mvLXN[ 1 ] = mvLXN[ 1 ] * 2 (8-216) + refIdxLXN = refIdxLXN / 2 (8-217) +  Otherwise, the vertical motion vector component mvLXN[ 1 ] and the reference index + refIdxLXN remain unchanged. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 140 + 3. MPEG-2 +3.1 MPEG2 Common Commands + +3.1.1 MFX_MPEG2_PIC_STATE Command + + MFX_MPEG2_PIC_STATE + +Source: VideoCS +Length Bias: 2 +This must be the very first command to issue after the surface state, the pipe select and base address setting +commands. For MPEG-2 the encoder is called per slice-group, however the picture state is called per picture.Notice +that a slice-group is a group of consecutive slices that no non-trivial slice headers are inserted in between. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_MPEG2_PIC_STATE + Format: OpCode + 26:24 Media Command Opcode + Default Value: 3h MPEG2_COMMON + Format: OpCode + 23:21 SubOpcode A + Default Value: 0h + Format: OpCode + 20:16 SubOpcode B + Default Value: 0h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default 0h Excludes DWord (0,1)= 00Bh, used for normal decode and encode mode000h, a + Value: special case to provide a dummy image state for stitch mode operation. In this case, fields + in DW1 which is part of the dummy image state command are ignored by hardware. + Project: All + Format: =n Total Length - 2 + + + +1 31:28 f_code[1][1]. + Used for backward motion vector prediction. See ISO/IEC 13818-2 §7.6.3.1 for details + 27:24 f_code[1][0]. + Used for backward motion vector prediction. See ISO/IEC 13818-2 §7.6.3.1 for details + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 141 + MFX_MPEG2_PIC_STATE + 23:20 f_code[0][1] + Used for forward motion vector prediction. See ISO/IEC 13818-2 §7.6.3.1 for details + 19:16 f_code[0][0] + Used for forward motion vector prediction. See ISO/IEC 13818-2 §7.6.3.1 for details + 15:14 Intra DC Precision + Project: All + Format: U32 + See ISO/IEC 13818-2 §6.3.10 for details. + + 13:12 Picture Structure + This field specifies whether the picture is encoded in the form of a frame picture or one field (top or + bottom) picture. See ISO/IEC 13818-2 §6.3.10 for details.Format = + MPEG_PICTURE_STRUCTURE00 = Reserved01 = MPEG_TOP_FIELD10 = + MPEG_BOTTOM_FIELD11 = MPEG_FRAME + 11 TFF (Top Field First) + When two fields are stored in a picture, this bit indicates if the top field is the first field.For a frame P + picture, the value 1 indicates that the top field of the reconstructed frame is the first field output by the + decoding process, the same as defined in ISO/IEC 13818-2 §6.3.10. Particularly, it is used by the + hardware to calculate derivative motion vectors from the dual-prime motion vectors.For a field P + picture, hardware uses this bit together with the Picture Structure to determine if the current picture is + the Second Field. In this case, the definition of this bit differs from ISO/IEC 13818-2 §6.3.10 – + software must derive the value for this bit according to the following relation:Picture Structure = top + fieldPicture Structure = bottom fieldSecond Field = 0TFF = 1TFF = 0Second Field = 1TFF = 0TFF = 1 + 10 Frame Prediction Frame DCT + This field provides constraints on the DCT type and prediction type. It affects the syntax of the + bitstream. + 9 Concealment Motion Vector Flag + This field indicates if the concealment motion vectors are coded in intra macroblocks. It affects the + syntax of the bitstream. + 8 Quantizer Scale Type + Format: MPEG_Q_SCALE_TYPE + This field specifies the quantizer scaling type. + Value Name Description + 0h MPEG_QSCALE_LINEAR + 1h D MPEG_QSCALE_NONLINEAR esc + 7 Intra VLC Format + This field is used by VLD + 6 Scan Order + Format: MPEG_INVERSESCAN_TYPE + This field specifies the Inverse Scan method for the DCT-domain coefficients in the blocks of the + current picture. + Value Name Description + 0h MPEG_ZIGZAG_SCAN + 1h MPEG_ALTERNATE_VERTICAL_SCAN + 5:0 Reserved +2 31:24 Reserved + + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 142 + MFX_MPEG2_PIC_STATE + 23:15 Reserved + Format: MBZ + 14 LoadSlicePointerFlag – LoadBitStreamPointerPerSlice + Exists If: Encoder + To support multiple slice picture and additional header/data insertion before and after an encoded + slice.When this field is set to 0, bitstream pointer is only loaded once for the first slice of a frame. For + subsequent slices in the frame, bitstream data are stitched together to form a single output data + stream.When this field is set to 1, bitstream pointer is loaded for each slice of a frame. Basically + bitstream data for different slices of a frame will be written to different memory locations. + Value Name Description + 0h Load BitStream Pointer only once for the first slice of a frame + 1h Load/reload BitStream Pointer only once for the each slice, reload the start location of + the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field + 13 Reserved + Format: MBZ + 12 Reserved + Format: MBZ + 11 Reserved + Format: MBZ + 10:9 Picture Coding Type + Format: MPEG_PICTURE_CODING_TYPE + This field identifies whether the picture is an intra-coded picture (I), predictive-coded picture (P) or bi- + directionally predictive-coded picture (B). See ISO/IEC 13818-2 §6.3.9 for details. + Value Name + 00b Reserved + 01b MPEG_I_PICTURE + 10b 10 = MPEG_P_PICTURE + 11b MPEG_B_PICTURE + 8:2 Reserved + Format: MBZ + 1 MismatchControlDisabled + These 2 bits flag disables mismatch control of the inverse transformation for some specific cases + during reference reconstruction. + Value Name Description + 00b Mismatch control applies to all MBs + 01b Disable mismatch control to all intra MBs whose all AC-coefficients are zero. + 10b Disable mismatch control to all MBs whose all AC-coefficients are zero. + 11b Disable mismatch control to all MBs. + 0 Disable Mismatch + To disable MPEG2 IDCT fixed point arithmetic correction +3 31 Reserved + + Format: MBZ + 30:29 Reserved + Format: MBZ + 23:16 FrameHeightInMBsMinus1[7:0] (Picture Height in Macroblocks) + Format: U8 + To support MB error concealment. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 143 + MFX_MPEG2_PIC_STATE + + 15:8 Reserved + Format: MBZ for future supporting width > 4K + + + + 7:0 FrameWidthInMBsMinus1[7:0] (Picture Width in Macroblocks) + Project: All + Format: U8 + To support MB error concealment. + +4 31:16 MinFrameWSize + Project: All + Format: U32 + Format: GraphicsAddress[31:0]U32 + – Minimum Frame Size [15:0] (16-bit) (Encoder Only)Mininum Frame Size is specified to compensate + for intel Rate ControlCurrently zero fill (no need to perform emulation byte insertion) is done only to + the end of the CABAC_ZERO_WORD insertion (if any) at the last slice of a picture. Intel encoder + parameter, not part of DXVA. The caller should always make sure that the value, represented by + Mininum Frame Size, is always less than maximum frame size FrameBitRateMax (DWORD 10 bits + 29:16). This field is reserved in Decode mode. + Value Name Description + [0,0003FFFFh] The programmable range when MinFrameWSizeUnits is 00. + [0,000FFFFFh] The Programmable range when MinFrameWSizeUnits is 01. + [0,03FFFFFFh] The Programmable range when MinFrameWSizeUnits is 10. + [0,FFFFFFFFh] The Programmable range when MinFrameWSizeUnits is 11. + 0h [Default] + 15 Reserved + Project: All + Format: MBZ + 14:12 RoundInterAC, + rounding precision for non-Intra AC000: +1/16001: +2/16010: +3/16011: +4/16100: +5/16101: + +6/16110: +7/16111: +8/16 + 11 Reserved + Format: MBZ + 10:8 RoundIntraAC + Project: All + Format: U32 + rounding precision for Intra AC000: +1/16001: +2/16010: +3/16011: +4/16100: +5/16101: +6/16110: + +7/16111: +8/16 + + 7 Reserved + Format: MBZ + 6:4 RoundInterDC + rounding Precision for non-Intra-DC000: +1/16001: +2/16010: +3/16011: +4/16100: +5/16101: + +6/16110: +7/16111: +8/16 + 3 Reserved + Format: MBZ + 2:1 RoundIntraDC + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 144 + MFX_MPEG2_PIC_STATE + rounding Precision for Intra-DC00: +1/801: +2/810: +3/811: +4/8 + 0 Reserved +5 31:17 Reserved(for future Mask bits) + 16 FrameSizeControlMask + Frame size conformance maskThis field is used when MacroblockStatEnable is set to 1. + Value Name Description + 0h Do not change Slice Quantization Parameter values in + MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level + Rate control + 1h Replace Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE + with suggested slice QP value for frame level Rate control values in + MFC_IMAGE_STATUS control register. + 15:13 Reserved + 12 InterMBForceCBPZeroControlMask + Format: U32 + Inter MB Force CBP ZERO mask. + Value Name Description Project + [0,FFFFFFFFh] + 0h No effect All + 1h Zero out all A/C coefficients for the inter MB violating Inter Confirmance All + 11:10 MinFrameWSizeUnits + This field is the Minimum Frame Size Units + Value Name Description Project + 00b compatibility mode Minimum Frame Size is in old mode (words, 2bytes) All + 01b 16 byte Minimum Frame Size is in 16bytes All + 10b 4Kb Minimum Frame Size is in 4Kbytes All + 11b 16Kb Minimum Frame Size is in 16Kbytes All + 9 MBRateControlMask + MB Rate Control conformance maskThis field is ignored when MacroblockStatEnable is disabled or + MB level Rate control flag for the current MB is disable in Macroblock Status Buffer. + Value Name Description + 0h Do not change QP values of inter macroblock with suggested QP values in Macroblock + Status Buffer + 1h Apply RC QP delta for all macroblock + 8 Reserved + 7 Reserved + Format: MBZ + 6:4 Reserved + 3 FrameBitRateMinReportMask + This is a mask bit controlling if the condition of frame level bit count is less than FrameBitRateMin. + Value Name Description Project + 0h Disable Do not update bit0 of MFC_IMAGE_STATUS control register. All + 1h Enable set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame All + level bit counter is less than or equal to Frame Bit rate Minimum limit. + 2 FrameBitRateMaxReportMask + This is a mask bit controlling if the condition of frame level bit count exceeds FrameBitRateMax. + Value Name Description Project + 0h Disable Do not update bit0 of MFC_IMAGE_STATUS control register. All + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 145 + MFX_MPEG2_PIC_STATE + 1h Enable set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame All + level bit counter is greater than or equal to Frame Bit rate Maximum limit. + 1 InterMBMaxSizeReportMask + This is a mask bit controlling if the condition of any inter MB in the frame exceeds InterMBMaxSize. + Value Name Description + 0h Do not update bit0 of MFC_IMAGE_STATUS control register. + 1h set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current + MB is greater than the Inter MB Conformance Max size limit. + 0 IntraMBMaxSizeReportMask + This is a mask bit controlling if the condition of any intra MB in the frame exceeds IntraMBMaxSize. + Value Name Description Project + 0h Do not update bit0 of MFC_IMAGE_STATUS control register. All + 1h set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the All + current MB is greater than the Intra MB Conformance Max size limit. +6 31:28 Reserved + Project: All +(Encode Format: MBZ +only) 27:16 InterMBMaxSize + Default Value: FFFh + This field, Inter MB Conformance Max size limit,indicates the allowed max bit count size for Inter MB + + 15:12 Reserved + Project: All + Format: MBZ + 11:0 IntraMBMaxSize + Default Value: FFFh + This field, Intra MB Conformance Max size limit,indicates the allowed max bit count size for Intra MB + +7 31:0 Reserved + Project: All + Format: MBZ +8 31:24 SliceDeltaQPMax[3] + Format: S7 +(Encode +only) + This field is the Slice level delta QP for total bit-count above FrameBitRateMax - first 1/8 regionThis + field is used to calculate the suggested slice QP into the MFC_IMAGE_STATUS control register + when total bit count for the entire frame exceeds FrameBitRateMax but is within 1/8 of + FrameBitRateMaxDelta above FrameBitRateMax, i.e., in the range of (FrameBitRateMax, + (FrameBitRateMax+ FrameBitRateMaxDelta>>3). + Range: [-30,30] + + + Value Name Project + 0h Disable All + 1h Enable All + + + Errata Description + # + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 146 + MFX_MPEG2_PIC_STATE + 23:16 SliceDeltaQPMax[2] + Format: S7 + + + Range: [-30,30] + This field is the Slice level delta QP for bit-count above FrameBitRateMax - above 1/8 and below 1/ 4 + This field is used to calculate the suggested slice QP into the MFC_IMAGE_STATUS control register + when total bit count for the entire frame is between 1/8 and ¼ of FrameBitRateMaxDelta above + FrameBitRateMax, i.e., in the range of ((FrameBitRateMax+ FrameBitRateMaxDelta>>3), + (FrameBitRateMax+ FrameBitRateMaxDelta>>2). + 15:8 SliceDeltaQPMax[1] + Format: S7 + + + Range: [-30,30] + This field is the Slice level delta QP for bit-count above FrameBitRateMax – above1/ 4 and below 1/2 + This field is used to calculate the suggested slice QP into the MFC_IMAGE_STATUS control register + when total bit count for the entire frame is between ¼ and ½ of FrameBitRateMaxDelta above + FrameBitRateMax, i.e., in the range of ((FrameBitRateMax+ FrameBitRateMaxDelta>>2), + (FrameBitRateMax+ FrameBitRateMaxDelta>>1). + 7:0 SliceDeltaQPMax[0] + Format: S7 + + + Range: [-30,30] + This field is the Slice level delta QP for bit-count above FrameBitRateMax - above 1/ 2This field is + used to calculate the suggested slice QP into the MFC_IMAGE_STATUS control register when total + bit count for the entire frame is above FrameBitRateMax by more than half the distance of + FrameBitRateMaxDelta , i.e., in the range of ((FrameBitRateMax+ FrameBitRateMaxDelta>>1), + infinite). +9 31:24 SliceDeltaQPMin[3] + Format: S7 +(Encode +only) + Range: [-30,30] + This field is the Slice level delta QP for total bit-count below FrameBitRateMin - first 1/8 regionThis + field is used to calculate the suggested slice QP into the MFC_IMAGE_STATUS control register + when total bit count for the entire frame is less than FrameBitRateMin and greater than or equal to + 1/8 the distance of FrameBitRateMinDelta from FrameBitRateMin, i.e., in the range of + [(FrameBitRateMin- FrameBitRateMinDelta>>3), FrameBitRateMin). + 23:16 SliceDeltaQPMin[2] + Format: S7 + + + Range: [-30,30] + This field is the Slice level delta QP for bit-count below FrameBitRateMin – below 1/ 8 and above 1/ + 4This field is used to calculate the suggested slice QP into the MFC_IMAGE_STATUS control + register when total bit count for the entire frame is between one-eighth and quarter the distance of + FrameBitRateMinDelta from FrameBitRateMin, i.e., in the range of [(FrameBitRateMin- + FrameBitRateMinDelta>>2), (FrameBitRateMin- FrameBitRateMinDelta>>3)). + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 147 + MFX_MPEG2_PIC_STATE + 15:8 SliceDeltaQPMin[1] + Format: S7 + + + Range: [-30,30] + This field is the Slice level delta QP for bit-count below FrameBitRateMin– below 1/4 and above 1/ + 2This field is used to calculate the suggested slice QP into the MFC_IMAGE_STATUS control + register when total bit count for the entire frame is between quarter and half the distance of + FrameBitRateMinDelta from FrameBitRateMin, i.e., in the range of [(FrameBitRateMin- + FrameBitRateMinDelta>>1), (FrameBitRateMin- FrameBitRateMinDelta>>2)). + 7:0 SliceDeltaQPMin[0] + Format: S7 + + + Range: [-30,30] + This field is the Slice Level Delta QP for bit-count below FrameBitRateMin – below 1/ 2This field is + used to calculate the suggested slice QP into the MFC_IMAGE_STATUS control register when total + bit count for the entire frame is below FrameBitRateMin by more than half the distance of + FrameBitRateMinDelta , i.e., in the range of [0, (FrameBitRateMin- FrameBitRateMinDelta>>1). +10 31 FrameBitrateMaxUnit + This field is the Frame Bitrate Maximum Limit Units. +(Encode Value Name Description Project +only) 0h Byte FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 All + and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 + 1h Kilobyte FrameBitRateMax is in units of 4KBytes Bytes when All + FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if + FrameBitrateMaxUnitMode is 0 + 30 FrameBitrateMaxUnitMode + BitFiel This field is the Frame Bitrate Maximum Limit Units.dDesc + Value Name Description Project + 0h Compatibility mode FrameBitRateMaxUnit is in old mode (128b/16Kb) All + 1h New mode FrameBitRateMaxUnit is in new mode (32byte/4Kb) All + 29:16 FrameBitRateMax + This field is the Frame Bitrate Maximum Limit. This field along with FrameBitrateMaxUnit determines + maximum allowed bits in a frame before multi-pass gets triggered (when enabled). In other words, + multi-pass is triggered when the actual frame byte count exceeds this value. When + FrameBitrateMaxUnitMode is 0(compatibility mode) bits 16:27 should be used, bits 28 and 29 should + be 0. + Value Name Description + 0-512KB The programmable range 0-512KB when FrameBitrateMaxUnit is 0. + 0-8190KB The programmable range 0-8190KB when FrameBitrateMaxUnit is 1. + 15 FrameBitrateMinUnit + This field is the Frame Bitrate Minimum Limit Units. + Value Name Description Project + 0h Byte FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 All + and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 + 1h KiloByte FrameBitRateMax is in units of 4KBytes Bytes when All + FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if + FrameBitrateMaxUnitMode is 0 + 14 FrameBitrateMinUnitMode + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 148 + MFX_MPEG2_PIC_STATE + This field is the Frame Bitrate Minimum Limit Units.ValueNameDescriptionProject + Value Name Description Project + 0h compatibility mode FrameBitRateMaxUnit is in old mode (128b/16Kb) All + 1h New Mode FrameBitRateMaxUnit is in new mode (32byte/4Kb) All + 13:0 FrameBitRateMin + This field is the Frame Bitrate Minimum Limit ()This field along with FrameBitrateMinUnit determines + minimum allowed bits in a Frame before Multi-Pass gets triggered (when enabled). In other words, + multi-pass is triggered when the actual frame byte count is less than this value. When + FrameBitrateMinUnitMode is 0 (compatibility mode) bits 0:11 should be used, bits 12 and 13 should + be 0. Range: The programmable range 0-512KB When FrameBitrateMinUnit is in 0. Programmable + range is 0–8190 KB when FrameBitrateMinUnit is in 1 +11 31 Reserved + Format: MBZ +(Encode 30:16 FrameBitRateMaxDelta +only) Default Value: 0h + Project: All + Access: None + Exists If: Always + Format: U32 + Format: GraphicsAddress[31:0]U32 + + + This field is used to select the slice delta QP when FrameBitRateMax Is exceeded. It shares the + same FrameBitrateMaxUnit. + The programmable range is either 0- 512KB or 4MBB in FrameBitrateMaxUnit of 128 Bytes or 16KB + respectively. + This field is used to select the slice delta QP when FrameBitRateMax Is exceeded. It shares the + same FrameBitrateMaxUnit. When FrameBitrateMaxUnitMode is 0(compatibility mode) bits 16:27 + should be used, bits 28, 29 and 30 should be 0. + 15 Reserved + Project: All + Format: MBZ + 14:0 FrameBitRateMinDelta + This field is used to select the slice delta QP when FrameBitRateMin Is exceeded. It shares the same + FrameBitrateMinUnit. When FrameBitrateMinUnitMode is 0(compatibility mode) bits 0:11 should be + used, bits 12, 13 and 14 should be 0.Note: HW requires the following condition + FrameBitRateMinDelta <= 2*FrameBitRateMinMust be true, otherwise it may cause unpredicted + behavior. + Value Name Description + 0-1024KB The programmable range 0-1024KB When FrameBitrateMinUnit is in 32Bytes. + 0-16380KB Programmable range is 0–16380KB when FrameBitrateMinUnit is in 4Kbytes. +12 31:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 149 + 3.2 MPEG2 Decoder Commands + +3.2.1 MFD_MPEG2_BSD_OBJECT Command (pipeline) + + MFD_MPEG2_BSD_OBJECT + +Source: VideoCS +Length Bias: 2 +Different from AVC and VC1, MFD_MPEG2_BSD_OBJECT command is pipelinable. This is for performance +purpose as in MPEG2 a slice is defined as a group of MBs of any size that must be within a macroblock row.Slice +header parameters are passed in as inline data and the bitstream data for the slice is passed in as indirect data. Of +the inline data, slice_horizontal_position and slice_vertical_position determines the location within the destination +picture of the first macroblock in the slice. The content in this command is identical to that in the MEDIA_OBJECT +command in VLD mode described in the Media Chapter. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFD_MPEG2_BSD_OBJECT + Format: OpCode + 26:24 Media Command Opcode + Default Value: 3h MPEG2_DEC + Format: OpCode + 23:21 SubOpcode A + Default Value: 1h + Format: OpCode + 20:16 SubOpcode B + Default Value: 8h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 0003h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:0 Indirect BSD Data Length + Project: All + Format: U32 + It is the length in bytes of the bitstream data for the current slice. It includes the first byte of the first + macroblock and the last non-zero byte of the last macroblock in the slice. Specifically, the zero-padding + bytes (if present) and the next start-code are excluded. + This field is sized to support beyond MPEG-2 MP@HL bitstream (<4K). According to Table 8-6 of + ISO/IEC 13818-2, the maximum number of bits per macroblock for 4:2:0 is 4608. So the maximum slice + size for 4K x 4K is 4608 * 256 / 8 = 147,456 bytes (0x24000), which requires 18 bits. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 150 + MFD_MPEG2_BSD_OBJECT + Programming Notes Project + As MPEG-2 spec does not post any limitation of the size of zero-padding bytes, it is possible + to have a slice data with large length (including zero-padding bytes). As the data beyond + 0x10E00 would only be zero bytes for a valid slice data + Hardware does not handle zero-padding at the end of the slice data so driver needs to + program the datalength from the first byte of the first macroblock and the last non-zero byte of + the last macroblock in the slice. This datalength must exclude all the extra zero padding at the + end of a slice bitstream. + Bits [31:24] must be programmed to 0. +2 31:29 Reserved + Project: All + Format: MBZ + 28:0 Indirect Data Start Address + This field specifies the Graphics Memory starting address of the data to be fetched into BSD Unit for + processing. This pointer is relative to the BSD Indirect Object Base Address.Hardware ignores this field + if indirect data is not present. It is a byte-aligned address for the MPEG2 VLD bitstream data This + address points to the first byte of the MB layer data, i.e. not including slice header. +3..4 31:0 Inline Data + All the required Slice Header parameters and error handling settings are captured as inline data of the + MPEG2_BSD_OBJECT command. It has a fixed size of 2 DWs. Its definition is described in the next + section. + + + +3.2.1.1 Inline Data Description in MFD_MPEG2_BSD_OBJECT + + Inline Data Description in MFD_MPEG2_BSD_OBJECT + +Source: VideoCS +Default Value: 0x00000000, 0x00000000 +DWord Bit Description +3 31 Reserved + Format: MBZ + 30:24 Slice Horizontal Position + Format: U7 in Macroblocks + + + This field indicates the horizontal position (in macroblock units) of the first macroblock in the slice. + + 23 Reserved + Format: MBZ + 22:16 Slice Vertical Position + Format: U7 in Macroblocks + + + This field indicates the vertical position (in macroblock units) of the first macroblock in the slice. + + 15 Reserved + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 151 + Inline Data Description in MFD_MPEG2_BSD_OBJECT + Format: MBZ + 14:8 Macroblock Count + Format: U7 in Macroblocks + + + This field indicates the number of macroblocks in the slice, including skipped macroblocks. + + 7:6 Reserved + Format: MBZ + 5 Last Pic Slice + This bit is added to support error concealment at the end of a picture. + Value Name Description + 1h The current Slice is the last Slice of the entire picture + 0h The current Slice is not the last Slice of current picture + 3 Is Last MB + Value Name Description + 1h The current MB is the last MB in the current Slice + 0h The current MB is not the last MB in the current Slice + 2:0 First Macroblock Bit Offset + Format: U3 + This field provides the bit offset of the first macroblock in the first byte of the input bitstream. + +4 31:29 Reserved + Format: MBZ + 28:24 Quantizer Scale Code + Format: U5 + This field sets the quantizer scale code of the inverse quantizer. It remains in effect until changed by a + decoded quantizer scale code in a macroblock. This field is decoded from the slice header by host + software. + + 23:0 Reserved + Format: MBZ + + + +3.2.1.2 Indirect Data Description +The indirect data start address in MFD_MPEG2_BSD_OBJECT specifies the starting Graphics Memory +address of the bitstream data that follows the slice header. It provides the byte address for the first +macroblock of the slice. Together with the First Macroblock Bit Offset field in the inline data, it provides +the bit location of the macroblock within the compressed bitstream. +The indirect data length in MFD_MPEG2_BSD_OBJECT provides the length in bytes of the bitstream +data for this slice. It includes the first byte of the first macroblock and the last non-zero byte of the last +macroblock in the slice. Specifically, the zero-padding bytes (if present) and the next start-code are +excluded. Hardware ignores the contents after the last non-zero byte. Indirect Data Description illustrates +these parameters for a slice data. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 152 + Indirect data buffer for a slice + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 153 + 4. JPEG +4.1 JPEG Decoder Commands + +4.1.1 MFD_JPEG_BSD_OBJECT Command + + MFD_JPEG_BSD_OBJECT +Project: All +Source: VideoCS +Length Bias: 2 +Decoder +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFD_JPEG_BSD_OBJECT + Format: OpCode + 26:24 Media Command Opcode + Default Value: 7h JPEG_DEC + Format: OpCode + 23:21 SubOpcode A + Default Value: 1h + Format: OpCode + 20:16 SubOpcode B + Default Value: 8h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 004h Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:0 Indirect Data Length + Project: All + . It is the length in bytes of the bitstream data for the current Scan. It includes the first byte of the first + MCU and the last non-zero byte of the last MCU in the Scan. Specifically, the zero-padding bytes (if + present) are excluded. Hardware ignores the contents after the last non-zero byte. + +2 31:29 Reserved + Project: All + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 154 + MFD_JPEG_BSD_OBJECT + Format: MBZ + 28:0 Indirect Data Start Address + Project: All + This field specifies the Graphics Memory starting address of the data to be fetched into BSD Unit for + processing. This pointer is relative to the BSD Indirect Object Base Address.Hardware ignores this field + if indirect data is not present. It is a byte-aligned address for the JPEG bitstream data + +3 31:29 Reserved + Project: All + Format: MBZ + 28:16 Scan Horizontal Position + Project: All + Format: U13 bits in blocks + + + This field indicates the horizontal position (in block units) of the first MCU in the Scan. + + 15:13 Reserved + Project: All + Format: U13 bits in blocks + + + + 12:0 Scan Vertical Position + Project: All + Format: U13 bits in blocks + + + This field indicates the vertical position (in block units) of the first MCU in the Scan. + +4 31 Reserved + Format: MBZ + 30 Interleaved + Value Name Description + 0 Non-Interleaved one component in the Scan + 1 Interleaved multiple components in the Scan + 29:27 Scan Components + Bit0: Y + Bit1: U + Bit2: V + For example, if non-interleaved Y, then it will be set to 001b. If interleaved Y, U, and V, it will be set to + 111b. + 26 Reserved + Format: MBZ + 25:0 MCU Count + Project: All + Format: U26 + This field indicates the number of MCUs in the Scan. + +5 31:16 Reserved + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 155 + MFD_JPEG_BSD_OBJECT + Project: All + Format: MBZ + 15:0 RestartInterval(16 bit) + Project: All + Format: U32 + Specifies the number of MCU in restart interval. Valid values are 1->0xFFFFValue of 0 implies that all + the SCAN have only one ECS. + + + + +4.1.2 MFX_JPEG_PIC_STATE Decoder + + MFX_JPEG_PIC_STATE_Decoder Only + +Source: VideoCS +Length Bias: 2 +Exists If: Decoder Only +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_MULTI_DW + Format: OpCode + 26:24 Media Command Opcode + Default Value: 7h JPEG_COMMON + Format: OpCode + 23:21 SubOpcode A + Default Value: 0h + Format: OpCode + 20:16 SubOpcode B + Default Value: 0h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Project: All + Format: =n Total Length - 2 + + + + + Value Name Description + 0001h [Default] Excludes DWord (0,1) +1 31:21 Reserved + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 156 + MFX_JPEG_PIC_STATE_Decoder Only + Format: MBZ + 20:19 Reserved + + Format: MBZ + 18 Reserved + + Format: MBZ + 17:16 Reserved + + + 15:12 Reserved + Format: MBZ + 11:8 Reserved + + Format: MBZ + 7:6 Reserved + Format: MBZ + 5:4 Rotation + Value Name Description + 00b no rotation + 01b rotate clockwise 90 degree + 10b rotate counter-clockwise 90 degree (same as rotating 270 degree clockwise) + 11b rotate 180 degree (NOT the same as flipped on the x-axis) + 3 Reserved + Format: MBZ + 2:0 Input Format YUV + Exists If: Always + Format: U32 GraphicsAddress[31:0] + + + + + Value Name Description + 0 [Default] YUV400 (grayscale image) + 1 YUV420 + 2 YUV422H_2Y (Horizontally chroma 2:1 subsampled) – horizontal 2 Y-block, 1U and 1V + 3 YUV444 + 4 YUV411 + 5 YUV422V_2Y (Vertically chroma 2:1 subsampled) – vertical 2 Y-blocks, 1U and 1V + 6 YUV422H_4Y - 2x2 Y-blocks, vertical 2U and 2V + 7 YUV422V_4Y - 2x2 Y-blocks, horizontal 2U and 2V +2 31:29 Reserved + Format: MBZ + 28:16 Frame Height In Blocks Minus 1 + Format: U32 + (The number of blocks in height) – 1. + This value is calculated using the number of lines Y and vertical sampling factor of the first component + V1 in Frame header. See the note following this table. + For interleaved components, (((Y + (V1*8 -1)) / (V1*8)) * V1) – 1 + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 157 + MFX_JPEG_PIC_STATE_Decoder Only + For non-interleaved components, ((Y + 7) / 8) – 1. + + 15:13 Reserved + Format: MBZ + 12:0 Frame Width In Blocks Minus 1 + Format: U32 + (The number of blocks in width) – 1. + This value is calculated using the number of samples per line X and horizontal sampling factor of the + first component H1 in Frame header. See the note following this table. + For interleaved components, (((X + (H1 *8 -1)) / (H1 *8)) * H1) – 1. + For non-interleaved components, ((X + 7) / 8) – 1. + + + + +For JPEG decoding, the following program note is informative. +For Rotation, it is important to note that rotation of 90 or 270 degrees also requires exchanging +FrameWidthlnBlksMinus1 with FrameHeightlnBlksMinus1 in the command. In addition, the rotation of +90 or 270 degrees also requires transportation of the quantization matrix will be transposed into the +position (y, x). +Chroma type is determined by the values of horizontal and vertical sampling factors of the components +(Hi and Vi where i is a component id) in the Frame header as shown in the following table. + + H1 H2 H3 V1 V2 V3 + + +0: YUV400 r Not Not available r Not available Not + available available + + +1: YUV420 2 1 1 2 1 1 + + +2:YUV422H_2Y 2 1 1 1 1 1 + + +3: YUV444 1 1 1 1 1 1 + + +4: YUV411 4 1 1 1 1 1 + + +5: YUV422V_2Y 1 1 1 2 1 1 + + +6: 2 1 1 2 2 2 +YUV422H_4Y + + +7: YUV422V_4Y 2 2 2 2 1 1 + +For YUV400, the value of V1 can be 1, 2, or 3 and will be same as the value of H1, and the Minimum +coded unit (MCU) is one 8x8 block. For the other chroma formats, if non-interleaved data, the MCU is one + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 158 + 8x8 block. For interleaved data, the MCU is the sequence of block units defined by the sampling factors +of the components. +For example, the following figures show the MCU structures of interleaved data and the decoding order of +blocks in the MCU: + 422H_2Y + + + + + 422H_4Y + + + + + 422V_2Y + + + + + 422V_4Y + + + + +If picture width X in the Frame header is not a multiple of 8, the decoding process needs to extend the +number of column to complete the right-most sample blocks. If the component is to be interleaved, the +decoding process needs to extend the number of samples by one or more additional blocks so that the +number of blocks is an integer multiple of Hi. In other words, “The number of blocks in width” in the table +should be an integer multiple of (8xH1). Similarly, if picture height Y in the Frame header is not a multiple +of 8, the decoding process needs extend the number of lines to complete bottom-most block-row. If the +component is to be interleaved, the decoding process also needs to extend the number of lines by one or +more additional block-rows so that the number of block-row is an integer multiple of (8xV1). For example, +if non-interleaved YUV411 with X=270, then “The number of blocks in width” shall be (270 + 7) / 8 = 34, +where “/” is integer division. Therefore, FrameWidthlnBlksMinus1 will be set to 33. However, for +interleaved data, “The number of blocks in width” shall be ((270 + 31) / 32) x 4 = 36. Therefore, +FrameWidthlnBlksMinus1 will be set to 35. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 159 + 4.1.3 MFX_JPEG_HUFF_TABLE_STATE + + MFX_JPEG_HUFF_TABLE_STATE +Project: All +Source: VideoCS +Length Bias: 2 +This Huffman table commands contains both DC and AC tables for either luma or chroma. Once a Huffman table has +been defined for a particular destination, it replaces the previous tables stored in that destination and shall be used in +the remaining Scans of the current image. A Huffman table will be sent to H/W only when it is loaded from bitstream. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFX_MULTI_DW + Format: OpCode + 26:24 Media Command Opcode + Default Value: 7h JPEG_COMMON + Format: OpCode + 23:21 SubOpcode A + Default Value: 0h + Format: OpCode + 20:16 SubOpcode B + Default Value: 2h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default Value: 033Dh Excludes DWord (0,1) + Project: All + Format: =n Total Length - 2 + + + +1 31:1 Reserved + Format: MBZ + 0 HuffTableID (1-bit) + Identifies the huffman table. + Value Name Description + 0 Y Huffman table for Y +2..4 31:0 DC_BITS (12 8-bit array) + The number of DC Huffman codes of length i, where i is 1~12 +5..7 31:0 DC_HUFFVAL (12 8-bit array) + The value associated with each DC Huffman code of length i. +8..11 31:0 AC_BITS (16 8-bit array) + the list of Li, number of Huffman codes of length i, where i is 1~16 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 160 + MFX_JPEG_HUFF_TABLE_STATE +12..51 31:0 AC_HUFFVAL (160 8-bit array) + the list of Vi,j, the value associated with each Huffman code of length i +52 31:16 Reserved + Project: All + Format: MBZ + 15:0 AC_HUFFVAL(2-8 bit array) + In AC table, BITS can have up to 16-bit codeword. Li can be 0 ~ 162. HUFFVAL will have a list of + likely random distributed values + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 161 + 5. More Decoder and Encoder +5.1 MFD IT Mode Decode Commands + +5.1.1 MFD_IT_OBJECT Command + + MFD_IT_OBJECT +Project: All +Source: VideoCS +Length Bias: 2 +All weight mode (default and implicit) are mapped to explicit mode. But the weights come in either as explicit or +implicit. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h PARALLEL_VIDEO_PIPE + Format: OpCode + 28:27 Pipeline + Default Value: 2h MFD_IT_OBJECT + Format: OpCode + 26:24 Media Command Opcode + Default Value: 0h MFX_COMMON_DEC + Format: OpCode + 23:21 SubOpcode A + Default Value: 1h + Format: OpCode + 20:16 SubOpcode B + Default Value: 9h + Format: OpCode + 15:12 Reserved + Project: All + Format: MBZ + 11:0 DWord Length + Default 0h Excludes DWord (0,1) For AVC = Ch + Value: + Project: All + Format: =n Total Length – 2Note: Regardless of the mode, inline data must be present in this + command. + + + +1 31:10 Reserved + Project: All + Format: MBZ + 9:0 Indirect IT-MV Data Length + Format: U10 FormatDesc: In bytes + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 162 + MFD_IT_OBJECT + + This field provides the length in bytes of the indirect data, which contains all the MVs for the current MB + (in any partitioning and subpartitioning form). A value zero indicates that indirect data fetching is + disabled – subsequently, the Indirect IT-MV Data Start Address field is ignored. This field must have + the same alignment as the Indirect Object Data Start Address.AVC-IT Mode: It must be DWord aligned + (since each MV is 4bytes in size)Driver has to derived this field from MVsize (MVquantity in DXVA, + exact size) *4 bytes per MV.This field is only valid in AVC decoder IT mode (VC1 and MPEG uses + inline MV data). + +2 31:29 Reserved + Project: All + Format: MBZ + 28:0 Indirect IT-MV Data Start Address Offset + This field specifies the memory starting address (offset) of the MV data to be fetched into the IT + pipeline for processing. This pointer is relative to the Indirect IT-MV Object Base Address.Hardware + ignores this field if indirect data is not present, i.e. the Indirect MV Data Length is set to 0. Alignment of + this address depends on the mode of operation.AVC-IT Mode: It must be DWord aligned (since each + MV is 4 bytes in size). This field is only valid in AVC decoder IT mode (VC1 and MPEG uses inline MV + data). + Value Name + [0,512MB) +3 31:12 Reserved + Project: All + Format: MBZ + 11:0 Indirect IT-COEFF Data Length + Project: All + This field provides the length in bytes of the indirect data, which contains all the non-zero coefficients + for the current MB. A value zero indicates that indirect data fetching is disabled – subsequently, the + Indirect IT-COEFF Data Start Address field is ignored. Since each IT-COEFF data is 1 DW in size, with + 12 bits, this field can be extended to support up to 4:4:4 format.(256 pixel * 3 byte pixel components * 4 + bytes per coeff).This field must be integer multiple of 16-bytes for AVC (since each coefficient is 4 bytes + in size).This field is only valid in AVC, VC1, MPEG2 decoder IT mode. + Value Name + [0,3072] In bytes [0, 256*3*4] +4 31:29 Reserved + Project: All + Format: MBZ + 28:0 Indirect IT-COEFF Data Start Address Offset + Project: All + This field specifies the memory starting address (offset) of the coeff data to be loaded into the IT + pipeline for processing. This pointer is relative to the Indirect IT-COEFF Object Base + Address.Hardware ignores this field if indirect IT-COEFF data is not present, i.e. the Indirect IT-COEFF + Data Length is set to 0.This field must be DW aligned, since each coeff icient is 4 bytes in size.Driver + will determine the Num of EOB 4x4/8x8 must match the block cbp flags, if not match, hardware cannot + hang – add error handling.This field is only valid in AVC, VC1, MPEG2 decoder IT mode. + Value Name + [0,512MB) +5 31:6 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 163 + MFD_IT_OBJECT + 5:0 Indirect IT-DBLK Control Data Length + Project: All + Format: U6 + This field provides the length in bytes of the indirect data, which contains all the deblocker control + information for the current MB (in 4x4 sub-block partitioning). A value zero indicates that indirect data + fetching is disabled – subsequently, the Indirect IT-DBLK Data Start Address field is ignored. This field + must have the same alignment as the Indirect IT-DBLK Data Start Address. It must be DWord aligned. + Each Deblock Control Data record is 48 bytes or 12 DWords in size.This field is only valid in AVC + decoder IT mode. + +6 31:29 Reserved + Format: MBZ + 28:0 Indirect IT-DBLK Control Data Start Address Offset + Format: IndirectObjectBaseAddress[28:0] + This field specifies the memory starting address (offset) of the Deblocker control data to be fetched into + the IT Pipeline for processing. This pointer is relative to the Indirect IT-DBLK Object Base Address. + Hardware ignores this field if indirect data is not present, ie. The indirect IT-DBLK Control Data Length + is set to 0. + It must be DWord aligned. Each Deblock Control Data record is 48 bytes or 12 DWords in size. + This field is only valid in AVC decoder IT mode. + Value Name + [0,512MB) +7..n 31:0 Inline Data + Union for all 3 codecs + + Includes IT, MC, IntraPred inline data as well as Deblocker control information + AVC-IT Modes: Hardware interprets this data in the specified format. + VC1-IT Modes: Hardware interprets this data in the specified format. MV inline + MPEG2-IT Modes: Hardware interprets this data in the specified format. (IS mode) MV inline + For AVC there 7 DWords of inline data, hence N is equal to 13. + + + +5.1.1.1 Common Indirect IT-COEFF Data Structure +Transform-domain residual data block in AVC-IT, VC1-IT and MPEG2-IT mode follows the same data +structure. +The indirect IT-COEFF data start address in MFD_IT_OBJECT command specifies the doubleword +aligned address of the first non-zero DCT coefficient of the first block of the macroblock. Only the non- +zero coefficients are present in the data buffer and they are packed in the 8x8 block sequence of Y0, Y1, +Y2, Y3, Cb4 and Cr5, as shown in Common Indirect IT COEFF Data Structure. When an 8x8 block is +further subdivided into 4x4 subblocks, the coefficients, if present, are organized in the subblock order. +The smallest subblock division is referred to as a transform block. The indirect IT-COEFF data length in +the command includes all the non-zero coefficients for the macroblock. It must be doubleword aligned. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 164 + Structure of the IDCT Compressed Data Buffer + + + + +Each non-zero coefficient in the indirect data buffer is contained in a doubleword-size data structure +consisting of the coefficient index, end of block (EOB) flag and the fixed-point coefficient value in 2’s +compliment form. As shown in Common Indirect IT COEFF Data Structure, index is the row major 'raster' +index of the coefficient within a transform block (please note that it is not converted to 8x8 block basis). +A coefficient is a 16-bit value in 2's complement. + +Structure of a transform-domain residue unit +DWord Bit Description + 0 31:16 + Transform-Domain Residual (coefficient) Value. This field contains the value of the non-zero + transform-domain residual data in 2’s compliment. + 15:7 Reserved: MBZ + 6:1 + Index. This field specifies the raster-scan address (raw address) of the coefficient within the transform + block. For a coefficient at Cartesian location (row, column) = (y, x) in a transform block of width W, + Index is equal to (y * W + x). For example, coefficient at location (row, column) = (0, 0) in a 4x4 + transform block has an index of 0; that at (2, 3) has an index of 2*4 + 3 = 11. + The valid range of this field depends on the size of the transform block. + Format = U6 + Range = [0, 63] + 0 + EOB (End of Block). This field indicates whether the transform-domain residue is the last one of the + current transform block. + + +Allowed transform block dimensions per coding standard +Transform Block Dimension AVC VC1 MPEG2 + 8x8 Yes Yes Yes + 8x4 No Yes No + 4x8 No Yes No + 4x4 Yes Yes No + +For AVC, there is intra16x16 mode, in which the DC Luma coefficients of all 4x4 sub-blocks within the +current MB are sent separately in its own 4x4 Luma block. As such, only 15 coefficients remains in each +of the 16 4x4 Luma blocks. + +5.1.1.2 Inline Data Description in AVC-IT Mode +The Inline Data includes all the required MB decoding states, extracted primarily from the Slice Data, MB +Header and their derivatives. It provides information for the following operations: + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 165 + 1. Inverse Quantization + 2. Inverse Transform + 3. Intra and inter-Prediction decoding operations + 4. Internal error handling +IT Mode supports only packed MV data as specified in the DXVA spec. +These state/parameter values may subject to change on a per-MB basis, and must be provided in each +MFD_IT_OBJECT command. The values set for these variables are retained internally, until they are +reset by hardware Asynchronous Reset or changed by the next MFC_AVC_PAK_OBJECT command. +The inline data has been designed to match the DXVA 2.0, with the exception of the starting byte +(DW0:0-7) and the ending dword (DW7:0-31). +The Deblocker Filter Control flags (FilterInternalEdgesFlag, FilterTopMbEdgeFlag and +FilterLeftMbEdgesFlag) are generated by H/W, which are depending on MbaffFrameFlag, CurrMbAddr, +PicWidthInMbs and disable_deblocking_filter_idc states. +Current MB [x,y] address is not sent, it is assumed that the H/W will keep track of the MB count and +current MB position internally. + DWord Bit Description + 0 31:24 + MvQuantity + Specify the number of MVs (in unit of motion + vector, 4 bytes each) to be fetched for motion + compensation operation. + Decoder IT mode only supports packed MV + format (DXVA). This field specifies the exact + number of MVs present for the current MB. + For a P-Skip MB, there is still 1 MV being sent + (Skip MV is sent explicitly); for a B-Direct/Skip + MB, there are 2 MVs being sent. + For an Intra-MB, MvQuantity is set to 0. + MvQuantity = 0, signifies there is no MV + indirect data for the current MB. + This field must be set in consistent with + Indirect MV Data Length, so as not to exceed + its bound + Unsigned. + + 23:20 Reserved MBZ (DXVA) + 19 + DcBlockCodedYFlag + 1 – the 4x4 DC-only Luma sub-block of the + Intra16x16 coded MB is present; it is still + possible that all DC coefficients are zero. + 0 – no 4x4 DC-only Luma sub-block is present; + either not in Intra16x16 MB mode or all DC + coefficients are zero. + 18 + DcBlockCodedCbFlag + For 4:2:0 case : + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 166 + DWord Bit Description + 1 – the 2x2 DC-only Chroma Cb sub-block of + all coded MB (any type) is present; it is still + possible that all DC coefficients are zero. + 0 – no 2x2 DC-only Chroma Cb sub-block is + present; all DC coefficients are zero. + 17 + DcBlockCodedCrFlag + For 4:2:0 case : + 1 – the 2x2 DC-only Chroma Cr sub-block of + all coded MB (any type) is present; it is still + possible that all DC coefficients are zero. + 0 – no 2x2 DC-only Chroma Cr sub-block is + present; all DC coefficients are zero. + 16 Reserved MBZ (DXVA) + 15 + Transform8x8Flag + 0: indicates the current MB is coded with 4x4 + transform and therefore the luma residuals are + presented in 4x4 blocks. + 1: indicates the current MB is coded with 8x8 + transform and therefore the luma residuals are + presented in 8x8 blocks. + Same as the transform_szie_8x8_flag syntax + element in AVC spec. + 14 + MbFieldFlag + This field specifies whether current macroblock + is coded as a field or frame macroblock in + MBAFF mode. + 1 = Field macroblock + 0 = Frame macroblock + This field is exactly the same as + FIELD_PIC_FLAG syntax element in non- + MBAFF mode. + Same as the mb_field_decoding_flag syntax + element in AVC spec. + 13 + IntraMbFlag + This field specifies whether the current + macroblock is an Intra (I) macroblock. + 0 – not an intra MB + 1 – is an intra MB + I_PCM is considered as Intra MB. + For I-picture MB (IntraPicFlag =1), this field + must set to 1. + This flag must be set in consistent with the + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 167 + DWord Bit Description + interpretation of MbType (inter or intra modes). + 12:8 + MbType + This field carries the Macroblock Type. The + meaning depends on IntraMbFlag. + If IntraMbFlag is 1, this field is the intra + macroblock type as defined in Macroblock + Type for Intra Cases. + If IntraMbFlag is 0, this field is the inter + macroblock type as defined in the first two + columns of Macroblock Type for Inter Cases. + All macroblock types in a P Slice are mapped + into the corresponding types in a B Slice. Skip + and Direct modes are converted into its + corresponding processing modes. + Programming note: It is exactly matched with + that of DXVA 2.0. + 7 + FieldMbPolarityFlag + This field indicates the field polarity of the + current macroblock. + Within a MbAff frame picture, this field may be + different per macroblock and is set to 1 only for + the second macroblock in a MbAff pair if + FieldMbFlag is set. Otherwise, it is set to 0. + Within a field picture, this field is set to 1 if the + current picture is the bottom field picture. + Otherwise, it is set to 0. It is a constant for the + whole field picture. + This field is only valid for MBAFF frame + picture. It is reserved and set to 0 for a + progressive frame picture or a field picture. + 0 = Current macroblock is a field macroblock + from the top field (first in a MBAFF pair) + 1 = Current macroblock is a field macroblock + from the bottom field (second in a MBAFF + pair) + 6 + IsLastMB + 1 – the current MB is the last MB in the current + Slice + 0 – the current MB is not the last MB in the + current Slice + 5-4 Reserved MBZ (Intel encoder) + 3:0 Reserved MBZ (DXVA Decoder) + 1 31:16 + CbpY[bit 15:0] (Coded Block Pattern Y) + For 4x4 sub-block (when Transform8x8flag = + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 168 + DWord Bit Description + 0 or in intra16x16) : + 16-bit cbp, one bit for each 4x4 Luma sub- + block (not including the DC 4x4 Luma block in + intra16x16) in a MB. The 4x4 Luma sub-blocks + are numbered as + blk0 1 4 5 bit15 14 + blk2 3 6 7 bit13 12 + blk8 9 12 13 bit7 6 + blk10 11 14 15 bit 5 4 + The cbpY bit assignment is cbpY bit [15 – X] + for sub-block_num X. + For 8x8 block (when Transform8x8flag = 1) + Only the lower 4 bits [3:0] are valid; the + remaining upper bits [15:4] are ignored. The + 8x8 Luma blocks are numbered as + + blk0 1 bit3 + blk2 3 bit1 + The cbpY bit assignment is cbpY bit [3 + – X] for block_num X. + 0 in a bit – indicates the corresponding 8x8 + block or 4x4 sub-block is not present (because + all coefficient values are zero) + 1 in a bit – indicates the corresponding 8x8 + block or 4x4 sub-block is present (although it is + still possible to have all its coefficients be zero + – bad coding). + + + 15:8 + VertOrigin (Vertical Origin). This field + specifies the vertical origin of current + macroblock in the destination picture in units of + macroblocks. + For field macroblock pair in MBAFF frame, the + vertical origins for both macroblocks should be + set as if they were located in corresponding + field pictures. For example, for field + macroblock pair originated at (16, 64) pixel + location in an MBAFF frame picture, the + Vertical Origin for both macroblocks should be + set as 2 (macroblocks). Whether the current + macroblock is the first/second (top/bottom) in a + MBAFF pair is specified by + FieldMbPolarityFlag. + The macroblocks with (VertOrigin, + HorzOrigin) must be delivered in the strict + order as coded in the bitstream (raster order + for progressive frame or field pictures and + MBAFF pair order for MBAFF pictures). No + gap is allowed. Otherwise, hardware behavior + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 169 + DWord Bit Description + is undefined. + Format = U8 in unit of macroblock. + 7:0 + HorzOrigin (Horizontal Origin). This field + specifies the horizontal origin of current + macroblock in the destination picture in units of + macroblocks. + Format = U8 in unit of macroblock. + + 2 31:16 + CbpCr (Coded Block Pattern Cr 4:2:0-only) + Only the lower 4 bits [3:0] are valid; the + remaining upper bits [15:4] are ignored (only + valid for 4:2:2 and 4:4:4). The 4x4 Chroma Cr + sub-blocks are numbered as + blk0 1 bit3 + blk2 3 bit1 + The cbpCr bit assignment is cbpCr bit [3 – X] + for sub-block_num X. + 0 in a bit – indicates the corresponding 4x4 + sub-block is not present (because all + coefficient values are zero) + 1 in a bit – indicates the corresponding 4x4 + sub-block is present (although it is still possible + to have all its coefficients be zero – bad + coding). + For monochrome, this field is ignored. + + + 15-0 + CbpCb (Coded Block Pattern Cb 4:2:0-only) + Only the lower 4 bits [3:0] are valid; the + remaining upper bits [15:4] are ignored (only + valid for 4:2:2 and 4:4:4). The 4x4 Chroma Cb + sub-blocks are numbered as + blk0 1 bit3 + blk2 3 bit1 + The cbpCb bit assignment is cbpCb bit [3 – X] + for sub-block_num X. + 0 in a bit – indicates the corresponding 4x4 + sub-block is not present (because all + coefficient values are zero) + 1 in a bit – indicates the corresponding 4x4 + sub-block is present (although it is still possible + to have all its coefficients be zero – bad + coding). + For monochrome, this field is ignored. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 170 + DWord Bit Description + 3 31:24 + Reserved MBz + + 23:16 + QpPrimeCr + Driver is responsible for deriving the + QpPrimeCr from QpPrimeY. + For 8-bit pixel data, QpCr is the same as + QpPrimeCr, and it takes on a value in the + range of 0 to 51, positive integer. + 15:8 + QpPrimeCb + Driver is responsible for deriving the + QpPrimeCb from QpPrimeY. + For 8-bit pixel data, QpCb is the same as + QpPrimeCb, and it takes on a value in the + range of 0 to 51, positive integer. + 7:0 + QpPrimeY + This is the per-MB QP value specified for the + current MB. + For 8-bit pixel data, QpY is the same as + QpPrimeY, and it takes on a value in the range + of 0 to 51, positive integer. + 4 to 6 + 31:0 For intra macroblocks, definition of these fields + are specified in Inline data subfields for an + Each + Intra Macroblock + For inter macroblocks, definition of these fields + are specified in Inline data subfields for an + Inter Macroblock + + +5.1.1.3 Indirect Data Format in AVC-IT Mode +Indirect data in AVC-IT mode consist of Motion Vectors, Transform-domain Residue (Coefficient) and +ILDB control data. All three data records have variable size. Size of each Motion Vector record is +determined by the MvQuantity value as shown in Indirect Data Format in AVC IT Mode. ILDB control +record is fixed at the same size for all MBs in a picture. Coefficient data record is variable size per MB, +since it may only consist of non-zero coefficients. +Each MV is represented in 4 bytes, in the form of + Lower 2 bytes : horizontal MVx component in q-pel units + Upper 2 bytes : vertical MVy component in q-pel units + Integer distance is measured in unit of samples in the frame or field grid position. + Chroma MVs are not sent and are derived in the H/W. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 171 + Indirect MV record size in AVC-IT mode + Macroblock Type MVQuant +BP_L0_16x16 1 + +B_L1_16x16 + 1 + +B_Bi_16x16 + 2 + +BP_L0_L0_16x8 2 + +BP_L0_L0_8x16 2 + +B_L1_L1_16x8 + 2 + +B_L1_L1_8x16 + 2 + +B_L0_L1_16x8 + 2 + +B_L0_L1_8x16 + 2 + +B_L1_L0_16x8 + 2 + +B_L1_L0_8x16 + 2 + +B_L0_Bi_16x8 3 + +B_L0_Bi_8x16 3 + +B_L1_Bi_16x8 3 + +B_L1_Bi_8x16 3 + +B_Bi_L0_16x8 + 3 + +B_Bi_L0_8x16 + 3 + +B_Bi_L1_16x8 + 3 + +B_Bi_L1_8x16 + 3 + +B_Bi_Bi_16x8 + 4 + +B_Bi_Bi_8x16 + 4 + +BP_8x8 Sum + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 172 + For macroblock type of BP_8x8, MvQuant takes the sum of value MvQ[i] of the four individual 8x8 sub +macroblocks. + +SubMbShape[i] SubMbPredMode[i] Description MvQ[i] + + 0 0 BP_L0_8x8 1 + 0 1 B_L1_8x8 1 + 0 2 B_BI_8x8 2 + 1 0 BP_L0_8x4 2 + 1 1 B_L1_8x4 2 + 1 2 B_BI_8x4 4 + 2 0 BP_L0_4x8 2 + 2 1 B_L1_4x8 2 + 2 2 B_BI_4x8 4 + 3 0 BP_L0_4x4 4 + 3 1 B_L1_4x4 4 + 3 2 B_BI_4x4 8 + +Indirect data Deblocking Filter Control block in AVC-IT mode: +AVC Deblocker Control Data record has a fixed size for each MB in a picture and is 48 bytes or 12 +Dwords in size. +DWord Bit Description + 0 31:24 Reserved : MBZ (DXVA Decoder) + 23 + FilterTopMbEdgeFlag + + 22 + FilterLeftMbEdgeFlag + + 21 + FilterInternal4x4EdgesFlag + + 20 + FilterInternal8x8EdgesFlag + + 19 + FieldModeAboveMbFlag + + 18 + FieldModeLeftMbFlag + + 17 + FieldModeCurrentMbFlag + + 16 + MbaffFrameFlag (DXVA Decoder reserved bit) + + 15:8 + VertOrigin Current MB y position (address) + + 7:0 + HorzOrigin Current MB x position (address) + + 1 31:30 + bS_h13 2-bit boundary strength for internal top horiz 4-pixel edge 3 + + 29:28 + bS_h12 2-bit boundary strength for internal top horiz 4-pixel edge 2 + + 27:26 + bS_h11 2-bit boundary strength for internal top horiz 4-pixel edge 1 + + 25:24 + bS_h10 2-bit boundary strength for internal top horiz 4-pixel edge 0 + + 23:22 + bS_v33 2-bit boundary strength for internal right vert 4-pixel edge 3 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 173 + DWord Bit Description + 21:20 + bS_v23 2-bit boundary strength for internal right vert 4-pixel edge 2 + + 19:18 + bS_v13 2-bit boundary strength for internal right vert 4-pixel edge 1 + + 17:16 + bS_v03 2-bit boundary strength for internal right vert 4-pixel edge 0 + + 15:14 + bS_v32 2-bit boundary strength for internal mid vert 4-pixel edge 3 + + 13:12 + bS_v22 2-bit boundary strength for internal mid vert 4-pixel edge 2 + + 11:10 + bS_v12 2-bit boundary strength for internal mid vert 4-pixel edge 1 + + 9:8 + bS_v02 2-bit boundary strength for internal mid vert 4-pixel edge 0 + + 7:6 + bS_v31 2-bit boundary strength for internal left vert 4-pixel edge 3 + + 5:4 + bS_v21 2-bit boundary strength for internal left vert 4-pixel edge 2 + + 3:2 + bS_v11 2-bit boundary strength for internal left vert 4-pixel edge 1 + + 1:0 + bS_v01 2-bit boundary strength for internal left vert 4-pixel edge 0 + + 2 31:28 + bS_v30_0 4-bit boundary strength for Left0 4-pixel edge 3 (MSbit is wasted) + + 17:24 + bS_v20_0 4-bit boundary strength for Left0 4-pixel edge 2 (MSbit is wasted) + + 23:20 + bS_v10_0 4-bit boundary strength for Left0 4-pixel edge 1 (MSbit is wasted) + + 19:16 + bS_v00_0 4-bit boundary strength for Left0 4-pixel edge 0 (MSbit is wasted) + + 15:14 + bS_h33 2-bit boundary strength for internal bot horiz 4-pixel edge 3 + + 13:12 + bS_h32 2-bit boundary strength for internal bot horiz 4-pixel edge 2 + + 11:10 + bS_h31 2-bit boundary strength for internal bot horiz 4-pixel edge 1 + + 9:8 + bS_h30 2-bit boundary strength for internal bot horiz 4-pixel edge 0 + + 7:6 + bS_h23 2-bit boundary strength for internal mid horiz 4-pixel edge 3 + + 5:4 + bS_h22 2-bit boundary strength for internal mid horiz 4-pixel edge 2 + + 3:2 + bS_h21 2-bit boundary strength for internal mid horiz 4-pixel edge 1 + + 1:0 + bS_h20 2-bit boundary strength for internal mid horiz 4-pixel edge 0 + + 3 31:28 + bS_h03_0 4-bit boundary strength for Top0 4-pixel edge 3 (MSbit is wasted) + + 27:24 + bS_h02_0 4-bit boundary strength for Top0 4-pixel edge 2 (MSbit is wasted) + + 23:20 + bS_h01_0 4-bit boundary strength for Top0 4-pixel edge 1 (MSbit is wasted) + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 174 + DWord Bit Description + 19:16 + bS_h00_0 4-bit boundary strength for Top0 4-pixel edge 0 (MSbit is wasted) + + 15:12 + bS_v03 4-bit boundary strength for Left1 4-pixel edge 3 (MSbit is wasted) + + 11:8 + bS_v02 4-bit boundary strength for Left1 4-pixel edge 2 (MSbit is wasted) + + 7:4 + bS_v01 4-bit boundary strength for Left1 4-pixel edge 1 (MSbit is wasted) + + 3:0 + bS_v00 4-bit boundary strength for Left1 4-pixel edge 0 (MSbit is wasted) + + 4 31:24 + bIndexBinternal_Y Internal index B for Y + + 23:16 + bIndexAinternal_Y Internal index A for Y + + 15:12 + bS_h03_1 4-bit boundary strength for Top1 4-pixel edge 3 (MSbit is wasted) + + 11:8 + bS_h02_1 4-bit boundary strength for Top1 4-pixel edge 2 (MSbit is wasted) + + 7:4 + bS_h01_1 4-bit boundary strength for Top1 4-pixel edge 1 (MSbit is wasted) + + 3:0 + bS_h00_1 4-bit boundary strength for Top1 4-pixel edge 0 (MSbit is wasted) + + 5 31:24 + bIndexBleft1_Y + + 23:16 + bIndexAleft1_Y + + 15:8 + bIndexBleft0_Y + + 7:0 + bIndexAleft0_Y + + 6 31:24 + bIndexBtop1_Y + + 23:16 + bIndexAtop1_Y + + 15:8 + bIndexBtop0_Y + + 7:0 + bIndexAtop0_Y + + 7 31:24 + bIndexBleft0_Cb + + 23:16 + bIndexAleft0_Cb + + 15:8 + bIndexBinternal_Cb + + 7:0 + bIndexAinternal_Cb + + 8 31:24 + bIndexBtop0_Cb + + 23:16 + bIndexAtop0_Cb + + 15:8 + bIndexBleft1_Cb + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 175 + DWord Bit Description + 7:0 + bIndexAleft1_Cb + + 9 31:24 + bIndexBinternal_Cr + + 23:16 + bIndexAinternal_Cr + + 15:8 + bIndexBtop1_Cb + + 7:0 + bIndexAtop1_Cb + + 10 31:24 + bIndexBleft1_Cr + + 23:16 + bIndexAleft1_Cr + + 15:8 + bIndexBleft0_Cr + + 7:0 + bIndexAleft0_Cr + + 11 31:24 + bIndexBtop1_Cr + + 23:16 + bIndexAtop1_Cr + + 15:8 + bIndexBtop0_Cr + + 7:0 + bIndexAtop0_Cr + + + +5.1.1.4 Inline Data Description in VC1-IT Mode +DWord Bit Description + +0 31:28 + MvFieldSelect. A bit-wise representation indicating which field in the reference frame is used as the + reference field for current field. It’s only used in decoding interlaced pictures. + This field is valid for non-intra macroblock only. + Bit Description + 28 Forward predict of current frame/field or TOP field of interlace frame, or block 0 in 4MV mode. + 29 Backward predict of current frame/field or TOP field of interlace frame, or forward predict for block + 1 in 4MV mode. + 30 Forward predict of BOTTOM field of interlace frame, or block 2 in 4MV mode. + 31 Backward predict of BOTTOM field of interlace frame, or forward predict for block 3 in 4MV mode. + Each corresponding bit has the following indication. + 0 = The prediction is taken from the top reference field. + 1 = The prediction is taken from the bottom reference field. + + + 27 + Reserved. MBZ + + 26 + MvFieldSelectChroma . This field specifies the polarity of reference field for chroma blocks when their + motion vector is derived in Motion4MV mode for interlaced (field) picture. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 176 + DWord Bit Description + Non-intra macroblock only. This field is derived from MvFieldSelect. + 0 = The prediction is taken from the top reference field. + 1 = The prediction is taken from the bottom reference field. + 25:24 + MotionType – Motion Type + For frame picture, a macroblock may only be either 00 or 10. + For interlace picture, a macroblock may be of any motion types. It can be 01 if and only if DctType is 1. + This field is 00 if and only if IntraMacroblock is 1. + 00 = Intra + 01 = Field Motion. + 10 = Frame Motion or no motion. + Others = Reserved. + 23 + Reserved. MBZ + + 22 + MvSwitch. This field specifies whether the prediction needs to be switched from forward to backward + or vice versa for single directional prediction for top and bottom fields of interlace frame B + macroblocks. + 0 = No directional prediction switch from top field to bottom field + 1 = Switch directional prediction from top field to bottom field + 21 + DctType. This field specifies whether the residual data is coded as field residual or frame residual for + interlaced picture. This field can be 1 only if MotionType is 00 (intra) or 01 (field motion). + For progressive picture, this field must be set to ‘0’, i.e. all macrobalcoks are frame macroblock. + 0 = Frame residual type. + 1 = Field residual type. + 20 + OverlapTransform. This field indicates whether overlap smoothing filter should be performed on I- + block boundaries. + 0 = No overlap smoothing filter. + 1 = Overlap smoothing filter performed. + 19 + Motion4MV. This field indicates whether current macroblock a progressive P picture uses 4 motion + vectors, one for each luminance block. + It’s only valid for progressive P-picture decoding. Otherwise, it is reserved and MBZ. For example, with + MotionForward is 0, this field must also be set to 0. + 0 = 1MV-mode. + 1 = 4MV-mode. + 18 + MotionBackward. This field specifies whether the backward motion vector is active for B-picture. This + field must be 0 if Motion4MV is 1 (no backward motion vector in 4MV-mode). + 0 = No backward motion vector. + 1 = Use backward motion vector(s). + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 177 + DWord Bit Description + 17 + MotionForward. This field specifies whether the forward motion vector is active for P and B pictures. + 0 = No forward motion vector. + 1 = Use forward motion vector(s). + 16 + IntraMacroblock. This field specifies if the current macroblock is intra-coded. When set, Coded Block + Pattern is ignored and no prediction is performed (i.e., no motion vectors are used). + For field motion, this field indicates whether the top field of the macroblock is coded as intra. + 0 = Non-intra macroblock. + 1 = Intra macroblock. + 15:12 + LumaIntra8x8Flag – Luma Intra 8x8 Flag + This field specifies whether each of the four 8x8 luminance blocks are intra or inter coded when + Motion4MV is set to 4MV-Mode. + Each bit corresponds to one block. “0” indicates the block is inter coded and ‘1’ indicates the block is + intra coded. + When Motion4MV is not 4MV-Mode, this field is reserved and MBZ. + Bit 15: Y0 + Bit 14: Y1 + Bit 13: Y2 + Bit 12: Y3 + 11:6 + CBP - Coded Block Pattern + This field specifies whether the 8x8 residue blocks in the macroblock are present or not. + Each bit corresponds to one block. “0” indicates residue block isn’t present, “1” indicates residue block + is present. + Note: For each block in an intra-coded macroblock or an intra-coded block in a P macroblock in 4MV- + Mode, the corresponding CBP must be 1. Subsequently, there must be at least one coefficient (this + coefficient might be zero) in the indirect data buffer associated with the bock (i.e. residue block must + be present). + Bit 11: Y0 + Bit 10: Y1 + Bit 9: Y2 + Bit 8: Y3 + Bit 7: Cb4 + Bit 6: Cr5 + 5 + ChromaIntraFlag - Derived Chroma Intra Flag + This field specifies whether the chroma blocks should be treated as intra blocks based on motion + vector derivation process in 4MV mode. + 0 = Chroma blocks are not coded as intra. + 1 = Chroma blocks are coded as intra + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 178 + DWord Bit Description + 4 + LastRowFlag – Last Row Flag + This field indicates that the current macroblock belongs to the last row of the picture. + This field may be used by the kernel to manage pixel output when overlap transform is on. + 0 = Not in the last row + 1 = In the last row + 3 + LastMBInRow – This field indicates the last MB in row flag. + + 2:0 + Reserved. MBZ + + +1 32:26 + Reserved. MBZ + + 15:8 + VertOrigin - Vertical Origin + In unit of macroblocks relative to the current picture (frame or field). + 7:0 + HorzOrigin - Horizontal Origin + In unit of macroblocks. + + +2 31:16 + MotionVector[0].Vert + + 15:0 + MotionVector[0].Horz + + +3 31:0 + MotionVector[1] + + +4 31:0 + MotionVector[2] + + +5 31:0 + MotionVector[3] + + +6 31:0 + MotionVectorChroma + This field is not valid for a field motion in an interlaced frame picture where 4 MVs for chroma blocks. + Notes: This field is derived from MotionVector[3:0] as described in the following section. + +7 31:24 + Subblock Code for Y3 + The following subblock coding definition applies to all 6 subblock coding bytes. Bits 7:6 are reserved. + + Subblock Partitioning Subblock Present + (Bits [1:0]) (0 means not present, 1 means present) + Specify Transform uses for an 8x8 + block + + Bits + [1:0] + Meaning Bit 2 Bit 3 Bit 4 Bit 5 + 00 Single 8x8 block (sb0) Sb0 Don’t care Don’t care Don’t care + 01 Two 8x4 subblocks (sb0-1) Sb1 (bot) Sb0 (top) Don’t care Don’t care + 10 Two 4x8 subblocks (sb0-1) Sb1 (right) Sb0 (left) Don’t care Don’t care + 11 Four 4x4 subblocks (sb0-3) Sb3 (lower Sb2 (lower Sb1 (upper Sb0 (upper + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 179 + DWord Bit Description + right) left) right) left) + 23:16 + Subblock Code for Y2 + + 15:8 + Subblock Code for Y1 + + 7:0 + Subblock Code for Y0 + + +8 31:16 + Reserved. MBZ + + 15:8 + Subblock Code for Cr + + 7:0 + Subblock Code for Cb + + +9 31:24 + ILDB control data for block Y3 + + 23:16 + ILDB control data for block Y2 + + 15:8 + ILDB control data for block Y1 + + 7:0 + ILDB control data for block Y0 + + +10 31:16 + Reserved + + 15:8 + ILDB control data for Cr block + + 7:0 + ILDB control data for Cb block + + + +5.1.1.5 Indirect Data Format in VC1-IT Mode +VC1-IT mode only contains IT-COEFF indirect data which is described in Common Indirect IT COEFF +Data Structure. + +5.1.1.6 Inline Data Description in MPEG2-IT Mode +The content in this command is similar to that in the MEDIA_OBJECT command in IS mode described in +the Media Chapter. +Each MFD_IT_OBJECT command corresponds to the processing of one macroblock. Macroblock +parameters are passed in as inline data and the non-zero DCT coefficient data for the macroblock is +passed in as indirect data. +Inline Data Description in MPEG2 IT Mode depicts the inline data format. Inline data starts at dword 7 of +MFD_IT_OBJECT command. There are 7 dwords total. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 180 + Inline data in MPEG2-IT Mode +DWord Bit Description + +0 31:28 + Motion Vertical Field Select. A bit-wise representation of a long [2][2] array as defined in §6.3.17.2 of + the ISO/IEC 13818-2 (see also §7.6.4). + Bit MVector[r] MVector[s] MotionVerticalFieldSelect Index + 28 0 0 0 + 29 0 1 1 + 30 1 0 2 + 31 1 1 3 + Format = MC_MotionVerticalFieldSelect. + 0 = The prediction is taken from the top reference field. + 1 = The prediction is taken from the bottom reference field. + + + 27 Reserved (was Second Field) + 26 Reserved. (HWMC mode) + 25:24 + Motion Type. When combined with the destination picture type (field or frame) this Motion Type field + indicates the type of motion to be applied to the macroblock. See ISO/IEC 13818-2 §6.3.17.1, Tables + 6-17, 6-18. In particular, the device supports dual-prime motion prediction (11) in both frame and field + picture type. + Format = MC_MotionType + + Destination = Frame Destination = Field + Picture_Structure = 11 Picture_Structure != 11 + Value + ‘00’ Reserved Reserved + ‘01’ Field Field + ‘10’ Frame 16x8 + ‘11’ Dual-Prime Dual-Prime + 23:22 Reserved. (Scan method) + 21 + DCT Type. This field specifies the DCT type of the current macroblock. The kernel should ignore this + field when processing Cb/Cr data. See ISO/IEC 13818-2 §6.3.17.1. This field is zero if Coded Block + Pattern is also zero (no coded blocks present). + 0 = MC_FRAME_DCT (Macroblock is frame DCT coded). + 1 = MC_FIELD_DCT (Macroblock is field DCT coded). + 20 Reserved (was Overlap Transform - H261 Loop Filter). + 19 + Reserved (was 4MV Mode - H263/) + + 18 + Macroblock Motion Backward. This field specifies if the backward motion vector is active. See + ISO/IEC 13818-2 Tables B-2 through B-4. + 0 = No backward motion vector. + 1 = Use backward motion vector(s). + 17 + Macroblock Motion Forward. This field specifies if the forward motion vector is active. See ISO/IEC + 13818-2 Tables B-2 through B-4. + 0 = No forward motion vector. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 181 + DWord Bit Description + 1 = Use forward motion vector(s). + 16 + Macroblock Intra Type. This field specifies if the current macroblock is intra-coded. When set, Coded + Block Pattern is ignored and no prediction is performed (i.e., no motion vectors are used). See + ISO/IEC 13818-2 Tables B-2 through B-4. + 0 = Non-intra macroblock. + 1 = Intra macroblock. + 15:12 + Reserved : MBZ + + 11:6 + Coded Block Pattern. This field specifies whether blocks are present or not. + Format = 6-bit mask. + Bit 11: Y0 + Bit 10: Y1 + Bit 9: Y2 + Bit 8: Y3 + Bit 7: Cb4 + Bit 6: Cr5 + 5:4 Reserved. (Quantization Scale Code) + 3 LastMBInRow – This field indicates the last MB in each row. + 2:0 Reserved: MBZ + +1 31:16 + Reserved : MBZ + + 15:8 + VertOrigin - Vertical Origin + In unit of macroblocks relative to the current picture (frame or field). + + 7:0 + HorzOrigin - Horizontal Origin + In unit of macroblocks. + +2 31:16 + Motion Vectors – Field 0, Forward, Vertical Component. Each vector component is a 16-bit two’s- + complement value. The vector is relative to the current macroblock location. According to ISO/IEC + 13818-2 Table 8, the valid range of each vector component is [-2048, +2047.5], implying a format of + s11.1. However, it should be noted that motion vector values are sign extended to 16 bits. + 15:0 + Motion Vectors – Field 0, Forward, Horizontal Component + + +3 31:16 + Motion Vectors – Field 0, Backward, Vertical Component + + 15:0 + Motion Vectors – Field 0, Backward, Horizontal Component + + +4 31:16 + Motion Vectors – Field 1, Forward, Vertical Component + + 15:0 + Motion Vectors – Field 1, Forward, Horizontal Component + + +5 31:16 + Motion Vectors – Field 1, Backward, Vertical Component + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 182 + DWord Bit Description + 15:0 + Motion Vectors – Field 1, Backward, Horizontal Component + + + +5.1.1.7 Indirect Data Format in MPEG2-IT Mode +MPEG2-IT mode only contains IT-COEFF indirect data which is described in Section Common Indirect IT +COEFF Data Structure. + + + + +5.2 Session Decoder StreamOut Data Structure +When StreamOut is enabled, per MB intermediated decoded data (MVs, mb_type, MB qp, etc.) are sent +to the memory in a fixed record format (and of fixed size). The per-MB records must be written in a strict +raster order and with no gap (i.e. every MB regardless of its mb_type and slice type, must have an entry +in the StreamOut buffer). Therefore, the consumer of the StreamOut data can offset into the StreamOut +Buffer (StreamOut Data Destination Base Address) using individual MB addresses. +A StreamOut Data record format is detailed as follows: +DWord Bit Description + 0 31:24 Format: U5, valid from 0 to 32 + + 23 + Reserved MBZ + + 22-20 + EdgeFilterFlag (AVC) / OverlapSmoothFilter (VC1) + + 19:17 + CodedPatternDC (for AVC only, 111b for others) + The field indicates whether DC coefficients are sent.. + 1 bit each for Y, U and V. + 16 + Reserved MBZ + + 15 + Transform8x8Flag + When it is set to 0, the current MB uses 4x4 transform. When it is set to 1, the current MB uses 8x8 + transform. The transform_szie_8x8_flag syntax element, if present in the output bitstream, is the + same as this field. However, whether transform_szie_8x8_flag is present or not in the output + bitstream depends on several conditions: + This field is only allowed to be set to 1 for two conditions: + It must be 1 if IntraMbFlag = INTRA and IntraMbMode = INTRA_8x8 + It may be 1 if IntraMbFlag = INTER and there is no sub partition size less than 8x8 + + Otherwise, this field must be set to 0. + 0: 4x4 integer transform + 1: 8x8 integer transform + + 14 + MbFieldFlag + This field specifies whether current macroblock is coded as a field or frame macroblock in MBAFF + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 183 + DWord Bit Description + mode. + This field is exactly the same as FIELD_PIC_FLAG syntax element in non-MBAFF mode. + Same as the mb_field_decoding_flag syntax element in AVC spec. + 0 = Frame macroblock + 1 = Field macroblock + 13 + IntraMbFlag + This field specifies whether the current macroblock is an Intra (I) macroblock. + I_PCM is considered as Intra MB. + For I-picture MB (IntraPicFlag =1), this field must be set to 1. + This flag must be set in consistent with the interpretation of MbType (inter or intra modes). + 0: INTER (inter macroblock) + 1: INTRA (intra macroblock) + + 12:8 + MbType5Bits + This field is encoded to match with the best macroblock mode determined as described in the next + section. It follows AVC encoding for inter and intra macroblocks. + 7 + MbPolarity FieldMB Polarity - vctrl_vld_top_field AVC + + 6 + Reserved MBZ + + 5:4 IntraMbMode + This field is provided to carry information partially overlapped with MbType. + This field is only valid if IntraMbFlag = INTRA, otherwise, it is ignored by hardware.. + + 3 + Reserved MBZ + + 2 MbSkipFlag + Reserved MBZ (DXVA Encoder). HW (VDSunit) doesn’t have skip MB info. + It sets to 1 if any of the sub-blocks is inter, uses predicted MVs, and skips sending MVs explicitly in + the code stream. Currently H/W can provide this flag and is defaulted to 0 always. + 1:0 + InterMbMode + This field is provided to carry redundant information as that in MbType. It also carries additional + information such as skip. + This field is only valid if IntraMbFlag =INTER, otherwise, it is ignored by hardware. + + 1 31:16 + MbYCnt (Vertical Origin). This field specifies the vertical origin of current macroblock in the + destination picture in units of macroblocks. + Format = U8 in unit of macroblock. + 15:0 + MbXCnt (Horizontal Origin). This field specifies the horizontal origin of current macroblock in the + destination picture in units of macroblocks. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 184 + DWord Bit Description + Format = U8 in unit of macroblock. + 31 + 2 Conceal MB Flag. This field specifies if the current MB is a conceal MB, use in AVC/VC1/MPEG2 + mode + + 30 + Last MB of the Slice Flag. This field indicate the current MB is a last MB of the slice. Use in + AVC/VC1/MPEG2 mode. + 29:24 + Reserved + + 23:20 + CbpAcV + 0 in a bit – indicates the corresponding 8x8 block or 4x4 sub-block is not present (because all + coefficient values are zero) + 1 in a bit – indicates the corresponding 8x8 block or 4x4 sub-block is present (although it is still + possible to have all its coefficients be zero – bad coding). + 19:16 + CbpAcU + 0 in a bit – indicates the corresponding 8x8 block or 4x4 sub-block is not present (because all + coefficient values are zero) + 1 in a bit – indicates the corresponding 8x8 block or 4x4 sub-block is present (although it is still + possible to have all its coefficients be zero – bad coding). + + 15:0 + CbpAcY + 0 in a bit – indicates the corresponding 8x8 block or 4x4 sub-block is not present (because all + coefficient values are zero) + 1 in a bit – indicates the corresponding 8x8 block or 4x4 sub-block is present (although it is still + possible to have all its coefficients be zero – bad coding). + Bit15=Y0Sub0, Bit0=Y3Sub3 + 3 + 31:28 Skip8x8Pattern (AVC) + AVC This field indicates whether each of the four 8x8 sub macroblocks is using the predicted MVs and + will not be explicitly coded in the bitstream (the sub macroblock will be coded as direct mode). It + contains four 1-bit subfields, corresponding to the 4 sub macroblocks in sequential order. The whole + macroblock may be actually coded as B_Direct_16x16 or B_Skip, according to the macroblock type + conversion rules described in a later sub section. + This field is only valid for a B slice. It is ignored by hardware for a P slice. Hardware also ignores this + field for an intra macroblock. + 0 in a bit – Corresponding MVs are sent in the bitstream + 1 in a bit – Corresponding MVs are not sent in the bitstream + 27:25 + Reserved + + 24:16 + NzCoefCountMB + – all coded coefficients input including AC/DC blocks in current MB. + Range 0 to 384 (9 bits) + 15:8 + [IVB+] MbClock16 – MB compute clocks in 16-clock unit. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 185 + DWord Bit Description + 7 + mbz (AVC) / QScaleType (MPEG2) + + 6:0 + QpPrimeY (AVC) / QScaleCode (MPEG2) + The luma quantization index. This is the per-MB QP value specified for the current MB. + + 4 to 6 31:0 + For intra macroblocks, definition of these fields are specified in 1 + Each + For inter macroblocks, definition of these fields are specified in 2 + 31:24 + 7 Reserved + + 23:20 + MvFieldSelect (Ref polarity top or bottom bits) for VC1 and MPEG2 + vcp_vds_mvdataR[162:159] VC1 + vmd_vds_mt_vert_fld_selR[3:0] MPEG2 + 19:12 + Reserved + + 11:10 + SubBlockCodeType V (If 8x8, 8x4, 4x8, 4x4 type) + + 9:8 + SubBlockCodeType U (specifies 8x8, 8x4, 4x8, 4x4 type) VC1 + + 7:6 + SubBlockCodeType Y3 (specifies 8x8, 8x4, 4x8, 4x4 type) VC1 + + 5:4 + SubBlockCodeType Y2 (specifies 8x8, 8x4, 4x8, 4x4 type) VC1 + + 3:2 + SubBlockCodeType Y1 (specifies 8x8, 8x4, 4x8, 4x4 type) VC1 + + 1:0 + SubBlockCodeType Y0 (specifies 8x8, 8x4, 4x8, 4x4 type) VC1 + + Inter +cases + 8 31:16 + MvFwd[0].y – y-component of the forward motion vector of the 1st 8x8 or 1st 4x4 subblock + + 15:0 + MvFwd[0].x – x-component of the forward motion vector of the 1st 8x8 or 1st 4x4 subblock + + 9 31:0 + MvBck[0] – the backward motion vector of the 1st 8x8 or 1st 4x4 subblock + + 10 31:0 + MvFwd[1] – the forward motion vector of the 2nd 8x8 or 4th 4x4 subblock + + 11 31:0 + MvBck[1] – the backward motion vector of the 2nd 8x8 or 4th 4x4 subblock + + 12 31:0 + MvFwd[2] – the forward motion vector of the 3rd 8x8 or 8th 4x4 subblock + + 13 31:0 + MvBck[2] – the backward motion vector of the 3rd 8x8 or 8th 4x4 subblock + + 14 31:0 + MvFwd[3] – the forward motion vector of the 4th 8x8 or 12th 4x4 subblock + + 15 31:0 + MvBck[3] – the backward motion vector of the 4th 8x8 or 12th 4x4 subblock + + Intra +Cases : + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 186 + DWord Bit Description +8 to 15 31:0 + Reserved MBZ + +The inline data content of Dwords 4 to 6 is defined either for intra prediction or for inter prediction, but not +both. + +Inline data subfields for an Intra Macroblock + 31:16 + 4 LumaIndraPredModes[1] + Specifies the Luma Intra Prediction mode for four 4x4 sub-block of a MB, 4-bit each. + AVC : See the bit assignment table later in this section. + VC1 : MBZ. + MPEG2 : MBZ. + 15:0 + LumaIndraPredModes[0] + Specifies the Luma Intra Prediction mode for four 4x4 sub-block, four 8x8 block or one intra16x16 of a + MB. + 4-bit per 4x4 sub-block (Transform8x8Flag=0, Mbtype=0 and intraMbFlag=1) or 8x8 block + (Transform8x8Flag=1, Mbtype=0, MbFlag=1), since there are 9 intra modes. + 4-bit for intra16x16 MB (Transform8x8Flag=0, Mbtype=1 to 24 and intraMbFlag=1), but only the + LSBit[1:0] is valid, since there are only 4 intra modes. + AVC : See the bit assignment table later in this section. + VC1 : MBZ. + MPEG2 : MBZ. + 31:16 + 5 LumaIndraPredModes[3] + AVC Specifies the Luma Intra Prediction mode for four 4x4 sub-block of a MB, 4-bit each. +INTRA + AVC : See the bit assignment table later in this section. + VC1 : MBZ. + MPEG2 : MBZ. + 15:0 + LumaIndraPredModes[2] + Specifies the Luma Intra Prediction mode for four 4x4 sub-block of a MB, 4-bit each. + AVC : See the bit assignment later in this section. + VC1 : MBZ. + MPEG2 : MBZ. + 31:8 + 6 Reserved (Reserved for encocder turbo mode IntraResidueDataSize, when this is not 0, optional + residue data are provided to the PAK; Reserved for decoder) + 7:0 + MbIntraStruct + The IntraPredAvailFlags[4:0] have already included the effect of the constrained_intra_pred_flag. See + the diagram later for the definition of neighbors position around the current MB or MB pair (in MBAFF + mode). + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 187 + 1 – IntraPredAvailFlagX, indicates the values of samples of neighbor X can be used in intra prediction + for the current MB. + 0 – IntraPredAvailFlagX, indicates the values of samples of neighbor X is not available for intra + prediction of the current MB. + IntraPredAvailFlag-A and -E can only be different from each other when constrained_intra_pred_flag + is equal to 1 and mb_field_decoding_flag is equal to 1 and the value of the mb_field_decoding_flag for + the macroblock pair to the left of the current macroblock is equal to 0 (which can only occur when + MbaffFrameFlag is equal to 1). + IntraPredAvailFlag-F is used only if + o it is in MBAFF mode, i.e. MbaffFrameFlag = 1, + o the current macroblock is of frame type, i.e. MbFieldFag = 0, and + o the current macroblock type is Intra8x8, i.e. IntraMbFlag = INTRA, IntraMbMode = + INTRA_8x8, and Transform8x8Flag = 1. + + In any other cases IntraPredAvailFlag-A shall be used instead. + Bits IntraPredAvailFlags[4:0] Definition + 7 + IntraPredAvailFlagF – F (Left 8th row (-1,7) neighbor) + + 6 + IntraPredAvailFlagA – A (Left neighbor top half) + + 5 + IntraPredAvailFlagE – E (Left neighbor bottom half) + + 4 + IntraPredAvailFlagB – B (Top neighbor) + + 3 + IntraPredAvailFlagC – C (Top right neighbor) + + 2 + IntraPredAvailFlagD – D (Top left corner neighbor) + + 1:0 + ChromaIntraPredMode – 2 bits to specify 1 of 4 chroma intra prediction mode, see the table in + later section. + + +Inline data subfields for an Inter Macroblock + 31:24 Reserved: MBZ (DXVA Decoder) + 4 + Reserved: MBZ (DXVA Decoder) + 23:16 + 15:8 + SubMbPredModes[bit 7:0] (Sub Macroblock Prediction Mode) + This field describes the prediction mode of the sub macroblocks (four 8x8 blocks). It + contains four subfields each with 2-bits, corresponding to the 4 fixed size 8x8 sub + macroblocks in sequential order. + This field is provided for MB with sub_mb_type equal to BP_8x8 only (B_8x8 and P_8x8 as + defined in DXVA) + This field is derived from MbType for a non-BP_8x8 inter macroblock, and carries redundant + information as MbType) + Bits [1:0]: SubMbPredMode[0] – for 8x8 Block 0 + Bits [3:2]: SubMbPredMode[1] – for 8x8 Block 1 + Bits [5:4]: SubMbPredMode[2] – for 8x8 Block 2 + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 188 + Bits [7:6]: SubMbPredMode[3] – for 8x8 Block 3 + Blocks of the MB is numbered as follows : + 01 + 23 + Each 2-bit value [1:0] is defined as : + 00 – Pred_L0 + 01 – Pred_L1 + 10 – BiPred + For VC1: + Bits [1:0]: “00”= Y0 Forward only, “01”= Y0 Backward only, “10”= Y0 Bi direction + Bits [3:2]: SubMbPredMode[1] – for 8x8 Block 1 + Bits [5:4]: SubMbPredMode[2] – for 8x8 Block 2 + Bits [7:6]: SubMbPredMode[3] – for 8x8 Block 3 + 7:0 + SubMbShape[bit 7:0] (Sub Macroblock Shape) + This field describes the sub-block partitioning of each sub macroblocks (four 8x8 blocks). It + contains four subfields each with 2-bits, corresponding to the 4 fixed size 8x8 sub + macroblocks in sequential order. + This field is provided for MB with sub_mb_type equal to BP_8x8 only (B_8x8 and P_8x8 as + defined in DXVA) + This field is forced to 0 for a non-BP_8x8 inter macroblock, and effectively carries redundant + information as MbType). ??? + Bits [1:0]: SubMbShape[0] – for 8x8 Block 0 + Bits [3:2]: SubMbShape[1] – for 8x8 Block 1 + Bits [5:4]: SubMbShape[2] – for 8x8 Block 2 + Bits [7:6]: SubMbShape[3] – for 8x8 Block 3 + Blocks of the MB is numbered as follows : + 01 + 23 + Each 2-bit value [1:0] is defined as : + 00 – SubMbPartWidth=8, SubMbPartHeight=8 + 01 – SubMbPartWidth=8, SubMbPartHeight=4 + 10 – SubMbPartWidth=4, SubMbPartHeight=8 + 11 – SubMbPartWidth=4, SubMbPartHeight=4 + For VC-1, This field indicates the transformation types used for luma components, 2 bits for + each 8x8. + 31:24 + 5 Frame Store ID L0[3] + Support up to 4 Frame store ID per L0 direction, one per MB partition, if exists. See details + in later section. This field specifies the frame Store ID into the Reference Picture List0 + Table. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 189 + Bit 7: Must Be One: (This is reserved for control fields in future extension, when reference + index are generated instead of frame store ID) + 1: indicate it is in Frame store ID format. + 0: indicate it is in Reference Index format. + Bit 6:5: reserved MBZ + Bit 4:0 : Frame store index or Frame Store ID (Bit 4:1 is used to form the binding table index + in intel implementation) + 23:16 + Frame Store ID L0[2] + Support up to 4 Frame store ID per L0 direction, one per MB partition, if exists. See details + in later section. This field specifies the frame Store ID into the Reference Picture List0 + Table. + Bit 7: Must Be One: (This is reserved for control fields in future extension, when reference + index are generated instead of frame store ID) + 1: indicate it is in Frame store ID format. + 0: indicate it is in Reference Index format. + Bit 6:5: reserved MBZ + Bit 4:0 : Frame store index or Frame Store ID (Bit 4:1 is used to form the binding table index + in intel implementation) + 15:8 + Frame Store ID L0[1] + Support up to 4 Frame store ID per L0 direction, one per MB partition, if exists. See details + in later section. This field specifies the frame Store ID into the Reference Picture List0 + Table. + Bit 7: Must Be One: (This is reserved for control fields in future extension, when reference + index are generated instead of frame store ID) + 1: indicate it is in Frame store ID format. + 0: indicate it is in Reference Index format. + Bit 6:5: reserved MBZ + Bit 4:0 : Frame store index or Frame Store ID (Bit 4:1 is used to form the binding table index + in intel implementation). + + 7:0 + Frame Store ID L0[0] + Support up to 4 Frame store ID per L0 direction, one per MB partition, if exists. See details + in later section. This field specifies the frame Store ID into the Reference Picture List0 + Table. + Bit 7: Must Be One: (This is reserved for control fields in future extension, when reference + index are generated instead of frame store ID) + 1: indicate it is in Frame store ID format. + 0: indicate it is in Reference Index format. + Bit 6:5: reserved MBZ + Bit 4:0 : Frame store index or Frame Store ID (Bit 4:1 is used to form the binding table index + in intel implementation) + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 190 + 31:24 + 6 Frame Store ID L1[3] + Support up to 4 Frame store ID per L0 direction, one per MB partition, if exists. See details + in later section. This field specifies the frame Store ID into the Reference Picture List0 + Table. + Bit 7: Must Be One: (This is reserved for control fields in future extension, when reference + index are generated instead of frame store ID) + 1: indicate it is in Frame store ID format. + 0: indicate it is in Reference Index format. + Bit 6:5: reserved MBZ + Bit 4:0 : Frame store index or Frame Store ID (Bit 4:1 is used to form the binding table index + in intel implementation) + 23:16 + Frame Store ID L1[2] + Support up to 4 Frame store ID per L0 direction, one per MB partition, if exists. See details + in later section. This field specifies the frame Store ID into the Reference Picture List0 + Table. + Bit 7: Must Be One: (This is reserved for control fields in future extension, when reference + index are generated instead of frame store ID) + 1: indicate it is in Frame store ID format. + 0: indicate it is in Reference Index format. + Bit 6:5: reserved MBZ + Bit 4:0 : Frame store index or Frame Store ID (Bit 4:1 is used to form the binding table index + in intel implementation) + 15:8 + Frame Store ID L1[1] + Support up to 4 Frame store ID per L0 direction, one per MB partition, if exists. See details + in later section. This field specifies the frame Store ID into the Reference Picture List0 + Table. + Bit 7: Must Be One: (This is reserved for control fields in future extension, when reference + index are generated instead of frame store ID) + 1: indicate it is in Frame store ID format. + 0: indicate it is in Reference Index format. + Bit 6:5: reserved MBZ + Bit 4:0 : Frame store index or Frame Store ID (Bit 4:1 is used to form the binding table index + in intel implementation) + + 7:0 + Frame Store ID L1[0] + Support up to 4 Frame store ID per L0 direction, one per MB partition, if exists. See details + in later section. This field specifies the frame Store ID into the Reference Picture List0 + Table. + Bit 7: Must Be One: (This is reserved for control fields in future extension, when reference + index are generated instead of frame store ID) + 1: indicate it is in Frame store ID format. + 0: indicate it is in Reference Index format. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 191 + Bit 6:5: reserved MBZ + Bit 4:0 : Frame store index or Frame Store ID (Bit 4:1 is used to form the binding table index + in intel implementation) + + + +5.3 Decoder Input Bitstream Formats + +5.3.1 AVC Bitstream Formats – DXVA Short +Bitstream Buffer Address starts after the 3-byte start code, i.e. starts (and includes) at the NAL Header +Byte. This byte must not be included in the Emulation Byte Detection Process. + + +5.3.2 AVC Bitstream Formats – DXVA Long +Bitstream Buffer Address starts after the 3-byte start code, i.e. starts (and includes) at the NAL Header +Byte. This byte must not be included in the Emulation Byte Detection Process. Application will provide the +Slice Header Skip Byte count (not including any possible Emulation Prevention Byte). + + +5.3.3 AVC Bitstream Formats – Intel Long +Obsolete – not supported. + + +5.3.4 VC1 Bitstream Formats – Intel Long +Bitstream starts right at the MB layer, with any emulation byte crossing the header and MB layer being +removed by application and the data length is adjusted. + + +5.3.5 MPEG2 Bitstream Formats – DXVA1 +Bitstream buffer starts right at the very first MB data. + + +5.3.6 JPEG Bitstream Formats – Intel +Bitstream buffer starts right at the very first MCU data of each Scan. +The indirect data start address in MFD_JPEG_BSD_OBJECT specifies the starting Graphics Memory +address of the bitstream data that follows the Scan header. It provides the byte address for the first MCU +of the Scan. Different from MFD_MPEG2_BSD_OBJECT command, First MCU Bit Offset does not need +to be specified because it is always set to zero. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 192 + Indirect data buffer for a Scan + + +The indirect data length in MFD_JPEG_BSD_OBJECT provides the length in bytes of the bitstream data +for the Scan excluding Scan header. It includes the first byte of the first macroblock and the last byte of +the last macroblock in the Scan. The Figure illustrates these parameters for a slice data. + + +5.4 Concurrent, Multiple Video Stream Decoding Support +The natural place for switching across multiple streams is at the Slice boundary. Each Slice is a self- +sustained unit of compressed video data and has no dependency with its neighbors (except for the +Deblocking process). In addition, there is no interruptability within a Slice. However, when ILDB is +invoked, the processing of some MBs will require neighbour MB information that crosses the Slice +boundary. Hence, to limit the buffering requirement, in this version of hardware design, stream switching +can only be performed at the picture boundary instead. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 193 + 6. Encoder StreamOut Mode Data + Structure Definition +When StreamOut is enabled, per MB (and/or per Slice, per Picture) intermediated coding data (e.g. bit +allocated for each MB, etc.) are sent to the memory in a fixed record format (and of fixed size) from the +PAK. The per-MB records must be written in a strict raster order and with no gap (i.e. every MB +regardless of its mb_type and slice type, must have an entry in the StreamOut buffer). Therefore, the +consumer of the StreamOut data can offset into the StreamOut Buffer (StreamOut Data Destination +Base Address) using individual MB addresses. +Adding per macroblock stream out for PAK is for the following purposes: + + • Immediate multi-pass PAK (without host or EU intervention) + o 3200-bit conformance + o Re-quantization + + • Providing information for host for offline processing + • Providing information for updated QP’s + +The description for the fixed format PAK streamout record : +Streamout Pointer: Use the existing streamout pointer and enabler +Per Macroblock Information (a fixed size structure) +DWord Bit Description + 0 31:24 + MbQpY - Actual QPY used by the macroblock. + + 23:16 + [IVB+] MbClock16 – MB compute clocks in 16-clock unit. + + 15:8 Reserved : MBZ + 7:4 + Reserved : MBZ (future conformance flags) + + 3 + Reserved + + 2 + MbRcFlag: MB level Rate control flag(pass through)The same value as + RateControlCounterEnable of MFX_AVC_SLICE_STATE Command + + 1 + MbInterConfFlag: MB level InterMB conformance flag to trigger mutli-pass1- if total Bit Count of an + inter macroblock is more than Inter Conformance Max size limit in the MFX_AVC_IMG_STATE + Command + 0 + MbIntraConfFlag: MB level IntraMB conformance flag to trigger mutli-pass1- if total Bit Count of an + intra macroblock is more than Intra Conformance Max size limit in the MFX_AVC_IMG_STATE + Command + 1 31:29 + Reserved + + 28:16 + MbBits : Total Bit Count for the macroblock + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 194 + DWord Bit Description + 15:12 + Reserved + + 12:0 + MbHdrBits : Header Bit count (bit count due to Pre-coefficient data) for the macroblock + + 2 31:27 + Reserved + + 26:0 + Cbp: Coded Block Pattern of sub-blocks + + 3 31:30 + Reserved + + 29 + IntraMBFlag + + 28:24 + MBType5Bits + + 23:17 + Reserved + + 16 + ClampFlag: Coefficient clamping flag for RC (Status) + 1 - Indicates if clamping of any coefficient is done on the macroblock for Rate Control + 15:0 + Reserved (future QRC stat output) + + + +6.1 PAK Multi-Pass +Multi-Pass PAK Usages: + + • Intra MB 3200-bit conformance + • Inter MB Re-quantization + • Frame level Re-quantization + +How to Enable Multi-Pass PAK? + + • Using the existing conditional batch buffer execution capability to skip/execute the second pass + o How to dynamically change the condition? +  Defined one error condition register with a mask. Do HW status page update + at the end of the first pass. 0 means all OK, non-zero means there is an error + condition, requiring second pass. Mask is used by the host to control what + kind of multi-pass is intended. +  For example, one error bit is 3200-bit conformance violation. Another error bit + is the total bit count exceeds (too much or too little) the target range (need to + define the target range in the state). +  The logic pefectly fits in the conditional batch buffer control logic that + VCS has today in GT. There is no additional logic need to be added in + VCS to support media functionality. (Batch Buffer Skip: This field only + takes effect if Compare Semaphore is set and the value at Semaphore + Address is NOT greater than the Semaphore Data Dword). + + • Adding a picture level state command to enable and control the behavior of the second pass PAK + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 195 + o How to control the re-PAK? Added 3 conformance flags (error registers) in the per-MB + streamout. Then the error control is based on the error register and the mask defined + in picture level states. There are 8 register flags defined out of which only the 3200-bit + case has usage model defined for today. The rest are left for future usage. +Issues and Limitations: + + • There is no programmable engine in MFX for flexible control: Therefore, whatever we have defined + must consider flexibility + +Following 2 MI packets are used inside VCS without any change to support Multipass-PAK behaviour. + + • MI_Conditional_Batch_Buffer_End + • Memory Interface Registers + + +6.2 Driver Usage +Driver places Image states in one batch buffer and all slice level and macroblock level states into another +batch buffer and link 2 batch buffers. Also replicate Image states with multipass changes in another batch +buffer link them to slice/macroblock batch buffer. In this way, only Image states are replicated but not the +slice/macroblock states. The image states includes all buffers defined at image(indirectMV, original pixel +buffer, etc). Following changes are needed in the Multipass Image State, + + • Reset- Stream-Out Enable(disable stream out in the second pass) + • Set- MacroblockStatEnable (enable reading of macroblock status buffer) + • Reset- 3200-bit conformance (do not report 3200-bit conformance) + + + + + • Define Conditional Batch Buffer End for CS/VCSVINunit + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 196 + 7. Programming Reference +7.1 Monochrome Picture Processing +Monochrome picture is specified using the Surface State with Surface Format of 12. Therefore, MFX +hardware, in either decode or encode mode, doesn’t generation any read or write traffic for U/V +components. Motivation for this bandwidth optimization is that monochrome video coding might be used +for wireless display. +For Encoder : + 1. No read in UV original components. + 2. processing UV component - no + 3. reconstructed UV component reference picture - no + 4. filter UV component - no +For Decoder : + 1. VLD mode : no color component coming out in Monochrome mode and so no processing and + not writing output + 2. IT mode : there is no color component in the coefficient buffer, and so no processing and not + writing output + + +7.2 Context Switch +There is no pre-emption for the BCS pipeline; hence every command buffer is required to contain all the +states setup (preamble). Specifically, CPU can not interrupt the BCS-BSD pipe, to stop the operation in +the middle of decoding a bitstream data. +Switch of contexts can only be performed at picture boundary. +No state needs to be saved. + + +7.3 Pipeline Flush +Implicit flush for AVC and VC1 is performed at the end of Slice : for MPEG2 is done when a new +image/picture command is issued. Because MPEG2 a slice can be one MB, no point to flush. MPEG2 will +snoop the next command if it is an img_state command. +Explicit flush MI (1 bit to do media pipeline vs Gx pipeline) flush and cache flush (switch reference frame) +– MI flush has bit to do cache flush. MI flush is for driver synchronization. + + +7.4 MMIO Interface +A set of registers are defined and accessible through MMIO interface to serve multiple purposes: + + • Use for system configuration + • For accessing Performance counters + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 197 + Register Address + Register Name Description Type Offset Dec/Enc +MFD ERROR Status MFD ERROR STATUS_VLD RO 12400 Dec + ERROR flags and counter +Reserved MBZ 12404~1241C +MFD picture-level parameter VC1 picture level parameters R/W 12420 Dec +Reserved MBZ 12434 +MFX PIPELINE_STATUS_FLAGS MFX PIPELINE STATUS RO 12438 Dec + Flags_MFX pipeline mode flags +MFX_Error_Injection_Parameter Control HW error injector WO 12454 Dec +Reserved 12458~1245C +MFX Frame Performance count Number of clocks spent RO 12460 Dec/Enc + decoding/encoding a frame +MFX Slice Performance count Number of clocks spent RO 12464 Dec/Enc + decoding/encoding a slice +MFX Frame Macroblock count Number of MBs decoded/encoded RO 12468 Dec/Enc + per frame +MFD Frame BITSTREAM SE/BIN count Number of bin/SE decoded per RO 1246C Dec + frame +MFX Memory Latency count1 Reference picture read latency -min RO 12470 Dec/Enc + and max +MFX Memory Latency count2 Reference picture read latency - RO 12474 Dec/ENc + Accumulative (used for compute + AVE latency) +MFX Memory Latency count3 row-store/bit-stream memory read RO 12478 Dec/Enc + latency -min and max +MFX Memory Latency count4 row-store/bit-stream memory read RO 1247C Dec/End + latency - accumulative (used to + compute AVE latency) +MFX Frame row-stored/bit-stream read # of row-store memory requests sent RO 12480 Dec/End +Count +MFX Motion Comp read Count total number of CL memory RO 12484 Dec/ENd + accesses per frame +MFX Motion Comp MISS Count total number of CL HITs per frame + RO 12488 Dec/ENd +Reserved 1248C~1249C +MFC_BITSTREAM_BYTECOUNT_FRAME Total Bitstream Output Byte Count RO 124A0 Enc + register per Frame +MFC_BITSTREAM_SE_BITCOUNT_FRAME Bitstream Output total Byte Count for RO 124A4 Enc + syntax eements ( total byes of MB + data from SEC per frame) +MFC_AVC_CABAC_BIN_COUNT_FRAME Bitstream Output total bin count per RO 124A8 Enc + frame +MFC_AVC_CABAC_INSERTION_COUNT Bitstream Output CABAC Insertion RO 124AC Enc + Count Register +MFC_AVC_MINSIZE_PADDING_COUNT Bitstream Output Minimal Size RO 124B0 Enc + Padding Count Register +MFC_IMAGE_STATUS_MASK image status(flags). R/W 124B4 Enc +MFC_IMAGE_STATUS_CONTROL suggested data for next frame in RO 124B8 Enc + multi-pass. +MFC_QP_STATUS_COUNT Overall adjusted delta QP via multi- RO 124BC Enc + pass, Sum of QPY for all + macroblocks of the frame + 124C0~124CC Enc +MFC_BITSTREAM_BYTECOUNT_SLICE Bitstream Output Byte Count RO 124D0 Enc + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 198 + Register Address + Register Name Description Type Offset Dec/Enc + Register per Slice +MFC_BITSTREAM_SE_BITCOUNT_SLICE Bitstream Output Bit Count for the RO 124D4 Enc + last Syntax Element Register +PAK_ REPORT_WARNING MPC Warning Register RO 124E4 Enc +PAK_REPORT_ERROR MPC Error Register RO 124E8 Enc +PAK_REPORT_RUNNING PAK_REPORT_RUNNING status RO 124EC Enc + register +Reserved 124F0~124FC Enc + + +7.4.1 Decoder Registers + +7.4.1.1 MFD ERROR STATUS_VLD ERROR flags and counter + + MFD_ERROR_STATUS - MFD Error Status +Register Space: MMIO: 0/2/0 +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12400h +This register stores the error status flags and count reports by the bit-stream decoder. + This register is not part of hardware context save and restore. Driver should read the content prior to starting a new +batch/frame. +DWord Bit Description +0 31:16 Number of Error Events + Exists If: JPEG == True + Format: U16 + This 16-bit field indicates the number of error events detected during decoding the current frame. This + field is clear at the start of decoding a new frame. + + 31:16 Number of MB Concealment + Exists If: AVC CAVLC, AVC CABAC, VC1 and MPEG2 == True + Format: U16 + This 16-bit field indicates the number of MB is concealmed by hardware. This field is clear at the start + of decoding a new frame. + + 15:0 Bit-stream Error flags + Bit-stream error detected by the VLD bit-steram decoder. These flags are reset at the beginning of a + frame and updated until starting of another frame. + AVC CAVLC: Please refer to AVC CAVLC table for each bit field + AVC CABAC: Please refer to AVC CABAC table for each bit field + VC1: Please refer to VC1 table for each bit field + MPEG2: Please refer to MPEG2 table for each bit field + JPEG: Please refer to JPEG table for each bit field + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 199 + 7.4.1.2 AVC CAVLC + + AVC CAVLC + +Source: VideoCS +Default Value: 0x00000000 +DWord Bit Description +0 15 Total Zero out-of-bound Error + This flag indicates the Total zero SE count exceed the max number of coeffs allowed in an intra16x16 AC + block. + 14 Coefficient level out-of-bound Error + This flag indicates the coded coefficient level SEs in the bit-stream is out-of-bound. + 13 RunBefore out-of-bound Error + This flag indicates the coded RunBefore SE value is larger than the remaining zero block count. + 12 Total coefficient Out-of-bound Error + This flag indicates the coded total coeff SE count exceed the max number of coeffs allowed in an + intra16x16 AC block. + 11 Temporal Direction Motion Vector Out-of-Bound Error + This flag indicates motion vectors calculated from Temporal Direct Motion Vector is larger than the + allowed range specified by the AVC spec. + 10 Final Motion Vector Out-of-Bound Error + This flag indicates final reconstructed Motion Vector value is larger than the allowed range specified by + the AVC spec. + 9 Motion Vector Delta SE Out-of-Bound Error + This flag indicates inconsistent Motion Vector Delta SEs coded in the bit-stream. + 8 Reference Index SE Out-of-Bound Error + This flag indicates inconsistent Reference Index SEs coded in the bit-stream. + 7 RunBefore/TotalZero Error + This flag indicates one or more inconsistent RunBefore or TotalZero SEs coded in the bit-stream. + 6 Exponential Golomb Error + This flag indicates hardware detects more than 18 leadzero for skip and more than 19 for other SEs from + the Exponential Golomb Logic + 5 Total Coeff SE Error + This flag indicates one or more inconsistent total coeff SEs coded in the bit-stream. + 4 Macroblock Coded Block Pattern Error + This flag indicates inconsistent CBP SEs coded in the bit-stream. + 3 Mbytpe/submbtype Error + This flag indicates inconsistent MBtype/SubMBtype SEs coded in the bit-stream. + 2 Chroma Intra prediction Mode Error + This flag indicates inconsistent Chroma Intra prediction mode SEs coded in the bit-stream. + 1 Luma Intra prediction Mode Error + This flag indicates inconsistent luma Intra prediction mode SE coded in the bit-stream. + 0 MB Concealment Flag + Each pulse from this flag indicates one MB is concealed by hardware. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 200 + 7.4.1.3 AVC CABAC + + AVC CABAC + +Source: VideoCS +Default Value: 0x00000000 +DWord Bit Description +0 15 Reserved + Format: MBZ + 14 Coefficient level out-of-bound Error + This flag indicates the coded coefficient level SEs in the bit-stream is out-of-bound. + 13 Reserved + Format: MBZ + 12 Reserved + Format: MBZ + 11 Temporal Direction Motion Vector Out-of-Bound Error + This flag indicates motion vectors calculated from Temporal Direct Motion Vector is larger than the + allowed range specified by the AVC spec. + 10 Final Motion Vector Out-of-Bound Error + This flag indicates final reconstructed Motion Vector value is larger than the allowed range specified by + the AVC spec. + 9 Motion Vector Delta SE Out-of-Bound Error + This flag indicates inconsistent Motion Vector Delta SEs coded in the bit-stream. + 8 Reference Index SE Out-of-Bound Error + This flag indicates inconsistent Reference Index SEs coded in the bit-stream. + 7 MacroBlock QpDelta Error + This flag indicates out-of-bound MB QP delta SEs coded in the bit-stream. + 6 Motion Vector Delta SE Error + This flag indicates out-of-bound motion vector delta SEs coded in the bit-stream. + 5 Reference Index SE Error + This flag indicates out-of-bound Refidx SEs coded in the bit-stream. + 4 Residual Error + This flag indicates out-of-bound absolute coefficient level SEs coded in the bit-stream. + 3 Slice end Error + This flag indicates a pre-matured slice_end SE or inconsistent slice end on the last MB of a slice. + 2 Chroma Intra prediction Mode Error + This flag indicates inconsistent Chroma Intra prediction mode SEs coded in the bit-stream. + 1 Luma Intra prediction Mode Error + This flag indicates inconsistent luma Intra prediction mode SE coded in the bit-stream. + 0 MB Concealment Flag + Each pulse from this flag indicates one MB is concealed by hardware. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 201 + 7.4.1.4 VC1 + + VC1 + +Source: VideoCS +Default Value: 0x00000000 + DWord Bit Description +0 15:8 Reserved + Format: MBZ + 7 Syncmarker Error + This flag indicates missing sync marker SEs coded in the bit-stream. + 6 Mbmode SE Error + This flag indicates inconsistent Macroblock SEs coded in the bit-stream. + 5 Transformtype SE Error + This flag indicates inconsistent transform type SEs coded in the bit-stream. + 4 Coefficient Error + This flag indicates inconsistent Coefficient SEs coded in the bit-stream. + 3 Motion Vector SE Error + This flag indicates inconsistent Motion Vector SEs coded in the bit-stream. + 2 Coded Block Pattern CY SE Error + This flag indicates inconsistent CBPCY SEs coded in the bit-stream. + 1 Mquant Error + This flag indicates inconsistent MQUANT SEs coded in the bit-stream. + 0 MB Concealment Flag + . Each pulse from this flag indicates one MB is concealed by hardware. + + + +7.4.1.5 MPEG2 + + MPEG2 + +Source: VideoCS +Default Value: 0x00000000 +DWord Bit Description +0 15:6 Reserved + Format: MBZ + 5 Missing EOB Error + This flag indicates missing EOB SEs coded in the bit-stream. Missing EOBs are concealed to match + CBP of the error MB. + 4 Inconsistent starting position Error – overlapping MBs + This flag indicates two slices overlapping one another by one or more MBs. Duplicate MBs decoded off + the second slice shall be discarded. + 3 Slice out-of-bound Error + This flag indicates a slice is running beyond the width of the picture. Out-of-bound MBs shall be + discarded. + 2 Premature frame end Error + This flag indicates missing slices/MBs coded in the bit-stream of a frame. One or more MBs are + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 202 + MPEG2 + concealed to reach end of picture. + 1 Inconsistent starting position Error – Missing MBs + This flag indicates one or more MBs are being concealed due to inconsistent MB starting and ending + positions between slices. + 0 MB Concealment Flag + . Each pulse from this flag indicates one MB is concealed by hardware. + + + +7.4.1.6 JPEG + + JPEG + +Source: VideoCS +Default Value: 0x00000000 +DWord Bit Description +0 15:5 Reserved + Format: MBZ + 4 Inconsistent VLD SE Error + This flag indicates an inconsistent SE coded in the bit-stream. Bit-stream does not match any entries in + the hauffman table. + 3 Extra Block Error + This flag indicates extra block coded within an ECS data boundary. + 2 Missing block Error + This flag indicates one or more blocks are missing within an ECS data boundary. + 1 Extra ECS Error + This flag indicates extra ECS’ coded in the bit-stream SCAN payload data. + 0 Missing ECS Error + This flag indicates one or more ECS’ are missing from the bit-stream SCAN payload data. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 203 + 7.4.1.7 MFD PICTURE PARAMETER - MFD Picture Parameter + + MFD_PICTURE_PARAM - MFD Picture Parameter +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 12420h + + + DWord Bit Description +0 31:0 Reserved + Format: MBZ + + + +7.4.1.8 MFX PIPELINE STATUS Flags_MFX pipeline mode flags + + MFX_STATUS_FLAGS - MFX Pipeline Status Flags +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12438h + + +This register stores the various pipeline status flags. + This register is not part of hardware context save and restore. + DWord Bit Description +0 31:17 Reserved + Format: MBZ + 16 MFX Active + Frame decoding/encoding is in progress. + Set on frame_start; + clear on frame_end. + 15:10 Reserved + Format: MBZ + 9 Streamout Enable + 7 Post Deblocking Mode Enable + 6 Pre Deblocking Mode Enable + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 204 + MFX_STATUS_FLAGS - MFX Pipeline Status Flags + 5 Decoder Mode Select + Value Name + 0 Configure the MFD Engine for VLD Mode + 1 Configure the MFD Engine for IT Mode + 4 Codec Select + Value Name + 0 Decode + 1 Encode + 3:2 Video Mode + Value Name + 00b MPEG2 + 01b VC1 + 10b AVC + 11b JPEG + 1 Decoder Short Format Mode + Value Name Description + 0 AVC/VC1 Short Format Mode is in use + 1 AVC/VC1 Long Format Mode is in use + 0 Stitch Mode + Value Name Description + 0b Not in Stitch Mode + 1b In the Special Stitch Mode + + + +7.4.1.9 MFX_FRAME_PERFORMANCE_CT - MFX Frame Performance Count + + MFX_FRAME_PERFORMANCE_CT - MFX Frame Performance Count +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12460h + + +This register stores the number of clock cycles spent decoding/encoding the current frame. + This register is not part of hardware context save and restore. +DWord Bit Description +0 31:0 MFX Frame Performance Count + Total number of clocks between frame start and frame end. This count is incremented on crm_clk + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 205 + 7.4.1.10 MFX Slice Performance Count – Reported clock count per slice + + MFX_SLICE_PERFORM_CT - MFX Slice Performance Count +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12464h + + +This register stores the number of clock cycles spent decoding/encoding the current slice. + This register is not part of hardware context save and restore. +DWord Bit Description +0 31:0 MFX Frame Performance Count + Total number of clocks between slice start and slice end. This count is incremented on crm_clk + + + +7.4.1.11 MFX_MB_COUNT - MFX Frame Macroblock Count + + MFX_MB_COUNT - MFX Frame Macroblock Count +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12468h + + +This register stores the number of Macro-blocks decoded/encoded in current frame. + This register is not part of hardware context save and restore. +DWord Bit Description +0 31:0 MFX Frame Macro-block Count + Total number of Macro-block decoded/encoded in current frame. This number is used with frame + performance count to derive clk/mb. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 206 + 7.4.1.12 MFX_SE-BIN_CT - MFX Frame BitSteam SE/BIN Count + + MFX_SE-BIN_CT - MFX Frame BitStream SE/BIN Count +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 1246Ch + + +This register stores the number of BINs (AVC CABAC) and SEs (CAVLD, VLD) decoded in a frame. + This register is not part of hardware context save and restore. +DWord Bit Description +0 31:0 MFX Frame Bit-stream SE/BIN Count + Total number of BINs/SEs decoded in current frame. This number is used with frame performance count + to derive Bin/clk or SE/clk. + + + +7.4.1.13 MFX Memory Latency Count1 – Reported Reference read latency + Counts + + MFX_LAT_CT1 - MFX_Memory_Latency_Count1 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12470h + + +This register stores the max and min memory latency counts reported on reference read requests. + This register is not part of hardware context save and restore. +DWord Bit Description +0 31:24 Max Request Count + This field indicates the maximum number of requests allowed by the memory sub-system channel. + 23:16 Current Request Count + This field indicates the number of requests currently outstanding in the memory sub-system. + This field should report with a value of zero at the end of frame; otherwise the motion compensation + engine is most likely hung waiting for read data to be returned from sub-system. + 15:8 MFX Reference picture read request - Max Latency Count in 8xMedia clock cycles + This field reports the maximum memory latency count on all reference reads requested by the motion + compensation engine. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 207 + MFX_LAT_CT1 - MFX_Memory_Latency_Count1 + 7:0 MFX Reference picture read request - Min Latency Count in 8xMedia clock cycles + This field reports the minimum memory latency count on all reference reads requested by the motion + compensation engine. + + + +7.4.1.14 MFX_LAT_CT2 - MFX Memory Latency Count2 + + MFX_LAT_CT2 - MFX Memory Latency Count2 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12474h + + +This register stores the accumulative memory latency count on reference picture read requests. + This register is not part of hardware context save and restore. +DWord Bit Description +0 31:26 Reserved + Format: MBZ + 25:0 MFX Reference picture read request - Accumulative Memory Latency Count for the entire frame + in 8xMedia clock cycles + The accumulative memory latency count of all reference reads requested by motion compensative + engine per frame. + This number is used with MFX Frame Motion Comp Read Count to derive average memory latency. + + + +7.4.1.15 MFX_LAT_CT3 - MFX Memory Latency Count3 + + MFX_LAT_CT3 - MFX Memory Latency Count3 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12478h + + +This register stores the max and min memory latency counts reported on row-stored/bit-stream read requests. Max + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 208 + MFX_LAT_CT3 - MFX Memory Latency Count3 +and current requests into memory sub-system engine. + This register is not part of hardware context save and restore. +DWord Bit Description +0 31:24 Max Request Count + This field indicates the maximum number of requests allowed by the memory sub-system channel. + 23:16 Current Request Count + This field indicates the number of requests currently outstanding in the memory sub-system. + This field should report with a value of zero at the end of frame; otherwise the pre-fetch engine most + likely hung waiting for read data to be returned from sub-system. + 15:8 MFX row-stored/bit-stream read request - Max Latency Count in 8xMedia clock cycles + This field reports the maximum memory latency count on all row-stored/bit-stream reads requested by + the memory pre-fetch engine. + 7:0 MFX row-stored/bit-stream read request - Min Latency Count in 8xMedia clock cycles + This field reports the minimum memory latency count on all row-stored/bit-stream reads requested by + the memory pre-fetch engine. + + + +7.4.1.16 MFX_LAT_CT4 - MFX Memory Latency Count4 + + MFX_LAT_CT4 - MFX Memory Latency Count4 +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 1247Ch + + +This register stores the accumulative memory latency count on row-stored/bit-stream read requests. + This register is not part of hardware context save and restore. +DWord Bit Description +0 31:26 Reserved + Format: MBZ + 25:0 MFX row-stored/bit-stream read request - Accumulative Memory Latency Count for the entire + frame in 8xMedia clock cycles + The accumulative memory latency count of all row-stored/bit-stream reads requested by pre-fetch + engine per frame. + This number is used with Frame row-stored/bit-stream memory read count to derive average + memory latency. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 209 + 7.4.1.17 MFX_SE-BIN_CT - MFX Frame BitStream SE/BIN Count + + MFX_SE-BIN_CT - MFX Frame BitStream SE/BIN Count +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 1246Ch + + +This register stores the number of BINs (AVC CABAC) and SEs (CAVLD, VLD) decoded in a frame. + This register is not part of hardware context save and restore. +DWord Bit Description +0 31:0 MFX Frame Bit-stream SE/BIN Count + Total number of BINs/SEs decoded in current frame. This number is used with frame performance count + to derive Bin/clk or SE/clk. + + + +7.4.1.18 MFX_READ_CT - MFX Frame Motion Comp Read Count + + MFX_READ_CT - MFX Frame Motion Comp Read Count +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12484h + + +This register stores the total number of reference picture read requests made by the Motion Compensation engine +per frame. + This register is not part of hardware context save and restore. +DWord Bit Description +0 31:20 Reserved + Format: MBZ + 19:0 MFX Frame Motion Comp CL read request Count + Total number of reference picture read requests by the motion compensation engine per frame. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 210 + 7.4.1.19 MFX_READ_CT - MFX Frame Motion Comp MISS Count + + MFX_MISS_CT - MFX Frame Motion Comp Miss Count +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12488h + + +This register stores the total number of cacheline hits occurred in the motion compensation cache per frame. + This register is not part of hardware context save and restore. +DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15:0 MFX Frame Motion Comp cache miss Count + Total number of CL misses occurred in the 12KB cache of the motion compensation engine per frame. + This number is used along with MFX Frame Motion Comp Read Count to derive motion comp cache + miss/hit ratio. + + + + +7.4.2 Encoder Registers + +7.4.2.1 MFC_VIN_AVD_ERROR_CNTR — AVC Bitstream Decoding Front-End + Parsing Logic Error Counter Report Register + + MFC_VIN_AVD_ERROR_CNTR - MFC_AVC Bitstream Decoding + Front-End Parsing Logic Error Counter +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Trusted Type: 1 +Address: 12804h + + + DWord Bit Description +0 31:0 Reserved + Format: MBZ +avd_error_flagsR[31:0] + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 211 + 7.4.3 MFC_BITSTREAM_BYTECOUNT_FRAME — Reported + Bitstream Output Byte Count per Frame + + MFC_BITSTREAM_BYTECOUNT_FRAME - Reported Bitstream + Output Byte Count per Frame Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 124A0h + + +This register stores the count of bytes of the bitstream output per frame +DWord Bit Description +0 31:0 MFC Bitstream Byte Count per Frame + Total number of bytes in the bitstream output per frame from the encoder. This includes header/tail/byte + alignment/data bytes/EMU (emulation) bytes/cabac-zero word insertion/padding insertion. This count is + updated for every time the internal bitstream counter is incremented and its reset at image start. + + + + +7.4.4 MFC_BITSTREAM_SE_BITCOUNT_FRAME (Reported + Bitstream Output Bit Count for Syntax Elements Only) + + MFC_BITSTREAM_SE_BITCOUNT_FRAME - Reported Bitstream + Output Bit Count for Syntax Elements Only Register +Register Space: MMIO: 0/2/0 +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 124A4h + + +This register stores the count of number of bits in the bitstream due to syntax elements only. This excludes header/ +byte alignment /tail/EMU/CABAC-0word/padding bits but includes the stop-one-bit. This register is part of the context +save and restore. +DWord Bit Description +0 31:0 MFC Bitstream Syntax Element Only Bit Count + Total number of bits in the bitstream output due to syntax elements only. It includes the data bytes only. + This count is updated for every time the internal bitstream counter is incremented and its reset at image + start. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 212 + 7.4.5 MFC_AVC_CABAC_BIN_COUNT_FRAME (Reported Bitstream + Output CABAC Bin Count) + + MFC_AVC_CABAC_BIN_COUNT_FRAME - Reported Bitstream + Output CABAC Bin Count Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 124A8h + + +This register stores the count of number of bins per frame. +DWord Bit Description +0 31:0 MFC AVC Cabac Bin Count + Total number of BINs in the bitstream output per frame from the encoder. This count is updated for every + time the bin counter is incremented and its reset at image start. + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 213 + 7.4.6 MFC_AVC_CABAC_INSERTION_COUNT — Reported Bitstream + Output CABAC Insertion Count + + AVC_CABAC_INSERTION_COUNT - + MFC_AVC_CABAC_INSERTION_COUNT +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 124ACh + + +This register stores the count in bytes of CABAC ZERO_WORD insertion. It is primarily provided for statistical +data gathering. +DWord Bit Description +0 31:0 MFC AVC Cabac Insertion Count + Total number of bytes in the bitstream output before for the CABAC zero word insertion. This count is + updated each time when the insertion count is incremented. + + + + +7.4.7 MFC_AVC_MINSIZE_PADDING_COUNT — Reported Bitstream + Output Minimal Size Padding Count + + MFC_AVC_MINSIZE_PADDING_COUNT - Bitstream Output Minimal + Size Padding Count Report Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 12414h +Name: VDBOX1 + + +This register stores the count in bytes of minimal size padding insertion. It is primarily provided for statistical +data gathering. This register is part of the context save and restore. +DWord Bit Description +0 31:0 MFC AVC MinSize Padding Count + Total number of bytes in the bitstream output contributing to minimal size padding operation. This count + is updated each time when the padding count is incremented. + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 214 + 7.5 MFC_IMAGE_STATUS_MASK + MFC_IMAGE_STATUS_MASK - MFC Image Status Mask +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 124B4h + + +This register stores the image status(flags). + DWord Bit Description +0 31:0 Control Mask + Control Mask for dynamic frame repeat. + + + + +7.5.1 MFC_IMAGE_STATUS_CONTROL + + MFC_IMAGE_STATUS_CONTROL - MFC Image Status Control +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Trusted Type: 1 +Address: 124B8h + + +This register stores the suggested data for next frame in multi-pass. +DWord Bit Description +0 31:24 Cumulative slice delta QP + 23:16 QP Value + suggested slice QP delta value for frame level Rate control. This value can be +ve or -ve + 15 QP-Polarity Change + Cumulative slice delta QP polarity change. + 14:13 Num-Pass Polarity Change + Number of passes after cumulative slice delta QP polarity changes. + 12 Reserved + Format: MBZ + 11:8 Total Num-Pass + 7:3 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 215 + MFC_IMAGE_STATUS_CONTROL - MFC Image Status Control + 2 Panic + Panic triggered to avoid too big packed file. + 1 Frame Bit Count + Frame Bit count over-run/under-run flag + 0 Max Conformance Flag + Max Macroblock conformance flag or Frame Bit count over-run/under-run + + + + +7.5.2 MFC_QUP_CT - MFC QP Status Count + + MFC_QUP_CT - MFC QP Status Count +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 124BCh + + +This register stores the suggested QP COUNTS in multi-pass. +DWord Bit Description +0 31:24 Cumulative QP Adjust + Format: U8 + Cumulative QP adjustment after multiple passes. If there is no need to multi-pass, this value would be + zero. (This is in sign magnitude form). + + 23:0 Cumulative QP + Format: U24 + Cumulative QP for all MB of a Frame ( Can be used for computing average QP). + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 216 + 7.5.3 MFC_BITSTREAM_BYTECOUNT_SLICE — Bitstream Output + Byte Count per Slice + + MFC_BITSTREAM_BYTECOUNT_SLICE - Bitstream Output Byte + Count Per Slice Report Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 124D0h + + +This register stores the count of bytes of the bitstream output. This register is part of the context save and restore. +DWord Bit Description +0 31:0 MFC Bitstream Byte Count + Total number of bytes in the bitstream output from the encoder. This count is updated for every time the + internal bitstream counter is incremented. + + + + +7.5.4 MFC_BITSTREAM_SE_BITCOUNT_SLICE — Bitstream Output + Bit Count for the last Syntax Element + + MFC_BITSTREAM_SE_BITCOUNT_SLICE - Bitstream Output Bit + Count for the last Syntax Element Report Register +Register Space: MMIO: 0/2/0 + + +Source: VideoCS +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Trusted Type: 1 +Address: 124D4h +Name: VDBOX1 + + +This register stores the count of number of bits in the bitstream for the last syntax element before padding. The bit +count is before the byte-aligned alignment padding insertion, but includes the stop-one-bit. This register is part of the +context save and restore. + DWord Bit Description +0 31:0 MFC Bitstream Syntax Element Bit Count + Total number of bits in the bitstream output before padding. This count is updated each time the + internal counter is incremented. + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 217 + 7.6 Row Store Sizes and Allocations + AVC VC1 MPEG2 JPEG IT ENC SEC ENC + Bitstream Bitstream Bitstream Bitstream VDS Orig Pix BSP data +vin_vmx_pixcoefind_ + COEF +addr[31:6] + + VAD BSD VMD RS VDS MV MPC MV +vin_vmx_mvbsdrs_ +addr[31:6] + + VAM MPR VDS ILDB MPC RS +vin_vmx_mpcildbmpr_ +addr[31:6] + + VAM DMV VCP DMV +vin_vmx_dmv*_ +addr[31:6] + + VCP BP +vin_vmx_bp_addr +[31:0] + + + + Write + Surf size + + VBP BP vin_bp_addr Frame width/pitch * Height + VMD RS vin_vmx_mvbsdrs_addr Frame width + VCP RS vin_vmx_mvbsdrs_addr Frame width + VCP DMV vin_vmx_dmv1_addr Frame size + VAD BSD vin_vmx_mvbsdrs_addr Frame width * (1+mbaff) + VAM MPR vin_vmx_mpcildbmpr_addr Frame width * (1+mbaff) + VAM DMV 34x1 mux, from IDC Frame size + Streamout vin_streamout_addr Frame size + VOP RS vin_ipred_os_addr Frame width + MPC RS vin_vmx_mpcildbmpr_addr Frame width * (1+mbaff) + BSP BS Direct from BSP + BSP MB Direct from BSP + + Read +row store VMD Frame width + vin_vmx_mvbsdrs_addr + +row store VCP Frame width + vin_vmx_mvbsdrs_addr + +DMV VCP Frame size + vin_vmx_dmv*_addr + +Bitplane VCD Frame width/pitch * Height + vin_vmx_bp_addr + +Bsd VAD Frame width * (1+mbaff) + vin_vmx_mvbsdrs_addr + +Mpr VAM Frame width * (1+mbaff) + vin_vmx_mpcildbmpr_addr + +Dmv VAM Frame size + vin_vmx_dmv*_addr + +Coef VDS Obj + vin_vmx_pixcoefind_addr + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 218 + Write + Surf size + +Mv VDS Obj + vin_vmx_mvbsdrs_addr + +Ildb VDS Obj + vin_vmx_mpcildbmpr_addr + +Rs VIP Frame width + vin_ipred_os_addr + +RS MPC Frame width * (1+mbaff) + vin_vmx_mpcildbmpr_addr + +MV MPC Obj + vin_vmx_mvbsdrs_addr + +sec enc BSP Obj + vin_vmx_mvbsdrs_addr + +multipass VIN Frame size + vin_vmx_bp_addr + +orig pix USB Frame size + vin_vmx_pixcoefind_addr + +MPEG2 VLD Decoding Mode : +use BSD Row Store only, and +MPEG2 IT Decoding Mode : +MPEG2 IT mode does not need row-store +JPEG VLD Decoding Mode : no row store is needed + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 219 + Revision History +Revision Number Description Revision Date +1.0 First 2012 OpenSource edition 2012 +1.1 Revisions based on user feedback 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V2 Pt 3_r1.1 – 05 12 7/19/2012 220 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol3_part1.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol3_part1.txt new file mode 100644 index 0000000..d33974c --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol3_part1.txt @@ -0,0 +1,2577 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 3 Part 1: VGA and Extended VGA +Registers +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 + Contents +1. VGA and Extended VGA Registers ...................................................................................................... 5 + 1.1 General Control and Status Registers ................................................................................................. 6 + 1.1.1 ST00 - Input Status 0 ...................................................................................................................... 7 + 1.1.2 ST01 - Input Status 1 ...................................................................................................................... 7 + 1.1.3 FCR - Feature Control .................................................................................................................... 9 + 1.1.4 MSR - Miscellaneous Output .......................................................................................................... 9 + 1.2 Sequencer Registers.......................................................................................................................... 11 + 1.2.1 SRX - Sequencer Index ................................................................................................................ 11 + 1.2.2 SR00 - Sequencer Reset .............................................................................................................. 12 + 1.2.3 SR01 - Clocking Mode .................................................................................................................. 12 + 1.2.4 SR02 - Plane/Map Mask ............................................................................................................... 13 + 1.2.5 SR03 - Character Font ................................................................................................................. 14 + 1.2.6 SR04 - Memory Mode Register .................................................................................................... 15 + 1.2.7 SR07 - Horizontal Character Counter Reset ................................................................................ 15 + 1.3 Graphics Controller Registers ............................................................................................................ 16 + 1.3.1 GRX - GRX Graphics Controller Index Register .......................................................................... 16 + 1.3.2 GR00 - Set/Reset Register ........................................................................................................... 16 + 1.3.3 GR01 - Enable Set/Reset Register .............................................................................................. 17 + 1.3.4 GR02 - Color Compare Register .................................................................................................. 17 + 1.3.5 GR03 - Data Rotate Register ....................................................................................................... 18 + 1.3.6 GR04 - Read Plane Select Register ............................................................................................. 18 + 1.3.7 GR05 - Graphics Mode Register .................................................................................................. 19 + 1.3.8 GR06 - Miscellaneous Register .................................................................................................... 21 + 1.3.9 GR07 - Color Don’t Care Register ................................................................................................ 22 + 1.3.10 GR08 - Bit Mask Register ........................................................................................................... 23 + 1.3.11 GR10 - Address Mapping ........................................................................................................... 23 + 1.3.12 GR11 - Page Selector ................................................................................................................ 24 + 1.3.13 GR18 - Software Flags ............................................................................................................... 25 + 1.4 Attribute Controller Registers ............................................................................................................. 25 + 1.4.1 ARX - Attribute Controller Index Register ..................................................................................... 25 + 1.4.2 AR[00:0F] - Palette Registers [0:F]............................................................................................... 26 + 1.4.3 AR10 - Mode Control Register ..................................................................................................... 27 + 1.4.4 AR12 - Memory Plane Enable Register ....................................................................................... 28 + 1.4.5 AR13 - Horizontal Pixel Panning Register .................................................................................... 29 + 1.4.6 AR14 - Color Select Register ....................................................................................................... 30 + 1.5 VGA Color Palette Registers ............................................................................................................. 30 + 1.5.1 DACMASK - Pixel Data Mask Register ........................................................................................ 31 + 1.5.2 DACSTATE – DAC State Register ............................................................................................... 32 + 1.5.3 DACRX - Palette Read Index Register ......................................................................................... 32 + 1.5.4 DACWX - Palette Write Index Register ........................................................................................ 33 + 1.5.5 DACDATA - Palette Data Register ............................................................................................... 33 + 1.6 CRT Controller Register ..................................................................................................................... 33 + 1.6.1 CRX - CRT Controller Index Register .......................................................................................... 35 + 1.6.2 CR00 - Horizontal Total Register.................................................................................................. 35 + 1.6.3 CR01 - Horizontal Display Enable End Register .......................................................................... 35 + 1.6.4 CR02 - Horizontal Blanking Start Register ................................................................................... 36 + 1.6.5 CR03 - Horizontal Blanking End Register .................................................................................... 36 + 1.6.6 CR04 - Horizontal Sync Start Register ......................................................................................... 37 + 1.6.7 CR05 - Horizontal Sync End Register .......................................................................................... 37 + 1.6.8 CR06 - Vertical Total Register ...................................................................................................... 38 + 1.6.9 CR07 - Overflow Register (Vertical) ............................................................................................. 38 + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 3 + 1.6.10 CR08 - Preset Row Scan Register ............................................................................................. 40 + 1.6.11 CR09 - Maximum Scan Line Register ........................................................................................ 41 + 1.6.12 CR0A - Text Cursor Start Register ............................................................................................. 42 + 1.6.13 CR0B - Text Cursor End Register .............................................................................................. 42 + 1.6.14 CR0C - Start Address High Register .......................................................................................... 43 + 1.6.15 CR0D - Start Address Low Register ........................................................................................... 43 + 1.6.16 CR0E - Text Cursor Location High Register .............................................................................. 43 + 1.6.17 CR0F - Text Cursor Location Low Register ............................................................................... 44 + 1.6.18 CR10 - Vertical Sync Start Register ........................................................................................... 44 + 1.6.19 CR11 - Vertical Sync End Register ............................................................................................ 44 + 1.6.20 CR12 - Vertical Display Enable End Register ............................................................................ 45 + 1.6.21 CR13 - Offset Register ............................................................................................................... 45 + 1.6.22 CR14 - Underline Location Register ........................................................................................... 46 + 1.6.23 CR15 - Vertical Blanking Start Register ..................................................................................... 47 + 1.6.24 CR16 - Vertical Blanking End Register ...................................................................................... 47 + 1.6.25 CR17 - CRT Mode Control ......................................................................................................... 47 + 1.6.26 CR18 - Line Compare Register .................................................................................................. 50 + 1.6.27 CR22 - Memory Read Latch Data Register ................................................................................ 51 + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 4 + 1. VGA and Extended VGA Registers +This section describes the registers and the functional operation notations for the observable registers in +the VGA section. This functionality is provided as a means for support of legacy applications and +operating systems. It is important to note that these registers will in general have the desired effects only +when running VGA display modes. + +The main exceptions to this are the palette interface which will allow real mode DOS applications and full +screen VGA applications under an OS control running in high resolution (non-VGA) modes to access the +palette through the VGA register mechanisms and the use of the ST01 status bits that determine when +the VGA enters display enable and sync periods. Other exceptions include the register bits that control +the memory accesses through the A000:0000 and B000:0000 memory segments which would get used +during operating system emulation of VGA for “DOS box” applications. Some of the functions of the VGA +are enabled or defeated through the programming of the VGA control register bits that are located in the +MMIO register space. +Given the legacy nature of this function, it has been adapted to the changing environment that it must +operate within. The three most notable changes were the addition of high resolution display mode +support, new operating system support, and the use of fixed resolution display devices (such as LCD +panels). Additional control bits in the PCI Config space will affect the ability to access the registers and +memory aperture associated with VGA. + + VGA VGA Palette (VGA) VGA + Mode of Disable Display VGA Memory VGA + Operation Registers Banking +VGA DOS No Yes Yes Yes Yes No +HiRes DOS Yes No Yes Yes No Yes +Fullscreen DOS Yes/No No/Yes Yes Yes Yes Yes +DOS Emulation Yes No Yes Yes Yes Yes + + + + 132 Column 9-Dot Main + Text Support Disable Support Use +VGA Display Mode Dot Clock Select Dot Clock Range +Native VGA Clock Select 25/28 MHz No No Analog CRT + (VGA + connector) +Centered Fixed at display Product Specific No Yes Digital + Requirements Display +Upper Left Corner Fixed at display Product Specific No Yes Internal + Requirements Panel + +Native, Centered, and Upper Left Corner support varies from product to product. +Even in the native VGA display operational modes, not all combinations of bit settings result in functional +operating modes. VGA display modes have the restriction that they can be used only when all other +display planes are disabled. +These registers are accessed via I/O space. The I/O space resides in the PCI compatibility hole and uses +only the addresses that were part of the original VGA I/O space (which includes EGA and MDA +emulation). Accesses to the VGA I/O addresses are steered to the proper bus and rely on proper setup of +bridge registers. Extended VGA registers such as GR10 and GR11 use additional indexes for the already + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 5 + defined I/O addresses. VGA register accesses are allowed as 8 or 16 bit naturally aligned transactions +only. Word transactions must have the least significant bit of the address set to zero. DWORD I/O +operations should not be performed on these registers. +Some products may support access to these registers through MMIO. The access method varies and is +documented elsewhere. + + +1.1 General Control and Status Registers +The setup, enable, and general registers are all directly accessible by the CPU. A sub indexing scheme is +not used to read from and write to these registers. + Read Write +Name Function I/O Memory Offset I/O Memory Offset +ST00 VGA Input Status Register 0 3C2h 3C2h -- -- +ST01 VGA Input Status Register 1 -- -- + 3BAh/3DAh1 3BAh/3DAh1 + FCR VGA Feature Control Register 3CAh 3CAh + 3BAh/3DAh1 3BAh/3DAh1 +MSR VGA Miscellaneous Output Register 3CCh 3CCh 3C2h 3C2h + 1 +Note: The address selection for ST01 reads and FCR writes is dependent on CGA or MDA emulation +mode as selected via the MSR register. +Various bits in these registers provide control over and the real-time status of the horizontal sync signal, +the horizontal retrace interval, the vertical sync signal, and the vertical retrace interval. The horizontal +retrace interval is the period during the drawing of each scan line containing active video data, when the +active video data is not being displayed. This period includes the horizontal front and back porches, and +the horizontal sync pulse. The horizontal retrace interval is always longer than the horizontal sync pulse. +The vertical retrace interval is the period during which the scan lines not containing active video data are +drawn. This includes the vertical front porch, back porch, and the vertical sync pulse. The vertical retrace +interval is normally longer than the vertical sync pulse. +Display Enable is a status bit (bit 0) in VGA Input Status Register 1 that indicates when either a horizontal +retrace interval or a vertical retrace interval is taking place. In the EGA graphics system (and the ones +that preceded it, including MDA and CGA), it was important to check the status of this bit to ensure that +one or the other retrace intervals was taking place before reading from or writing to the frame buffer. In +these earlier systems, reading from or writing to frame buffer at times outside the retrace intervals meant +that the CRT controller would be denied access to the frame buffer in while accessing pixel data needed +to draw pixels on the display. This resulted in either “snow” or a flickering display. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 6 + 1.1.1 ST00 - Input Status 0 +I/O (and Memory Offset) Address:3C2h +Default:00h +Attributes:Read Only + 7 6 5 4 3 0 +CRT Interrupt Reserved (00) RGB Cmp / Sen Reserved (0000) + + + Bit Descriptions + 7 + CRT Interrupt Pending. This bit is here for EGA compatibility and will always return zero. Note that the + generation of interrupts was originally enabled, through bits [4,5] of the Vertical Retrace End Register + (CR11). This ability to generate interrupts at the start of the vertical retrace interval is a feature that is + typically unused by DOS software and therefore is only supported through other means for use under a + operating system support. + 0 = CRT (vertical retrace interval) interrupt is not pending. + 1 = CRT (vertical retrace interval) interrupt is pending + 6:5 + Reserved. Read as 0s. + + 4 + RGB Comparator / Sense. This bit is here for compatibility and will always return one. Monitor detection + must be done be done through the programming of registers in the MMIO space. + 0 = Below threshold + 1 = Above threshold + + 3:0 + Reserved. Read as 0s. + + + +1.1.2 ST01 - Input Status 1 +I/O (and Memory Offset) Address:3BAh/3DAh +Default:00h +Attributes:Read Only +The address selection is dependent on CGA or MDA emulation mode as selected via the MSR register. + 7 6 5 4 3 2 1 0 +Reserved (0)Reserved (0)Video FeedbackVertical RetraceReserved (00)Display Enable + + + Bit Descriptions + 7 + Reserved (as per VGA specification). Read as 0s. + + 6 + Reserved. Read as 0. + + 5:4 + Video Feedback 1, 0. These are diagnostic video bits that are selected by the Color Plane Enable + Register. These bits that are programmably connected to 2 of the 8 color bits sent to the palette. Bits 4 + and 5 of the Color Plane Enable Register (AR12) selects which two of the 8 possible color bits become + connected to these 2 bits of this register. The current software normally does not use these 2 bits. They + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 7 + Bit Descriptions + exist for EGA compatibility. + 3 + Vertical Retrace/Video. + 0 = VSYNC inactive (Indicates that a vertical retrace interval is not taking place). + 1 = VSYNC active (Indicates that a vertical retrace interval is taking place). + Note: + VGA pixel generation is not locked to the display output but is loosely coupled. A VSYNC indication may + not occur during the actual VSYNC going to the display but during the VSYNC that is generated as part + of the VGA pixel generation. The exact relationship will vary with the VGA display operational mode. + This status bit will remain active when the VGA is disabled and the device is running in high resolution + modes (non-VGA) to allow for applications that (now incorrectly) use these status registers bits. In this + case, the status will come from the pipe that the VGA is assigned to. + Bits 4 and 5 of the Vertical Retrace End Register (CR11) previously could program this bit to generate + an interrupt at the start of the vertical retrace interval. This ability to generate interrupts at the start of the + vertical retrace interval is a feature that is largely unused by legacy software. Interrupts are not + supported through the VGA register bits. + + 2:1 + Reserved. Read as 0s. + + 0 + Display Enable Output. Display Enable is a status bit (bit 0) in VGA Input Status Register 1 that + indicates when either a horizontal retrace interval or a vertical retrace interval is taking place. This bit + was used with the EGA graphics system (and the ones that preceded it, including MDA and CGA). In + those cases, it was important to check the status of this bit to ensure that one or the other retrace + intervals was taking place before reading from or writing to the frame buffer. In these earlier systems, + reading from or writing to the frame buffer at times outside the retrace intervals meant that the CRT + controller would be denied access to the frame buffer. Those behaviors resulted in either “snow” or a + flickering display. This bit provides compatibility with software designed for those early graphics + controllers. This bit is currently used in DOS applications that access the palette to prevent the sparkle + associated with read and write accesses to the palette RAM with the same address on the same clock + cycle. + This status bit remains active when the VGA display is disabled and the device is running in high + resolution modes (non-VGA) to allow for applications that (now considered incorrect) use these + status registers bits. In this case, the status will come from the pipe that the VGA is assigned to. + When in panel fitting VGA or centered VGA operation, the meaning of these bits will not be + consistent with native VGA timings. + 0 = Active display data is being sent to the display. Neither a horizontal retrace interval or a vertical + retrace interval is currently taking place. + 1 = Either a horizontal retrace interval (horizontal blanking) or a vertical retrace interval (vertical + blanking) is currently taking place. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 8 + 1.1.3 FCR - Feature Control +I/O (and Memory Offset) Address:3BAh/3DAh - Write; 3CAh - Read +Default:00h +Attributes:See Address above +The I/O address used for writes is dependent on CGA or MDA emulation mode as selected via the MSR +register. In the original EGA, bits 0 and 1 were used as part of the feature connector interface. Feature +connector is not supported in these devices and those bits will always read as zero. +7 4 3 2 0 +Reserved (0000)VSYNC ControlReserved (000) + + + Bit Descriptions + 7:4 + Reserved. Read as 0. + + 3 + VSYNC Control. This bit is provided for compatibility only and has no other function. Reads and writes + to this bit have no effect other than to change the value of this bit. The previous definition of this bit + selected the output on the VSYNC pin. + 0 = Was used to set VSYNC output on the VSYNC pin (default). + 1 = Was used to set the logical 'OR' of VSYNC and Display Enable output on the VSYNC pin. This + capability was not typically very useful. + + 2:0 + Reserved. Read as 0. + + + +1.1.4 MSR - Miscellaneous Output +I/O (and Memory Offset) Address:3C2h - Write; 3CCh - Read +Default:00h +Attributes:See Address above + 7 6 5 4 3 2 1 0 +VSYNC Polarity HSYNC Polarity Page Select Reserved (0) Clock Select Memory Enable I/O Address + + + Bit Descriptions + 7 CRT VSYNC Polarity. This is a legacy function that is used in native VGA modes. For most cases, sync + polarity will be controlled by the port control bits. The VGA settings can be optionally selected for + compatibility with the original VGA when used in the VGA native mode. Sync polarity was used in VGA to + signal the monitor how many lines of active display are being generated. + 0 = Positive Polarity (default). + 1 = Negative Polarity. + 6 CRT HSYNC Polarity. This is a legacy function that is used in native VGA modes. For most cases, sync + polarity will be controlled by the port control bits. The VGA settings can be optionally selected for + compatibility with the original VGA when used in the VGA native mode. + 0 = Positive Polarity (default). + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 9 + Bit Descriptions + 1 = Negative Polarity + 5 Page Select. In Odd/Even Memory Map Mode 1 (GR6), this bit selects the upper or lower 64 KB page in + display memory for CPU access: + 0 = Upper page (default) + 1 = Lower page. + Selects between two 64KB pages of frame buffer memory during standard VGA odd/even modes (modes + 0h through 5h). Bit 1 of register GR06 can also program this bit in other modes. Note that this bit is would + normally set to 1 by the software. + 4 Reserved. Read as 0. + 3:2 Clock Select. These bits can select the dot clock source for the CRT interface. The bits should be used to + select the dot clock in standard native VGA modes only. When in the centering or upper left corner modes, + these bits should be set to have no effect on the clock rate. The actual frequencies that these bits select, if + they have any affect at all, is programmable through the DPLL MMIO registers. + 00 = CLK0, 25.175 MHz (for standard VGA modes with 640 pixel (8-dot) horizontal resolution) (default) + 01 = CLK1, 28.322 MHz. (for standard VGA modes with 720 pixel (9-dot) horizontal resolution) + 10 = Was used to select an external clock (now unused) + 11 = Reserved + 1 A0000-BFFFFh Memory Access Enable. VGA Compatibility bit enables access to video memory (frame + buffer) at A0000-BFFFFh. When disabled, accesses to VGA memory are blocked in this region. This bit is + independent of and does not block CPU access to the video linear frame buffer at other addresses. + + + 0 = Prevent CPU access to memory/registers/ROM through the A0000-BFFFF VGA memory aperture + (default). + 1 = Allow CPU access to memory/registers/ROM through the A0000-BFFFF VGA memory aperture. This + memory must be mapped as UC by the CPU. + + 0 I/O Address Select. This bit selects 3Bxh or 3Dxh as the I/O address for the CRT Controller registers, the + Feature Control Register (FCR), and Input Status Register 1 (ST01). Presently ignored (whole range is + claimed), but will “ignore” 3Bx for color configuration or 3Dx for monochrome. + Note that it is typical in AGP chipsets to shadow this bit and properly steer I/O cycles to the proper bus for + operation where a MDA exists on another bus such as ISA. + + + 0 = Select 3Bxh I/O address (MDA emulation) (default). + 1 = Select 3Dxh I/O address (CGA emulation). + + + + +Note: In standard VGA modes using the analog VGA connector, bits 7 and 6 indicate which of the three +standard VGA vertical resolutions the standard VGA display should use. Extended modes, including +those with a vertical resolution of 480 scan lines, may use a setting of 0 for both of these bits. Different +connector standards and timing standards specify the proper use of sync polarity. This setting was +“reserved” in the VGA standard. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 10 + Analog CRT Display Sync Polarities + V H Display Horizontal Frequency Vertical Frequency + P P 200 Line 15.7 KHz 60 Hz + N P 350 Line 21.8 KHz 60 Hz + P N 400 Line 31.5 KHz 70 Hz + N N 480 Line 31.5 KHz 60 Hz + + + +1.2 Sequencer Registers +The sequencer registers are accessed via either I/O space or Memory space. To access registers the +VGA Sequencer Index register (SRX) at I/O address 3C4h (or memory address 3C4h) is written with the +index of the desired register. Then the desired register is accessed through the data port for the +sequencer registers at I/O address 3C5 (or memory address 3C5). + + +1.2.1 SRX - Sequencer Index +I/O (and Memory Offset) Address:3C4h +Default:00h +Attributes:Read/Write +7 32 0 +Reserved (00000)Sequencer Index + + + Bit Description + 7:3 + Reserved. Read as 0s. + + 2:0 + Sequencer Index. This field contains a 3-bit Sequencer Index value used to access sequencer + data registers at indices 0 through 7. + Notes: +  SR02 is referred to in the VGA standard as the Map Mask Register. However, the word “map” + is used with multiple meanings in the VGA standard and was, therefore, deemed too + confusing; hence, the reason for calling it the Plane Mask Register. +  SR07 is a standard VGA register that was not documented. It is not a graphics controller + extension. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 11 + 1.2.2 SR00 - Sequencer Reset +I/O (and Memory Offset) Address:3C5h(Index=00h) +Default:00h +Attributes:Read/Write +7 2 1 0 +Reserved (000000)ReservedReserved + + + Bit Descriptions + 7:2 + Reserved. Read as 0. + + 1 + Reserved. Reserved for VGA compatibility (was reset). + + 0 + Reserved. Reserved for VGA compatibility. (was reset) + + + +1.2.3 SR01 - Clocking Mode +I/O (and Memory Offset) Address:3C5h (Index=01h) +Default:00h +Attributes:Read/Write +7 6 5 4 3 2 1 0 +Reserved (00)Screen OffShift 4Dot Clock DivideShift LoadReserved (0)8/9 Dot Clocks + + + Bit Descriptions + 7:6 + Reserved. Read as 0s. + + 5 + Screen Off. + 0 = Normal Operation (default). + 1 = Disables video output (blanks the screen) and turns off display data fetches. Synchronization pulses + to the display, however, are maintained. Setting this bit to 1 had been used as a way to more rapidly + update and improve CPU access performance to the frame buffer during VGA modes. In non-VGA modes + (VGA Disable=1), this bit has no effect. Before the VGA is disabled through the MMIO VGA control + register, this bit should be set to stop the memory accesses from the display. + + + + + Programming Notes: The following sequence must be used when disabling the VGA plane. + 1. Write SR01 to set bit 5 = 1 to disable video output. + 2. Wait for 100us. + 3. Disable the VGA plane via Bit 31 of the MMIO VGA control register (location found in the MMIO + display register programming specification). + 4 + Shift 4. + 0 = Load video shift registers every 1 or 2 character clocks (depending on bit 2 of this register) (default). + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 12 + Bit Descriptions + 1 = Load shift registers every 4th character clock. + 3 + Dot Clock Divide. Setting this bit to 1 stretches doubles all horizontal timing periods that are specified in + the VGA horizontal CRTC registers. This bit is used in standard VGA 40-column text modes to stretch + timings to create horizontal resolutions of either 320 or 360 pixels (as opposed to 640 or 720 pixels, + normally used in standard VGA 80-column text modes). The effect of this is that there will actually be + twice the number of pixels sent to the display per line. + 0 = Pixel clock is left unaltered (used for 640 (720) pixel modes); (default). + 1 = Pixel clock divided by 2 (used for 320 (360) pixel modes). + + 2 + Shift Load. Bit 4 of this register must be 0 for this bit to be effective. + 0 = Load video data shift registers every character clock (default). + 1 = Load video data shift registers every other character clock. + 1 + Reserved. Read as 0. + + 0 + 8/9 Dot Clocks. This bit determines whether a character clock is 8 or 9 dot clocks long if clock doubling is + disabled and 16 or 18 clocks if it is. This also changes the interpretation of the pixel panning values (see + chart). An additional control bit determines if this bit is to be ignored and 8-dot characters are to be used + always. The 9-dot disable would be used when doubling the horizontal pixels on a 1280 wide display or + non-doubling on a 640 wide display. Panning however will occur according to the expected outcome. + 0 = 9 dot clocks (9 horizontal pixels) per character in text modes with a horizontal resolution of 720 pixels. + 1 = 8 dot clocks (8 horizontal pixels) per character in text or graphics modes with a horizontal resolution of + 640 pixels. + + + + +1.2.4 SR02 - Plane/Map Mask +I/O (and Memory Offset) Address:3C5h (Index=02h) +Default:00h +Attributes:Read/Write +7 43 0 +ReservedMemory Planes Processor Write Access Enable. + + + Bit Descriptions +7:4 + Reserved. Read as 0s. + +3:0 + Memory Planes [3:0] Processor Write Access Enable. In both the Odd/Even Mode and the Chain 4 + Mode, these bits still control access to the corresponding color plane. + 0 = Disable. + 1 = Enable. + Note:This register is referred to in the VGA standard as the Map Mask Register. However, the word “map” + is used with multiple meanings in the VGA standard and was, therefore, considered too confusing; hence, + the reason for calling it the Plane Mask Register. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 13 + 1.2.5 SR03 - Character Font +I/O (and Memory Offset) Address:3C5h (index=03h) +Default:00h +Attributes:Read/Write +7 6 5 4 3 21 0 +Reserved Char Map A Select (bit Char Map B Select (bit + Character Map A Character Map B Select +(00) 0) 0) + Select (bits 2 and 1) + (bits 2 and 1) + + + + Bit Descriptions +7:6 + Reserved. Read as 0s. + +3:2,5 + Character Map Select Bits for Character Map B. These three bits are used to select the character + map (character generator tables) to be used as the secondary character set (font). Note that the + numbering of the maps is not sequential. + Bit [3:2, 5] Map Number Table Location + 00,0 0 1st 8KB of plane 2 at offset 0 (default) + 00,1 4 2nd 8KB of plane 2 at offset 8K + 01,0 1 3rd 8KB of plane 2 at offset 16K + 01,1 5 4th 8KB of plane 2 at offset 24K + 10,0 2 5th 8KB of plane 2 at offset 32K + 10,1 6 6th 8KB of plane 2 at offset 40K + 11,0 3 7th 8KB of plane 2 at offset 48K + 11,1 7 8th 8KB of plane 2 at offset 56K +1:0,4 + Character Map Select Bits for Character Map A. These three bits are used to select the character + map (character generator tables) to be used as the primary character set (font). Note that the + numbering of the maps is not sequential. + Bit [1:0,4] Map Number Table Location + 00,0 0 1st 8KB of plane 2 at offset 0 (default) + 00,1 4 2nd 8KB of plane 2 at offset 8K + 01,0 1 3rd 8KB of plane 2 at offset 16K + 01,1 5 4th 8KB of plane 2 at offset 24K + 10,0 2 5th 8KB of plane 2 at offset 32K + 10,1 6 6th 8KB of plane 2 at offset 40K + 11,0 3 7th 8KB of plane 2 at offset 48K + 11,1 7 8th 8KB of plane 2 at offset 56K + +NOTES: +1. In text modes, bit 3 of the video data’s attribute byte normally controls the foreground intensity. This + bit may be redefined to control switching between character sets. This latter function is enabled + whenever there is a difference in the values of the Character Font Select A and the Character Font + Select B bits. If the two values are the same, the character select function is disabled and attribute + bit 3 controls the foreground intensity. +2. Bit 1 of the Memory Mode Register (SR04) must be set to 1 for the character font select function of + this register to be active. Otherwise, only character maps 0 and 4 are available. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 14 + 1.2.6 SR04 - Memory Mode Register +I/O (and Memory Offset) Address:3C5h (index=04h) +Default:00h +Attributes:Read/Write +7 4 3 2 1 0 +Reserved (0000)Chain 4Odd/EvenExtended MemoryReserved (0) + + + Bit Description +7:4 + Reserved. Read as 0. + +3 + Chain 4 Mode. The selections made by this bit affect both CPU Read and write accesses to the frame + buffer. + 0 = The manner in which the frame buffer memory is mapped is determined by the setting of bit 2 of this + register (default). + 1 = The frame buffer memory is mapped in such a way that the function of address bits 0 and 1 are + altered so that they select planes 0 through 3. This setting is used in mode x13 to allow all four planes to + be accessed via sequential addresses. + +2 + Odd/Even Mode. Bit 3 of this register must be set to 0 for this bit to be effective. The selections made by + this bit affect only non-paged CPU accesses to the frame buffer through the VGA aperture. + 0 = The frame buffer memory is mapped in such a way that the function of address bit 0 such that even + addresses select planes 0 and 2 and odd addresses select planes 1 and 3 (default). + 1 = Addresses sequentially access data within a bit map, and the choice of which map is accessed is + made according to the value of the Plane Mask Register (SR02). +1 + Extended Memory Enable. This bit must be set to 1 to enable the selection and use of character maps in + plane 2 via the Character Map Select Register (SR03). + 0 = Disable CPU accesses to more than the first 64KB of VGA standard memory (default). + 1 = Enable CPU accesses to the rest of the 256KB total VGA memory beyond the first 64KB. +0 + Reserved. Read as 0. + + + +1.2.7 SR07 - Horizontal Character Counter Reset +I/O (and Memory Offset) Address:3C5h (index=07h) +Default:00h +Attributes:Read/Write +For standard VGAs, writing this register (with any data) causes the horizontal character counter to be held +in reset (the character counter output will remain 0). It remained in reset until a write occurred to any other +sequencer register location with SRX set to an index of 0 through 6. In this implementation that sequence +has no such special effect. +The vertical line counter is clocked by a signal derived from the horizontal display enable (which does not +occur if the horizontal counter is held in reset). Therefore, if a write occurs to this register during the +vertical retrace interval, both the horizontal and vertical counters will be set to 0. A write to any other + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 15 + sequencer register location (with SRX set to an index of 0 through 6) may then be used to start both +counters with reasonable synchronization to an external event via software control. Although this was a +standard VGA register, it was not documented. + Bit Description +7:0 + Horizontal Character Counter. + + + +1.3 Graphics Controller Registers +The graphics controller registers are accessed via either I/O space or Memory space. Accesses to the +registers of the VGA Graphics Controller are done through the use of address 3CEh (or memory address +3CEh) written with the index of the desired register. Then the desired register is accessed through the +data port for the graphics controller registers at I/O address 3CFh (or memory address 3CFh). Indexes 10 +and 11 should only be accessed through the I/O space only. + + +1.3.1 GRX - GRX Graphics Controller Index Register +I/O (and Memory Offset) Address:3CEh +Default:000UUUUUb (U=Undefined) +Attributes:Read/Write +7 54 0 +Reserved (000)Graphics Controller Register Index + + + Bit Description + 7:5 + Reserved. Read as 0. + + 4:0 + Graphics Controller Register Index. This field selects any one of the graphics controller registers (GR00- + GR18) to be accessed via the data port at I/O (or memory offset) location 3CFh. + + + +1.3.2 GR00 - Set/Reset Register +I/O (and Memory Offset) Address:3CFh (index=00h) +Default:0Uh (U=Undefined) +Attributes:Read/Write +7 4 3 2 1 0 +Reserved (0000)Plane 3Plane 2Plane 1Plane 0 + + + Bit Description + 7:4 + Reserved. Read as 0. + + 3:0 + Set/Reset Plane [3:0]. When the Write Mode bits (bits 0 and 1) of the Graphics Mode Register (GR05) are + set to select Write Mode 0, all 8 bits of each byte of each memory plane are set to either 1 or 0 as + specified in the corresponding bit in this register, if the corresponding bit in the Enable Set/Reset Register + (GR01) is set to 1. + When the Write Mode bits (bits 0 and 1) of the Graphics Mode Register (GR05) are set to select Write + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 16 + Bit Description + Mode 3, all CPU data written to the frame buffer is rotated, then logically ANDed with the contents of the + Bit Mask Register (GR08), and then treated as the addressed data’s bit mask, while value of these four + bits of this register are treated as the color value. + + + +1.3.3 GR01 - Enable Set/Reset Register +I/O (and Memory Offset) Address:3CFh (Index=01h) +Default:0Uh (U=Undefined) +Attributes:Read/Write +7 4 3 2 1 0 +Reserved (0000) + Enable Enable Enable Enable + Set/ Reset Set/ Reset Set/ Reset Set/ Reset + Plane 3 Plane 2 Plane 1 Plane 0 + Bit Description +7:4 + Reserved. Read as 0. + +3:0 + Enable Set/Reset Plane [3:0]. + This register works in conjunction with the Set/Reset Register (GR00). The Write Mode bits (bits 0 and 1) + must be set for Write Mode 0 for this register to have any effect. + 0 = The corresponding memory plane can be read from or written to by the CPU without any special bitwise + operations taking place. + 1 = The corresponding memory plane is set to 0 or 1 as specified in the Set/Reset Register (GR00). + + + +1.3.4 GR02 - Color Compare Register +I/O (and Memory Offset) Address:3CFh (Index=02h) +Default:0Uh (U=Undefined) +Attributes:Read/Write +7 4 3 2 1 0 + Color Compare + Reserved + Plane Plane Plane Plane + (0000) + 3 2 1 0 + Bit Description +7:4 + Reserved. Read as 0. + +3:0 + Color Compare Plane [3:0]. When the Read Mode bit (bit 3) of the Graphics Mode Register (GR05) is + set to select Read Mode 1, all 8 bits of each byte of each of the 4 memory planes of the frame buffer + corresponding to the address from which a CPU read access is being performed are compared to the + corresponding bits in this register (if the corresponding bit in the Color Don’t Care Register (GR07) is + set to 1). + The value that the CPU receives from the read access is an 8-bit value that shows the result of this + comparison, wherein value of 1 in a given bit position indicates that all of the corresponding bits in the + bytes across all of the memory planes that were included in the comparison had the same value as + their memory plane’s respective bits in this register. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 17 + 1.3.5 GR03 - Data Rotate Register +I/O (and Memory Offset) Address:3CFh (Index=03h) +Default:0Uh (U=Undefined) +Attributes:Read/Write +7 54 32 0 +ReservedFunction SelectRotate Count + + + Bit Description + 7:5 + Reserved. Read as 0. + + 4:3 + Function Select. These bits specify the logical function (if any) to be performed on data that is meant to be + written to the frame buffer (using the contents of the memory read latch) just before it is actually stored in + the frame buffer at the intended address location. + 00 = Data being written to the frame buffer remains unchanged, and is simply stored in the frame buffer. + 01 = Data being written to the frame buffer is logically ANDed with the data in the memory read latch before + it is actually stored in the frame buffer. + 10 = Data being written to the frame buffer is logically ORed with the data in the memory read latch before + it is actually stored in the frame buffer. + 11 = Data being written to the frame buffer is logically XORed with the data in the memory read latch before + it is actually stored in the frame buffer. + + 2:0 + Rotate Count. These bits specify the number of bits to the right to rotate any data that is meant to be + written to the frame buffer just before it is actually stored in the frame buffer at the intended address + location. + + + +1.3.6 GR04 - Read Plane Select Register +I/O (and Memory Offset) Address:3CFh (Index=04h) +Default:0Uh (U=Undefined) +Attributes:Read/Write +7 21 0 +Reserved (000000)Read Plane Select + + + Bit Description + 7:2 + Reserved. Read as 0. + + 1:0 + Read Plane Select. These two bits select the memory plane from which the CPU reads data in Read + Mode 0. In Odd/Even Mode, bit 0 of this register is ignored. In Chain 4 Mode, both bits 1 and 0 of this + register are ignored. The four memory planes are selected as follows: + 00 = Plane 0 + 01 = Plane 1 + 10 = Plane 2 + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 18 + Bit Description + 11 = Plane 3 + These two bits also select which of the four memory read latches may be read via the Memory read + Latch Data Register (CR22). The choice of memory read latch corresponds to the choice of plane + specified in the table above. The Memory Read Latch Data register and this additional function served + by 2 bits are features of the VGA standard that were never documented. + + + +1.3.7 GR05 - Graphics Mode Register +I/O (and Memory Offset) Address:3CFh (Index=05h) +Default:0UUU U0UUb (U=Undefined) +Attributes:Read/Write + 7 6 5 4 3 2 1 0 +Reserved (0)Shift Register ControlOdd/EvenRead ModeReservedWrite Mode + + + Bit Description + 7 + Reserved. Read as 0. + + 6:5 + Shift Register Control. In standard VGA modes, pixel data is transferred from the 4 graphics memory + planes to the palette via a set of 4 serial output bits. These 2 bits of this register control the format in + which data in the 4 memory planes is serialized for these transfers to the palette. + Bits [6:5]=00 + One bit of data at a time from parallel bytes in each of the 4 memory planes is transferred to the palette + via the 4 serial output bits, with 1 of each of the serial output bits corresponding to a memory plane. + This provides a 4-bit value on each transfer for 1 pixel, making possible a choice of 1 of 16 colors per + pixel. + Serial + Out 1st Xfer 2nd Xfer 3rd Xfer 4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer + Bit 3 plane3 bit7 plane3 bit6 plane3 bit5 plane3 bit4 plane3 bit3 plane3 bit2 plane3 bit1 plane3 bit0 + Bit 2 plane2 bit7 plane2 bit6 plane2 bit5 plane2 bit4 plane2 bit3 plane2 bit2 plane2 bit1 plane2 bit0 + Bit 1 plane1 bit7 plane1 bit6 plane1 bit5 plane1 bit4 plane1 bit3 plane1 bit2 plane1 bit1 plane1 bit0 + Bit 0 plane0 bit7 plane0 bit6 plane0 bit5 plane0 bit4 plane0 bit3 plane0 bit2 plane0 bit1 plane0 bit0 + Bits [6:5]=01 + Two bits of data at a time from parallel bytes in each of the 4 memory planes are transferred to the + palette in a pattern that alternates per byte between memory planes 0 and 2, and memory planes 1 and + 3. First the even-numbered and odd-numbered bits of a byte in memory plane 0 are transferred via + serial output bits 0 and 1, respectively, while the even-numbered and odd-numbered bits of a byte in + memory plane 2 are transferred via serial output bits 2 and 3. Next, the even-numbered and odd- + numbered bits of a byte in memory plane 1 are transferred via serial output bits 0 and 1, respectively, + while the even-numbered and odd-numbered bits of memory plane 3 are transferred via serial out bits 1 + and 3. This provides a pair of 2-bit values (one 2-bit value for each of 2 pixels) on each transfer, making + possible a choice of 1 of 4 colors per pixel. + Serial + Out 1st Xfer 2nd Xfer 3rd Xfer 4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer + Bit 3 plane2 bit7 plane2 bit5 plane2 bit3 plane2 bit1 plane3 bi7t plane3 bit5 plane3 bit3 plane3 bit1 + Bit 2 plane2 bit6 plane2 bit4 plane2 bit2 plane2 bit0 plane3 bit6 plane3 bit4 plane3 bit2 plane3 bit0 + Bit 1 plane0 bit7 plane0 bit5 plane0 bit3 plane0 bit1 plane1 bit7 plane1 bit5 plane1 bit3 plane1 bit1 + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 19 + Bit Description + Bit 0 plane0 bit6 plane0 bit4 plane0 bit2 plane0 bit0 plane1 bit6 plane1 bit4 plane1 bit2 plane1 bit0 + This alternating pattern is meant to accommodate the use of the Odd/Even mode of organizing the 4 + memory planes, which is used by standard VGA modes 2h and 3h. + Bits [6:5]=1x + Four bits of data at a time from parallel bytes in each of the 4 memory planes are transferred to the + palette in a pattern that iterates per byte through memory planes 0 through 3. First the 4 most + significant bits of a byte in memory plane 0 are transferred via the 4 serial output bits, followed by the 4 + least significant bits of the same byte. Next, the same transfers occur from the parallel byte in memory + planes 1, 2 and lastly, 3. Each transfer provides either the upper or lower half of an 8 bit value for the + color for each pixel, making possible a choice of 1 of 256 colors per pixel. This is the setting used in + mode x13. + Serial + Out 1st Xfer 2nd Xfer 3rd Xfer 4th Xfer 5th Xfer 6th Xfer 7th Xfer 8th Xfer + Bit 3 plane0 bit7 plane0 bit3 plane1 bit7 plane1 bit3 plane2 bit7 plane2 bit3 plane3 bit7 plane3 b3it + Bit 2 plane0 bit6 plane0 bit2 plane1 bit6 plane1 bit2 plane2 bit6 plane2 bit2 plane3 bit6 plane3 bit2 + Bit 1 plane0 bit5 plane0 bit1 plane1 bit5 plane1 bit1 plane2 bit5 plane2 bit1 plane3 bit5 plane3 bit1 + Bit 0 plane0 bit4 plane0 bit0 plane1 bit4 plane1 bit0 plane2 bit4 plane2 bit0 plane3 bit4 plane3 bit0 + This pattern is meant to accommodate mode 13h, a standard VGA 256-color graphics mode. + + + 4 + Odd/Even Mode. + Addresses sequentially access data within a bit map, and the choice of which map is accessed is + 0= + made according to the value of the Plane Mask Register (SR02). + The frame buffer is mapped in such a way that the function of address bit 0 is such that even + 1= + addresses select memory planes 0 and 2 and odd addresses select memory planes 1 and 3. + Note:This works in a way that is the inverse of (and is normally set to be the opposite of) bit 2 of the + Memory Mode Register (SR02). + + + 3 + Read Mode. + During a CPU read from the frame buffer, the value returned to the CPU is data from the + 0= + memory plane selected by bits 1 and 0 of the Read Plane Select Register (GR04). + During a CPU read from the frame buffer, all 8 bits of the byte in each of the 4 memory + 1= + planes corresponding to the address from which a CPU read access is being performed are + compared to the corresponding bits in this register (if the corresponding bit in the Color Don’t + Care Register (GR07) is set to 1). The value that the CPU receives from the read access is + an 8-bit value that shows the result of this comparison. A value of 1 in a given bit position + indicates that all of the corresponding bits in the bytes across all 4 of the memory planes + that were included in the comparison had the same value as their memory plane’s + respective bits in this register. + 2 + Reserved. Read as 0. + + 1:0 + Write Mode. + Write Mode 0 - During a CPU write to the frame buffer, the addressed byte in each of the 4 + 00 = + memory planes is written with the CPU write data after it has been rotated by the number of + counts specified in the Data Rotate Register (GR03). If, however, the bit(s) in the Enable + Set/Reset Register (GR01) corresponding to one or more of the memory planes is set to 1, + then those memory planes will be written to with the data stored in the corresponding bits in + the Set/Reset Register (GR00). + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 20 + Bit Description + Write Mode 1 - During a CPU write to the frame buffer, the addressed byte in each of the 4 + 01 = + memory planes is written to with the data stored in the memory read latches. (The memory + read latches stores an unaltered copy of the data last read from any location in the frame + buffer.) + Write Mode 2 - During a CPU write to the frame buffer, the least significant 4 data bits of the + 10 = + CPU write data is treated as the color value for the pixels in the addressed byte in all 4 + memory planes. The 8 bits of the Bit Mask Register (GR08) are used to selectively enable or + disable the ability to write to the corresponding bit in each of the 4 memory planes that + correspond to a given pixel. A setting of 0 in a bit in the Bit Mask Register at a given bit + position causes the bits in the corresponding bit positions in the addressed byte in all 4 + memory planes to be written with value of their counterparts in the memory read latches. A + setting of 1 in a Bit Mask Register at a given bit position causes the bits in the corresponding + bit positions in the addressed byte in all 4 memory planes to be written with the 4 bits taken + from the CPU write data to thereby cause the pixel corresponding to these bits to be set to + the color value. + Write Mode 3 - During a CPU write to the frame buffer, the CPU write data is logically ANDed + 11 = + with the contents of the Bit Mask Register (GR08). The result of this ANDing is treated as the + bit mask used in writing the contents of the Set/Reset Register (GR00) are written to + addressed byte in all 4 memory planes. + + +1.3.8 GR06 - Miscellaneous Register +I/O (and Memory Offset) Address:3CFh (Index=06h) +Default: 0Uh (U=Undefined) +Attributes:Read/Write +7 43 2 1 0 +Reserved (0000)Memory Map ModeChain Odd/EvenGraphics / Text Mode + + + Bit Description + 7:4 + Reserved. Read as 0s. + + 3:2 Memory Map Mode. + These 2 bits control the mapping of the VGA address range for frame buffer into the CPU address space as + follows: + + + 00 = A0000h - BFFFFh + 01 = A0000h - AFFFFh + 10 = B0000h - B7FFFh + 11 = B8000h - BFFFFh + + + + + Note: +  This function is used in standard VGA modes, extended VGA modes (132 column text), and in non-VGA + modes (hi-res). 132 column text modes are no longer supported. +  VGA aperture memory accesses are also controlled by the PCI configuration Memory Enable bit and + MSR<1>. +  For accesses using GR10 and GR11 to paged VGA RAM or to device MMIO registers, set these bits to + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 21 + Bit Description + 01 to select the (A0000-AFFFF) range. +  The CPU must map this memory as uncacheable (UC). + + Chain Odd/Even. + 1 This bit provides the ability to alter the interpretation of address bit A0, so that it may be used in selecting + between the odd-numbered memory planes (planes 1 and 3) and the even-numbered memory planes (planes + 0 and 2). + + + 0 = A0 functions normally. + 1 = A0 is switched with a high order address bit, in terms of how it is used in address decoding. The result is + that A0 is used to determine which memory plane is being accessed + (A0=0 for planes 0 and 2 and A0=1 for planes 1 and 3). + 0 Graphics/Text Mode. + This is one of two bits that are used to determine if the VGA is operating in text or graphics modes. The other + bit is in AR10[0], these two bits need to be programmed in a consistent manner to achieve the proper results. + + + 0 = Text mode. + 1 = Graphics mode. + + + +1.3.9 GR07 - Color Don’t Care Register +I/O (and Memory Offset) Address:3CFh (Index=07h) +Default: 0Uh (U=Undefined) +Attributes:Read/Write +7 4 3 2 1 0 +Reserved (0000) + Ignore Ignore Ignore Ignore + Color Plane 3 Color Plane 2 Color Plane 1 Color Plane 0 + + + + Bit Description + 7:4 + Reserved. Read as 0. + + 3:0 + Ignore Color Plane [3:0]. Note that these bits have effect only when bit 3 of the Graphics Mode Register + (GR05) is set to 1 to select read mode 1. + 0 = The corresponding bit in the Color Compare Register (GR02) will not be included in color + comparisons. + 1 = The corresponding bit in the Color Compare Register (GR02) is used in color comparisons. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 22 + 1.3.10 GR08 - Bit Mask Register +I/O (and Memory Offset) Address:3CFh (Index=08h) +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Bit Mask. + 0 = The corresponding bit in each of the 4 memory planes is written to with the corresponding bit in the + memory read latches. + 1 = Manipulation of the corresponding bit in each of the 4 memory planes via other mechanisms is enabled. + Notes: +  This bit mask applies to any writes to the addressed byte of any or all of the 4 memory planes, + simultaneously. +  This bit mask is applicable to any data written into the frame buffer by the CPU, including data that is + also subject to rotation, logical functions (AND, OR, XOR), and Set/Reset. To perform a proper read- + modify-write cycle into frame buffer, each byte must first be read from the frame buffer by the CPU + (and this will cause it to be stored in the memory read latches), this Bit Mask Register must be set, and + the new data then written into the frame buffer by the CPU. + + + +1.3.11 GR10 - Address Mapping +I/O (avoid MMIO access) Address:3CFh (Index=10h) +Default:00h +Attributes:R/W +This register should only be accessed using I/O operations and never be accessed through the A/B +segment addressing map, I/O space register map, or direct MMIO operations. + Bit Description + 7:4 Page Select Extension - Unused + These bits form the upper bits of a 12-bit page selection value. When combined with the GR11 <7:0> bits + they define the offset into stolen memory to the 64KB page that is accessible via the VGA Memory paging + mechanism. + These bits are ignored. + 3 + Reserved + + 2:1 Paging Map Target. + When paging is enabled, these bits determine the target for data cycle accesses through the VGA memory + aperture. + + + VGA graphics memory starts from the base of graphics data stolen memory defined in the PCI + configuration BDSM register. + + + + + VGA display uses the first four 64KB pages of VGA graphics memory. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 23 + Bit Description + + + 00 = VGA Graphics Memory + 01 = Reserved + 10 = Reserved + 11 = Reserved + 0 Page Mapping Enable. + This mode allows the mapping of the VGA memory address space. + + Some Notes on Paging. + Once this is enabled, no VGA memory address swizzel will be performed, addresses are directly mapped to + memory. + A single paging register is used to map the 64KB [A0000:AFFFF] window. An internal address is generated + using GR11 as the address lines extension to the lower address lines of the access A[15:2]. + + + When mapping is enabled, the B0000:BFFFF area must be disabled using GR06<3:2>=01. + The use of addresses in the A0000-BFFFF range require that both the graphics device PCI configuration + memory enable and MSR<1> be enabled. + + + + 0 = Disable (default) + 1 = Enable + + + +1.3.12 GR11 - Page Selector +I/O Address (avoid MMIO access):3CFh (Index=11h) +Default: 00h +Attributes:R/W + Bit Description + 7 + Reserved + + 6:0 Page Select. + When concatenated with the GR10<7:4> bits, selects a 64KB window within target area when Page + Mapping is enabled (GR10[0]=1). + This requires that the graphics device PCI configuration space memory enable, the GR06<3:2> bits to be + 01 (select A0000-AFFFF only), and the MSR<1:1> bit to be set. + This register provides the Address[22:16] bits for the access. + VGA paging of frame buffer memory is for non-VGA packed modes only and should not be enabled when + using basic VGA modes. + This register should only be accessed using I/O operations. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 24 + 1.3.13 GR18 - Software Flags +I/O (and Memory Offset) Address:3CFh (Index=18h) +Default: 00 +Attribute:R/W + Bit Description + 7:0 + Software Flags. Used as scratch pad space in video BIOS. These bits are separate from the bits which + appear in the memory mapped IO space. They are used specifically by the SMI BIOS which does not + have access to memory mapped IO at the time they are required. These register bits have no effect on + H/W operation. + + + +1.4 Attribute Controller Registers +Unlike the other sets of indexed registers, the attribute controller registers are not accessed through a +scheme employing entirely separate index and data ports. I/O address 3C0h (or memory address 3C0h) +is used both as the read and write for the index register, and as the write address for the data port. I/O +address 3C1h (or memory address 3C1h) is the read address for the data port. +To write to the attribute controller registers, the index of the desired register must be written to I/O +address 3C0h (or memory address 3C0h), and then the data is written to the very same I/O (memory) +address. A flip-flop alternates with each write to I/O address 3C0h (or memory address 3C0h) to change +its function from writing the index to writing the actual data, and back again. This flip-flop may be +deliberately set so that I/O address 3C0h (or memory address 3C0h) is set to write to the index (which +provides a way to set it to a known state) by performing a read operation from Input Status Register 1 +(ST01) at I/O address 3BAh (or memory address 3BAh) or 3DAh (or memory address 3DAh), depending +on whether the graphics system has been set to emulate an MDA or a CGA as per MSR[0]. +To read from the attribute controller registers, the index of the desired register must be written to I/O +address 3C0h (or memory address 3C0h), and then the data is read from I/O address 3C1h (or memory +address 3C1h). A read operation from I/O address 3C1h (or memory address 3C1h) does not reset the +flip-flop to writing to the index. Only a write to 3C0h (or memory address 3C0h) or a read from 3BAh or +3DAh (or memory address 3BAh or 3DAh), as described above, will toggle the flip-flop back to writing to +the index. + + +1.4.1 ARX - Attribute Controller Index Register +I/O (and Memory Offset) Address:3C0h +Default:00UU UUUUb (U=Undefined) +Attributes:Read/Write +7 6 5 4 0 +Reserved (00)Video EnableAttribute Controller Register Index + + + Bit Description +7:6 + Reserved. Read as 0s. + +5 + Video Enable. Note that In the VGA standard, this is called the “Palette Address Source” bit. Clearing this bit + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 25 + Bit Description + will cause the VGA display data to become all 00 index values. For the default palette, this will cause a black + screen. The video timing signals continue. Another control bit will turn video off and stop the data fetches. + 0 = Disable. Attribute controller color registers (AR[00:0F]) can be accessed by the CPU. + 1 = Enable. Attribute controller color registers (AR[00:0F]) are inaccessible by the CPU. +4:0 + Attribute Controller Register Index. These five bits are used to select any one of the attribute controller + registers (AR[00:14]), to be accessed. + + + + + Note:AR12 is referred to in the VGA standard as the Color Plane Enable Register. The words “plane,” “color + plane,” “display memory plane,” and “memory map” have been all been used in literature on the VGA + standard to describe the four separate regions in the frame buffer where the pixel color or attribute + information is split up and stored in standard VGA planar modes. This use of multiple terms for the same + subject was deemed to be confusing, therefore, AR12 is called the Memory Plane Enable Register. Attribute + Controller Register Index. + + + +1.4.2 AR[00:0F] - Palette Registers [0:F] +I/O (and Memory Offset) Address:Read at 3C1h and Write at 3C0h; (index=00h-0Fh) +Default:00UU UUUUb (U=Undefined) +Attributes:Read/Write +7 65 0 +ReservedPalette Bits P[5:0] + + + Bit Description +7:6 + Reserved. Read as 0. + +5:0 + Palette Bits P[5:0]. In each of these 16 registers, these are the lower 6 of 8 bits that are used to map either + text attributes or pixel color input values (for modes that use 16 colors) to the 256 possible colors available to + be selected in the palette. + + + + + Note:Bits 3 and 2 of the Color Select Register (AR14) supply bits P7 and P6 for the values contained in all + 16 of these registers. Bits 1 and 0 of the Color Select Register (AR14) can also replace bits P5 and P4 for + the values contained in all 16 of these registers, if bit 7 of the Mode Control Register (AR10) is set to 1. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 26 + 1.4.3 AR10 - Mode Control Register +I/O (and Memory Offset) Address: Read at 3C1h and Write at 3C0h; (index=10h) +Default: UUh (U=Undefined) +Attributes: Read/Write + + + + 7 6 5 4 3 2 1 0 + Palette Bits Pixel Width/ Pixel Reserved Enable Line Select Graphics/ + Enable Blink/ +P5, P4 Select Clock Select Panning (0) Graphics Char Display Alpha + Select Bkgnd + Compat Code Type Mode + Int + + + + Bit Description + 7 + Palette Bits P5, P4 Select. + 0 = P5 and P4 for each of the 16 selected colors (for modes that use 16 colors) are individually provided by + bits 5 and 4 of their corresponding Palette Registers (AR[00:0F]). + 1 = P5 and P4 for all 16 of the selected colors (for modes that use 16 colors) are provided by bits 1 and 0 of + Color Select Register (AR14). + 6 + Pixel Width/Clock Select. + 0 = Six bits of video data (translated from 4 bits via the palette) are output every dot clock. + 1 = Two sets of 4 bits of data are assembled to generate 8 bits of video data which is output every other dot + clock, and the Palette Registers (AR[00:0F]) are bypassed. + Note: This bit is set to 0 for all of the standard VGA modes, except mode 13h. + + 5 + Pixel Panning Compatibility. + 0 = Scroll both the upper and lower screen regions horizontally as specified in the Pixel Panning Register + (AR13). + 1 = Scroll only the upper screen region horizontally as specified in the Pixel Panning Register (AR13). + Note: This bit has application only when split-screen mode is being used, where the display area is divided + into distinct upper and lower regions which function somewhat like separate displays. + 4 + Reserved. Read as 0. + + 3 + Enable Blinking/Select Background Intensity. + 0 = Disables blinking in graphics modes, and for text modes, sets bit 7 of the character attribute bytes to + control background intensity, instead of blinking. + 1 = Enables blinking in graphics modes and for text modes, sets bit 7 of the character attribute bytes to control + blinking, instead of background intensity. + Note: The blinking rate is derived by dividing the VSYNC signal. The Blink Rate Control field of the VGA + control register defines the blinking rate. + 2 + Enable Line Graphics Character Code. + 0 = Every 9th pixel of a horizontal line (i.e., the last pixel of each horizontal line of each 9-pixel wide character + box) is assigned the same attributes as the background of the character of which the given pixel is a part. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 27 + Bit Description + 1 = Every 9th pixel of a horizontal line (i.e., the last pixel of each horizontal line of each 9-pixel wide character + box) is assigned the same attributes as the 8th pixel if the character of which the given pixel is a part. This + setting is intended to accommodate the line-drawing characters of the PC’s extended ASCII character set -- + characters with an extended ASCII code in the range of B0h to DFh. + Note: In some literature describing the VGA standard, the range of extended ASCII codes that are said to + include the line-drawing characters is mistakenly specified as C0h to DFh, rather than the correct range of + B0h to DFh. + 1 + Select Display Type. + 0 = Attribute bytes in text modes are interpreted as they would be for a color display. + 1 = Attribute bytes in text modes are interpreted as they would be for a monochrome display. + + 0 + Graphics/Alphanumeric Mode. This bit (along with GR06[0]) select either graphics mode or text mode. + These two bits must be programmed in a consistent manner to achieve the desired results. + 0 = Alphanumeric (text) mode. + 1 = Graphics mode. + + + +1.4.4 AR12 - Memory Plane Enable Register +I/O (and Memory Offset) Address:Read at 3C1h and Write at 3C0h; (index=12h) +Default:00UU UUUUb (U=Undefined) +Attributes:Read/Write +7 65 4 3 2 1 0 +Reserved (00)Video Status MuxEnable Plane 3Enable Plane 2Enable Plane 1Enable Plane 0 + + + Bit Description + 7:6 + Reserved. Read as 0. + + 5:4 + Video Status Mux. These 2 bits are used to select 2 of the 8 possible palette bits (P7-P0) to be made + available to be read via bits 5 and 4 of the Input Status Register 1 (ST01). The table below shows the + possible choices. + + + + Bit [5:4] ST01 Bit 5 ST01 Bit 4 + 00 P2 (default) P0 (default) + 01 P5 P4 + 10 P3 P1 + 11 P7 P6 + These bits are typically unused by current software; they are provided for EGA compatibility. + + + 3:0 + Enable Plane [3:0]. These 4 bits individually enable the use of each of the 4 memory planes in providing 1 + of the 4 bits used in video output to select 1 of 16 possible colors from the palette to be displayed. + + + + 0= Disable the use of the corresponding memory plane in video output to select colors, forcing the bit + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 28 + Bit Description + that the corresponding memory plane would have provided to a value of 0. + 1= Enable the use of the corresponding memory plane in video output to select colors. + + + + Note: AR12 is referred to in the VGA standard as the Color Plane Enable Register. The words “plane,” + “color plane,” “display memory plane,” and “memory map” have been all been used in literature on the VGA + standard to describe the 4 separate regions in the frame buffer that are amongst which pixel color or + attributes information is split up and stored in standard VGA planar modes. This use of multiple terms for + the same subject was considered confusing; therefore, AR12 is called the Memory Plane Enable Register. + + + + +1.4.5 AR13 - Horizontal Pixel Panning Register +I/O (and Memory Offset) Address:Read at 3C1h and Write at 3C0h; (index=13h) +Default:0Uh (U=Undefined) +Attributes:Read/Write +7 43 0 +Reserved (0000)Horizontal Pixel Shift + + + Bit Description + 7:4 + Reserved. + + 3:0 + Horizontal Pixel Shift 3-0. This field holds a 4-bit value that selects the number of pixels by which the + image is shifted horizontally to the left. This function is available in both text and graphics modes and allows + for pixel panning. + In text modes with a 9-pixel wide character box, the image can be shifted up to 9 pixels to the left. In text + modes with an 8-pixel wide character box, and in graphics modes other than those with 256 colors, the + image can be shifted up to 8 pixels to the left. A pseudo 9-bit mode is when the 9-dot character is selected + but overridden by the VGA control bit. + In standard VGA mode 13h (where bit 6 of the Mode Control Register, AR10, is set to 1 to support 256 + colors), bit 0 of this register must remain set to 0, and the image may be shifted up to only 4 pixels to the + left. In this mode, the number of pixels by which the image is shifted can be further controlled using bits 6 + and 5 of the Preset Row Scan Register (CR08). + Number of Pixels Shifted + Bits [3:0] 9-dot Pseudo 9-dot 8-dot 256-Color + 0 1 1 0 0 + 1 2 2 1 Undefined + 2 3 3 2 1 + 3 4 4 3 Undefined + 4 5 5 4 2 + 5 6 6 5 Undefined + 6 7 7 6 3 + 7 8 7 7 Undefined + 8 0 0 Undefined Undefined + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 29 + 1.4.6 AR14 - Color Select Register +I/O (and Memory Offset) Address:Read at 3C1h and Write at 3C0h; (index=14h) +Default:0Uh (U=Undefined) +Attributes:Read/Write +7 4 3 2 1 0 + Reserved (0000) P7 P6 Alt P5 Alt P4 + + + Bit Description + 7:4 + Reserved. + + 3:2 + Palette Bits P[7:6]. These are the 2 upper-most of the 8 bits that are used to map either text attributes or + pixel color input values (for modes that use 16 colors) to the 256 possible colors contained in the palette. + These 2 bits are common to all 16 sets of bits P5 through P0 that are individually supplied by Palette + Registers 0-F (AR[00:0F]). + + 1:0 + Alternate Palette Bits P[5:4]. These 2 bits can be used as an alternate version of palette bits P5 and P4. + Unlike the P5 and P4 bits that are individually supplied by Palette Registers 0-F (AR[00:0F]), these 2 + alternate palette bits are common to all 16 of Palette Registers. Bit 7 of the Mode Control Register (AR10) + is used to select between the use of either the P5 and P4 bits that are individually supplied by the 16 + Palette Registers or these 2 alternate palette bits. + + + +1.5 VGA Color Palette Registers +In devices that have multiple display pipes, there is one palette for each display pipe. These palettes are +the same for VGA modes and non-VGA modes. Accesses through VGA register methods can optionally +read or write from either one. +For each palette, the color data stored in these 256 color data positions can be accessed only through a +complex sub-addressing scheme, using a data register and two index registers. The Palette Data +Register at I/O address 3C9h (or memory address offset 3C1h) is the data port. The Palette Read Index +Register at I/O address 3C7h (or memory address offset 3C7h) and the Palette Write Index Register at +I/O address 3C8h (or memory address offset 3C8h) are the two index registers. The Palette Read Index +Register is the index register that is used to choose the color data position that is to be read from via the +data port, while the Palette Write Index Register is the index register that is used to choose the color data +position that is to be written to through the same data port. This arrangement allows the same data port to +be used for reading from and writing to two different color data positions. Reading and writing the color +data at a color data position involves three successive reads or writes since the color data stored at each +color data position consists of three bytes. +To read a palette color data position, the index of the desired color data position must first be written to +the Palette Read Index Register. Then all three bytes of data in a given color data position may be read at +the Palette Data Register. The first byte read from the Palette Data Register retrieves the 8-bit value +specifying the intensity of the red color component. The second and third bytes read are the +corresponding 8-bit values for the green and blue color components respectively. After completing the +third read operation, the Palette Read Index Register is automatically incremented so that the data of the +next color data position becomes accessible for being read. This allows the contents of all of the 256 + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 30 + color data positions of the palette to be read in sequence. This is done by specifying only the index of the +0th color data position in the Palette Read Index Register, and then simply performing 768 successive +reads from the Palette Data Register. +Writing a color data position, entails a very similar procedure. The index of the desired color data position +must first be written to the Palette Write Index Register. Then all three bytes of data to specify a given +color may be written to the Palette Data Register. The first byte written to the Palette Data Register +specifies the intensity of the red color component, the second byte specifies the intensity for the green +color component, and the third byte specifies the same for the blue color component. One important detail +is that all three of these bytes must be written before the hardware will actually update these three values +in the given color data position. When all three bytes have been written, the Palette Write Index Register +is automatically incremented so that the data of the next color data position becomes accessible for being +written. This allows the contents of all of the 256 color data positions of the palette to be written in +sequence. This is done by specifying only the index of the 0th color data position in the Palette Write +Index Register, and then simply performing 768 successive writes to the Palette Data Register. + + +1.5.1 DACMASK - Pixel Data Mask Register +I/O (and Memory Offset) Address:3C6h +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Pixel Data Mask. In indexed-color mode, the 8 bits of this register are logically ANDed with the 8 bits of + pixel data received from the frame buffer for each pixel. The result of this ANDing process becomes the + actual index used to select color data positions within the palette. This has the effect of limiting the choice + of color data positions that may be specified by the incoming 8-bit data. + 0 = Corresponding bit in the resulting 8-bit index being forced to 0. + 1 = Allows the corresponding bit in the resulting index to reflect the actual value of the corresponding bit in + the incoming 8-bit pixel data. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 31 + 1.5.2 DACSTATE – DAC State Register +I/O (and Memory Offset) Address:3C7h +Default:00h +Attributes:Read Only +7 21 0 +Reserved (000000)DAC State + + + Bit Description + 7:2 + Reserved. Read as 0. + + 1:0 + DACState. This field indicates which of the two index registers was most recently written. + Bits [1:0] Index Register Indicated + 00 = Palette Write Index Register at I/O Address 3C7h (default) + 01 = Reserved + 10 = Reserved + 11 = Palette Read Index Register at I/O Address 3C8h + + + +1.5.3 DACRX - Palette Read Index Register +I/O (and Memory Offset) Address:3C7h +Default:00h +Attributes:Write Only + Bit Description + 7:0 + Palette Read Index. The 8-bit index value programmed into this register chooses which of 256 standard + color data positions within the palette are to be made accessible for being read from via the Palette Data + Register (DACDATA). The index value held in this register is automatically incremented when all three bytes + of the color data position selected by the current index have been read. A write to this register will abort a + uncompleted palette write sequence. This register allows access to the palette even when running non-VGA + display modes. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 32 + 1.5.4 DACWX - Palette Write Index Register +I/O (and Memory Offset) Address:3C8h +Default:00h +Attributes:Write Only + Bit Description + 7:0 + Palette Write Index. The 8-bit index value programmed into this register chooses which of 256 + standard color data positions within the palette are to be made accessible for being written via the + Palette Data Register (DACDATA). The index value held in this register is automatically incremented + when all three bytes of the color data position selected by the current index have been written. This + register allows access to the palette even when running non-VGA display modes. + + + +1.5.5 DACDATA - Palette Data Register +I/O (and Memory Offset) Address:3C9h +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Palette Data. This byte-wide data port provides read or write access to the three bytes of data of each + color data position selected using the Palette Read Index Register (DACRX) or the Palette Write Index + Register (DACWX). + The three bytes in each color data position are read or written in three successive read or write + operations. The first byte read or written specifies the intensity of the red component of the color + specified in the selected color data position. The second byte is for the green component, and the third + byte is for the blue component. When writing data to a color data position, all three bytes must be written + before the hardware will actually update the three bytes of the selected color data position. + When reading or writing to a color data position, ensure that neither the Palette Read Index Register + (DACRX) or the Palette Write Index Register (DACWX) are written to before all three bytes are read or + written. A write to either of these two registers causes the circuitry that automatically cycles through + providing access to the bytes for red, green and blue components to be reset such that the byte for the + red component is the one that will be accessed by the next read or write operation via this register. This + register allows access to the palette even when running non-VGA display modes. Writes to the palette + can cause sparkle if not done during inactive video periods. This sparkle is caused by an attempt to write + and read the same address on the same cycle. Anti-sparkle circuits will substitute the previous pixel + value for the read output. + + + +1.6 CRT Controller Register +For native VGA modes, the CRTC registers determine the display timing that is to be used. In centered +VGA modes, these registers determine the size of the VGA image that is to be centered in the larger +timing generator defined rectangle. +The CRT controller registers are accessed by writing the index of the desired register into the CRT +Controller Index Register at I/O address 3B4h or 3D4h, depending on whether the graphics system is +configured for MDA or CGA emulation. The desired register is then accessed through the data port for the +CRT controller registers located at I/O address 3B5h or 3D5h, again depending upon the choice of MDA + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 33 + or CGA emulation as per MSR[0]. For memory mapped accesses, the Index register is at 3B4h (MDA +mode) or 3D3h (CGA mode) and the data port is accessed at 3B5h (MDA mode) or 3D5h (CGA mode). +Note: + 1. Group 0 Protection: In the original VGA, CR[0:7] could be made write-protected by CR11[7]. + In BIOS code, this write protection is set following each mode change. Other protection groups + have no current use, and would not be used going forward by the BIOS or by drivers. They are + the result of an industry fad some years ago to attempt to write protect other groups of + registers; however, all such schemes were chip specific. Only the write protection (Group 0 + Protection) is supported. +The following figure shows display fields and dimensions and the particular CRxx register that provides +the control. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 34 + 1.6.1 CRX - CRT Controller Index Register +I/O (and Memory Offset) Address:3B4h/3D4h +Default:0Uh (U=Undefined) +Attributes:Read/Write + Bit Description + 7 + Reserved. Read as 0. + + 6:0 + CRT Controller Index. These 7 bits are used to select any one of the CRT controller registers to be + accessed via the data port at I/O location 3B5h or 3D5h, depending upon whether the graphics system is + configured for MDA or CGA emulation. The data port memory address offsets are 3B5h/3D5h. + + + +1.6.2 CR00 - Horizontal Total Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=00h) +Default:00h +Attributes:Read/Write (Group 0 Protection) + Bit Description + 7:0 + Horizontal Total. This register is used to specify the total length of each scan line. This encompasses both + the part of the scan line that is within the active display area and the part that is outside of it. Programming + this register to a zero has the effect of stopping the fetching of display data. + This field should be programmed with a value equal to the total number of character clocks within the entire + length of a scan line, minus 5. + + + + +1.6.3 CR01 - Horizontal Display Enable End Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=01h) +Default:Undefined +Attributes:Read/Write (Group 0 Protection) + Bit Description + 7:0 + Horizontal Display Enable End. This register is used to specify the end of the part of the scan line that is + within the active display area relative to its beginning. In other words, this is the horizontal width of the active + display area. + This field should be programmed with a value equal to the number of character clocks that occur within the + horizontal active display area, minus 1. Horizontal display enable will go active at the beginning of each line + during vertical active area, it will go inactive based on the programming of this register or the programming + of the horizontal total (CR00) register. When this register value is programmed to a number that is larger + than the total number of characters on a line, display enable will be active for all but the last character of the + horizontal display line. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 35 + 1.6.4 CR02 - Horizontal Blanking Start Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=02h) +Default:Undefined +Attributes:Read/Write (Group 0 Protection) + Bit Description + 7:0 + Horizontal Blanking Start. This register is used to specify the beginning of the horizontal blanking period + relative to the beginning of the active display area of a scan line. Horizontal blanking should always be set + to start no sooner than after the end of horizontal active. + This field should be programmed with a value equal to the number of character clocks that occur on a scan + line from the beginning of the active display area to the beginning of the horizontal blanking. + + + +1.6.5 CR03 - Horizontal Blanking End Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=03h) +Default:1UUU UUUUb (U=Undefined) +Attributes:Read/Write (Group 0 Protection) + 7 6 54 0 +ReservedDisplay Enable Skew ControlHorizontal Blanking End Bits 4:0 + + + Bit Description + 7 + Reserved. Values written to this bit are ignored, and to maintain consistency with the VGA standard, a value + of 1 is returned when this bit is read. At one time, this bit was used to enable access to certain light pen + registers. At that time, setting this bit to 0 provided this access, but setting this bit to 1 was necessary for + normal operation. + 6:5 + Display Enable Skew Control. Defines the degree to which the start and end of the active display area are + delayed along the length of a scan line to compensate for internal pipeline delays. These 2 bits describe the + delay in terms of a number character clocks. + Bit [6:5] Amount of Delay + 00 = no delay + 01 = delayed by 1 character clock + 10 = delayed by 2 character clocks + 11 = delayed by 3 character clocks + + 4:0 + Horizontal Blanking End Bits [4:0]. This field provides the 5 least significant bits of a 6-bit value that + specifies the end of the blanking period relative to its beginning on a single scan line. Bit 7 of the Horizontal + Sync End Register (CR05) supplies the most significant bit. + This 6-bit value should be programmed to be equal to the least significant 6 bits of the result of adding the + length of the blanking period in terms of character clocks to the value specified in the Horizontal Blanking + Start Register (CR02). End of blanking should occur before horizontal total. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 36 + 1.6.6 CR04 - Horizontal Sync Start Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=04h) +Default:Undefined +Attributes:Read/Write (Group 0 Protection) + Bit Description + 7:0 + Horizontal Sync Start This register is used to specify the position of the beginning of the horizontal sync + pulse relative to the start of the active display area on a scan line. + This field should be set equal to the number of character clocks that occur from beginning of the active + display area to the beginning of the horizontal sync pulse on a single scan line. Horizontal sync should + always occur at least 2 clocks after the start of horizontal blank and 2 clocks before the end of horizontal + blank. The actual start of sync will also be affected by both the horizontal sync skew register field and + whether it is a text or graphics mode. + + + +1.6.7 CR05 - Horizontal Sync End Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=05h) +Default:00h +Attributes:Read/Write (Group 0 Protection) + 7 6 54 0 +Hor Blank End <5>Horizontal Sync DelayHorizontal Sync End + + + Bit Description + 7 + Horizontal Blanking End Bit 5. This bit provides the most significant bit of a 6-bit value that specifies the + end of the horizontal blanking period relative to its beginning. Bits [4:0] of Horizontal Blanking End Register + (CR03) supplies the 5 least significant bits. See CR03[4:0] for further details. + This 6-bit value should be set to the least significant 6 bits of the result of adding the length of the blanking + period in terms of character clocks to the value specified in the Horizontal Blanking Start Register (CR02). + + 6:5 + Horizontal Sync Delay. This field defines the degree to which the start and end of the horizontal sync pulse + are delayed to compensate for internal pipeline delays. This capability is supplied to implement VGA + compatibility. These field describes the delay in terms of a number character clocks. + Bit [6:5] Amount of Delay + 00 + no delay + 01 + delayed by 1 character clock + 10 + delayed by 2 character clocks + 11 delayed by 3 character clocks + 4:0 + Horizontal Sync End. This field provides the 5 least significant bits of a 5-bit value that specifies the end of + the horizontal sync pulse relative to its beginning. A value equal to the 5 least significant bits of the horizontal + character counter value at which time the horizontal retrace signal becomes inactive (logical 0). Thus, this 5- + bit value specifies the width of the horizontal sync pulse. To obtain a retrace signal of W, the following + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 37 + Bit Description + algorithm is used: Value of Horizontal Sync start Register (CR04) + width of horizontal retrace signal in + character clock units = 5 bit result to be programmed in this field + + + +1.6.8 CR06 - Vertical Total Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=06h) +Default:00h +Attributes:Read/Write (Group 0 Protection) + Bit Description + 7:0 + Vertical Total Bits [7:0]. This field provides the 8 least significant bits of either a 10-bit or 12-bit value that + specifies the total number of scan lines. This includes the scan lines both inside and outside of the active + display area. + In standard VGA modes, the vertical total is specified with a 10-bit value. The 8 least significant bits of this + value are supplied by these 8 bits of this register, and the 2 most significant bits are supplied by bits 5 and + 0 of the Overflow Register (CR07). + + + +1.6.9 CR07 - Overflow Register (Vertical) +I/O (and Memory Offset) Address:3B5h/3D5h (index=07h) +Default:UU0U UUU0b (U=Undefined) +Attributes:Read/Write (Group 0 Protection on bits [7:5, 3:0]) + 7 6 5 4 3 2 1 0 + Vert Total Line Vert Blank Vert Sync Vert Display Enable +Vert Sync Vert Disp Vert + <9> Cmp<8> Start<8> Start<8> <8> +Start Enable Total +<9> <9> <8> + + + + Bit Description + 7 + Vertical Sync Start Bit 9. The vertical sync start is a 10-bit that specifies the beginning of the vertical sync + pulse relative to the beginning of the active display area. The 8 least significant bits of this value are + supplied by bits [7:0] of the Vertical Sync Start Register (CR10), and the most and second-most significant + bits are supplied by this bit and bit 2, respectively, of this register. This 10-bit value should be programmed + to be equal to the number of scan lines from the beginning of the active display area to the start of the + vertical sync pulse. Since the active display area always starts on the 0th scan line, this number should be + equal to the number of the scan line on which the vertical sync pulse begins. + + 6 + Vertical Display Enable End Bit 9. The vertical display enable end is a 10-bit that specifies the number of + the last scan line within the active display area. In standard VGA modes, the vertical display enable end is + specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of the + Vertical Display Enable End Register (CR12), and the most and second-most significant bits are supplied + by this bit and bit 1, respectively, of this register. This 10-bit value should be programmed to be equal to + the number of the last scan line within in the active display area. Since the active display area always starts + on the 0th scan line, this number should be equal to the total number of scan lines within the active display + area, minus 1. + 5 + Vertical Total Bit 9. The vertical total is a 10-bit value that specifies the total number of scan lines. This + includes the scan lines both inside and outside of the active display area. The 8 least significant bits of this + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 38 + Bit Description + value are supplied by bits [7:0] of the Vertical Total Register (CR06), and the most and second-most + significant bits are supplied by this bit and bit 0, respectively, of this register. + This 10-bit value should be programmed equal to the total number of scan lines, minus 2. + 4 + Line Compare Bit 8. This bit provides the second most significant bit of a 10-bit value that specifies the + scan line at which the memory address counter restarts at the value of 0. Bit 6 of the Maximum Scan Line + Register (CR09) supplies the most significant bit, and bits 7-0 of the Line Compare Register (CR18) supply + the 8 least significant bits. Normally, this 10-bit value is set to specify a scan line after the last scan line of + the active display area. When this 10-bit value is set to specify a scan line within the active display area, it + causes that scan line and all subsequent scan lines in the active display area to display video data starting + at the very first byte of the frame buffer. The result is what appears to be a screen split into a top and + bottom part, with the image in the top part being repeated in the bottom part. When used in cooperation + with the Start Address High Register (CR0C) and the Start Address Low Register (CR0D), it is possible to + create a split display, as described earlier, but with the top and bottom parts displaying different data. The + top part will display what data exists in the frame buffer starting at the address specified in the two + aforementioned start address registers, while the bottom part will display what data exists in the frame + buffer starting at the first byte of the frame buffer. + + 3 + Vertical Blanking Start Bit 8. The vertical blanking start is a 10-bit that specifies the beginning of the + vertical blanking period relative to the beginning of the active display area. The 8 least significant bits of + this value are supplied by bits [7:0] of the Vertical Blanking Start Register (CR15), and the most and + second-most significant bits are supplied by bit 5 of the Maximum Scan Line Register (CR09) and this bit of + this register, respectively. + This 10-bit value should be programmed to be equal to the number of scan lines from the beginning of the + active display area to the beginning of the blanking period. Since the active display area always starts on + the 0th scan line, this number should be equal to the number of the scan line on which the vertical blanking + period begins. + 2 + Vertical Sync Start Bit 8. The vertical sync start is a 10-bit value that specifies the beginning of the + vertical sync pulse relative to the beginning of the active display area. The 8 least significant bits of this + value are supplied by bits [7:0] of the Vertical Sync Start Register (CR10), and the most and second-most + significant bits are supplied by bit 7 and this bit, respectively, of this register. + This 10-bit value should be programmed to be equal to the number of scan lines from the beginning of the + active display area to the start of the vertical sync pulse. Since the active display area always starts on the + 0th scan line, this number should be equal to the number of the scan line on which the vertical sync pulse + begins. + 1 + Vertical Display Enable End Bit 8. The vertical display enable end is a 10-bit value that specifies the + number of the last scan line within the active display area. The 8 least significant bits of this value are + supplied by bits [7:0] of the Vertical Display Enable End Register (CR12), and the two most significant bits + are supplied by bit 6 and this bit, respectively, of this register. + This 10-bit or value should be programmed to be equal to the number of the last scan line within in the + active display area. Since the active display area always starts on the 0th scan line, this number should be + equal to the total number of scan lines within the active display area, minus 1. + + 0 + Vertical Total Bit 8. The vertical total is a 10-bit value that specifies the total number of scan lines. This + includes the scan lines both inside and outside of the active display area. The 8 least significant bits of this + value are supplied by bits [7:0] of the Vertical Total Register (CR06), and the most and second-most + significant bits are supplied by bit 5 and this bit, respectively, of this register. + This 10-bit value should be programmed to be equal to the total number of scan lines, minus 2. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 39 + 1.6.10 CR08 - Preset Row Scan Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=08h) +Default:0UUU UUUUb (U=Undefined) +Attributes:Read/Write + 7 6 54 0 +Reserved (0)Byte PanningStarting Row Scan Count + + + Bit Description + 7 + Reserved. Read as 0s. + + 6:5 + Byte Panning. This field holds a 2-bit value that selects number of bytes (up to 3) by which the image is + shifted horizontally to the left on the screen. This function is available in both text and graphics modes. + In text modes with a 9-pixel wide character box, the image can be shifted up to 27 pixels to the left, in + increments of 9 pixels. In text modes with an 8-pixel wide character box, and in all standard VGA + graphics modes, the image can be shifted up to 24 pixels to the left, in increments of 8 pixels. When the + Nine dot disable bit of the VGA control register is set, the pixel shift will be equivalent to the 8-dot mode. + The image can be shifted still further, in increments of individual pixels, through the use of bits [3:0] of + the Horizontal Pixel Panning Register (AR13). + Number of Pixels Shifted + Bit [6:5] 9-Pixel Text + 8-Pixel Text & Graphics + + 00 0 0 + 01 9 8 + 10 18 16 + 11 27 24 + 4:0 + Starting Row Scan Count. This field specifies which horizontal line of pixels within the character boxes + of the characters used on the top-most row of text on the display will be used as the top-most scan line. + The horizontal lines of pixels of a character box are numbered from top to bottom, with the top-most line + of pixels being number 0. If a horizontal line of the these character boxes other than the top-most line is + specified, then the horizontal lines of the character box above the specified line of the character box will + not be displayed as part of the top-most row of text characters on the display. Normally, the value + specified by these 5 bits should be 0, so that all of the horizontal lines of pixels within these character + boxes will be displayed in the top-most row of text, ensuring that the characters in the top-most row of + text do not look as though they have been cut off at the top. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 40 + 1.6.11 CR09 - Maximum Scan Line Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=09h) +Default:00h +Attributes:Read/Write + 7 6 5 4 0 +Double ScanningLine Cmp <9>Vert Blank Start <9>Starting Row Scan Count + + + Bit Description + 7 + Double Scanning Enable. + 0 = Disable. When disabled, the clock to the row scan counter is equal to the horizontal scan rate. This is + the normal setting for many of the standard VGA modes. + 1 = Enable. When enabled, the clock to the row scan counter is divided by 2. This is normally used to allow + CGA-compatible modes that have only 200 scan lines of active video data to be displayed as 400 scan lines + (each scan line is displayed twice). + 6 + Line Compare Bit 9. This bit provides the most significant bit of a 10-bit value that specifies the scan line at + which the memory address counter restarts at the value of 0. Bit 4 of the Overflow Register (CR07) supplies + the second most significant bit, and bits 7-0 of the Line Compare Register (CR18) supply the 8 least + significant bits. + Normally, this 10-bit value is set to specify a scan line after the last scan line of the active display area. + When this 10-bit value is set to specify a scan line within the active display area, it causes that scan line and + all subsequent scan lines in the active display area to display video data starting at the very first byte of the + frame buffer. The result is what appears to be a screen split into a top and bottom part, with the image in the + top part being repeated in the bottom part. + When used in cooperation with the Start Address High Register (CR0C) and the Start Address Low Register + (CR0D), it is possible to create a split display, as described earlier, but with the top and bottom parts + displaying different data. The top part will display whatever data exists in the frame buffer starting at the + address specified in the two aforementioned start address registers, while the bottom part will display + whatever data exists in the frame buffer starting at the first byte of the frame buffer. + + 5 + Vertical Blanking Start Bit 9. The vertical blanking start is a 10-bit value that specifies the beginning of the + vertical blanking period relative to the beginning of the active display area. The 8 least significant bits of this + value are supplied by bits [7:0] of the Vertical Blanking Start Register (CR15), and the most and second- + most significant bits are supplied by this bit and bit 3 of the Overflow Register (CR07), respectively. + This 10-bit value should be programmed to be equal to the number of scan line from the beginning of the + active display area to the beginning of the blanking period. Since the active display area always starts on the + 0th scan line, this number should be equal to the number of the scan line on which the vertical blanking + period begins. + 4:0 + Starting Row Scan Count. This field provides all 5 bits of a 5-bit value that specifies the number of scan + lines in a horizontal row of text. This value should be programmed to be equal to the number of scan lines in + a horizontal row of text, minus 1. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 41 + 1.6.12 CR0A - Text Cursor Start Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=0Ah) +Default:00UU UUUUb (U=Undefined) +Attributes:Read/Write +7 6 5 4 0 +Reserved (00)Text Cursor OffText Cursor Start + + + Bit Description + 7:6 + Reserved. Read as 0. + + 5 + Text Cursor Off. This cursor is the text cursor that is part of the VGA standard. This text cursor exists only + in text modes, and thus, this register is entirely ignored in graphics modes. + 0 = Enables the text cursor. + 1 = Disables the text cursor. + + 4:0 + Text Cursor Start. This field specifies which horizontal line of pixels in a character box is to be used to + display the first horizontal line of the cursor in text mode. The horizontal lines of pixels in a character box + are numbered from top to bottom, with the top-most line being number 0. The value specified by these 5 + bits should be the number of the first horizontal line of pixels on which the cursor is to be shown. + + + +1.6.13 CR0B - Text Cursor End Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=0Bh) +Default:0UUU UUUUb (U=Undefined) +Attributes:Read/Write + 7 6 54 0 +Reserved (0)Text Cursor SkewText Cursor End + + + Bit Description + 7 + Reserved. Read as 0. + + 6:5 + Text Cursor Skew. This field specifies the degree to which the start and end of each horizontal line of + pixels making up the cursor is delayed to compensate for internal pipeline delays. These 2 bits describe the + delay in terms of a number character clocks. + Bit [6:5] Amount of Delay + 00 = No delay + 01 = Delayed by 1 character clock + 10 = Delayed by 2 character clocks + 11 = Delayed by 3 character clocks + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 42 + Bit Description + 4:0 + Text Cursor End. This field specifies which horizontal line of pixels in a character box is to be used to + display the last horizontal line of the cursor in text mode. The horizontal lines of pixels in a character box + are numbered from top to bottom, with the top-most line being number 0. The value specified by these 5 + bits should be the number of the last horizontal line of pixels on which the cursor is to be shown. + + + +1.6.14 CR0C - Start Address High Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=0Ch) +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Start Address Bits [15:8].This register provides either bits 15 through 8 of a 16-bit value that specifies the + memory address offset from the beginning of the frame buffer at which the data to be shown in the active + display area begins. (default is 0) + In standard VGA modes, the start address is specified with a 16-bit value. The eight bits of this register + provide the eight most significant bits of this value, while the eight bits of the Start Address Low Register + (CR0D) provide the eight least significant bits. + + + +1.6.15 CR0D - Start Address Low Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=0Dh) +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Start Address Bits [7:0] This register provides either bits 7 through 0 of a 16 bit value that specifies the + memory address offset from the beginning of the frame buffer at which the data to be shown in the active + display area begins. (default is 0) + In standard VGA modes the start address is specified with a 16-bit value. The eight bits of the Start Address + High Register (CR0C) provide the eight most significant bits of this value, while the eight bits of this register + provide the eight least significant bits. + + + +1.6.16 CR0E - Text Cursor Location High Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=0Eh) +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Text Cursor Location Bits [15:8]. This field provides the 8 most significant bits of a 16-bit value that + specifies the address offset from the beginning of the frame buffer at which the text cursor is located. Bit 7:0 + of the Text Cursor Location Low Register (CR0F) provide the 8 least significant bits. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 43 + 1.6.17 CR0F - Text Cursor Location Low Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=0Fh) +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Text Cursor Location Bits [7:0]. This field provides the 8 least significant bits of a 16-bit value that specifies + the address offset from the beginning of the frame buffer at which the text cursor is located. Bits 7:0 of the + Text Cursor Location High Register (CR0E) provide the 8 most significant bits. + + + +1.6.18 CR10 - Vertical Sync Start Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=10h) +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Vertical Sync Start Bits [7:0]. This register provides the 8 least significant bits of a 10-bit that specifies + the beginning of the vertical sync pulse relative to the beginning of the active display area of a screen. In + standard VGA modes, this value is described in 10 bits with bits [7,2] of the Overflow Register (CR07) + supplying the 2 most significant bits. + This 10-bit value should equal the vertical sync start in terms of the number of scan lines from the + beginning of the active display area to the beginning of the vertical sync pulse. Since the active display + area always starts on the 0th scan line, this number should be equal to the number of the scan line on + which the vertical sync pulse begins. + + + +1.6.19 CR11 - Vertical Sync End Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=11h) +Default:0U00 UUUUb (U=Undefined) +Attributes:Read/Write + 7 6 5 4 3 0 +Protect Regs 0:7ReservedVert Int EnableVert Int ClearVertical Sync End + + + Bit Description + 7 + Protect Registers [0:7]. Note that the ability to write to Bit 4 of the Overflow Register (CR07) is not + affected by this bit (i.e., bit 4 of the Overflow Register is always writeable). + 0 = Enable writes to registers CR[00:07]. (default) + 1 = Disable writes to registers CR[00:07]. + + 6 + Reserved. In the VGA standard, this bit was used to switch between 3 and 5 frame buffer refresh cycles + during the time required to draw each horizontal line. + 5 + Vertical Interrupt Enable. This bit is reserved for compatibility only. While this bit may be written or read, + it’s value will have no effect. Note that the VGA does not provide an interrupt signal which would be + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 44 + Bit Description + connected to an input of the system’s interrupt controller. Bit 7 of Input Status Register 0 (ST00) originally + indicated the status of the vertical retrace interrupt. + 0 = Enable the generation of an interrupt at the beginning of each vertical retrace period. + 1 = Disable the generation of an interrupt at the beginning of each vertical retrace period. + 4 + Vertical Interrupt Clear. This is reserved for compatibility only. Note that the VGA does not provide an + interrupt signal which would be connected to an input of the system’s interrupt controller. + 0 = Setting this bit to 0 clears a pending vertical retrace interrupt. This bit must be set back to 1 to enable + the generation of another vertical retrace interrupt. + + 3:0 + Vertical Sync End. This 4-bit field provides a 4-bit value that specifies the end of the vertical sync pulse + relative to its beginning. This 4-bit value should be set to the least significant 4 bits of the result of adding + the length of the vertical sync pulse in terms of the number of scan lines that occur within the length of the + vertical sync pulse to the value that specifies the beginning of the vertical sync pulse (see the description + of the Vertical Sync Start Register for more details). + + + +1.6.20 CR12 - Vertical Display Enable End Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=12h) +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Vertical Display Enable End Bits [7:0]. This register provides the 8 least significant bits of a 10-bit value + that specifies the number of the last scan line within the active display area. In standard VGA modes, this + value is described in 10 bits with bits [6,1] of the Overflow Register (CR07) supplying the two most + significant bits. This 10-bit value should be programmed to be equal to the number of the last scan line + within in the active display area. Since the active display area always starts on the 0th scan line, this + number should be equal to the total number of scan lines within the active display area,minus 1. + + + +1.6.21 CR13 - Offset Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=13h) +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Offset Bits [7:0]. This register provides either all 8 bits of an 8-bit value that specifies the number of words + or DWords of frame buffer memory occupied by each horizontal row of characters. Whether this value is + interpreted as the number of words or DWords is determined by the settings of the bits in the Clocking + Mode Register (SR01). + In standard VGA modes, the offset is described with an 8-bit value, all the bits of which are provided by this + register. This 8-bit value should be programmed to be equal to either the number of words or DWords + (depending on the setting of the bits in the Clocking Mode Register, SR01) of frame buffer memory that is + occupied by each horizontal row of characters. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 45 + 1.6.22 CR14 - Underline Location Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=14h) +Default:0UUU UUUUb (U=Undefined) +Attributes:Read/Write + 7 6 5 4 0 +Reserved (0) Count By 4Underline Location + Dword + Mode + + + + Bit Description + 7 + Reserved. Read as 0. + + 6 + DWord Mode. + 0 = Frame buffer addresses are interpreted by the frame buffer address decoder as being either byte + addresses or word addresses, depending on the setting of bit 6 of the CRT Mode Control Register (CR17). + 1 = Frame buffer addresses are interpreted by the frame buffer address decoder as being DWord addresses, + regardless of the setting of bit 6 of the CRT Mode Control Register (CR17). + Note that this bit is used in conjunction with bits 6 and 5 of the CRT Mode Control Register (CR17) to select + how frame buffer addresses from the CPU are interpreted by the frame buffer address decoder as shown + below: + CR14[6] CR17[6] Addressing Mode + 0 0 Word Mode + 0 1 Byte Mode + 1 0 DWord Mode + 1 1 DWord Mode + 5 + Count By 4. + 0 = The memory address counter is incremented either every character clock or every other character clock, + depending upon the setting of bit 3 of the CRT Mode Control Register. + 1 = The memory address counter is incremented either every 4 character clocks or every 2 character clocks, + depending upon the setting of bit 3 of the CRT Mode Control Register. . This is used in mode x13 to allow for + using all four planes. + Note that this bit is used in conjunction with bit 3 of the CRT Mode Control Register (CR17) to select the + number of character clocks are required to cause the memory address counter to be incremented as shown, + below: + CR14[5] CR17[3] Addressing Incrementing Interval + 0 0 every character clock + 0 1 every 2 character clocks + 1 0 every 4 character clocks + 1 1 every 2 character clocks + 4:0 + Underline Location. This field specifies which horizontal line of pixels in a character box is to be used to + display a character underline in text mode. The horizontal lines of pixels in a character box are numbered from + top to bottom, with the top-most line being number 0. The value specified by these 5 bits should be the + number of the horizontal line on which the character underline mark is to be shown. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 46 + 1.6.23 CR15 - Vertical Blanking Start Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=15h) +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Vertical Blanking Start Bits [7:0]. This register provides the 8 least significant bits of a 10-bit value that + specifies the beginning of the vertical blanking period relative to the beginning of the active display area of + the screen. In standard VGA modes, the vertical blanking start is specified with a 10-bit value. The most + and second-most significant bits of this value are supplied by bit 5 of the Maximum Scan Line Register + (CR09) and bit 3 of the Overflow Register (CR07), respectively. This 10-bit value should be programmed + to be equal the number of scan lines from the beginning of the active display area to the beginning of the + vertical blanking period. Since the active display area always starts on the 0th scan line, this number + should be equal to the number of the scan line on which vertical blanking begins. + + + +1.6.24 CR16 - Vertical Blanking End Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=16h) +Default:Undefined +Attributes:Read/Write +This register provides a 8-bit value that specifies the end of the vertical blanking period relative to its +beginning. + Bit Description + 7:0 + Vertical Blanking End Bits [7:0]. This 8-bit value should be set equal to the least significant 8 bits of the + result of adding the length of the vertical blanking period in terms of the number of scan lines that occur + within the length of the vertical blanking period to the value that specifies the beginning of the vertical + blanking period (see the description of the Vertical Blanking Start Register for details). + + + +1.6.25 CR17 - CRT Mode Control +I/O (and Memory Offset) Address:3B5h/3D5h (index=17h) +Default:0UU0 UUUUb (U=Undefined) +Attributes:Read/Write + 7 6 5 4 3 2 1 0 + CRT Ctrl Word or Byte Address Reserved Count By Horizontal Retrace Select Row Compat Mode + Reset Mode Wrap (0) 2 Select Scan Cntr Support + + + Bit Description + 7 + CRT Controller Reset. This bit has no effect except in native VGA modes (non-centered). + 0 = Forces horizontal and vertical sync signals to be inactive. No other registers or outputs are affected. + 1 = Permits normal operation. + 6 + Word Mode or Byte Mode. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 47 + Bit Description + 0 = The memory address counter’s output bits are shifted by 1 bit position before being passed on to the + frame buffer address decoder such that they are made into word-aligned addresses when bit 6 of the + Underline Location Register (CR17) is set to 0. + 1 = The memory address counter’s output bits remain unshifted before being passed on to the frame buffer + address decoder such that they remain byte-aligned addresses when bit 6 of the Underline Location Register + (CR17) is set to 0. + Note that this bit is used in conjunction with bits 6 and 5 of the CRT Mode Control Register (CR17) to control + how frame buffer addresses from the memory address counter are interpreted by the frame buffer address + decoder as shown below: + CR14[6] CR17[6] Address Mode + 0 0 + Word Mode - Addresses from the memory address counter are shifted once to + become word-aligned + 0 1 + Byte Mode - Addresses from the memory address counter are not shifted + 1 0 + DWord Mode - Addresses from the memory address counter are shifted twice to + become DWord-aligned + 1 1 + DWord Mode - Addresses from the memory address counter are shifted twice to + become DWord-aligned + 5 + Address Wrap. Note that this bit is only effective when word mode is made active by setting bit 6 in both the + Underline Location Register and this register to 0. + 0 = Wrap frame buffer address at 16 KB. This is used in CGA-compatible modes. + 1 = No wrapping of frame buffer addresses. + + 4 + Reserved. Read as 0. + + 3 + Count By 2. This bit is used in conjunction with bit 5 of the Underline Location Register (CR14) to select the + number of character clocks are required to cause the memory address counter to be incremented. + 0 = The memory address counter is incremented either every character clock or every 4 character clocks, + depending upon the setting of bit 5 of the Underline Location Register. + 1 = The memory address counter is incremented either every other clock. + CR14[5] CR17[3] Address Incrementing interval + 0 0 + every character clock + 0 1 + every 2 character clocks + 1 0 + every 4 character clocks + 1 1 + every 2 character clocks + 2 + Horizontal Retrace Select. This bit provides a way of effectively doubling the vertical resolution by allowing + the vertical timing counter to be clocked by the horizontal retrace clock divided by 2 (usually, it would be + undivided). + 0 = The vertical timing counter is clocked by the horizontal retrace clock. + 1 = The vertical timing counter is clocked by the horizontal retrace clock divided by 2. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 48 + Bit Description + 1 + Select Row Scan Counter. + 0 = A substitution takes place, where bit 14 of the 16-bit memory address generated of the memory address + counter (after the stage at which these 16 bits may have already been shifted to accommodate word or + DWord addressing) is replaced with bit 1 of the row scan counter at a stage just before this address is + presented to the frame buffer address decoder. + 1 = No substitution takes place. See following tables. + 0 + Compatibility Mode Support. + 0 = A substitution takes place, where bit 13 of the 16-bit memory address generated of the memory address + counter (after the stage at which these 16 bits may have already been shifted to accommodate word or + DWord addressing) is replaced with bit 0 of the row scan counter at a stage just before this address is + presented to the frame buffer address decoder. + 1 = No substitution takes place. See following tables. + +The following tables show the possible ways in which the address bits from the memory address counter +can be shifted and/or reorganized before being presented to the frame buffer address decoder. First, the +address bits generated by the memory address counter are reorganized, if need be, to accommodate +byte, word or DWord modes. The resulting reorganized outputs (MAOut15-MAOut0) from the memory +address counter may also be further manipulated with the substitution of bits from the row scan counter +(RSOut1 and RSOut0) before finally being presented to the input bits of the frame buffer address decoder +(FBIn15-FBIn0). + +Memory Address Counter Address Bits [15:0] + + Byte Mode Word Mode Word Mode DWord Mode + CR14 bit 6=0 CR14 bit 6=0 CR14 bit 6=0 CR14 bit 6=1 + CR17 bit 6=1 CR17 bit 6=0 CR17 bit 6=0 CR17 bit 6=X + CR17 bit 5=X CR17 bit 5=1 CR17 bit 5=0 CR17 bit 5=X + +MAOut0 0 15 13 12 +MAOut1 1 0 0 13 +MAOut2 2 1 1 0 +MAOut3 3 2 2 1 +MAOut4 4 3 3 2 +MAOut5 5 4 4 3 +MAOut6 6 5 5 4 +MAOut7 7 6 6 5 +MAOut8 8 7 7 6 +MAOut9 9 8 8 7 +MAOut10 10 9 9 8 +MAOut11 11 10 10 9 +MAOut12 12 11 11 10 +MAOut13 13 12 12 11 +MAOut14 14 13 13 12 +MAOut15 15 14 14 13 + +X = Don’t Care + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 49 + Frame Buffer Address Decoder + CR17 bit 1=1 CR17 bit 1=1 CR17 bit 1=0 CR17 bit 1=0 + CR17 bit 0=1 CR17 bit 0=0 CR17 bit 0=1 CR17 bit 0=0 +FBIn0 MAOut0 MAOut0 MAOut0 MAOut0 +FBIn1 MAOut1 MAOut1 MAOut1 MAOut1 +FBIn2 MAOut2 MAOut2 MAOut2 MAOut2 +FBIn3 MAOut3 MAOut3 MAOut3 MAOut3 +FBIn4 MAOut4 MAOut4 MAOut4 MAOut4 +FBIn5 MAOut5 MAOut5 MAOut5 MAOut5 +FBIn6 MAOut6 MAOut6 MAOut6 MAOut6 +FBIn7 MAOut7 MAOut7 MAOut7 MAOut7 +FBIn8 MAOut8 MAOut8 MAOut8 MAOut8 +FBIn9 MAOut9 MAOut9 MAOut9 MAOut9 +FBIn10 MAOut10 MAOut10 MAOut10 MAOut10 +FBIn11 MAOut11 MAOut11 MAOut11 MAOut11 +FBIn12 MAOut12 MAOut12 MAOut12 MAOut12 +FBIn13 MAOut13 MAOut13 RSOut0 RSOut0 +FBIn14 MAOut14 RSOut1 MAOut14 RSOut1 +FBIn15 MAOut15 MAOut15 MAOut15 MAOut15 + + +1.6.26 CR18 - Line Compare Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=18h) +Default:Undefined +Attributes:Read/Write + Bit Description + 7:0 + Line Compare Bits [7:0]. This register provides the 8 least significant bits of a 10-bit value that specifies + the scan line at which the memory address counter restarts at the value of 0. Bit 6 of the Maximum Scan + Line Register (CR09) supplies the most significant bit, and bit 4 of the Overflow Register (CR07) supplies + the second most significant bit. + Normally, this 10-bit value is set to specify a scan line after the last scan line of the active display area. + When this 10-bit value is set to specify a scan line within the active display area, it causes that scan line and + all subsequent scan lines in the active display area to display video data starting at the very first byte of the + frame buffer. The result is what appears to be a screen split into a top and bottom part, with the image in the + top part being repeated in the bottom part. (This register is only used in split screening modes, and this is + not a problem because split screening is not actually used for extended modes. As a result, there is no + benefit to extending the existing overflow bits for higher resolutions. ) + When used in cooperation with the Start Address High Register (CR0C) and the Start Address Low Register + (CR0D), it is possible to create a split display, as described earlier, but with the top and bottom parts + displaying different data. The top part will display whatever data exists in the frame buffer starting at the + address specified in the two aforementioned start address registers, while the bottom part will display + whatever data exists in the frame buffer starting at the first byte of the frame buffer. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 50 + 1.6.27 CR22 - Memory Read Latch Data Register +I/O (and Memory Offset) Address:3B5h/3D5h (index=22h) +Default:00h +Attributes:Read Only + Bit Description + 7:0 + Memory Read Latch Data. This field provides the value currently stored in 1 of the four memory read + latches. Bits 1 and 0 of the Read Map Select Register (GR04) select which of the four memory read + latches may be read via this register. + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 51 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V3 Pt 1 – 05 12 5/31/2012 52 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol3_part2.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol3_part2.txt new file mode 100644 index 0000000..f62a504 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol3_part2.txt @@ -0,0 +1,2012 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 3 Part 2: PCI Registers +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 1 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 + Contents +1. PCI Device 2 Configuration Space ...................................................................................................... 4 + 1.1 VID2 - Vendor Identification ................................................................................................................. 5 + 1.2 DID2 - Device Identification ................................................................................................................. 5 + 1.3 PCICMD2 - PCI Command .................................................................................................................. 6 + 1.4 PCISTS2 - PCI Status .......................................................................................................................... 7 + 1.5 RID2 - Revision Identification ............................................................................................................... 9 + 1.6 CC - Class Code .................................................................................................................................. 9 + 1.7 CLS - Cache Line Size ....................................................................................................................... 10 + 1.8 MLT2 - Master Latency Timer ............................................................................................................ 10 + 1.9 HDR2 - Header Type ......................................................................................................................... 11 + 1.10 GTTMMADR - Graphics Translation Table, Memory Mapped Range Address ............................... 11 + 1.11 GMADR - Graphics Memory Range Address ................................................................................... 12 + 1.12 IOBAR - I/O Base Address ............................................................................................................... 13 + 1.13 SVID2 - Subsystem Vendor Identification ........................................................................................ 14 + 1.14 SID2 - Subsystem Identification ....................................................................................................... 14 + 1.15 ROMADR - Video BIOS ROM Base Address ................................................................................... 15 + 1.16 CAPPOINT - Capabilities Pointer ..................................................................................................... 15 + 1.17 INTRLINE - Interrupt Line ................................................................................................................. 16 + 1.18 INTRPIN - Interrupt Pin..................................................................................................................... 16 + 1.19 MINGNT - Minimum Grant Value ..................................................................................................... 17 + 1.20 MAXLAT - Maximum Latency ........................................................................................................... 17 + 1.21 CAPID0 - Capability Identifier ........................................................................................................... 18 + 1.22 CAPCTRL0 - Capabilities Control .................................................................................................... 18 + 1.23 CAPID0_A - Capabilities A ............................................................................................................... 19 + 1.24 CAPID0_B - Capabilities B ............................................................................................................... 22 + 1.25 MGGC0 - Mirror of GMCH Graphics Control Register ..................................................................... 25 + 1.26 DEVEN0 - Device Enable ................................................................................................................. 27 + 1.27 BDSM - Base Data of Stolen Memory .............................................................................................. 29 + 1.28 HSRW - Hardware Scratch Read Write............................................................................................ 30 + 1.29 MSAC - Multi Size Aperture Control ................................................................................................. 30 + 1.30 VTD_STATUS - VTd Status ............................................................................................................. 31 + 1.31 MSI_CAPID - Message Signaled Interrupts Capability ID................................................................ 32 + 1.32 MC - Message Control ...................................................................................................................... 32 + 1.33 MA - Message Address .................................................................................................................... 34 + 1.34 MD - Message Data .......................................................................................................................... 34 + 1.35 AFCIDNP - Advanced Features Capabilities Identifier and Next Pointer ......................................... 35 + 1.36 AFLC - Advanced Features Length and Capabilities ....................................................................... 35 + 1.37 AFCTL - Advanced Features Control ............................................................................................... 36 + 1.38 AFSTS - Advanced Features Status ................................................................................................ 37 + 1.39 PMCAPID - Power Management Capabilities ID ............................................................................. 37 + 1.40 PMCAP - Power Management Capabilities ...................................................................................... 38 + 1.41 PMCS - Power Management Control/Status .................................................................................... 39 + 1.42 SWSMI - Software SMI ..................................................................................................................... 40 + 1.43 GSE - Graphics System Event ......................................................................................................... 40 + 1.44 SWSCI - Software SCI...................................................................................................................... 41 + 1.45 ASLS - ASL Storage ......................................................................................................................... 42 + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 3 + 1. PCI Device 2 Configuration Space +The following table is ordered by register start offset. + Register Register Register + Register Name Symbol Start End Default Value Access +Vendor Identification VID2 00h 01h 8086h RO; +Device Identification DID2 02h 03h 0152h RO-V; RO- + FW; +PCI Command PCICMD2 04h 05h 0000h RW; RO; +PCI Status PCISTS2 06h 07h 0090h RO; RO-V; +Revision Identification RID2 08h 08h 00h RO-FW; +Class Code CC 09h 0Bh 030000h RO-V; RO; +Cache Line Size CLS 0Ch 0Ch 00h RO; +Master Latency Timer MLT2 0Dh 0Dh 00h RO; +Header Type HDR2 0Eh 0Eh 00h RO; +Graphics Translation Table, Memory GTTMMADR 10h 17h 0000000000000004h RO; RW; +Mapped Range Address +Graphics Memory Range Address GMADR 18h 1Fh 000000000000000Ch RW; RO; + RW-L; +I/O Base Address IOBAR 20h 23h 00000001h RW; RO; +Subsystem Vendor Identification SVID2 2Ch 2Dh 0000h RW-O; +Subsystem Identification SID2 2Eh 2Fh 0000h RW-O; +Video BIOS ROM Base Address ROMADR 30h 33h 00000000h RO; +Capabilities Pointer CAPPOINT 34h 34h 90h RO-V; +Interrupt Line INTRLINE 3Ch 3Ch 00h RW; +Interrupt Pin INTRPIN 3Dh 3Dh 01h RO; +Minimum Grant MINGNT 3Eh 3Eh 00h RO; +Maximum Latency MAXLAT 3Fh 3Fh 00h RO; +Capability Identifier CAPID0 40h 41h 0009h RO; +Capabilities Control CAPCTRL0 42h 43h 010Ch RO; +Capabilities A CAPID0_A 44h 47h 00000000h RO-FW; RO- + KFW; +Capabilities B CAPID0_B 48h 4Bh 00000000h RO-FW; +Mirror of GMCH Graphics Control MGGC0 50h 51h 0028h RO-V; +Register +Device Enable DEVEN0 54h 57h 0000209Fh RO-V; +Base Data of Stolen Memory BDSM 5Ch 5Fh 00000000h RO-V; +Hardware Scratch Read Write HSRW 60h 61h 0000h RW; +Multi Size Aperture Control MSAC 62h 62h 02h RW; RW-K; +VTd Status VTD_STATUS 63h 63h 00h RO-VFW; +Capabilities List Control CAPL 7Fh 7Fh 00h RW; +Message Signaled Interrupts Capability MSI_CAPID 90h 91h D005h RO; +ID +Message Control MC 92h 93h 0000h RO; RW; +Message Address MA 94h 97h 00000000h RW; RO; +Message Data MD 98h 99h 0000h RW; +Advanced Features Capabilities AFCIDNP A4h A5h 0013h RO; +Identifier and Next Pointer +Advanced Features Length and AFLC A6h A7h 0306h RO; +Capabilities + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 4 + Register Register Register + Register Name Symbol Start End Default Value Access +Advanced Features Control AFCTL A8h A8h 00h RW1S; +Advanced Features Status AFSTS A9h A9h 00h RO; +Power Management Capabilities ID PMCAPID D0h D1h A401h RO; +Power Management Capabilities PMCAP D2h D3h 0022h RO; +Power Management Control/Status PMCS D4h D5h 0000h RO; RW; +Software SMI SWSMI E0h E1h 0000h RW; +Graphics System Event GSE E4h E7h 00000000h RW; +Software SCI SWSCI E8h E9h 0000h RW-O; RW; +ASL Storage ASLS FCh FFh 00000000h RW; + + + +1.1 VID2 - Vendor Identification +B/D/F/Type: 0/2/0/PCI +Address Offset: 0-1h +Default Value: 8086h +Access: RO; +Size: 16 bits + +This register combined with the Device Identification register uniquely identifies any PCI device. + Bit Access Default Value RST/PWR Description +15:0 RO 8086h Uncore + Vendor Identification Number (VID): + PCI standard identification for Intel. + + + +1.2 DID2 - Device Identification +B/D/F/Type: 0/2/0/PCI +Address Offset: 2-3h +Default Value: 0152h +Access: RO-V; RO-FW; +Size: 16 bits + +This register combined with the Vendor Identification register uniquely identifies any PCI device. +This register is a 16-bit value assigned to the IVB graphics device. + Bit Access Default Value RST/PWR Description +15:4 RO-FW 015h Uncore + Device Identification Number MSB (DID_MSB): + This is the upper part of a 16-bit value assigned to the Graphics device. + Changed the default value from 010h to 015h. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 5 + 1.3 PCICMD2 - PCI Command +B/D/F/Type: 0/2/0/PCI +Address Offset: 4-5h +Default Value: 0000h +Access: RW; RO; +Size: 16 bits +BIOS Optimal Default: 00h + +This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD +Register in the IGD disables the IGD PCI-compliant master accesses to main memory. + Default + Bit Access Value RST/PWR Description +15:11 RO 0h Reserved (RSVD). +10 RW 0b FLR, + Interrupt Disable (INTDIS): + Uncore + This bit disables the device from asserting INTx#. + 0: Enable the assertion of this device's INTx# signal. + 1: Disable the assertion of this device's INTx# signal, so that DO_INTx messages + are not sent to DMI. +9 RO 0b Uncore + Fast Back-to-Back (FB2B): + Not Implemented. Hardwired to 0. +8 RO 0b Uncore + SERR Enable (SERRE): + Not Implemented. Hardwired to 0. + +7 RO 0b Uncore + Address/Data Stepping Enable (ADSTEP): + Not Implemented. Hardwired to 0. +6 RO 0b Uncore + Parity Error Enable (PERRE): + Not Implemented. Hardwired to 0. Since the IGD belongs to the category of + devices that do not corrupt programs or data in system memory or hard drives, + the IGD ignores any parity error that it detects and continues with normal + operation. +5 RO 0b Uncore + Video Palette Snooping (VPS): + This bit is hardwired to 0 to disable snooping. +4 RO 0b Uncore + Memory Write and Invalidate Enable (MWIE): + Hardwired to 0. The IGD does not support memory write and invalidate + commands. + +3 RO 0b Uncore + Special Cycle Enable (SCE): + This bit is hardwired to 0. The IGD ignores Special cycles. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 6 + Default + Bit Access Value RST/PWR Description +2 RW 0b FLR, + Bus Master Enable (BME): + Uncore + 0: Disable IGD bus mastering. + 1: Enable the IGD to function as a PCI-compliant master. + +1 RW 0b FLR, + Memory Access Enable (MAE): + Uncore + This bit controls the IGD's response to memory space accesses. + 0: Disable. + 1: Enable. +0 RW 0b FLR, + I/O Access Enable (IOAE): + Uncore + This bit controls the IGD's response to I/O space accesses. + 0: Disable. + 1: Enable. + + + +1.4 PCISTS2 - PCI Status +B/D/F/Type: 0/2/0/PCI +Address Offset: 6-7h +Default Value: 0090h +Access: RO; RO-V; +Size: 16 bits +BIOS Optimal Default: 0h + +PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI +compliant target abort. +PCISTS also indicates the DEVSEL# timing that has been set by the IGD. + Default + Bit Access Value RST/PWR Description +15 RO 0b Uncore + Detected Parity Error (DPE): + The IGD does not detect parity errors. This bit is hardwired to 0. +14 RO 0b Uncore + Signaled System Error (SSE): + The IGD never asserts SERR#, thus this bit is hardwired to 0. + +13 RO 0b Uncore + Received Master Abort Status (RMAS): + The IGD never gets a Master Abort, thus this bit is hardwired to 0. +12 RO 0b Uncore + Received Target Abort Status (RTAS): + The IGD never gets a Target Abort, thus this bit is hardwired to 0. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 7 + Default + Bit Access Value RST/PWR Description +11 RO 0b Uncore + Signaled Target Abort Status (STAS): + Hardwired to 0. The IGD does not use target abort semantics. + +10:9 RO 00b Uncore + DEVSEL Timing (DEVT): + N/A. This field is hardwired to 00b. +8 RO 0b Uncore + Master Data Parity Error Detected (DPD): + Since Parity Error Response is hardwired to disabled (and the IGD does not do + any parity detection), this bit is hardwired to 0. +7 RO 1b Uncore + Fast Back-to-Back (FB2B): + Hardwired to 1. The IGD accepts fast back-to-back when the transactions are not + to the same agent. +6 RO 0b Uncore + User Defined Format (UDF): + Hardwired to 0. + +5 RO 0b Uncore + 66 MHz PCI Capable (C66): + N/A - Hardwired to 0. +4 RO 1b Uncore + Capability List (CLIST): + This bit is set to 1 to indicate that the register at 34h provides an offset into the + function's PCI Configuration Space containing a pointer to the list's first item. +3 RO-V 0b Uncore + Interrupt Status (INTSTS): + This bit reflects the state of the interrupt in the device. Only when the Interrupt + Disable bit in the command register is a 0 and this Interrupt Status bit is a 1, is the + device's INTx# signal asserted. +2:0 RO 0h Reserved (RSVD). + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 8 + 1.5 RID2 - Revision Identification +B/D/F/Type: 0/2/0/PCI +Address Offset: 8h +Default Value: 00h +Access: RO-FW; +Size: 8 bits + +This register contains the revision number for Device #2 Functions 0. +These bits are read only and writes to this register have no effect. +For the A-0 Stepping, the register value is 00h. +Bit Access Default Value RST/PWR Description +7:4 RO-FW 0h Uncore + Revision Identification Number MSB (RID_MSB): + Four MSB of RID. +3:0 RO-FW 0h Uncore + Revision Identification Number LSB (RID_LSB): + Four LSB of RID. + + + +1.6 CC - Class Code +B/D/F/Type: 0/2/0/PCI +Address Offset: 9-Bh +Default Value: 030000h +Access: RO-V; RO; +Size: 24 bits + +This register contains the device programming interface information related to the Sub-Class Code and +Base Class Code definition for the IGD. This register also contains the Base Class Code and the function +sub-class in relation to the Base Class Code. + Default + Bit Access Value RST/PWR Description +23:16 RO-V 03h Uncore + Base Class Code (BCC): + This is an 8-bit value that indicates the base class code. + When MGGC0[VAMEN] is 0 this code is 03h, indicating a Display Controller. + When MGGC0[VAMEN] is 1 this code is value 04h, indicating a Multimedia + Device. + +15:8 RO-V 00h Uncore + Sub-Class Code (SUBCC): + When MGGC0[VAMEN] is 0 this value is determined based on Device 0 GGC + register, GMS and IVD fields. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 9 + Default + Bit Access Value RST/PWR Description + 00h: VGA compatible. + 80h: Non VGA (GMS = "00h" or IVD = "1b"). + When MGGC0[VAMEN] is 1, this value is 80h, indicating other multimedia + device. + +7:0 RO 00h Uncore + Programming Interface (PI): + When MGGC0[VAMEN] is 0 this value is 00h, indicating a Display Controller. + When MGGC0[VAMEN] is 1 this value is 00h, indicating a NOP. + + + +1.7 CLS - Cache Line Size +B/D/F/Type: 0/2/0/PCI +Address Offset: Ch +Default Value: 00h +Access: RO; +Size: 8 bits + +The IGD does not support this register as a PCI slave. + Default +Bit Access Value RST/PWR Description +7:0 RO 00h Uncore + Cache Line Size (CLS): + This field is hardwired to 0s. The IGD as a PCI-compliant master does not use the + Memory Write and Invalidate command and, in general, does not perform + operations based on cache line size. + + + +1.8 MLT2 - Master Latency Timer +B/D/F/Type: 0/2/0/PCI +Address Offset: Dh +Default Value: 00h +Access: RO; +Size: 8 bits + +The IGD does not support programming the master latency timer because it does not perform bursts. +Bit Access Default Value RST/PWR Description +7:0 RO 00h Uncore + Master Latency Timer Count Value (MLTCV): + Hardwired to 0s. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 10 + 1.9 HDR2 - Header Type +B/D/F/Type: 0/2/0/PCI +Address Offset: Eh +Default Value: 00h +Access: RO; +Size: 8 bits + +This register contains the Header Type of the IGD. + Default +Bit Access Value RST/PWR Description +7 RO 0b Uncore + Multi Function Status (MFUNC): + Indicates if the device is a Multi-Function Device. This field is hardwired to 0, as + graphics is a single function. +6:0 RO 00h Uncore + Header Code (H): + This 7-bit value indicates the Header Code for the IGD. This code has the value + 00h, indicating a type 0 configuration space format. + + + +1.10 GTTMMADR - Graphics Translation Table, Memory + Mapped Range Address +B/D/F/Type: 0/2/0/PCI +Address Offset: 10-17h +Default Value: 0000000000000004h +Access: RO; RW; +Size: 64 bits + +This register requests allocation for the combined Graphics Translation Table Modification Range and +Memory Mapped Range. The range requires 4 MB combined for MMIO and Global GTT aperture, with 2 +MB of that used by MMIO and 2 MB used by GTT. GTTADR begins at (GTTMMADR + 2 MB) while the +MMIO base address will be the same as GTTMMADR. +For the Global GTT, this range is defined as a memory BAR in graphics device config space. It is an alias +into which software is required to write Page Table Entry values (PTEs). Software may read PTE values +from the global Graphics Translation Table (GTT). PTEs cannot be written directly into the global GTT +memory area. +The device snoops writes to this region in order to invalidate any cached translations within the various +TLB's implemented on-chip. +The allocation is for 4 MB and the base address is defined by bits [38:22]. + Default + Bit Access Value RST/PWR Description +63:39 RW 0000000h FLR, + Reserved for Memory Base Address (RSVDRW): + Uncore + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 11 + Default + Bit Access Value RST/PWR Description + Must be set to 0 since addressing above 512 GB is not supported. + +38:22 RW 00000h FLR, + Memory Base Address (MBA): + Uncore + Set by the OS, these bits correspond to address signals [38:22]. 4 MB + combined for MMIO and Global GTT table aperture (2 MB for MMIO and 2 MB + for GTT). +21:4 RO 00000h Uncore + Address Mask (ADM): + Hardwired to 0s to indicate at least 4 MB address range. +3 RO 0b Uncore + Prefetchable Memory (PREFMEM): + Hardwired to 0 to prevent prefetching. +2:1 RO 10b Uncore + Memory Type (MEMTYP): + 00: Indicate 32-bit base address. + 01: Reserved. + 10: Indicate 64-bit base address. + 11: Reserved. + +0 RO 0b Uncore + Memory/IO Space (MIOS): + Hardwired to 0 to indicate memory space. + + + +1.11 GMADR - Graphics Memory Range Address +B/D/F/Type: 0/2/0/PCI +Address Offset: 18-1Fh +Default Value: 000000000000000Ch +Access: RW; RO; RW-L; +Size: 64 bits + +GMADR is the PCI aperture used by software to access tiled GFX surfaces in a linear fashion. + Default + Bit Access Value RST/PWR Description +63:39 RW 0000000h FLR, + Reserved for Memory Base Address (RSVDRW): + Uncore + Must be set to 0 since addressing above 512GB is not supported. +38:29 RW 0000000000b FLR, + Memory Base Address (MBA): + Uncore + Memory Base Address (MBA): Set by the OS, these bits correspond to + address signals [38:29]. +28 RW-L 0b FLR, + 512MB Address Mask (ADMSK512): + Uncore + This bit is either part of the Memory Base Address (R/W) or part of the + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 12 + Default + Bit Access Value RST/PWR Description + Address Mask (RO), depending on the value of MSAC[2:1]. See MSAC + (Dev2, Func 0, offset 62h) for details. + +27 RW-L 0b FLR, + 256 MB Address Mask (ADMSK256): + Uncore + This bit is either part of the Memory Base Address (R/W) or part of the + Address Mask (RO), depending on the value of MSAC[2:1]. See MSAC (Dev + 2, Func 0, offset 62h) for details. +26:4 RO 000000h Uncore + Address Mask (ADM): + Hardwired to 0s to indicate at least 128MB address range. +3 RO 1b Uncore + Prefetchable Memory (PREFMEM): + Hardwired to 1 to enable prefetching. +2:1 RO 10b Uncore + Memory Type (MEMTYP): + 00b: indicates 32-bit address. + 10b: Indicates 64-bit address. + +0 RO 0b Uncore + Memory/IO Space (MIOS): + Hardwired to 0 to indicate memory space. + + + +1.12 IOBAR - I/O Base Address +B/D/F/Type: 0/2/0/PCI +Address Offset: 20-23h +Default Value: 00000001h +Access: RW; RO; +Size: 32 bits +BIOS Optimal Default: 00000h + +This register is the Base offset of the I/O registers within Device #2. Bits 15:6 are programmable, allowing +the I/O Base to be located anywhere in 16-bit I/O Address Space. Bits 2:1 are fixed and return 0s; bit 0 is +hardwired to a 1 indicating that 8 bytes of I/O space are decoded. Access to the 8Bs of IO space is +allowed in PM state D0 when IO Enable (PCICMD bit 0) is set. Access is disallowed in PM states D1-D3 +or if IO Enable is clear or if Device #2 is turned off or if Internal graphics is disabled through the fuse or +fuse override mechanisms. +Note that access to this I/O BAR is independent of VGA functionality within Device #2. +If access to this I/O BAR is allowed then all 8, 16, or 32 bit I/O cycles from IA cores that fall within the 8B +are claimed. + Bit Access Default Value RST/PWR Description +31:16 RO 0h Reserved (RSVD). +15:6 RW 000h FLR, Uncore + I/O Base Address (IOBASE): + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 13 + Bit Access Default Value RST/PWR Description + Set by the OS, these bits correspond to address signals [15:6]. +5:3 RO 0h Reserved (RSVD). +2:1 RO 00b Uncore + Memory Type (MEMTYPE): + Hardwired to 0s to indicate 32-bit address. + +0 RO 1b Uncore + Memory / I/O Space (MIOS): + Hardwired to 1 to indicate I/O space. + + + +1.13 SVID2 - Subsystem Vendor Identification +B/D/F/Type: 0/2/0/PCI +Address Offset: 2C-2Dh +Default Value: 0000h +Access: RW-O; +Size: 16 bits + +This register uniquely identifies the subsystem where the PCI device resides. + Default + Bit Access Value RST/PWR Description +15:0 RW-O 0000h Uncore + Subsystem Vendor ID (SUBVID): + This value identifies the vendor of the subsystem. This register should be + programmed by BIOS during boot-up. Once written, this register becomes Read- + Only. This register can only be cleared by a Reset. + + + +1.14 SID2 - Subsystem Identification +B/D/F/Type: 0/2/0/PCI +Address Offset: 2E-2Fh +Default Value: 0000h +Access: RW-O; +Size: 16 bits + +This register uniquely identifies the subsystem where the PCI device resides. + Default + Bit Access Value RST/PWR Description +15:0 RW-O 0000h Uncore + Subsystem Identification (SUBID): + This value identifies a particular subsystem. This field should be programmed by + BIOS during boot-up. Once written, this register becomes Read-Only. This register + can only be cleared by a Reset. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 14 + 1.15 ROMADR - Video BIOS ROM Base Address +B/D/F/Type: 0/2/0/PCI +Address Offset: 30-33h +Default Value: 00000000h +Access: RO; +Size: 32 bits +BIOS Optimal Default: 000h + +The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s. + Bit Access Default Value RST/PWR Description +31:18 RO 0000h Uncore + ROM Base Address (RBA): + Hardwired to 0s. +17:11 RO 00h Uncore + Address Mask (ADMSK): + Hardwired to 0s to indicate 256 KB address range. +10:1 RO 0h Reserved (RSVD). +0 RO 0b Uncore + ROM BIOS Enable (RBE): + 0: ROM not accessible. + + + +1.16 CAPPOINT - Capabilities Pointer +B/D/F/Type: 0/2/0/PCI +Address Offset: 34h +Default Value: 90h +Access: RO-V; +Size: 8 bits + +This register points to a linked list of capabilities implemented by this device. + Default +Bit Access Value RST/PWR Description +7:0 RO-V 90h Uncore + Capabilities Pointer Value (CPV): + This field is an offset into the function's PCI Configuration Space for the first item in + the New Capabilities Linked List, the MSI Capabilities ID registers at address 90h or + the Power Management capability at D0h. + This value is determined by the configuration in CAPL[0]. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 15 + 1.17 INTRLINE - Interrupt Line +B/D/F/Type: 0/2/0/PCI +Address Offset: 3Ch +Default Value: 00h +Access: RW; +Size: 8 bits + +This 8-bit register communicates interrupt line routing information. It is read/write and must be +implemented by the device. POST software writes the routing information into this register as it initializes +and configures the system. +The value in this register tells which input of the system interrupt controller(s) the device's interrupt pin is +connected to. The device itself does not use this value, rather it is used by device drivers and operating +systems to determine interrupt priority and vector information. + Default +Bit Access Value RST/PWR Description +7:0 RW 00h Uncore + Interrupt Connection (INTCON): + Communicates interrupt line routing information. POST software writes the routing + information into this register as it initializes and configures the system. The register + value indicates to which input of the system interrupt controller the device's interrupt + pin is connected. + + + +1.18 INTRPIN - Interrupt Pin +B/D/F/Type: 0/2/0/PCI +Address Offset: 3Dh +Default Value: 01h +Access: RO; +Size: 8 bits + +This register tells which interrupt pin the device uses. The Integrated Graphics Device uses INTA#. +Bit Access Default Value RST/PWR Description +7:0 RO 01h Uncore + Interrupt Pin (INTPIN): + As a single function device, the IGD specifies INTA# as its interrupt pin. + 01h: INTA#. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 16 + 1.19 MINGNT - Minimum Grant Value +B/D/F/Type: 0/2/0/PCI +Address Offset: 3Eh +Default Value: 00h +Access: RO; +Size: 8 bits + +The Integrated Graphics Device has no requirement for the settings of Latency Timers. +Bit Access Default Value RST/PWR Description +7:0 RO 00h Uncore + Minimum Grant Value (MGV): + The IGD does not burst as a PCI-compliant master. + + + +1.20 MAXLAT - Maximum Latency +B/D/F/Type: 0/2/0/PCI +Address Offset: 3Fh +Default Value: 00h +Access: RO; +Size: 8 bits + +The Integrated Graphics Device has no requirement for the settings of Latency Timers. + Default +Bit Access Value RST/PWR Description +7:0 RO 00h Uncore + Maximum Latency Value (MLV): + The IGD has no specific requirements for how often it needs to access the PCI + bus. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 17 + 1.21 CAPID0 - Capability Identifier +B/D/F/Type: 0/2/0/PCI +Address Offset: 40-41h +Default Value: 0009h +Access: RO; +Size: 16 bits + +Control of bits in this register is only required for customer-visible SKU differentiation. + Default + Bit Access Value RST/PWR Description +15:8 RO 00h Uncore + Next Capability Pointer (NEXT_CAP): + This field is hardwired to 00h indicating the end of the capabilities linked list. + +7:0 RO 09h Uncore + Capability Identifier (CAP_ID): + This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG + for vendor-dependent capability pointers. + + + +1.22 CAPCTRL0 - Capabilities Control +B/D/F/Type: 0/2/0/PCI +Address Offset: 42-43h +Default Value: 010Ch +Access: RO; +Size: 16 bits +BIOS Optimal Default: 0h + +Control of bits in this register is only required for customer visible SKU differentiation. + Default + Bit Access Value RST/PWR Description +15:12 RO 0h Reserved (RSVD). +11:8 RO 1h Uncore + CAPID Version (CAPID_VER): + This field has the value 0001b to identify the first revision of the CAPID + register definition. +7:0 RO 0Ch Uncore + CAPID Length (CAPIDLEN): + This field has the value 0Ch to indicate the structure length (12 bytes). + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 18 + 1.23 CAPID0_A - Capabilities A +B/D/F/Type: 0/2/0/PCI +Address Offset: 44-47h +Default Value: 00000000h +Access: RO-FW; RO-KFW; +Size: 32 bits +BIOS Optimal Default: 000000h + +Control of bits in this register is only required for customer-visible SKU differentiation. + Default + Bit Access Value RST/PWR Description + 31 RO- 0b Uncore + PEG60 Disable (PEG60D): + KFW + 0: Device 6 Function 0 and associated memory spaces are accessible. + 1: Device 6 Function 0 and associated memory and I/O spaces are disabled by + hardwiring the D6F0EN field, bit 13 of the Device Enable register, (DEVEN Dev 0 + Offset 54h) to 0. + 30 RO- 0b Uncore + PEG12 Disable (PEG12D): + KFW + 0: Device 1 Function 2 and associated memory spaces are accessible. + 1: Device 1 Function 2 and associated memory and I/O spaces are disabled by + hardwiring the D1F2EN field, bit 1 of the Device Enable register, (DEVEN Dev 0 + Offset 54h) to 0. + 29 RO- 0b Uncore + PEG11 Disable (PEG11D): + KFW + 0: Device 1 Function 1 and associated memory spaces are accessible. + 1: Device 1 Function 1 and associated memory and I/O spaces are disabled by + hardwiring the D1F1EN field, bit 2 of the Device Enable register, (DEVEN Dev 0 + Offset 54h) to 0. + 28 RO- 0b Uncore + PEG10 Disable (PEG10D): + KFW + 0: Device 1 Function 0 and associated memory spaces are accessible. + 1: Device 1 Function 0 and associated memory and I/O spaces are disabled by + hardwiring the D1F0EN field, bit 3 of the Device Enable register, (DEVEN Dev 0 + Offset 54h) to 0. + 27 RO-FW 0b Uncore + PCI Express Link Width Upconfig Disable (PELWUD): + 0: Link width upconfig is supported. The CPU advertises upconfig capability using + the data rate symbol in its TS2 training ordered sets during + Configuration.Complete. The CPU responds to link width upconfigs initiated by the + downstream device. + 1: Link width upconfig is NOT supported. The CPU does not advertise upconfig + capability using the data rate field in TS2 training ordered sets during + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 19 + Default + Bit Access Value RST/PWR Description + Configuration.Complete. The CPU does not respond to link width upconfigs + initiated by the downstream device. + + 26 RO-FW 0b Uncore + DMI Width (DW): + 0: DMI x4. + 1: DMI x2. + 25 RO-FW 0b Uncore + ECC Disable (ECCDIS): + 0: ECC capable. + 1: Not ECC capable. + 24 RO-FW 0b Uncore + Force DRAM ECC Enabled (FDEE): + 0: DRAM ECC optional via software. + 1: DRAM ECC enabled. MCHBAR C0MISCCTL bit [0] and C1MISCCTL bit [0] + forced to 1 and Read-Only. + NOTE: FDEE and ECCDIS must not both be 1. + 23 RO- 0b Uncore + VTd Disable (VTDD): + KFW + 0: Enable VTd. + 1: Disable VTd. + + 22 RO-FW 0b Uncore + DMI Gen 2 Disable (DMIG2DIS): + 0: Capable of running DMI in Gen 2 mode. + 1: Not capable of running DMI in Gen 2 mode. + 21 RO-FW 0b Uncore + PEG Gen 2 Disable (PEGG2DIS): + 0: Can run any of the PEG controllers in Gen 2 mode. + 1: Cannot run any of the PEG controllers in Gen 2 mode. +20:19 RO-FW 00b Uncore + DDR Size (DDRSZ): + This field defines the maximum allowed memory size per channel. + 00b: Unlimited (16GB per channel) + 01b: Maximum 8GB per channel + 10b: Maximum 2GB per channel + 11b: Maximum 0.5GB per channel + 18 RO-FW 0b Uncore Spare (SPARE18). + 17 RO-FW 0b Uncore + Disable 1N Mode (D1NM): + 0: Part can support 1n mode timings on the DDR interface. + 1: Part cannot support 1n mode. The only supported timings are 2n or greater. + 15 RO- 0b Uncore + Camarillo Device Disable (CDD): + KFW + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 20 + Default + Bit Access Value RST/PWR Description + 0: Camarillo Device enabled. + 1: Camarillo Device disabled + + 14 RO-FW 0b Uncore + 2 DIMMS per Channel Disable (DDPCD): + Allows Dual Channel operation but only supports 1 DIMM per channel. + 0: 2 DIMMs per channel enabled. + 1: 2 DIMMs per channel disabled. This setting hardwires bits 2 and 3 of the rank + population field for each channel to zero (MCHBAR offset 260h, bits 22-23 for + channel 0 and MCHBAR offset 660h, bits 22-23 for channel 1). + 13 RO-FW 0b Uncore + X2APIC Enabled (X2APIC_EN): + Extended Interrupt Mode. + 0: Hardware does not support Extended APIC mode. + 1: Hardware supports Extended APIC mode. + 12 RO-FW 0b Uncore + Performance Dual Channel Disable (PDCD): + 0: Capable of Dual Channels. + 1: Not Capable of Dual Channels - only single channel capable. + 11 RO- 0b Uncore + Internal Graphics Disable (IGD): + KFW + 0: There is a graphics engine within this CPU. Internal Graphics Device (Device 2) + is enabled and all of its memory and I/O spaces are accessible. Configuration + cycles to Device 2 are completed within the CPU. All non-SMM memory and I/O + accesses to VGA are handled based on Memory and I/O enables of Device 2 and + I/O registers within Device 2 and VGA Enable of the PCI to PCI bridge control + register in Devices 1 and 6 (If PCI Express GFX attach is supported). A selected + amount of Graphics Memory space is pre-allocated from the main memory based + on Graphics Mode Select (GMS in the GGC Register). Graphics Memory is pre- + allocated above TSEG Memory. + 1: There is no graphics engine within this CPU. Internal Graphics Device (Device + 2) and all of its memory and I/O functions are disabled. Configuration cycle + targeted to Device 2 are passed on to DMI. In addition, all clocks to internal + graphics logic are turned off. All non-SMM memory and I/O accesses to VGA are + handled based on VGA Enable of the PCI to PCI bridge control register in Devices + 1 and 6. DEVEN [4:3] (Device 0, offset 54h) has no meaning. Device 2 Functions 0 + and 1 are disabled and hidden. + + 9:8 RO-FW 00b Uncore + Capability Device ID (CDID): + Identifier assigned to the core/primary PCI device. + 7:4 RO-FW 0h Uncore + Compatibility Rev ID (CRID): + This 4-bit value is the revision identification number for the Host Device 0. For the + A-0 Stepping, this value is 00h. + 3 RO-FW 0b Uncore + DDR Overclocking (DDR_OVERCLOCK): + Indicates support for DDR Overclocking. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 21 + Default + Bit Access Value RST/PWR Description + 2 RO-FW 0b Uncore + IA Overclocking Enabled by DSKU (OC_ENABLED_DSKU): + The default constant (non-fuse) value is zero. When the VDM sets this bit, we will + apply OC if OC_CTL_SSKU points to DSKU. + + 1 RO-FW 0b Uncore + On-die DDR write Vref generation allowed (DDR_WRTVREF): + Allow on-die DDR write Vref generation. PCODE will update this field with the + value ofFUSE_DDR_WRTVREF. + 0 RO-FW 0b Uncore + DDR3L (1.35V DDR) operation allowed (DDR3L_EN): + Allow DDR3L (1.35V DDR) operation. PCODE updates this field with the value + ofFUSE_DDR3L_EN. + + + +1.24 CAPID0_B - Capabilities B +B/D/F/Type: 0/2/0/PCI +Address Offset: 48-4Bh +Default Value: 00000000h +Access: RO-FW; +Size: 32 bits +BIOS Optimal Default: 00h + +Control of bits in this register is only required for customer-visible SKU differentiation. + Default + Bit Access Value RST/PWR Description +30 RO-FW 0b Uncore + IA Overclocking is controlled by SSKU rather than DSKU (OC_CTL_SSKU): + PCODE updates this field with the value of FUSE_OC_CTL_SSKU and then + applies SSKU overrides. + IA Overclocking is controlled by SSKU rather than DSKU. +29 RO-FW 0b Uncore + IA Overclocking Enabled by SSKU (OC_ENABLED_SSKU): + PCODE updates this field with the value of FUSE_OC_ENABLED_SSKU. + 0: Over-clocking is Disabled. + 1: Over-clocking is Enabled. + If over-clocking is enabled, FUSE_OC_BINS contains how many bits of over- + clocking are supported, with the following encoding: + 0h: Overclocking is disabled. + 1h: Max 1 bin of overclocking is allowed. + 2h: Max 2 bins of overclocking are allowed. + 3h: Max 3 bins of overclocking are allowed. + 4h: Max 4 bins of overclocking are allowed. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 22 + Default + Bit Access Value RST/PWR Description + 5h: Max 5 bins of overclocking are allowed. + 6h: Max 6 bins of overclocking are allowed. + 7h: Overclocking is not limited. + If overclocking is not enabled, FUSE_OC_BINS is meaningless, and should be 0. + +28 RO-FW 0b Uncore + SMT Capability (SMT): + This setting indicates whether the CPU is SMT capable. +27:25 RO-FW 000b Uncore + Cache Size Capability (CACHESZ): + This setting indicates the supporting cache sizes. +24 RO-FW 0b Uncore + Soft Bin Capability (SOFTBIN): + CPU is Soft Bin capable via FUSE_SSKU_SOFT_BIN_EN and if it is enabled by + the PCH. Both the Mask and Value are needed to enable this feature. If enabled, + PCODE uses the final resolved values in CAPID.D-G (except CAPID0_E[31:12]) + for frequency/branding instead of the baseline non-SSKU fused values. +23:21 RO-FW 000b Uncore + DDR3 Maximum Frequency Capability with 100 Memory (PLL_REF100_CFG): + DDR3 Maximum Frequency Capability with 100 Memory. PCODE updates this + field with the value of FUSE_PLL_REF100_CFG and then applies SSKU + overrides. + Maximum allowed memory frequency with 100 MHz ref clk. Also serves as + defeature. + Unlike 133 MHz ref fuses, this is a normal 3-bit field: + 0: 100 MHz ref disabled. + 1: Up to DDR-1400 (7 x 200). + 2: Up to DDR-1600 (8 x 200). + 3: Up to DDR-1800 (9 x 200). + 4: Up to DDR-2000 (10 x 200). + 5: Up to DDR-2200 (11 x 200). + 6: Up to DDR-2400 (12 x 200). + 7: No limit (but still limited by %MAX_DDR_FREQ200 to 2600). + +20 RO-FW 0b Uncore + PCIe Gen 3 Disable (PEGG3_DIS): + IVB: PCIe Gen 3 Disable. PCODE updates this field with the value of + FUSE_PEGG3_DIS and then applies SSKU overrides. + This is a defeature fuse; an un-programmed device should have PCIe Gen 3 + capabilities enabled. + 0: Capable of running any of the Gen 3-compliant PEG controllers in Gen 3 mode + (Devices 0/1/0, 0/1/1, 0/1/2). + 1: Not capable of running any of the PEG controllers in Gen 3 mode. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 23 + Default + Bit Access Value RST/PWR Description +19 RO-FW 0b Uncore + Package Type (PKGTYP): + This setting indicates the CPU Package Type. + +18 RO-FW 0b Uncore + Additive Graphics Enabled (ADDGFXEN): + 0: Additive Graphics Disabled. + 1: Additive Graphics Enabled. +17 RO-FW 0b Uncore + Additive Graphics Capable (ADDGFXCAP): + 0 - Capable of Additive Graphics + 1 - Not capable of Additive Graphics +16 RO-FW 0b Uncore + PCIe lane control x16/x8 (PEGX16D): + 0: Capable of x16 PEGPort + 1: Not Capable of x16 PEG port, instead PEG is limited to x8 and below. Causes + PEG port to enable and train logical lanes 7:0 only. Logical lanes 15:8 are powered + down (unless in use by the other PEG port or the embedded Display Port), and the + Max Link Width field of the Link Capability register reports x8 instead of x16. (In the + case of lane reversal, lanes 15:8 are active and lanes 7:0 are powered down.) +15:12 RO-FW 0h Uncore + Reserved for Future Capabilities (SPARE15_12): + Reserved for future capabilities. + +6:4 RO-FW 000b Uncore + DDR3 Maximum Frequency Capability (DMFC): + PCODE updates this field with the value of FUSE_DMFC, and then applies SSKU + overrides. + Maximum allowed memory frequency with 133 MHz ref clk. + This is a reversed 3-bit field: + 7: Up to DDR-1066 (4 x 266). + 6: Up to DDR-1333 (5 x 266). + 5: Up to DDR-1600 (6 x 266). + 4: Up to DDR-1866 (7 x 266). + 3: Up to DDR-2133 (8 x 266). + 2: Up to DDR-2400 (9 x 266). + 1: Up to DDR-2666 (10 x 266). + 0: Up to DDR-2933 (11 x 266). This is a reserved fuse value, not currently + supported. +3 RO-FW 0b Uncore + Reserved for Future Capabilities (SPARE3): + Reserved for future capabilities +2 RO-FW 0b Uncore + Reserved for Future Capabilities (SPARE2): + Reserved for future capabilities + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 24 + Default + Bit Access Value RST/PWR Description +1 RO-FW 0b Uncore + Dual PEG Force x1 when VGA Enabled (DPEGFX1): + This bit has no effect on Device 1 unless Device 1 is configured for at least two + ports via the PEG0CFGSEL strap. + This bit always applies to Device 6. + 0: All PEG port widths do not depend on their respective BCTRL[VGAEN]. + 1: Each PEG port width is limited to x1 operation when its respective + BCTRL[VGAEN] is set to 1b. + +0 RO-FW 0b Uncore + Single PEG Force x1 when VGA Enabled (SPEGFX1): + This bit has no effect on Device 1 unless Device 1 is configured for a single port + via the PEG0CFGSEL strap. + This bit always applies to Device 6. + 0: PEG10 and PEG60 widths do not depend on their respective BCTRL[VGAEN]. + 1: PEG10 and PEG60 widths are limited to x1 operation when their respective + BCTRL[VGAEN] is set to 1b. + + + +1.25 MGGC0 - Mirror of GMCH Graphics Control Register +B/D/F/Type: 0/2/0/PCI +Address Offset: 50-51h +Default Value: 0028h +Access: RO-V; +Size: 16 bits +BIOS Optimal Default: 00h + +All bits in this register are LT lockable. + Default + Bit Access Value RST/PWR Description +15 RO 0h Reserved (RSVD). +14 RO-V 0b Uncore + Versatile Acceleration Mode Enable (VAMEN): + Enables the use of the iGFXenbines for Versatile Acceleration. + 1: iGFX engines are in Versatile Acceleration Mode. Device 2 Class Code is + 048000h. + 0: iGFX engines are in iGFX Mode. Device 2 Class Code is 030000h. +13:10 RO 0h Reserved (RSVD). +9:8 RO-V 0h Uncore + GTT Graphics Memory Size (GGMS): + This field selects the amount of Main Memory that is pre-allocated to support the + Internal Graphics Translation Table. The BIOS ensures that memory is pre- + allocated only when Internal graphics is enabled. + GSM is assumed to be a contiguous physical DRAM space with DSM, and BIOS + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 25 + Default + Bit Access Value RST/PWR Description + needs to allocate a contiguous memory chunk. Hardware derives the base of + GSM from DSM using only the GSM size programmed in the register. + Hardware functionality in case of programming this value to Reserved is not + guaranteed. + Encoding Description + 1h 1MB of Preallocated Memory + 3h Reserved + 2h 2MB of Preallocated Memory + 0h No Preallocated Memory +7:3 RO-V 05h Uncore + Graphics Mode Select (GMS): + This field selects the amount of Main Memory that is pre-allocated to support the + Internal Graphics device in VGA (non-linear) and Native (linear) modes. The BIOS + ensures that memory is pre-allocated only when Internal graphics is enabled. + This register is also LT lockable. + Hardware does not clear or set any of these bits automatically based on IGD + being disabled/enabled. + BIOS Requirement: BIOS must not set this field to 0h if IVD (bit 1 of this register) + is 0. + Encoding Description + 5h 32 MB + 6h 48 MB + 7h 64 MB + 8h 128 MB + 9h 256 MB + Ah 96 MB + Bh 160 MB + Ch 224 MB + Dh 352 MB + 0h 0MB + 1h 32MB + 2h 64MB + 3h 96MB + 4h 128MB + Eh 448MB + Fh 480MB + 10h 512MB + Other Reserved + 0h 0MB + 1h 32MB + 2h 64MB + 3h 96MB + 4h 128MB + 5h 160MB + 6h 192MB + 7h 224MB + 8h 256MB + 9h 288MB + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 26 + Default + Bit Access Value RST/PWR Description + Ah 320MB + Bh 352MB + Ch 384MB + Dh 416MB + Eh 448MB + Fh 480MB + 10h 512MB + Other Reserved +2 RO 0h Reserved (RSVD). +1 RO-V 0b Uncore + IGD VGA Disable (IVD): + 0: Enable. Device 2 (IGD) claims VGA memory and I/O cycles. The Sub-Class + Code within Device 2 Class Code register is 00. + 1: Disable. Device 2 (IGD) does not claim VGA memory or I/O cycles. The Sub- + Class Code field within Device 2 function 0 Class Code register is 80. + BIOS Requirement: BIOS must not set this bit to 0 if the GMS field (bits 7:3 of this + register) pre-allocates no memory. + This bit MUST be set to 1 if Device 2 is disabled, either via a fuse or a fuse + override (CAPID0_A[IGD] = 1) or via a register (DEVEN[3] = 0). + This register is locked by LT lock. + Encoding Description + 0b Enable + 1b Disable + 0b Enable + 1b Disable + 0b Enable + 1b Disable +0 RO-V 0b Uncore + GGC Lock (GGCLCK): + When set to 1b, this bit locks all bits in this register. + + + +1.26 DEVEN0 - Device Enable +B/D/F/Type: 0/2/0/PCI +Address Offset: 54-57h +Default Value: 0000209Fh +Access: RO-V; +Size: 32 bits +BIOS Optimal Default: 000000h + +Supports enabling or disabling PCI devices and functions within the CPU package. The table below the +bit definitions describes the behavior of all combinations of transactions to devices controlled by this +register. +All the bits in this register are LT Lockable. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 27 + Default + Bit Access Value RST/PWR Description +31:15 RO 0h Reserved (RSVD). +14 RO-V 0b Uncore + Chap Enable (D7EN): + 0: Bus 0 Device 7 is disabled and not visible. + 1: Bus 0 Device 7 is enabled and visible. + Non-production BIOS code should provide a setup option to enable Bus 0 Device + 7. When enabled, Bus 0 Device 7 must be initialized in accord with standard PCI + device initialization procedures. + Encoding Description + 0b Device 7 disabled. + 1b Device 7 enabled. +13 RO-V 1b Uncore + PEG60 Enable (D6F0EN): + 0: Bus 0 Device 6 Function 0 is disabled and hidden. + 1: Bus 0 Device 6 Function 0 is enabled and visible. + This bit is set to 0 and remains 0 if PEG60 capability is disabled. + Encoding Description + 0b Device 6 disabled. + 1b Device 6 enabled. + 0b Device 6 disabled. + 1b Device 6 enabled. + 0b Device 6 disabled. + 1b Device 6 enabled. + 0b Device 6 disabled. + 1b Device 6 enabled. + 0b Device 6 disabled. + 1b Device 6 enabled. + 0b Device 6 disabled. + 1b Device 6 enabled. + 0b Device 6 disabled. + 1b Device 6 enabled. + 0b Device 6 disabled. + 1b Device 6 enabled. + 0b Device 6 disabled. + 1b Device 6 enabled. +12:8 RO 0h Reserved (RSVD). +7 RO-V 1b Uncore + Device 4 Enable (D4EN): + 0: Bus 0 Device 4 is disabled and not visible. + 1: Bus 0 Device 4 is enabled and visible. + This bit is set to 0 and remains 0 if Device 4 capability is disabled. +6:5 RO 0h Reserved (RSVD). +4 RO-V 1b Uncore + Internal Graphics Engine (D2EN): + 0: Bus 0 Device 2 is disabled and hidden. + 1: Bus 0 Device 2 is enabled and visible. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 28 + Default + Bit Access Value RST/PWR Description + This bit is set to 0 and remains 0 if Device 2 capability is disabled. + +3 RO-V 1b Uncore + PEG10 Enable (D1F0EN): + 0: Bus 0 Device 1 Function 0 is disabled and hidden. + 1: Bus 0 Device 1 Function 0 is enabled and visible. + This bit is set to 0 and remains 0 if PEG10 capability is disabled. +2 RO-V 1b Uncore + PEG11 Enable (D1F1EN): + 0: Bus 0 Device 1 Function 1 is disabled and hidden. + 1: Bus 0 Device 1 Function 1 is enabled and visible. + This bit is set to 0 and remains 0 if: + - PEG11 capability is disabled by fuses, OR + - PEG11 is disabled by strap (PEG0CFGSEL). +1 RO-V 1b Uncore + PEG12 Enable (D1F2EN): + 0: Bus 0 Device 1 Function 2 is disabled and hidden. + 1: Bus 0 Device 1 Function 2 is enabled and visible. + This bit is set to 0 and remains 0 if: + - PEG12 capability is disabled by fuses, OR + - PEG12 is disabled by strap (PEG0CFGSEL). +0 RO-V 1b Uncore + Host Bridge (D0EN): + Bus 0 Device 0 Function 0 cannot be disabled and is therefore hardwired to 1. + + + +1.27 BDSM - Base Data of Stolen Memory +B/D/F/Type: 0/2/0/PCI +Address Offset: 5C-5Fh +Default Value: 00000000h +Access: RO-V; +Size: 32 bits +BIOS Optimal Default: 00000h + +This register contains the base address of graphics data stolen DRAM memory. The BIOS determines the +base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 +offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BC bits 31:20). + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 29 + Default + Bit Access Value RST/PWR Description +31:20 RO-V 000h Uncore + Graphics Base of Stolen Memory (BDSM): + This register contains bits 31 to 20 of the base address of stolen DRAM memory. + The BIOS determines the base of graphics stolen memory by subtracting the + graphics stolen memory size (PCI Device 0 offset 52 bits 6:4) from TOLUD (PCI + Device 0 offset BC bits 31:20). + +19:1 RO 0h Reserved (RSVD). +0 RO-V 0b Uncore + Lock (LOCK): + This bit locks all writeable settings in this register, including itself. + + + +1.28 HSRW - Hardware Scratch Read Write +B/D/F/Type: 0/2/0/PCI +Address Offset: 60-61h +Default Value: 0000h +Access: RW; +Size: 16 bits + +This register is reserved as a hardware scratchpad. + Bit Access Default Value RST/PWR Description +15:0 RW 0000h FLR, Uncore + Reserved R/W (ReservedRW): + Reserved for future use. + + + +1.29 MSAC - Multi Size Aperture Control +B/D/F/Type: 0/2/0/PCI +Address Offset: 62h +Default Value: 02h +Access: RW; RW-K; +Size: 8 bits +BIOS Optimal Default: 0h + +This register determines the size of the graphics memory aperture in function 0 and in the trusted space. +Only the system BIOS writes this register based on pre-boot address allocation efforts, but the graphics +may read this register to determine the correct aperture size. The system BIOS needs to save this value +on boot so that it can reset it correctly during S3 resume. +Note: This register is LT locked. It becomes read-only when trusted environment is launched. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 30 + Default + Bit Access Value RST/PWR Description +7:4 RW 0h Uncore + Reserved R/W (RSVDRW): + Scratch Bits Only. Have no physical effect on hardware. + +3:3 RO 0h Reserved (RSVD). +2 RW-K 0b Uncore + Untrusted Aperture Size High (LHSASH): + This field is used with LHSASL. The description below is for both fields (LHSASH + & LHSASL). + 11b: Bits [28:27] of GMADR are RO, allowing 512 MB of GMADR. + 10b: Illegal Programming. + 01b: Bit [28] of GMADR is RW but bit [27] of GMADR is RO, allowing 256 MB of + GMADR. + 00b: Bits [28:27] of GMADR are RW, allowing 128 MB of GMADR. +1 RW-K 1b Uncore + Untrusted Aperture Size Low (LHSASL): + This field is used with LHSASH. The description below is for both fields + (LHSASH & LHSASL). + 11b: Bits [28:27] of GMADR are RO, allowing 512 MB of GMADR. + 10b: Illegal Programming. + 01b: Bit [28] of GMADR is RW but bit [27] of GMADR is RO, allowing 256 MB of + GMADR. + 00b: Bits [28:27] of GMADR are RW, allowing 128 MB of GMADR. +0:0 RO 0h Reserved (RSVD). + + + +1.30 VTD_STATUS - VTd Status +B/D/F/Type: 0/2/0/PCI +Address Offset: 63h +Default Value: 00h +Access: RO-VFW; +Size: 8 bits +BIOS Optimal Default: 00h + +This register contains indicator bits for Graphics VTd mode. +Bit Access Default Value RST/PWR Description +7:1 RO 0h Reserved (RSVD). +0 RO-VFW 0b Uncore + GFX VTd Active (VTACT): + Reflects whether GFX VTd Mode is active, 1 if active, 0 if inactive. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 31 + 1.31 MSI_CAPID - Message Signaled Interrupts Capability ID +B/D/F/Type: 0/2/0/PCI +Address Offset: 90-91h +Default Value: D005h +Access: RO; +Size: 16 bits + +When a device supports MSI it can generate an interrupt request to the processor by writing a predefined +data item (a message) to a predefined memory address. Reporting this capability's existence can be +disabled by setting MSICH (CAPL[0] @ 7Fh). In that case, walking this linked list skips this capability and +instead goes directly to the PCI PM capability. + Default + Bit Access Value RST/PWR Description +15:8 RO D0h Uncore + Pointer to Next Capability (POINTNEXT): + This field is a pointer to the next item in the capabilities list, which is the Power + Management capability. +7:0 RO 05h Uncore + Capability ID (CAPID): + 05h: Identifies this linked list item (capability structure) as being for MSI + registers. + + + +1.32 MC - Message Control +B/D/F/Type: 0/2/0/PCI +Address Offset: 92-93h +Default Value: 0000h +Access: RO; RW; +Size: 16 bits +BIOS Optimal Default: 00h + +System software can modify bits in this register, but the device is prohibited from doing so. If the device +writes the same message multiple times, only one of those messages is guaranteed to be serviced. If all +of them must be serviced, the device must not generate the same message again until the driver services +the earlier one. + Default + Bit Access Value RST/PWR Description +15:8 RO 0h Reserved (RSVD). +7 RO 0b Uncore + 64 Bit Capable (CAP64B): + Hardwired to 0 to indicate that the function does not implement the upper 32 bits + of the Message Address register and is not able to generate a 64-bit memory + address. +6:4 RW 000b + FLR, Multiple Message Enable (MME): + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 32 + Default +Bit Access Value RST/PWR Description + Uncore System software programs this field to indicate the actual number of messages + allocated to this device. This number will be less than or equal to the number + actually requested. + The encoding is the same as for the MMC field below. + +3:1 RO 000b Uncore + Multiple Message Capable (MMC): + System software reads this field to determine the number of messages + requested by this device. + Value: Number of requests + 000: 1 + All of the following are reserved in this implementation: + 001: 2 + 010: 4 + 011: 8 + 100: 16 + 101: 32 + 110: Reserved + 111: Reserved +0 RW 0b FLR, + MSI Enable (MSIEN): + Uncore + Controls this device's ability to generate MSIs. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 33 + 1.33 MA - Message Address +B/D/F/Type: 0/2/0/PCI +Address Offset: 94-97h +Default Value: 00000000h +Access: RW; RO; +Size: 32 bits + +This register contains the Message Address for MSIs sent by the device. + Default + Bit Access Value RST/PWR Description +31:2 RW 00000000h FLR, + Message Address (MESSADD): + Uncore + Used by system software to assign an MSI address to the device. + The device handles an MSI by writing the padded contents of the MD register + to this address. +1:0 RO 00b Uncore + Force Dword Align (FDWORD): + Hardwired to 0 so that addresses assigned by system software are always + aligned on a DWORD address boundary. + + + +1.34 MD - Message Data +B/D/F/Type: 0/2/0/PCI +Address Offset: 98-99h +Default Value: 0000h +Access: RW; +Size: 16 bits + +This register contains the Message Data for MSIs sent by the device. + Default + Bit Access Value RST/PWR Description +15:0 RW 0000h FLR, + Message Data (MESSDATA): + Uncore + Base message data pattern assigned by system software and used to handle an + MSI from the device. + When the device must generate an interrupt request, it writes a 32-bit value to the + memory address in the MA register. The upper 16 bits are always set to 0. The + lower 16 bits are supplied by this register. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 34 + 1.35 AFCIDNP - Advanced Features Capabilities Identifier + and Next Pointer +B/D/F/Type: 0/2/0/PCI +Address Offset: A4-A5h +Default Value: 0013h +Access: RO; +Size: 16 bits + +When this capability is linked into the list, the second function of the Internal Graphics Device can be +reset independently of the first function. + Default + Bit Access Value RST/PWR Description +15:8 RO 00h Uncore + NEXT_PTR (NEXT_PTR): + This field is a pointer to the next item in the capabilities list. If this is the final + capability in the list then this field must be 00h. +7:0 RO 13h Uncore + CAP_ID (CAP_ID): + A value of 13h identifies that this PCI Function is capable of Advanced Features. + + + +1.36 AFLC - Advanced Features Length and Capabilities +B/D/F/Type: 0/2/0/PCI +Address Offset: A6-A7h +Default Value: 0306h +Access: RO; +Size: 16 bits +BIOS Optimal Default: 00h + +See the July 27th 2006 Engineering Change Notice for Conventional PCI Advanced Capabilities. + Default + Bit Access Value RST/PWR Description +15:10 RO 0h Reserved (RSVD). +9 RO 1b Uncore + FLR Capability (FLR_CAP): + Indicates support for Function Level Reset (FLR). +8 RO 1b Uncore + TXP Capability (TXP_CAP): + Indicates support for the Transactions Pending bit. +7:0 RO 06h Uncore + Capability Length (CAP_LEN): + The Advanced Features capability structure requires 6 bytes of configuration + space. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 35 + 1.37 AFCTL - Advanced Features Control + B/D/F/Type: 0/2/0/PCI + Address Offset: A8h + Default Value: 00h + Access: RW1S; + Size: 8 bits + BIOS Optimal 00h + Default: + Default +Bit Access Value RST/PWR Description +7:1 RO 0h Reserved (RSVD). +0 RW1S 0b FLR, + Initiate Function Level Reset (INIT_FLR): + Uncore + A write of 1b initiates Function Level Reset (FLR). + FLR requirements are defined in the PCI Express Base Specification. Registers + and state information that do not apply to conventional PCI are exempt from the + FLR requirements given there. + Once written 1, FLR will be initiated. During FLR, a read returns 1s since device 2 + reads abort. Once FLR completes, hardware clears the bit to 0. + + + The following sequence is required in order to initiate the FLR for 0/2/0 PCI: + 1. Write MMIO 0x45010=0x00000002 + 2. Write MMIO 0xC2004=0x00000005 + 3. Read MMIO 0xC7204, modify bit 0=0, write back to MMIO 0xC7204 + 4. Poll for MMIO 0xC7200 bit 31=0 and bits 29:28=00. Timeout and continue if poll + not complete after 5 seconds. + 5. Write MMIO 0xD0100=0x00000002 + 6. Write 1b to INIT_FLR + The above MMIO register addresses are offsets from the 0/2/0 PCI config register + offset 0x10, GTTMMADR, bits 38:22 Memory Base Address (MBA). + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 36 + 1.38 AFSTS - Advanced Features Status +B/D/F/Type: 0/2/0/PCI +Address Offset: A9h +Default Value: 00h +Access: RO; +Size: 8 bits +BIOS Optimal Default: 00h + +See the July 27th 2006 Engineering Change Notice for Conventional PCI Advanced Capabilities. + Default +Bit Access Value RST/PWR Description +7:1 RO 0h Reserved (RSVD). +0 RO 0b Uncore + Transactions Pending (TP): + 1: The Function has issued one or more non-posted transactions that have not + been completed, including non-posted transactions that a target has terminated + with Retry. + 0: All non-posted transactions are complete. + + + +1.39 PMCAPID - Power Management Capabilities ID +B/D/F/Type: 0/2/0/PCI +Address Offset: D0-D1h +Default Value: A401h +Access: RO; +Size: 16 bits + +This register contains the PCI Power Management Capability ID and the next capability pointer. + Bit Access Default Value RST/PWR Description +15:8 RO A4h Uncore + Next Capability Pointer (NEXT_PTR): + This field points to the next item in the capabilities list. + +7:0 RO 01h Uncore + Capability Identifier (CAP_ID): + SIG defines this ID, 01h for power management. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 37 + 1.40 PMCAP - Power Management Capabilities +B/D/F/Type: 0/2/0/PCI +Address Offset: D2-D3h +Default Value: 0022h +Access: RO; +Size: 16 bits +BIOS Optimal Default: 0h + +This register provides information on the capabilities of functions related to power management. + Default + Bit Access Value RST/PWR Description +15:11 RO 00h Uncore + PME Support (PMES): + This field indicates the power states in which the IGD may assert PME#. It is + hardwired to 0 to indicate that the IGD does not assert the PME# signal. +10 RO 0b Uncore + D2 Support (D2): + The D2 power management state is not supported. This bit is hardwired to 0. + +9 RO 0b Uncore + D1 Support (D1): + The D1 power management state is not supported. This bit is hardwired to 0. +8:6 RO 0h Reserved (RSVD). +5 RO 1b Uncore + Device Specific Initialization (DSI): + This bit is hardwired to 1 to indicate that special initialization of the IGD is + required before a generic class device driver uses it. +4 RO 0h Reserved (RSVD). +3 RO 0b Uncore + PME Clock (PMECLK): + Hardwired to 0 to indicate that IGD does not support PME# generation. +2:0 RO 010b Uncore + Version (VER): + Hardwired to 010b to indicate that four bytes of power management registers are + implemented and that this device complies with revision 1.1 of the PCI Power + Management Interface Specification. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 38 + 1.41 PMCS - Power Management Control/Status +B/D/F/Type: 0/2/0/PCI +Address Offset: D4-D5h +Default Value: 0000h +Access: RO; RW; +Size: 16 bits +BIOS Optimal Default: 00h + + + + Default + Bit Access Value RST/PWR Description +15 RO 0b Uncore + PME Status (PMESTS): + This bit is 0 to indicate that IGD does not support PME# generation from D3 + (cold). +14:13 RO 00b Uncore + Data Scale (DSCALE): + The IGD does not support data register. This field always returns 00b when read; + writes have no effect. +12:9 RO 0h Uncore + Data Select (DSEL): + The IGD does not support data register. This field always returns 0h when read; + writes have no effect. +8 RO 0b Uncore + PME Enable (PME_EN): + This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled. + +7:2 RO 0h Reserved (RSVD). +1:0 RW 00b FLR, + Power State (PWRSTAT): + Uncore + This field indicates the current power state of the IGD and can be used to set the + IGD into a new power state. If software attempts to write an unsupported state to + this field, write operations must complete normally on the bus but the data is + discarded and no state change occurs. On a transition from D3 to D0 the graphics + controller is optionally reset to initial values. Behavior of the graphics controller in + supported states is detailed in the BSpec power management section. + Bits [1:0] Power state: + 00b: D0 Default + 01b: D1 Not Supported + 10b: D2 Not Supported + 11b: D3 + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 39 + 1.42 SWSMI - Software SMI +B/D/F/Type: 0/2/0/PCI +Address Offset: E0-E1h +Default Value: 0000h +Access: RW; +Size: 16 bits + + + + Bit Access Default Value RST/PWR Description +15:8 RW 00h Uncore Software Scratch Bits (SWSB). +7:1 RW 00h Uncore + Software Flag (SWF): + Indicates caller and SMI function desired, as well as return result. +0 RW 0b Uncore + GMCH Software SMI Event (GSSMIE): + When 1 this bit triggers an SMI. Software must write 0 to clear this bit. + SMI is triggered only if SWSCI[SMISCISEL] is set to select SMI. + + + +1.43 GSE - Graphics System Event +B/D/F/Type: 0/2/0/PCI +Address Offset: E4-E7h +Default Value: 00000000h +Access: RW; +Size: 32 bits + +This register can be accessed by either Byte, Word, or Dword PCI config cycles. Writing this register +causes the Graphics System Event (Display Interrupt) if enabled. + Default + Bit Access Value RST/PWR Description +31:24 RW 00h Uncore + GSE Scratch Trigger 3 (GSE3): + When written, this scratch byte triggers an interrupt when GSE is enabled in the + display register and the Display B Event is enabled in IER and unmasked in IMR + etc. If written as part of a 16-bit or 32-bit write, only one interrupt is generated in + common. +23:16 RW 00h Uncore + GSE Scratch Trigger 2 (GSE2): + When written, this scratch byte triggers an interrupt when GSE is enabled in the + isplay register and the Display B Event is enabled in IER and unmasked in IMR + etc. If written as part of a 16-bit or 32-bit write, only one interrupt is generated in + common. +15:8 RW 00h Uncore + GSE Scratch Trigger 1 (GSE1): + When written, this scratch byte triggers an interrupt when GSE is enabled in the + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 40 + Default + Bit Access Value RST/PWR Description + display register and the Display B Event is enabled in IER and unmasked in IMR + etc. If written as part of a 16-bit or 32-bit write, only one interrupt is generated in + common. + +7:0 RW 00h Uncore + GSE Scratch Trigger 0 (GSE0): + When written, this scratch byte triggers an interrupt when GSE is enabled in the + display register and the Display B Event is enabled in IER and unmasked in IMR + etc. If written as part of a 16-bit or 32-bit write, only one interrupt is generated in + common. + + + +1.44 SWSCI - Software SCI +B/D/F/Type: 0/2/0/PCI +Address Offset: E8-E9h +Default Value: 0000h +Access: RW-O; RW; +Size: 16 bits + +This register serves 2 purposes: +1. Support selection of SMI or SCI event source (SMISCISEL - bit15). +2. SCI Event trigger (GSSCIE - bit 0). +To generate a software SCI event, software (System BIOS/Graphics driver) should program bit 15 +(SMISCISEL) to 1. This is typically programmed once (assuming SMIs are never triggered). On a 0 to 1 +subsequent transition in bit 0 of this register (caused by a software write operation), the CPU sends a +single SCI message down the DMI link to PCH. PCH then sets the DMISCI bit in its TCO1_STS register +and the TCOSCI_STS bit in its GPE0 register on receiving this message from DMI. The corresponding +SCI event handler in the BIOS must be defined as an _Lxx method, indicating level trigger to the +operating system. +Once written as 1, software must write 0 to this bit to clear it, and all other write transitions (1->0, 0->0, 1- +>1) or if bit 15 is 0 do not cause the CPU to send an SCI message to the DMI link. +To generate a software SMI event, software should program bit 15 to 0 and trigger SMI via writes to the +SWSMI register (See the SWSMI register for programming details). + Bit Access Default Value RST/PWR Description +15 RW-O 0b Uncore + SMI or SCI event select (SMISCISEL): + 0 = SMI (default) + 1 = SCI + If the selected event source is SMI, SMI trigger and associated scratch + bits accesses are performed via the SWSMI register at offset E0h. If the + SCI event source is selected, the rest of the bits in this register provide + SCI trigger capability and associated SW scratch pad area. +14:1 RW 00000000000000b Uncore + Software scratch bits (SCISB): + Software scratch bits (read/write bits not used by hardware). + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 41 + Bit Access Default Value RST/PWR Description +0 RW 0b Uncore + Software SCI Event (GSSCIE): + If the SCI event is selected (SMISCISEL = 1), on a 0 to 1 transition of the + GSSCIE bit, a SCI message is sent via DMI link to ICH to cause the + TCOSCI_STS bit in its GPE0 register to be set to 1. + Software must write a 0 to clear this bit. + + + +1.45 ASLS - ASL Storage +B/D/F/Type: 0/2/0/PCI +Address Offset: FC-FFh +Default Value: 00000000h +Access: RW; +Size: 32 bits + +This software scratch register only needs to be read/write accessible. The exact bit register usage must +be worked out in common between System BIOS and driver software, but storage for switching/indicating +up to six devices is possible with this amount. +For each device, the ASL control method requires two bits for _DOD (BIOS detectable yes or no, +VGA/NonVGA), one bit for _DGS (enable/disable requested), and two bits for _DCS (enabled +now/disabled now, connected or not). + Bit Access Default Value RST/PWR Description +31:0 RW 00000000h Uncore + Device Switching Storage (DSS): + Software controlled usage to support device switching. + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 42 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V3 Pt 2 – 05 12 5/31/2012 43 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol3_part3.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol3_part3.txt new file mode 100644 index 0000000..c1242a9 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol3_part3.txt @@ -0,0 +1,6477 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 3 Part 3: North Display Engine +Registers +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 + Contents +1. Introduction............................................................................................................................................ 6 + 1.1 Terminology ......................................................................................................................................... 6 + 1.2 Display Pixel Rate Limitations .............................................................................................................. 6 +2. Display Mode Set Sequence................................................................................................................. 9 +3. North Display Engine Shared Functions .......................................................................................... 12 + 3.1 VGA .................................................................................................................................................... 12 + 3.1.1 VGA_CONTROL-VGA Control ..................................................................................................... 12 + 3.2 Frame Buffer Compression ................................................................................................................ 14 + 3.2.1 FBC_CFB_BASE-FBC Compressed Buffer Address ................................................................... 14 + 3.2.2 FBC_CTL-FBC Control ................................................................................................................. 14 + 3.3 Interrupts ............................................................................................................................................ 16 + 3.3.1 Display Engine Interrupt Bit Definition .......................................................................................... 17 + 3.3.2 GT Interrupt Bit Definition ............................................................................................................. 19 + 3.3.3 Power Management Interrupt Bit Definition .................................................................................. 20 + 3.3.4 ISR-Interrupt Status ...................................................................................................................... 20 + 3.4 IMR-Interrupt Mask ............................................................................................................................ 21 + 3.4.1 IIR-Interrupt Identity ...................................................................................................................... 22 + 3.4.2 IER-Interrupt Enable ..................................................................................................................... 23 + 3.4.3 HOTPLUG_CTL-Hot Plug Control ................................................................................................ 23 + 3.4.4 ERR_INT-Error Interrupts ............................................................................................................. 24 + 3.5 Display Engine Render Response ..................................................................................................... 27 + 3.5.1 Display Engine Render Response Message Bit Definition .......................................................... 27 + 3.5.2 DE_RRMR - Display Engine Render Response Mask ................................................................. 28 + 3.6 Display Timestamp............................................................................................................................. 29 + 3.6.1 TIMESTAMP_CTR-Time Stamp Counter Value .......................................................................... 29 + 3.7 Display Arbitration Control ................................................................................................................. 30 + 3.7.1 ARB_CTL-Display Arbitration Control 1 ....................................................................................... 30 + 3.7.2 ARB_CTL2-Display Arbitration Control 2 ..................................................................................... 31 + 3.7.3 MSG_CTL-Display Message Control ........................................................................................... 32 + 3.8 Display Watermarks ........................................................................................................................... 33 + 3.8.1 WM_PIPE-Pipe Main Watermarks ............................................................................................... 33 + 3.8.2 WM_LP-Low Power Watermarks ................................................................................................. 34 + 3.8.3 WM_LP_SPR-Low Power Sprite Watermark ............................................................................... 35 + 3.9 Backlight Control ................................................................................................................................ 36 + 3.9.1 BLC_PWM_CTL-Backlight PWM Control ..................................................................................... 36 + 3.9.2 BLC_PWM_DATA-Backlight PWM Data ...................................................................................... 37 + 3.9.3 BLM_HIST_CTL-Image Enhancement Control ............................................................................ 38 + 3.9.4 BLM_HIST_BIN-Image Enhancement Bin Data........................................................................... 40 + 3.9.5 BLM_HIST_GUARD-Histogram Threshold Guardband ............................................................... 41 + 3.10 Color Space Conversion ................................................................................................................... 41 + 3.10.1 CSC_COEFF-CSC Coefficients ................................................................................................. 45 + 3.10.2 CSC_MODE-CSC Mode ............................................................................................................ 46 + 3.10.3 CSC_PREOFF-CSC Pre-Offsets ............................................................................................... 47 + 3.10.4 CSC_POSTOFF-CSC Post-Offsets ........................................................................................... 48 + 3.11 Pipe Palette and Gamma.................................................................................................................. 49 + 3.11.1 PAL_LGC-Legacy Palette .......................................................................................................... 53 + 3.11.2 PAL_PREC_INDEX-Precision Palette Index .............................................................................. 54 + 3.11.3 PAL_PREC_DATA-Precision Palette Data ................................................................................ 55 + 3.11.4 PAL_GC_MAX-Gamma Correction Max .................................................................................... 57 + 3.11.5 PAL_EXT_GC_MAX-Extended Gamma Correction Max ........................................................... 58 + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 3 + 3.12 Pipe Color Gamut Enhancement ...................................................................................................... 59 + 3.12.1 CGE_CTRL-Color Gamut Enhancement Control ....................................................................... 61 + 3.12.2 CGE_WEIGHT-Color Gamut Enhancement Weight .................................................................. 62 + 3.13 Software Flags .................................................................................................................................. 64 + 3.14 GTSCRATCH-GT Scratchpad .......................................................................................................... 64 +4. North Display Engine Pipe and Port Controls .................................................................................. 66 + 4.1 Pipe Timing ........................................................................................................................................ 66 + 4.1.1 HTOTAL-Horizontal Total ............................................................................................................. 66 + 4.1.2 HBLANK-Horizontal Blank ............................................................................................................ 67 + 4.1.3 HSYNC-Horizontal Sync ............................................................................................................... 68 + 4.1.4 VTOTAL-Vertical Total ................................................................................................................. 69 + 4.1.5 VBLANK-Vertical Blank ................................................................................................................ 70 + 4.1.6 VSYNC-Vertical Sync ................................................................................................................... 71 + 4.1.7 SRCSZ-Source Image Size .......................................................................................................... 72 + 4.1.8 VSYNCSHIFT-Vertical Sync Shift ................................................................................................ 73 + 4.2 Pipe M/N Values ................................................................................................................................ 73 + 4.2.1 DATAM-Data M Value .................................................................................................................. 74 + 4.2.2 DATAN-Data N Value ................................................................................................................... 75 + 4.2.3 LINKM-Link M Value ..................................................................................................................... 76 + 4.2.4 LINKN-Link N Value ..................................................................................................................... 77 + 4.3 FDI Transmit ...................................................................................................................................... 78 + 4.3.1 FDI_TX_CTL-FDI Tx Control ........................................................................................................ 78 + 4.4 DisplayPort ......................................................................................................................................... 82 + 4.4.1 DP_CTL-DisplayPort Control........................................................................................................ 82 + 4.4.2 DP_AUX_CTL-DisplayPort AUX Channel Control ....................................................................... 87 + 4.4.3 DP_AUX_DATA-DisplayPort AUX Channel Data ........................................................................ 89 + 4.5 Panel Fitter ......................................................................................................................................... 90 + 4.5.1 PF_PWR_GATE-Panel Fitter Power Gate Control ...................................................................... 90 + 4.5.2 PF_WIN_POS-Panel Fitter Window Position ............................................................................... 91 + 4.5.3 PF_WIN_SZ-Panel Fitter Window Size ........................................................................................ 92 + 4.5.4 PF_CTRL-Panel Fitter Control ..................................................................................................... 93 + 4.5.5 PF_COEF_INDEX-Panel Fitter Coefficients Index....................................................................... 94 + 4.5.6 PF_COEF_DATA-Panel Fitter Coefficients Data ......................................................................... 96 +5. North Display Engine Pipe and Plane Controls ............................................................................... 98 + 5.1 Pipe Control ....................................................................................................................................... 98 + 5.1.1 PIPE_SCANLINE-Pipe Scan Line ................................................................................................ 98 + 5.1.2 PIPE_SCANLINECOMP-Pipe Scan Line Compare ..................................................................... 99 + 5.1.3 PIPE_CONF-Pipe Configuration ................................................................................................ 100 + 5.1.4 PIPE_FRMCNT-Pipe Frame Count ............................................................................................ 103 + 5.1.5 PIPE_FLIPCNT-Pipe Flip Count................................................................................................. 104 + 5.1.6 PIPE_FRMTMSTMP-Pipe Frame Time Stamp .......................................................................... 105 + 5.1.7 PIPE_FLIPTMSTMP-Pipe Flip Time Stamp ............................................................................... 106 + 5.2 Cursor Plane .................................................................................................................................... 106 + 5.2.1 CUR_CTL-Cursor Control .......................................................................................................... 107 + 5.2.2 CUR_BASE-Cursor Base Address ............................................................................................. 109 + 5.2.3 CUR_POS-Cursor Position ........................................................................................................ 110 + 5.2.4 CUR_PAL-Cursor Palette ........................................................................................................... 111 + 5.2.5 CUR_FBC_CTL-Cursor FBC Control ......................................................................................... 113 + 5.2.6 PLANE_SURFLIVE-Plane Live Base Address........................................................................... 114 + 5.3 Primary Plane ................................................................................................................................... 115 + 5.3.1 PRI_CTL-Primary Control ........................................................................................................... 115 + 5.3.2 PRI_LINOFF-Primary Linear Offset............................................................................................ 118 + 5.3.3 PRI_STRIDE-Primary Stride ...................................................................................................... 119 + 5.3.4 PRI_SURF-Primary Surface Base Address ............................................................................... 120 + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 4 + 5.3.5 PRI_TILEOFF-Primary Tiled Offset ............................................................................................ 121 + 5.4 Sprite Plane ...................................................................................................................................... 121 + 5.4.1 SPR_CTL-Sprite Control ............................................................................................................ 123 + 5.4.2 SPR_LINOFF-Sprite Linear Offset ............................................................................................. 126 + 5.4.3 SPR_STRIDE-Sprite Stride ........................................................................................................ 127 + 5.4.4 SPR_POS-Sprite Position .......................................................................................................... 128 + 5.4.5 SPR_SIZE-Sprite Size ................................................................................................................ 129 + 5.4.6 SPR_SURF-Sprite Surface Base Address ................................................................................. 130 + 5.4.7 SPR_TILEOFF-Sprite Tiled Offset ............................................................................................. 131 + 5.4.8 SPR_KEYVAL-Sprite Key Color Value ...................................................................................... 132 + 5.4.9 SPR_KEYMSK-Sprite Key Mask ................................................................................................ 133 + 5.4.10 SPR_KEYMAX-Sprite Key Color Max ...................................................................................... 134 + 5.4.11 SPR_SCALE-Sprite Scaler Control .......................................................................................... 135 + 5.4.12 SPR_GAMC-Sprite Gamma Correction ................................................................................... 137 + 5.4.13 SPR_GAMC16-Sprite Gamma Correction Point 16 ................................................................. 140 + 5.4.14 SPR_GAMC17-Sprite Gamma Correction Point 17 ................................................................. 142 + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 5 + 1. Introduction +This chapter contains the register descriptions for the display portion of a family of graphics devices. +These registers vary by devices within the family of devices, so special attention needs to be paid to +which devices use which registers and register fields. +Different devices within the family may add, modify, or delete registers or register fields relative to another +device in the same family based on the supported functions of that device. +Unless specifically indicated, all references to Cougarpoint (CPT) will apply to both Cougarpoint (CPT) +and Pantherpoint (PPT). + + +1.1 Terminology + Description Software Use Should be implemented as +Read/Write, R/W This bit can be read or written. + Don’t assume a value for these bits. Writes are ignored. Reads return zero. + Reserved + Writes have no effect. +Reserved: must Software must always write a zero to Writes are ignored. Reads return zero. Maybe be +be zero, MBZ these bits. This allows new features to connected as Read/Write in future projects. + be added using these bits that will be + disabled when using old software and + as the default case. +Reserved: PBC, Software must write the original value + Read only. +software must back to this bit. This allows new +preserve contents features to be added using these bits. +Read Only This bit is read only. The read value is According to each specific bit. The bit value is determined + determined by hardware. Writes to this by hardware and not affected by register writes to the + bit have no effect. actual bit. +Read/Clear, This bit can be read. Writes to it with a Hardware events cause the bit to be set and the bit will be +Read/Write Clear one cause the bit to clear. cleared on a write operation where the corresponding bit + has a one for a value. +Double Buffered Two stages of registers used. First stage is written into + Write when desired. Read gives the + and used for readback (unless specified otherwise). First + unbuffered value (written value) unless + stage value is transferred into second stage at the update + specified otherwise. Written values will + update to take effect after a certain point. Second stage value is used to control hardware. + point. Arm/disarm flag for specific arming sequences. + + Some have a specific arming + sequence where a write to another + register is required before the update + can take place. This is used to ensure + atomic updates of several registers. + + + +1.2 Display Pixel Rate Limitations +The maximum display pixel rate is limited by factors including the memory bandwidth and latency +available to display, maximum watermark values, maximum display PLL frequencies, maximum +bandwidth supported by the port technology, and restrictions within the display pipes. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 6 + DisplayPort Restrictions (maximum may be limited by other factors): + Port Configuration Maximum Pixel Rate +DisplayPort A (eDP) 6 bits per color 388 MHz +DisplayPort A (eDP) 8 bits per color 348 MHz +DisplayPort B, C, D 6 bits per color with FDI using 4 lanes 357 MHz +DisplayPort B, C, D 6 bits per color with FDI using 3 lanes 315 MHz +DisplayPort B, C, D 8 bits per color 348 MHz + + + +Display Pipe Restrictions (maximum may be limited by other factors): +Within a display pipe the restrictions on the maximum pixel rate are based on the planes enabled, the +pixel format of those planes, panel fitting, and sprite scaling. +The restriction is found with the following formula: + // Find the ratio for each plane + For each enabled plane (primary and sprite) { + If sprite scaling is enabled { + If pixel format is 16bpp {Plane Ratio = 32/33} + Else If pixel format is 32bpp {Plane Ratio = 16/19} + Else If pixel format is 64bpp {Plane Ratio = 8/12} + Else {Plane Ratio = 1/1} + } + Else If both sprite and primary planes are enabled { + If pixel format is 32bpp {Plane Ratio = 16/17} + Else If pixel format is 64bpp {Plane Ratio = 8/10} + Else {Plane Ratio = 1/1} + } + Else If only a single plane is enabled { + If pixel format is 64bpp {Plane Ratio = 8/9} + Else {Plane Ratio = 1/1} + } + Else {Plane Ratio = 1/1} + } + + + + + // Adjust for sprite down-scaling + If sprite scaling is enabled and sprite destination width < sprite source width { + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 7 + Sprite Plane Ratio = Sprite Plane Ratio * (sprite destination width / sprite source width) + } + // Select the worst ratio, Cursor does not contribute to any restrictions on pipe ratio + Pipe Ratio = Minimum(Sprite Plane Ratio, Primary Plane Ratio) + + + + + // Adjust for panel fitter horizontal down-scaling + If panel fitting is enabled and panel fitter window horizontal size < pipe horizontal source size { + Pipe Ratio = Pipe Ratio * (panel fitter window horizontal size / pipe horizontal source size) + } + + + + + // Adjust for 90% rule + Pipe Ratio = Minimum(Pipe Ratio, 9/10) + + + + + The resulting Pipe Ratio gives the ratio of the maximum allowed pixel rate for this display pipe + divided by the core display clock frequency (CDCLK). + On Ivybridge the core display clock frequency is 400 MHz. + + + + + Example Primary plane 32bpp, sprite plane 16bpp, sprite up-scaling, panel fitting down-scaling + 1/1.12: + Primary ratio = 16/19 + Sprite ratio = 32/33 + Pipe ratio = 16/19 * 1/1.12 + Maximum pipe pixel rate = 16/19 * 1/1.12 * 400 MHz = 300 MHz + + + + + Example Primary plane 64bpp, sprite plane 32bpp, sprite up-scaling, no panel fitting: + Primary ratio = 8/12 + Sprite ratio = 16/19 + Pipe ratio = 8/12 + Maximum pipe pixel rate = 8/12 * 400 MHz = 266 MHz + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 8 + 2. Display Mode Set Sequence + Wait Values +PCH clock reference source and PCH SSC modulator warmup = 1uS +PCH FDI receiver PLL warmup = 25us +PCH DPLL warmup = 50uS +CPU DisplayPort PLL warmup = 20uS +CPU FDI transmitter PLL warmup = 10us +DMI latency = 20uS +FDI training pattern 1 time = 0.5uS +FDI training pattern 2 time = 1.5uS +FDI idle pattern time = 31uS +FDI auto training time = 5uS + Enable Sequence +1. Enable panel power as needed to retrieve panel configuration + a. Enable panel power override using AUX VDD enable override bit + b. Wait for delay given in panel requirements + c. Leave panel power override enabled until later step +2. Enable PCH clock reference source and PCH SSC modulator, wait for warmup (Can be done anytime before + enabling port) +3. If enabling CPU embedded DisplayPort A: (Can be done anytime before enabling CPU pipe or port) + a. Enable PCH 120MHz clock source output to CPU, wait for DMI latency + b. Configure and enable CPU DisplayPort PLL in the DisplayPort A control register, wait for warmup +4. If enabling port on PCH: (Must be done before enabling CPU pipe or FDI) + a. Enable PCH FDI Receiver PLL, wait for warmup plus DMI latency + b. Switch from Rawclk to PCDclk in FDI Receiver + c. Enable CPU FDI Transmitter PLL, wait for warmup +5. Enable CPU panel fitter if needed (Can be done anytime before enabling CPU pipe) +6. Configure CPU pipe timings, M/N/TU, and other pipe settings (Can be done anytime before enabling CPU pipe) +7. Enable CPU pipe +8. Configure and enable CPU planes (VGA or hires) +9. If enabling port on PCH: + a. Program PCH FDI Receiver TU size same as Transmitter TU size for TU error checking + b. If Auto Train FDI + i. Set pre-emphasis and voltage (iterate if training steps fail) + ii. Enable CPU FDI Transmitter and PCH FDI Receiver with auto training enabled + Do not change auto-traing setting while FDI is enabled + iii. Wait for FDI auto training time + iv. Read CPU FDI Transmitter register for auto train done +  If not done, see note on FDI training failure handling + v. Enable PCH FDI Receiver Fill Start and Fill End Error Correction + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 9 + Wait Values + c. Configure and enable PCH DPLL, wait for PCH DPLL warmup (Can be done anytime before enabling PCH + transcoder) + d. Configure DPLL_SEL to set the DPLL to transcoder mapping and enable DPLL to the transcoder + e. Configure DPLL_CTL DPLL HDMI multiplier + f. Configure PCH transcoder timings, M/N/TU, and other transcoder settings (should match CPU settings) + g. Configure and enable Transcoder DisplayPort Control if DisplayPort will be used + Workaround: Set timing override (transcoder A 0xF0064, transcoder B 0xF1064, transcoder C 0xF2064) + bit 31 = 1 + h. Enable PCH transcoder +10. Enable ports + DisplayPort must enable in training pattern 1 +11. Enable panel power through panel power sequencing +12. Wait for panel power sequencing to reach enabled steady state +13. Disable panel power override +14. If DisplayPort, complete link training +15. Enable panel backlight +16. If Audio will be used, follow audio enable sequence documented in the audio registers section + Disable Sequence + 1. If Audio is used, follow audio disable sequence documented in the audio registers section. + 2. Disable panel backlight + 3. Disable panel power through panel power sequencing + 4. Disable CPU planes (VGA or hires) + 5. Disable CPU pipe + 6. Wait for CPU pipe off status (CPU pipe config register pipe state) + 7. Disable CPU panel fitter (Can be done anytime after CPU pipe is off) + 8. If disabling DisplayPort on PCH, write the DisplayPort control register bit 31 to 0b. + 9. If disabling CPU embedded DisplayPort A + a. Disable port + b. Disable CPU DisplayPort PLL in the DisplayPort A control register + c. Disable PCH 120MHz clock source output to CPU +10. If disabling any port on PCH: + a. Disable CPU FDI Transmitter and PCH FDI Receiver + Workaround: If Auto Train FDI, clear the transmitter auto training enable bit in the same write as the + transmitter is disabled and clear the receiver auto training enable bit in the same write as the receiver is + disabled. + b. Disable port + c. Disable PCH transcoder + d. Wait for PCH transcoder off status (PCH transcoder config register transcoder state) + Workaround: Clear timing override (transcoder A 0xF0064, transcoder B 0xF1064, transcoder C 0xF2064) + bit 31 = 0. + e. Disable Transcoder DisplayPort Control if DisplayPort was used + f. Disable Transcoder DPLL Enable bit in DPLL_SEL + g. Disable PCH DPLL (Can be done anytime after PCH ports and transcoder are off) + h. If no other PCH transcoder is enabled + i. Switch from PCDclk to Rawclk in PCH FDI Receiver + ii. Disable CPU FDI Transmitter PLL + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 10 + Wait Values + iii. Disable PCH FDI Receiver PLL +11. If SSC is no longer needed, disable PCH SSC modulator +12. If clock reference no longer needed, disable PCH clock reference source + Pipe timings change + Use complete disable sequence followed by complete enable sequence with new mode programming. + Pipe source size can be changed on the fly when panel fitting is enabled. + Notes + CPU FDI Transmitter should not be set to idle while PCH transcoder is enabled. + + + + + FDI training failure handling: + When a failure is detected, reread the failing register bit at least once to confirm failure, then disable CPU FDI + Transmitter and PCH FDI Receiver and return to the start of FDI training sequence to retry training. + Retraining should iterate through the available pre-emphasis and voltage settings. Each setting should be tried at + least twice before failing mode set. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 11 + 3. North Display Engine Shared + Functions +3.1 VGA +The VGA Control register is located here. The VGA I/O registers are located in the VGA Registers +document. + + +3.1.1 VGA_CONTROL-VGA Control + + VGA_CONTROL +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 41000h-41003h +Name: VGA Control +ShortName: VGA_CONTROL +Note: VGA requires panel fitting to be enabled. + Note: VGA is always connected to pipe A. +DWord Bit Description +0 31 VGA Display Disable + This bit will disable the VGA compatible display mode. It has no effect on VGA register or A0000- + BFFFF memory aperture accesses which are controlled by the PCI configuration and VGA register + settings. + VGA display should only be enabled if all display planes other than VGA are disabled. + Value Name Description + 0b Enable [Default] VGA Display Enabled + 1b Disable VGA Display Disabled + + + Programming Notes + The VGA SR01 screen off bit must be programmed when enabling and disabling VGA. See the VGA + Registers document. + KVMR sprite can temporarily override VGA display to be disabled, causing this bit to become 1b + (Disable). In order to properly disable VGA this bit should be programmed to 1b even if it already reads + as 1b. + Workaround : Program registers 42000h bits 31:29 = 101b and 42004h bit 25 = 0b before enabling + VGA display and keep them at those values while VGA display is enabled. It is safe to have those + values even when VGA display is disabled. + 30:27 Reserved + Format: PBC + 26 VGA Border Enable + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 12 + VGA_CONTROL + This bit determines if the VGA border areas are included in the active display area. The border will be + scaled along with the pixel data. + Value Name Description + 0b Disable [Default] VGA border areas are not displayed + 1b Enable VGA border areas are displayed + 25 Reserved + Format: PBC + 24 Pipe CSC Enable + This bit enables pipe color space conversion for the VGA pixel data. CSC mode in the pipe CSC + registers must be set to match the format of the VGA pixel data. + Value Name Description + 0b Bypass [Default] VGA pixel data bypasses the pipe color space conversion logic + 1b Pass VGA pixel data passes through the pipe color space conversion logic + 23:21 Reserved + Format: PBC + 20 Legacy 8Bit Palette En + This bit only affects reads and writes to the palette through VGA I/O addresses. In the 6-bit mode, the + 8-bits of data are shifted up two bits on the write (upper two bits are lost) and shifted two bits down on + the read. It provides backward compatibility for original VGA programs (in its default state) as well as + VESA VBE support for 8-bit palette. It does not affect palette accesses through the palette register + MMIO path. + Value Name Description + 0b 6 bit DAC [Default] 6-bit DAC + 1b 8 bit DAC 8-bit DAC + 17:16 Reserved + Format: PBC + 7:6 Blink Duty Cycle + Controls the VGA text mode blink duty cycle relative to the VGA cursor blink duty cycle. + Value Name Description + 00b 100% [Default] 100% Duty Cycle,% Full Cursor Rate + 01b 25% 25% Duty Cycle, 1/2 Cursor Rate + 10b 50% 50% Duty Cycle, 1/2 Cursor Rate + 11b 75% 75% Duty Cycle, 1/2 Cursor Rate + 5:0 VSYNC Blink Rate + Controls the VGA blink rate in terms of the number of VSYNCs per on/off cycle. These bits are + programmed with the (VSYNCs/cycle)/2-1. The proper programming of this register is determined by + the VSYNC rate that the display requires when in a VGA display mode. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 13 + 3.2 Frame Buffer Compression + +3.2.1 FBC_CFB_BASE-FBC Compressed Buffer Address + + FBC_CFB_BASE +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 43200h-43203h +Name: FBC Compressed Buffer Address +ShortName: FBC_CFB_BASE +The contents of this register can not be changed while compression is enabled. +DWord Bit Description +0 31:28 Reserved + Format: MBZ + 27:12 CFB Offset Address + This register specifies offset of the Compressed Frame Buffer from the base of stolen memory. The + buffer must be 4K byte aligned. + 11:0 Reserved + Format: MBZ + + + + +3.2.2 FBC_CTL-FBC Control + + FBC_CTL +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 43208h-4320Bh +Name: FBC Control +ShortName: FBC_CTL +The contents of this register can not be changed, except bit 31, while compression is enabled. + Frame Buffer Compression is only supported with 16bpp and 32bpp 8:8:8 primary plane source pixel formats. It is +not supported with any 10:10:10 or 64bpp format. + Frame Buffer Compression is only supported with memory surfaces of 4096 lines or less and pipe source sizes of +4096 pixels by 2048 lines or less. +DWord Bit Description +0 31 Enable FBC + This bit is used to globally enable FBC function at the next Vertical Blank start. + Frame buffer compression can only be enabled after the selected primary plane has been enabled for + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 14 + FBC_CTL + one or more vertical blanks and must be disabled before disabling the primary plane. + Value Name Description + 0b Disable [Default] Disable frame buffer compression + 1b Enable Enable frame buffer compression + + + Programming Notes Project + Workaround (WaFbcAsynchFlipDisableFbcQueue) : Display register 42000h bit 22 must be set + to 1b for the entire time that Frame Buffer Compression is enabled. + Workaround (WaFbcDisableDpfcClockGating) : Display register 42020h bit 9 must be set to 1b + for the entire time that Frame Buffer Compression is enabled. + 30:29 Plane Select + Value Name Description + 00b Primary Plane A [Default] Primary Plane A + 01b Primary Plane B Primary Plane B + 10b Primary Plane C Primary Plane C + 11b Reserved Reserved + 28 CPU Fence Enable + Value Name Description + 0b No CPU Disp Buf Display Buffer is not in a CPU fence. No modifications are allowed from + [Default] CPU to the Display Buffer + 1b CPU Disp Buf Display Buffer exists in a CPU fence + 27:25 Reserved + Format: MBZ + 14:11 Reserved + Format: MBZ + 7:6 Compression Limit + + This register sets a minimum limit on compression. This determines the maximum size of the + compressed frame buffer. Display lines that do not meet the compression limit will not be compressed, + so the best compression will be achieved with a 1:1 ratio. + + Compression Ratio 1, Pixel Format 16 bpp - Not Supported + + Compression Ratio 1, Pixel Format 32 bpp - Supported (CFB=FB) + + Compression Ratio 1/2, Pixel Format 16 bpp - Supported (CFB=FB) + + Compression Ratio 1/2, Pixel Format 32 bpp - Supported (CFB=1/2 FB) + + Compression Ratio 1/4, Pixel Format 16 bpp - Supported (CFB=1/2FB) + + Compression Ratio 1/4, Pixel Format 32 bpp - Supported (CFB=1/4 FB) + + FB = Frame Buffer Size + + CFB = Compressed Frame Buffer Size + Value Name Description + 00b 1:1 1:1 compression, compressed buffer is the same size as the uncompressed buffer + [Default] + 01b 2:1 2:1 compression, compressed buffer is one half the size of the uncompressed + buffer. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 15 + FBC_CTL + 10b 4:1 4:1 compression, compressed buffer is one quarter the size of the uncompressed + buffer. + 11b Reserved Reserved + 5:4 Write Back Watermark + The compressed data write back engine waits for this number of entries to be ready before writing the + data out to memory. + Value Name Description + 00b 4 [Default] 4 entries + 01b 8 8 entries + 10b 16 16 entries + 11b 32 32 entries + 3:0 CPU Fence Number + Default Value: 0000b Fence 0 + + + Programming Notes + Restriction : This field must be programmed to 0000b. + + + + +3.3 Interrupts + + + + +For every first level interrupt bit: + The interrupt event comes in. + There may be more levels of interrupt handling behind each event. For example the PCH + Display interrupt event is the result of the SDE interrupt registers. + The interrupt event goes to the Interrupt Status Register (ISR) where live status can be read back. + The live status is not useful for pulse interrupt events due to the short period that the status + will be present. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 16 + The interrupt event is ANDed with the inverted Interrupt Mask Register (IMR) to create the + unmasked interrupt. + Only unmasked interrupts will proceed. + The unmasked interrupt rising edge sets the sticky bit in the Interrupt Indentity Register (IIR). + The IIR can be cleared by writing a 1 to it. + The IIR can queue up to two interrupt events. When the IIR is cleared, it will set itself again + if a second event was stored. + The sticky interrupt is ANDed with the Interrupt Enable Register (IER) to create the enabled + interrupt. + Only enabled interrupts will proceed. +All enabled interrupts are then ORed to create the combined interrupt. +The combined interrupt is ANDed with the Master Interrupt Enable (DEIER Bit 31) to create the master +enabled interrupt. + Only a master enabled interrupt will proceed. +The master enabled interrupt then goes to PCI device 2 configuration registers PCISTS2, PCICMD2, and +MC which control the MSI and line interrupt. + + + +A Function Level Reset (FLR) or Reset Warn will reset all graphics interrupt logic, causing the master +enabled interrupt to de-assert which can cause the MSI or line interrupt to de-assert. + + +3.3.1 Display Engine Interrupt Bit Definition + + Display Engine Interrupt Bit Definition +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Size (in bits): 32 +The DE_IIR and GT_IIR and PM_IIR are ORed together to generate the CPU interrupt. + The Display Engine Interrupt Control Registers all share the same bit definitions from this table. +DWord Bit Description +0 31 Master Interrupt Control + This bit exists only in the DEIER Display Engine Interrupt Enable Register. + This is the master control for the Display to CPU interrupt. This bit must be set to 1 for any interrupts to + propagate to the system. + 30 Error Interrupts Combined + This is an active high level while any of the Error Interrupt bits are set. + 29 GSE + This is an active high pulse on the GSE system level event. + 28 PCH Display interrupt event + This is an active high level while there is an interrupt being generated by the PCH Display. It will stay + asserted until the interrupts in the PCH Display are all cleared. + 27 DisplayPort A Hotplug + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 17 + Display Engine Interrupt Bit Definition + This is an active high level while either of the Digital Port A Hot Plug Interrupt Detect Status register bits + are set. + 26 AUX Channel A + This is an active high pulse on the AUX A done event. + 25 DPST histogram event + This is an active high pulse on the DPST histogram event. + 24 DPST phase in event + This is an active high pulse on the DPST phase in event. + 23:15 Reserved + 14 Sprite Plane Flip Done C + This is an active high pulse when a sprite plane flip is done. + 13 Primary Plane Flip Done C + This is an active high pulse when a primary plane flip is done. + 12 Line Compare Pipe C + This is an active high level for the duration of the selected pipe scan line. + 11 Vsync Pipe C + This is an active high level for the duration of the pipe vertical sync. + 10 Vblank Pipe C + This is an active high level for the duration of the pipe vertical blank. + 9 Sprite Plane Flip Done B + This is an active high pulse when a sprite plane flip is done. + 8 Primary Plane Flip Done B + This is an active high pulse when a primary plane flip is done. + 7 Line Compare Pipe B + This is an active high level for the duration of the selected pipe scan line. + 6 Vsync Pipe B + This is an active high level for the duration of the pipe vertical sync. + 5 Vblank Pipe B + This is an active high level for the duration of the pipe vertical blank. + 4 Sprite Plane Flip Done A + This is an active high pulse when a sprite plane flip is done. + 3 Primary Plane Flip Done A + This is an active high pulse when a primary plane flip is done. + 2 Line Compare Pipe A + This is an active high level for the duration of the selected pipe scan line. + 1 Vsync Pipe A + This is an active high level for the duration of the pipe vertical sync. + 0 Vblank Pipe A + This is an active high level for the duration of the pipe vertical blank. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 18 + 3.3.2 GT Interrupt Bit Definition + + GT Interrupt Bit Definition +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Size (in bits): 32 +The DE_IIR and GT_IIR and PM_IIR are ORed together to generate the CPU interrupt. + The GT Interrupt Control Registers all share the same bit definitions from this table. + DWord Bit Description +0 31 Reserved + 30 Blitter AS Context Switch Interrupt + 29 Blitter page directory faults + 28:27 Reserved + 26 Blitter MI FLUSH DW notify + 25 Blitter Command Streamer error interrupt + 24 Billter MMIO sync flush status + 23 Reserved + 22 Blitter Command Streamer MI USER INTERRUPT + 21 Reserved + 20 Video AS Context Switch Interrupt + 19 Video page directory faults + 18 Video Command Streamer Watchdog counter exceeded + 17 Reserved + 16 Video MI FLUSH DW notify + 15 Video Command Streamer error interrupt + 14 Video MMIO sync flush status + 13 Reserved + 12 Video Command Streamer MI USER INTERRUPT + 11:10 Reserved + 9 Render Monitor Buffer Half Full + 8 Render AS Context Switch Interrupt + 7 Render page directory faults + 6 Render Command Streamer Watchdog counter exceeded + 5 L3 Parity Error + 4 Render PIPE CONTROL notify + 3 Render Command Streamer error interrupt + 2 Render MMIO sync flush status + 0 Render Command Streamer MI USER INTERRUPT + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 19 + 3.3.3 Power Management Interrupt Bit Definition + + Power Management Interrupt Bit Definition +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Size (in bits): 32 +The DE_IIR and GT_IIR and PM_IIR are ORed together to generate the CPU interrupt. + The Power Management Interrupt Control Registers all share the same bit definitions from this table. + DWord Bit Description +0 31:26 Reserved + Format: MBZ + 25 PCU pcode2driver mailbox event + 24 PCU Thermal Event + 23:7 Reserved + Format: MBZ + 6 Render Frequency Downward Timeout During RC6 interrupt + 5 RP UP threshold interrupt + 4 RP DOWN threshold interrupt + 3 Reserved + Format: MBZ + 2 Render geyserville UP evaluation interval interrupt + 1 Render geyserville Down evaluation interval interrupt + 0 Reserved + Format: MBZ + + + +3.3.4 ISR-Interrupt Status + + ISR +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 44000h-44003h +Name: DE Interrupt Status +ShortName: DE_ISR +Address: 44010h-44013h +Name: GT Interrupt Status +ShortName: GT_ISR +Address: 44020h-44023h +Name: PM Interrupt Status + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 20 + ISR +ShortName: PM_ISR +See the interrupt bit definition tables to find the source event for each interrupt bit. +DWord Bit Description +0 31:0 Interrupt Status Bits + This field contains the non-persistent values of all interrupt status bits. The IMR register selects which of + these interrupt conditions are reported in the persistent IIR. + Value Name Description + 0b Condition Doesn't exist Interrupt Condition currently does not exist + 1b Condition Exists Interrupt Condition currently exists + + + Programming Notes + Restriction : Some inputs to this register are short pulses; therefore software should not expect to use + this register to sample these conditions. + + + + +3.4 IMR-Interrupt Mask + IMR +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 44004h-44007h +Name: DE Interrupt Mask +ShortName: DE_IMR +Address: 44014h-44017h +Name: GT Interrupt Mask +ShortName: GT_IMR +Address: 44024h-44027h +Name: PM Interrupt Mask +ShortName: PM_IMR +For GT command streamer interrupts DO NOT use this register to mask interrupt events. Instead use the individual +GT command streamer MASK bits. + For PM interrupts DO NOT use this register to mask interrupt events. Instead use the individual PM MASK bits in the +corresponding PMunit register space. + See the interrupt bit definition tables to find the source event for each interrupt bit. + DWord Bit Description +0 31:0 Interrupt Mask Bits + This field contains a bit mask which selects which interrupt bits from the ISR are reported in the IIR. + Value Name Description + 0b Not Masked Not Masked - will be reported in the IIR + 1b Masked Masked - will not be reported in the IIR + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 21 + 3.4.1 IIR-Interrupt Identity + + IIR +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/WC +Size (in bits): 32 +Address: 44008h-4400Bh +Name: DE Interrupt Identity +ShortName: DE_IIR +Address: 44018h-4401Bh +Name: GT Interrupt Identity +ShortName: GT_IIR +Address: 44028h-4402Bh +Name: PM Interrupt Identity +ShortName: PM_IIR +See the interrupt bit definition tables to find the source event for each interrupt bit. +DWord Bit Description +0 31:0 Interrupt Identity Bits + This field holds the persistent values of the interrupt bits from the ISR which are unmasked by the IMR. + If enabled by the IER, bits set in this register will generate a CPU interrupt. + Bits set in this register will remain set (persist) until the interrupt condition is cleared by writing a '1' to + the appropriate bits. + For each bit, the IIR can store a second pending interrupt if two or more of the same interrupt conditions + occur before the first condition is cleared, and upon clearing the interrupt, the IIR bit will momentarily go + low, then return high to indicate there is another interrupt pending + Value Name Description + 0b Condition Not Interrupt Condition Not Detected + Detected + 1b Condition Detected Interrupt Condition Detected (may or may not have generated a CPU + interrupt) + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 22 + 3.4.2 IER-Interrupt Enable + + IER +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 4400Ch-4400Fh +Name: DE Interrupt Enable +ShortName: DE_IER +Address: 4401Ch-4401Fh +Name: GT Interrupt Enable +ShortName: GT_IER +Address: 4402Ch-4402Fh +Name: PM Interrupt Enable +ShortName: PM_IER +See the interrupt bit definition tables to find the source event for each interrupt bit. +DWord Bit Description +0 31:0 Interrupt Enable Bits + The bits in this register enable a CPU interrupt to be generated whenever the corresponding bit in the + IIR becomes set. + A disabled interrupt will still appear in the IIR register to allow polling of interrupt sources. + The DE_IER master interrupt control bit must be set to 1 for any interrupts to propagate to the system. + Value Name Description + 0b Disable Disable + 1b Enable Enable + + + + +3.4.3 HOTPLUG_CTL-Hot Plug Control + + HOTPLUG_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 44030h-44033h +Name: Hot Plug Control +ShortName: HOTPLUG_CTL +DWord Bit Description +0 31:5 Reserved + 4 DP A HPD Input Enable + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 23 + HOTPLUG_CTL + Controls the state of the hot plug detect buffer for the digital port A. The buffer state is independent of + whether the port is enabled or not. + Value Name Description + 0b Disable [Default] Buffer disabled + 1b Enable Buffer enabled. Hot plugs bit reflect the electrical state of the HPD pin + 3:2 DP A HPD Short Pulse Duration + These bits define the duration of the pulse defined as a short pulse for digital port A. + Value Name Description + 00b 2ms 2 ms + 01b 4.5ms 4.5 ms + 10b 6ms 6 ms + 11b 100ms 100 ms + 1:0 DP A HPD Status + Access: R/WC + This reflects hot plug detect status on the digital port A. This bit is used for either monitor hotplug/unplug + or for notification of a sink event. When either a long or short pulse is detected, one of these bits will set. + These bits are ORed together to go to the main ISR hotplug register bit. These are sticky bits, cleared by + writing 1s to them. + Value Name Description + 00b Not Detected Digital port hot plug event not detected + 1Xb Long Pulse Digital port long pulse hot plug event detected + X1b Short Pulse Digital port short pulse hot plug event detected + + + + +3.4.4 ERR_INT-Error Interrupts + + ERR_INT +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/WC +Size (in bits): 32 +Address: 44040h-44043h +Name: Error Interrupts +ShortName: ERR_INT +These are sticky bits, cleared by writing 1 to them. All the Error Interrupt bits are ORed together to go to the Display +Engine ISR Error Interrupts Combined bit. + DWord Bit Description +0 31 Poison Status + This bit is set upon receiving the poison message. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 30 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 24 + ERR_INT + 29 Invalid GTT page table entry + This bit is set upon receiving the iMPH Invalid GTT page table entry notification. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 28 Invalid page table entry data + This bit is set upon receiving the iMPH Invalid page table entry data notification. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 27:24 Reserved + Format: MBZ + 23 Sprite GTT Fault Status C + This bit is set when a GTT fault is detected for this sprite plane. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 22 Primary GTT Fault Status C + This bit is set when a GTT fault is detected for this primary plane. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 21 Cursor GTT Fault Status C + This bit is set when a GTT fault is detected for this cursor plane. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 20 Sprite GTT Fault Status B + This bit is set when a GTT fault is detected for this sprite plane. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 19 Primary GTT Fault Status B + This bit is set when a GTT fault is detected for this primary plane. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 18 Cursor GTT Fault Status B + This bit is set when a GTT fault is detected for this cursor plane. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 17 Sprite GTT Fault Status A + This bit is set when a GTT fault is detected for this sprite plane. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 16 Primary GTT Fault Status A + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 25 + ERR_INT + This bit is set when a GTT fault is detected for this primary plane. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 15 Cursor GTT Fault Status A + This bit is set when a GTT fault is detected for this cursor plane. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 14:12 Reserved + Format: MBZ + 11:9 Reserved + Format: MBZ + 6 Pipe FIFO Underrun C + This bit is set when the pipe FIFO underrun signal is high. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 3 Pipe FIFO Underrun B + This bit is set when the pipe FIFO underrun signal is high. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + 0 Pipe FIFO Underrun A + This bit is set when the pipe FIFO underrun signal is high. + Value Name Description + 0b Not Detected [Default] Event not detected + 1b Detected Event detected + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 26 + 3.5 Display Engine Render Response + +3.5.1 Display Engine Render Response Message Bit Definition + + Display Engine Render Response Message Bit Definition +Project: +Size (in bits): 32 +Default Value: 0x00000000 +Display Engine (DE) render response message bits come from events within the display engine. The Display Engine +Render Response Message Registers all share the same bit definitions from this table. + DWord Bit Description +0 31:23 Reserved + 22 Pipe C Start of Horizontal Blank Event + This event will be reported on the start of the Pipe C Horizontal Blank. + 21 Pipe C Start of Vertical Blank Event + This event will be reported on the start of the Pipe C Vertical Blank. + 20 Pipe C Sprite Plane Flip Done Event + This event will be reported on the completion of a flip for the Pipe C Sprite Plane. + 19:16 Reserved + 15 Pipe C Primary Plane Flip Done Event + This event will be reported on the completion of a flip for the Pipe C Primary Plane. + 14 Pipe C Scanline Event + This event will be reported on the start of the scan line specified in the Pipe C Display Scan Line + Count Range Compare Register. + 13 Pipe B Start of Horizontal Blank Event + This even will be reported on the start of the Pipe B Horizontal Blank. + 12 Reserved + 11 Pipe B Start of Vertical Blank Event + This even will be reported on the start of the Pipe B Vertical Blank. + 10 Pipe B Sprite Plane Flip Done Event + This even will be reported on the completion of a flip for the Pipe B Sprite Plane. + 9 Pipe B Primary Plane Flip Done Event + This even will be reported on the completion of a flip for the Pipe B Primary Plane. + 8 Pipe B Scanline Event + This even will be reported on the start of the scan line specified in the Pipe B Display Scan Line + Count Range Compare Register. + 7:6 Reserved + 5 Pipe A Start of Horizontal Blank Event + This even will be reported on the start of the Pipe A Horizontal Blank. + 4 Reserved + 3 Pipe A Start of Vertical Blank Event + This even will be reported on the start of the Pipe A Vertical Blank. + 2 Pipe A Sprite Plane Flip Done Event + This even will be reported on the completion of a flip for the Pipe A Sprite Plane. + 1 Pipe A Primary Plane Flip Done Event + This even will be reported on the completion of a flip for the Pipe A Primary Plane. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 27 + Display Engine Render Response Message Bit Definition + 0 Pipe A Scanline Event + This even will be reported on the start of the scan line specified in the Pipe A Display Scan Line + Count Range Compare Register. + + + + +3.5.2 DE_RRMR - Display Engine Render Response Mask + + DE_RRMR +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 44050h-44053h +Name: Render Response Mask +ShortName: DE_RRMR +See the render response message bit definition table to find the source event for each bit. + +This register is used by software to control which render response message bits are masked or unmasked. +Unmasked bits will cause a render response message to be sent and will be reported in that message. +Masked bits will not be reported and will not cause a render response message to be sent. + + Events must be unmasked prior to waiting for them with a MI_WAIT_FOR_EVENT ring command, or in the case of +flips or scanlines, prior to starting the flip or loading the scanline. + + Unmasked events will wake render (command streamer) as they occur, so for improved power savings it is +recommended to only unmask events that are required. + + Programming this register can be done through MMIO or a command streamer LOAD_REGISTER_IMMEDIATE +(LRI) command. + When using LRI care must be taken to follow all the programming rules for LRI targetting the display engine. + Programming Notes +The render response message is sent from the display engine to the render command streamer (CS) or blitter +command streamer (BCS). The message is used to inform CS and BCS of certain display events. + + Vertical and horizontal blank events occur periodically while the associated display pipe timing generator is running +and will be reported in a render response to CS if un-masked here. + +Scanline events occur after they have been initiated through MMIO writes or LOAD_REGISTER_IMMEDIATE to the +Display Load Scan Lines register. A scanline event will be reported in a render response to CS if un-masked here. + + Flip done events occur after they have been initiated through MI_DISPLAY_FLIP or MMIO write to the primary or +sprite plane surface address registers. + A flip event will be reported in a render response to CS if un-masked here and the flip source is CS. + A flip event will be reported in a render response to BCS if un-masked here and the flip source is BCS. +Workaround : Always program MI_MODE 0x209C bit 14 to 1b. +Workaround (WaDisplayFlipAWaitAFlipBWaitB) : Do not cause more than one display event to be reported in a + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 28 + DE_RRMR +single render response. The following restrictions are necessary: + * Do not un-mask more than one blank event at a time. Do not mix un-masked blanks with waits for scanlines or +flips to CS. + * Do not initiate more than one un-masked scanline event at a time. After each scanline load always wait for the +scanline done before changing this mask or initiating a new scanline or CS flip. + * Do not initiate more than one un-masked flip event to CS at a time. After each CS flip always wait for the CS flip +done before changing this mask or initiating a new CS flip or scanline. + * Do not initiate more than one un-masked flip event to BCS at a time. After each BCS flip always wait for the BCS +flip done before changing this mask or initiating a new BCS flip. Flips to BCS can be mixed with flips to CS, blanks, +or scanlines. + DWord Bit Description +0 31:0 DE RRMR + Format: Display Engine Render Response Message Bit Definition + This field contains a bit mask which selects which events cause and are reported in the render + response message. + Value Name Description + 0b Not Masked Not Masked - will cause and be reported in the message + 1b Masked Masked - will not cause or be reported in the message + + + + +3.6 Display Timestamp +This register provides an elapsed real-time value that can be used as a timestamp for GPU events over +short periods of time. +The register counts at a constant frequency by adjusting the increment amount according to the actual +core display clock frequency. SW therefore does not need to know the reference clock frequency. + + +3.6.1 TIMESTAMP_CTR-Time Stamp Counter Value + + TIMESTAMP_CTR +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/WC +Size (in bits): 32 +Address: 44070h-44073h +Name: Time Stamp Counter +ShortName: TIMESTAMP_CTR +DWord Bit Description +0 31:0 TIMESTAMP Counter + This field increments every microsecond. The value in this field is latched in the Pipe Flip TIMESTAMP + registers when flips occur, and in the Pipe Frame TIMESTAMP registers at start of vertical blank. The + register value will reset if any value is written to it. The register is not reset by a graphics software reset. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 29 + 3.7 Display Arbitration Control + +3.7.1 ARB_CTL-Display Arbitration Control 1 + + ARB_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x16661056 +Access: R/W +Size (in bits): 32 +Address: 45000h-45003h +Name: Display Arbitration Control 1 +ShortName: ARB_CTL +DWord Bit Description +0 28:26 HP Queue Watermark + Default Value: 101b 6 + The value in this register indicates the number of entries the high priority queue should have before it + can be read. The value is zero based. + + 25:24 LP Write Request Limit + The value in this register indicates the maximum number of back to back LP write requests that will be + accepted from a single client before re-arbitrating. + Value Name Description + 00b 1 1 + 01b 2 2 + 10b 4 [Default] 4 (default) + 11b 8 8 + 23:20 TLB Request Limit + The value in this register indicates the maximum number of TLB requests that can be made in an + arbitration loop. Zero is not a valid programming. + Value Name + [1,15] + 0110b 6 [Default] + 19:16 TLB Request InFlight Limit + The value in this register indicates the maximum number of TLB (or VTd) requests that can be in flight + at any given time. Zero is not a valid programming. + Value Name + [1,15] + 0110b 6 [Default] + 14:13 Tiled Address Swizzling + DRAM configuration registers show if memory address swizzling is needed. + Value Name Description + 00b No Display No display request address swizzling + 01b Enable Enable display request address bit[6] swizzling for tiled surfaces + 10b Reserved Reserved + 11b Reserved Reserved + 12:8 HP Page Break Limit + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 30 + ARB_CTL + The value in this register represents the maximum number of page breaks allowed in a HP request + chain. Zero is not a valid programming. + Value Name + [1,31] + 10000b 16 [Default] + 7 Reserved + 6:0 HP Data Request Limit + The value in this register represents the maximum number of cachelines allowed in a HP request + chain. Zero is not a valid programming. + Value Name + [1,127] + 1010110b 86 [Default] + + + + +3.7.2 ARB_CTL2-Display Arbitration Control 2 + + ARB_CTL2 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 45004h-45007h +Name: Display Arbitration Control 2 +ShortName: ARB_CTL2 +DWord Bit Description +0 30:9 Reserved + 8 Fetch Timing + The value in this register is valid only when Opportunistic Fetches are enabled. The value in this register + is used to specify when an opportunistic fetch can happen. For any opportunistic fetch to happen, + display should not be in the process of waking the system. + Value Name Description + 0b FE inSR Fetch on falling edge of inSR + 1b Not inSR Fetch when not inSR + 7 Opportunistic Fetch Behavior + The value in this register is valid only when Opportunistic Fetches are enabled. The value in this register + represents the fetch behavior when an opportunistic fetch is triggered. For any opportunistic fetch to + happen, display should not be in the process of waking the system. + Value Name Description + 0b One Burst One Burst Only + 1b Fill FIFO Fill FIFO to Top + 6 Data Buffer Partitioning + Double Buffer Update Start of vertical blank on the low power pipe or not in low power mode or all + Point: pipes disabled + This bit controls the data buffer partitioning when sprite LP states are used. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 31 + ARB_CTL2 + Value Name Description + 0b 1/2 Sprite has 1/2 and primary has 1/2 of the buffer + 1b 5/6 Sprite has 5/6 and primary has 1/6 of the buffer + 5:4 Inflight HP Read Request Limit + The value in this register represents the maximum number of HP read request transactions that can + inflight at any given time. + Value Name Description + 00b 128 HP 128 HP inflight transactions limit + 01b 64 HP 64 HP inflight transactions limit + 10b 32 HP 32 HP inflight transactions limit + 11b 16 HP 16 HP inflight transactions limit + 3:2 Reserved + 1:0 RTID FIFO Watermark + The value in this register represents the watermark value for the RTID FIFO. HP transactions will start + only when the FIFO level is above or equal the watermark + Value Name Description + 00b 8 RTIDs 8 RTIDs available in FIFO + 01b 16 RTIDs 16 RTIDs available in FIFO + 10b 32 RTIDs 32 RTIDs available in FIFO + 11b Reserved Reserved + + + + +3.7.3 MSG_CTL-Display Message Control + + MSG_CTL +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 45010h-45013h +Name: Display Message Control +ShortName: MSG_CTL +DWord Bit Description +0 31:2 Reserved + Format: PBC + 1 Wait for PCH ResetWarn Ack + Set to 1b to make north display wait for south display to acknowledge a Reset Warn. By default north + display will not wait. + Value Name + 0b Do not wait + 1b Wait + + + Programming Notes + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 32 + MSG_CTL + Restriction : BIOS must set this to 1b after the PCH display BDF has been enabled and before enabling + any function in the PCH display. + 0 Wait for PCH FLR Ack + Set to 1b to make north display wait for south display to acknowledge a Function Level Reset. By default + north display will not wait. + Value Name + 0b Do not wait + 1b Wait + + + Programming Notes + Restriction : BIOS must set this to 1b after the PCH display BDF has been enabled and before enabling + any function in the PCH display. + + + + +3.8 Display Watermarks +The watermark registers are used to control the display to memory request timing. The watermarks must +be programmed according to the rules provided in the “Programming Watermarks” document. The default +values of the watermarks should allow the display to operate in any high power mode supported by the +memory configuration. However, the default watermarks are not optimized for power or memory +bandwidth efficiency. +Watermarks must enable from the bottom up, meaning if WM_LP2 is disabled, WM_LP3 must also be +disabled, and if WM_LP1 is disabled, both WM_LP2 and WM_LP3 must also be disabled. Watermark +latency values must increase from the bottom up, meaning WM_LP1 (if enabled) must have higher +latency than WM_PIPE, and so on. +The memory latency values are provided by the MCHBAR PCU 0:0:0 0x5D10 SSKPD config register. + + +3.8.1 WM_PIPE-Pipe Main Watermarks + + WM_PIPE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00783818 +Access: R/W +Size (in bits): 32 +Address: 45100h-45103h +Name: Pipe A Watermarks +ShortName: WM_PIPE_A +Address: 45104h-45107h +Name: Pipe B Watermarks +ShortName: WM_PIPE_B +Address: 45200h-45203h + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 33 + WM_PIPE +Name: Pipe C Watermarks +ShortName: WM_PIPE_C +These are the normal watermark values. +DWord Bit Description +0 31:23 Reserved + 22:16 Pipe Primary Watermark + Default Value: 1111000b + Number in 64Bs of data in FIFO below which the Pipe Primary Plane stream will generate requests to + memory + + 15 Reserved + 14:8 Pipe Sprite Watermark + Default Value: 0111000b + Number in 64Bs of data in FIFO below which the Pipe Sprite Plane stream will generate requests to + memory + + 7:6 Reserved + 5:0 Pipe Cursor Watermark + Default Value: 011000b + Number in 64Bs of data in FIFO below which the Pipe Cursor Plane stream will generate requests to + memory + + + + +3.8.2 WM_LP-Low Power Watermarks +The Low Power (LP) watermark register will be used when only one pipe is enabled, sprite scaling is not +enabled, and the power controller has requested display go into the LP state. + + WM_LP +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 45108h-4510Bh +Name: Low Power 1 Watermarks +ShortName: WM_LP1 +Address: 4510Ch-4510Fh +Name: Low Power 2 Watermarks +ShortName: WM_LP2 +Address: 45110h-45113h +Name: Low Power 3 Watermarks + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 34 + WM_LP +ShortName: WM_LP3 +These are Low Power (LP) watermark values which will be used when display is in a LP state. +DWord Bit Description +0 31 Enabled + Enables this LP watermark. This bit allows the associated LP state to be used. + 30:24 Latency + The latency associated with this LP watermark in half usecs. + 23:20 FBC LP Watermark + Number of equivalent lines of the primary display for this watermark + 19:18 Reserved + 17:8 LP Primary Watermark + Number in 64Bs of data in the display data buffer below which the Primary Plane stream will generate + requests to memory. + 7:0 LP Cursor Watermark + Number in 64Bs of data in the display data buffer below which the Cursor Plane stream will generate + requests to memory. + Programming Notes Project + Workaround (WaDoubleCursorLP3Latency) : The WM_LP3 cursor watermark calculation must + use twice the latency value found in the SSKPD WM3 field. The primary watermark, FBC + watermark, and latency value fields are not affected. + + + + +3.8.3 WM_LP_SPR-Low Power Sprite Watermark +The Low Power Sprite (LP_SPR) watermark register will be used when one pipe is enabled, a sprite is +enabled, sprite scaling is not enabled, and the power controller has requested display go into the LP +state. This will be used together with the associated LP watermarks for FBC, Primary, and Cursor. + + WM_LP_SPR +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 45120h-45123h +Name: Low Power 1 Sprite Watermarks +ShortName: WM_LP1_SPR +Address: 45124h-45127h +Name: Low Power 2 Sprite Watermarks +ShortName: WM_LP2_SPR +Address: 45128h-4512Bh +Name: Low Power 3 Sprite Watermarks +ShortName: WM_LP3_SPR +This is a Low Power Sprite (LP_SPR) watermark value which will be used when display is in a LP state. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 35 + DWord Bit Description +0 31:10 Reserved + 9:0 LP Sprite Watermark + Number in 64Bs of data in the display data buffer below which the Sprite Plane stream will generate + requests to memory. + + + + +3.9 Backlight Control + +3.9.1 BLC_PWM_CTL-Backlight PWM Control + + BLC_PWM_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 48250h-48253h +Name: Backlight PWM Control +ShortName: BLC_PWM_CTL +DWord Bit Description +0 31 PWM Enable + This bit enables the PWM counter logic + Value Name Description + 0b Disable [Default] PWM disabled (drives 0 always) + 1b Enable PWM enabled + 30:29 PWM Pipe assignment + This bit assigns PWM to a pipe. The PWM function must be disabled in order to change the value of + this field. + Value Name Description + 00b Pipe A [Default] Pipe A + 01b Pipe B Pipe B + 10b Pipe C Pipe C + 11b Reserved Reserved + 28:27 Reserved + 26 Phase In Interrupt Status + Access: R/WC + This bit will be set by hardware when a Phase-In interrupt has occurred. Clear this bit by writing a '1', + which will reset the interrupt generation. + Value Name + 0b Interrupt + 1b No interrupt + 25 Phase In Enable + Setting this bit enables a PWM phase in based on the programming of the Phase In registers below. + This bit clears itself when the phase in is completed. + Value Name + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 36 + BLC_PWM_CTL + 0b Disable + 1b Enable + 24 Phase In Interrupt Enable + Setting this bit enables an interrupt to be generated when the PWM phase in is completed. + Value Name + 0b Disable + 1b Enable + 23:16 Phase In time base + This field determines the number of VBLANK events that pass before one increment occurs. + Value Name Description + 00h Invalid [Default] Invalid + 01h-FFh Count VBlank Count + 15:8 Phase In Count + This field determines the number of increment events in this phase in. + Writes to this register should only be done when hardware-phase-ins are disabled. A value of 0 is + invalid. + Reads to this register can be done any time, where the value in this field indicates the number of + increment events remaining to fully apply a phase-in request as hardware automatically decrements + this value. + 7:0 Phase In Increment + This field indicates the amount to adjust the PWM duty cycle register on each increment event. This is + a two's complement number. + + + + +3.9.2 BLC_PWM_DATA-Backlight PWM Data + + BLC_PWM_DATA +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W (DWORD access only, no byte access) +Size (in bits): 32 +Address: 48254h-48257h +Name: Backlight PWM Data +ShortName: BLC_PWM_DATA +DWord Bit Description +0 31:16 Reserved + 15:0 Backlight Duty Cycle + This field determines the number of time base events for the active portion of the PWM backlight + control. This should never be larger than the frequency field. + A value of zero will turn the backlight off. A value equal to the backlight modulation frequency field will + be full on. + This field should be updated when it is desired to change the intensity of the backlight, it will take affect + at the end of the current PWM cycle. + This value represents the active time of the PWM stream in PCH display raw clock periods multiplied + by 128. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 37 + BLC_PWM_DATA + Programming Notes + Restriction : This register must be written only as a full 32 bit dword. Byte or word writes are not + supported. + + + + +3.9.3 BLM_HIST_CTL-Image Enhancement Control + + BLM_HIST_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 48260h-48263h +Name: Image Enhancement Control +ShortName: BLM_HIST_CTL +DWord Bit Description +0 31 IE Histogram Enable + This bit enables the Image Enhancement histogram logic to collect data. + Value Name Description + 0b Disable Image histogram is disabled + [Default] + 1b Enable The image histogram is enabled. When this bit is changed from a zero to a one, + histogram calculations will begin after the next VBLANK of the assigned pipe. + 30:29 IE Pipe + This bit assigns the IE function to a pipe. IE events will be synchronized to the VBLANK of the selected + pipe. The IE function must be disabled in order to change the value of this field. + Value Name Description + 00b Pipe A [Default] Pipe A + 01b Pipe B Pipe B + 10b Pipe C Pipe C + 11b Reserved Reserved + 28 Reserved + 27 IE Modification Table Enable + This bit enables the Image Enhancement modification table. + Value Name Description + 0b Disable Disabled + [Default] + 1b Enable Enabled. When this bit is changed from a zero to a one, modifications begin after + the next VBLANK of the assigned pipe. + 26:25 Reserved + 24 Histogram Mode Select + Value Name Description + 0b YUV [Default] YUV Luma Mode + 1b HSV HSV Intensity Mode + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 38 + BLM_HIST_CTL + 23:16 Sync to Phase In Count + This field indicates the phase in count number on which the Image Enhancement table will be loaded if + the Sync to Phase in is enabled. + 15 IE Table Value Format + This field indicates what format is used for the image enhancement table values. + Value Name Description + 0b 1.9 [Default] 1 integer and 9 fractional bits + 1b 2.8 2 integer and 8 fractional bits + 14:13 Enhancement mode + Value Name Description + 00b Direct [Default] Direct look up mode + 01b Additive Additive mode + 10b Multiplicative Multiplicative mode + 11b Reserved Reserved + 12 Sync to Phase In + Setting this bit enables the double buffered registers to be loaded on the phase in count value specified + instead of the next vblank. + 11 Bin Register Function Select + This field indicates what data is being written to or read from the bin data register. + Value Name Description + 0b TC Threshold Count. A read from the bin data register returns that bin's threshold value + [Default] from the most recent vblank load event (guardband threshold trip). Valid range for the + Bin Index is 0 to 31. + 1b IE Image Enhancement Value. Valid range for the Bin Index is 0 to 32 + 10:7 Reserved + 6:0 Bin Register Index + This field indicates the bin number whose data can be accessed through the bin data register. This + value is automatically incremented by a read or a write to the bin data register if the busy bit is not set. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 39 + 3.9.4 BLM_HIST_BIN-Image Enhancement Bin Data + + BLM_HIST_BIN +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Image Enhancement: Next vblank if in normal mode, or on phase in Sync event frame if it +Point: is enabled +Address: 48264h-48267h +Name: Image Enhancement Bin Data +ShortName: BLM_HIST_BIN +Access to this address are steered to the correct register by programming the Bin Register Function Select and the +Bin Register Index. +DWord Bit Description +0 31 Busy Bit + If (BLM_HIST_CTL:Bin Register Function Select = Threshold Count) {This is a read only bit. If set, the + engine is busy and the rest of the register is undefined. If clear, the register contains valid data.} + Else (Image Enhancement){This bit is reserved.} + 30:22 Reserved + 21:0 Bin Count or Correction Factor + If (BLM_HIST_CTL:Bin Register Function Select = Threshold Count){Bits 21:0 are read only bits. They + indicate the total number of pixels in this bin, value is updated when guardband interrupt delay is met.} + Else (Image Enhancement){Bits 21:10 are reserved. Bits 9:0 are read/write. The program the + correction value for this bin. Writes to this register are double buffered on the next vblank if in normal + mode, or on the phase in Sync event frame if it is enabled. The value written here is the 10bit corrected + channel value for the lowest point of the bin. The correction value is taken as a positive number.} + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 40 + 3.9.5 BLM_HIST_GUARD-Histogram Threshold Guardband + + BLM_HIST_GUARD +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Address: 48268h-4826Bh +Name: Histogram Threshold Guardband +ShortName: BLM_HIST_GUARD +DWord Bit Description +0 31 Histogram Interrupt enable + Value Name Description + 0b Disable Disabled + [Default] + 1b Enable This generates a histogram interrupt once a Histogram event occurs. Software + must always program 1. + 30 Histogram Event status + Access: R/WC + When a Histogram event has occurred, this will get set by the hardware. For any more Histogram + events to occur, the software needs to clear this bit by writing a '1'. The default state for this bit is '0' + Value Name Description + 0b Not Occurred [Default] Histogram event has not occurred + 1b Occured Histogram event has occurred + 29:22 Guardband Interrupt Delay + An interrupt is always generated after this many consecutive frames of the guardband threshold being + surpassed. This value is double buffered on start of vblank. A value of 0 is invalid. + 21:0 Threshold Guardband + This value is used to determine the guardband for the threshold interrupt generation. This single value + is used for all the segments. This value is double buffered on start of vblank + + + + +3.10 Color Space Conversion +These registers contain the coefficients of the pipe color space converter. +The high color channel is the most significant bits of the color. The low color channel is the least +significant bits of the color. The medium color channel is the bits between high and low. For example: In +RGB modes Red is in the High channel, Green in Medium, and Blue in Low. In YUV modes, U is in the +High channel, Y in Medium, and V in Low. + +The color space conversion registers are double buffered and are updated on the start of vertical blank +following a write to the CSC Mode register for the respective pipe. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 41 + The matrix equations are as follows: + OutputHigh = (CoefficientRU * InputHigh) + (CoefficientGU * InputMedium) + (CoefficientBU * + InputLow) + OutputMedium = (CoefficientRY * InputHigh) + (CoefficientGY * InputMedium) + (CoefficientBY * + InputLow) + OutputLow = (CoefficientRV * InputHigh) + (CoefficientGV * InputMedium) + (CoefficientBV * + InputLow) + + +Example programming for RGB to YUV is in the following table: + The input is RGB on high, medium, and low channels respectively. + The output is VYU on high, medium, and low channels respectively. + Program CSC_MODE to put gamma before CSC. + Program the CSC Post-Offsets to +1/2, +1/16, and +1/2 for high, medium, and low channels + respectively. + The coefficients and pre and post offsets can be scaled if desired. + Bt.601 Bt.709 + Value Program Value Program + RU 0x1990 0x2D98 + 0.2990 0.21260 + GU 0x0968 0x0B70 + 0.5870 0.71520 + + BU 0x3E98 0x3940 + 0.1140 0.07220 + RV 0xAAC8 0xBEA8 + -0.1687 -0.11460 + GV 0x9A98 0x9C58 + -0.3313 -0.38540 + BV 0x0800 0x0800 + 0.5000 0.50000 + + RY 0x0800 0x0800 + 0.5000 0.50000 + GY 0x9D68 0x9E88 + -0.4187 -0.45420 + BY 0xBA68 0xB5E0 + -0.0813 -0.04580 + + + + +Example programming for YUV to RGB is in the following table: + The input is VYU on high, medium, and low channels respectively. + The output is RGB on high, medium, and low channels respectively. + Program CSC_MODE to put gamma after CSC. + Program the CSC Pre-Offsets to -1/2, -1/16, and -1/2 for high, medium, and low channels + respectively. + The coefficients and pre and post offsets can be scaled if desired. + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 42 + Bt.601 Reverse Bt.709 Reverse + Value Program Value Program + GY 0x7800 0x7800 + 1.000 1.000 + BY 0x0000 0x0000 + 0.000 0.000 + + RY 0x7AF8 0x7C98 + 1.371 1.574 + GU 0x7800 0x7800 + 1.000 1.000 + BU 0x9AC0 0xABF8 + -0.336 -0.187 + RU 0x8B28 0x9EF8 + -0.698 -0.468 + + GV 0x7800 0x7800 + 1.000 1.000 + BV 0x7DD8 0x7ED8 + 1.732 1.855 + RV 0x0000 0x0000 + 0.000 0.000 + + + + +The pipe gamma and color space conversion blocks can be placed in three different arrangements: + +  Gamma before CSC, selected through the CSC Mode register. This is mostly used for RGB to YUV + conversion. +  Gamma after CSC, selected through the CSC Mode register. This is mostly used for YUV to RGB + conversion or linear RGB to RGB conversion. This mode can be used with pipe color gamut + enhancement. +  Split gamma, selected through the Pipe Config register. This is mostly used for RGB to RGB + conversion. This mode can be used with pipe color gamut enhancement. In this mode, the pipe + gamma enable per plane will control whether a plane will go through both gamma blocks. It is not + possible to send a plane through one gamma block and not the other. + + + +In either arrangement, the final output of the pipe gamma and CSC and gamut enhancement logic is +clamped to fit in the 0 to 1.0 range before going to the ports. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 43 + Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 44 + 3.10.1 CSC_COEFF-CSC Coefficients + + CSC COEFFICIENT FORMAT +Project: +Size (in bits): 16 +Default Value: 0x00000000 +Coefficients for the CSC are stored in sign-exponent-mantissa format. Two CSC coefficients are stored in each +dword, the table below show the data packing in each dword. + DWord Bit Description +0 15 Sign + Value Name Description + 0b Positive Positive + 1b Negative Negative + 14:12 Exponent bits + Represented as 2^(-n) + Value Name Description + 110b 4 4 or mantissa is bb.bbbbbbb + 111b 2 2 or mantissa is b.bbbbbbbb + 000b 1 1 or mantissa is 0.bbbbbbbbb + 001b 0.5 0.5 or mantissa is 0.0bbbbbbbbb + 010b 0.25 0.25 or mantissa is 0.00bbbbbbbbb + 011b 0.125 0.125 or mantissa is 0.000bbbbbbbbb + Others Reserved Reserved + 11:3 Mantissa + 2:0 Reserved + + + + + CSC_COEFF +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 6x32 +Double Buffer Update Point: Start of vertical blank after armed +Double Buffer Armed By: Write to CSC_MODE +Address: 49010h-49027h +Name: CSC A Coefficients +ShortName: CSC_COEFF_[1-6]_A +Address: 49110h-49127h +Name: CSC B Coefficients +ShortName: CSC_COEFF_[1-6]_B +Address: 49210h-49227h +Name: CSC C Coefficients + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 45 + CSC_COEFF +ShortName: CSC_COEFF_[1-6]_C + DWord Bit Description +0 31:16 RY + Format: CSC COEFFICIENT FORMAT + 15:0 GY + Format: CSC COEFFICIENT FORMAT +1 31:16 BY + Format: CSC COEFFICIENT FORMAT + 15:0 Reserved + Format: MBZ +2 31:16 RU + Format: CSC COEFFICIENT FORMAT + 15:0 GU + Format: CSC COEFFICIENT FORMAT +3 31:16 BU + Format: CSC COEFFICIENT FORMAT + 15:0 Reserved + Format: MBZ +4 31:16 RV + Format: CSC COEFFICIENT FORMAT + 15:0 GV + Format: CSC COEFFICIENT FORMAT +5 31:16 BV + Format: CSC COEFFICIENT FORMAT + 15:0 Reserved + Format: MBZ + + + + +3.10.2 CSC_MODE-CSC Mode + + CSC_MODE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Address: 49028h-4902Bh +Name: CSC A Mode +ShortName: CSC_MODE_A +Address: 49128h-4912Bh +Name: CSC B Mode +ShortName: CSC_MODE_B + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 46 + CSC_MODE +Address: 49228h-4922Bh +Name: CSC C Mode +ShortName: CSC_MODE_C +Writes to this register arm CSC registers for this pipe +DWord Bit Description +0 31:2 Reserved + 1 CSC Position + Selects the CSC position in the pipe. This is ignored when split gamma mode is selected in the pipe + config register. + Value Name Description + 0b CSC After [Default] CSC is after gamma + 1b CSC Before CSC is before gamma + 0 Reserved + Format: MBZ + + + + +3.10.3 CSC_PREOFF-CSC Pre-Offsets + + CSC_PREOFF +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000, 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 3x32 +Double Buffer Update Point: Start of vertical blank after armed +Double Buffer Armed By: Write to CSC_MODE +Address: 49030h-4903Bh +Name: CSC A Pre-Offsets +ShortName: CSC_PREOFF_[1-3]_A +Address: 49130h-4913Bh +Name: CSC B Pre-Offsets +ShortName: CSC_PREOFF_[1-3]_B +Address: 49230h-4923Bh +Name: CSC C Pre-Offsets +ShortName: CSC_PREOFF_[1-3]_C +The pre-offset is intended to remove an offset from 0 on the Y or RGB channels and to convert UV channels from +excess 0.5 to 2's complement as they enter pipe color space conversion (CSC). +DWord Bit Description +0 31:13 Reserved + Format: MBZ + 12:0 PreCSC High Offset + This 2's complement value is used to give an offset to the high color channel as it enters CSC logic. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 47 + CSC_PREOFF + The value is a 2's complement fraction allowing offsets between -1 and +1 (exclusive). +1 31:13 Reserved + Format: MBZ + 12:0 PreCSC Medium Offset + This 2's complement value is used to give an offset to the medium color channel as it enters CSC logic. + The value is a 2's complement fraction allowing offsets between -1 and +1 (exclusive). +2 31:13 Reserved + Format: MBZ + 12:0 PreCSC Low Offset + This 2's complement value is used to give an offset to the low color channel as it enters CSC logic. The + value is a 2's complement fraction allowing offsets between -1 and +1 (exclusive). + + + + +3.10.4 CSC_POSTOFF-CSC Post-Offsets + + CSC_POSTOFF +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000, 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 3x32 +Double Buffer Update Point: Start of vertical blank after armed +Double Buffer Armed By: Write to CSC_MODE +Address: 49040h-4904Bh +Name: CSC A Post-Offsets +ShortName: CSC_POSTOFF_[1-3]_A +Address: 49140h-4914Bh +Name: CSC B Post-Offsets +ShortName: CSC_POSTOFF_[1-3]_B +Address: 49240h-4924Bh +Name: CSC C Post-Offsets +ShortName: CSC_POSTOFF_[1-3]_C +The post-offset is intended to add an offset from 0 on the Y or RGB channels and to convert UV channels from 2's +complement to excess 0.5 as they exit pipe color space conversion (CSC). +DWord Bit Description +0 31:13 Reserved + Format: MBZ + 12:0 PostCSC High Offset + This 2's complement value is used to give an offset to the high color channel as it exits CSC logic. The + value is a 2's complement fraction allowing offsets between -1 and +1 (exclusive). +1 31:13 Reserved + Format: MBZ + 12:0 PostCSC Medium Offset + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 48 + CSC_POSTOFF + This 2's complement value is used to give an offset to the medium color channel as it exits CSC logic. + The value is a 2's complement fraction allowing offsets between -1 and +1 (exclusive). +2 31:13 Reserved + Format: MBZ + 12:0 PostCSC Low Offset + This 2's complement value is used to give an offset to the low color channel as it exits CSC logic. The + value is a 2's complement fraction allowing offsets between -1 and +1 (exclusive). + + + + +3.11 Pipe Palette and Gamma +The display palette provides a means to correct the gamma of an image stored in a frame buffer to match +the gamma of the monitor or presentation device. Additionally, the display palette provide a method for +converting indexed data values to color values for VGA and 8-bpp indexed display modes. The display +palette is located after the plane blender. Using the individual plane gamma enables, the blended pixels +can go through or bypass the palette on a pixel by pixel basis. + +The display palette can be accessed through multiple methods and operate in one of four different +modes. + +8 bit legacy palette/gamma mode: + This provides a palette mode for indexed pixel data formats (VGA and primary plane 8 bpp) and + gamma correction for legacy programming requirements. + All input values are clamped to the 0.0 to 1.0 range before the palette/gamma calculation. It is not + recommended to use legacy palette mode with extended range formats. + For input values greater than or equal to 0 and less than 1.0, the input value is used to directly + lookup the result value from one of the 256 palette/gamma entries. The 256 entries are stored in + the legacy palette with 8 bits per color in a 0.8 format with 0 integer and 8 fractional bits. + The legacy palette is programmable through both MMIO and VGA I/O registers. Through VGA I/O, + the palette can look as though there are only 6 bits per color component, depending on + programming of other VGA I/O registers. + Workaround: Set MMIO GTTMMADDR offsets 0x70064, 0x71064, and 0x72064 bits 6 to 1b prior + to accessing the palette through VGA I/O. Clear the bits when done with palette access. + +10 bit gamma mode: + This provides the highest quality gamma for pixel data formats of 30 bits per pixel or less. + All input values are clamped to the greater than -3.0 and less than 3.0 range before the gamma + calculation. + For input values greater than or equal to 0 and less than 1.0, the input value is used to directly + lookup the result value from one of the first 1024 gamma entries. The first 1024 entries are stored + in the precision palette with 10 bits per color in a 0.10 format with 0 integer and 10 fractional bits. + For input values greater than or equal to 1.0 and less than 3.0, the input value is used to linearly + interpolate between the 1024th and 1025th gamma entries to create the result value. The 1025th + entry is stored in the PAL_EXT_GC_MAX register with 19 bits per color in a 3.16 format with 3 + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 49 + integer and 16 fractional bits (maximum value <4.0 when pipe CSC is enabled and after pipe + gamma, <8.0 otherwise). + For negative input values, gamma is mirrored along the X-axis, giving the same result as positive + input values, except for a negative sign. When gamma input may be negative, the first gamma + point should be programmed to a value of 0.0 in order to have a symmetric mirroring. + + +Split gamma mode: + Split gamma mode is composed of two gamma functions. The first gamma is before pipe color + space conversion (CSC) and the second is after CSC. This split gamma mode permits mapping to + linear gamma, then color space conversion, then mapping to monitor gamma. This provides the + highest quality pipe color space conversion and gamma correction for inputs with non-linear + gamma. + First gamma (before CSC): + All input values are clamped to the greater than -3.0 and less than 3.0 range before the + gamma calculation. + For input values greater than or equal to 0 and less than 1.0, the input value is used to + directly lookup the result value from one of the first 512 gamma entries. The first 512 entries + are stored in the precision palette indexes 0 to 511 with 10 bits per color in a 0.10 format + with 0 integer and 10 fractional bits. + For input values greater than or equal to 1.0 and less than 3.0, the input value is used to + linearly interpolate between the 512th and 513th gamma entries to create the result value. + The 513th entry is stored in the PAL_EXT_GC_MAX register with 19 bits per color in a 3.16 + format with 3 integer and 16 fractional bits (maximum value <4.0). + For negative input values, gamma is mirrored along the X-axis, giving the same result as + positive input values, except for a negative sign. When gamma input may be negative, the + first gamma point should be programmed to a value of 0.0 in order to have a symmetric + mirroring. + Second gamma (after CSC): + All input values are clamped to the 0.0 to 1.0 range before the gamma calculation. + For input values greater than or equal to 0 and less than 1.0, the input value is used to + directly lookup the result value from one of the first 512 gamma entries. The first 512 entries + are stored in the precision palette indexes 512 to 1023 with 10 bits per color in a 0.10 format + with 0 integer and 10 fractional bits. + + +12 bit interpolated gamma mode: + This provides the highest quality gamma for pixel data formats greater than 30 bits per pixel. + The gamma correction curve is represented by specifying a set of gamma entry reference points + spaced equally along the curve for values between -1 and 1. For extended values there is an + extended gamma entry reference point at the maximum alowed input value. + All input values are clamped to the greater than -3.0 and less than 3.0 range before the gamma + calculation. + For input values greater than or equal to 0 and less than 1.0, the input value is used to linearly + interpolate between two adjacent points of the first 513 gamma entries to create the result value. + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 50 + The first 512 entries are stored in the precision palette with 16 bits per color in a 0.16 format with 0 + integer and 16 fractional bits (upper 10 bits in odd indexes, lower 6 bits in even indexes). The + 513th entry is stored in the PAL_GC_MAX register with 17 bits per color in a 1.16 format with 1 + integer and 16 fractional bits. + For input values greater than or equal to 1.0 and less than 3.0, the input value is used to linearly + interpolate between the 513th and 514th gamma entries to create the result value. The 514th entry + is stored in the PAL_EXT_GC_MAX register with 19 bits per color in a 3.16 format with 3 integer + and 16 fractional bits (maximum value <4.0 when pipe CSC is enabled and after pipe gamma, <8.0 + otherwise). + For negative input values, gamma is mirrored along the X-axis, giving the same result as positive + input values, except for a negative sign. When gamma input may be negative, the first gamma + point should be programmed to a value of 0.0 in order to have a symmetric mirroring. + To program the gamma correction entries, calculate the desired gamma curve for inputs from 0 to + 3.0. The curve must be flat or increasing, never decreasing. For inputs of 0 to 1.0, multiply the + input value by 512 to find the gamma entry number, then store the desired gamma result in that + entry. For inputs greater than 1.0 and less than or equal to 3.0, store the result for an input of 3.0 in + the 514th gamma entry. + + + +Note: If any gamma value to be programmed exceeds the maximum allowable value in the associated +gamma register, then the programmed value must be clamped to the maximum allowable value. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 51 + Example Pipe Gamma Correction Curve + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 52 + 3.11.1 PAL_LGC-Legacy Palette + + PAL_LGC +Register MMIO: 0/2/0 +Space: +Project: +Default 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 +Access: R/W (DWORD access only, no byte access) +Address: 4A000h-4A3FFh +Name: Legacy Palette A +ShortName: PAL_LGC_[0-255]_A +Address: 4A800h-4ABFFh +Name: Legacy Palette B + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 53 + PAL_LGC +ShortName: PAL_LGC_[0-255]_B +Address: 4B000h-4B3FFh +Name: Legacy Palette C +ShortName: PAL_LGC_[0-255]_C + DWord Bit Description +0..255 31:24 Reserved + Format: MBZ + 23:16 Red Legacy Palette Entry + Default Value: UUh + Red legacy palette entry value. + + 15:8 Green Legacy Palette Entry + Default Value: UUh + Green legacy palette entry value. + + 7:0 Blue Legacy Palette Entry + Default Value: UUh + Blue legacy palette entry value. + + + + +3.11.2 PAL_PREC_INDEX-Precision Palette Index + + PAL_PREC_INDEX +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 4A400h-4A403h +Name: Precision Palette A Index +ShortName: PAL_PREC_INDEX_A +Address: 4AC00h-4AC03h +Name: Precision Palette B Index +ShortName: PAL_PREC_INDEX_B +Address: 4B400h-4B403h +Name: Precision Palette C Index +ShortName: PAL_PREC_INDEX_C +This index controls access to the array of precision palette data values. +DWord Bit Description +0 31 Precision Palette Format + This field selects the format of the precision palette data. It must be set when reading or writing + precision palette entries for split gamma mode. It must be cleared before programming the legacy + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 54 + PAL_PREC_INDEX + palette. + Value Name Description + 0b Non-split [Default] 10 bpc or 12 bpc gamma format + 1b Split Split gamma format + 30:16 Reserved + Format: MBZ + 15 Index Auto Increment + This field enables the index auto increment. + Value Name Description + 0b No Increment [Default] Do not automatically increment the index value. + 1b Auto Increment Increment the index value with each read or write to the data register. + + + Programming Notes + Restriction : Index auto increment mode should not be used. + 14:10 Reserved + Format: MBZ + 9:0 Index Value + This field indicates the data location to be accessed through the data register. This value can be + automatically incremented by a read or a write to the data register if the index auto increment bit is set. + When automatically incrementing, the current automatically calculated index value can be read here. + When automatically incrementing, the index will roll over to 0 after reaching the end of the allowed + range. + Value Name + [0,1023] + + + + +3.11.3 PAL_PREC_DATA-Precision Palette Data + + PAL_PREC_DATA +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W (DWORD access only, no byte access) +Size (in bits): 32 +Address: 4A404h-4A407h +Name: Precision Palette A Data +ShortName: PAL_PREC_DATA_A +Address: 4AC04h-4AC07h +Name: Precision Palette B Data +ShortName: PAL_PREC_DATA_B +Address: 4B404h-4B407h +Name: Precision Palette C Data +ShortName: PAL_PREC_DATA_C + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 55 + PAL_PREC_DATA +These are the precision palette entries used for the 10 bpc, split, and 12 bpc gamma. The Precision Palette Index +Value indicates the precision palette location to be accessed through this register +DWord Bit Description +0 31:30 Reserved + 29:20 Red Precision Palette Entry + Default Value: UUUUUUUUUUb + For 10 bpc, program with the red 10 bit palette entry fraction value. + For 12 bpc gamma odd indexes, program with the upper 10 bits of the red palette entry fraction + value. + For 12 bpc gamma even indexes, program the MSbs with the lower 6 bits of the red palette entry + fraction value, then program all 0s in the LSbs. + For split gamma indexes 0 to 511, program with the first gamma (before CSC) red 10 bit palette entry + fraction value. + For split gamma indexes 512 to 1023, program with the second gamma (after CSC) red 10 bit palette + entry fraction value. + + 19:10 Green Precision Palette Entry + Default Value: UUUUUUUUUUb + For 10 bpc, program with the green 10 bit palette entry fraction value. + For 12 bpc gamma odd indexes, program with the upper 10 bits of the green palette entry fraction + value. + For 12 bpc gamma even indexes, program the MSbs with the lower 6 bits of the green palette entry + fraction value, then program all 0s in the LSbs. + For split gamma indexes 0 to 511, program with the first gamma (before CSC) green 10 bit palette + entry fraction value. + For split gamma indexes 512 to 1023, program with the second gamma (after CSC) green 10 bit + palette entry fraction value. + + 9:0 Blue Precision Palette Entry + Default Value: UUUUUUUUUUb + For 10 bpc, program with the blue 10 bit palette entry fraction value. + For 12 bpc gamma odd indexes, program with the upper 10 bits of the blue palette entry fraction + value. + For 12 bpc gamma even indexes, program the MSbs with the lower 6 bits of the blue palette entry + fraction value, then program all 0s in the LSbs. + For split gamma indexes 0 to 511, program with the first gamma (before CSC) blue 10 bit palette + entry fraction value. + For split gamma indexes 512 to 1023, program with the second gamma (after CSC) blue 10 bit + palette entry fraction value. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 56 + 3.11.4 PAL_GC_MAX-Gamma Correction Max + + PAL_GC_MAX +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00010000, 0x00010000, 0x00010000 +Access: R/W +Size (in bits): 3x32 +Address: 4A410h-4A41Bh +Name: Gamma Correction A Max +ShortName: PAL_GC_MAX_[1-3]_A +Address: 4AC10h-4AC1Bh +Name: Gamma Correction B Max +ShortName: PAL_GC_MAX_[1-3]_B +Address: 4B410h-4B41Bh +Name: Gamma Correction C Max +ShortName: PAL_GC_MAX_[1-3]_C +DWord Bit Description +0 31:17 Reserved + Format: MBZ + 16:0 Red Max GC Point + Default Value: 10000000000000000b + Format: U1.16 + The 513th entry for the red color channel of the 12 bit interpolated gamma correction. + This value is represented in a 1.16 format with 1 integer and 16 fractional bits. + Programming Notes + Restriction : The value should always be programmed to be less than or equal to 1.0. +1 31:17 Reserved + Format: MBZ + 16:0 Green Max GC Point + Default Value: 10000000000000000b + Format: U1.16 + The 513th entry for the green color channel of the 12 bit interpolated gamma correction. + This value is represented in a 1.16 format with 1 integer and 16 fractional bits. + Programming Notes + Restriction : The value should always be programmed to be less than or equal to 1.0. +2 31:17 Reserved + Format: MBZ + 16:0 Blue Max GC Point + Default Value: 10000000000000000b + Format: U1.16 + The 513th entry for the blue color channel of the 12 bit interpolated gamma correction. + This value is represented in a 1.16 format with 1 integer and 16 fractional bits. + Programming Notes + Restriction : The value should always be programmed to be less than or equal to 1.0. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 57 + 3.11.5 PAL_EXT_GC_MAX-Extended Gamma Correction Max + + PAL_EXT_GC_MAX +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x0007FFFF, 0x0007FFFF, 0x0007FFFF +Access: R/W +Size (in bits): 3x32 +Address: 4A420h-4A42Bh +Name: Extended Gamma Correction A Max +ShortName: PAL_EXT_GC_MAX_[1-3]_A +Address: 4AC20h-4AC2Bh +Name: Extended Gamma Correction B Max +ShortName: PAL_EXT_GC_MAX_[1-3]_B +Address: 4B420h-4B42Bh +Name: Extended Gamma Correction C Max +ShortName: PAL_EXT_GC_MAX_[1-3]_C +DWord Bit Description +0 31:19 Reserved + Format: MBZ + 18:0 Red Ext Max GC Point + Default Value: 1111111111111111111b + Format: U3.16 + The extended point for red color channel gamma correction. + This value is represented in a 3.16 format with 3 integer and 16 fractional bits. + Programming Notes + Restriction : The value should always be programmed to be less than 8.0. + The value must be programmed to be less than 4.0 when pipe color space conversion is enabled and + pipe gamma is placed before pipe color space conversion or split gamma is used. +1 31:19 Reserved + Format: MBZ + 18:0 Green Ext Max GC Point + Default Value: 1111111111111111111b + Format: U3.16 + The extended point for green color channel gamma correction. + This value is represented in a 3.16 format with 3 integer and 16 fractional bits. + Programming Notes + Restriction : The value should always be programmed to be less than 8.0. + The value must be programmed to be less than 4.0 when pipe color space conversion is enabled and + pipe gamma is placed before pipe color space conversion or split gamma is used. +2 31:19 Reserved + Format: MBZ + 18:0 Blue Ext Max GC Point + Default Value: 1111111111111111111b + Format: U3.16 + The extended point for blue color channel gamma correction. + This value is represented in a 3.16 format with 3 integer and 16 fractional bits. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 58 + PAL_EXT_GC_MAX + Programming Notes + Restriction : The value should always be programmed to be less than 8.0. + The value must be programmed to be less than 4.0 when pipe color space conversion is enabled and + pipe gamma is placed before pipe color space conversion or split gamma is used. + + + + +3.12 Pipe Color Gamut Enhancement +Pipe color gamut enhancement is used to enhance display of standard gamut content on wide gamut +displays. It processes the color value from before and after the pipe gamma and color space correction +blocks to create the color gamut enhanced output. The typical usage is to output the pipe gamma and +CSC corrected color for areas of low saturated content and the input (not gamma or CSC corrected) color +for areas of high saturated content. It is not recommended to use color gamut enhancement with wide +gamut inputs. +The pipe Gamma and CSC must be programmed to either the split gamma mode or gamma after CSC +mode when using pipe color gamut enhancement. + + + + +The saturation level of the pipe gamma and CSC input color is detected and used to index into a look up +table (LUT) containing programmable weights. The saturation values are linearly distributed across the +LUT indexes from the lowest index for lowest saturation to the highest index for highest saturation. +The enhanced output color is created by using the weight value to interpolate between the input color and +corrected color. See the following table of weights to amount of input or corrected color used to create the +enhanced output color. + +Weighting of input and corrected colors + Amount of Input Color in Enhanced Amount of Corrected Color in Enhanced + Weight from LUT Output Output +00 0000b (minimum) 0% 100% +... ... ... +00 1000b 25% 75% +... ... ... +01 0000b 50% 50% + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 59 + Amount of Input Color in Enhanced Amount of Corrected Color in Enhanced + Weight from LUT Output Output +... ... ... +01 1000b 75% 25% +... ... ... +10 0000b 100% 0% +(maximum) + +Example weight programming + + CGE CGE CGE CGE CGE + LUT Index Weight Value Weight Value Weight Percent Input Weight Percent Corrected + Decimal Binary Color Color + +0 (lowest 0 00 0000b 0% 100% +saturation) +1 0 00 0000b 0% 100% +2 0 00 0000b 0% 100% +3 0 00 0000b 0% 100% +4 0 00 0000b 0% 100% +5 0 00 0000b 0% 100% +6 1.6 00 0010b 5% 95% +7 3.2 00 0011b 10% 90% +8 4.8 00 0101b 15% 85% +9 6.4 00 0110b 20% 80% +10 8.64 00 1001b 27% 73% +11 12.8 00 1101b 40% 60% +12 19.2 01 0011b 60% 40% +13 25.6 01 1010b 80% 20% +14 28.8 01 1101b 90% 10% +15 32 10 0000b 100% 0% +16 (highest 32 10 0000b 100% 0% +saturation) + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 60 + 3.12.1 CGE_CTRL-Color Gamut Enhancement Control + + CGE_CTRL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Address: 49080h-49083h +Name: Color Gamut Enhancement A Control +ShortName: CGE_CTRL_A +Address: 49180h-49183h +Name: Color Gamut Enhancement B Control +ShortName: CGE_CTRL_B +Address: 49280h-49283h +Name: Color Gamut Enhancement C Control +ShortName: CGE_CTRL_C + DWord Bit Description +0 31 CGE Enable + This bit enables the Color Gamut Enhancement logic. + Value Name Description + 0b Disable [Default] Disable CGE + 1b Enable Enable CGE + 30:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 61 + 3.12.2 CGE_WEIGHT-Color Gamut Enhancement Weight + + CGE_WEIGHT +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 4x32 +Address: 49090h-490A3h +Name: Color Gamut Enhancement A Weights +ShortName: CGE_WEIGHT_[0-4]_A +Address: 49190h-491A3h +Name: Color Gamut Enhancement B Weights +ShortName: CGE_WEIGHT_[0-4]_B +Address: 49290h-492A3h +Name: Color Gamut Enhancement C Weights +ShortName: CGE_WEIGHT_[0-4]_C +These are the weights contained in the lookup up table (LUT) used in pipe color gamut enhancement. + LUT index 0 contains the weight for the least saturated colors, and LUT index 16 contains the weight for the most +saturated colors. + Weight values can range from 00000b (100% of the enhanced output color is from the pipe gamma and CSC output +corrected color) to 100000b (100% of the enhanced output color is from the pipe gamma and CSC input color). + Programming Notes +Restriction : The weight values should only be changed while color gamut enhancement is disabled, otherwise +screen artifacts may show temporarily. + DWord Bit Description +0 31:30 Reserved + Format: MBZ + 29:24 CGE Weight Index 3 + This is the weight value for this color gamut enhancement LUT index. + 23:22 Reserved + Format: MBZ + 21:16 CGE Weight Index 2 + This is the weight value for this color gamut enhancement LUT index. + 15:14 Reserved + Format: MBZ + 13:8 CGE Weight Index 1 + This is the weight value for this color gamut enhancement LUT index. + 7:6 Reserved + Format: MBZ + 5:0 CGE Weight Index 0 + This is the weight value for this color gamut enhancement LUT index. +1 31:30 Reserved + Format: MBZ + 29:24 CGE Weight Index 7 + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 62 + CGE_WEIGHT + This is the weight value for this color gamut enhancement LUT index. + 23:22 Reserved + Format: MBZ + 21:16 CGE Weight Index 6 + This is the weight value for this color gamut enhancement LUT index. + 15:14 Reserved + Format: MBZ + 13:8 CGE Weight Index 5 + This is the weight value for this color gamut enhancement LUT index. + 7:6 Reserved + Format: MBZ + 5:0 CGE Weight Index 4 + This is the weight value for this color gamut enhancement LUT index. +2 31:30 Reserved + Format: MBZ + 29:24 CGE Weight Index 11 + This is the weight value for this color gamut enhancement LUT index. + 23:22 Reserved + Format: MBZ + 21:16 CGE Weight Index 10 + This is the weight value for this color gamut enhancement LUT index. + 15:14 Reserved + Format: MBZ + 13:8 CGE Weight Index 9 + This is the weight value for this color gamut enhancement LUT index. + 7:6 Reserved + Format: MBZ + 5:0 CGE Weight Index 8 + This is the weight value for this color gamut enhancement LUT index. +3 31:30 Reserved + Format: MBZ + 29:24 CGE Weight Index 15 + This is the weight value for this color gamut enhancement LUT index. + 23:22 Reserved + Format: MBZ + 21:16 CGE Weight Index 14 + This is the weight value for this color gamut enhancement LUT index. + 15:14 Reserved + Format: MBZ + 13:8 CGE Weight Index 13 + This is the weight value for this color gamut enhancement LUT index. + 7:6 Reserved + Format: MBZ + 5:0 CGE Weight Index 12 + This is the weight value for this color gamut enhancement LUT index. +4 31:6 Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 63 + CGE_WEIGHT + Format: MBZ + 5:0 CGE Weight Index 16 + This is the weight value for this color gamut enhancement LUT index. + + + + +3.13 Software Flags + SWF +Register MMIO: 0/2/0 +Space: +Project: +Default 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000 +Access: R/W +Size (in 36x32 +bits): +Address: 4F000h-4F08Fh +Name: Software Flags +ShortName: SWF_[0-35] +These registers are used as scratch pad data storage space and have no direct effect on hardware operation. The +use of these registers is defined by the software architecture. + DWord Bit Description +0..35 31:0 Software Flags + + + + +3.14 GTSCRATCH-GT Scratchpad + GTSCRATCH +Register MMIO: 0/2/0 +Space: +Project: +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000 +Access: R/W +Size (in bits): 8x32 +Address: 4F100h-4F11Fh +Name: GT Scratchpad + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 64 + GTSCRATCH +ShortName: GTSCRATCH_[0-7] +These registers are used by hardware and must not be used by software. + DWord Bit Description +0..7 31:0 GT Scratchpad + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 65 + 4. North Display Engine Pipe and Port + Controls +4.1 Pipe Timing + +4.1.1 HTOTAL-Horizontal Total + + HTOTAL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 60000h-60003h +Name: Pipe A Horizontal Total +ShortName: PIPE_HTOTAL_A +Address: 61000h-61003h +Name: Pipe B Horizontal Total +ShortName: PIPE_HTOTAL_B +Address: 62000h-62003h +Name: Pipe C Horizontal Total +ShortName: PIPE_HTOTAL_C +DWord Bit Description +0 31:29 Reserved + Format: MBZ + 28:16 Horizontal Total + This field specifies Horizontal Total size. + This should be equal to the sum of the horizontal active and the horizontal blank sizes. + This field is programmed to the number of pixels desired minus one. + Programming Notes + Restriction : The number of pixels (before the minus one) needs to be a multiple of two when driving + the LVDS port in two channel mode. + Restriction : This register must always be programmed to the same value as the Horizontal Blank End. + 15:12 Reserved + Format: MBZ + 11:0 Horizontal Active + This field specifies Horizontal Active Display size. + The first horizontal active display pixel is considered pixel number 0. + This field is programmed to the number of pixels desired minus one. + Programming Notes + Restriction : The number of pixels (before the minus one) needs to be a multiple of two when driving + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 66 + HTOTAL + the LVDS port in two channel mode. + The minimum horizontal active display size is 64 pixels. + This register must always be programmed to the same value as the Horizontal Blank Start. + + + + +4.1.2 HBLANK-Horizontal Blank + + HBLANK +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 60004h-60007h +Name: Pipe A Horizontal Blank +ShortName: PIPE_HBLANK_A +Address: 61004h-61007h +Name: Pipe B Horizontal Blank +ShortName: PIPE_HBLANK_B +Address: 62004h-62007h +Name: Pipe C Horizontal Blank +ShortName: PIPE_HBLANK_C +DWord Bit Description +0 31:29 Reserved + 28:16 Horizontal Blank End + This field specifies Horizontal Blank End position relative to the horizontal active display start. + Programming Notes + Restriction : The number of pixels within horizontal blank needs to be a multiple of two when driving + the LVDS port in two channel mode. + The minimum horizontal blank size is 32 pixels. + This register must always be programmed to the same value as the Horizontal Total. + 15:13 Reserved + 12:0 Horizontal Blank Start + This field specifies the Horizontal Blank Start position relative to the horizontal active display start. + Programming Notes + Restriction : This register must always be programmed to the same value as the Horizontal Active. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 67 + 4.1.3 HSYNC-Horizontal Sync + + HSYNC +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 60008h-6000Bh +Name: Pipe A Horizontal Sync +ShortName: PIPE_HSYNC_A +Address: 61008h-6100Bh +Name: Pipe B Horizontal Sync +ShortName: PIPE_HSYNC_B +Address: 62008h-6200Bh +Name: Pipe C Horizontal Sync +ShortName: PIPE_HSYNC_C +DWord Bit Description +0 31:29 Reserved + Format: MBZ + 28:16 Horizontal Sync End + This field specifies the Horizontal Sync End position relative to the horizontal active display start. + It is programmed with HorizontalActive+FrontPorch+Sync-1. + Programming Notes + Restriction : The number of pixels within horizontal sync needs to be a multiple of two when driving the + LVDS port in two channel mode. + This value must be greater than the horizontal sync start and less than Horizontal Total. + Restriction : HDMI and DVI with audio are not supported when HSYNC Start is programmed equal to + HBLANK Start. + 15:13 Reserved + Format: MBZ + 12:0 Horizontal Sync Start + This field specifies the Horizontal Sync Start position relative to the horizontal active display start. + It is programmed with HorizontalActive+FrontPorch-1. + Programming Notes + Restriction : The number of pixels from active to horizontal sync needs to be a multiple of two when + driving the LVDS port in two channel mode. + This value must be greater than Horizontal Active. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 68 + 4.1.4 VTOTAL-Vertical Total + + VTOTAL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 6000Ch-6000Fh +Name: Pipe A Vertical Total +ShortName: PIPE_VTOTAL_A +Address: 6100Ch-6100Fh +Name: Pipe B Vertical Total +ShortName: PIPE_VTOTAL_B +Address: 6200Ch-6200Fh +Name: Pipe C Vertical Total +ShortName: PIPE_VTOTAL_C +DWord Bit Description +0 31:29 Reserved + 28:16 Vertical Total + This field specifies Vertical Total size. + This should be equal to the sum of the vertical active and the vertical blank sizes. + For progressive display modes, this field is programmed to the number of lines desired minus one. + For interlaced display modes, this field is programmed with the number of lines desired minus two. + The vertical counter is incremented on the leading edge of the horizontal sync. + For interlaced display, hardware uses this value to calculate the vertical total in each field. + Both even and odd vertical totals are supported. + Programming Notes + Restriction : This register must always be programmed to the same value as the Vertical Blank End. + 15:12 Reserved + 11:0 Vertical Active + This field specifies Vertical Active Display size. + The first vertical active display line is considered pixel number 0. + This field is programmed to the number of lines desired minus one. + For interlaced display, hardware uses this value to calculate the vertical active in each field. + Programming Notes + Restriction : When using the internal panel fitting logic, the minimum vertical active area must be seven + lines. + This register must always be programmed to the same value as the Vertical Blank Start. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 69 + 4.1.5 VBLANK-Vertical Blank + + VBLANK +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 60010h-60013h +Name: Pipe A Vertical Blank +ShortName: PIPE_VBLANK_A +Address: 61010h-61013h +Name: Pipe B Vertical Blank +ShortName: PIPE_VBLANK_B +Address: 62010h-62013h +Name: Pipe C Vertical Blank +ShortName: PIPE_VBLANK_C +DWord Bit Description +0 31:29 Reserved + 28:16 Vertical Blank End + This field specifies Vertical Blank End position relative to the vertical active display start. + For interlaced display, hardware uses this value to calculate the vertical blank end in each field. + Programming Notes + Restriction : This register must always be programmed to the same value as the Vertical Total. + The minimum vertical blank size is 5 lines. + 15:13 Reserved + 12:0 Vertical Blank Start + This field specifies the Vertical Blank Start position relative to the vertical active display start. + For interlaced display, hardware uses this value to calculate the vertical blank start in each field. + Programming Notes + Restriction : This register must always be programmed to the same value as the Vertical Active + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 70 + 4.1.6 VSYNC-Vertical Sync + + VSYNC +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 60014h-60017h +Name: Pipe A Vertical Sync +ShortName: PIPE_VSYNC_A +Address: 61014h-61017h +Name: Pipe B Vertical Sync +ShortName: PIPE_VSYNC_B +Address: 62014h-62017h +Name: Pipe C Vertical Sync +ShortName: PIPE_VSYNC_C +DWord Bit Description +0 31:29 Reserved + 28:16 Vertical Sync End + This field specifies the Vertical Sync End position relative to the vertical active display start. + It is programmed with VerticalActive+FrontPorch+Sync-1. + For interlaced display, hardware uses this value to calculate the vertical sync start in each field. + Programming Notes + Restriction : This value must be greater than the vertical sync start and less than Vertical Total. + 15:13 Reserved + 12:0 Vertical Sync Start + This field specifies the Vertical Sync Start position relative to the vertical active display start. + It is programmed with VerticalActive+FrontPorch-1. + For interlaced display, hardware uses this value to calculate the vertical sync end in each field. + Programming Notes + Restriction : This value must be greater than Vertical Active. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 71 + 4.1.7 SRCSZ-Source Image Size + + SRCSZ +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Address: 6001Ch-6001Fh +Name: Pipe A Source Image Size +ShortName: PIPE_SRCSZ_A +Address: 6101Ch-6101Fh +Name: Pipe B Source Image Size +ShortName: PIPE_SRCSZ_B +Address: 6201Ch-6201Fh +Name: Pipe C Source Image Size +ShortName: PIPE_SRCSZ_C +In VGA display mode, this register is ignored and the VGA size from the VGA registers is used instead. +DWord Bit Description +0 31:28 Reserved + Format: MBZ + 27:16 Horizontal Source Size + This field specifies Horizontal Source Size. This determines the horizontal size of the image created by + the display planes. + This field is programmed to the number of pixels desired minus one. + Programming Notes + Restriction : This register must always be programmed to the same value as the Horizontal Active, + except when panel fitting is enabled. + 15:12 Reserved + Format: MBZ + 11:0 Vertical Source Size + This field specifies Vertical Source Size. This determines the vertical size of the image created by the + display planes. + This field is programmed to the number of lines desired minus one. + For interlaced display, hardware divides this number by 2 and adds any necessary half lines to get the + vertical blank end for each field. + Programming Notes + Restriction : This register must always be programmed to the same value as the Vertical Active, except + when panel fitting is enabled. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 72 + 4.1.8 VSYNCSHIFT-Vertical Sync Shift + + VSYNCSHIFT +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 60028h-6002Bh +Name: Pipe A Vertical Sync Shift +ShortName: PIPE_VSYNCSHIFT_A +Address: 61028h-6102Bh +Name: Pipe B Vertical Sync Shift +ShortName: PIPE_VSYNCSHIFT_B +Address: 62028h-6202Bh +Name: Pipe C Vertical Sync Shift +ShortName: PIPE_VSYNCSHIFT_C +DWord Bit Description +0 31:13 Reserved + 12:0 Second Field VSync Shift + This value specifies the vertical sync alignment for the start of the interlaced second field, expressed in + terms of the absolute pixel number relative to the horizontal active display start. + This value will only be used if the transcoder is in an interlaced mode. + + Typically, the interlaced second field vertical sync should start one pixel after the point halfway + between successive horizontal syncs, so the value of this register should be programmed to: + horizontal sync start - floor[horizontal total / 2] + (use the actual horizontal sync start and horizontal total values and not the minus one values + programmed into the registers) + + This vertical sync shift only occurs during the interlaced second field. In all other cases the vertical + sync start position is aligned with horizontal sync start. + + + + +4.2 Pipe M/N Values +These values are used for the embedded DisplayPort and FDI. +For dynamic switching between multiple refresh rates, both the M1/N1 data and link values and the +M2/N2 link values must be programmed. The PIPE_CONF Refresh Rate Switch setting can be changed +on the fly and then alternate M/N values will be used in the next frame that is output. +Calculation of TU, Data M, and Data N is as follows: +For modes that divide into the link frequency evenly, +Active/TU = Payload/Capacity = Data M/N = dot clock * bytes per pixel / ls_clk * number of lanes +Default value to program TU size is "111111" for TU size of 64. + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 73 + Calculation of Link M and Link N is as follows: + Link M/N = dot clock / ls_clk + Restriction on clocks and number of lanes: + Number of lanes >= INT(dot clock * bytes per pixel / ls_clk) + Pcdclk * number of lanes >= dot clock * bytes per pixel +Please note that in the DisplayPort specifcation, dot clock is referred to as strm_clk. + + +4.2.1 DATAM-Data M Value + + DATAM +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Double Buffer Armed By: Writing the LINKN +Address: 60030h-60033h +Name: Pipe A Data M Value 1 +ShortName: PIPE_DATAM1_A +Address: 60038h-6003Bh +Name: Pipe A Data M Value 2 +ShortName: PIPE_DATAM2_A +Address: 61030h-61033h +Name: Pipe B Data M Value 1 +ShortName: PIPE_DATAM1_B +Address: 61038h-6103Bh +Name: Pipe B Data M Value 2 +ShortName: PIPE_DATAM2_B +Address: 62030h-62033h +Name: Pipe C Data M Value 1 +ShortName: PIPE_DATAM1_C +Address: 62038h-6203Bh +Name: Pipe C Data M Value 2 +ShortName: PIPE_DATAM2_C + DWord Bit Description +0 31 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 74 + DATAM + 30:25 TU Size + This field is the size of the transfer unit, minus one. + 24 Reserved + Format: MBZ + 23:0 Data M value + This field is the m value for internal use of the DDA. + + + + +4.2.2 DATAN-Data N Value + + DATAN +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Double Buffer Armed By: Writing the LINKN +Address: 60034h-60037h +Name: Pipe A Data N Value 1 +ShortName: PIPE_DATAN1_A +Address: 6003Ch-6003Fh +Name: Pipe A Data N Value 2 +ShortName: PIPE_DATAN2_A +Address: 61034h-61037h +Name: Pipe B Data N Value 1 +ShortName: PIPE_DATAN1_B +Address: 6103Ch-6103Fh +Name: Pipe B Data N Value 2 +ShortName: PIPE_DATAN2_B +Address: 62034h-62037h +Name: Pipe C Data N Value 1 +ShortName: PIPE_DATAN1_C +Address: 6203Ch-6203Fh +Name: Pipe C Data N Value 2 +ShortName: PIPE_DATAN2_C + DWord Bit Description +0 31:24 Reserved + Format: MBZ + 23:0 Data N value + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 75 + DATAN + This field is the n value for internal use of the DDA. + + + + +4.2.3 LINKM-Link M Value + + LINKM +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Double Buffer Armed By: Writing the LINKN +Address: 60040h-60043h +Name: Pipe A Link M Value 1 +ShortName: PIPE_LINKM1_A +Address: 60048h-6004Bh +Name: Pipe A Link M Value 2 +ShortName: PIPE_LINKM2_A +Address: 61040h-61043h +Name: Pipe B Link M Value 1 +ShortName: PIPE_LINKM1_B +Address: 61048h-6104Bh +Name: Pipe B Link M Value 2 +ShortName: PIPE_LINKM2_B +Address: 62040h-62043h +Name: Pipe C Link M Value 1 +ShortName: PIPE_LINKM1_C +Address: 62048h-6204Bh +Name: Pipe C Link M Value 2 +ShortName: PIPE_LINKM2_C + DWord Bit Description +0 31:24 Reserved + Format: MBZ + 23:0 Link M value + This field is the m value for external transmission in the Main Stream Attributes. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 76 + 4.2.4 LINKN-Link N Value + + LINKN +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Address: 60044h-60047h +Name: Pipe A Link N Value 1 +ShortName: PIPE_LINKN1_A +Address: 6004Ch-6004Fh +Name: Pipe A Link N Value 2 +ShortName: PIPE_LINKN2_A +Address: 61044h-61047h +Name: Pipe B Link N Value 1 +ShortName: PIPE_LINKN1_B +Address: 6104Ch-6104Fh +Name: Pipe B Link N Value 2 +ShortName: PIPE_LINKN2_B +Address: 62044h-62047h +Name: Pipe C Link N Value 1 +ShortName: PIPE_LINKN1_C +Address: 6204Ch-6204Fh +Name: Pipe C Link N Value 2 +ShortName: PIPE_LINKN2_C +Writes to this register arm M/N registers for this pipe. +DWord Bit Description +0 31:24 Reserved + Format: MBZ + 23:0 Link N value + This field is the n value for external transmission in the Main Stream Attributes and VB-ID. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 77 + 4.3 FDI Transmit + +4.3.1 FDI_TX_CTL-FDI Tx Control + + FDI_TX_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00040000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Depends on Bit +Address: 60100h-60103h +Name: FDI A Tx Control +ShortName: FDI_TX_CTL_A +Address: 61100h-61103h +Name: FDI B Tx Control +ShortName: FDI_TX_CTL_B +Address: 62100h-62103h +Name: FDI C Tx Control +ShortName: FDI_TX_CTL_C +FDI B maximum port width is 4 lanes when FDI C is disabled, 2 lanes when FDI C is enabled. + FDI C maximum port width is 2 lanes. +DWord Bit Description +0 31 FDI Tx Enable + Disabling this port will put it in its lowest power state. + Value Name Description + 0b Disable [Default] Disable the FDI Tx interface + 1b Enable Enable the FDI Tx interface + 30:28 Reserved + Format: MBZ + 27:22 Vswing and Preemp + + These bits are used for setting link voltage swing and pre-emphasis The settings require additional + programming in the DPAFE_DL<0,1>_IREFCAL registers. DPAFE_DL0_IREFCAL is used for FDI A. + DPAFE_DL1_IREFCAL is used for FDI B and FDI C. + + "Non-adjustable" settings use hard-coded voltage swing values. + + "Adjustable" settings allow voltage swing values to be optimized with fine tuning through the + DPAFE_DL<0,1>_IREFCAL registers. + + The voltages listed in the description are nominal at 1V supply and recommended board design and + default DPAFE_BMUFNC de-emphasis settings. + + Certain settings require additional programming in the DPAFE_DL0_IREFCAL and + DPAFE_DL1_IREFCAL registers. + Value Name Description + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 78 + FDI_TX_CTL + 000000b Adjustable 500mV+0dB [Default] + Adjustable + + Design: Non-transition 500mV, Transition 500mV + + Additional programming required: + + DPAFE_DL<0,1>_IREFCAL[16:2]=00010 10111 10111b + + Alternate: Non-transition 400mV, Transition 400mV + + Additional programming required: + + DPAFE_DL<0,1>_IREFCAL[16:2]=00110 00111 00111b + 111010b Adjustable 500mV+6dB + Adjustable + + Design: Non-transition 500mV, Transition 1000mV + + Additional programming required: + + DPAFE_DL<0,1>_IREFCAL[16:2]=00010 10111 10111b + + Alternate: Non-transition 400mV, Transition 800mV + + Additional programming required: + + DPAFE_DL<0,1>_IREFCAL[16:2]=00110 00111 00111b + 111001b 666mV+3.5dB + Non-adjustable + + Design: Non-transition 666mV, Transition 1000mV + + Additional programming required: + + DPAFE_DL<0,1>_IREFCAL[16:2]=00010 10111 10111b + 111000b 1000mV+0dB + Non-adjustable + + Design: Non-transition 1000mV, Transition 1000mV + + Additional programming required: + + DPAFE_DL<0,1>_IREFCAL[16:2]=00010 10111 10111b + Others Reserved + Reserved + 21:19 Port Width Selection + This field selects the number of lanes to be enabled on the link. + Port width change must be done as a part of mode set. The field is locked once port is enabled and + only updates when the port is disabled then re-enabled. + Value Name Description + 000b X1 [Default] x1 Mode + 001b X2 x2 Mode + 010b X3 x3 Mode + 011b X4 x4 Mode + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 79 + FDI_TX_CTL + Others Reserved Reserved + + + Programming Notes + Restriction : FDI B and FDI C share lanes. FDI C maximum port width is 2 lanes. FDI B maximum port + width is 4 lanes when FDI C is disabled, 2 lanes when FDI C is enabled. + 18 Enhanced Framing Enable + This bit selects enhanced framing. The field is locked once port is enabled and only updates when the + port is disabled then re-enabled. + Value Name Description + 0b Disabled Enhanced framing disabled + 1b Enabled [Default] Enhanced framing enabled + 17:15 Reserved + Format: MBZ + 14 FDI PLL enable + This bit enables the FDI PLL. + This bit is ORed with the PLL enable bit from any other FDI Tx Control registers. + Value Name Description + 0b Disable [Default] FDI PLL not enabled through this FDI Tx + 1b Enable FDI PLL enabled + + + Programming Notes + Restriction : Wait for the PLL warmup cycle before enabling the port through bit 31 of this register. + 13:12 Reserved + Format: MBZ + 11 Composite Sync Select + This bit selects between composite Sync and separate Fsync/Lsync on this port. + Value Name Description + 0b Separate [Default] Separate Fsync/Lsync + 1b Composite Composite Sync + + + Programming Notes + Restriction : FDI A can use either separate sync or composite sync. FDI A must use composite sync + when FDI C is enabled. + FDI B can use either separate sync or composite sync. FDI B must use composite sync when FDI C is + enabled. + FDI C can only use composite sync. + It is recommended to always use composite sync, even when just using FDI A or FDI B, so that FDI C + can be enabled later without needing to temporarily disable FDI A and FDI B in order to change them + to composite. + 10 Auto Train Enable + This bit enables auto-training on this port. See the mode set enable sequence for usage. Do not + change this bit while the port is enabled. + Value Name Description + 0b Disable [Default] Disable auto-training + 1b Enable Enable auto-training + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 80 + FDI_TX_CTL + Programming Notes + Workaround : When disabling FDI, clear the FDI Transmitter Auto Train Enable bit in the same write as + the FDI Tx enable is cleared, and clear the FDI Receiver Auto Train Enable bit in the same write as the + FDI Rx enable is cleared. + 9:8 Link training pattern enable + These bits are used for manual link initialization. The link must first be configured prior to sending + training patterns. + Manual link training can not be used when auto-training is enabled. + Value Name Description + 00b Pattern 1 [Default] Pattern 1 enabled + 01b Pattern 2 Pattern 2 enabled + 10b Idle Idle Pattern enabled + 11b Normal Send normal pixels + + + Programming Notes + Restriction : When enabling the port, it must be turned on with pattern 1 enabled. + When retraining a link, the port must be disabled, then re-enabled with pattern 1 enabled. + 6 Reserved + Format: MBZ + 4:2 Reserved + Format: MBZ + 1 Auto Train Done + Access: RO + This bit indicates auto-training completed on this port. + Value Name Description + 0b Not Done [Default] Auto-training is not complete or not started + 1b Done Auto-training is complete + + + +Adjustable Voltage Swing Programming for FDI + + DP_AFE_DL<0,1>_IREFCAL + <11:7> TXVcmSel + Vdiff Single Ended Swing DP_AFE_DL<0,1>_IREFCAL <6:2> TXVrefSel + (Transition Bits) <16:12> TXIRefSel (Both fields set to same value) + +500 mV 2 decimal 23 decimal +400 mV 6 decimal 7 decimal +This is only for use with the FDI_TX_CTL<27:22> Vswing_and_Preemp selections marked as "adjustable". +FDI_TX_CTL<27:22> Vswing_and_Preemp must be set to 000000b or 111010b. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 81 + 4.4 DisplayPort + +4.4.1 DP_CTL-DisplayPort Control + + DP_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000018 +Access: R/W +Size (in bits): 32 +Address: 64000h-64003h +Name: DisplayPort A Control +ShortName: DP_CTL_A +DWord Bit Description +0 31 DisplayPort Enable + Disabling this port will put it in its lowest power state. + Value Name Description + 0b Disable [Default] Disable the DisplayPort interface + 1b Enable Enable the DisplayPort interface + 30:29 Pipe Select + This bit determines from which display pipe the source data will originate. + Value Name Description + 00b Pipe A [Default] Pipe A + 01b Pipe B Pipe B + 10b Pipe C Pipe C + 11b Reserved Reserved + 28 Reserved + Format: MBZ + 27:22 Vswing Emp Set + + These bits are used for setting link voltage swing and emphasis. + + Certain settings require additional programming in the DPAFE_DP_IREFCAL register. + + "Non-adjustable" settings use hard-coded voltage swing values. These are the recommended settings + for general use. + + "Adjustable" settings allow voltage swing values to be optimized with fine tuning through the + DPAFE_DP_IREFCAL register. + + The voltages listed are nominal at 1V supply and recommended board design and default + DPAFE_BMUFNC de-emphasis settings. + + 27 = AFE fullSwingMode + + 26:24 = AFE sel 2:0 + + 23 = AFE dmpen (1 enable de-emphasis, 0 disable de-emphasis) + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 82 + DP_CTL + 22 = AFE dmplv (1 set 6dB de-emphasis, 0 set 3.5dB de-emphasis) + Value Name Description + 100100b 0.4V+0dB + Non-adjustable + + DP spec equivalent: 0.4V + 0dB emphasis + + Design: Non-transition 300mV, Transition 300mV + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=0b + 101010b 0.4V+3.5dB + Non-adjustable + + DP spec equivalent: 0.4V + 3.5dB emphasis + + Design: Non-transition 300mV, Transition 450mV + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=0b + 101111b 0.4V+6dB + Non-adjustable + + DP spec equivalent: 0.4V + 6dB emphasis + + Design: Non-transition 300mV, Transition 600mV + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=0b + 110000b 0.6V+0dB + Non-adjustable + + DP spec equivalent: 0.6V + 0dB emphasis + + Design: Non-transition 450mV, Transition 450mV + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=0b + 110110b 0.6V+3.5dB + Non-adjustable + + DP spec equivalent: 0.6V + 3.5dB emphasis + + Design: Non-transition 450mV, Transition 675mV + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=0b + 111000b 0.8V+0dB + Non-adjustable + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 83 + DP_CTL + + DP spec equivalent: 0.8V + 0dB emphasis + + Design: Non-transition 600mV, Transition 600mV + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=0b + 111110b 0.8V+3.5dB + Non-adjustable + + DP spec equivalent: 0.8V + 3.5dB emphasis + + Design: Non-transition 600mV, Transition 900mV + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=0b + 000000b 0.5V+0dB [Default] + Non-adjustable + + Design: Non-transition 500mV, Transition 500mV + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=1b + + DPAFE_DP_IREFCAL[16:2]=00010 11101 11101b + 000010b 0.5V-3.5dB + Non-adjustable + + Design: Non-transition 500mV, Transition 333mV + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=1b + + DPAFE_DP_IREFCAL[16:2]=00010 11101 11101b + 100000b Adjustable MaxV+0dB + Adjustable: Non-transition maxV, Transition maxV + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=1b + + DPAFE_DP_IREFCAL[16:2]=Adjustable + 100010b Adjustable MaxV-3.5dB + Adjustable: Non-transition maxV, Transition maxV - 3.5dB + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=1b + + DPAFE_DP_IREFCAL[16:2]=Adjustable + 100011b Adjustable MaxV-6dB + Adjustable: Non-transition maxV, Transition maxV - 6dB + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 84 + DP_CTL + + Additional programming required: + + DPAFE_DP_IREFCAL[31]=1b + + DPAFE_DP_IREFCAL[16:2]=Adjustable + Others Reserved + Reserved + 21:19 Port Width Selection + This field selects the number of lanes to be enabled on the DisplayPort link. + Port width change must be done as a part of mode set. + The field is locked once port is enabled and only updates when the port is disabled then re-enabled. + Value Name Description + 000b x1 x1 Mode + 001b x2 x2 Mode + 011b x4 x4 Mode + Others Reserved Reserved + 18 Enhanced Framing Enable + This bit selects enhanced framing. The field is locked once port is enabled and only updates when the + port is disabled then re-enabled. + Value Name Description + 0b Disable [Default] Enhanced framing disabled + 1b Enable Enhanced framing enabled. + 17:16 DP PLL Frequency + This bit selects the DisplayPort PLL frequency. + Value Name Description + 00b 270mhz 270mhz + 01b 162mhz 162mhz. + Others Reserved Reserved + 15 Port reversal + This bit enables lane reversal within the port: lane 0 mapped to lane 3, lane 1 mapped to lane 2. + Port reversal does not affect AUX channel lane mapping. + The field is locked once port is enabled and only updates when the port is disabled then re-enabled. + Value Name Description + 0b Not reversed [Default] Port not reversed + 1b Reversed Port reversed + 14 DisplayPort PLL enable + This bit enables the DisplayPort PLL. + Value Name Description + 0b Disable [Default] PLL not enabled + 1b Enable PLL enabled + + + Programming Notes + Restriction : Wait for the PLL warmup cycle before enabling the port through bit 31 of this register. + 13:10 Reserved + Format: MBZ + 9:8 Link training pattern enable + These bits are used for link initialization as defined in the DisplayPort specification. + The link must first be configured prior to sending training patterns. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 85 + DP_CTL + Value Name Description + 00b Pattern 1 [Default] Pattern 1 enabled + 01b Pattern 2 Pattern 2 enabled + 10b Idle Idle Pattern enabled + 11b Normal Send normal pixels + + + Programming Notes + Restriction : When enabling the port, it must be turned on with pattern 1 enabled. + When retraining a link, the port must be disabled, then re-enabled with pattern 1 enabled. + 6 Alternate SR Enable + This bit enables the embedded DisplayPort Alternate Scrambler Reset. + Value Name Description + 0b Disable [Default] Alternate SR disabled + 1b Enable Alternate SR enabled + 4:3 Sync Polarity + This bit indicates the polarity of Hsync and Vsync to be transmitted in MSA. + Value Name Description + 00b Low VS and HS are active low (inverted) + 01b VS Low, HS High VS is active low (inverted), HS is active high + 10b VS High, HS Low VS is active high, HS is active low (inverted) + 11b High [Default] VS and HS are active high + 2 Digital Display Detected + Access: RO + This bit indicates whether a digital display was detected during initialization. + It signifies the level of the detect pin at boot. This bit is valid regardless of whether the port is enabled. + Value Name Description + 0b Not Detected [Default] Digital display not detected during initialization + 1b Detected Digital display detected during initialization + 1:0 Reserved + Format: MBZ + + + +Adjustable Voltage Swing Programming for Embedded DisplayPort + + DP_AFE_DP_IREFCAL + <11:7> TXVcmSel + <6:2> TXVrefSel + Vdiff Single Ended Swing DP_AFE_DP_IREFCAL (Both fields set to same value) + (Transition Bits) <16:12> TXIRefSel + 500 mV 2 decimal 3 decimal + 475 mV 3 decimal 28 decimal + 450 mV 4 decimal 12 decimal + 425 mV 5 decimal 20 decimal + 400 mV 6 decimal 4 decimal + 375 mV 7 decimal 29 decimal + 350 mV 8 decimal 13 decimal + 325 mV 9 decimal 21 decimal + 300 mV 10 decimal 5 decimal + 275 mV 11 decimal 30 decimal + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 86 + DP_AFE_DP_IREFCAL + <11:7> TXVcmSel + <6:2> TXVrefSel + Vdiff Single Ended Swing DP_AFE_DP_IREFCAL (Both fields set to same value) + (Transition Bits) <16:12> TXIRefSel + 250 mV 12 decimal 14 decimal + 225 mV 13 decimal 22 decimal + 200 mV 14 decimal 5 decimal + 175 mV 15 decimal 31 decimal + 150 mV 16 decimal 15 decimal + 125 mV 17 decimal 23 decimal + 100 mV 18 decimal 7 decimal + This is only for use with the DP_CTL_A <27> Vswing_Emp_Set selections marked as "adjustable". + DPAFE_DP_IREFCAL <31> SwingCtlDis must be set to 1. + DP_CTL_A <27> Vswing_Emp_Set fullSwingMode must be set to 1. + DP_CTL_A <23:22> Vswing_Emp_Set dmpen and dmplv are set to 00b for no de-emphasis, 10b for 3.5dB de- + emphasis, or 11b for 6dB de-emphasis. + + + +4.4.2 DP_AUX_CTL-DisplayPort AUX Channel Control + + DP_AUX_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x000300C8 +Access: R/W Special +Size (in bits): 32 +Address: 64010h-64013h +Name: DisplayPort A AUX Channel Control +ShortName: DP_AUX_CTL_A +DWord Bit Description +0 31 Send Busy + Access: R/W Special + Setting this bit to a one initiates the transaction, when read this bit will be a 1 until the transmission + completes. + The transaction is completed when the response is received or when a timeout occurs. + Do not write a 1 again until transaction completes. + Programming Notes + Restriction : Do not change any fields while Send/Busy bit 31 is asserted. + 30 Done + Access: R/WC + A sticky bit that indicates the transaction has completed. + Write a 1 to this bit to clear the event + Value Name + 0b Not done + 1b Done + 29 Interrupt on Done + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 87 + DP_AUX_CTL + Access: R/W + Enable an interrupt in the hotplug status register when the transaction completes or times out. + Value Name + 0b Enable + 1b Disable + 28 Time out error + Access: R/WC + A sticky bit that indicates the transaction has timed out. + Write a 1 to this bit to clear the event. + + 27:26 Time out timer value + Access: R/W + Used to determine how long to wait for receiver response before timing out. + Value Name Description + 00b 400us [Default] 400us + 01b 600us 600us + 10b 800us 800us + 11b 1600us 1600us + 25 Receive error + Access: R/WC + A sticky bit that indicates that the data received was corrupted, not in multiples of a full byte, or more + than 20 bytes. + Write a 1 to this bit to clear the event. + Value Name + 0b Error [Default] + 1b Not Error + 24:20 Message Size + This field is used to indicate the total number bytes to transmit (including the header). It also indicates + the number of bytes received in a transaction (including the header). + Reads of this field are valid only when the done bit is set and timeout or receive error has not + occurred. + Sync/Stop are not part of the message or the message size. + Reads of this field will give the response message size. + The read value will not be valid while Send/Busy bit 31 is asserted. + Message sizes of 0 or >20 are not allowed. + 19:16 Precharge Time + Default Value: 0011b 6us + Access: R/W + Used to determine the precharge time for the Aux Channel drivers. During this time the Aux Channel + will drive the SYNC pattern. Every microsecond gives one additional SYNC pulse beyond the hard + coded 26 SYNC pulses. + The value is the number of microseconds times 2. + Default is 3 decimal which gives 6us of precharge which is 6 extra SYNC pulses for a total of 32. + + 10:0 2X Bit Clock divider + Default Value: 00 1100 1000b 200 + Used to determine the 2X bit clock the Aux Channel logic runs on. + This value divides the input clock frequency down to 2X bit clock rate. It should be programmed to get + as close as possible to the ideal rate of 2MHz. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 88 + DP_AUX_CTL + Default is 200 decimal which divides the 400MHz input clock to become 2MHz bit clock. + + + + +4.4.3 DP_AUX_DATA-DisplayPort AUX Channel Data + + DP Aux Channel Data Format +Project: +Default Value: 0x00000000 +DWord Bit Description +0 31:0 AUX CH DATA + A DWord of the message. Writes give the data to transmit during the transaction. The MSbyte is + transmitted first. Reads will give the response data after transaction complete. + + + + + DP_AUX_DATA +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 5x32 +Address: 64014h-64027h +Name: DisplayPort A AUX Channel Data +ShortName: DP_AUX_DATA_[1-5]_A +The read value will not be valid while the DisplayPort Aux Channel Control Register Send/Busy bit is asserted. + DWord Bit Description +0 31:0 AUX CH DATA1 + Format: DP Aux Channel Data Format +1 31:0 AUX CH DATA2 + Format: DP Aux Channel Data Format +2 31:0 AUX CH DATA3 + Format: DP Aux Channel Data Format +3 31:0 AUX CH DATA4 + Format: DP Aux Channel Data Format +4 31:0 AUX CH DATA5 + Format: DP Aux Channel Data Format + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 89 + 4.5 Panel Fitter + +4.5.1 PF_PWR_GATE-Panel Fitter Power Gate Control + + PF_PWR_GATE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank after armed +Double Buffer Armed By: Write to PF_WIN_SZ +Address: 68060h-68063h +Name: PF 0 Power Gate Control +ShortName: PF_PWR_GATE_0 +Address: 68860h-68863h +Name: PF 1 Power Gate Control +ShortName: PF_PWR_GATE_1 +Address: 69060h-69063h +Name: PF 2 Power Gate Control +ShortName: PF_PWR_GATE_2 + DWord Bit Description +0 31:5 Reserved + Format: MBZ + 4:3 Settling Time + Time for RAMs in a given filter group to settle after they are powered up. + Value Name Description + 00b 32 cdclks 80ns + 01b 64 cdclks 160ns + 10b 96 cdclks 240ns + 11b 128 cdcclks 320ns + 2 Reserved + Format: MBZ + 1:0 SLPEN Delay + Delay between sleep enables of individual banks of RAMs. + Value Name Description + 00b 8 cdclks 20ns + 01b 16 cdclks 40ns + 10b 24 cdclks 60ns + 11b 32 cdclks 80ns + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 90 + 4.5.2 PF_WIN_POS-Panel Fitter Window Position + + PF_WIN_POS +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank after armed +Double Buffer Armed By: Write to PF_WIN_SZ +Address: 68070h-68073h +Name: PF 0 Window Position +ShortName: PF_WIN_POS_0 +Address: 68870h-68873h +Name: PF 1 Window Position +ShortName: PF_WIN_POS_1 +Address: 69070h-69073h +Name: PF 2 Window Position +ShortName: PF_WIN_POS_2 +DWord Bit Description +0 31:29 Reserved + Format: MBZ + 28:16 XPOS + The X coordinate in pixels of the upper left most pixel of the panel fitted display window. + Programming Notes + Restriction : The X position must not be programmed to be 1 (28:16=0 0000 0000 0001b). + 15:12 Reserved + Format: MBZ + 11:0 YPOS + The Y coordinate in lines of the upper left most pixel of the panel fitter display window. + Programming Notes + Restriction : LSB must be zero for interlaced modes. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 91 + 4.5.3 PF_WIN_SZ-Panel Fitter Window Size + + PF_WIN_SZ +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Address: 68074h-68077h +Name: PF 0 Window Size +ShortName: PF_WIN_SZ_0 +Address: 68874h-68877h +Name: PF 1 Window Size +ShortName: PF_WIN_SZ_1 +Address: 69074h-69077h +Name: PF 2 Window Size +ShortName: PF_WIN_SZ_2 +Coordinates are determined with a value of (0,0) being the upper left corner of the display device (rotation does not +affect this). +Writes to this register arm PF registers on this pipe. + DWord Bit Description +0 31:29 Reserved + Format: MBZ + 28:16 XSIZE + The horizontal size in pixels of the desired panel fitted window. + 15:12 Reserved + Format: MBZ + 11:0 YSIZE + The vertical size in pixels of the desired panel fitted window. + Programming Notes + Restriction : LSB must be zero for interlaced modes. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 92 + 4.5.4 PF_CTRL-Panel Fitter Control + + PF_CTRL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank after armed +Double Buffer Armed By: Write to PF_WIN_SZ +Address: 68080h-68083h +Name: PF 0 Control +ShortName: PF_CTRL_0 +Address: 68880h-68883h +Name: PF 1 Control +ShortName: PF_CTRL_1 +Address: 69080h-69083h +Name: PF 2 Control +ShortName: PF_CTRL_2 +There are three panel fitters: +Panel fitter 0 is always 7x5 filter capable. +Panel fitter 1 is always 3x3 filter capable. +Panel fitter 2 is always 3x3 filter capable. + + The 3x3 capable filter can support pipe horizontal source sizes less than or equal to 2048 pixels. It must not be +enabled when the pipe horizontal source size is greater than 2048 pixels. + + The 7x5 capable filter can support pipe horizontal source sizes of less than or equal to 4096 pixels. When the pipe +horizontal source size is greater than 2048 pixels, or the hard-coded 3x3 filter coefficients are selected, the filter will +automatically switch to a 3x3 filter mode. It must not be enabled when the pipe horizontal source size is greater than +4096 pixels. + + When using panel fitter down scaling (pipe source size is larger than panel fitter window size) the maximum +supported pixel rate will be reduced by the down scale amount and the watermark for planes on the same pipe has +to increase by the down scale amount. + Programming Notes +Restriction : The 3x3 capable filter must not be enabled when the pipe horizontal source size is greater than 2048 +pixels. + The 7x5 capable filter must not be enabled when the pipe horizontal source size is greater than 4096 pixels. + + Down scaling is only supported up to 1.125 (pipe source size / panel fitter window size) in each direction. + DWord Bit Description +0 31 Enable Pipe Scaler + Value Name Description + 0b Disable [Default] Data bypasses the scaler + 1b Enable The scaler is enabled + 30:29 Pipe Select + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 93 + PF_CTRL + This bit determines which display pipe this panel fitter will connect to. Do not enable and connect + more than one panel fitter to a pipe. + Value Name Description + 00b Pipe A [Default] Pipe A + 01b Pipe B Pipe B + 10b Pipe C Pipe C + 11b Reserved Reserved + 24:23 FILTER SELECT + Selects filter coefficients. + Value Name Description + 00b Programmed Programmed Coefficients (Recommended for 7x5 capable panel fitters, + not available for 3x3 capable panel fitters + 01b Hardcoded Med Hardcoded Coefficients for Medium 3x3 Filtering + 10b Hardcoded Edge Hardcoded Coefficients for Edge Enhancing 3x3 Filtering + Enhance + 11b Hardcoded Edge Hardcoded Coefficients for Edge Softening 3x3 Filtering + Soften + + + Programming Notes + Restriction : Programmed coefficients only work with 7x5 capable panel fitters. + For panel fitters that are only 3x3 capable, this field must be programmed to select one of the + hardcoded coefficient sets. + 22 Reserved + Format: MBZ + 16:0 Reserved + Format: MBZ + + + + +4.5.5 PF_COEF_INDEX-Panel Fitter Coefficients Index +Horizontal coefficients are accessed through the index and data registers following the mapping shown +below. 17 phase of 7 taps requires 119 coefficients in 60 dwords per set. The letter represents the filter +tap (D is the center tap) and the number represents the coefficient set for a phase (0-16). +Horizontal Luma/Red Coefficient Mapping Horizontal Chroma/Green/Blue Coefficient Mapping + + Index Data Value Data Value Index Data Value Data Value + Value Coefficient2 Coefficient1 Value Coefficient2 Coefficient1 + +00h B0 A0 3Ch B0 A0 +01h D0 C0 3Dh D0 C0 +02h F0 E0 3Eh F0 E0 +03h A1 G0 3Fh A1 G0 +04h C1 B1 40h C1 B1 +... ... ... ... ... ... +38h B16 A16 74h B16 A16 +39h D16 C16 75h D16 C16 +3Ah F16 E16 76h F16 E16 +3Bh Reserved G16 77h Reserved G16 + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 94 + Vertical coefficients are accessed through the index and data registers following the mapping shown +below. 17 phase of 5 taps requires 85 coefficients in 43 dwords per set. The letter represents the filter tap +(C is the center tap) and the number represents the coefficient set for a phase (0-16). +Vertical Luma/Red Coefficient Mapping Vertical Chroma/Green/Blue Coefficient Mapping + + Index Data Value Data Value Index Data Value Data Value + Value Coefficient2 Coefficient1 Value Coefficient2 Coefficient1 + +00h B0 A0 2Bh B0 A0 +01h D0 C0 2Ch D0 C0 +02h A1 E0 2Dh A1 E0 +03h C1 B1 2Eh C1 B1 +... ... ... ... ... ... +27h B16 A16 53h B16 A16 +28h D16 C16 54h D16 C16 +2Ah Reserved E16 55h Reserved E16 + + + PF_COEF_INDEX +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 680A0h-680A3h +Name: PF 0 Horizontal Coefficients Index +ShortName: PF_HCOEF_INDEX_0 +Address: 680B0h-680B3h +Name: PF 0 Vertical Coefficients Index +ShortName: PF_VCOEF_INDEX_0 +This index controls access to the array of panel fitter coefficient data values. See the coefficient mapping tables for +information on mapping of index to data values for each set of coefficients. +DWord Bit Description +0 31:16 Reserved + Format: MBZ + 15 Index Auto Increment + This field enables the index auto increment. + Value Name Description + 0b No Increment [Default] Do not automatically increment the index value. + 1b Auto Increment Increment the index value with each read or write to the data register. + 14:7 Reserved + Format: MBZ + 6:0 Index Value + This field indicates the data location to be accessed through the data register. This value can be + automatically incremented by a read or a write to the data register if the index auto increment bit is set. + When automatically incrementing, the current automatically calculated index value can be read here. + When automatically incrementing, the index will roll over to 0 after reaching the end of the allowed + range. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 95 + 4.5.6 PF_COEF_DATA-Panel Fitter Coefficients Data + + Panel Fitter Coefficient Format +Project: +Default Value: 0x00000000 +DWord Bit Description +0 15 Sign + Value Name Description + 0b Positive Positive + 1b Negative Negative + 14 Reserved + Format: MBZ + 13:12 Exponent + The meaning of the exponent bits varies for center tap or non-center tap coefficients. + Value Name Description + 00b 2 or 0.125 Center taps: 2 or mantissa is b.bbbbbbbb + Non-center taps: 0.125 or mantissa is 0.000bbbbbbb + 01b 1 1 or mantissa is 0.bbbbbbb.. + 10b 0.5 0.5 or mantissa is 0.0bbbbbbb.. + 11b 0.25 0.25 or mantissa is 0.00bbbbbbb.. + Others Reserved Reserved + 11:3 Mantissa + Size of the mantissa varies based on the filter, but the MSB of the mantissa is always bit 11. + Center tap coefficients use all 9 bits of mantissa. + Non-center tap coefficients use only the upper 7 bits of mantissa and the lower 2 bits are ignored. + 2:0 Reserved + Format: MBZ + + + + + PF_COEF_DATA +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W (DWORD access only, no byte access) +Size (in bits): 32 +Address: 680A4h-680A7h +Name: PF 0 Horizontal Coefficients Data +ShortName: PF_HCOEF_DATA_0 +Address: 680B4h-680B7h +Name: PF 0 Vertical Coefficients Data +ShortName: PF_VCOEF_DATA_0 +These are the coefficient values for panel fitter. + The Panel Fitter Coefficients Index Value indicates the Panel Fitter Coefficients location to be accessed through this +register. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 96 + PF_COEF_DATA + Only 7x5 capable panel fitters can use programmed coefficients. + DWord Bit Description +0 31:16 Coefficient2 + Format: Panel Fitter Coefficient Format + Specifies the value for the second coefficient stored in this dword. + + 15:0 Coefficient1 + Format: Panel Fitter Coefficient Format + Specifies the value for the first coefficient stored in this dword. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 97 + 5. North Display Engine Pipe and Plane + Controls +5.1 Pipe Control + +5.1.1 PIPE_SCANLINE-Pipe Scan Line + + PIPE_SCANLINE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 70000h-70003h +Name: Pipe A Scan Line +ShortName: PIPE_SCANLINE_A +Address: 71000h-71003h +Name: Pipe B Scan Line +ShortName: PIPE_SCANLINE_B +Address: 72000h-72003h +Name: Pipe C Scan Line +ShortName: PIPE_SCANLINE_C +This register provides the read back of the display pipe vertical line counter. + The value increments at the leading edge of HSYNC and can be safely read any time. + The value resets to line zero at the first active line of the display. + In interlaced display timings, the scan line counter provides the current line in the field. One field can have a total +number of lines that is one greater than the other field. + DWord Bit Description +0 31 Current Field + Provides read back of the current field being displayed on the display pipe. + Value Name Description + 0b Odd [Default] First field (odd field) + 1b Even Second field (even field) + 30:13 Reserved + 12:0 Line Counter for Display + Provides read back of the display pipe vertical line counter. This is an indication of the current + display scan line. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 98 + 5.1.2 PIPE_SCANLINECOMP-Pipe Scan Line Compare + + PIPE_SCANLINECOMP +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 70004h-70007h +Name: Pipe A Scan Line Range Compare +ShortName: PIPE_SCANLINECOMP_A +Address: 71004h-71007h +Name: Pipe B Scan Line Range Compare +ShortName: PIPE_SCANLINECOMP_B +Address: 72004h-72007h +Name: Pipe C Scan Line Range Compare +ShortName: PIPE_SCANLINECOMP_C + Description Project +The scan line number register is compared with the display line value from the pipe timing generator. + The result of this comparison is used to generate interrupts and render responses. + The value programmed should be desired value - 1, so for line 0, the value programmed is VTOTAL, and for +line 1, the value programmed is 0. + In interlaced display timings, the scan line is per field. One field can have a total number of lines that is one +greater than the other field. +Reserved. Scan line compare is now done through DE_LOAD_SL (pipe A 0x70068, pipe B 0x71068, pipe C +0x72068). + DWord Bit Description +0 31:13 Reserved + Format: MBZ + 12:0 Reserved + Project: + 12:0 Scan Line Number + + + + + Range: 0..Vertical Total + This field specifies the scan line number on which to generate scan line interrupt and render + response. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 99 + 5.1.3 PIPE_CONF-Pipe Configuration + + PIPE_CONF +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank OR pipe disabled +Address: 70008h-7000Bh +Name: Pipe A Config +ShortName: PIPE_CONF_A +Address: 71008h-7100Bh +Name: Pipe B Config +ShortName: PIPE_CONF_B +Address: 72008h-7200Bh +Name: Pipe C Config +ShortName: PIPE_CONF_C +DWord Bit Description +0 31 Pipe Enable + Setting this bit to the value of one, turns on this pipe. + Turning the pipe off disables the timing generator and synchronization pulses to the display will not be + maintained. + Pipe timing registers must contain valid values before this bit is enabled. + Value Name Description + 0b Disable [Default] Disable + 1b Enable Enable + 30 Pipe State + This read only bit indicates the actual state of the pipe. + Value Name Description + 0b Disabled [Default] Pipe is disabled + 1b Enabled Pipe is enabled + 29 Reserved + 26 Reserved + 25:24 Pipe Palette Gamma Mode + These bits select which mode the pipe gamma correction logic works in. + See the Display Palette Registers section for information on the different palette/gamma modes. + Other gamma units such as in the sprite are unaffected by this bit. + Value Name Description + 00b 8 bit [Default] 8-bit Legacy Palette Mode + 01b 10 bt 10-bit Precision Palette Mode + 10b 12 bit 12-bit Interpolated Gamma Mode + 11b Split Split Gamma Mode (separate pipe gamma functions before and after pipe CSC) + 23:21 Interlaced Mode + These bits are used for software control of the pipe interlaced mode. + Value Name Description + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 100 + PIPE_CONF + 000b PF-PD Progressive Fetch with Progressive Display. + [Default] + 001b PF-ID Progressive Fetch with Interlaced Display. Requires 7x5 capable panel fitter to + be enabled and in 7x5 mode + 011b IF-ID Interlaced Fetch with Interlaced Display + Others Reserved Reserved + + + Programming Notes + Restriction : VGA display modes do not work while in interlaced fetch modes. + 20 Display Power Mode Switch + This bit selects the the software controlled progressive-to-progressive power saving mode (software + controlled DRRS). + Link and data M/N 1 values are used for normal settings, M/N 2 values for low power settings. + Pixel clock FP0 values are used for normal settings, FP1 values for low power settings. + Value Name Description + 0b Normal [Default] Normal progressive refresh rate + 1b Low Power Low power progressive refresh rate + + + Programming Notes + Workaround : If this pipe is connected to a port on the PCH and this power savings mode will be used, + then before the pipe and transcoder are enabled, the frame start delay in the pipe and transcoder must + be set to 11b. When these conditions are no longer true, the frame start delay must be returned to the + previous value after the pipe and transcoder are disabled. + Frame start delay register locations: + Pipe A frame start delay 0x70008 bits 28:27 + Pipe B frame start delay 0x71008 bits 28:27 + Pipe C frame start delay 0x72008 bits 28:27 + Cougarpoint/Pantherpoint transcoder A frame start delay 0xF0064 bits 28:27 + Cougarpoint/Pantherpoint transcoder B frame start delay 0xF1064 bits 28:27 + Cougarpoint/Pantherpoint transcoder C frame start delay 0xF2064 bits 28:27 + Workaround (WaFrameStartDelayWaForSDRRS) : If this pipe is connected to the LVDS port and + LVDS clockgating is disabled (bits 14, 30 set to 1b in 0xC2020), then clockgating must be temporarily + enabled (bits 14, 30 cleared to 0b) when toggling Display Power Mode Switch followed by wait of 2 + vblanks and then disabled again. + 19:18 MSA Timing Delay + This field selects the vertical blank line on which MSA is sent. + It is intended for use with embedded DisplayPort panels that support sDRRS. + The sDRRS timing switch shall occur on same line as the MSA. + Value Name Description + 00b Line1 [Default] MSA and sDRRS timing switch occur within the first line of vertical blank + 01b Line2 MSA and sDRRS timing switch occur within the second line of vertical blank + 10b Line3 MSA and sDRRS timing switch occur within the third line of vertical blank + 11b Line4 MSA and sDRRS timing switch occur within the fourth line of vertical blank + 17:16 Reserved + Format: MBZ + 15:14 Display Rotation Info + These are informative bits set by software to indicate this pipe is being rotated. + Software should set these for both hardware and software rotation cases. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 101 + PIPE_CONF + Hardware rotation is not enabled through these bits. + Value Name Description + 00b None [Default] No rotation on this pipe + 01b 90 90 degree rotation on this pipe + 10b 180 180 degree rotation on this pipe + 11b 270 270 degree rotation on this pipe + 13 Color Range Select + This bit is used to select the color range of outputs. + When CE color range is selected the pipe output will be compressed and offset to the CE range. + Value Name Description + 0b Full [Default] Apply full color range to the output + 1b CE Apply CE color range to the output + 12:11 Pipe output color space select + This field informs the ports of the pipe output color space. + Plane data formats and CSC need to be programmed to match what is selected here. + Value Name Description + 00b RGB [Default] RGB + 01b YUV 601 YUV 601 + 10b YUV 709 YUV 709 + 11b Reserved Reserved + 10 xcYCC Color Range Limit + This bit is used to limit the color range of the port outputs from 1 to 254 for 8-bit components, 4 to 109 + for 10bit components, or 16 to 4079 for 12-bit components. + Values outside of the range will be clamped to fit within the range. + There is no need to set the equivalent bit in the south display transcoder configuration register if the bit + is set in this register. + Value Name Description + 0b Full [Default] Do not limit the range + 1b Limit Limit range + 9 Reserved + Format: MBZ + 8 BFI enable + This bit enables black frame insertion on this pipe. + This bit should not be changed while the pipe or port are enabled. + Value Name Description + 0b Disable [Default] BFI disabled + 1b Enable BFI enabled + 7:5 Bits Per Color + This field selects the number of bits per color output on ports connected to this pipe. + Software should enable dithering if selecting a pixel color depth higher or lower than the pixel color + depth of the frame buffer. + Value Name Description + 000b 8 bpc [Default] 8 bits per color + 001b 10 bpc 10 bits per color + 010b 6 bpc 6 bits per color + 011b 12 bpc 12 bits per color + Others Reserved Reserved + 4 Dithering enable + This bit enables dithering + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 102 + PIPE_CONF + Value Name Description + 0b Disable [Default] Dithering disabled + 1b Enable Dithering enabled + 3:2 Dithering type + These bits select dithering type. + Value Name Description + 00b Spatial [Default] Spatial + 10b ST2 Spatio-Temporal 2 + 1:0 Reserved + Format: MBZ + + + + +5.1.4 PIPE_FRMCNT-Pipe Frame Count + + PIPE_FRMCNT +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 70040h-70043h +Name: Pipe A Frame Count +ShortName: PIPE_FRMCNT_A +Address: 71040h-71043h +Name: Pipe B Frame Count +ShortName: PIPE_FRMCNT_B +Address: 72040h-72043h +Name: Pipe C Frame Count +ShortName: PIPE_FRMCNT_C +DWord Bit Description +0 31:0 Pipe Frame Counter + Provides read back of the display pipe frame counter. This counter increments on every start of vertical + blank and rolls over back to 0 after (2^32)-1 frames. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 103 + 5.1.5 PIPE_FLIPCNT-Pipe Flip Count + + PIPE_FLIPCNT +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 70044h-70047h +Name: Pipe A Flip Count +ShortName: PIPE_FLIPCNT_A +Address: 71044h-71047h +Name: Pipe B Flip Count +ShortName: PIPE_FLIPCNT_B +Address: 72044h-72047h +Name: Pipe C Flip Count +ShortName: PIPE_FLIPCNT_C +DWord Bit Description +0 31:0 Pipe Flip Counter + This field provides read back of the display pipe flip counter. + The counter increments on the start of each flip to the primary plane of this pipe. + The start of flip is when the plane surface address is updated, not when the flip completes. + The flip can be through command streamer asynchronous and synchronous flips or MMIO writes to the + primary plane surface address. + It rolls over back to 0 after (2^32)-1 flips. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 104 + 5.1.6 PIPE_FRMTMSTMP-Pipe Frame Time Stamp + + PIPE_FRMTMSTMP +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 70048h-7004Bh +Name: Pipe A Frame Time Stamp +ShortName: PIPE_FRMTMSTMP_A +Address: 71048h-7104Bh +Name: Pipe B Frame Time Stamp +ShortName: PIPE_FRMTMSTMP_B +Address: 72048h-7204Bh +Name: Pipe C Frame Time Stamp +ShortName: PIPE_FRMTMSTMP_C + DWord Bit Description +0 31:0 Pipe Frame Time Stamp + This field provides read back of the display pipe frame time stamp. + The time stamp value is sampled at every start of vertical blank. + The TIMESTAMP_CTR register has the current time stamp value. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 105 + 5.1.7 PIPE_FLIPTMSTMP-Pipe Flip Time Stamp + + PIPE_FLIPTMSTMP +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: 7004Ch-7004Fh +Name: Pipe A Flip Time Stamp +ShortName: PIPE_FLIPTMSTMP_A +Address: 7104Ch-7104Fh +Name: Pipe B Flip Time Stamp +ShortName: PIPE_FLIPTMSTMP_B +Address: 7204Ch-7204Fh +Name: Pipe C Flip Time Stamp +ShortName: PIPE_FLIPTMSTMP_C +DWord Bit Description +0 31:0 Pipe Flip Time Stamp + This field provides read back of the display pipe flip time stamp. + The time stamp value is sampled on the start of each flip to the primary plane of this pipe. + The start of flip is when the plane surface address is updated, not when the flip completes. + The flip can be through command streamer asynchronous and synchronous flips or MMIO writes to the + primary plane surface address. + The TIMESTAMP_CTR register has the current time stamp value. + + + + +5.2 Cursor Plane +The CUR_CTL and CUR_FBC_CTL active registers will be updated on the vertical blank or when pipe is +disabled, or when cursor is not yet enabled – thus providing an atomic update of those registers together +with the CUR_BASE register. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 106 + 5.2.1 CUR_CTL-Cursor Control + + CUR_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled or cursor disabled, after armed +Double Buffer Armed By: Write to CUR_BASE +Address: 70080h-70083h +Name: Cursor A Control +ShortName: CUR_CTL_A +Address: 71080h-71083h +Name: Cursor B Control +ShortName: CUR_CTL_B +Address: 72080h-72083h +Name: Cursor C Control +ShortName: CUR_CTL_C +The cursor is enabled by programming a valid cursor mode in the cursor mode select fields. The cursor is disabled +by programming all 0s in the cursor mode select fields. +DWord Bit Description +0 31:28 Reserved + 26 Gamma Enable + This bit enables pipe gamma correction for the cursor pixel data. + Value Name Description + 0b Disable [Default] Cursor pixel data bypasses pipe gamma correction + 1b Enable Cursor pixel data passes through pipe gamma correction + 25 Reserved + 24 Pipe CSC Enable + This bit enables pipe color space conversion for the cursor pixel data. + Value Name Description + 0b Disable [Default] Cursor pixel data bypasses pipe color space conversion + 1b Enable Cursor pixel data passes through pipe color space conversion + 23:16 Reserved + 15 180 Rotation + This mode causes the cursor image to be rotated 180 degrees. + In addition to setting this bit, software must also adjust the cursor position to match the physical + orientation of the display. + Value Name Description + 0b None [Default] No rotation + 1b 180 180 degree rotation (only for 32 bit per pixel cursors) + + + Programming Notes + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 107 + CUR_CTL + Restriction : Only 32 bits per pixel cursors can be rotated. This field must be zero when the cursor + format is 2 bits per pixel. + 14 Trickle Feed Enable + Value Name Description + 0b Enable Trickle Feed Enabled - Data requests are sent whenever there is space in the + [Default] Display Data Buffer + 1b Disable Trickle Feed Disabled - Data requests are sent in bursts + 13:12 Reserved + 11:10 Force Alpha Plane Select + This field selects which planes the cursor alpha value will be forced for. It is used together the the + Force_Alpha_Value field. + Value Name Description + 00b Disable [Default] Disable alpha forcing + 01b Sprite Enable alpha forcing where cursor overlaps sprite pixels + 10b Primary Enable alpha forcing where cursor overlaps primary pixels + 11b Both Enable alpha forcing where cursor overlaps either sprite or primary pixels. + 9:8 Force Alpha Value + This field controls the behavior of cursor when alpha blending onto certain plane pixels. Force Alpha is + only for use with ARGB cursor formats. It is used together with the Force_Alpha_Plane_Select field. + Value Name Description + 00b Disable Cursor pixels alpha blend normally over any plane + [Default] + 01b 50 Cursor pixels with alpha >= 50% are made fully opaque where they overlap the + selected plane(s). Cursor pixels with alpha < 50% are made fully transparent where + they overlap the selected plane(s). + 10b 75 Cursor pixels with alpha >= 75% are made fully opaque where they overlap the + selected plane(s). Cursor pixels with alpha < 75% are made fully transparent where + they overlap the selected plane(s). + 11b 100 Cursor pixels with alpha = 100% are made fully opaque where they overlap the + selected plane(s). Cursor pixels with alpha < 100% are made fully transparent + where they overlap the selected plane(s). + 7:6 Reserved + 5 Cursor Mode Select 5 + + This bit together with bits 2:0 select the mode for cursor as shown in the cursor mode select table + below. + Bit Bits + 5 2:0 Mode + 0 000 Cursor is disabled + 0 001 Reserved + 0 010 128 x 128 32bpp AND/INVERT See description off 64 x 64 32bpp AND/INVERT format + 0 011 256 x 256 32bpp AND/INVERT See description off 64 x 64 32bpp AND/INVERT format + 0 100 64 x 64 2bpp Indexed 3-color and transparency mode + 0 101 64 x 64 2bpp Indexed AND/XOR 2-plane mode + 0 110 64 x 64 2bpp Indexed 4-color mode + 0 111 64 x 64 32bpp AND/INVERT Least significant three bytes provides cursor RGB 888 color + information Most Significant Byte: All Ones: Opaque, show the cursor color All Zeros: + Transparent (color must also equal zero) Other: Invert the underlying display pixel data + (ignore the color) + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 108 + CUR_CTL + 1 000 Reserved + 1 001 Reserved + 1 010 128 x 128 32bpp ARGB (8:8:8:8 MSB-A:R:G:B) + 1 011 256 x 256 32bpp ARGB (8:8:8:8 MSB-A:R:G:B) + 1 100 64 x 64 32bpp AND/XOR Least significant three bytes provides cursor RGB 888 color + information Most Significant Byte: All Ones: Opaque, show the cursor color All Zeros: + Transparent (color must also equal zero) Other: XOR the cursor color with the underlying + display pixel data + 1 101 128 x 128 32bpp AND/XOR See description off 64 x 64 32bpp AND/XOR format + 1 110 256 x 256 32bpp AND/XOR See description off 64 x 64 32bpp AND/XOR format + 1 111 64 x 64 32bpp ARGB (8:8:8:8 MSB-A:R:G:B) + + Note: The cursor vertical size can be overriden by the size reduction mode + + Note: INVERT, XOR, and alpha blends may not look as expected when the plane underlying the + cursor is YUV or extended range RGB. Out of range RGB values will be clamped prior to alpha + blending, INVERT, or XOR with cursor. It is recommended to use Force_Alpha when cursor is alpha + blending onto an plane of a different color space or extended gamut + + 4:3 Reserved + 2:0 Cursor Mode Select 2 0 + These three bits together with bit 5 select the mode for cursor as shown in the table described in bit 5. + + + + +5.2.2 CUR_BASE-Cursor Base Address + + CUR_BASE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled +Address: 70084h-70087h +Name: Cursor A Base Address +ShortName: CUR_BASE_A +Address: 71084h-71087h +Name: Cursor B Base Address +ShortName: CUR_BASE_B +Address: 72084h-72087h +Name: Cursor C Base Address +ShortName: CUR_BASE_C +Writes to this register arm cursor registers for this pipe. This register specifies the graphics memory address at which +the cursor image data is located. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 109 + DWord Bit Description +0 31:12 Cursor Base + Format: GraphicsAddress[31:12] + This field specifies bits 31:12 of the graphics address of the base of the cursor. + The cursor surface address must be 4K byte aligned. + The cursor must be in linear memory, it cannot be tiled. + When performing 180 degree rotation, this address does not need to change, hardware will internally + offset to start from the last pixel of the last line of the cursor. + Programming Notes + Workaround : To prevent false VT-d type 6 errors, use 64KB address alignment and allocate an extra 2 + Page Table Entries (PTEs) beyond the end of the displayed surface. + Only the PTEs will be used, not the pages themselves. + 11:3 Reserved + 1:0 Reserved + + + + +5.2.3 CUR_POS-Cursor Position + + CUR_POS +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled +Address: 70088h-7008Bh +Name: Cursor A Position +ShortName: CUR_POS_A +Address: 71088h-7108Bh +Name: Cursor B Position +ShortName: CUR_POS_B +Address: 72088h-7208Bh +Name: Cursor C Position +ShortName: CUR_POS_C +This register specifies the screen position of the cursor. The cursor must have at least a single pixel positioned over +the pipe source area. + The origin of the cursor position is always the upper left corner of the display pipe source image area. + When performing 180 degree rotation, the cursor image is rotated by hardware, but the position is not, so it must be +adjusted by software if it is desired to maintain the same apparent position on a physically rotated display. + DWord Bit Description +0 31 Y Position Sign + This specifies the sign of the vertical position of the cursor upper left corner. + 30:28 Reserved + Format: MBZ + 27:16 Y Position Magnitude + This specifies the magnitude of the vertical position of the cursor upper left corner in lines. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 110 + CUR_POS + 15 X Position Sign + This specifies the sign of the horizontal position of the cursor upper left corner. + 14:12 Reserved + Format: MBZ + 11:0 X Position Magnitude + This specifies the magnitude of the horizontal position of the cursor upper left corner in pixels. + + + + +5.2.4 CUR_PAL-Cursor Palette + + Cursor Palette Format +Project: +Default Value: 0x00000000 +DWord Bit Description +0 31:24 Reserved + Format: MBZ + 23:16 Palette Red + These registers specify the cursor palette. The data can be pre-gamma corrected and bypass the pipe + gamma correction logic or pass through the pipe gamma correction. + 15:8 Palette Green + 7:0 Palette Blue + + + + + CUR_PAL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 4x32 +Double Buffer Update Point: Start of vertical blank or pipe disabled +Address: 70090h-7009Fh +Name: Cursor A Palette +ShortName: CUR_PAL_[0-3]_A +Address: 71090h-7109Fh +Name: Cursor B Palette +ShortName: CUR_PAL_[0-3]_B +Address: 72090h-7209Fh +Name: Cursor C Palette +ShortName: CUR_PAL_[0-3]_C + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 111 + CUR_PAL +The cursor palette provides color information when using one of the indexed modes. The two-bit index selects one +of the four colors or two of the colors when in the AND/XOR cursor mode. The cursor palette provides color +information when using one of the indexed modes. The two-bit index selects one of the four colors or two of the +colors when in the AND/XOR cursor mode. + +The table below describes the palette usage for different cursor modes and indexes. + + Index 2 color 3color 4color + + 00 palette 0 palette 0 palette 0 + + 01 palette 1 palette 1 palette 1 + + 10 transparent transparent palette 2 + + 11 invert destination palette 3 palette 3 + + (palette 3 all 1s) + +Palette 3 must be programmed with all 1s for invert destination. + + DWord Bit Description +0 31:0 CUR PAL0 + Format: Cursor Palette Format +1 31:0 CUR PAL1 + Format: Cursor Palette Format +2 31:0 CUR PAL2 + Format: Cursor Palette Format +3 31:0 CUR PAL3 + Format: Cursor Palette Format + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 112 + 5.2.5 CUR_FBC_CTL-Cursor FBC Control + + CUR_FBC_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled or cursor disabled, after armed +Double Buffer Armed By: Write to CUR_BASE +Address: 700A0h-700A3h +Name: Cursor A FBC Control +ShortName: CUR_FBC_CTL_A +Address: 710A0h-710A3h +Name: Cursor B FBC Control +ShortName: CUR_FBC_CTL_B +Address: 720A0h-720A3h +Name: Cursor C FBC Control +ShortName: CUR_FBC_CTL_C +DWord Bit Description +0 31 Size Reduction Enable + This enables cursor size reduction logic. The cursor engine will fetch and display the programmed + reduced number of lines, then go transparent for the rest of the frame. + The reduced scan lines value must be programmed when cursor size reduction is enabled. + Value Name Description + 0b Disable [Default] Disable cursor size reduction + 1b Enable Enable cursor size reduction + + + Programming Notes + Restriction : Cursor size reduction is not allowed with 2bpp cursor formats or cursor 180 degree rotation. + 30:8 Reserved + 7:0 Reduced Scan Lines + This specifies the number of scan lines of cursor data to fetch and display when cursor size reduction is + enabled. The value programmed is the size minus one. + Programming Notes + Restriction : The minimum size is 8 lines, programmed as 07h. + Restriction : The maximum size can not be greater than the normal size when size reduction is not + enabled. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 113 + 5.2.6 PLANE_SURFLIVE-Plane Live Base Address + + PLANE_SURFLIVE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: 700ACh-700AFh +Name: Cursor A Live Base Address +ShortName: CUR_SURFLIVE_A +Address: 701ACh-701AFh +Name: Primary A Live Base Address +ShortName: PRI_SURFLIVE_A +Address: 702ACh-702AFh +Name: Sprite A Live Base Address +ShortName: SPR_SURFLIVE_A +Address: 710ACh-710AFh +Name: Cursor B Live Base Address +ShortName: CUR_SURFLIVE_B +Address: 711ACh-711AFh +Name: Primary B Live Base Address +ShortName: PRI_SURFLIVE_B +Address: 712ACh-712AFh +Name: Sprite B Live Base Address +ShortName: SPR_SURFLIVE_B +Address: 720ACh-720AFh +Name: Cursor C Live Base Address +ShortName: CUR_SURFLIVE_C +Address: 721ACh-721AFh +Name: Primary C Live Base Address +ShortName: PRI_SURFLIVE_C +Address: 722ACh-722AFh +Name: Sprite C Live Base Address +ShortName: SPR_SURFLIVE_C +DWord Bit Description +0 31:0 Live Surface Base Address + This gives the live value of the surface base address as being currently used for the plane. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 114 + 5.3 Primary Plane +Many of the plane control active registers will be updated on the vertical blank or when pipe is disabled, +after the surface base address register is written, or when the plane is not yet enabled – thus providing an +atomic update of those registers together with the surface base address register. + + +5.3.1 PRI_CTL-Primary Control + + PRI_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled or primary disabled, after armed +Double Buffer Armed By: Write to PRI_SURF +Address: 70180h-70183h +Name: Primary A Control +ShortName: PRI_CTL_A +Address: 71180h-71183h +Name: Primary B Control +ShortName: PRI_CTL_B +Address: 72180h-72183h +Name: Primary C Control +ShortName: PRI_CTL_C +DWord Bit Description +0 31 Primary Plane Enable + Format: Enable + When this bit is set, the primary plane will generate pixels for display. When set to zero, primary plane + memory fetches cease and plane output is transparent. When in Self Refresh Big FIFO mode, a write + to enable the plane will be internally buffered and delayed while Big FIFO mode is exiting. + + 30 Gamma Enable + This bit enables pipe gamma correction for the plane pixel data. For 8-bit indexed display data, this bit + should be set to a one. + Value Name Description + 0b Disable [Default] Plane pixel data bypasses pipe gamma correction + 1b Enable Plane pixel data passes through pipe gamma correction + 29:26 Source Pixel Format + This field selects the source pixel format for the primary plane. + The 8-bpp indexed format will use the pipe palette. + Before entering the blender, each source format is converted to the pipe pixel format. + Alpha values are ignored. + Value Name Description + 0010b 8-bit Indexed 8-bit Indexed + 0101b 16-bit BGRX 5:6:5 16-bit BGRX (5:6:5 MSB-R:G:B) + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 115 + PRI_CTL + 0110b 32-bit BGRX 8:8:8 32-bit BGRX (8:8:8:8 MSB-X:R:G:B) + 1000b 32-bit RGBX 10:10:10 32-bit RGBX (2:10:10:10 MSB-X:B:G:R) + 1001b 32-bit XR_BIAS RGBX 10:10:10 32-bit Extended Range Bias RGBX (2:10:10:10 MSB-X:B:G:R) + 1010b 32-bit BGRX 10:10:10 32-bit BGRX (2:10:10:10 MSB-X:R:G:B) + 1100b 64-bit RGBX FP 64-bit RGBX Floating Point(16:16:16:16 MSB-X:B:G:R) + 1110b 32-bit RGBX 8:8:8 32-bit RGBX (8:8:8:8 MSB-X:B:G:R) + Others Reserved Reserved + + + Programming Notes + Workaround (WaFP16GammaEnabling) : When using the 64-bit format, the plane output on each color + channel has one quarter amplitude. It can be brought up to full amplitude by using pipe gamma + correction or pipe color space conversion to multiply the plane output by four. + 25 Reserved + 24 Pipe CSC Enable + This bit enables pipe color space conversion for the plane pixel data. + Value Name Description + 0b Disable [Default] Plane pixel data bypasses the pipe color space conversion + 1b Enable Plane pixel data passes through the pipe color space conversion + 23:16 Reserved + 15 180 Display Rotation + This mode causes the plane image to be rotated 180 degrees. + In addition to setting this bit, software must also set the surface address offset (lineary or tiled offset + registers depending on tiled surface select) to the lower right corner of the unrotated image. + Value Name Description + 0b None [Default] No rotation + 1b 180 180 degree rotation + 14 Trickle Feed Enable + Value Name Description + 0b Enable Trickle Feed Enabled - Plane data requests are sent whenever there is space in + [Default] the Display Data Buffer. + 1b Disable Trickle Feed Disabled - Plane data requests are sent in bursts + 13:11 Reserved + 10 Tiled Surface + This bit indicates that the surface data is in tiled memory. The tile pitch is specified in bytes in the plane + stride register. Only X tiling is supported. + When this bit is set, it affects the interpretation of the offset and surface address registers. + This bit may be updated through MMIO writes or through a command streamer initiated synchronous + flip. + Value Name Description + 0b Linear [Default] Plane uses linear memory + 1b X-Tiled Planes uses X-Tiled memory + 9 Async Address Update Enable + This bit will enable asynchronous updates of the plane surface address when written by MMIO (MMIO + asynchronous flips). + The surface address will change with the next plane TLB request or when start of vertical blank is + reached. + Updates during vertical blank may not complete until after the first few active lines are displayed. + This bit is not double-buffered, so it will update immediately after being written. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 116 + PRI_CTL + Value Name Description + 0b Sync Surface Address MMIO writes will update synchronous to start of vertical blank + [Default] (synchronous flips) + 1b Async Surface Address MMIO writes will update asynchronously (asynchronous flips) + + + Programming Notes + Restriction : No command streamer initiated flips to this plane are allowed when this bit is enabled. + Each surface address write must be followed by a wait for flip done indication before writing the + surface address register again. + Linear memory does not support async updates. + 8:0 Reserved + Format: MBZ + + + +Plane Source Pixel Format Mapping of Bits to Colors: + +Format Ignored Red Green Blue + +16-bit BGRX 5:6:5 N/A 15:11 10:5 4:0 +32-bit BGRX 8:8:8 31:24 23:16 15:8 7:0 +32-bit RGBX 10:10:10 31:30 9:0 19:10 29:20 +32-bit BGRX 10:10:10 31:30 29:20 19:10 9:0 + 63:48 15:0 31:16 47:32 +64-bit RGBX Float 16:16:16 +Each component is 1:5:10 MSb-sign:exponent:fraction +32-bit RGBX 8:8:8 31:24 7:0 15:8 23:16 +32-bit XR_BIAS RGBX 10:10:10 31:30 9:0 19:10 29:20 + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 117 + 5.3.2 PRI_LINOFF-Primary Linear Offset + + PRI_LINOFF +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled +Address: 70184h-70187h +Name: Primary A Linear Offset +ShortName: PRI_LINOFF_A +Address: 71184h-71187h +Name: Primary B Linear Offset +ShortName: PRI_LINOFF_B +Address: 72184h-72187h +Name: Primary C Linear Offset +ShortName: PRI_LINOFF_C +DWord Bit Description +0 31:0 Linear Offset + This register specifies the panning for the plane surface in linear memory. + This value is added to the surface address to get the address of the first pixel to be displayed. + This offset must be at least pixel aligned for RGB formats. + When performing 180 degree rotation, the unpanned offset must be the difference between the last + pixel of the last line of the display data in its unrotated orientation and the display surface address. + When the surface is tiled, the tiled offset is programmed and the contents of this register are ignored. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 118 + 5.3.3 PRI_STRIDE-Primary Stride + + PRI_STRIDE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled or primary disabled, after armed +Double Buffer Armed By: Write to PRI_SURF +Address: 70188h-7018Bh +Name: Primary A Stride +ShortName: PRI_STRIDE_A +Address: 71188h-7118Bh +Name: Primary B Stride +ShortName: PRI_STRIDE_B +Address: 72188h-7218Bh +Name: Primary C Stride +ShortName: PRI_STRIDE_C +DWord Bit Description +0 31:16 Reserved + 15:6 Stride + This is the stride for the plane in bytes. This value is used to determine the line to line increment for the + plane. When using linear memory, this must be at least 64 byte aligned. When using tiled memory, this + must be at least 512 byte aligned. This register may be updated through MMIO writes or through a + command streamer initiated synchronous flip. The stride is limited to a maximum of 32K bytes. + 5:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 119 + 5.3.4 PRI_SURF-Primary Surface Base Address + + PRI_SURF +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank, pipe disabled, or next plane line request if asynchronous flip +Address: 7019Ch-7019Fh +Name: Primary A Base Address +ShortName: PRI_SURF_A +Address: 7119Ch-7119Fh +Name: Primary B Base Address +ShortName: PRI_SURF_B +Address: 7219Ch-7219Fh +Name: Primary C Base Address +ShortName: PRI_SURF_C +Writes to this register arm primary registers for this pipe +DWord Bit Description +0 31:12 Surface Base Address + Format: GraphicsAddress[31:12] + This address specifies the surface base address. + It represents an offset from the graphics memory aperture base and is mapped to physical pages + through the global GTT. + It must be at least 4KB aligned. + When performing asynchronous flips and the display surface is in tiled memory, this address must be + 256KB aligned. + This register may be updated through MMIO writes or through a command streamer initiated + synchronous or asynchronous flip. + Programming Notes + Workaround : To prevent false VT-d type 6 errors, use 256KB address alignment and allocate an extra + 128 Page Table Entries (PTEs) beyond the end of the displayed surface. + Only the PTEs will be used, not the pages themselves. + 11:3 Reserved + 1:0 Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 120 + 5.3.5 PRI_TILEOFF-Primary Tiled Offset + + PRI_TILEOFF +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled +Address: 701A4h-701A7h +Name: Primary A Tiled Offset +ShortName: PRI_TILEOFF_A +Address: 711A4h-711A7h +Name: Primary B Tiled Offset +ShortName: PRI_TILEOFF_B +Address: 721A4h-721A7h +Name: Primary C Tiled Offset +ShortName: PRI_TILEOFF_C +This register specifies the panning for the plane surface in tiled memory. + When the surface is in linear memory, the linear offset is programmed and the contents of this register are ignored. + When the surface is tiled, the start position is specified in this register as a (x, y) offset from the beginning of the +surface. + When performing 180 degree rotation, the unpanned offset must be programmed to the last pixel of the last line of +the display data. + DWord Bit Description +0 31:28 Reserved + Format: MBZ + 27:16 Start Y Position + The vertical offset in lines of the beginning of the active display plane relative to the display surface. + 15:12 Reserved + Format: MBZ + 11:0 Start X Position + The horizontal offset in pixels of the beginning of the active display plane relative to the display + surface. + + + + +5.4 Sprite Plane +Many of the plane control active registers will be updated on the vertical blank or when pipe is disabled, +after the surface base address register is written, or when the plane is not yet enabled – thus providing an +atomic update of those registers together with the surface base address register. +Data flow through the sprite plane (Steps 2-6 may be enabled or disabled by programming control bits): + 1. Unpack data into pixels + 2. Scale + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 121 + 3. Source Key + 4. YUV Range Correction (can only be used by YUV source pixel formats) + 5. YUV to RGB Color Space Conversion (can only be used by YUV source pixel formats) + 6. Sprite Gamma Correction + 7. Conversion to pipe data format + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 122 + 5.4.1 SPR_CTL-Sprite Control + + SPR_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled or sprite disabled, after armed +Double Buffer Armed By: Write to SPR_SURF +Address: 70280h-70283h +Name: Sprite A Control +ShortName: SPR_CTL_A +Address: 71280h-71283h +Name: Sprite B Control +ShortName: SPR_CTL_B +Address: 72280h-72283h +Name: Sprite C Control +ShortName: SPR_CTL_C + +DWord Bit Description +0 31 Sprite Enable + Format: Enable + When this bit is set, the sprite plane will generate pixels for display. When set to zero, sprite plane + memory fetches cease and plane output is transparent. When in Self Refresh Big FIFO mode, a write + to enable the plane will be internally buffered and delayed while Big FIFO mode is exiting. + + 30 Pipe Gamma Enable + This bit enables pipe gamma correction for the sprite pixel data. + Value Name Description + 0b Disable [Default] Plane pixel data bypasses pipe gamma correction + 1b Enable Plane pixel data passes through pipe gamma correctopm + 29 Reserved + Format: MBZ + 28 YUV Range Correction Disable + Setting this bit disables the YUV range correction logic inside the sprite. The range correction logic is + used to expand the compressed range YUV to full range YUV. The Y channel is expanded from the 8 + bit +16 to +235 range to full range. The U and V channels are expanded from the 8 bit -112 to +112 + range to full range. Extended range values will be preserved after the expansion. This bit has no effect + on RGB source pixel formats since they automatically bypass range correction. + Value Name Description + 0b Enable [Default] Range correction enabled + 1b Disable No range correction + 27:25 Source Pixel Format + This field selects the source pixel format for the sprite plane. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 123 + SPR_CTL + Before entering the blender, each source format is converted to the pipe pixel format. + Alpha values are ignored. + YUV 4:2:2 byte order is programmed separately. + YUV 4:4:4 byte order is not programmable. + RGB color order is programmed separately, except RGB XR_BIAS byte order is not programmable. + Value Name Description + 000b YUV 16-bit 4:2:2 YUV 16-bit 4:2:2 packed + 001b RGB 32-bit 2:10:10:10 RGB 32-bit 2:10:10:10 + 010b RGB 32-bit 8:8:8:8 RGB 32-bit 8:8:8:8 + 011b RGB 64-bit 16:16:16:16 RGB 64-bit 16:16:16:16 Floating Point + 100b YUV 32-bit 4:4:4 YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V) + 101b RGB 32-bit XR_BIAS RGB 32-bit Extended Range Bias RGBX (2:10:10:10 MSB- + 10:10:10 X:B:G:R) + Others Reserved Reserved + + + Programming Notes + Workaround (WaFP16GammaEnabling) : When using the 64-bit format, the sprite output on each color + channel has one quarter amplitude. It can be brought up to full amplitude by using sprite internal + gamma correction, pipe gamma correction, or pipe color space conversion to multiply the sprite output + by four. + Workaround (DisableSpritePassThroughMode) : When using YUV formats and the sprite internal CSC + is disabled, the sprite output will not have a 1/2 offset on the U and V channels. An offset on U and V + channels is typically required by receivers. It can be added using the pipe CSC. + + If pipe CSC is already in use for RGB to YUV conversion, then the sprite internal CSC can be used to + convert the sprite output to RGB, and the sprite can be sent through the pipe CSC, programmed for + RGB to YUV conversion with pipe CSC post-offset of +1/2. + + If pipe CSC is not already in use, then the sprite output can be kept as YUV, and the sprite can be + sent through the pipe CSC, programmed for 1:1 pass through with pipe CSC post-offset of +1/2. + 24 Pipe CSC Enable + This bit enables pipe color space conversion for the plane pixel data. This is separate from the color + conversion logic within the sprite plane. + Value Name Description + 0b Disable [Default] Plane pixel data bypasses the pipe color space conversion + 1b Enable Plane pixel data passes through the pipe color space conversion + 23 Reserved + Format: MBZ + 22 Sprite Source Key Enable + This bit enables source color keying. Sprite pixel values that match (within range) the key will become + transparent. Source key can not be enabled if destination key is enabled. + Value Name Description + 0b Disable [Default] Sprite source key is disabled + 1b Enable Sprite source key is enabled + 21 Reserved + Format: MBZ + 20 RGB Color Order + This field is used to select the color order when using RGB data formats, except RGB 32-bit XR_BIAS + 10:10:10. For other formats, this field is ignored. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 124 + SPR_CTL + Value Name Description + 0b BGRX [Default] BGRX (MSB-X:R:G:B) + 1b RGBX RGBX (MSB-X:B:G:R) + 19 Sprite YUV to RGB CSC Dis + This bit controls the sprite internal YUV to RGB color space conversion. RGB source pixel formats + automatically bypass the sprite internal color space conversion. + Value Name Description + 0b Enable [Default] YUV pixel data goes through the sprite color conversion + 1b Disable YUV pixel data bypasses the sprite color conversion + 18 Sprite YUV to RGB CSC Format + This bit specifies the source YUV format for the sprite internal YUV to RGB color space conversion + operation. This field is ignored when source data is RGB. + Value Name Description + 0b BT.601 [Default] ITU-R Recommendation BT.601 + 1b BT.709 ITU-R Recommendation BT.709 + 17:16 YUV 422 Byte Order + This field is used to select the byte order when using YUV 4:2:2 data formats. For other formats, this + field is ignored. + Value Name Description + 00b YUYV [Default] YUYV (8:8:8:8 MSB-V:Y2:U:Y1) + 01b UYVY UYVY (8:8:8:8 MSB-Y2:V:Y1:U) + 10b YVYU YVYU (8:8:8:8 MSB-U:Y2:V:Y1) + 11b VYUY VYUY (8:8:8:8 MSB-Y2:U:Y1:V) + 15 180 Display Rotation + This mode causes the plane image to be rotated 180 degrees. + In addition to setting this bit, software must also set the surface address offset (linear or tiled offset + registers depending on tiled surface select) to the lower right corner of the unrotated and unscaled + surface image and adjust the plane position to match the physical orientation of the display. + Value Name Description + 0b None [Default] No rotation + 1b 180 180 degree rotation + 14 Trickle Feed Enable + Value Name Description + 0b Enable Trickle Feed Enabled - Data requests are sent whenever there is space in the + [Default] Display Data Buffer + 1b Disable Trickle Feed Disabled - Data requests are sent in bursts. + 13 Sprite Gamma Disable + This bit controls sprite internal gamma correction. + Value Name Description + 1b Disable Disable sprite internal gamma correction + 0b Enable [Default] Enable sprite internal gamma correction + 12:11 Reserved + 10 Tiled Surface + This bit indicates that the surface data is in tiled memory. + The tile pitch is specified in bytes in the plane stride register. + Only X tiling is supported. + When this bit is set, it affects the interpretation of the offset and surface address registers. + This bit may be updated through MMIO writes or through a command streamer initiated synchronous + flip. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 125 + SPR_CTL + Value Name Description + 0b Linear [Default] Plane uses linear memory + 1b X-Tiled Planes uses X-Tiled memory + 9:3 Reserved + Format: MBZ + 2 Sprite Destination Key + This bit enables the destination key function. + When blending together sprite and primary planes, if the primary plane pixel matches the key value, + then the sprite pixel is output, otherwise the primary pixel is output. + Destination Key can not be enabled if source key is enabled. + Value Name Description + 0b Disable [Default] Destination Key is disabled + 1b Enable Destination Key is enabled + 1:0 Reserved + Format: MBZ + +Sprite Source Pixel Format Mapping of Bits to Colors: +Note: For RGB formats, see the primary plane source pixel format mapping table + + SPRITE YUV 4:2:2 Y1 U Y2 V + +YUV 4:2:2 YUYV 7:0 15:8 23:16 31:24 +YUV 4:2:2 UYVY 15:8 7:0 31:24 23:16 +YUV 4:2:2 YVYU 7:0 31:24 23:16 15:8 +YUV 4:2:2 VYUY 15:8 23:16 31:24 7:0 + SPRITE YUV 4:4:4 Ignored Y U V + +YUV 32-bit 4:4:4 31:24 23:16 15:8 7:0 + + +5.4.2 SPR_LINOFF-Sprite Linear Offset + + SPR_LINOFF +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled +Address: 70284h-70287h +Name: Sprite A Linear Offset +ShortName: SPR_LINOFF_A +Address: 71284h-71287h +Name: Sprite B Linear Offset +ShortName: SPR_LINOFF_B + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 126 + SPR_LINOFF +Address: 72284h-72287h +Name: Sprite C Linear Offset +ShortName: SPR_LINOFF_C +DWord Bit Description +0 31:0 Linear Offset + This register specifies the panning for the plane surface in linear memory. + This value is added to the surface address to get the address of the first pixel to be displayed. + This offset must be at least pixel aligned for unrotated RGB or YUV 4:4:4 formats and even pixel + aligned for unrotated YUV 4:2:2 formats. + When performing 180 degree rotation, the unpanned offset must be the difference between the last + pixel of the last line of the display data in its unrotated orientation and the display surface address. + When the surface is tiled, the tiled offset is programmed and the contents of this register are ignored. + When using sprite scaling the offset is done on the source pixels. + + + + +5.4.3 SPR_STRIDE-Sprite Stride + + SPR_STRIDE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled or sprite disabled, after armed +Double Buffer Armed By: Write to SPR_SURF +Address: 70288h-7028Bh +Name: Sprite A Stride +ShortName: SPR_STRIDE_A +Address: 71288h-7128Bh +Name: Sprite B Stride +ShortName: SPR_STRIDE_B +Address: 72288h-7228Bh +Name: Sprite C Stride +ShortName: SPR_STRIDE_C +DWord Bit Description +0 31:15 Reserved + 14:6 Stride + This is the stride for the plane in bytes. This value is used to determine the line to line increment for the + plane. When using linear memory, this must be at least 64 byte aligned. When using tiled memory, this + must be at least 512 byte aligned. This register may be updated through MMIO writes or through a + command streamer initiated synchronous flip. The stride is limited to a maximum of 16K bytes when + sprite scaling is not enabled, 4K bytes when sprite scaling is enabled. + 5:0 Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 127 + 5.4.4 SPR_POS-Sprite Position + + SPR_POS +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled or sprite disabled, after armed +Double Buffer Armed By: Write to SPR_SURF +Address: 7028Ch-7028Fh +Name: Sprite A Position +ShortName: SPR_POS_A +Address: 7128Ch-7128Fh +Name: Sprite B Position +ShortName: SPR_POS_B +Address: 7228Ch-7228Fh +Name: Sprite C Position +ShortName: SPR_POS_C +This register specifies the screen position of the sprite. The sprite must be completely contained within the pipe +source area. Pipe source size >= sprite position + sprite size The origin of the sprite position is always the upper left +corner of the display pipe source image area. When performing 180 degree rotation, the sprite image is rotated by +hardware, but the position is not, so it must be adjusted by software if it is desired to maintain the same apparent +position on a physically rotated display. + DWord Bit Description +0 31:28 Reserved + Format: MBZ + 27:16 Y Position + This specifies the vertical position of the sprite upper left corner in lines. + 15:12 Reserved + Format: MBZ + 11:0 X Position + This specifies the horizontal position of the sprite upper left corner in pixels. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 128 + 5.4.5 SPR_SIZE-Sprite Size + + SPR_SIZE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled or sprite disabled, after armed +Double Buffer Armed By: Write to SPR_SURF +Address: 70290h-70293h +Name: Sprite A Size +ShortName: SPR_SIZE_A +Address: 71290h-71293h +Name: Sprite B Size +ShortName: SPR_SIZE_B +Address: 72290h-72293h +Name: Sprite C Size +ShortName: SPR_SIZE_C +This register specifies the size of the sprite. The sprite must be completely contained within the pipe source area. +Pipe source size >= sprite position + sprite sizeThe sprite must be at least one pixel high and one pixel wide. +DWord Bit Description +0 31:28 Reserved + Format: MBZ + 27:16 Height + This specifies the height of the sprite in lines. The value in the register is the height minus one. + 15:12 Reserved + Format: MBZ + 11:0 Width + This specifies the width of the sprite in pixels. The value in the register is the width minus one. This + should be less than or equal to the stride in pixels. The width (prior to minus one) must be even when a + YUV 4:2:2 source pixel format is used. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 129 + 5.4.6 SPR_SURF-Sprite Surface Base Address + + SPR_SURF +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled +Address: 7029Ch-7029Fh +Name: Sprite A Surface Base Address +ShortName: SPR_SURF_A +Address: 7129Ch-7129Fh +Name: Sprite B Surface Base Address +ShortName: SPR_SURF_B +Address: 7229Ch-7229Fh +Name: Sprite C Surface Base Address +ShortName: SPR_SURF_C +Writes to this register arm sprite registers for this pipe +DWord Bit Description +0 31:12 Surface Base Address + Format: Graphicsdress[31:12] + This address specifies the surface base address. + It represents an offset from the graphics memory aperture base and is mapped to physical pages + through the global GTT. + It must be at least 4KB aligned. + This register may be updated through MMIO writes or through a command streamer initiated + synchronous flip. + Programming Notes + Workaround : To prevent false VT-d type 6 errors, use 128KB address alignment and allocate an extra + 64 Page Table Entries (PTEs) beyond the end of the displayed surface. + Only the PTEs will be used, not the pages themselves. + 11:3 Reserved + 1:0 Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 130 + 5.4.7 SPR_TILEOFF-Sprite Tiled Offset + + SPR_TILEOFF +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled +Address: 702A4h-702A7h +Name: Sprite A Tiled Offset +ShortName: SPR_TILEOFF_A +Address: 712A4h-712A7h +Name: Sprite B Tiled Offset +ShortName: SPR_TILEOFF_B +Address: 722A4h-722A7h +Name: Sprite C Tiled Offset +ShortName: SPR_TILEOFF_C +This register specifies the panning for the plane surface in tiled memory. + When the surface is in linear memory, the linear offset is programmed and the contents of this register are ignored. + When the surface is tiled, the start position is specified in this register as a (x, y) offset from the beginning of the +surface. + When performing 180 degree rotation, the unpanned offset must be programmed to the last pixel of the last line of +the display data. + When using sprite scaling the offset is done on the source pixels. + This offset must be even pixel aligned for unrotated YUV 4:2:2 formats. + DWord Bit Description +0 31:28 Reserved + Format: MBZ + 27:16 Start Y Position + The vertical offset in lines of the beginning of the active display plane relative to the display surface. + 15:12 Reserved + Format: MBZ + 11:0 Start X Position + The horizontal offset in pixels of the beginning of the active display plane relative to the display + surface. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 131 + 5.4.8 SPR_KEYVAL-Sprite Key Color Value + + SPR_KEYVAL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled +Address: 70294h-70297h +Name: Sprite A Key Color Value +ShortName: SPR_KEYVAL_A +Address: 71294h-71297h +Name: Sprite B Key Color Value +ShortName: SPR_KEYVAL_B +Address: 72294h-72297h +Name: Sprite C Key Color Value +ShortName: SPR_KEYVAL_C +For source key when sprite source is YUV, this register specifies the source key YUV minimum color value to be +used together with the YUV maximum color value and the color channel enable bits to determine if the sprite +matches the source key color range. + For source key when sprite source is RGB, this register specifies the source key RGB color value to be used +together with the color channel enable bits to determine if the sprite matches the source key color. + For destination key, this register specifies the destination key RGB color value to be used together with the RGB +mask bits to determine if the primary matches the destination key color. + A key match can only occur for positive pixel values in the 0 to 1 range. Extended range pixel values will not match. +DWord Bit Description +0 31:24 Reserved + Format: MBZ + 23:16 V R Min Dest Key Value + Specifies the color key minimum value for the sprite V channel source key, the compare value for + sprite Red channel source key, or the compare value for the primary Red channel destination key. + 15:8 Y G Min Dest Key Value + Specifies the color key minimum value for the sprite Y channel source key, the compare value for + sprite Green channel source key, or the compare value for the primary Green channel destination key. + 7:0 U B Min Dest Key Value + Specifies the color key minimum value for the sprite U channel source key, the compare value for + sprite Blue channel source key, or the compare value for the primary Blue channel destination key. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 132 + 5.4.9 SPR_KEYMSK-Sprite Key Mask + + SPR_KEYMSK +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled +Address: 70298h-7029Bh +Name: Sprite A Key Mask +ShortName: SPR_KEYMSK_A +Address: 71298h-7129Bh +Name: Sprite B Key Mask +ShortName: SPR_KEYMSK_B +Address: 72298h-7229Bh +Name: Sprite C Key Mask +ShortName: SPR_KEYMSK_C +For source key, this register specifies which channels to perform key color checking on. A channel that is not enabled +for key comparison will always match on the full range of values. + For destination key, this register specifies the key mask to be used with the color value bits to determine if the +primary plane pixels match the key. A zero bit in the mask indicates that the corresponding bit match failure should +be ignored when determining if the pixel matches. + Programming Notes +Restriction : Source key and destination key are mutually exclusive modes of operation, they can not be used +simultaneously. For the function that is not enabled, the associated bits in this register should be programmed to +zeroes. + DWord Bit Description +0 31:27 Reserved + Format: MBZ + 26 V R Source Key Channel Enable + Enables the V/Red channel for source key color comparison. + 25 Y G Source Key Channel Enable + Enables the Y/Green channel for source key color comparison. + 24 U B Source Key Channel Enable + Enables the U/Blue channel for source key color comparison. + 23:16 R Dest Key Mask Value + Specifies the destination color key mask for the Red channel + 15:8 G Dest Key Mask Value + Specifies the destination color key mask for the Green channel + 7:0 B Dest Key Mask Value + Specifies the destination color key mask for the Blue channel + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 133 + 5.4.10 SPR_KEYMAX-Sprite Key Color Max + + SPR_KEYMAX +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled +Address: 702A0h-702A3h +Name: Sprite A Key Color Max +ShortName: SPR_KEYMAX_A +Address: 712A0h-712A3h +Name: Sprite B Key Color Max +ShortName: SPR_KEYMAX_B +Address: 722A0h-722A3h +Name: Sprite C Key Color Max +ShortName: SPR_KEYMAX_C +For source key when sprite source is YUV, this register specifies the source key YUV maximum color value to be +used together with the YUV minimum color value and the color channel enable bits to determine if the sprite matches +the source key color range. + DWord Bit Description +0 31:24 Reserved + Format: MBZ + 23:16 V Source Key Max Value + Specifies the color key maximum value for the sprite V channel source key + 15:8 Y Source Key Max Value + Specifies the color key maximum value for the sprite Y channel source key + 7:0 U Source Key Max Value + Specifies the color key maximum value for the sprite U channel source key + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 134 + 5.4.11 SPR_SCALE-Sprite Scaler Control + + SPR_SCALE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank or pipe disabled or sprite disabled, after armed +Double Buffer Armed By: Write to SPR_SURF +Address: 70304h-70307h +Name: Sprite A Scaler Control +ShortName: SPR_SCALE_A +Address: 71304h-71307h +Name: Sprite B Scaler Control +ShortName: SPR_SCALE_B +Address: 72304h-72307h +Name: Sprite C Scaler Control +ShortName: SPR_SCALE_C +This register controls the sprite scaling. + When scaling is enabled, the SPR_SIZE register gives the destination (output to pipe) size of the sprite and this +register gives the source (input to sprite) size of the sprite, then the source size will be scaled up or down to the +destination size. + Programming Notes +Restriction : Sprite scaling should not be enabled with the RGB XR_BIAS 10:10:10 format, RGB 64-bit format, or any +YUV format containing extended range data. + Source and destination sizes must be 3x3 (3x6 when interlacing) or greater when scaling is enabled. + Upscaling of any amount is allowed. + Downscaling less than 2X (source/destination) is allowed. + Downscaling greater than or equal to 2X is not supported. + Downscaling increases memory bandwidth requirements. + Horizontal downscaling limits the maximum pixel rate. See the section on Display Pixel Rate Limitations. +DWord Bit Description +0 31 Scaling Enable + Format: Enable + This field enables the scaling function. + Source width can be no more than 4k bytes with scaling enabled. + For best picture quality, disable when scaling is not required. + Value Name + 0b Disable [Default] + 1b Enable + + + Programming Notes + Restriction : Scaling should not be left enabled when sprite is disabled. + Workaround (WaCxSRDisabledForSpriteScaling) : Low Power watermarks must be disabled for at + least one frame before enabling sprite scaling, and kept disabled until sprite scaling is disabled. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 135 + SPR_SCALE + + Suggested sequence: + 0. Driver notified that scaling will be enabled + 1. Disable WM_LP (write WM_LP3 bit 31=0 first, then WM_LP2, then WM_LP1) + 2. Wait for vertical blank + 3. Enable scaling + .... + 4. Driver notified that scaling will not be enabled + 5. Disable scaling + 6. Restore WM_LP (restore WM_LP1 first, then WM_LP2, then WM_LP3) + 30:29 Filter Control + Filter selection + Value Name Description + 00b Medium Medium Filtering + 01b Enhancing Edge Enhancing Filtering + 10b Softening Edge Softening Filtering + 11b Reserved Reserved + 28 Field Offset + Select the vertical offset of the filtered data. Software is responsible for updating this to match the + surface data. + Value Name Description + 0b 0 [Default] Vertical initial phase of 0 + 1b 0.5 Vertical initial phase of 0.5 + 27 Field Enable + Enable adjustment of the vertical offset of the filtered data. + Value Name Description + 0b Disable [Default] Off (Vertical initial phase is 1/2 the scale factor) + 1b Enable On (Vertical initial phase is selected by the Field Offset bit) + 26:16 Source Width + The horizontal size of the source image to be scaled in pixels. Max number of pixels is 2048; minimum + is 3. The value programmed is one less than the number of pixels. Source width can be no more than + 4k bytes, counting from a 64 byte alignment. The sprite width (actual width, not the width minus one + value) is limited to even values when YUV 4:2:2 source pixel format is used. + 15:11 Reserved + Format: MBZ + 10:0 Source Height + The vertical size of the source image to be scaled in lines. If the source is a field, this is the number of + lines in the field. Max number of lines is 2048; minimum is 3 (6 when interlacing). The value + programmed is one less than the number of lines. The height must be even when sprite scaling is + enabled and the pipe has set planes to interlaced fetch. That means the programmed value must be + odd. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 136 + 5.4.12 SPR_GAMC-Sprite Gamma Correction + + SPR_GAMC REFERENCE POINT FORMAT +Project: +Size (in bits): 30 +Default Value: 0x00000000 +This format is used to determine the first 16 reference points (points 0 to 15) for sprite gamma correction. + The values are represented in an unsigned 0.10 format with 0 integer and 10 fractional bits. + See SPR_GAMC for sprite gamma programming information. +DWord Bit Description +0 29:20 Red Gamma Reference Point + Format: U0.10 + This value specifies a reference point that is used for the red color channel sprite gamma correction. + + 19:10 Green Gamma Reference Point + Format: U0.10 + This value specifies a reference point that is used for the green color channel sprite gamma correction. + + 9:0 Blue Gamma Reference Point + Format: U0.10 + This value specifies a reference point that is used for the blue color channel sprite gamma correction. + + + + SPR_GAMC +Register MMIO: 0/2/0 +Space: +Project: +Default 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000 +Access: R/W +Size (in 16x32 +bits): +Address: 70400h-7043Fh +Name: Sprite A Gamma Correction +ShortName: SPR_GAMC_[0-15]_A +Address: 71400h-7143Fh +Name: Sprite B Gamma Correction +ShortName: SPR_GAMC_[0-15]_B +Address: 72400h-7243Fh +Name: Sprite C Gamma Correction +ShortName: SPR_GAMC_[0-15]_C +These registers are used to determine the characteristics of the gamma correction for the sprite pixel data pre- +blending. Additional gamma correction can be done in the display pipe gamma if desired. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 137 + SPR_GAMC + The gamma correction curve is represented by specifying a set of gamma entry reference points spaced equally +along the curve for values between -1 and 1. For extended values there is an extended gamma entry reference point +at the maximum alowed input value. + +All input values are clamped to the greater than -3.0 and less than 3.0 range before the gamma calculation. + + * For input values greater than or equal to 0 and less than 1.0, the input value is used to linearly interpolate between +two adjacent points of the first 17 gamma entries to create the result value. The first 16 entries are stored in +SPR_GAMC with 10 bits per color in a 0.10 format with 0 integer and 10 fractional. The 17th entry is stored in the +SPR_GAMC16 register with 11 bits per color in a 1.10 format with 1 integer and 10 fractional bits. + + * For input values greater than or equal to 1.0 and less than 3.0, the input value is used to linearly interpolate +between the 17th and 18th gamma entries to create the result value. The 18th entry is stored in the SPR_GAMC17 +register with 12 bits per color in a 2.10 format with 2 integer and 10 fractional bits. + + * For negative input values, gamma is mirrored along the X-axis, giving the same result as positive input values, +except for a negative sign. When gamma input may be negative, the first gamma point should be programmed to a +value of 0.0 in order to have a symmetric mirroring. + + To program the gamma correction entries, calculate the desired gamma curve for inputs from 0 to 3.0. The curve +must be flat or increasing, never decreasing. For inputs of 0 to 1.0, multiply the input value by 16 to find the gamma +entry number, then store the desired gamma result in that entry. For inputs greater than 1.0 and less than or equal to +3.0, store the result for an input of 3.0 in the 18th gamma entry (SRP_GAMC17). + + The gamma correction registers should only be updated when the sprite is off, otherwise screen artifacts may show +temporarily. + Gamma correction can be enabled or disabled through the sprite control register. + See Pipe Gamma for an example gamma curve diagram. + DWord Bit Description +0 31:30 Reserved + Format: MBZ + 29:0 GAMC0 + Default Value: 00000000h + Format: SPR_GAMC REFERENCE POINT FORMAT +1 31:30 Reserved + Format: MBZ + 29:0 GAMC1 + Default Value: 04010040h + Format: SPR_GAMC REFERENCE POINT FORMAT +2 31:30 Reserved + Format: MBZ + 29:0 GAMC2 + Default Value: 08020080h + Format: SPR_GAMC REFERENCE POINT FORMAT +3 31:30 Reserved + Format: MBZ + 29:0 GAMC3 + Default Value: 0C0300C0h + Format: SPR_GAMC REFERENCE POINT FORMAT +4 31:30 Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 138 + SPR_GAMC + Format: MBZ + 29:0 GAMC4 + Default Value: 10040100h + Format: SPR_GAMC REFERENCE POINT FORMAT +5 31:30 Reserved + Format: MBZ + 29:0 GAMC5 + Default Value: 14050140h + Format: SPR_GAMC REFERENCE POINT FORMAT +6 31:30 Reserved + Format: MBZ + 29:0 GAMC6 + Default Value: 18060180h + Format: SPR_GAMC REFERENCE POINT FORMAT +7 31:30 Reserved + Format: MBZ + 29:0 GAMC7 + Default Value: 1C0701C0h + Format: SPR_GAMC REFERENCE POINT FORMAT +8 31:30 Reserved + Format: MBZ + 29:0 GAMC8 + Default Value: 20080200h + Format: SPR_GAMC REFERENCE POINT FORMAT +9 31:30 Reserved + Format: MBZ + 29:0 GAMC9 + Default Value: 24090240h + Format: SPR_GAMC REFERENCE POINT FORMAT +10 31:30 Reserved + Format: MBZ + 29:0 GAMC10 + Default Value: 280A0280h + Format: SPR_GAMC REFERENCE POINT FORMAT +11 31:30 Reserved + Format: MBZ + 29:0 GAMC11 + Default Value: 2C0B02C0h + Format: SPR_GAMC REFERENCE POINT FORMAT +12 31:30 Reserved + Format: MBZ + 29:0 GAMC12 + Default Value: 300C0300h + Format: SPR_GAMC REFERENCE POINT FORMAT +13 31:30 Reserved + Format: MBZ + 29:0 GAMC13 + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 139 + SPR_GAMC + Default Value: 340D0340h + Format: SPR_GAMC REFERENCE POINT FORMAT +14 31:30 Reserved + Format: MBZ + 29:0 GAMC14 + Default Value: 380E0380h + Format: SPR_GAMC REFERENCE POINT FORMAT +15 31:30 Reserved + Format: MBZ + 29:0 GAMC15 + Default Value: 3C0F03C0h + Format: SPR_GAMC REFERENCE POINT FORMAT + + + + +5.4.13 SPR_GAMC16-Sprite Gamma Correction Point 16 + + SPR_GAMC16 +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000400, 0x00000400, 0x00000400 +Access: R/W +Size (in bits): 3x32 +Address: 70440h-7044Bh +Name: Sprite A Gamma Correction Point 16 +ShortName: SPR_GAMC16_[0-2]_A +Address: 71440h-7144Bh +Name: Sprite B Gamma Correction Point 16 +ShortName: SPR_GAMC16_[0-2]_B +Address: 72440h-7244Bh +Name: Sprite C Gamma Correction Point 16 +ShortName: SPR_GAMC16_[0-2]_C +These registers are used to determine the 17th reference point (point 16 when counting from 0) for sprite gamma +correction. + The values are represented in an unsigned 1.10 format with 1 integer and 10 fractional bits. + See SPR_GAMC for sprite gamma programming information. + Programming Notes +Restriction : The value should always be programmed to be less than or equal to 1.0. +DWord Bit Description +0 31:11 Reserved + Format: MBZ + 10:0 GAMC16R + Default Value: 00000400h + Format: U1.10 + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 140 + SPR_GAMC16 + This value specifies the 17th reference point that is used for the red color channel sprite gamma + correction. + +1 31:11 Reserved + Format: MBZ + 10:0 GAMC16G + Default Value: 00000400h + Format: U1.10 + This value specifies the 17th reference point that is used for the green color channel sprite gamma + correction. + +2 31:11 Reserved + Format: MBZ + 10:0 GAMC16B + Default Value: 00000400h + Format: U1.10 + This value specifies the 17th reference point that is used for the blue color channel sprite gamma + correction. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 141 + 5.4.14 SPR_GAMC17-Sprite Gamma Correction Point 17 + + SPR_GAMC17 +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000C00, 0x00000C00, 0x00000C00 +Access: R/W +Size (in bits): 3x32 +Address: 7044Ch-70457h +Name: Sprite A Gamma Correction Point 17 +ShortName: SPR_GAMC17_[0-2]_A +Address: 7144Ch-71457h +Name: Sprite B Gamma Correction Point 17 +ShortName: SPR_GAMC17_[0-2]_B +Address: 7244Ch-72457h +Name: Sprite C Gamma Correction Point 17 +ShortName: SPR_GAMC17_[0-2]_C +These registers are used to determine the 18th reference point (point 17 when counting from 0) for sprite gamma +correction. + The values are represented in an unsigned 2.10 format with 2 integer and 10 fractional bits. + See SPR_GAMC for sprite gamma programming information. + Programming Notes +Restriction : The value should always be programmed to be less than or equal to 3.0. +DWord Bit Description +0 31:12 Reserved + Format: MBZ + 11:0 GAMC17R + Default Value: 00000C00h + Format: U2.10 + This value specifies the 18th reference point that is used for the red color channel sprite gamma + correction. +1 31:12 Reserved + Format: MBZ + 11:0 GAMC17G + Default Value: 00000C00h + Format: U2.10 + This value specifies the 18th reference point that is used for the green color channel sprite gamma + correction. + +2 31:12 Reserved + Format: MBZ + 11:0 GAMC17B + Default Value: 00000C00h + Format: U2.10 + This value specifies the 18th reference point that is used for the blue color channel sprite gamma + correction. + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 142 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V3 Pt 3 – 05 12 5/31/2012 143 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol3_part4.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol3_part4.txt new file mode 100644 index 0000000..bf92c56 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol3_part4.txt @@ -0,0 +1,5277 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 3 Part 4: South Display Engine +Registers +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 + Contents +1. Introduction............................................................................................................................................ 5 + 1.1 Display Mode Set Sequence ................................................................................................................ 5 + 1.1.1 Simultaneous Display Capabilities on a Single Display Pipe/Transcoder ...................................... 5 + 1.1.2 Terminology .................................................................................................................................... 6 +2. South Display Engine Shared Functions ............................................................................................ 7 + 2.1 South Display Engine Interrupts .......................................................................................................... 7 + 2.1.1 South Display Engine Interrupt Bit Definition ................................................................................. 7 + 2.1.2 ISR — Interrupt Status ................................................................................................................... 9 + 2.1.3 IMR — Interrupt Mask .................................................................................................................... 9 + 2.1.4 IIR — Interrupt Identity ................................................................................................................. 10 + 2.1.5 IER — Interrupt Enable ................................................................................................................ 11 + 2.1.6 SHOTPLUG_CTL — South Hot Plug Control .............................................................................. 11 + 2.1.7 SERR_INT—South Error Interrupts ............................................................................................. 13 + 2.2 GMBUS and GPIO ............................................................................................................................. 14 + 2.2.1 GPIO Pin Usage (By Functions) ................................................................................................... 14 + 2.2.2 GPIO_CTL— GPIO Control.......................................................................................................... 15 + 2.2.3 GMBUS Controller Programming Interface .................................................................................. 18 + 2.2.4 GMBUS0—GMBUS Clock/Port Select ......................................................................................... 19 + 2.2.5 GMBUS1—GMBUS Command/Status ......................................................................................... 20 + 2.2.6 GMBUS2—GMBUS Status .......................................................................................................... 22 + 2.2.7 GMBUS3—GMBUS Data Buffer .................................................................................................. 24 + 2.2.8 GMBUS4—GMBUS Interrupt Mask ............................................................................................. 25 + 2.2.9 GMBUS5—GMBUS 2 Byte Index................................................................................................. 26 + 2.3 Display Clock Control ......................................................................................................................... 26 + 2.3.1 DPLL_CTL—DPLL Control........................................................................................................... 27 + 2.3.2 DPLL_FP0—DPLL Divisor 0 ........................................................................................................ 30 + 2.3.3 DPLL_FP1—DPLL Divisor 1 ........................................................................................................ 31 + 2.3.4 DREF_CTL — Display Reference Clock Control ......................................................................... 32 + 2.3.5 RAWCLK_FREQ—Rawclk Frequency ......................................................................................... 35 + 2.3.6 SSC4_PARMS – SSC4 Parameters ............................................................................................ 35 + 2.3.7 DPLL_SEL— DPLL Select ........................................................................................................... 37 + 2.4 Panel Power Sequencing ................................................................................................................... 38 + 2.4.1 PP_STATUS—Panel Power Status ............................................................................................. 38 + 2.4.2 PP_CONTROL—Panel Power Control ........................................................................................ 39 + 2.4.3 PP_ON_DELAYS—Panel Power On Sequencing Delays ........................................................... 41 + 2.4.4 PP_OFF_DELAYS—Panel Power Off Sequencing Delays ......................................................... 42 + 2.4.5 PP_DIVISOR—Panel Power Cycle Delay and Reference Divisor ............................................... 43 + 2.5 Backlight Control ................................................................................................................................ 44 + 2.5.1 SBLC_BLM_CTL1—South BLM PWM Control 1 ......................................................................... 44 + 2.5.2 SBLC_BLM_CTL2—South BLM PWM Control 2 ......................................................................... 45 +3. South Display Engine Transcoder and Port Controls ..................................................................... 46 + 3.1 Transcoder Timing ............................................................................................................................. 46 + 3.1.1 HTOTAL—Horizontal Total........................................................................................................... 46 + 3.1.2 HBLANK—Horizontal Blank ......................................................................................................... 47 + 3.1.3 HSYNC—Horizontal Sync ............................................................................................................ 48 + 3.1.4 VTOTAL—Vertical Total ............................................................................................................... 49 + 3.1.5 VBLANK—Vertical Blank .............................................................................................................. 50 + 3.1.6 VSYNC—Vertical Sync ................................................................................................................. 51 + 3.1.7 VSYNCSHIFT— Vertical Sync Shift ............................................................................................. 52 + 3.2 Transcoder M/N Values ..................................................................................................................... 52 + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 3 + 3.2.1 DATAM— Data M Value ............................................................................................................... 53 + 3.2.2 DATAN— Data N Value ............................................................................................................... 54 + 3.2.3 LINKM— Link M Value ................................................................................................................. 55 + 3.2.4 LINKN— Link N Value .................................................................................................................. 56 + 3.3 Transcoder Video DIP ........................................................................................................................ 57 + 3.3.1 VIDEO_DIP_CTL—Video DIP Control ......................................................................................... 57 + 3.3.2 VIDEO_DIP_DATA–Video Data Island Packet Data ................................................................... 60 + 3.3.3 VIDEO_DIP_GCP–Video Data Island Payload GCP ................................................................... 62 + 3.4 Transcoder DisplayPort Control ......................................................................................................... 63 + 3.4.1 TRANS_DP_CTL—Transcoder DisplayPort Control.................................................................... 63 + 3.5 Analog Port CRT DAC ....................................................................................................................... 65 + 3.5.1 DAC_CTL—Analog Port CRT DAC Control ................................................................................. 65 + 3.6 HDMI Port .......................................................................................................................................... 67 + 3.6.1 HDMI_CTL—HDMI Port Control................................................................................................... 67 + 3.6.2 HDMI_BUF_CTL—HDMI Buffer Control ...................................................................................... 70 + 3.7 LVDS Port .......................................................................................................................................... 72 + 3.7.1 LVDS_CTL—LVDS Port Control .................................................................................................. 72 + 3.8 DisplayPort ......................................................................................................................................... 75 + 3.8.1 DP_CTL—DisplayPort Control ..................................................................................................... 75 + 3.8.2 DP_AUX_CTL—DisplayPort AUX Channel Control ..................................................................... 78 + 3.8.3 DP_AUX_DATA—DisplayPort AUX Channel Data ...................................................................... 80 + 3.8.4 DP_BUFTRANS—DisplayPort Buffer Translation ........................................................................ 81 +4. South Display Engine Audio .............................................................................................................. 85 + 4.1 Audio Programming Sequence .......................................................................................................... 85 + 4.2 Audio Configuration............................................................................................................................ 87 + 4.2.1 AUD_CONFIG—Audio Configuration ........................................................................................... 87 + 4.2.2 AUD_CTS_ENABLE – Audio CTS Programming Enable ............................................................ 88 + 4.2.3 AUD_MISC_CTRL—Audio MISC Control .................................................................................... 89 + 4.2.4 AUD_VID_DID—Audio Vendor ID / Device ID ............................................................................. 90 + 4.2.5 AUD_RID—Audio Revision ID...................................................................................................... 90 + 4.2.6 AUD_PWRST—Audio Power State ............................................................................................. 91 + 4.2.7 AUD_PINW_CONNLNG_LIST—Audio Connection List .............................................................. 93 + 4.2.8 AUD_PINW_CONNLNG_SEL—Audio Connection Select .......................................................... 94 + 4.2.9 AUD_CNTL_ST—Audio Control State ......................................................................................... 94 + 4.2.10 AUD_CNTRL_ST2— Audio Control State 2 .............................................................................. 96 + 4.2.11 AUD_HDMIW_HDMIEDID—Audio HDMI Data EDID Block ...................................................... 97 + 4.2.12 AUD_HDMIW_INFOFR—Audio Widget Data Island Packet ..................................................... 98 +5. South Display Engine Transcoder and FDI Control......................................................................... 99 + 5.1 Transcoder Control ............................................................................................................................ 99 + 5.1.1 TRANS_CONF—Transcoder Configuration ................................................................................. 99 + 5.2 FDI Receiver .................................................................................................................................... 100 + 5.2.1 FDI_RX_CTL— FDI Rx Control.................................................................................................. 100 + 5.2.2 FDI_RX_MISC— FDI Rx Miscellaneous .................................................................................... 104 + 5.2.3 FDI_RX_IMR — FDI Rx Interrupt Mask ..................................................................................... 105 + 5.2.4 FDI_RX_IIR — FDI Rx Interrupt Identity .................................................................................... 107 + 5.2.5 FDI_RX_TUSIZE— FDI Rx Transfer Unit Size .......................................................................... 108 + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 4 + 1. Introduction +This chapter contains the register descriptions for the display portion of a family of graphics devices. +These registers vary by devices within the family of devices, so special attention needs to be paid to +which devices use which registers and register fields. +Different devices within the family may add, modify, or delete registers or register fields relative to another +device in the same family based on the supported functions of that device. +This chapter applies to both Cougarpoint (CPT) and Pantherpoint (PPT) display. Unless specifically +indicated, all references to Cougarpoint (CPT) will apply to both Cougarpoint (CPT) and Pantherpoint +(PPT). + + +1.1 Display Mode Set Sequence +See the North Display Engine Registers document. + + +1.1.1 Simultaneous Display Capabilities on a Single Display + Pipe/Transcoder + Embedded DisplayPort (on Integrated + CPU) LVDS HDMI/DVI DisplayPort CRT +Embedded DisplayPort (on + No (4) No (7) No (7) No (7) No (7) +CPU) +Integrated LVDS Some (3, + No (4) No (2, 3, 8) No (2, 8, 9) + 8) +HDMI/DVI Some (5, + No (6, No (6, 8, 9) + 8) + 8,10) + +DisplayPort + No (3, 6, 8, No (5, 8, + 9) 9) +CRT + No (4) + +Shading: Rose = Does not work, White = Some cases work, Green = Works, Gray = Redundant (see +other half of table) +2) No internal LVDS HDMI/DVI, or DisplayPort on same pipe/transcoder. +3) No SSC on CRT or HDMI/DVI. DisplayPort optionally has SSC. +4) Only 1 integrated LVDS, and 1 CRT on PCH. Only 1 embedded DisplayPort on CPU. +5) Only works if DisplayPort/HDMI/DVI is in 24bpp mode. +6) DisplayPort/HDMI/DVI ports are multiplexed on the same pins, only works if ports are on different pins. +7) Embedded DisplayPort is on the CPU; can not share the link. +8) Dithering, range correction, and gamma are done in the CPU; the display with lower bpp can truncate +or the display with higher bpp can lose bits. One of the displays dictates range and gamma. +9) No DisplayPort allowed with other port on the same pipe/transcoder. + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 + 10) No HDMI allowed with another HDMI on the same transcoder. + + +1.1.2 Terminology + Description Software Use Should be implemented as +Read/Write, R/W This bit can be read or written. + Don’t assume a value for these bits. Writes are ignored. Reads return zero. + Reserved + Writes have no effect. +Reserved: must Software must always write a zero to Writes are ignored. Reads return zero. Maybe be +be zero, MBZ these bits. This allows new features to connected as Read/Write in future projects. + be added using these bits that will be + disabled when using old software and + as the default case. +Reserved: PBC, Software must write the original value +software must back to this bit. This allows new +preserve contents features to be added using these bits. +Read Only This bit is read only. The read value is According to each specific bit. The bit value is determined + determined by hardware. Writes to this by hardware and not affected by register writes to the + bit have no effect. actual bit. +Read/Clear, This bit can be read. Writes to it with a Hardware events cause the bit to be set and the bit will be +Read/Write Clear one cause the bit to clear. cleared on a write operation where the corresponding bit + has a one for a value. +Double Buffered Two stages of registers used. First stage is written into + Write when desired. Read gives the + and used for readback (unless specified otherwise). First + unbuffered value (written value) unless + stage value is transferred into second stage at the update + specified otherwise. Written values will + update to take effect after a certain point. Second stage value is used to control hardware. + point. Arm/disarm flag for specific arming sequences. + + Some have a specific arming + sequence where a write to another + register is required before the update + can take place. This is used to ensure + atomic updates of several registers. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 6 + 2. South Display Engine Shared + Functions +2.1 South Display Engine Interrupts + +2.1.1 South Display Engine Interrupt Bit Definition + + South Display Engine Interrupt Bit Definition +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Size (in bits): 32 +South Display Engine (SDE) interrupt bits come from events within the south display engine. + The SDE_IIR bits are ORed together to generate the South/PCH Display Interrupt Event which will appear in the +North Display Engine Interrupt Control Registers. + The South Display Engine Interrupt Control Registers all share the same bit definitions from this table. + Programming Notes +Only the rising edge of the PCH Display interrupt will cause the North Display IIR (DEIIR) PCH Display Interrupt +event bit to be set, so all PCH Display Interrupts, including back to back interrupts, must be cleared in the SDEIIR +before a new PCH Display Interrupt can cause the DEIIR to be set. + DWord Bit Description +0 31 Audio Power State change Port D + This is an active high pulse when there is a power state change for audio for port D. + 30 Audio Power State change Port C + This is an active high pulse when there is a power state change for audio for port C. + 29 Audio Power State change Port B + This is an active high pulse when there is a power state change for audio for port B. + 28 Reserved + 27 AUX Channel D + This is an active high pulse on the AUX D done event + 26 AUX Channel C + This is an active high pulse on the AUX C done event + 25 AUX Channel B + This is an active high pulse on the AUX B done event + 24 Reserved + 23 DisplayPort/HDMI/DVI D Hotplug + The ISR is an active high level representing the Digital Port D hotplug line when the Digital Port D + hotplug detect input is enabled. + The unmasked IIR is set on either a short or long pulse detection status in the Digital Port Hot Plug + Control Register. + 22 DisplayPort/HDMI/DVI C Hotplug + The ISR is an active high level representing the Digital Port C hotplug line when the Digital Port C + hotplug detect input is enabled. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 7 + South Display Engine Interrupt Bit Definition + The unmasked IIR is set on either a short or long pulse detection status in the Digital Port Hot Plug + Control Register. + 21 DisplayPort/HDMI/DVI B Hotplug + The ISR is an active high level representing the Digital Port B hotplug line when the Digital Port B + hotplug detect input is enabled. + The unmasked IIR is set on either a short or long pulse detection status in the Digital Port Hot Plug + Control Register. + 20 Reserved + 19 CRT Hotplug + The ISR is an active high level representing the ORed together blue and green channel detection + status as of the last detection cycle. + The unmasked IIR is set on the rising or falling edges of the blue or green channel detection status + in the Analog Port CRT DAC Control Register. + 17 Gmbus + This is an active high pulse when any of the events unmasked events in GMBUS4 Interrupt Mask + register occur. + 16 South Error Interrupts Combined + This is an active high level while any of the South Error Interrupt bits are set. + 15:11 Reserved + 9 Audio CP Change Transcoder C + This is an active high pulse when there is a change in the protection request from audio azalia verb + programming for transcoder C. + 8 FDI RX Interrupts Combined C + This is an active high level while any of the FDI_RX_ISR bits are set for transcoder C + 7 Reserved + 5 Audio CP Change Transcoder B + This is an active high pulse when there is a change in the protection request from audio azalia verb + programming for transcoder B. + 4 FDI RX Interrupts Combined B + This is an active high level while any of the FDI_RX_ISR bits are set for transcoder B + 3 Reserved + 1 Audio CP Change Transcoder A + This is an active high pulse when there is a change in the protection request from audio azalia verb + programming for transcoder A. + 0 FDI RX Interrupts Combined A + This is an active high level while any of the FDI_RX_ISR bits are set for transcoder A + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 8 + 2.1.2 ISR — Interrupt Status + + ISR +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: C4000h-C4003h +Name: South DE Interrupt Status +ShortName: SDE_ISR +See the interrupt bit definition table to find the source event for each interrupt bit. +DWord Bit Description +0 31:0 Interrupt Status Bits + This field contains the non-persistent values of all interrupt status bits. + The IMR register selects which of these interrupt conditions are reported in the persistent IIR. + Value Name Description + 0b Condition Doesn’t exist Interrupt Condition currently does not exist + 1b Condition Exists Interrupt Condition currently exists + + + Programming Notes + Some inputs to this register are short pulses; therefore software should not expect to use this register to + sample these conditions. + + + + +2.1.3 IMR — Interrupt Mask + + IMR +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C4004h-C4007h +Name: South DE Interrupt Mask +ShortName: SDE_IMR +See the interrupt bit definition table to find the source event for each interrupt bit. +DWord Bit Description +0 31:0 Interrupt Mask Bits + This field contains a bit mask which selects which interrupt bits from the ISR are reported in the IIR. + Value Name Description + 0b Not Masked Not Masked – will be reported in the IIR + 1b Masked Masked – will not be reported in the IIR + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 9 + 2.1.4 IIR — Interrupt Identity + + IIR +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/WC +Size (in bits): 32 +Address: C4008h-C400Bh +Name: South DE Interrupt Identity +ShortName: SDE_IIR +See the interrupt bit definition table to find the source event for each interrupt bit. +DWord Bit Description +0 31:0 Interrupt Identity Bits + This field holds the persistent values of the interrupt bits from the ISR which are unmasked by the IMR. + If enabled by the IER, bits set in this register will generate a PCH display interrupt. + Bits set in this register will remain set (persist) until the interrupt condition is cleared by writing a ‘1’ to + the appropriate bits. + + For each bit, the IIR can store a second pending interrupt if two or more of the same interrupt conditions + occur before the first condition is cleared, then upon clearing the first interrupt, the IIR bit and PCH + display interrupt will momentarily go low, then return high to indicate there is another interrupt pending. + Value Name Description + 0b Condition Not Interrupt Condition Not Detected + Detected + 1b Condition Detected Interrupt Condition Detected (may or may not have generated a PCH + display interrupt) + + + Programming Notes + Only the rising edge of the PCH Display interrupt will cause the North Display IIR (DEIIR) PCH Display + Interrupt event bit to be set, so all PCH Display Interrupts, including back to back interrupts, must be + cleared here before a new PCH Display Interrupt can cause the DEIIR to be set. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 10 + 2.1.5 IER — Interrupt Enable + + IER +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C400Ch-C400Fh +Name: South DE Interrupt Enable +ShortName: SDE_IER +See the interrupt bit definition table to find the source event for each interrupt bit. +DWord Bit Description +0 31:0 Interrupt Enable Bits + The bits in this register enable a PCH display interrupt to be generated whenever the corresponding bit + in the IIR becomes set. + A disabled interrupt will still appear in the IIR register to allow polling of interrupt sources. + Value Name Description + 0b Disable Disable + 1b Enable Enable + + + + +2.1.6 SHOTPLUG_CTL — South Hot Plug Control + + SHOTPLUG_CTL +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C4030h-C4033h +Name: South Hot Plug control +ShortName: SHOTPLUG_CTL +DWord Bit Description +0 31:21 Reserved + 20 DP D HPD Input Enable + Controls the state of the HPD buffer for the digital port D. The buffer state is independent of whether + the port is enabled or not. + Value Name Description + 0b Disable Buffer disabled + 1b Enable Buffer enabled. Hot plugs bit reflect the electrical state of the HPD pin + 19:18 DP D HPD Short Pulse Duration + These bits define the duration of the pulse defined as a short pulse for the digital port D. + Value Name Description + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 11 + SHOTPLUG_CTL + 00b 2ms 2mS + 01b 4.5ms 4.5mS + 10b 6ms 6mS + 11b 100ms 100mS + 17:16 DP D HPD Status + This reflects hot plug detect status on the digital port D. + Write a one to these bits to clear the status. + These bits are used for either monitor hotplug/unplug or for notification of a sink event. + When either a long or short pulse is detected, one of these bits will set. + These bits are ORed together to go to the main ISR hotplug register bit. + Value Name Description + 00b No Detect [Default] Digital port hot plug event not detected + X1b Short Detect Digital port short pulse hot plug event detected + 1Xb Long Detect Digital port long pulse hot plug event detected + 15:13 Reserved + 12 DP C HPD Input Enable + Controls the state of the HPD buffer for the digital port C. The buffer state is independent of whether + the port is enabled or not. + Value Name Description + 0b Disable Buffer disabled + 1b Enable Buffer enabled. Hot plugs bit reflect the electrical state of the HPD pin + 11:10 DP C HPD Short Pulse Duration + These bits define the duration of the pulse defined as a short pulse for the digital port C. + Value Name Description + 00b 2ms 2mS + 01b 4.5ms 4.5mS + 10b 6ms 6mS + 11b 100ms 100mS + 9:8 DP C HPD Status + This reflects hot plug detect status on the digital port C. + Write a one to these bits to clear the status. + These bits are used for either monitor hotplug/unplug or for notification of a sink event. + When either a long or short pulse is detected, one of these bits will set. + These bits are ORed together to go to the main ISR hotplug register bit. + Value Name Description + 00b No Detect [Default] Digital port hot plug event not detected + X1b Short Detect Digital port short pulse hot plug event detected + 1Xb Long Detect Digital port long pulse hot plug event detected + 7:5 Reserved + 4 DP B HPD Input Enable + Controls the state of the HPD buffer for the digital port B. The buffer state is independent of whether + the port is enabled or not. + Value Name Description + 0b Disable Buffer disabled + 1b Enable Buffer enabled. Hot plugs bit reflect the electrical state of the HPD pin + 3:2 DP B HPD Short Pulse Duration + These bits define the duration of the pulse defined as a short pulse for the digital port B. + Value Name Description + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 12 + SHOTPLUG_CTL + 00b 2ms 2mS + 01b 4.5ms 4.5mS + 10b 6ms 6mS + 11b 100ms 100mS + 1:0 DP B HPD Status + This reflects hot plug detect status on the digital port B. + Write a one to these bits to clear the status. + These bits are used for either monitor hotplug/unplug or for notification of a sink event. + When either a long or short pulse is detected, one of these bits will set. + These bits are ORed together to go to the main ISR hotplug register bit. + Value Name Description + 00b No Detect [Default] Digital port hot plug event not detected + X1b Short Detect Digital port short pulse hot plug event detected + 1Xb Long Detect Digital port long pulse hot plug event detected + + + + +2.1.7 SERR_INT—South Error Interrupts + + SERR_INT +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/WC +Size (in bits): 32 +Address: C4040h-C4043h +Name: South Error Interrupts +ShortName: SERR_INT +These are sticky bits, cleared by writing 1 to them. + All the South Error Interrupt bits are ORed together to go to the South Display Engine ISR Error Interrupts Combined +bit. + DWord Bit Description +0 31 South Poison Status + This bit is set upon receiving the poison message. + Value Name Description + 0b Not Detected Event not detected + 1b Detected Event detected + 30:7 Reserved + 6 Transcoder FIFO Underrun C + This bit is set when the transcoder FIFO underrun signal is high. + Value Name Description + 0b Not Detected Event not detected + 1b Detected Event detected + 5:4 Reserved + 3 Transcoder FIFO Underrun B + This bit is set when the transcoder FIFO underrun signal is high. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 13 + SERR_INT + Value Name Description + 0b Not Detected Event not detected + 1b Detected Event detected + 2:1 Reserved + 0 Transcoder FIFO Underrun A + This bit is set when the transcoder FIFO underrun signal is high. + Value Name Description + 0b Not Detected Event not detected + 1b Detected Event detected + + + +2.2 GMBUS and GPIO + +2.2.1 GPIO Pin Usage (By Functions) +GPIO pins allow the support of simple query and control functions such as DDC and I 2C interface +protocols. GPIO pins exist in pairs (for the most part) and provide a mechanism to control external +devices through a register programming interface. GPIO pins can be set to a level or the value of the pin +can be read. This allows for a “bit banging” version of an I2C interface to be implemented. An additional +function of using the GMBUS engine to run the I2C protocols is also allowed. Refer to the Philips I2C- +BUS SPECIFICATION version 2.1 for a description of the I2C bus and protocol. +Some of the GPIO pins will be muxed with other functions and are only available when the other function +is not being used. The following subsections describe the GPIO pin to register mapping. OEMs have the +ability to remap these functions onto other pins as long as the hardware limitations are observed. + + Pin Use I2C + (Name) GMBUS Internal +Port Use Pullup Device Description +5 HDMI/DPD Yes No No (weak Yes All DDC for HDMI connection via the integrated + CTLDATA pulldown HDMI port D + on reset) + HDMI/DPD No Yes + CTLCLK +4 + +3 HDMI/DPC Yes No No (weak Yes All DDC for HDMI connection via the integrated + CTLDATA pulldown HDMI port C. + on reset) + HDMI/DPC No Yes + CTLCLK +2 Yes No No Yes All DDC for Digital Display connection via the + LVDS DDC + integrated LVDS + Data + (DDCLDATA) + LVDS DDC Yes + Clock + (DDCLCLK) +1 I2C Data Yes No No Yes All For control of SSC clock generator devices on + (LCLKCTRLB) motherboard. Support can be optionally I2C or + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 14 + Pin Use I2C + (Name) GMBUS Internal +Port Use Pullup Device Description + control level. + I2C Clock Yes + (LCLKCTRLA) +0 Yes No No Yes All DDC for Analog monitor (VGA) connection. + DAC DDC + This cannot be shared with other DDC or I2C + Data + pairs due to legacy monitor issues. + (DDCADATA) + Yes + DAC DDC + Clock + (DDCACLK) + + + +2.2.2 GPIO_CTL— GPIO Control + + GPIO Control Register Format + +Default Value: 0x00000808 +DWord Bit Description +0 31:13 Reserved + Format: MBZ + 12 GPIO Data In + Default Value: Ub Undefined (read only depends on I/O pin) + Access: RO + This is the value that is sampled on the GPIO_Data pin as an input. + This input is synchronized to the Core Clock domain. + Because the default setting is this buffer is an input, this bit is undefined at reset. + + 11 GPIO Data Value + Default Value: 1b One + Access: R/W + This is the value that should be place on the GPIO Data pin as an output. + This value is only written into the register if GPIO DATA MASK is also asserted. + The value will appear on the pin if this data value is actually written to this register and the GPIO Data + DIRECTION VALUE contains a value that will configure the pin as an output. + TThe hardware drives a default of ‘1’ since the I2C interface defaults to a ‘1’(this mimics the I2C + external pull-ups on the bus). + + 10 GPIO Data Mask + Access: WO + This is a mask bit to determine whether the GPIO DATA VALUE bit should be written into the register. + This value is not stored and when read returns 0. + Value Name Description + 0b No Write Do NOT write GPIO Data Value bit + 1b Write Write GPIO Data Value bit. + 9 GPIO Data Direction Value + Access: R/W + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 15 + GPIO Control Register Format + This is the value that should be used to define the output enable of the GPIO Data pin. + This value is only written into the register if GPIO Data DIRECTION MASK is also asserted. + The value that will appear on the pin is defined by what is in the register for the GPIO DATA VALUE + bit. + Value Name Description + 0b Input Pin is configured as an input + 1b Output Pin is configured as an output + 8 GPIO Data Direction Mask + Access: WO + This is a mask bit to determine whether the GPIO DIRECTION VALUE bit should be written into the + register. + This value is not stored and when read always returns 0. + Value Name Description + 0b No Write Do NOT write GPIO Data Direction Value bit + 1b Write Write GPIO Data Direction Value bit + 7:5 Reserved + Format: MBZ + 4 GPIO Clock Data In + Default Value: Ub Undefined (read only depends on I/O pin) + Access: RO + This is the value that is sampled on the GPIO Clock pin as an input. + This input is synchronized to the Core Clock domain. + Because the default setting is this buffer is an input, this bit is undefined at reset. + + 3 GPIO Clock Data Value + Default Value: 1b One + Access: R/W + This is the value that should be place on the GPIO Clk pin as an output. + This value is only written into the register if GPIO Clock DATA MASK is also asserted. + The value will appear on the pin if this data value is actually written to this register and the GPIO Clock + DIRECTION VALUE contains a value that will configure the pin as an output. + The hardware drives a default of ‘1’ since the I2C interface defaults to a ‘1’ (this mimics the I2C + external pull-ups on the bus). + + 2 GPIO Clock Data Mask + Access: WO + This is a mask bit to determine whether the GPIO Clock DATA VALUE bit should be written into the + register. + This value is not stored and when read always returns 0. + Value Name Description + 0b No Write Do NOT write GPIO Clock Data Value bit + 1b Write Write GPIO Clock Data Value bit + 1 GPIO Clock Direction Value + Access: R/W + This is the value that should be used to define the output enable of the GPIO Clock pin. + This value is only written into the register if GPIO Clock DIRECTION MASK is also asserted. + The value that will appear on the pin is defined by what is in the register for the GPIO Clock DATA + VALUE bit. + Value Name Description + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 16 + GPIO Control Register Format + 0b Input Pin is configured as an input and the output driver is set to tri-state + 1b Output Pin is configured as an output + 0 GPIO Clock Direction Mask + Access: WO + This is a mask bit to determine whether the GPIO Clock DIRECTION VALUE bit should be written into + the register. + This value is not stored and when read returns 0. + Value Name Description + 0b No Update Do NOT update the GPIO Clock Direction Value bit on a write + 1b Update Update the GPIO Clock Direction Value bit. on a write operation to this register + + + + + GPIO_CTL +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000808, 0x00000808, 0x00000808, 0x00000808, 0x00000808, 0x00000808 +Access: R/W +Size (in bits): 6x32 +Address: C5010h-C5027h +Name: GPIO Control +ShortName: GPIO_CTL_[0-5] +These registers define the control of sets of the “general purpose” I/O pins. + Each register controls a pair of pins that can be used for general purpose control, but most are designated for +specific functions according to the requirements of the device and the system that the device is in. + +Each pin of the two pin pair is designated as a clock or data for descriptive purposes. + + See the table at the beginning of this section to determine which pins/registers are supported and their intended +functions. + Board design variations are possible and would affect the usage of these pins. + + The registers that control digital display (HDMI/DVI and DisplayPort) pins should only be utilized if the Port Detected +bit in the related control register is set to 1. + DWord Bit Description +0 31:0 GPIOCTL 0 + Format: GPIO Control Register Format +1 31:0 GPIOCTL 1 + Format: GPIO Control Register Format +2 31:0 GPIOCTL 2 + Format: GPIO Control Register Format +3 31:0 GPIOCTL 3 + Format: GPIO Control Register Format +4 31:0 GPIOCTL 4 + Format: GPIO Control Register Format +5 31:0 GPIOCTL 5 + Format: GPIO Control Register Format + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 17 + 2.2.3 GMBUS Controller Programming Interface +The GMBUS (Graphic Management Bus) can be used to indirectly access/control devices connected to a +GMBUS bus as an alternate to bit-wise programming via software. +The GMBUS interface is I2C compatible. The basic features are listed as follow: + 1. Works as the master of a single master bus. + 2. The bus clock frequency is selectable by software to be 50KHz, 100KHz, 400KHz , and 1MHz + 3. The GMBUS controller can be attached to the selected GPIO pin pairs. + 4. 7 or 10-Bit Slave Address and 8- or 16-bit index. + 5. Hardware byte counter to track the data transmissions/reception + 6. Timing source from core display clock. + 7. There is a double buffered data register and a 9 bit counter to support 0 byte to 256 byte + transfers. + 8. The slave device can cause a stall by pulling down the clock line (Slave Stall), or delay the + slave acknowledge response. + 9. The master controller detects and reports time out conditions for a stall from a slave device or + delayed or missing slave acknowledge. + 10. Interrupt may optionally be generated. + 11. The GMBUS is controlled by a set of memory mapped IO registers. Status is reported through + the GMBUS status register. + 12. The GMBUS controller does not directly support segment pointer addressing as defined by the + Enhanced Display Data Channel standard. Segment pointer addressing for EDDC shall be + supported as follows: + a. Use bit bashing (manual GPIO programming) to complete segment pointer write over + ther target I2C port without terminating in a stop or wait cycle. + b. Terminate bit bashing phase with both I2C lines pulled high by tri-stating the data line + before the clock line. Follow EDDC requirement for response received from slave + device. + c. Initiate GMBUS cycle as required to transfer EDID following normal procedure. +The byte counter register is a read/write register, and in receiving mode, is used to track the data bytes +received. There is a status register to indicate the error condition, data buffer busy, time out, and data +complete acknowledgement. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 18 + 2.2.4 GMBUS0—GMBUS Clock/Port Select + + GMBUS0 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C5100h-C5103h +Name: GMBUS0 Clock/Port Select +ShortName: GMBUS0 +The GMBUS0 register will set the clock rate of the serial bus and the device the controller is connected to. + This register should be set before the first data valid bit is set, because it will be read only at the very first data valid +bit, and not read during the period of the transmission until stop is issued and next first data valid bit is set. + DWord Bit Description +0 31:12 Reserved + 10:8 GMBUS Rate Select + These two bits select the rate that the GMBUS will run at. + It also defines the AC timing parameters used. + It should only be changed when between transfers when the GMBUS is idle. + Value Name Description + 000b 100KHz [Default] 100 KHz + 001b 50KHz 50 KHz + 010b 400KHz 400 KHz + 011b 1MHz 1 MHz + Others Reserved Reserved + 7:3 Reserved + Format: MBZ + 2:0 Pin Pair Select + This field selects a GMBUS pin pair for use in the GMBUS communication. + Use the table above to determine which pin pairs are available for a particular device and the + intended function of that pin pair. + It is not a straight forward mapping of port numbers to pair select numbers. + Value Name Description + 000b None [Default] None (disabled) + 001b LCTRCLK LCTRCLKA, LCTRLCLKB + 010b Analog Mon Dedicated Analog Monitor DDC Pins (DDC1DATA, DDC1CLK) + 011b LVDS Integrated Digital Panel DDC Pins, LVDS + 100b Port C Port C + 101b Port B Port B + 110b Port D Port D + 111b Reserved Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 19 + 2.2.5 GMBUS1—GMBUS Command/Status + + GMBUS1 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W Protect +Size (in bits): 32 +Address: C5104h-C5107h +Name: GMBUS1 Command/Status +ShortName: GMBUS1 +This register lets the software indicate to the GMBUS controller the slave device address, register index, and indicate +when the data write is complete. +When the SW_CLR_INT bit is asserted, all writes to the GMBUS2, GMBUS3, and GMBUS4 registers are discarded. + The GMBUS1 register writes to any other bit except the SW_CLR_INT are also lost. + Reads to these registers always work normally regardless of the state of the SW_CLR_INT bit. +DWord Bit Description +0 31 Software Clear Interrupt + Access: R/W + (SW_CLR_INT) This bit must be clear for normal operation. + Setting the bit then clearing it acts as local reset to the GMBUS controller. + This bit is commonly used by software to clear a BUS_ERROR when a slave device delivers a NACK. + Value Name Description + 0b Clear If this bit is written as a zero when its current state is a one, will clear the HW_RDY + HW_RDY bit and allows register writes to be accepted to the GMBUS registers (Write Protect + Off). + This bit is cleared to zero when an event causes the HW_RDY bit transition to + occur. + 1b Assert Asserted by software after servicing the GMBUS interrupt. + HW_RDY Setting this bit causes the INT status bit to be cleared. + Setting (1) this bit also asserts the HW_RDY bit (until this bit is written with a 0). + When this bit is set, no writes to GMBUS registers will cause the contents to + change with the exception of this bit which can be written. + 30 Software Ready + (SW_RDY) Data handshake bit used in conjunction with HW_RDY bit. + Value Name Description + 0b De-Assert De-asserted via the assertion event for HW_RDY bit + 1b SW Assert When asserted by software, results in de-assertion of HW_RDY bit + 29 Enable Timeout + (ENT) Enables timeout for slave response. + When this bit is enabled and the slave device response has exceeded the timeout period, the GMBUS + Slave Stall Timeout Error interrupt bit is set. + Value Name Description + 0b Disable Disable timeout counter + 1b Enable Enable timeout counter + 28 Reserved + 27:25 Bus Cycle Select + GMBUS cycle will always consist of a START followed by Slave Address, followed by an optional read + or write data phase. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 20 + GMBUS1 + A read cycle with an index will consist of a START followed by a Slave Address a WRITE indication + and the INDEX and then a RESTART with a Slave Address and an optional read data phase. + The GMBUS cycle will terminate either with a STOP or by entering a wait state. + The WAIT state is exited by generating a STOP or by starting another GMBUS cycle. + This can only cause a STOP to be generated if a GMBUS cycle is generated, the GMBUS is currently + in a data phase, or it is in a WAIT phase + Note that the three bits can be decoded as follows: 27 = STOP generated, 26 = INDEX used, 25 = + Cycle ends in a WAIT + Value Name Description + 000b No cycle No GMBUS cycle is generated + 001b No Index, No Stop, GMBUS cycle is generated without an INDEX, with no STOP, and ends + Wait with a WAIT + 010b Reserved Reserved + 011b Index, No Stop, Wait GMBUS cycle is generated with an INDEX, with no STOP, and ends with a + WAIT + 100b Gen Stop Generates a STOP if currently in a WAIT or after the completion of the + current byte if active + 101b No Index, Stop GMBUS cycle is generated without an INDEX and with a STOP + 110b Reserved Reserved + 111b Index, Stop GMBUS cycle is generated with an INDEX and with a STOP + 24:16 Total Byte Count + This determines the total number of bytes to be transferred during the DATA phase of a GMBUS cycle. + The DATA phase can be prematurely terminated by generating a STOP while in the DATA phase (see + Bus Cycle Select). + Do not change the value of this field during GMBUS cycles transactions. + 15:8 8 bit Slave Register Index + (INDEX) This field specifies the 8-bits of index to be used for the generated bus write transaction or the + index used for the WRITE portion of the WRITE/READ pair. + It only has an effect if the enable Index bit is set. + Do not change this field during a GMBUS transaction. + 7:0 Slave Address And Direction + Bits 7:1 = 7-bit GMBUS Slave Address (SADDR): When a GMBUS cycle is to be generated using the + Bus Cycle Select field, this field specifies the value of the slave address that is to be sent out. + For use with 10-bit slave address devices, set this value to 11110XXb (where the last two bits (XX) are + the two MSBs of the 10-bit address) and the slave direction bit to a write. + This is followed by the first data byte being the 8 LSBs of the 10-bit slave address. + + Bit 0 = Slave Direction Bit: When a GMBUS cycle is to be generated based on the Bus Cycle Select, + this bit determines if the operation will be a read or a write. + A read operation with the index enabled will perform a write with just the index followed by a re-start + and a read. + A 1 indicates that a Read from the slave device operation is to be performed. + A 0 indicates that a Write to the slave device operation is to be performed. + Value Name Description + 00000001b General General Call Address + 00000000b Start Start Bye + 0000001Xb CBUS CBUS Address + 11110XXXb 10-bit 10-Bit addressing + Others Reserved Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 21 + 2.2.6 GMBUS2—GMBUS Status + + GMBUS2 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000800 +Access: R/W Protect +Size (in bits): 32 +Address: C5108h-C510Bh +Name: GMBUS2 Status +ShortName: GMBUS2 +DWord Bit Description +0 31:16 Reserved + 15 INUSE + Software wishing to arbitrate for the GMBUS resource can poll this bit until it reads a zero and will then + own usage of the GMBUS controller. + This bit has no effect on the hardware, and is only used as semaphore among various independent + software threads that don’t know how to synchronize their use of this resource that may need to use + the GMBUS logic. + Writing a one to this bit is software’s indication that the software use of this resource is now terminated + and it is available for other clients. + Value Name Description + 0b GMBUS is Read operation that contains a zero in this bit position indicates that the GMBUS + Acquired engine is now acquired and the subsequent reads of this register will now have + this bit set. + Writing a 0 to this bit has no effect. + 1b GMBUS in Read operation that contains a one for this bit indicates that the GMBUS is + Use currently allocated to someone else and “In use”. + Once set, a write of a 1 to this bit indicates that the software has relinquished the + GMBUS resource and will reset the value of this bit to a 0. + 14 Hardware Wait Phase + Access: RO + (HW_WAIT_PHASE) Once in a WAIT_PHASE, the software can now choose to generate a STOP + cycle or a repeated start (RESTART) cycle followed by another GMBUS transaction on the GMBUS. + Value Name Description + 0b No The GMBUS engine is not in a wait phase. + Wait + 1b Wait Set when GMBUS engine is in wait phase. + Wait phase is entered at the end of the current transaction when that transaction is + selected not to terminate with a STOP. + 13 Slave Stall Timeout Error + Access: RO + This bit indicates that a slave stall timeout has occurred. + It is tied to the Enable Timeout (ENT) bit. + Value Name Description + 0b No Slave Timeout No slave timeout has occurred + 1b Slave Timeout A slave acknowledge timeout has occurred + 12 GMBUS Interrupt Status + Access: RO + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 22 + GMBUS2 + This bit indicates that an event that causes a GMBUS interrupt has occurred. + Value Name Description + 0b No The conditions that could cause a GMBUS interrupt have not occurred or this bit has + Interrupt been cleared by software assertion of the SW_CLR_INT bit. + 1b Interrupt GMBUS interrupt event occurred. This interrupt must have been one of the types + enabled in the GMBUS4 register + 11 Hardware Ready + Access: RO + (HW_RDY) This provides a method of detecting when the current software client routine can proceed + with the next step in a sequence of GMBUS operations. + This data handshake bit is used in conjunction with the SW_RDY bit. + When this bit is asserted by the GMBUS controller, it results in the de-assertion of the SW_RDY bit. + This bit resumes to normal operation when the SW_CLR_INT bit is written to a 0. + Value Name Description + 0b Ready 0 Condition required for assertion has not occurred or when this bit is a one and + SW_RDY bit has been asserted + During a GMBUS read transaction, after the each read of the data register + During a GMBUS write transaction, after each write of the data register + SW_CLR_INT bit has been cleared + 1b Ready 1 This bit is asserted under the following conditions: + [Default] After a reset or when the transaction is aborted by the setting of the SW_CLR_INT + bit + When an active GMBUS cycle has terminated with a STOP When during a GMBUS + write transaction, the data register needs and can accept another four bytes of data + During a GMBUS read transaction, this bit is asserted when the data register has + four bytes of new data or the read transaction DATA phase is complete and the data + register contains the last few bytes of the read data + 10 NAK Indicator + Access: RO + + + Value Name Description + 0b No bus No bus error has been detected or SW_CLR_INT has been written as a zero since + error the last bus error + 1b No Ack Set by hardware if any expected device acknowledge is not received from the slave + within the timeout + 9 GMBUS Active + Access: RO + (GA) This is a status bit that indicates whether the GMBUS controller is in an IDLE state or not. + Value Name Description + 0b Idle The GMBUS controller is currently IDLE + 1b Active This indicates that the bus is in START, ADDRESS, INDEX, DATA, WAIT, or STOP + Phase. Set when GMBUS hardware is not IDLE. + 8:0 Current Byte Count + Access: RO + Can be used to determine the number of bytes currently transmitted/received by the GMBUS controller + hardware. + Set to zero at the start of a GMBUS transaction data transfer and incremented after the completion of + each byte of the data phase. + Note that because reads have internal storage, the byte count on a read operation may be ahead of + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 23 + GMBUS2 + the data that has been accepted from the data register. + + + + +2.2.7 GMBUS3—GMBUS Data Buffer + + GMBUS3 +Register Space: MMIO: 0/2/0 + + +Default Value: 0x00000000 +Access: R/W Protect +Size (in bits): 32 +Double Buffer Update Point: Start of next Vblank +Double Buffer Armed By: HW_RDY +Address: C510Ch-C510Fh +Name: GMBUS3 Data Buffer +ShortName: GMBUS3 +This is data read/write register. This register is double buffered. + Bit 0 is the first bit sent or read, bit 7 is the 8th bit sent or read, all the way through bit 31 being the 32nd bit sent or +read. + For GMBUS write operations with a non-zero byte count, this register should be written with the data before the +GMBUS cycle is initiated. + For byte counts that are greater than four bytes, this register will be written with subsequent data only after the +HW_RDY status bit is set indicating that the register is now ready for additional data. + For GMBUS read operations, software should wait until the HW_RDY bit indicates that the register contains the next +set of valid read data before reading this register. + DWord Bit Description +0 31:24 Data Byte 3 + 23:16 Data Byte 2 + 15:8 Data Byte 1 + 7:0 Data Byte 0 + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 24 + 2.2.8 GMBUS4—GMBUS Interrupt Mask + + GMBUS4 +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C5110h-C5113h +Name: GMBUS4 Interrupt Mask +ShortName: GMBUS4 +DWord Bit Description +0 31:5 Reserved + 4:0 Interrupt Mask + This field specifies which GMBUS interrupts events may contribute to the setting of GMBUS interrupt + status bit in second level interrupt status register. + + For gmbus writes, the HW Ready (HWRDY) interrupt indicates that software can write the next + DWORD. It does NOT mean that the transfer of data to the slave device has completed. + The IDLE or HW wait interrupt may be used to detect the end of writing data to the slave device. + The HWRDY interrupt may be used for gmbus write cycles only to detect when to write the next + DWORD after the first two DWORDs have been written to GMBUS3. + For gmbus reads, the HWRDY interrupt indicates the arrival of the next dword. + Value Name Description + 0XXXXb GMBUS Slave stall TO Disable GMBUS Slave stall timeout interrupt + Disable + 1XXXXb GMBUS Slave stall TO Enable GMBUS Slave stall timeout interrupt + Enable + X0XXXb GMBUS NAK Disable Disable GMBUS NAK interrupt + X1XXXb GMBUS NAK Enable Enable GMBUS NAK interrupt + XX0XXb GMBUS Idle Disable Disable GMBUS Idle interrupt + XX1XXb GMBUS Idle Enable Enable GMBUS Idle interrupt + XXX0Xb HW Wait Disable Disable Hardware wait (GMBUS cycle without a stop has + completed) Interrupt + XXX1Xb HW Wait Enable Enable Hardware wait (GMBUS cycle without a stop has + completed) Interrupt + XXXX0b HW Ready Disable Disable Hardware ready (Data has been transferred) interrupt + XXXX1b HW Ready Enable Enable Hardware ready (Data has been transferred) interrupt + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 25 + 2.2.9 GMBUS5—GMBUS 2 Byte Index + + GMBUS5 +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C5120h-C5123h +Name: GMBUS5 2 Byte Index +ShortName: GMBUS5 +This register provides a method for the software indicate to the GMBUS controller the 2 byte device index. + DWord Bit Description +0 31 2 Byte Index Enable + When this bit is asserted (1), then bits 15:0 are used as the index. + Bits 15:8 are used in the first byte which is the most significant index bits. + The slave index in the GMBUS1<15:8> are ignored. + Bits 7:0 are used in the second byte which is the least significant index bits. + 30:16 Reserved + 15:0 2 Byte Slave Index + This is the 2 byte index used in all GMBUS accesses when bit 31 is asserted (1). + + + + +2.3 Display Clock Control +Pixel Data Rate Dot Clock Dual Channel? External Clock Data Clock Rate Multiplier + 100-200MHz NO 100-200MHz 1.0-2.0GHz 4x + 100-200MHz NO 100-200MHz 1.0-2.0GHz 2x + 100-225MHz NO 100-225MHz 1.0-2.25GHz 1x + 25-112MHz NO 25-112MHz 175-784MHz 1x + LVDS + 25-112MHz + + 80-224MHz YES 80-224MHz 280-784MHz 1x + LVDS + 80-224MHz + + + + Display Modes Display Clock Frequency Range (MHz) + CRT DAC 25-350 + HDMI/DVI + 25-225 + (pixel rate can differ from clock frequency) + + 100-225 + (pixel rate can differ from clock frequency) + LVDS (Single Channel) 25-112 + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 26 + Display Modes Display Clock Frequency Range (MHz) + LVDS (Dual Channel) 80-224 + 100-200 + DisplayPort + 162, 270 + (pixel rate can differ from clock frequency) + + + +The PLL frequency selection must be done such that the internal VCO frequency is within its limits. +The PLL Frequency is based on the selected register and the following formula. +DotClk_Frequency = (ReferenceFrequency * (5* (M1+2)+(M2+2)) / (N+2))/ (P1* P2) +Reference Frequency: 120 MHz for CRT, HDMI, LVDS, 100MHz for the FDI. + + + Item Units Range Notes +Dot Clock Frequency 20-350 MHz (Combining ALL modes) +VCO Frequency 1760-3510 MHz +N – Counter Value 3-8 +M – Counter Value 79-127 M=5*(M1+2)+(M2+2) +M1 and M2 M1 > M2 +M1 Value 12-22 +M2 Value 5-9 +P-Div Value 5-80 +P-Div Value 28-112 Combined P1 and P2 for LVDS mode +P1-Div Value 1-8 All modes + + + +Note: For HDMI 12bpc usage model, the PCH display pixel clock should be programmed at 1.5x the +effective pixel clock of the CPU display. This needs to be taken into account when setting the post +divisors. + + +2.3.1 DPLL_CTL—DPLL Control + + DPLL_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x04800080 +Access: R/W Protect +Size (in bits): 32 +Double Buffer Update Point: Transcoder vertical blank, except as stated +Address: C6014h-C6017h +Name: DPLLA Control +ShortName: DPLL_CTL_A +Address: C6018h-C601Bh +Name: DPLLB Control + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 27 + DPLL_CTL +ShortName: DPLL_CTL_B +Write Protect by Panel Power Sequencer when panel is connected to this transcoder. +DWord Bit Description +0 31 DPLL VCO Enable + Access: R/W + This bit will enable or disable the PLL VCO. Disabling the PLL will cause the display pixel clock to stop. + Value Name Description + 0b Disable DPLL is disabled in its lowest power state + 1b Enable DPLL is enabled and operational + 30 DPLL High Speed IO clock En + Value Name Description + 0b Disable High Speed IO Clock Disabled + 1b Enable High Speed IO Clock Enabled (must be set in HDMI/DVI and DisplayPort modes). + 29:28 Reserved + Format: MBZ + 27:26 DPLL Mode Select + Configure the DPLL for various supported Display Modes. + Value Name Description + 00b Reserved Reserved + 01b Non-LVDS [Default] DPLL in DAC/HDMI/DisplayPort mode. + 10b LVDS DPLL in LVDS mode + 11b Reserved Reserved + 25:24 FP0 FP1 P2 Clock Divide + Value Name Description + 00b Div 14 or 10 Divide by 14 for Single-Channel LVDS. + Divide by 10 for DisplayPort. + Also used for DAC and HDMI modes with Dot Clock <= 225MHz. + 01b Div 7 or 5 Divide by 7 for Dual-Channel LVDS + Divide by 5 for DAC and HDMI modes with Dot Clock > 225MHz. + Others Reserved Reserved + 23:16 FP0 P1 Post Divisor + Writes to this byte finalize the write of m, n and p values into the PLL when the PLL is disabled. + Writing to FP1 when FP0 is in use (or vice versa) is also allowed. + Writes to this register take effect immediately. + Value Name Description + 00000001b 1 Divide by one + 00000010b 2 Divide by two + 00000100b 3 Divide by three + 00001000b 4 Divide by four + 00010000b 5 Divide by five + 00100000b 6 Divide by six + 01000000b 7 Divide by seven + 10000000b 8 [Default] Divide by eight + Others Reserved Reserved + 15:13 PLL Reference Input Select + (Not Double Buffered) The PLL reference should be selected based on the display device that is being + driven. + The standard reference clock is used for CRT modes using the analog port CRT DAC or LCD panels + or for the integrated LVDS. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 28 + DPLL_CTL + Value Name Description + 000b DREFCLK DREFCLK (default is 120 MHz) for DAC/HDMI/DVI/DisplayPort. + 001b Super SSC 120MHz super-spread clock + 011b SSC Spread spectrum input clock (120MHz default) for LVDS/DisplayPort. + Others Reserved Reserved + 12 Reserved + 11:9 DPLL HDMI multiplier + This field determines the data multiplier for HDMI and is also applied to CRT. + In order to keep the clock rate to a more narrow range of rates, the multiplier is set and the Display + PLL programmed to a multiple of the display mode’s actual clock rate. + The value is = multiplication factor - 1 + Value Name + 000b 1X + 001b 2X + 010b 3X + 011b 4X + + + Programming Notes + Restriction : The DPLL must be enabled and stable before setting these bits. + These bits must be programmed after DPLL_SEL is programmed. + 8 Reserved + Format: MBZ + 7:0 FP1 P1 Post Divisor + Writes to this byte finalize the write of m, n and p values into the PLL when the PLL is disabled. + Writing to FP1 when FP0 is in use (or vice versa) is also allowed. + Writes to this register take effect immediately. + Value Name Description + 00000001b 1 Divide by one + 00000010b 2 Divide by two + 00000100b 3 Divide by three + 00001000b 4 Divide by four + 00010000b 5 Divide by five + 00100000b 6 Divide by six + 01000000b 7 Divide by seven + 10000000b 8 [Default] Divide by eight + Others Reserved Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 29 + 2.3.2 DPLL_FP0—DPLL Divisor 0 + + DPLL_FP0 +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W Protect +Size (in bits): 32 +Double Buffer Update Point: Transcoder vertical blank +Address: C6040h-C6043h +Name: DPLLA Divisor 0 +ShortName: DPLL_FP0_A +Address: C6048h-C604Bh +Name: DPLLB Divisor 0 +ShortName: DPLL_FP0_B +Write Protect by Panel Power Sequencer when panel is connected to this transcoder. +DWord Bit Description +0 31:28 Reserved + Format: MBZ + 27 Frequency doubler clock enable + This bit enables/disables the frequency doubler clock. When the VCO clock to the doubler is disabled, + the circuit does not dissipate power and its output clock is not available + Value Name Description + 0b Disable Disables clock of frequency doubler + 1b Enable Enables clock of frequency doubler + 26:25 Reserved + Format: MBZ + 24:22 CB Tuning + + These bits are used for CB tuning the Display PLL Analog core on PCH. These bits are required to + improve the jitter performance and VCO headroom of the Display PLL across Process, Voltage and + Temperature variations. The CB tune should be turned on when the M/N ratio is less than a certain + value given in the table below. The bits should be programmed to 0x011 to turn the complete CB cap + on. + Display Mode If M/N Ratio is less than Bits [24:22] + DAC 21.00 011 + HDMI 21.00 011 + LVDS 1ch (120mhz input clock) 21.00 011 + LVDS 2ch (120mhz input clock) 21.00 011 + LVDS 1ch (100mhz input clock) 25.00 011 + LVDS 2ch (100mhz input clock) 25.00 011 + Example 1 + + + In DAC mode, for pixel clock = 31MHz, N=4; M=83; P=80; + + Therefore M/N ratio = 20.75 which is < 21.00 mentioned in the table above. Hence the CB tune bits + [24:22] need to be programmed to 011. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 30 + DPLL_FP0 + Example 2 + + + In DAC mode, for pixel clock = 31.5MHz, N=4; M=84; P=80; + + Therefore M/N ratio = 21 which equal to the value of M/N ration mentioned in the table above. Hence + the CB tune bits [24:22] need to be programmed to 000. + Value Name Description + 000b Off CB Tune Off + 011b 100% CB Tune 100% On + 21:16 FP0 N Divisor + N-Divisor value calculated for the desired output frequency. + The register value is programmed two less than the actual divisor. + 15:14 Reserved + Format: MBZ + 13:8 FP0 M1 Divisor + M-Divisor value calculated for the desired output frequency. + The register value is programmed to two less than the actual divisor. + 7:6 Reserved + Format: MBZ + 5:0 FP0 M2 Divisor + M-Divisor value calculated for the desired output frequency. + The register value is programmed two less than the actual divisor. + + + + +2.3.3 DPLL_FP1—DPLL Divisor 1 + + DPLL_FP1 +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W Protect +Size (in bits): 32 +Double Buffer Update Point: Transcoder vertical blank +Address: C6044h-C6047h +Name: DPLLA Divisor 1 +ShortName: DPLL_FP1_A +Address: C604Ch-C604Fh +Name: DPLLB Divisor 1 +ShortName: DPLL_FP1_B +Write Protect by Panel Power Sequencer when panel is connected to this transcoder. + DWord Bit Description +0 31:25 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 31 + DPLL_FP1 + 24:22 CB Tuning + See FP0 CB_Tuning description + Value Name Description + 000b Off CB Tune Off + 011b 100% CB Tune 100% On + 21:16 FP1 N Divisor + N-Divisor value calculated for the desired output frequency. + The register value is programmed two less than the actual divisor. + 15:14 Reserved + Format: MBZ + 13:8 FP1 M1 Divisor + M-Divisor value calculated for the desired output frequency. + The register value is programmed to two less than the actual divisor. + 7:6 Reserved + Format: MBZ + 5:0 FP1 M2 Divisor + M-Divisor value calculated for the desired output frequency. + The register value is programmed two less than the actual divisor. + + + + +2.3.4 DREF_CTL — Display Reference Clock Control + + DREF_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C6200h-C6203h +Name: Display Reference Clock Control +ShortName: DREF_CTL +DWord Bit Description +0 31:15 Reserved + Format: MBZ + 14:13 120MHz CPU source output en + Value Name Description + 00b Disabled Source output to CPU disabled + 01b Reserved Rerserved + 10b Downspread -0.5% SSC downspread source output to CPU enabled. Both the 120MHz SSC + source (bits 12:11) and the SSC1 modulator (bit1) must be enabled prior to + enabling this output + 11b Non-spread Non-spread source output to CPU enabled. The 120MHz non-SSC source (bit 10:9) + must be enabled prior to enabling this output + 12:11 120MHz SSC source en + This bit enables the 120MHz SSC source used as a reference for DisplayPort or CPU + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 32 + DREF_CTL + Value Name Description + 00b Disabled Source disabled + 01b Reserved Reserved for CK505 buffered source enabled + 10b Enabled Integrated source enabled + 11b Reserved Reserved + 10:9 120MHz nonspread source en + This field enables the 120MHz non-SSC source for display + Value Name Description + 00b Disabled Source disabled + 01b CK505 CK505 buffered source enabled. + 10b Integrated Integrated source enabled + 11b Reserved Reserved + 8:7 120MHz superspread source en + This field enables the 120MHz super-SSC source for display + Value Name Description + 00b Disabled Source disabled + 01b Reserved Reserved + 10b Enabled Integrated source enabled + 11b Reserved Reserved + 6 SSC4 Spread Mode + This is the reference clock used for super-spread on LVDS. + This bit must not be changed after bit 0 is set. It may be updated simultaneously with the update of bit + 0. + Value Name Description + 0b Downspread Center vs downspread: this bit sets down spread on the SSC4 modulator used for + superspread. + 1b Centerspread Center vs downspread: this bit sets center spread on the SSC4 modulator used for + superspread. + + + Programming Notes + Restriction : This reference is shared with SATA. If it is used for SATA it must not be used for LVDS. + 5:2 Reserved + Format: MBZ + 1 120MHz SSC1 modulation en + This bit enables the -0.5% modulator used for the 120MHz SSC source used for the CPU DisplayPort + or as the -0.5% input to the DPLL in the PCH. + It must be set 0uS or more after the 120MHz SSC output is enabled (this bit and bits 12:11 can be + written to enable at the same time). + PLL’s using this clock as an input must be enabled 1uS or more after this bit is enabled to ensure a + stable input. + Value Name Description + 0b Disabled SSC1 disabled + 1b Enabled SSC1 enabled + 0 120MHz SSC4 modulation en + This bit enables the variable % modulator used for the 120MHz SSC source used for LVDS. + It must be set 0uS or more after the 120MHz super-spread source is enabled (this bit and bits 8:7 can + be written to enable at the same time). + PLL’s using this clock as an input must be enabled 1uS or more after this bit is enabled to ensure a + stable input. + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 33 + DREF_CTL + Value Name Description + 0b Disabled SSC4 disabled + 1b Enabled SSC4 enabled + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 34 + 2.3.5 RAWCLK_FREQ—Rawclk Frequency + + RAWCLK_FREQ +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C6204h-C6207h +Name: Rawclk Frequency +ShortName: RAWCLK_FREQ + DWord Bit Description +0 31:10 Reserved + 9:0 Rawclk frequency + Program this field to match the rawclk frequency of 125 MHz. + This is used to generate a divided down clock for miscellaneous timers in display. + + + + +2.3.6 SSC4_PARMS – SSC4 Parameters + + SSC4_PARMS +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x01204860 +Access: R/W +Size (in bits): 32 +Address: C6210h-C6213h +Name: SSC4 Parameters +ShortName: SSC4_PARMS +Notes: +  This register must not be changed after bit 0 of register DREF_CTL is set. +  Default values of this register are meaningless. +  0% spread option for SSC4 should be configured by clearing bit 0 of DREF_CTL to disable SSC4 module. In this + case, registers SSC4PARMS and SSC4AuxPARMS settings have no effect and are don’t care to the hardware. + Bits 8:7 of DREF_CTL still need to be configured to enable the divisor DIV4, i.e. the source of the clock. +  This register needs to be configured by the display driver for desired spread percentages. Recommended + settings for 0.5% down spread and 0.5%, 1.0%, 1.5%, 2.0%, and 2.5% center spread are listed in the following + look-up table. Recommended settings for half-step clock bending usage is also listed. + + Register Half-step 0.5% down 0.5% center 1.0% center 1.5% center 2.0% center 2.5% center + fields clock bend spread spread spread spread spread spread +6/5/4Ni_1NjRpt 00b 01b 01b 01b 01b 01b 01b +, [29:28] +3Ni_1NjRpt, 000b 010b 010b 010b 010b 010b 010b + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 35 + SSC4_PARMS +[26:24] +2Ni1NjRpt, 000b 111b 111b 111b 111b 111b 111b +[22:20] +1Ni1NjRpt, 0_0000_0000 0_0010_1001 0_0010_1001 0_0000_0010 0_0000_1010 0_0000_0010 0_0000_1010 +[18:10] b b b b b b b +MxPhsStp, 000_0000b 000_0101b 000_0010b 000_0101b 000_0100b 000_0101b 000_0100b +[9:3] +PhsIncVal, 000b 000b 000b 000b 001b 001b 010b +[2:0] + +DWor + d Bit Description +0 31:3 Reserved + 0 Format: MBZ + 29:2 SSC4 6 5 4Ni 1Nj Repeat Count + 8 Select the number of repeats for the portion of 4, or 5, or 6 clocks of Ni and 1 clock of Nj within a dithering + pattern of a step. See 1Ni_1Nj Repeat Count for more information. Value is zero based. + Value Name + 00b 1 times + 27 Reserved + Format: MBZ + 26:2 SSC4 3Ni 1Nj Repeat Count + 4 Default Value: 001b 2 times + Select the number of repeats for the portion of 3 clocks of Ni and 1 clock of Nj within a dithering pattern of + a step. See 1Ni_1Nj Repeat Count for more information. Value is zero based. + + 23 Reserved + Format: MBZ + 22:2 SSC4 2Ni 1Nj Repeat Count + 0 Default Value: 010b 3 times + Select the number of repeats for the portion of 2 clocks of Ni and 1 clock of Nj within a dithering pattern of + a step. See 1Ni_1Nj Repeat Count for more information. Value is zero based. + + 19 Reserved + Format: MBZ + 18:1 SSC4 1Ni 1Nj Repeat Count + 0 Default Value: 000010010b 19 times + Select the number of repeats for the portion of 1 clock of Ni and 1 clock of Nj within a dithering pattern of + a step. Together, 1Ni_1Nj Repeat Count, 2Ni_1Nj Repeat Count, 3Ni_1Nj Repeat Count, and 6/5/4Ni_1Nj + Repeat Count tune the width of the target 32Khz modulated period. For down spread, the target these + fields are to be tuned to is one half of the modulated period. For center spread, the target is one quarter of + the modulated period. Value is zero based. + + 9:3 SSC4 Max Phase Step + Default Value: 0001100b 13 steps + Select the number of steps to reach peak of modulated phase adjustment value. Together, Max Phase + Step field and Phase Increment Value field control the magnitude of the spread. Value is zero based. + + 2:0 SSC4 Phase Increment Value + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 36 + SSC4_PARMS + Select the granularity of each phase step. Together, Max Phase Step field and Phase Increment Value + field control the magnitude of the spread. Value is zero based. + Value Name + 000b 1 PI change per step + + + + +2.3.7 DPLL_SEL— DPLL Select + + DPLL_SEL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C7000h-C7003h +Name: DPLL Select +ShortName: DPLL_SEL +Individual bits are write protected by panel power sequencing when the panel is connected to the transcoder +associated with that bit. + DWord Bit Description +0 31:12 Reserved + 11 Transcoder C DPLL Enable + Value Name Description + 0b Disable Disable DPLL to this transcoder + 1b Enable Enable DPLL to this transcoder + 10:9 Reserved + 8 Transcoder C DPLL Select + Value Name Description + 0b DPLLA Select DPLLA for this transcoder + 1b DPLLB Select DPLLB for this transcoder + 7 Transcoder B DPLL Enable + Value Name Description + 0b Disable Disable DPLL to this transcoder + 1b Enable Enable DPLL to this transcoder + 6:5 Reserved + 4 Transcoder B DPLL Select + Value Name Description + 0b DPLLA Select DPLLA for this transcoder + 1b DPLLB Select DPLLB for this transcoder + 3 Transcoder A DPLL Enable + Value Name Description + 0b Disable Disable DPLL to this transcoder + 1b Enable Enable DPLL to this transcoder + 2:1 Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 37 + DPLL_SEL + 0 Transcoder A DPLL Select + Value Name Description + 0b DPLLA Select DPLLA for this transcoder + 1b DPLLB Select DPLLB for this transcoder + + + + +2.4 Panel Power Sequencing + +2.4.1 PP_STATUS—Panel Power Status + + PP_STATUS +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x08000000 +Access: RO +Size (in bits): 32 +Address: C7200h-C7203h +Name: Panel Power Status +ShortName: PP_STATUS +DWord Bit Description +0 31 Panel Power On Status + This field gives the current panel power status + Value Name Description + 0b Off Indicates that the panel power down sequencing has completed. + A power cycle delay may be currently active. + It is safe and allowed to program timing, port, and DPLL registers. + 1b On Indicates that the panel is currently powered up or is currently in the power down + sequence and it is unsafe to change the timing, port, and DPLL registers for the pipe or + transcoder that is assigned to the panel output. Register write protect is active and writes + to protected registers will be ignored unless the write protect key value is set in the panel + sequencing control register. + 30 Require Asset Status + This bit indicates the status of programming of the DPLL and the selected port. + A power on cycle will not be allowed unless this status indicates that the required assets are + programmed and ready for use or the PP_CONTROL Write Protect Key is programmed to 0xABCD. + The following conditions determine that the assets are ready: + 1) PCH DPLL is enabled and frequency locked. + 2) Port selected in PP_ON_DELAYS Panel control port select is enabled or is DisplayPort A. + Value Name Description + 0b Not Ready All required assets are not properly programmed + 1b Ready All required assets are ready for the driving of a panel + + + Programming Notes + This bit should be ignored when using DisplayPort A. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 38 + PP_STATUS + 29:28 Power Sequence Progress + Value Name Description + 00b None Indicates that the panel is not in a power sequence + 01b Power Up Indicates that the panel is in a power up sequence (may include power cycle delay) + 10b Power Down Indicates that the panel is in a power down sequence + 11b Reserved Reserved + 27 Power Cycle Delay Active + Power cycle delays occur after a panel power down sequence or after a hardware reset. + On reset, a power cycle delay will occur using the default value for the timing. + Value Name Description + 0b Not Active A power cycle delay is not currently active + 1b Active [Default] A power cycle delay (T4) is currently active + 26:4 Reserved + + + + +2.4.2 PP_CONTROL—Panel Power Control + + PP_CONTROL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C7204h-C7207h +Name: Panel Power Control +ShortName: PP_CONTROL +When the panel is either powered up or in the process of a power up sequence, registers involved in generation of +panel timing or control become write protected. + Any write cycles to those write protected registers, while they will complete as normal, will not change the value of +the register when write protected. + In situations where the embedded panel port is unused, the port should remain powered down and the write protect +will be inactive. + +List of write protected registers: +- LVDS Port Control (entire register) +- DisplayPort Control (port enable and port to transcoder select bits) +- Panel power on sequencing delays +- Panel power off sequencing delays +- Panel power cycle delay and Reference Divisor +- DPLL Control DPLL Divisors +- HTOTAL—Horizontal Total Register +- HBLANK—Horizontal Blank Register +- HSYNC—Horizontal Sync Register +- VTOTAL—Vertical Total Register +- VBLANK—Vertical Blank Register +- VSYNC—Vertical Sync Register +DWord Bit Description + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 39 + PP_CONTROL +0 31:16 Write Protect Key + This field in normal operation should be kept at the default value of 0000h. This field can be + programmed with the key value "ABCD" to uncoditionally disable write protect. + Value Name + 0000h Enable Write Protect [Default] + ABCDh Disable Write Protect + Others Enable Write Protect + + + Programming Notes + Workaround : Write Protect Key must be programmed to 0xABCD when using panel power sequencing + on DisplayPort A (PP_ON_DELAYS bits 31:30 Panel Control port select is set to 01b DisplayPort A). + 15:4 Reserved + 3 eDP VDD Override for AUX + This bit is used to force on VDD for the embedded DisplayPort panel so AUX transactions can occur + without enabling the panel power sequence. + This is intended for panels that require VDD to be asserted before accessing AUX port on the receiver. + Value Name Description + 0b Not Panel VDD controlled by Panel Power Sequence state machine + Force + 1b Force Force panel VDD on to allow AUX transaction. Panel power sequence flow should be + used regardless of the state of this bit when it is desired to enable the embedded + DisplayPort main link. + + + Programming Notes + Restriction : When software clears this bit from ‘1’ to ‘0’ (disable VDD override) it must ensure that T4 + power cycle delay is met before setting this bit to ‘1’ again. + 2 Backlight Enable + Enabling this bit enables the panel backlight when hardware is in the correct panel power sequence + state and the port is a DisplayPort, as indicated in PP_ON_DELAYS Panel_control_port_select. + Value Name Description + 0b Disable Backlight disabled + 1b Enable Backlight enabled + 1 Power Down on Reset + Enabling this bit causes the panel to power down on reset warning. + When system reset is initiated, the panel power down sequence begins automatically. + If the panel is not on during a reset event, this bit is ignored. + Value Name Description + 0b Do not Run Do not run panel power down sequence when reset is detected + 1b Run Run panel power down sequence when system is reset + 0 Power State Target + This bit sets the panel power state target. It can be written at any time and takes effect at the + completion of any current power cycle. + Value Name Description + 0b Off The panel power state target is off. + If the panel is either on or in a power on sequence, a power off sequence is started as + soon as the panel reaches the power on state. This may include a power cycle delay. + If the panel is currently off, there is no change of the power state or sequencing done. + 1b On The panel power state target is on. + If the panel is in either the off state or a power off sequence, and all pre-conditions are + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 40 + PP_CONTROL + met, a power on sequence is started as soon as the panel reaches the power off state. + This may include a power cycle delay. + If the panel is currently on, there is no change of the power state or sequencing done. + + + + +2.4.3 PP_ON_DELAYS—Panel Power On Sequencing Delays + + PP_ON_DELAYS +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W Protect +Size (in bits): 32 +Address: C7208h-C720Bh +Name: Panel Power On Sequencing Delays +ShortName: PP_ON_DELAYS +Write Protect by Panel Power Sequencer +DWord Bit Description +0 31:30 Panel control port select + These bits define to which port the embedded panel is connected. This is used for automatic control of + the panel power. + If the selected port is disabled, the power sequence will not allow a panel power up. + Value Name Description + 00b LVDS Panel is connected to the LVDS port + 01b DisplayPort A Panel is connected to the DisplayPort A + 10b DisplayPort C Panel is connected to the DisplayPort C + 11b DisplayPort D Panel is connected to the DisplayPort D + + + Programming Notes + Workaround : PP_CONTROL bits 31:16 Write_Protect_Key must be programmed to 0xABCD when + using panel power sequencing on DisplayPort A. + 29 Reserved + 28:16 Power up delay + Programmable value of panel power sequencing delay during panel power up. + The time unit used is the 100us timer. + + LVDS: This provides the time delay for the T1+T2 time sequence. + + DisplayPort: Software programs this field with the time delay for the eDP T3 time value; the time from + the source enabling panel power to when the sink HPD and AUX channel are ready. + 15:13 Reserved + 12:0 Power on to backlight on + Power on to backlight enable delay. + Programmable value of panel power sequencing delay during panel power up. + The time unit used is the 100us timer. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 41 + PP_ON_DELAYS + + LVDS: This provides the time delay for the T5 time sequence. + + DisplayPort: Software programs this field with a value of 1b to get the minimum delay from hardware. + Software controls the source valid video data output and backlight enable after this delay has been + met. Hardware will not allow the backlight to enable until after this delay and the power up delay (eDP + T3) have passed. + + + + +2.4.4 PP_OFF_DELAYS—Panel Power Off Sequencing Delays + + PP_OFF_DELAYS +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W Protect +Size (in bits): 32 +Address: C720Ch-C720Fh +Name: Panel Power Off Sequencing Delays +ShortName: PP_OFF_DELAYS +Write Protect by Panel Power Sequencer +DWord Bit Description +0 31:29 Reserved + 28:16 Power Down delay + Programmable value of panel power sequencing delay during power up. + The time unit used is the 100us timer. + + LVDS: This provides the time delay for the T3 time sequence. + + DisplayPort: Software programs this field with the time delay for the eDP T10 time value; the time from + source ending valid video data to source disabling panel power. Software controls the source valid + video data output, so this together with T9 is only used as a step towards the final power down delay. + 15:13 Reserved + 12:0 Backlight off to power down + Power backlight off to power down delay. + The time unit used is the 100us timer. + + LVDS: Programmable value of panel power sequencing delay during power down. This provides the + time delay for the Tx time sequence. + + DisplayPort: Software programs this field with the time delay for the eDP T9 time value; the time from + backlight disable to source ending valid video data. Software controls the backlight disable and source + valid video data output, so this together with T10 is only used as a step towards the final power down + delay. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 42 + 2.4.5 PP_DIVISOR—Panel Power Cycle Delay and Reference Divisor + + PP_DIVISOR +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00186904 +Access: R/W Protect +Size (in bits): 32 +Address: C7210h-C7213h +Name: Panel Power Cycle Delay and Reference Divisor +ShortName: PP_DIVISOR +DWord Bit Description +0 31:8 Reference divider + Default Value: 001869h 125MHz + This field provides the value of the divider used for the creation of the panel timer reference clock. + The value of zero should not be used. + When it is desired to divide by N, the actual value to be programmed is (N/2)-1. The value should be + (100 * Ref clock frequency in MHz / 2) - 1. + + Reference Clock Frequency Value of Field + 125MHz 1869h + 7:5 Reserved + 4:0 Power Cycle Delay + Default Value: 4h 300 mS + Programmable value of time panel must remain in a powered down state after powering down. + If the panel power on sequence is attempted during this delay, the power on sequence will commence + once the power cycle delay is complete. + + The time unit used is the 100 ms timer. + This register needs to be programmed to a “+1” value. For instance to achieve 400 ms, program a value + of 5. + Writing a value of 0 selects no delay or is used to abort the delay if it is active. + + For devices coming out of reset, the timer will be set to the default value and the count down will begin + after the de-assertion of reset. Even if the panel is not enabled, the count happens after reset. + + LVDS: This corresponds to the T4 of the SPWG specification. + + DisplayPort: This provides the time delay for the eDP T12 time value; the shortest time from panel + power disable to power enable. If a panel power on sequence is attempted during this delay, the power + on sequence will not commence until the delay is complete. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 43 + 2.5 Backlight Control + +2.5.1 SBLC_BLM_CTL1—South BLM PWM Control 1 + + SBLC_PWM_CTL1 +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C8250h-C8253h +Name: South BLM Control 1 +ShortName: SBLC_PWM_CTL1 + DWord Bit Description +0 31 PWM PCH Enable + This bit enables the PWM counter logic in the PCH. + Value Name Description + 0b Disable PCH PWM disabled + 1b Enable PCH PWM enabled + 29 Backlight Polarity + This field controls the polarity of the PWM signal. + Value Name Description + 0b High Active High + 1b Low Active Low + 28:0 Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 44 + 2.5.2 SBLC_BLM_CTL2—South BLM PWM Control 2 + + SBLC_PWM_CTL2 +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: C8254h-C8257h +Name: South BLM Control 2 +ShortName: SBLC_PWM_CTL2 +DWord Bit Description +0 31:16 Backlight Modulation Frequency + This field determines the number of time base events in total for a complete cycle of modulated + backlight control. + This field is normally set once during initialization based on the frequency of the clock that is being + used and the desired PWM frequency. + This value represents the period of the PWM stream in PCH display raw clocks multiplied by 128. + 15:0 Backlight Duty Cycle Override + This value overrides the CPU control of PWM duty cycle when the PWM PCH Override Enable bit is + set. + This field determines the number of time base events for the active portion of the PWM backlight + control. + This should never be larger than the frequency field. + A value of zero will turn the backlight off. + A value equal to the backlight modulation frequency field will be full on. + This field gets updated when it is desired to change the intensity of the backlight, it will take affect at + the end of the current PWM cycle. + This value represents the active time of the PWM stream in PCH display raw clock periods multiplied + by 128. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 45 + 3. South Display Engine Transcoder and + Port Controls +3.1 Transcoder Timing + +3.1.1 HTOTAL—Horizontal Total + + HTOTAL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: E0000h-E0003h +Name: Transcoder A Horizontal Total +ShortName: TRANS_HTOTAL_A +Address: E1000h-E1003h +Name: Transcoder B Horizontal Total +ShortName: TRANS_HTOTAL_B +Address: E2000h-E2003h +Name: Transcoder C Horizontal Total +ShortName: TRANS_HTOTAL_C +Write Protect by Panel Power Sequencer when panel is connected to this transcoder. +DWord Bit Description +0 31:29 Reserved + Format: MBZ + 28:16 Horizontal Total + This field specifies Horizontal Total size. + This should be equal to the sum of the horizontal active and the horizontal blank sizes. + This field is programmed to the number of pixels desired minus one. + Programming Notes + Restriction : The number of pixels (before the minus one) needs to be a multiple of two when driving + the LVDS port in two channel mode. + This register must always be programmed to the same value as the Horizontal Blank End. + 15:12 Reserved + Format: MBZ + 11:0 Horizontal Active + This field specifies Horizontal Active Display size. + The first horizontal active display pixel is considered pixel number 0. + This field is programmed to the number of pixels desired minus one. + Programming Notes + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 46 + HTOTAL + Restriction : The number of pixels (before the minus one) needs to be a multiple of two when driving + the LVDS port in two channel mode. + The minimum horizontal active display size is 64 pixels. + This register must always be programmed to the same value as the Horizontal Blank Start. + + + + +3.1.2 HBLANK—Horizontal Blank + + HBLANK +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: E0004h-E0007h +Name: Transcoder A Horizontal Blank +ShortName: TRANS_HBLANK_A +Address: E1004h-E1007h +Name: Transcoder B Horizontal Blank +ShortName: TRANS_HBLANK_B +Address: E2004h-E2007h +Name: Transcoder C Horizontal Blank +ShortName: TRANS_HBLANK_C +Write Protect by Panel Power Sequencer when panel is connected to this transcoder. +DWord Bit Description +0 31:29 Reserved + 28:16 Horizontal Blank End + This field specifies Horizontal Blank End position relative to the horizontal active display start. + Programming Notes + Restriction : The number of pixels within horizontal blank needs to be a multiple of two when driving + the LVDS port in two channel mode. + The minimum horizontal blank size is 32 pixels + This register must always be programmed to the same value as the Horizontal Total. + 15:13 Reserved + 12:0 Horizontal Blank Start + This field specifies the Horizontal Blank Start position relative to the horizontal active display start. + Programming Notes + Restriction : This register must always be programmed to the same value as the Horizontal Active. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 47 + 3.1.3 HSYNC—Horizontal Sync + + HSYNC +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: E0008h-E000Bh +Name: Transcoder A Horizontal Sync +ShortName: TRANS_HSYNC_A +Address: E1008h-E100Bh +Name: Transcoder B Horizontal Sync +ShortName: TRANS_HSYNC_B +Address: E2008h-E200Bh +Name: Transcoder C Horizontal Sync +ShortName: TRANS_HSYNC_C +Write Protect by Panel Power Sequencer when panel is connected to this transcoder. +DWord Bit Description +0 31:29 Reserved + Format: MBZ + 28:16 Horizontal Sync End + This field specifies the Horizontal Sync End position relative to the horizontal active display start. + It is programmed with HorizontalActive+FrontPorch+Sync-1. + Programming Notes + Restriction : The number of pixels within horizontal sync needs to be a multiple of two when driving the + LVDS port in two channel mode. + This value must be greater than the horizontal sync start and less than Horizontal Total. + Restriction : HDMI and DVI with audio are not supported when HSYNC Start is programmed equal to + HBLANK Start. + 15:13 Reserved + Format: MBZ + 12:0 Horizontal Sync Start + This field specifies the Horizontal Sync Start position relative to the horizontal active display start. + It is programmed with HorizontalActive+FrontPorch-1. + Programming Notes + Restriction : The number of pixels from active to horizontal sync needs to be a multiple of two when + driving the LVDS port in two channel mode. + This value must be greater than Horizontal Active. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 48 + 3.1.4 VTOTAL—Vertical Total + + VTOTAL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: E000Ch-E000Fh +Name: Transcoder A Vertical Total +ShortName: TRANS_VTOTAL_A +Address: E100Ch-E100Fh +Name: Transcoder B Vertical Total +ShortName: TRANS_VTOTAL_B +Address: E200Ch-E200Fh +Name: Transcoder C Vertical Total +ShortName: TRANS_VTOTAL_C +Write Protect by Panel Power Sequencer when panel is connected to this transcoder. +DWord Bit Description +0 31:29 Reserved + 28:16 Vertical Total + This field specifies Vertical Total size. + This should be equal to the sum of the vertical active and the vertical blank sizes. + For progressive display modes, this field is programmed to the number of lines desired minus one. + For interlaced display modes, this field is programmed with the number of lines desired minus two. + The vertical counter is incremented on the leading edge of the horizontal sync. + For interlaced display, hardware uses this value to calculate the vertical total in each field. + Both even and odd vertical totals are supported. + Programming Notes + Restriction : This register must always be programmed to the same value as the Vertical Blank End. + 15:12 Reserved + 11:0 Vertical Active + This field specifies Vertical Active Display size. + The first vertical active display line is considered pixel number 0. + This field is programmed to the number of lines desired minus one. + For interlaced display, hardware uses this value to calculate the vertical active in each field. + Programming Notes + Restriction : When using the internal panel fitting logic, the minimum vertical active area must be seven + lines. + This register must always be programmed to the same value as the Vertical Blank Start. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 49 + 3.1.5 VBLANK—Vertical Blank + + VBLANK +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: E0010h-E0013h +Name: Transcoder A Vertical Blank +ShortName: TRANS_VBLANK_A +Address: E1010h-E1013h +Name: Transcoder B Vertical Blank +ShortName: TRANS_VBLANK_B +Address: E2010h-E2013h +Name: Transcoder C Vertical Blank +ShortName: TRANS_VBLANK_C +Write Protect by Panel Power Sequencer when panel is connected to this transcoder. +DWord Bit Description +0 31:29 Reserved + 28:16 Vertical Blank End + This field specifies Vertical Blank End position relative to the vertical active display start. + For interlaced display, hardware uses this value to calculate the vertical blank end in each field. + Programming Notes + Restriction : This register must always be programmed to the same value as the Vertical Total. + The minimum vertical blank size is 5 lines. + 15:13 Reserved + 12:0 Vertical Blank Start + This field specifies the Vertical Blank Start position relative to the vertical active display start. + For interlaced display, hardware uses this value to calculate the vertical blank start in each field. + Programming Notes + Restriction : This register must always be programmed to the same value as the Vertical Active + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 50 + 3.1.6 VSYNC—Vertical Sync + + VSYNC +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: E0014h-E0017h +Name: Transcoder A Vertical Sync +ShortName: TRANS_VSYNC_A +Address: E1014h-E1017h +Name: Transcoder B Vertical Sync +ShortName: TRANS_VSYNC_B +Address: E2014h-E2017h +Name: Transcoder C Vertical Sync +ShortName: TRANS_VSYNC_C +Write Protect by Panel Power Sequencer when panel is connected to this transcoder. +DWord Bit Description +0 31:29 Reserved + 28:16 Vertical Sync End + This field specifies the Vertical Sync End position relative to the vertical active display start. + It is programmed with VerticalActive+FrontPorch+Sync-1. + For interlaced display, hardware uses this value to calculate the vertical sync start in each field. + Programming Notes + Restriction : This value must be greater than the vertical sync start and less than Vertical Total. + 15:13 Reserved + 12:0 Vertical Sync Start + This field specifies the Vertical Sync Start position relative to the vertical active display start. + It is programmed with VerticalActive+FrontPorch-1. + For interlaced display, hardware uses this value to calculate the vertical sync end in each field. + Programming Notes + Restriction : This value must be greater than Vertical Active. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 51 + 3.1.7 VSYNCSHIFT— Vertical Sync Shift + + VSYNCSHIFT +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: E0028h-E002Bh +Name: Transcoder A Vertical Sync Shift +ShortName: TRANS_VSYNCSHIFT_A +Address: E1028h-E102Bh +Name: Transcoder B Vertical Sync Shift +ShortName: TRANS_VSYNCSHIFT_B +Address: E2028h-E202Bh +Name: Transcoder C Vertical Sync Shift +ShortName: TRANS_VSYNCSHIFT_C +Write Protect by Panel Power Sequencer when panel is connected to this transcoder. +DWord Bit Description +0 31:13 Reserved + 12:0 Second Field VSync Shift + This value specifies the vertical sync alignment for the start of the interlaced second field, expressed in + terms of the absolute pixel number relative to the horizontal active display start. + This value will only be used if the transcoder is in an interlaced mode. + + Typically, the interlaced second field vertical sync should start one pixel after the point halfway + between successive horizontal syncs, so the value of this register should be programmed to: + horizontal sync start - floor[horizontal total / 2] + (use the actual horizontal sync start and horizontal total values and not the minus one values + programmed into the registers) + + This vertical sync shift only occurs during the interlaced second field. In all other cases the vertical + sync start position is aligned with horizontal sync start. + + + + +3.2 Transcoder M/N Values +These values are used for DisplayPort. +When switching between two refresh rates, both the M1/N1 data and link values and the M2/N2 link +values must be programmed. For dynamic refresh rate control, M1/N1 values are the primary values and +are used for the normal M/N value setting, and M2/N2 values are the secondary values and are used for +the lower power M/N value setting. Selection of M1/N1 or M2/N2 is indicated via MSA from the CPU +display. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 52 + Example calculation of TU, Data M, and Data N: (See DisplayPort specification for exact calculation) +For modes that divide into the link frequency evenly, +Active/TU = Payload/Capacity = Data M/N = dot clock * bytes per pixel / ls_clk * number of lanes +Default value to program TU size is "111111" for TU size of 64. + +Calculation of Link M and Link N: +Link M/N = dot clock / ls_clk +Restriction on clocks and number of lanes: +Number of lanes >= INT(dot clock * bytes per pixel / ls_clk) +Pcdclk * number of lanes >= dot clock * bytes per pixel +Please note that in the DisplayPort specification, dot clock is referred to as strm_clk. + + +3.2.1 DATAM— Data M Value + + DATAM +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Double Buffer Armed By: Writing the LINKN +Address: E0030h-E0033h +Name: Transcoder A Data M value 1 +ShortName: TRANS_DATAM1_A +Address: E0038h-E003Bh +Name: Transcoder A Data M value 2 +ShortName: TRANS_DATAM2_A +Address: E1030h-E1033h +Name: Transcoder B Data M value 1 +ShortName: TRANS_DATAM1_B +Address: E1038h-E103Bh +Name: Transcoder B Data M value 2 +ShortName: TRANS_DATAM2_B +Address: E2030h-E2033h +Name: Transcoder C Data M value 1 +ShortName: TRANS_DATAM1_C +Address: E2038h-E203Bh +Name: Transcoder C Data M value 2 + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 53 + DATAM +ShortName: TRANS_DATAM2_C + DWord Bit Description +0 31 Reserved + Format: MBZ + 30:25 TU Size + This field is the size of the transfer unit, minus one. + 24 Reserved + Format: MBZ + 23:0 Data M value + This field is the m value for internal use of the DDA. + + + + +3.2.2 DATAN— Data N Value + + DATAN +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Double Buffer Armed By: Writing the LINKN +Address: E0034h-E0037h +Name: Transcoder A Data N value 1 +ShortName: TRANS_DATAN1_A +Address: E003Ch-E003Fh +Name: Transcoder A Data N value 2 +ShortName: TRANS_DATAN2_A +Address: E1034h-E1037h +Name: Transcoder B Data N value 1 +ShortName: TRANS_DATAN1_B +Address: E103Ch-E103Fh +Name: Transcoder B Data N value 2 +ShortName: TRANS_DATAN2_B +Address: E2034h-E2037h +Name: Transcoder C Data N value 1 +ShortName: TRANS_DATAN1_C +Address: E203Ch-E203Fh +Name: Transcoder C Data N value 2 +ShortName: TRANS_DATAN2_C + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 54 + DWord Bit Description +0 31:24 Reserved + Format: MBZ + 23:0 Data N value + This field is the n value for internal use of the DDA. + + + + +3.2.3 LINKM— Link M Value + + LINKM +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Double Buffer Armed By: Writing the LINKN +Address: E0040h-E0043h +Name: Transcoder A Link M value 1 +ShortName: TRANS_LINKM1_A +Address: E0048h-E004Bh +Name: Transcoder A Link M value 2 +ShortName: TRANS_LINKM2_A +Address: E1040h-E1043h +Name: Transcoder B Link M value 1 +ShortName: TRANS_LINKM1_B +Address: E1048h-E104Bh +Name: Transcoder B Link M value 2 +ShortName: TRANS_LINKM2_B +Address: E2040h-E2043h +Name: Transcoder C Link M value 1 +ShortName: TRANS_LINKM1_C +Address: E2048h-E204Bh +Name: Transcoder C Link M value 2 +ShortName: TRANS_LINKM2_C + DWord Bit Description +0 31:24 Reserved + Format: MBZ + 23:0 Link M value + This field is the m value for external transmission in the Main Stream Attributes. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 55 + 3.2.4 LINKN— Link N Value + + LINKN +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank +Address: E0044h-E0047h +Name: Transcoder A Link N value 1 +ShortName: TRANS_LINKN1_A +Address: E004Ch-E004Fh +Name: Transcoder A Link N value 2 +ShortName: TRANS_LINKN2_A +Address: E1044h-E1047h +Name: Transcoder B Link N value 1 +ShortName: TRANS_LINKN1_B +Address: E104Ch-E104Fh +Name: Transcoder B Link N value 2 +ShortName: TRANS_LINKN2_B +Address: E2044h-E2047h +Name: Transcoder C Link N value 1 +ShortName: TRANS_LINKN1_C +Address: E204Ch-E204Fh +Name: Transcoder C Link N value 2 +ShortName: TRANS_LINKN2_C +Writes to this register arm M/N registers for this transcoder. +DWord Bit Description +0 31:24 Reserved + Format: MBZ + 23:0 Link N value + This field is the n value for external transmission in the Main Stream Attributes and VB-ID. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 56 + 3.3 Transcoder Video DIP + +3.3.1 VIDEO_DIP_CTL—Video DIP Control + + VIDEO_DIP_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00200900 +Access: R/W +Size (in bits): 32 +Address: E0200h-E0203h +Name: Transcoder A Video Data Island Packet Control +ShortName: VIDEO_DIP_CTL_A +Address: E1200h-E1203h +Name: Transcoder B Video Data Island Packet Control +ShortName: VIDEO_DIP_CTL_B +Address: E2200h-E2203h +Name: Transcoder C Video Data Island Packet Control +ShortName: VIDEO_DIP_CTL_C +Please note that writes to this register take effect immediately. Therefore, it is critical for software to follow the write +and read sequences as described in the bit 31 text. +DWord Bit Description +0 31 Enable Graphics DIP + + Data Island Packet (DIP) is a mechanism that allows up to 36 bytes to be sent over digital port during + VBLANK, according to the HDMI and DisplayPort specifications. This includes header, payload, + checksum and ECC information. Each type of DIP + can be sent once per vsync, once every other vsync, or once. This data can be transmitted on either + transcoder, through any digital port (digital port B, C or D), but not two simultaneously on one + transcoder. + + + Please note that the audio subsystem is also capable of sending Data Island Packets. These packets + are programmed by the audio driver and can be read by in MMIO space via the audio control state + and audio HDMI widget data island registers. + + + + Write sequence: + + + + + 2. + Wait for 1 VSync to ensure completion of any pending DIP transmissions. + 3. + Disable the Video_DIP_type_enable and set the Video_DIP_buffer_index for the DIP being written. + 4. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 57 + VIDEO_DIP_CTL + Set the Video_DIP_access_address to the desired DWORD to be written. + 5. + Write DIP data 1 DWORD at a time. The DIP access address auto-increments with each DWORD + write, wrapping around to address 0 when the max buffer address size has been reached. Please + note that software must write an entire DWORD at a time. + 6. + Enable the DIP type and transmission frequency. + + Read sequence: + + + + 2. + Set the Video_DIP_buffer_index for the DIP being read. + 3. + Set the Video_DIP_access_address to the desired DWORD to be read. + 4. + Read DIP data 1 DWORD at a time. The DIP access address auto-increments with each DWORD + read, wrapping around to address 0 when the max buffer address size has been reached. + Value Name Description + 0b Disable Video DIP is disabled + 1b Enable Video DIP is enabled + + + Programming Notes + Partial DIPs are never sent out while the port is enabled. Disabling the DIP at the same time it is being + transferred will result in the DIP being completed before the function is disabled. + Shutting off the port on which DIP is being transmitted will result in partial transfer of DIP data. There + is no need to switch off the DIP enable bit if the port transmitting DIP is disabled. + + Enabling a DIP function at the same time that the DIP would have been sent out (had it already been + enabled) will result in the DIP being sent on the following frame. + Enabling should only be done after the buffer contents have been written. + + If DIP is enabled but DIP types are all disabled, no DIP is sent. However, a single Null DIP will be sent + at the same point in the stream that DIP packets would have been sent. This is done to keep the port + in HDMI mode, otherwise it would revert to DVI mode. HDMI_CTL HDMI or DVI Select overrides this + behavior. + Restriction : When disabling both the DIP port and DIP transmission, first disable the port and then + disable DIP. + Workaround : Enable_Graphics_DIP (bit 31) and Data_Island_Packet_type_enable for AVI (bit 23) + must be set or cleared in the same write if the HDMI port is already enabled. + 30:26 Reserved + 25 GCP DIP enable + This bit enables the output of the General Control Packet. + GCP is different from other DIPs in that much of the payload is automatically reflected in the packet, + and therefore a DIP buffer for GCP is not needed. + Writes to this bit take effect immediately. + Value Name Description + 0b Disable GCP DIP disabled + 1b Enable GCP DIP enabled + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 58 + VIDEO_DIP_CTL + + Programming Notes + Workaround : Enable this bit before enabling the port when GCP is required, and disable this bit after + disabling the port. + 24:21 Video DIP type enable + These bits enable the output of a given data island packet type. + It can be updated while the port is enabled and is immediately updated (not double-buffered). + Within 2 vblank periods, the DIP is guaranteed to have been transmitted. + Value Name Description + 0001b Enable AVI DIP [Default] + XXX1b Enable AVI Enable AVI DIP + XX1Xb Enable Vendor Enable Vendor-specific DIP + X1XXb Enable Gamut Enable Gamut Metadata Packet + 1XXXb Enable Source Enable Source Product Description DIP + + + Programming Notes + Workaround : Software must enable VS DIP type (initialized to zero or programmed with valid VS + payload) in addition when it is desired to enable AVI + SPD + GMP. + AVI enable (bit 23) and Enable_Graphics_DIP (bit 31) must be set or cleared in the same write if the + HDMI port is already enabled. + AVI should be updated dynamically (without clearing the enable bit) by waiting for vertical blank and + then updating the AVI buffer. + 20:19 Video DIP buffer index + This field is used during programming of different DIPs. + These bits are used as an index to their respective DIP buffers. + The transmission frequency must also be written when programming the buffer. + Value Name Description + 00b AVI AVI DIP (31 bytes of space available) + 01b Vendor-specific Vendor-specific DIP + 10b Gamut Metadata Gamut Metadata Packet + 11b Source Product Source Product Description DIP + 18 Reserved + 17:16 Video DIP frequency + These bits dictate the frequency of Video DIP transmission for the DIP buffer index designated in bits + 20:19. + When writing Video DIP data, this value is also latched when the first DW of the Video DIP is written. + When read, this value reflects the Video DIP transmission frequency for the Video DIP buffer + designated in bits 20:19. + This field is ignored for Gamut Metadata Packet transmission. + Value Name Description + 00b Send Once Send Once + 01b Every VSync Send Every VSync (Default for AVI) + 10b Every Other Vsync Send at least every other VSync + 11b Reserved Reserved + + + Programming Notes + Restriction : Always program AVI to "Send Every Vsync" when enabling AVI. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 59 + VIDEO_DIP_CTL + 15:12 Reserved + Format: MBZ + 11:8 Video DIP buffer size + Default Value: 1001b 9 dwords + Access: RO + This reflects the buffer size in dwords available for the type of Video DIP being indexed by bits 20:19 of + this register, including the header. It is hardwired to the maximum size of a Video DIP, 36 bytes. Please + note that this count includes ECC bytes, which are not writable by software. These bits are immediately + valid after write of the DIP index. + + 7:4 Reserved + Format: MBZ + 3:0 Video DIP access address + Selects the DWORD address for access to the Video DIP buffers. This value is automatically + incremented after each read or write of the Video DIP Data Register. The value wraps back to zero + when it autoincrements past the max address value of 0xF. This field change takes effect immediately + after being written. The read value indicates the current access address. + + + + +3.3.2 VIDEO_DIP_DATA–Video Data Island Packet Data + + VIDEO_DIP_DATA +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W (DWORD access only, no byte access) +Size (in bits): 32 +Address: E0208h-E020Bh +Name: Transcoder A Video Data Island Packet Data +ShortName: VIDEO_DIP_DATA_A +Address: E1208h-E120Bh +Name: Transcoder B Video Data Island Packet Data +ShortName: VIDEO_DIP_DATA_B +Address: E2208h-E220Bh +Name: Transcoder C Video Data Island Packet Data +ShortName: VIDEO_DIP_DATA_C + Programming Notes +Restriction : Writes must be full 32 bit DWORDs only. Byte enables are ignored. +DWord Bit Description +0 31:0 Video DIP DATA + When read, this returns the current value at the location specified in the Video DIP buffer index select + and Video DIP access address fields. + The address index is incremented after each read or write of this register. + DIP data can be read at any time. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 60 + VIDEO_DIP_DATA + Data should be loaded before enabling the transmission through the DIP type enable bit. + + + +Construction of DIP Data: + +Dword Byte3 Byte2 Byte1 Byte0 + + HB2 HB1 HB0 +0 DP : HB3 + HDMI: ECC (RO) + DB3 DB2 DB1 DB0 +1 + + DB7 DB6 DB5 DB4 +2 + + DB11 DB10 DB9 DB8 +3 + + DB15 DB14 DB13 D12 +4 + + DB19 DB18 DB17 DB16 +5 + + DB23 DB22 DB21 DB20 +6 + + DB27 DB26 DB25 DB24 +7 + + ECC byte3 (RO) ECC byte2 (RO) ECC byte1 (RO) ECC byte0 (RO) +8 + +9 DP: ECC byte7 (RO) DP: ECC byte6 (RO) DP: ECC byte5 (RO) DP: ECC byte4 (RO) + HDMI : Reserved HDMI : Reserved HDMI : Reserved HDMI : Reserved + +10 DP: ECC byte11 (RO) DP: ECC byte10 (RO) DP: ECC byte9 (RO) DP: ECC byte8 (RO) + HDMI : Reserved HDMI : Reserved HDMI : Reserved HDMI : Reserved + + Reserved Reserved Reserved Reserved +11 + + Reserved Reserved Reserved Reserved +12 + + Reserved Reserved Reserved Reserved +13 + + Reserved Reserved Reserved Reserved +14 + + Reserved Reserved Reserved Reserved +15 + +HB = Header Byte +DB = Data Byte +DP = DisplayPort + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 61 + 3.3.3 VIDEO_DIP_GCP–Video Data Island Payload GCP + + VIDEO_DIP_GCP +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: E0210h-E0213h +Name: Transcoder A Video Data Island Payload +ShortName: VIDEO_DIP_GCP_A +Address: E1210h-E1213h +Name: Transcoder B Video Data Island Payload +ShortName: VIDEO_DIP_GCP_B +Address: E2210h-E2213h +Name: Transcoder C Video Data Island Payload +ShortName: VIDEO_DIP_GCP_C +DWord Bit Description +0 31:3 Reserved + Format: MBZ + 2 GCP color indication + This bit must be set when in deep color mode. It may optionally be set for 24-bit mode. + It must be set if the sink attached to the transcoder can receive GCP data. + Value Name Description + 0b Don’t Don’t indicate color depth. CD and PP bits in GCP set to zero + Indicate + 1b Indicate Indicate color depth using CD bits in GCP. It will be set depending on programmed + pixel depth in port control register + 1 GCP default phase enable + Indicates the video timings meet alignment requirements such that the following conditions are met: + + Htotal is an even number +  + Hactive is an even number +  + Hsync is an even number +  + Front and back porches for Hsync are even numbers +  + Vsync always starts on an even-numbered pixel within a line in interlaced modes (starting counting + with 0) + + Value Name Description + 0b Clear Default phase bit in GCP is cleared + 1b Require Met Default phase bit in GCP is set. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 62 + VIDEO_DIP_GCP + All requirements must be met before setting this bit + + + +3.4 Transcoder DisplayPort Control + +3.4.1 TRANS_DP_CTL—Transcoder DisplayPort Control + + TRANS_DP_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x60000018 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Depends on bit +Address: E0300h-E0303h +Name: Transcoder A DisplayPort Control +ShortName: TRANS_DP_CTL_A +Address: E1300h-E1303h +Name: Transcoder B DisplayPort Control +ShortName: TRANS_DP_CTL_B +Address: E2300h-E2303h +Name: Transcoder C DisplayPort Control +ShortName: TRANS_DP_CTL_C +This register configures transcoder based DisplayPort logic. This register must be used in conjunction with the +DisplayPort Control registers. +DWord Bit Description +0 31 Transcoder DP Output Enable + This bit determines if this transcoder will output to a DisplayPort. + Value Name Description + 0b Disable Disable the transcoder output to DisplayPort + 1b Enable Enable the transcoder to output to DisplayPort + + + Programming Notes + Restriction : Transcoder DP Port Select needs to be set to 11b (None) when writing a 0b to this bit to + disable transcoder output to DisplayPort. + 30:29 Transcoder DP Port Select + This bit determines which DisplayPort port block will be driven by the DisplayPort output of this + transcoder. Port selection takes place on the Vblank after being written. + Value Name Description + 00b Port B DisplayPort Port B + 01b Port C DisplayPort Port C + 10b Port D DisplayPort Port D + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 63 + TRANS_DP_CTL + 11b None [Default] No port selected + + + Programming Notes + Restriction : This field needs to be set to 11b (None) when writing a 0b to + Transcoder_DP_Output_Enable to disable transcoder output to DisplayPort. + 28:27 Reserved + Format: MBZ + 25:19 Reserved + Format: MBZ + 17:12 Reserved + Format: MBZ + 11:9 Transcoder DP Bits Per Color + This field selects the number of bits per color output on DisplayPorts connected to this transcoder. + Software should enable dithering in the pipe if selecting a pixel color depth higher or lower than the + pixel color depth of the frame buffer. + Value Name Description + 000b 8 bpc 8 bits per color + 001b 10 bpc 10 bits per color + 010b 6 bpc 6 bits per color + 011b 12 bpc 12 bits per color + Others Reserved Reserved + 8:5 Reserved + Format: MBZ + 4:3 Transcoder DP Sync Polarity + Indicates the polarity of Hsync and Vsync to be transmitted in MSA on this transcoder DisplayPort + output. + Value Name Description + 00b Low VS and HS are active low (inverted) + 01b VS Low, HS High VS is active low (inverted), HS is active high + 10b VS High, HS Low VS is active high, HS is active low (inverted) + 11b High [Default] VS and HS are active high + 2:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 64 + 3.5 Analog Port CRT DAC + +3.5.1 DAC_CTL—Analog Port CRT DAC Control + + DAC_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00040000 +Access: R/W +Size (in bits): 32 +Address: E1100h-E1103h +Name: Analog Port CRT DAC Control +ShortName: DAC_CTL +DWord Bit Description +0 31 Port Enable + This bit enables or disables the analog port CRT DAC and syncs outputs. + The CRT DAC disable fuse can block this from enabling. + Value Name Description + 0b Disable Disable the analog port DAC and disable output of syncs + 1b Enable Enable the analog port DAC and enable output of syncs + 30:29 Transcoder Select + Determines which transcoder will feed this DAC port. + Value Name Description + 00b Transcoder A Transcoder A + 01b Transcoder B Transcoder B + 10b Transcoder C Transcoder C + 11b Reserved Reserved + 28:26 Reserved + 25:24 CRT HPD Channel Status + Access: RO + These bits are set when a CRT hot plug or unplug event has been detected and indicate which color + channels were attached. + Write a one to these bits to clear the status. + The rising or falling edges of these bits are ORed together to go to the SDE_ISR CRT hot plug register + bit. + Value Name Description + 00b None No channels attached + 01b Blue Blue channel only is attached + 10b Green Green channel only is attached + 11b Both Both blue and green channel attached + 23 CRT HPD Enable + Hot plug detection is used to set status bits or an interrupt on the connection or disconnection of a CRT + to the analog port CRT DAC. + Value Name Description + 0b Disable CRT hot plug detection is disabled + 1b Enable CRT hot plug detection is enabled + 22 CRT HPD Activation Period + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 65 + DAC_CTL + This bit sets the activation period for the CRT hot plug circuit. + Value Name Description + 0b 64 rawclk 64 rawclk periods + 1b 128 rawclk 128 rawclk periods + 21 CRT HPD Warmup Time + This bit sets the warmup time for the CRT hot plug circuit. + Value Name Description + 0b 4ms Approximately 4ms + 1b 8ms Approximately 8ms + 20 CRT HPD Sampling Period + This bit determines the length of time between sampling periods when the transcoder is disabled. + Value Name Description + 0b 2 seconds Approximately 2 seconds + 1b 4 seconds Approximately 4 seconds + 19:18 CRT HPD Voltage Value + Compare value for Vref to determine whether the analog port is connected to a CRT. + Value Name Description + 00b 40 40 + 01b 50 [Default] 50 + 10b 60 60 + 11b 70 70 (bit 17 must be = 1) + 17 CRT HPD Reference Voltage + Value Name Description + 0b 325mv 325mv + 1b 475mv 475mv (bits 19:18 must be = 11) + 16 Force CRT HPD Trigger + Triggers a CRT hotplug/unplug detection cycle independent of the hot plug detection enable bit. + This bit is automatically cleared after the detection is completed. + The result of this trigger is reflected in the CRT Hot Plug Detection Status. Software must reset status + after a force CRT detect trigger. + Value Name Description + 0b No Trigger No Trigger + 1b Force Trigger Force Trigger + 15:5 Reserved + 4 VSYNC Polarity Control + The output VSYNC polarity is controlled by this bit. + This is used to implement display modes that require inverted polarity syncs and to set the disabled + state of the VSYNC signal. + Value Name Description + 0b Low Active Low + 1b High Active High + 3 HSYNC Polarity Control + The output HSYNC polarity is controlled by this bit. + This is used to implement display modes that require inverted polarity syncs and to set the disabled + state of the HSYNC signal. + Value Name Description + 0b Low Active Low + 1b High Active High + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 66 + DAC_CTL + 2:0 Reserved + + + + +3.6 HDMI Port + +3.6.1 HDMI_CTL—HDMI Port Control + + HDMI_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000018 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Depends on bit +Address: E1140h-E1143h +Name: HDMI Port B Control +ShortName: HDMI_CTL_B +Address: E1150h-E1153h +Name: HDMI Port C Control +ShortName: HDMI_CTL_C +Address: E1160h-E1163h +Name: HDMI Port D Control +ShortName: HDMI_CTL_D +DisplayPort B uses the same physical pins as HDMI/DVI B. Therefore HDMI/DVI B and DisplayPort B cannot be +enabled simultaneously. The same applies for ports C and D. +DWord Bit Description +0 31 Port Enable + Disabling this port will put it in its lowest power state. + Port enable takes place on the Vblank after being written. + Both this bit and the audio output bit of this register must be enabled to send audio over this port. + Value Name Description + 0b Disable Disable and tristates the port interface + 1b Enable Enables the port interface + + + Programming Notes + Workaround : During modeset, for inverted vertical sync mode turn on Port_Enable during the vertical + active region. + 30:29 Transcoder Select + This bit determines from which display transcoder the source data will originate. + Transcoder selection takes place on the Vblank after being written. + Value Name Description + 00b Transcoder A Transcoder A + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 67 + HDMI_CTL + 01b Transcoder B Transcoder B + 10b Transcoder C Transcoder C + 11b Reserved Reserved + 28:26 Color Format + This field selects the number of bits per color sent to a receiver device connected to this port. + Color format takes place on the Vblank after being written. + Color format change must be done as a part of mode set since different color depths require different + pixel clock settings. + Software should enable dithering in the pipe/transcoder if selecting a pixel color depth higher or lower + than the pixel color depth of the frame buffer. + Value Name Description + 000b 8 BPC 8 bits per color + 011b 12 BPC 12 bits per color + Others Reserved Reserved + + + Programming Notes + Workaround (WaEnableHDMI8bpcBefore12bpc) : When enabling HDMI with the 12 BPC mode, + disable HDMI clock gating, enable HDMI with Color Format in 8 BPC mode, switch Color Format to 12 + BPC mode, then restore HDMI clock gating. + + Suggested sequence: + 0. Driver notified that HDMI must be enabled with the 12 bits per color format + 1. Disable HDMI clock gating (see clock gate disable locations below) + 2. Write to HDMI control register with Port Enable = Enable, Color Format = 8 BPC, and other fields + set as needed + 3. Write to HDMI control register with Port Enable = Enable, Color Format = 12 BPC, and other fields + set as needed + 4. Restore HDMI clock gating + + HDMI clock gating for transcoder A is disabled by setting 0xF0060 bit 10 = 1. + HDMI clock gating for transcoder B is disabled by setting 0xF1060 bit 10 = 1. + HDMI clock gating for transcoder C is disabled by setting 0xF2060 bit 10 = 1. + 24 Reserved + 22:19 Reserved + 17:16 Reserved + 15 Port Lane Reversal + This bit reverses the order of the 4 lanes within the port. + Locked once port is enabled. Updates when the port is disabled then re-enabled + Value Name Description + 0b Not reversed Not reversed + 1b Reversed Reversed + 14:12 Reserved + 11:10 Encoding + These bits select among encoding types. + Value Name Description + 10b TMDS TMDS encoding for HDMI/DVI. In this mode, the external HPD pin is used to generate + hotplug. + Others Reserved Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 68 + HDMI_CTL + 9 HDMI or DVI Select + This bit selects between HDMI and DVI modes of operation. + HDMI mode enables a null packet (32 bytes of a value of 0) to be sent when Vsync=1 on this port, + required for HDMI operation. It also enables preambles and guardbands prior to the null packets, in + accordance with the HDMI specification. + Value Name Description + 0b DVI Port will function in DVI mode if no DIP packets are enabled and no audio is present. + 1b HDMI Port will function in HDMI mode. + 8 Reserved + Format: MBZ + 6 Audio Output Enable + This bit directs audio to this port. + When enabled and audio data is available, the audio data will be combined with the video data and + sent over this port. + The status of this bit is used to indicate presence of the HDMI output to the audio driver. + Value Name Description + 0b Disable No audio output on this port + 1b Enable Enable audio on this port + 4:3 Sync Polarity + Indicates the polarity of Hsync and Vsync. + Inverted polarity is transmitted as SYNC-BLANK-SYNC and standard polarity is transmitted as + BLANK-SYNC-BLANK. + For example, if Vsync is not inverted and Hsync is inverted, an Hsync period transmitted during Vsync + would be transmitted as BLANK+VS+HS – BLANK+VS – BLANK+VS+HS. + Value Name Description + 00b VS Low, HS Low VS and HS are active low (inverted) + 01b VS Low, HS High VS is active low (inverted), HS is active high + 10b VS High, HS Low VS is active high, HS is active low (inverted) + 11b VS High, HS High [Default] VS and HS are active high + 2 Port Detected + Access: RO + Read-only bit indicating whether a digital display was detected during initialization. + It signifies the level of the GMBUS port (port 4 for B, port 3 for C, port 5 for D) data line at boot. + This bit is valid regardless of whether the port is enabled. + Value Name Description + 0b Not Detected Port not detected during initialization + 1b Detected Port detected during initialization + 1:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 69 + 3.6.2 HDMI_BUF_CTL—HDMI Buffer Control + + HDMI_BUF_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x01773F30 +Access: R/W +Size (in bits): 32 +Address: FC810h-FC813h +Name: HDMI Buffer Control Lane 0 +ShortName: HDMI_BUF_CTL_0 +Address: FC81Ch-FC81Fh +Name: HDMI Buffer Control Lane 1 +ShortName: HDMI_BUF_CTL_1 +Address: FC828h-FC82Bh +Name: HDMI Buffer Control Lane 2 +ShortName: HDMI_BUF_CTL_2 +Address: FC834h-FC837h +Name: HDMI Buffer Control Lane 3 +ShortName: HDMI_BUF_CTL_3 +Address: FCC00h-FCC03h +Name: HDMI Buffer Control Lane 4 +ShortName: HDMI_BUF_CTL_4 +Address: FCC0Ch-FCC0Fh +Name: HDMI Buffer Control Lane 5 +ShortName: HDMI_BUF_CTL_5 +Address: FCC18h-FCC1Bh +Name: HDMI Buffer Control Lane 6 +ShortName: HDMI_BUF_CTL_6 +Address: FCC24h-FCC27h +Name: HDMI Buffer Control Lane 7 +ShortName: HDMI_BUF_CTL_7 +Address: FD000h-FD003h +Name: HDMI Buffer Control Lane 8 +ShortName: HDMI_BUF_CTL_8 +Address: FD00Ch-FD00Fh +Name: HDMI Buffer Control Lane 9 +ShortName: HDMI_BUF_CTL_9 +Address: FD018h-FD01Bh +Name: HDMI Buffer Control Lane 10 + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 70 + HDMI_BUF_CTL +ShortName: HDMI_BUF_CTL_10 +Address: FD024h-FD027h +Name: HDMI Buffer Control Lane 11 +ShortName: HDMI_BUF_CTL_11 +Lanes 0-3 are used by port B. + Lanes 4-7 are used by port C. + Lanes 8-11 are used by port D. + Programming Notes +The default values are not the optimal values. + Correct values should be programmed prior to enabling HDMI. + See the HDMI Buffer Control Register Settings table for the correct values to use. + DWord Bit Description +0 31:25 Reserved + Format: MBZ + 24:17 Driver Swing Control + This field modulates the output swing while maintaining the pre-emphasis level. + Value Name + 01100110b 0.90x + 01110111b 0.95x + 10001000b 1.00x + 10011001b 1.05x + 10101010b 1.10x + 10111011b 1.15x [Default] + 11001100b 1.20x + 11011101b 1.25x + 11101110b 1.30x + 11111111b 1.35x + 16:3 Driver Enable and Pre-Emphasis Control + Default Value: 10011111100110b + This field sets the Driver Enable/Pre-emphasis Settings. + Programming Notes + Refer to the HDMI Buffer Control Register Settings table for valid settings. + 2:0 Reserved + Format: MBZ + + +HDMI Buffer Control Register Settings: +Approximate Swing Approximate Preemp Register Value Notes +800mV 4.0dB 0x01773F30 Register default +800mV 0.0dB 0x01986F00 HDMI Active Level Shifter Optimized Setting +800mV 3.0dB 0x01FFFF28 HDMI Cost Reduced Level Shifter Optimized Setting +1000mV 0.0dB 0x01993F00 Alternate HDMI Setting +900mV 0.0dB 0x01987D00 Alternate HDMI Setting +775mV 0.0dB 0x01987300 Alternate HDMI Setting +750mV 0.0dB 0x01986D00 Alternate HDMI Setting +725mV 0.0dB 0x01986B00 Alternate HDMI Setting +700mV 0.0dB 0x01986700 Alternate HDMI Setting +400mV 0.0dB 0x01982000 Level 0 Preemp 0 +400mV 3.5dB 0x01981710 Level 0 Preemp 1 + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 71 + Approximate Swing Approximate Preemp Register Value Notes +400mV 6.0dB 0x0198DF48 Level 0 Preemp 2 +400mV 9.5dB 0x01DCBF70 Level 0 Preemp 3 +600mV 0.0dB 0x01981700 Level 1 Preemp 0 +600mV 3.5dB 0x01996F40 Level 1 Preemp 1 +600mV 6.0dB 0x01FF3F68 Level 1 Preemp 2 +800mV 0.0dB 0x01983D00 Level 2 Preemp 0 +800mV 3.5dB 0x01FF3F30 Level 3 Preemp 1 +1200mV 0.0dB 0x01FFFF00 Level 4 Preemp 0 + + + +3.7 LVDS Port + +3.7.1 LVDS_CTL—LVDS Port Control + + LVDS_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W Protect +Size (in bits): 32 +Address: E1180h-E1183h +Name: LVDS Port Control +ShortName: LVDS_CTL +Write Protect by Panel Power Sequencer +DWord Bit Description +0 31 LVDS Port Enable + When disabled the LVDS port is inactive and in it’s low power state. + Enabling the LVDS port changes the way that the PLL for this transcoder is programmed. + This bit must be set before the display PLL is enabled and the port is power sequenced on using the + panel power sequencing logic. + Value Name Description + 0b Disable The port is disabled and all LVDS pairs are powered down. + 1b Enable The port is enabled. + The LVDS disable fuse can block this port from enabing. + + + Programming Notes + Workaround : LVDS clock gating must be disabled (South Display Unit Clock Gating Disable bits #30 + and #14 in 0xC2020 set to ‘1’) at boot and remained disabled before enabling dual channel LDVS + mode. + 30:29 LVDS Port Transcoder Select + This field selects which transcoder LVDS is attached to. + Value Name Description + 00b Transcoder A The port gets data from Transcoder A + 01b Transcoder B The port gets data from Transcoder B + 10b Transcoder C The port gets data from Transcoder C + 11b Reserved Reserved + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 72 + LVDS_CTL + + Programming Notes + Workaround : The transcoder select state must be preserved when disabling the port. The transcoder + select may be updated after the port has been disabled. + 28:25 Reserved + 24 Data Format Select + Combined with the other control bits it selects the LVDS data format. Other control bits in this register + determine if two channel is enabled and 18 or 24 bit color is enabled. + Value Name Description + 0b 1x18.0, 2x18.0, 1x24.0 or 2x24.0 1x18.0, 2x18.0, 1x24.0 or 2x24.0 + 1b 1x24.1 or 2x24.1 1x24.1 or 2x24.1 + 23 LE Control Enable + This bit is used when the second channel control signal field indicates that we are using the LE instead + of HS and the two channel mode is enabled. In single channel mode, this bit has no effect. + Value Name Description + 0b Send 0 Send 0 on second channel HS (B2<2>) + 1b Send 1 Send 1 on second channel HS + 22 LF Control Enable + This bit is used when the second channel control signal field indicates that we are using the LF instead + of VS and two channel mode is enabled. In single channel mode, this bit has no effect. + Value Name Description + 0b Send 0 Send 0 on second channel VS (B2<3>) + 1b Send 1 Send 1 on second channel VS + 21 VSYNC Polarity + This controls the polarity of the VSYNC indicator that is sent over the LVDS connection. Panels may + require one or the other polarity or work with either polarity. + Value Name Description + 0b No Invert No inversion (1=active) + 1b Invert Invert the sense (0=active) + 20 HSYNC Polarity + (LP_Invert) This controls the polarity of the HSYNC indicator that is sent over the LVDS connection. + Panels may require one or the other polarity or work with either polarity. + Value Name Description + 0b No Invert No inversion (1=active) + 1b Invert Invert the sense (0=active) + 19 DE Invert + This controls the polarity of the DE indicator that is sent over the LVDS connection. + Value Name Description + 0b No Invert No inversion of DE (1=active) + 1b Invert Invert the sense of DE (0=active) + 18:17 Second Channel Control Signals + This bit only applies to the two channel modes of operation it has no effect in single channel modes. + Value Name Description + 00b Send Send DE, HS, VS on second channel if enabled + 01b Reserved + 10b Do not send Do not send DE, HS, VS on second channel use zero instead + 11b DE 0 Use DE=0, HS=LE, VS=LF on second channel + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 73 + LVDS_CTL + 16 Channel Reserved Bits + Value Name Description + 0b Send 0 Send 0 for the channel reserved bits + 1b Send Duplicate Send duplicate data bit for reserved bits + 15:11 Reserved + 10 Buffer Power Down State + This bit selects the state of the LVDS buffers during a powered down state caused by the power + sequence logic power down. + This selection will be made based on the connected panel requirements. + Value Name Description + 0b Zero Zero Volts (Driven on both lines of the pairs) + 1b Tri-State Tri-State (High impedance state) + 9:8 ClkA0 A2 Control + This field controls the A0-A2 data pairs and CLKA. + It sets the highest level of activity that is allowed on these lines when the panel is powered on. + Power sequencing for LVDS connected panels overrides the control. When the power sequencer is in + the power down mode all signals are in the power down state. + Value Name Description + 00b Power Down Power Down all A channel signals including A3 (0V) + 01b Power Up Data 0 Power up – A0, A1, A2 Data bits forced to 0,Timing active, Clock Active + 10b Reserved + 11b Power Up All Active Power up – Data lines and clock active + 7:6 Eight bit ch A3 B3 Control + This field can control both the A3 and B3 data pairs. + Enabling those pairs indicates the selection of 8-bit per color channel mode. + It sets the highest level of activity that is allowed on these lines when the panel is powered on. + The A3 pair will only be powered up if both this field and the A0, A1, A2, CLKA field indicates that the + pair should be powered up and will only be active if both indicate that it should be active. + The B3 pair will only be powered up if both this field and the B0, B1, B2, (B3) field indicates that the + pair should be powered up and will only be active if both indicate that it should be active. + Power sequencing for LVDS connected panels overrides the control. When the power sequencer is in + the power down mode all signals are in the power down state. + Value Name Description + 00b Power Down Power Down all signals A3, B3 (common mode) + 01b Power Up Data 0 Power up – A3, (B3) Data (pixel data not control) lines forced to 0 output + 10b Reserved + 11b Power Up Data Active Power up – A3, (B3) Data lines active + 5:4 Two channel mode ClkB Control + When in two channel mode, this field controls the CLKB pair. + It sets the highest level of activity that is allowed on these lines when the panel is powered on. + The CLKB pair should only be powered up if the B0, B1, B2, (B3) field indicates that the second + channel should be powered up and will only be active if both indicate that it should be active. + Power sequencing for LVDS connected panels overrides the control. + Value Name Description + 00b Power Down Power Down CLKB (common mode) + 01b Power Up CLKB 0 Power up – CLKB Forced to 0 + 10b Reserved + 11b Power Up CLKB Active Power up – Clock B active + 3:2 Two channel mode B0 B2 Control + This field controls both the set B0-B2 data pairs. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 74 + LVDS_CTL + It sets the highest level of activity that is allowed on these lines when the panel is powered on. + Power sequencing for LVDS connected panels overrides the control. + During single channel operation (1x18.0), these bits need to be both zero. + Two channel operation is selected by setting them to ones. + The second clock can be optionally enabled or disabled by the two channel mode ClkB control field. + Value Name Description + 00b Power Down Power Down all signals including B3 and CLKB + 01b Power Up Data 0 Power up – B0, B1, B2, Data lines forced to 0, timing is active + 10b Reserved + 11b Power Up Data Active Power up – Data lines active (color and timing) + 1 Port Detected + Access: RO + Read-only bit indicating whether LVDS was detected during initialization. It signifies the level of the + GMBUS port 2 (LVDS) data line at boot. This bit is valid regardless of whether the port is enabled. + Value Name Description + 0b Not Detected LVDS not detected during initialization + 1b Detected LVDS detected during initialization + 0 Reserved + + + + +3.8 DisplayPort + +3.8.1 DP_CTL—DisplayPort Control + + DP_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Depends on bit +Address: E4100h-E4103h +Name: DisplayPort B Control +ShortName: DP_CTL_B +Address: E4200h-E4203h +Name: DisplayPort C Control +ShortName: DP_CTL_C +Address: E4300h-E4303h +Name: DisplayPort D Control +ShortName: DP_CTL_D +Port enable is write protected by Panel Power Sequencer when panel is connected to this port. +DisplayPort B uses the same physical pins as HDMI/DVI B. Therefore HDMI/DVI B and DisplayPort B cannot be + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 75 + DP_CTL +enabled simultaneously. The same applies for ports C and D. +DWord Bit Description +0 31 DisplayPort Enable + Disabling this port will put it in its lowest power state. Port enable takes place on the Vblank after being + written. + Value Name Description + 0b Disable Disable and tristate the DisplayPort interface + 1b Enable Enable the DisplayPort interface + + + Programming Notes Project + Workaround : When panel power sequencing is selected for DisplayPort D, the clock gating + disable register SCLKGATE_DIS 0xC2020 bit 14 must be set to 1b prior to enabling + DisplayPort D, then cleared to 0b after disabling DisplayPort D. + 30:28 Reserved + Format: MBZ + 27:25 Voltage swing level set + These bits are used for setting the voltage swing for pattern 1, defined as Vdiff_pp in the DisplayPort + specification. + Value Name Description + 000b 0.4V 0.4V + 001b 0.6V 0.6V + 010b 0.8V 0.8V + 011b 1.2V 1.2V + Others Reserved Reserved + 24:22 Preemphasis level set + These bits are used for setting link pre-emphasis for pattern 2, as defined in the DisplayPort + specification. + Value Name Description + 000b 0dB No pre-emphasis + 001b 3.5dB 3.5dB pre-emphasis (1.5x) + 010b 6dB 6dB pre-emphasis (2x) + 011b 9.5dB 9.5dB pre-emphasis (3x) + Others Reserved Reserved + 21:19 Port Width Selection + This bit selects the number of lanes to be enabled on the DisplayPort link. + Port width change must be done as a part of mode set. Locked once port is enabled. Updates when + the port is disabled then re-enabled. + Value Name Description + 000b x1 x1 Mode + 001b x2 x2 Mode + 011b x4 x4 Mode + Others Reserved Reserved + 18:16 Reserved + Format: MBZ + 15 Port reversal + Enables lane reversal within the port: lane 0 mapped to lane 3, lane 1 mapped to lane 2, etc. + Port reversal does not affect AUX channel lane mapping. + Locked once port is enabled. Updates when the port is disabled then re-enabled + Value Name Description + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 76 + DP_CTL + 0b Not Reversed Port not reversed + 1b Reversed Port reversed + 14:11 Reserved + Format: MBZ + 10:8 Link training pattern enable + These bits are used for link initialization as defined in the DisplayPort specification. + The link must first be configured prior to sending training patterns. + Value Name Description + 000b Pattern 1 Pattern 1 enabled + 001b Pattern 2 Pattern 2 enabled + 010b Idle Idle Pattern enabled + 011b Normal Link not in training: Send normal pixels + Others Reserved Reserved + + + Programming Notes + Restriction : When enabling the port, it must be turned on with pattern 1 enabled. When retraining, the + port must be disabled, then re-enabled with pattern 1 enabled. + 6 Audio Output Enable + This bit enables audio output on this port. + It may be enabled or disabled only when the link training is complete and set to "Normal". + Value Name Description + 0b Disable Audio output disabled + 1b Enable Audio output enabled + 4:3 Reserved + Format: MBZ + 2 Port Detected + Access: RO + Read-only bit indicating whether a digital display was detected during initialization. + It signifies the level of the detect pin (GMBUS port 4 for port B, GMBUS port 3 for port C, GMBUS port + 5 for port D) at boot. + This bit is valid regardless of whether the port is enabled. + Value Name Description + 0b Not Detected Digital display not detected during initialization + 1b Detected Digital display detected during initialization + 1:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 77 + 3.8.2 DP_AUX_CTL—DisplayPort AUX Channel Control + + DP_AUX_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00050000 +Access: R/W Special +Size (in bits): 32 +Address: E4110h-E4113h +Name: DisplayPort B AUX Channel Control +ShortName: DP_AUX_CTL_B +Address: E4210h-E4213h +Name: DisplayPort C AUX Channel Control +ShortName: DP_AUX_CTL_C +Address: E4310h-E4313h +Name: DisplayPort D AUX Channel Control +ShortName: DP_AUX_CTL_D +DWord Bit Description +0 31 Send Busy + Setting this bit to a one initiates the transaction, when read this bit will be a 1 until the transmission + completes. + The transaction is completed when the response is received or when a timeout occurs. + Do not write a 1 again until transaction completes. Writes of 0 will be ignored. + Value Name + 0b Not Busy + 1b Send or Busy + + + Programming Notes + Do not change any fields while Send/Busy bit 31 is asserted. + 30 Done + Access: R/WC + A sticky bit that indicates the transaction has completed. + Write a 1 to this bit to clear the event. + Value Name + 0b Not done + 1b Done + 29 Interrupt on Done + Enable an interrupt in the hotplug status register when the transaction completes or times out. + Value Name + 0b Enable + 1b Disable + 28 Time out error + Access: R/WC + A sticky bit that indicates the transaction has timed out. + Write a 1 to this bit to clear the event. + Value Name + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 78 + DP_AUX_CTL + 0b Not error + 1b Error + 27:26 Time out timer value + Used to determine how long to wait for receiver response before timing out. + Value Name Description + 00b 400us 400us + 01b 600us 600us + 10b 800us 800us + 11b 1600us 1600us + 25 Receive error + Access: R/WC + A sticky bit that indicates that the data received was corrupted, not in multiples of a full byte, or more + than 20 bytes. + Write a 1 to this bit to clear the event. + Value Name + 0b Not error + 1b Error + 24:20 Message Size + This field is used to indicate the total number bytes to transmit (including the header). It also indicates + the number of bytes received in a transaction (including the header). + This field is valid only when the done bit is set, and if timeout or receive error has not occurred. + Sync/Stop are not part of the message or the message size. + Reads of this field will give the response message size. The read value will not be valid while + Send/Busy bit 31 is asserted. + Message sizes of 0 or >20 are not allowed. + 19:16 Precharge Time + Default Value: 0101b 10us + This field determines the precharge time for the Aux Channel drivers. During this time the Aux Channel + will drive the SYNC pattern. + Every microsecond gives one additional SYNC pulse beyond the hard coded 26 SYNC pulses. + The value is the number of microseconds times 2. + Default is 5 decimal which gives 10us of precharge which is 10 extra SYNC pulses for a total of 36. + Example: For 10us precharge, program 5 (10us/2us). + + 10:0 2X Bit Clock divider + Used to determine the 2X bit clock the Aux Channel logic runs on. + This value divides the input clock frequency down to 2X bit clock rate. + For the 125 MHz input clock and desired 2MHz 2X bit clock, program 63 (125MHz/2MHz). + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 79 + 3.8.3 DP_AUX_DATA—DisplayPort AUX Channel Data + + DP Aux Channel Data Format +Project: +Size (in bits): 32 +Default Value: 0x00000000 + DWord Bit Description +0 31:0 AUX CH DATA + A DWord of the message. + Writes give the data to transmit during the transaction. The MSbyte is transmitted first. + Reads will give the response data after transaction complete. + + + + + DP_AUX_DATA +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 5x32 +Address: E4114h-E4127h +Name: DisplayPort B AUX Channel Data +ShortName: DP_AUX_DATA_[1-5]_B +Address: E4214h-E4227h +Name: DisplayPort C AUX Channel Data +ShortName: DP_AUX_DATA_[1-5]_C +Address: E4314h-E4327h +Name: DisplayPort D AUX Channel Data +ShortName: DP_AUX_DATA_[1-5]_D +The read value will not be valid while the DisplayPort Aux Channel Control Register Send/Busy bit is asserted. + DWord Bit Description +0 31:0 AUX CH DATA1 + Format: DP Aux Channel Data Format +1 31:0 AUX CH DATA2 + Format: DP Aux Channel Data Format +2 31:0 AUX CH DATA3 + Format: DP Aux Channel Data Format +3 31:0 AUX CH DATA4 + Format: DP Aux Channel Data Format +4 31:0 AUX CH DATA5 + Format: DP Aux Channel Data Format + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 80 + 3.8.4 DP_BUFTRANS—DisplayPort Buffer Translation + + DisplayPort Buffer Translation Format +Project: +Size (in bits): 32 +Default Value: 0x00000000 + DWord Bit Description +0 31:28 Reserved + Format: MBZ + 27:19 OE + These bits select the OE vswing level + Value Name + [0,511] + 18:17 Reserved + Format: MBZ + 16:12 Pre Emphasis + These bits select the pre-emphasis level + Value Name + [0,31] + 11:10 Reserved + Format: MBZ + 9:6 P current drive + These bits select the P current drive value + Value Name + [0,15] + 5:4 Reserved + Format: MBZ + 3:0 N current drive + These bits select the N current drive value + Value Name + [0,15] + + + +Programming Requirements: + Offset Value + DP mode + +L1 0dB 0xE4F00 + 0x0100030C + +L1 3.5dB 0xE4F04 + 0x00B8230C + +L1 6dB 0xE4F08 + 0x06F8930C + +L1 9.5dB 0xE4F0C + 0x05F8E38E + +L2 0dB 0xE4F10 + 0x00B8030C + +L2 3.5dB 0xE4F14 + 0x0B78830C + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 81 + Offset Value + DP mode + +L2 6dB 0xE4F18 + 0x09F8D3CF + +L3 0dB 0xE4F1C + 0x01E8030C + +L3 3.5dB 0xE4F20 + 0x09F863CF + +L4 0 dB 0xE4F24 + 0x0FF803CF + + + + + Vswing 0dB 3.5dB 6dB 9.5dB + pre-emphasis pre-emphasis pre-emphasis pre-emphasis + + 400mV DWord 0 DWord 1 DWord 2 DWord 3 + Not supported + 600mV DWord 4 DWord 5 Dword 6 + Not supported Not supported + 800mV Dword 7 Dword 8 + Not supported Not supported Not supported + 1200mV Dword 9 + + + + + DP_BUFTRANS +Register MMIO: 0/2/0 +Space: +Project: +Default 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x00000000, 0x00000000, 0x00000000 +Access: R/W +Size (in bits): 10x32 +Address: E4F00h-E4F27h +Name: DP Buffer Translation +ShortName: DP_BUFTRANS_[0-9] +These registers define current drive, pre-emphasis and voltage swing buffer programming required for the different +voltage swing and pre-emphasis settings in the DisplayPort Control. + The default values are not the optimal values. See the programming notes for the correct values to use. + DWord Bit Description +0 31:0 Vswing400mV Pre0.0dB + Default Value: 0100038Eh + Format: DisplayPort Buffer Translation Format + + + Programming Notes + Recommended programming is 0100_030Ch +1 31:0 Vswing400mV Pre3.5dB + Default Value: 00B8338Eh + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 82 + DP_BUFTRANS + Format: DisplayPort Buffer Translation Format + + + Programming Notes + Recommended programming is 00B8_230Ch +2 31:0 Vswing400mV Pre6.0dB + Default Value: 0178838Eh + Format: DisplayPort Buffer Translation Format + + + Programming Notes + Recommended programming is 06F8_930Ch +3 31:0 Vswing400mV Pre9.5dB + Default Value: 09F8E38Eh + Format: DisplayPort Buffer Translation Format + + + Programming Notes + Recommended programming is 05F8_E38Eh +4 31:0 Vswing600mV Pre0.0dB + Default Value: 00B8038Eh + Format: DisplayPort Buffer Translation Format + + + Programming Notes + Recommended programming is 00B8_030Ch +5 31:0 Vswing600mV Pre3.5dB + Default Value: 0978838Eh + Format: DisplayPort Buffer Translation Format + + + Programming Notes + Recommended programming is 0B78_830Ch +6 31:0 Vswing600mV Pre6.0dB + Default Value: 09F8B38Eh + Format: DisplayPort Buffer Translation Format + + + Programming Notes + Recommended programming is 09F8_D3CFh +7 31:0 Vswing800mV Pre0.0dB + Default Value: 0178038Eh + Format: DisplayPort Buffer Translation Format + + + Programming Notes + Recommended programming is 01E8_030Ch +8 31:0 Vswing800mV Pre3.5dB + Default Value: 09F8638Eh + Format: DisplayPort Buffer Translation Format + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 83 + DP_BUFTRANS + + Programming Notes + Recommended programming is 09F8_63CFh +9 31:0 Vswing1200mV Pre0.0dB + Default Value: 09F8038Eh + Format: DisplayPort Buffer Translation Format + + + Programming Notes + Recommended programming is 0FF8_03CFh + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 84 + 4. South Display Engine Audio +4.1 Audio Programming Sequence +The following HDMI and DisplayPort audio programming sequences are for use when enabling or +disabling audio or temporarily disabling audio during a display mode set. +The audio codec and audio controller disable sequences must be followed prior to disabling the +transcoder or port in a display mode set. +The audio codec and controller enable sequences can be followed after the transcoder is enabled and the +port is enabled and completed link training (not sending TP1, TP2, or Idle). +The audio controller and audio codec sequences may be done in parallel or serial. In general, the change +in ELDV/PD in the codec sequence will generate an unsolicited response to the audio controller driver to +indicate that the controller sequence should start, but other mechanisms may be used. + + +Audio codec disable sequence: + + Disable sample fabrication +  Set AUD_MISC_CTRL Sample_Fabrication_EN (bit 2) to “0”. +  Disable timestamps +  Set AUD_CONFIG N_value_index (bit 29) to "0" for HDMI or "1" for DisplayPort. +  Set N_programming_enable (bit 28) to "1" +  Set Upper_N_value and Lower_N_value (bits 28:20, 15:4) to all "0"s. + Disable ELDV and ELD buffer +  Set AUD_CNTRL_ST2 ELD_valid (bit 0, 4, or 8 based on which port is used) to "0" +  Wait for 2 vertical blanks + Optional: Disable audio PD (Presence Detect) +  Software may choose to skip this in order to keep PD enabled during a resolution switch. +  Set the port control register (HDMI_CTL or DP_CTL) Audio_Output_Enable (bit 6) to "0". + + +Audio controller disable sequence: + Program Stream ID to 0 – Verb ID 706 + Disable audio info frames transmission – Verb ID 732 + Disable Digen – Verb ID 70D + Program the codec to D3 state if needed. + Audio driver may stop the audio controller DMA engine at this point if needed, but not required. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 85 + Audio codec enable sequence: + +  Enable audio Presence Detect +  Set the port control register (HDMI_CTL or DP_CTL) Audio_Output_Enable (bit 6) to "1". +  Wait for 1 vertical blank +  Load ELD buffer and Enable ELDV +  Set AUD_CNTRL_ST2 ELD_valid (bit 0, 4, or 8 based on which port is used) to "1". +  Enable timestamps +  Set AUD_CONFIG N_value_index (bit 29) to "0" for HDMI or "1" for DisplayPort. +  Set N_programming_enable (bit 28) to "0". +  Program Upper_N_value and Lower_N_value (bits 28:20, 15:4) if a non-default N value is + needed. +  Enable sample fabrication if this feature is needed +  Set AUD_MISC_CTRL Sample_Fabrication_EN (bit 2) to “1”. + + +Audio controller enable sequence: + + Program the codec to D0 state if in D3 state. + Program Stream ID to non zero – Verb ID 706 + Enable audio info frames transmission – Verb ID 732 + Enable Digen – Verb ID 70D + If audio controller DMA engine is stopped, audio driver can start the DMA engine at this point. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 86 + 4.2 Audio Configuration + +4.2.1 AUD_CONFIG—Audio Configuration + + AUD_CONFIG +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: E5000h-E5003h +Name: Audio Configuration Transcoder A +ShortName: AUD_CONFIG_A +Address: E5100h-E5103h +Name: Audio Configuration Transcoder B +ShortName: AUD_CONFIG_B +Address: E5200h-E5203h +Name: Audio Configuration Transcoder C +ShortName: AUD_CONFIG_C +This register configures the audio output. +DWord Bit Description +0 31:30 Reserved + 29 N value Index + Value Name Description + 0b HDMI N value read on bits 27:20 and 15:4 reflects HDMI N value. Bits 27:20 and 15:4 are + programmable to any N value – default h7FA6. + 1b DisplayPort N value read on bits 27:20 and 15:4 reflects DisplayPort N value. Set this bit to 1 + before programming N value register. When this bit is set to 1, 27:20 and 15:4 will + reflect the current N value – default h8000. + 28 N programming enable + This bit enables programming of N values for non-CEA modes. Please note that the Transcoder to + which audio is attached must be disabled when changing this field. + 27:20 Upper N value + These are bits [19:12] of programmable N values for non-CEA modes. Bit 29 of this register must also + be written in order to enable programming. Please note that the Transcoder to which audio is attached + must be disabled when changing this field. + This register can also be used to program N value for DisplayPort for a specific Port. Default value for + N when bit 29 is set to 0 is h7FA6 + 19:16 Pixel Clock HDMI + This is the target frequency of the CEA/HDMI video mode to which the audio stream is added. This + value is used for generating N_CTS packets. + This refers to only HDMI Pixel clock and does not refer to DisplayPort Link clock. DisplayPort Link + clock does not require this programming. + Note: The Transcoder on which audio is attached must be disabled when changing this field. + Value Name Description + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 87 + AUD_CONFIG + 0000b 25.2 / 1.001 MHz 25.2 / 1.001 MHz + 0001b 25.2 MHz 25.2 MHz (Program this value for pixel clocks not listed in this field) + 0010b 27 MHz 27 MHz + 0011b 27 * 1.001 MHz 27 * 1.001 MHz + 0100b 54 MHz 54 MHz + 0101b 54 * 1.001 MHz 54 * 1.001 MHz + 0110b 74.25 / 1.001 MHz 74.25 / 1.001 MHz + 0111b 74.25 MHz 74.25 MHz + 1000b 148.5 / 1.001 MHz 148.5 / 1.001 MHz + 1001b 148.5 MHz 148.5 MHz + Others Reserved Reserved + 15:4 Lower N value + These are bits [11:0] of programmable N values for non-CEA modes. Bit 29 of this register must also + be written in order to enable programming. Please note that the Transcoder to which audio is attached + must be disabled when changing this field. + This register can also be used to program N value for DisplayPort for a specific Port. Default value for + N when bit 29 is set to 0 is h7FA6 + 2:0 Reserved + + + + +4.2.2 AUD_CTS_ENABLE – Audio CTS Programming Enable + + AUD_CTS_ENABLE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: E5028h-E502Bh +Name: Audio CTS Programming Enable Transcoder A +ShortName: AUD_CTS_ENABLE_A +Address: E5128h-E512Bh +Name: Audio CTS Programming Enable Transcoder B +ShortName: AUD_CTS_ENABLE_B +Address: E5228h-E522Bh +Name: Audio CTS Programming Enable Transcoder C +ShortName: AUD_CTS_ENABLE_C +These values are returned from the device as the Subordinate Node Count response to a Get Root Node command. +DWord Bit Description +0 31:22 Reserved + 21 CTS M value Index + Value Name Description + 0b CTS CTS value read on bits 23:4 reflects CTS value. Bit 23:4 is programmable to any CTS + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 88 + AUD_CTS_ENABLE + value. default is 0 + 1b M M value read on bits 21:4 reflects DisplayPort M value. Set this bit to 1 before + programming M value register. When this is set to 1 23:4 will reflect the current N value + 20 Enable CTS or M programming + When set will enable CTS or M programming. + 19:0 CTS programming + These are bits [19:0] of programmable CTS values for non-CEA modes. Bit 21 of this register must also + be written in order to enable programming. Please note that the Transcoder to which audio is attached + must be disabled when changing this field. + + + + +4.2.3 AUD_MISC_CTRL—Audio MISC Control + + AUD_MISC_CTRL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000040 +Access: RO +Size (in bits): 32 +Address: E5010h-E5013h +Name: Audio Misc Control Converter A +ShortName: AUD_MISC_CTRL_A +Address: E5110h-E5113h +Name: Audio Misc Control Converter B +ShortName: AUD_MISC_CTRL_B +Address: E5210h-E5213h +Name: Audio Misc Control Converter C +ShortName: AUD_MISC_CTRL_C +DWord Bit Description +0 31:9 Reserved + Format: MBZ + 7:4 Output Delay + Default Value: 0100b 4 samples + The number of samples between when the sample is received and when it appears as an analog signal + at the pin. + + 3 Reserved + Format: MBZ + 2 Sample Fabrication EN bit + Access: R/W + This bit indicates whether internal fabrication of audio samples is enabled during a link underrun. + Value Name Description + 0b Disable Audio fabrication disabled + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 89 + AUD_MISC_CTRL + 1b Enable Audio fabrication enabled + 0 Reserved + Format: MBZ + + + + +4.2.4 AUD_VID_DID—Audio Vendor ID / Device ID + + AUD_VID_DID +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x80862805 +Access: RO +Size (in bits): 32 +Address: E5020h-E5023h +Name: Audio Vendor ID / Device ID +ShortName: AUD_VID_DID +These values are returned from the device as the Vendor ID/ Device ID response to a Get Root Node command. +DWord Bit Description +0 31:16 Vendor ID + Default Value: 8086h + Used to identify the codec within the PnP system. + This field is hardwired within the device. + + 15:0 Device ID + Constant used to identify the codec within the PnP system. This field is set by the device hardware. + Value Name Description Project + 2805h [Default] Cougarpoint + 2806h [Default] Pantherpoint + + + + +4.2.5 AUD_RID—Audio Revision ID + + AUD_RID +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: E5024h-E5027h +Name: Audio Revision ID +ShortName: AUD_RID + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 90 + AUD_RID +These values are returned from the device as the Revision ID response to a Get Root Node command. + DWord Bit Description +0 31:24 Reserved + 15:8 Revision ID + The vendor’s revision number for this given Device ID. + This field is hardwired within the device. + Value Name + 00000000b + 7:0 Stepping ID + An optional vendor stepping number within the given Revision ID. + This field is hardwired within the device. + Value Name + 00000000b + + + + +4.2.6 AUD_PWRST—Audio Power State + + Audio Power State Format +Project: +Size (in bits): 2 +Default Value: 0x00000003 + DWord Bit Description +0 1:0 Power State + Value Name Description + 00b D0 D0 + 01b,10b Unsupported Unsupported + 11b D3 [Default] D3 + + + + + AUD_PWRST +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x0FFFFFFF +Access: RO +Size (in bits): 32 +Address: E504Ch-E504Fh +Name: Audio Power State +ShortName: AUD_PWRST +These values are returned from the device as the Power State response to a Get Audio Function Group command. + DWord Bit Description +0 31:28 Reserved + 27:26 Func Grp Dev PwrSt Curr + Format: Audio Power State Format + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 91 + AUD_PWRST + Function Group Device current power state + + 25:24 Func Grp Dev PwrSt Set + Format: Audio Power State Format + Function Group Device power state that was set + + 23:22 ConvC Widget PwrSt Curr + Format: Audio Power State Format + ConverorC Widget current power state + + 21:20 ConvC Widget PwrSt Req + Format: Audio Power State Format + ConverorC Widget power state that was requested by audio software + + 19:18 ConvertorB Widget PwrSt Curr + Format: Audio Power State Format + ConverorB Widget current power state + + 17:16 ConvertorB Widget PwrSt Req + Format: Audio Power State Format + ConverorB Widget power state that was requested by audio software + + 15:14 ConvertorA Widget PwrSt Curr + Format: Audio Power State Format + ConverorA Widget current power state + + 13:12 ConvertorA Widget PwrSt Req + Format: Audio Power State Format + ConverorA Widget power state that was requested by audio software + + 11:10 PinD Widget PwrSt Curr + Format: Audio Power State Format + PinD Widget current power state + + 9:8 PinD Widget PwrSt Set + Format: Audio Power State Format + PinD Widget power state that was set + + 7:6 PinC Widget PwrSt Curr + Format: Audio Power State Format + PinC Widget current power state + + 5:4 PinC Widget PwrSt Set + Format: Audio Power State Format + PinC Widget power state that was set + + 3:2 PinB Widget PwrSt Curr + Format: Audio Power State Format + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 92 + AUD_PWRST + PinB Widget current power state + + 1:0 PinB Widget PwrSt Set + Format: Audio Power State Format + PinB Widget power state that was set + + + + +4.2.7 AUD_PINW_CONNLNG_LIST—Audio Connection List + + AUD_PINW_CONNLNG_LIST +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000302 +Access: RO +Size (in bits): 32 +Address: E50A8h-E50ABh +Name: Audio Connection List +ShortName: AUD_PINW_CONNLNG_LIST +These values are returned from the device as the Connection List Length response to a Get Pin Widget command. +DWord Bit Description +0 31:16 Reserved + 15:8 Connection List Entry + Default Value: 03h 0x03 + Connection to Convertor Widget Node 0x03 + + 7 Long Form + This bit indicates whether the items in the connection list are ‘long form’ or ‘short form’. + This bit is hardwired to 0 (items in connection list are short form) + 6:0 Connection List Length + Default Value: 02h 0x02 + This field indicates the number of items in the connection list. If this field is 2, there is only one + hardwired input possible, which is read from the Connection List, and there is no Connection Select + Control. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 93 + 4.2.8 AUD_PINW_CONNLNG_SEL—Audio Connection Select + + AUD_PINW_CONNLNG_SEL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: E50ACh-E50AFh +Name: Audio Connection Select +ShortName: AUD_PINW_CONNLNG_SEL +These values are returned from the device as the Connection List Length response to a Get Pin Widget command. + DWord Bit Description +0 31:24 Reserved + 23:16 Connection select Control D + Connection Index Currently Set [Default 0x00], Port D Widget is set to 0x00 + 15:8 Connection select Control C + Connection Index Currently Set [Default 0x00], Port C Widget is set to 0x00 + 7:0 Connection select Control B + Connection Index Currently Set [Default 0x00], Port B Widget is set to 0x00 + + + + +4.2.9 AUD_CNTL_ST—Audio Control State + + AUD_CNTL_ST +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00005400 +Access: R/W +Size (in bits): 32 +Address: E50B4h-E50B7h +Name: Audio Control State Transcoder A +ShortName: AUD_CNTL_ST_A +Address: E51B4h-E51B7h +Name: Audio Control State Transcoder B +ShortName: AUD_CNTL_ST_B +Address: E52B4h-E52B7h +Name: Audio Control State Transcoder C +ShortName: AUD_CNTL_ST_C +DWord Bit Description +0 31 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 94 + AUD_CNTL_ST + 30:29 DIP Port Select + Access: RO + This read-only bit reflects which port is used to transmit the DIP data. This can only change when DIP + is disabled. If one or more audio-related DIP packets is enabled and audio is enabled on a digital port, + these bits will reflect the digital port to which audio is directed. + Value Name Description + 00b Reserved Reserved + 01b Digital Port B Digital Port B + 10b Digital Port C Digital Port C + 11b Digital Port D Digital Port D + 28:25 Reserved + Format: MBZ + 24:21 DIP type enable status + Access: RO + These bits reflect the DIP types enabled. It can be updated while the port is enabled. Within 2 vblank + periods, the DIP is guaranteed to have been transmitted. Disabling a DIP type results in setting the + contents of that DIP buffer to zero. A reserved setting reflects a disabled DIP. + Value Name Description + XXX0b Disable Audio DIP disabled + XXX1b Enable Audio DIP enabled + XX0Xb Disable Generic 1 (ACP) DIP disabled + XX1Xb Enable Generic 1 (ACP) DIP enabled + X0XXb Disable Generic 2 DIP disabled + X1XXb Enable Generic 2 DIP enabled, can be used by ISRC1 or ISRC2 + 1XXXb Reserved Reserved + 20:18 DIP buffer index + This field is used during read of different DIPs, and during read or write of ELD data. These bits are + used as an index to their respective DIP or ELD buffers. When the index is not valid, the contents of the + DIP will return all 0’s. + Value Name Description + 000b Audio Audio DIP (31 bytes of address space, 31 bytes of data) + 001b Gen 1 Generic 1 (ACP) Data Island Packet (31 bytes of address space, 31 bytes of data) + 010b Gen 2 Generic 2 (ISRC1) Data Island Packet (31 bytes of address space, 31 bytes of data) + 011b Gen 3 Generic 3 (ISRC2) Data Island Packet (31 bytes of address space, 31 bytes of data) + Others Reserved Reserved + 17:16 DIP transmission frequency + Access: RO + These bits reflect the frequency of DIP transmission for the DIP buffer type designated in bits 20:18. + When writing DIP data, this value is also latched when the first DW of the DIP is written. + When read, this value reflects the DIP transmission frequency for the DIP buffer designated in bits + 20:18. + Value Name Description + 00b Disable Disabled + 01b Reserved Reserved + 10b Send Once Send Once + 11b Best Effort Best effort (Send at least every other vsync) + 15 Reserved + Format: MBZ + 14:10 ELD buffer size + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 95 + AUD_CNTL_ST + Default Value: 10101b 84 Bytes of ELD + Access: RO + This field reflects the size of the ELD buffer in DWORDs + + 9:5 ELD access address + Selects the DWORD address for access to the ELD buffer (84 bytes). The value wraps back to zero + when incremented past the max addressing value 0x1F. This field change takes effect immediately + after being written. The read value indicates the current access address. + 4 ELD ACK + Acknowledgement from the audio driver that ELD read has been completed + 3:0 DIP access address + Selects the DWORD address for access to the DIP buffers. The value wraps back to zero when it + incremented past the max addressing value of 0xF. This field change takes effect immediately after + being written. The read value indicates the current access address. + + + + +4.2.10 AUD_CNTRL_ST2— Audio Control State 2 + + AUD_CNTRL_ST2 +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: E50C0h-E50C3h +Name: Audio Control State 2 +ShortName: AUD_CNTRL_ST2 +This register is used for handshaking between the audio and video drivers for interrupt management. + Display software sets these bits as part of enabling the respective audio-enabled digital port. + For each port, ELD readiness is sent by the display software to the audio software via an unsolicited response when +the ELD ready bit is set. +DWord Bit Description +0 31:10 Reserved + 8 ELD validD + This R/W bit reflects the state of the ELD data written to the ELD RAM. After writing the ELD data, the + video software must set this bit to 1 to indicate that the ELD data is valid. At audio codec initialization, + or on a hotplug event, this bit is set to 0 by the video software. This bit is reflected in the audio pin + complex widget as the ELD valid status bit. + Value Name Description + 0b Invalid ELD data invalid (default, when writing ELD data, set 0 by software) + 1b Valid ELD data valid (Set by video software only) + 7:6 Reserved + 4 ELD validC + See ELD_validD descripion. + Value Name Description + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 96 + AUD_CNTRL_ST2 + 0b Invalid ELD data invalid (default, when writing ELD data, set 0 by software) + 1b Valid ELD data valid (Set by video software only) + 3:2 Reserved + 0 ELD validB + See ELD_validD descripion. + Value Name Description + 0b Invalid ELD data invalid (default, when writing ELD data, set 0 by software) + 1b Valid ELD data valid (Set by video software only) + + + + +4.2.11 AUD_HDMIW_HDMIEDID—Audio HDMI Data EDID Block + + AUD_HDMIW_HDMIEDID +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: E5050h-E5053h +Name: Audio HDMI Data EDID Block Transcoder A +ShortName: AUD_HDMIW_HDMIEDID_A +Address: E5150h-E5153h +Name: Audio HDMI Data EDID Block Transcoder B +ShortName: AUD_HDMIW_HDMIEDID_B +Address: E5250h-E5253h +Name: Audio HDMI Data EDID Block Transcoder C +ShortName: AUD_HDMIW_HDMIEDID_C +These registers contain the HDMI data block from the EDID. The graphics driver reads the EDID and writes the +structure to these registers. The vendor specific data block may be longer than 8 bytes, but the driver must not write +more than 48 bytes to the buffer. The EDID format is Version 3 within the CEA-861B specification. The HDMI Vendor +Specific Data Block is described in version 1.1 of the HDMI specification. + These values are returned from the device as the HDMI Vendor Specific Data Block response to a Get HDMI Widget +command. + Writing sequence: + - Video software sets ELD invalid, and sets the ELD access address to 0, or to the desired + DWORD to be written. + - Video software writes ELD data 1 DWORD at a time. The ELD access address autoincrements with each DWORD +write, wrapping around to address 0 when the max buffer address size of 0xF has been reached. Please note that +software must write an entire DWORD at a time. + - Please note that the audio driver checks the valid bit with each byte read of the ELD. This means that the video +driver can unilaterally write ELD irrespective of audio driver ELD read status. + Reading sequence: + - Video software sets the ELD access address to 0, or to the desired DWORD to be read. + - Video software reads ELD data 1 DWORD at a time. The ELD access address autoincrements with each DWORD + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 97 + AUD_HDMIW_HDMIEDID +read, wrapping around to address 0 when the max buffer address size of 0xF has been reached. + DWord Bit Description +0 31:0 EDID HDMI Data Block + Please note that the contents of this buffer are not cleared when ELD is disabled. The contents of + this buffer are cleared during gfx reset + + + + +4.2.12 AUD_HDMIW_INFOFR—Audio Widget Data Island Packet + + AUD_HDMIW_INFOFR +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: RO +Size (in bits): 32 +Address: E5054h-E5057h +Name: Audio Widget Data Island Packet Transcoder A +ShortName: AUD_HDMIW_INFOFR_A +Address: E5154h-E5157h +Name: Audio Widget Data Island Packet Transcoder B +ShortName: AUD_HDMIW_INFOFR_B +Address: E5254h-E5257h +Name: Audio Widget Data Island Packet Transcoder C +ShortName: AUD_HDMIW_INFOFR_C +When the IF type or dword index is not valid, the contents of the DIP will return all 0’s. + These values are programmed by the audio driver in an HDMI Widget Set command. + To fetch a specific byte, the audio driver should send an HDMI Widget HDMI DIP Index Pointer Set command to set +the index, then fetch the indexed byte using the HDMI DIP get. + Video software reads DIP data 1 DWORD at a time. + The DIP access address auto increments with each DWORD write, wrapping around to address 0 when the max +buffer address size of 0xF has been reached. + DWord Bit Description +0 31:0 Data Island Packet Data + This reflects the contents of the DIP indexed by the DIP access address. The contents of this buffer + are cleared during function reset. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 98 + 5. South Display Engine Transcoder and + FDI Control +5.1 Transcoder Control + +5.1.1 TRANS_CONF—Transcoder Configuration + + TRANS_CONF +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Start of vertical blank OR transcoder disabled +Address: F0008h-F000Bh +Name: Transcoder A Config +ShortName: TRANS_CONF_A +Address: F1008h-F100Bh +Name: Transcoder B Config +ShortName: TRANS_CONF_B +Address: F2008h-F200Bh +Name: Transcoder C Config +ShortName: TRANS_CONF_C +DWord Bit Description +0 31 Transcoder Enable + Setting this bit to the value of one, turns on the transcoder. + Turning the transcoder off disables the timing generator and synchronization pulses to the display will + not be maintained. + Transcoder timing registers must contain valid values before this bit is enabled. + Value Name Description + 0b Disable Disabled + 1b Enable Enabled + + + Programming Notes + Workaround : Set timing override (transcoder A 0xF0064, transcoder B 0xF1064, transcoder C + 0xF2064) bit 31 = 1 prior to enabling the transcoder. Clear timing override (transcoder A 0xF0064, + transcoder B 0xF1064, transcoder C 0xF2064) bit 31 = 0 after disabling the transcoder. + 30 Transcoder State + This read only bit indicates the actual state of the transcoder. + Value Name Description + 0b Disabled Transcoder is disabled + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 99 + TRANS_CONF + 1b Enabled Transcoder is enabled + 29:24 Reserved + 23:21 Interlaced Mode + These bits are used for control of the transcoder interlaced mode. + Value Name Description + 000b Progressive Progressive + 011b Interlaced Interlaced (north display must also be set to interlaced) + Others Reserved + 20:11 Reserved + 10 xvYCC Color Range Limit + This bit is used to limit the color range of the port outputs from 1 to 254 for 8-bit components, 4 to 109 + for 10-bit components, or 16 to 4079 for 12-bit components. + Values outside of the range will be clamped to fit within the range. + There is no need to set this bit if the equivalent bit is set in the north display pipe configuration register. + Value Name Description + 0b Full Do not limit the range + 1b Limit Limit range + 9:0 Reserved + + + + +5.2 FDI Receiver + +5.2.1 FDI_RX_CTL— FDI Rx Control + + FDI_RX_CTL +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000040 +Access: R/W +Size (in bits): 32 +Double Buffer Update Point: Depends on bit +Address: F000Ch-F000Fh +Name: FDI A RX Control +ShortName: FDI_RX_CTL_A +Address: F100Ch-F100Fh +Name: FDI B RX Control +ShortName: FDI_RX_CTL_B +Address: F200Ch-F200Fh +Name: FDI C RX Control +ShortName: FDI_RX_CTL_C +DWord Bit Description + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 100 + FDI_RX_CTL +0 31 FDI Rx Enable + Disabling this port will put it in its lowest power state. + Value Name Description + 0b Disable Disable the FDI Rx interface + 1b Enable Enable the FDI Rx interface + + + Programming Notes Project + Restriction : IF FDI polarity is reversed, set FDI Polarity Reversal (transcoder A 0xF0064, + transcoder B 0xF1064, transcoder C 0xF2064) bit 29 = 1 prior to enabling FDI Rx. + Restriction : FDIC can only be enabled if FDIB is never used. + Workaround : 0xC2000 bit #12 must be programmed correctly prior to enabling FDIB or FDIC + and cannot be changed after enabling either FDIB or FDIC. + + If 0xC2000 bit #12 = 0: Only FDIB can be used. FDIC cannot be used. FDIB can use up to 4 + lanes. + + If 0xC2000 bit #12 = 1: Both FDIB and FDIC can be used. FDIB can use up to 2 lanes and + FDIC can use up to 2 lanes. It is recommended to select this when using FDIB in 1 or 2 lane + modes, even if FDIC will not be used at that time, so that if FDIC is later enabled it will not be + necessary to disable FDIB and change the 0xC2000 setting. + 30:28 Reserved + Format: MBZ + 27 FS error correction enable + This bit enables the Fill Start error correction over FDI. + Once the FS code is incorrectly received, the receiver will recover the FS code. + The FDI Rx TU size register must be set correctly and the following condition must be met in order to + set this bit: (Active+2)/TU >= 1 + Value Name Description + 0b Disable Disable FS Error Correction + 1b Enable Enable FS Error Correction + 26 FE error correction enable + This bit enables the Fill End error correction over FDI. + Value Name Description + 0b Disable Disable FE Error Correction + 1b Enable Enable FE Error Correction + 25 FS error reporting enable + This bit enables the FS error reporting over FDI. + Value Name Description + 0b Disable Disable FS Error Reporting + 1b Enable Enable FS Error Reporting + 24 FE error reporting enable + This bit enables the FE error reporting over FDI. + Value Name Description + 0b Disable Disable FE Error Reporting + 1b Enable Enable FE Error Reporting + 23:22 Reserved + 21:19 Port Width Selection + These bits select the number of lanes to be enabled on the link. + Port width change must be done as a part of mode set. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 101 + FDI_RX_CTL + Locked once port is enabled. Updates when the port is disabled then re-enabled + Value Name Description + 000b x1 Mode x1 Mode + 001b x2 Mode x2 Mode + 010b x3 Mode x3 Mode + 011b x4 Mode x4 Mode + Others Reserved + + + Programming Notes + Restriction : FDI B and FDI C share lanes. + FDI C maximum port width is 2 lanes. + FDI B maximum port width is 4 lanes when FDI C is disabled, 2 lanes when FDI C is enabled. + 18:16 Bits Per Color + This field selects the number of bits per color sent over the link. + Color format takes place on the Vblank after being written. + Value Name Description + 000b 8 bpc 8 bits per color + 001b 10 bpc 10 bits per color + 010b 6 bpc 6 bits per color + 011b 12 bpc 12 bits per color + Others Reserved Reserved + 15 Link reversal strap override + By default, link is reversed if DMI is reversed according to the DMI reversal strap. This bit can be set to + override FDI to use the reverse of what is strapped for DMI. + All FDI links must be off in order for this bit to take effect. + This bit is ORed with the link reversal strap overrides from any other FDI Rx Control registers. + Value Name Description + 0b Not Overwritten Link reversal strap not overwritten + 1b Overwritten Link reversal strap overwritten. + 14 DMI Link reversal status + Access: RO + This bit reflects the DMI link reversal strap. + Value Name Description + 0b Not Reversed Link not reversed + 1b Reversed Link reversed. + 13 FDI PLL enable + Format: Enable + This bit enables the FDI PLL. + This bit is ORed with the FDI PLL enables from any other FDI Rx Control registers. + Programming Notes + Restriction : After enabling the FDI PLL, software must wait for a warmup period before enabling the + link. + 12 Reserved + 11 Composite Sync Select + This bit selects between composite Sync and separate Fsync/Lsync on this port. + This bit is ORed with the composite sync select from any other FDI Rx Control registers. + Value Name Description + 0b Separate Separate Fsync/Lsync + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 102 + FDI_RX_CTL + 1b Composite Composite Sync + + + Programming Notes + Restriction : Composite sync can only be used if the CPU display supports it. + + FDI A can use either separate sync or composite sync. FDI A must use composite sync when FDI C is + enabled. + FDI B can use either separate sync or composite sync. FDI B must use composite sync when FDI C is + enabled. + FDI C can only use composite sync. + + It is recommended to always use composite sync when the CPU display supports it, even when just + using FDI A or FDI B, so that FDI C can be enabled later without needing to temporarily disable FDI A + and FDI B in order to change them to composite. + 10 FDI Auto Train + This bit enables FDI auto-training on this port. + Locked once port is enabled. Updates when port is disabled. + Value Name Description + 0b Disable Disable FDI auto-training + 1b Enable Enable FDI auto-training + 9:8 Link training pattern enable + These bits are used for link initialization. + Value Name Description + 00b Pattern 1 Pattern 1 enabled + 01b Pattern 2 Pattern 2 enabled + 10b Idle Idle Pattern enabled + 11b Normal Link not in training: Send normal pixels + + + Programming Notes + Restriction : When enabling the port, it must be turned on with pattern 1 enabled. When retraining, the + port must be disabled, then re-enabled with pattern 1 enabled. + 6 Enhanced Framing Enable + This bit selects enhanced framing. + Locked once port is enabled. Updates when the port is disabled then re-enabled + Value Name Description + 0b Disable Enhanced framing disabled + 1b Enable [Default] Enhanced framing enabled + 4 Rawclk to PCDCLK selection + This bit switches PCH display clocking between the raw oscillator clock and PCDCLK. + It must be programmed as part of enabling and disabling the link. + This bit is ORed with the selection bit from any other FDI Rx Control registers. + Value Name Description + 0b Rawclk Rawclk used + 1b PCDCLK PCDCLK used + + + Programming Notes + Restriction : The FDI PLL must be enabled and warmed up before switching to PCDCLK. + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 103 + FDI_RX_CTL + 3:0 Reserved + Format: MBZ + + + + +5.2.2 FDI_RX_MISC— FDI Rx Miscellaneous + + FDI_RX_MISC +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000080 +Access: R/W +Size (in bits): 32 +Address: F0010h-F0013h +Name: FDI A RX Miscellaneous +ShortName: FDI_RX_MISC_A +Address: F1010h-F1013h +Name: FDI B RX Miscellaneous +ShortName: FDI_RX_MISC_B +Address: F2010h-F2013h +Name: FDI C RX Miscellaneous +ShortName: FDI_RX_MISC_C +DWord Bit Description +0 31:22 Reserved + Format: MBZ + 21:20 TP1 to TP2 Time + These bits select the number of link clocks to count before transitioning from TP1 to TP2 during auto + training. + Value Name Description + 10b 48 48 clocks - required programming + 11b 64 64 clocks + + + Programming Notes + Restriction : Program to 48 clocks before enabling FDI with auto-training. + 19 Reserved + Format: MBZ + 18:16 Bit Lock Timeout Time + These bits select the number of link clocks to count before timing out on bit lock during auto training. + Value Name Description + 000b 128 128 clocks + 001b 256 256 clocks + 010b 384 384 clocks + 011b 512 512 clocks + 100b 640 640 clocks + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 104 + FDI_RX_MISC + 101b 768 768 clocks + 110b 896 896 clocks + 111b 1024 1024 clocks + 15:13 Reserved + Format: MBZ + 12:0 FDI Delay + This field specifies latency as relative delay with respect to the dot clock required for active data over + the FDI interface to reach the timing generator FIFO in the transcoder. + Value Name Description + 80h 80h [Default] Default + 90h 90h Required for all FDI configurations + + + Programming Notes + Workaround : Program 90h when FDI is used. + + + + +5.2.3 FDI_RX_IMR — FDI Rx Interrupt Mask + + FDI Receiver Interrupt Bit Definition +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Size (in bits): 32 +FDI Receiver (FDI Rx) interrupt bits come from FDI Receiver events. + The FDI_RX_IIR bits are ORed together to generate the FDI_RX Combined Interrupt which will appear in the South +Display Engine Interrupt Control Registers. + The FDI Receiver Interrupt Control Registers all share the same bit definitions from this table. + DWord Bit Description +0 31:12 Reserved + 11 FDI RX Bit Lock Timeout + This indicates that bit lock timeout occured. + 10 FDI RX Interlane Alignment + This indicates all the lanes are properly inter-lane aligned. + 9 FDI RX Symbol Lock + This indicates training pattern 2 was consecutively received successfully on all the enabled lanes. + 8 FDI RX Bit Lock + This indicates training pattern 1 was consecutively received successfully on all the enabled lanes. + 7 FDI RX Training Pattern 2 Fail + This indicates that the training pattern 2 has failed. + 6 FS Code Error + This reports the Fill Start code missing condition. + 5 FE Code Error + This reports the Fill End code missing condition. + 4 FDI RX High Symbol Error Rate + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 105 + FDI Receiver Interrupt Bit Definition + This indicates the received symbol error rate is more than 10^-10. + 2 FDI RX Pixel FIFO Overflow + This indicates the Pixel FIFO overflowed. + 1 FDI RX Cross Clock FIFO Overflow + This indicates the cross clock symbol clock to display clock FIFO overflowed. + 0 FDI RX Symbol Queue overflow + This indicates the symbol queue overflowed. + + + + + FDI_RX_IMR +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/W +Size (in bits): 32 +Address: F0018h-F001Bh +Name: FDI A RX Interrupt Mask +ShortName: FDI_RX_IMR_A +Address: F1018h-F101Bh +Name: FDI B RX Interrupt Mask +ShortName: FDI_RX_IMR_B +Address: F2018h-F201Bh +Name: FDI C RX Interrupt Mask +ShortName: FDI_RX_IMR_C +See the interrupt bit definition table to find the source event for each interrupt bit. +DWord Bit Description +0 31:0 Interrupt Mask Bits + This field contains a bit mask which selects which FDI_RX events are reported int the FDI_RX_IIR. + Value Name Description + 0b Not Masked Not Masked – will be reported in the FDI_RX_IIR + 1b Masked Masked – will not be reported in the FDI_RX_IIR + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 106 + 5.2.4 FDI_RX_IIR — FDI Rx Interrupt Identity + + FDI_RX_IIR +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x00000000 +Access: R/WC +Size (in bits): 32 +Address: F0014h-F0017h +Name: FDI A RX Interrupt Identity +ShortName: FDI_RX_IIR_A +Address: F1014h-F1017h +Name: FDI B RX Interrupt Identity +ShortName: FDI_RX_IIR_B +Address: F2014h-F2017h +Name: FDI C RX Interrupt Identity +ShortName: FDI_RX_IIR_C +See the interrupt bit definition table to find the source event for each interrupt bit. +DWord Bit Description +0 31:0 Interrupt Identity Bits + This field holds the persistent values of the FDI_RX interrupt bits which are unmasked by the + FDI_RX_IMR. + Bits set in this register will propagate to the combined FDI_RX interrupt in the SDE_ISR. + Bits set in this register will remain set (persist) until the interrupt condition is cleared by writing a ‘1’ to + the appropriate bits. + Value Name Description + 0b Condition Not Detected Interrupt Condition Not Detected + 1b Condition Detected Interrupt Condition Detected + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 107 + 5.2.5 FDI_RX_TUSIZE— FDI Rx Transfer Unit Size + + FDI_RX_TUSIZE +Register Space: MMIO: 0/2/0 +Project: +Default Value: 0x7E000000 +Access: R/W +Size (in bits): 32 +Address: F0030h-F0033h +Name: FDI A RX TU Size 1 +ShortName: FDI_RX_TUSIZE_1_A +Address: F0038h-F003Bh +Name: FDI A RX TU Size 2 +ShortName: FDI_RX_TUSIZE_2_A +Address: F1030h-F1033h +Name: FDI B RX TU Size 1 +ShortName: FDI_RX_TUSIZE_1_B +Address: F1038h-F103Bh +Name: FDI B RX TU Size 2 +ShortName: FDI_RX_TUSIZE_2_B +Address: F2030h-F2033h +Name: FDI C RX TU Size 1 +ShortName: FDI_RX_TUSIZE_1_C +Address: F2038h-F203Bh +Name: FDI C RX TU Size 2 +ShortName: FDI_RX_TUSIZE_2_C + Programming Notes +Restriction : The FDI Receiver TU1 and TU2 sizes must be programmed to match the TU sizes used by the FDI +Transmitter. + When switching between two refresh rates, both the TU1 and TU2 values must be programmed. + For dynamic refresh rate control, TU1 values are the primary values and are used for the normal setting, and TU2 +values are the secondary values and are used for the lower power setting. + DWord Bit Description +0 31 Reserved + Format: MBZ + 30:25 TU Size + This field is the size of the transfer unit for FDI, minus one. + Value Name + 111111b 63 [Default] + [1,63] + 24:0 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 108 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 5/31/2012 109 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol4_part1.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol4_part1.txt new file mode 100644 index 0000000..e6b6650 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol4_part1.txt @@ -0,0 +1,14448 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 4 Part 1: Subsystem and Cores – +Shared Functions +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S +TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY +WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO +SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO +FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY +PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. + +A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly +or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 + Contents +1. Subsystem Overview ............................................................................................................................ 5 + 1.1 Introduction .......................................................................................................................................... 5 + 1.2 Subsystem Topology............................................................................................................................ 5 + 1.3 Execution Units (EUs) .......................................................................................................................... 5 + 1.4 Thread Dispatching .............................................................................................................................. 6 + 1.5 Shared Functions ................................................................................................................................. 6 + 1.5.1 Message Payload Containing a Header ......................................................................................... 7 + 1.5.2 Writebacks ...................................................................................................................................... 7 + 1.5.3 Message Delivery Ordering Rules .................................................................................................. 8 + 1.5.4 Execution Mask and Messages ...................................................................................................... 8 + 1.5.5 End-Of-Thread (EOT) Message ..................................................................................................... 8 + 1.5.6 Performance ................................................................................................................................... 9 + 1.5.7 Message Description Syntax .......................................................................................................... 9 + 1.5.8 Message Errors ............................................................................................................................ 10 +2. Sampling Engine ................................................................................................................................. 12 + 2.1 Texture Coordinate Processing ......................................................................................................... 12 + 2.1.1 Texture Coordinate Normalization ................................................................................................ 13 + 2.1.2 Texture Coordinate Computation ................................................................................................. 13 + 2.2 Texel Address Generation ................................................................................................................. 14 + 2.2.1 Level of Detail Computation (Mipmapping) .................................................................................. 14 + 2.2.2 Intra-Level Filtering Setup ............................................................................................................ 18 + 2.2.3 Texture Address Control ............................................................................................................... 21 + 2.3 Texel Fetch ........................................................................................................................................ 24 + 2.3.1 Texel Chroma Keying ................................................................................................................... 25 + 2.4 Shadow Prefilter Compare ................................................................................................................. 25 + 2.5 Texel Filtering ..................................................................................................................................... 26 + 2.6 Texel Color Gamma Linearization ..................................................................................................... 26 + 2.7 Multisampled Surface Behavior ......................................................................................................... 26 + 2.7.1 Multisample Control Surface ........................................................................................................ 27 + 2.8 Denoise/Deinterlacer .......................................................................................................................... 27 + 2.8.1 Introduction ................................................................................................................................... 27 + 2.8.2 Denoise Algorithm ........................................................................................................................ 29 + 2.8.3 Block Noise Estimate (part of Global Noise Estimate) ................................................................. 32 + 2.8.4 Deinterlacer Algorithm .................................................................................................................. 33 + 2.8.5 Field Motion Detector ................................................................................................................... 46 + 2.8.6 Implementation Overview ............................................................................................................. 48 + 2.9 Adaptive Video Scaler ........................................................................................................................ 50 + 2.9.1 Filtering Operations ...................................................................................................................... 51 + 2.10 Image Enhancement Filter and Video Signal Analysis ..................................................................... 52 + 2.10.1 Detail Filter Algorithm ................................................................................................................. 53 + 2.10.2 Skin-Tone Tuned IEF ................................................................................................................. 53 + 2.10.3 Video Analytics Functions – Functional Description................................................................... 54 + 2.11 Mirror pixel at boundary edges for Media (sample_8x8 messages) ................................................ 57 + 2.11.1 Restriction when Mirror mode is enabled for Sample_8x8 messages ....................................... 60 + 2.12 State.................................................................................................................................................. 61 + 2.12.1 BINDING_TABLE_STATE.......................................................................................................... 61 + 2.12.2 SURFACE_STATE ..................................................................................................................... 61 + 2.12.3 SAMPLER_STATE ..................................................................................................................... 91 + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 3 + 2.12.4 SAMPLER_8x8_STATE ........................................................................................................... 111 + 2.12.5 SAMPLER_BORDER_COLOR_STATE .................................................................................. 116 + 2.12.6 3DSTATE_CHROMA_KEY ...................................................................................................... 119 + 2.12.7 3DSTATE_SAMPLER_PALETTE_LOAD0 .............................................................................. 120 + 2.12.8 3DSTATE_MONOFILTER_SIZE .............................................................................................. 122 + 2.13 Messages ....................................................................................................................................... 123 + 2.13.1 Initiating Message ..................................................................................................................... 123 + 2.13.2 Writeback Message .................................................................................................................. 142 +3. Shared Functions – Data Port .......................................................................................................... 167 + 3.1 Cache Agents ................................................................................................................................... 168 + 3.1.1 Render Cache............................................................................................................................. 168 + 3.1.2 Data Cache ................................................................................................................................. 169 + 3.1.3 Sampler Cache ........................................................................................................................... 169 + 3.2 Surfaces ........................................................................................................................................... 169 + 3.2.1 Surface State Model ................................................................................................................... 169 + 3.2.2 Stateless Model .......................................................................................................................... 169 + 3.2.3 Shared Local Memory (SLM)...................................................................................................... 170 + 3.3 Write Commit ................................................................................................................................... 170 + 3.4 Read/Write Ordering ........................................................................................................................ 171 + 3.5 Accessing Buffers ............................................................................................................................ 171 + 3.6 Accessing Media Surfaces ............................................................................................................... 172 + 3.6.1 Color Processing ........................................................................................................................ 172 + 3.6.2 Boundary Behavior ..................................................................................................................... 197 + 3.7 Accessing Render Targets ............................................................................................................... 197 + 3.7.1 Single Source ............................................................................................................................. 198 + 3.7.2 Dual Source ................................................................................................................................ 198 + 3.7.3 Replicate Data ............................................................................................................................ 198 + 3.7.4 Multiple Render Targets (MRT) .................................................................................................. 199 + 3.8 State ................................................................................................................................................. 199 + 3.8.1 BINDING_TABLE_STATE.......................................................................................................... 199 + 3.8.2 SURFACE_STATE ..................................................................................................................... 199 + 3.8.3 COLOR_PROCESSING_STATE ............................................................................................... 199 + 3.9 Messages ......................................................................................................................................... 225 + 3.9.1 Global Definitions ....................................................................................................................... 225 + 3.9.2 Data Port Messages ................................................................................................................... 226 + 3.9.3 OWord Block Read/Write ........................................................................................................... 233 + 3.9.4 Unaligned OWord Block Read.................................................................................................... 235 + 3.9.5 OWord Dual Block Read/Write ................................................................................................... 236 + 3.9.6 Media Block Read/Write ............................................................................................................. 239 + 3.9.7 DWord Scattered Read/Write ..................................................................................................... 245 + 3.9.8 Byte Scattered Read/Write ......................................................................................................... 248 + 3.9.9 Typed/Untyped Surface Read/Write and Typed/Untyped Atomic Operation ............................. 251 + 3.9.10 Scratch Block Read/Write......................................................................................................... 274 + 3.9.11 Render Target Write ................................................................................................................. 276 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 4 + 1. Subsystem Overview +1.1 Introduction +The subsystem consists of an array of execution units (EUs, sometimes referred to as an arrray of cores) +along with a set of shared functions outside the EUs that the EUs leverage for I/O and for complex +computations. Programmers access the subsystem via the 3D or Media pipelines. +EUs are general-purpose programmable cores that support a rich instruction set that has been optimized +to support various 3D API shader languages as well as media functions (primarily video) processing. +Shared functions are hardware units which serve to provide specialized supplemental functionality for the +EUs. A shared function is implemented where the demand for a given specialized function is insufficient +to justify the costs on a per-EU basis. Instead a single instantiation of that specialized function is +implemented as a stand-alone entity outside the EUs and shared among the EUs. +Invocation of the shared functionality is performed via a communication mechanism called a message. A +message is a small self-contained packet of information created by a kernel and directed to a specific +shared function. Messages are dispatched to the shared function under software control via the send +instruction. This instruction identifies the contents of the message and the GRF register locations to direct +any response. +The message construction and delivery mechanisms are general in their definition and capable of +supporting a wide variety of shared functions. + + +1.2 Subsystem Topology +The subsystem is organized as an array of EUs, and a set of functions that are shared among all of the +EUs. (The EU array is further divided into rows with each row having its own first level instruction cache +and Extended Math shared function, though this aspect of the implemented topology is not exposed to +software). The Sampler, DataPort, URB and Message Gateway functions are shared among the entire +array of EUs. + + +1.3 Execution Units (EUs) +Each EU is a vector machine capable of performing a given operation on as many as 16 pieces of data of +the same type in parallel (though not necessarily on the same instant in time). In addition, each EU can +support a number of execution contexts called threads that are used to avoid stalling the EU during a +high-latency operation (external to the EU) by providing an opportunity for the EU to switch to a +completely different workload with minimal latency while waiting for the high-latency operation to +complete. +For example, if a program executing on an EU requires a texture read by the sampling engine, the EU +may not necessarily idle while the data is fetched from memory, arranged, filtered and returned to the EU. +Instead the EU will likely switch execution to another (unrelated) thread associated with that EU. If that +thread encounters a stall, the EU may switch to yet another thread and so on. Once the Sampler result +arrives back at the EU, the EU can switch back to the original thread and use the returned data as it +continues execution of that thread. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 5 + The fact that there are multiple EU cores each with multiple threads can generally be ignored by software. +There are some exceptions to this rule: e.g., for + +  thread-to-thread communication (see Message Gateway, Media) +  synchronization of thread output to memory buffers (see Geometry Shader). + +In contrast, the internal SIMD aspects of the EU are very much exposed to software. +This volume will not deal with the details of the EUs. + + +1.4 Thread Dispatching +When the 3D and Media pipelines send requests for thread initiation to the Subsystem, the thread +Dispatcher receives the requests. The dispatcher performs such tasks as arbitrating between concurrent +requests, assigning requested threads to hardware threads on EUs, allocating register space in each EU +among multiple threads, and initializing a thread’s registers with data from the fixed functions and from +the URB. This operation is largely transparent to software. + + +1.5 Shared Functions +In general, a shared function has the ability to receive messages at its input, perform some specialized +amount of work for each, and if required, generate output back to the message’s originating execution +unit (Message Gateway may generate output to a target execution unit specified by the message). +To uniquely identify shared functions, each is assigned a unique 4-bit identifier code called its ‘Function +ID’. This ID is specified in the ‘send’ instruction’s 32b field of each message. Function ID +assignments are listed in the Graphics Processing Engine chapter of this specification. +Each shared function may support one or more related operations within itself. For example an Extended +Math shared function may support operations such as reciprocal, sine, cosine, and/or others. These are +generically referred to as sub-functions. The communication method as to which sub-function is desired is +typically contained in the 16b ‘function-control’ field of the ‘send’ instruction field. Alternatively, a +function may choose to define sub-function encodings in-band within message payload, or in the case of +a single function shared-function, the function code may be implied. The architecture, in no way interprets +the sub-function code and the actual implementation choice is left to the function itself. +The Shared Function units included in the Subsystem are as follows (refer to the chapters devoted to +each of these functions): + +  Extended Math function +  Sampling Engine function +  DataPort function +  Message Gateway function +  Unified Return Buffer (URB) +  Thread Spawner (TS) +  Null function + +The Extended Math function acts as an extension of the math functions already available inside the EUs. +Certain functions such as inverse, square root, exponentiation, etc., require significant hardware +resources to implement and are used infrequently enough that it is inefficient to implement them +separately in each EU. The EUs therefore send the operands for these operations along with the + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 6 + operation to be performed to the Extended Math function which computes and returns the result to the +requesting EU. +The Sampling Engine acts a (read-only) I/O port on behalf of the EUs, translating texture coordinates +(and/or structure references) to memory addresses, reading texels and/or other data from memory, and in +the case of texels, combining and filtering them according to programmed state. The resulting pixel and/or +other data are then returned to the requesting EU. +The Data Port function acts as another I/O port on behalf of the EUs. It is both a read and a write port, +and the only way for the Graphics Processing Engine to write results (e.g., images) back to memory. The +Data Port contains the render and depth caches which receive the newly rendered pixels and write them +out to memory when necessary. They also permit previously rendered objects to be read back efficiently +by the Graphics Processing Engine in order to blend them with other rendered objects and test for +visibility of newly rendered objects. Finally, the Data Port also provides read access constant buffers +(arrays of constants in memory.) +The Message Gateway allows a thread to communicate (send a message to) another thread. A key is +used to connect the sender and receiver threads, and a simple gateway protocol is used to send +messages. This is primarily intended for media where a parent/child thread model is sometimes used and +requires parent and child threads to synchronize and efficiently share information. It is not intended to be +used by 3D graphics rendering threads. +The Unified Return Buffer (URB) is a single set of registers that EU threads use to return result data for +future fixed functions and their threads to make use of. Individual entries in the buffer are “owned” by a +given fixed function but a mechanism is provided where other fixed functions (those that follow) can read +the data placed there by another fixed function. The buffer is considered a “Shared Function” since EUs +need to be able to write result data to it using messages. In general, EU threads write their final results +either to memory via the Data Port or to the URB for re-use by subsequent EU threads or certain 3D +pipeline fixed-function units (CLIP, GS). +The Thread Spawner (TS) is a Shared Function that acts as a conduit for dispatching kernel-software- +generated threads, one thread can request another thread to be dispatched by sending a request to the +TS. TS is unique as it is also a Fixed Function in the media pipeline for dispatching threads originated +from Video Front End fixed function. +The Null shared function is supported to allow the broadcast of certain information (e.g, End Of Thread) +without invoking any other operation or response. + + +1.5.1 Message Payload Containing a Header +For most shared functions, the first register of the message payload contains the header payload of the +message (or simply the message header). Consequently, the rest of the message payload is referred to +as the data payload. +Messages to Extended Math do not have a header and only contain data payload. Those messages may +be referred to as header-less messages. Messages to Gateway combine the header and data payloads in +a single message register. + + +1.5.2 Writebacks +Some messages generate return data as dictated by the ‘function-control’ (opcode) field of the ‘send’ +instruction (part of the field). The execution unit and message passing infrastructure do not +interpret this field in any way to determine if writeback data is to be expected. Instead explicit fields in the +‘send’ instruction to the execution unit the starting GRF register and count of returning data. The +execution unit uses this information to set in-flight bits on those registers to prevent execution of any + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 7 + instruction which uses them as an operand until the register(s) is(are) eventually written in response to +the message. If a message is not expected to return data, the ‘send’ instruction’s writeback destination +specifier () must be set to ‘null’ and the response length field of must be 0 (see ‘send’ +instruction for more details). +The writeback data, if called for, arrives as a series of register writes to the GRF at the location specified +by the starting GRF register and length as specified in the ‘send’ instruction. As each register is written +back to the GRF, its in-flight flag is cleared and it becomes available for use as an instruction operand. If +a thread was suspended pending return of that register, the dependency is lifted and the thread is allowed +to continue execution (assuming no other dependency for that thread remains outstanding). + + +1.5.3 Message Delivery Ordering Rules +All messages between a thread and an individual shared function are delivered in the ordered they were +sent. Messages to different shared functions originating from a single thread may arrive at their respective +shared functions out of order. +The writebacks of various messages from the shared functions may return in any order. Further individual +destination registers resulting from a single message may return out of order, potentially allowing +execution to continue before the entire response has returned (depending on the dependency chain +inherent in the thread). + + +1.5.4 Execution Mask and Messages +The Architecture defines an Execution Mask (EMask) for each instruction issued. This 16b bit-field +identifies which SIMD computation channels are enabled for that instruction. Since the ‘send’ instruction +is inherently scalar, the EMask is ignored as far as instruction dispatch is concerned. Further the +execution size has no impact on the size of the ‘send' instruction’s implicit move (it is always 1 register +regardless of specified execution size). +The 16b EMask is forwarded with the message to the destination shared function to indicate which SIMD +channels were enabled at the time of the ‘send’. A shared function may interpret or ignore this field as +dictated by the functionality it exposes. For instance, the Extended Math shared function observes this +field and performs the specified operation only on the operands with enabled channels, while the +DataPort writes to the render cache ignore this field completely, instead using the pixel mask included in- +band in the message payload to indicate which channels carry valid data. + + +1.5.5 End-Of-Thread (EOT) Message +The final instruction of all threads must be a ‘send’ instruction which signals ‘End-Of-Thread’ (EOT). An +EOT message is one in which the EOT bit is set in the ‘send’ instruction’s 32b field. When issuing +instructions, the EU looks for an EOT message, and when issued, shuts down the thread from further +execution and considers the thread completed. +Only a subset of the shared functions can be specified as the target function of an EOT message, as +shown in the table below. + + Target Shared Functions Target Shared Functions + supporting EOT messages not supporting EOT messages + +Null, DataPortWrite, URB, MessageGateway, ThreadSpawner DataPortRead, Sampler + +Both the fixed-functions and the thread dispatcher require EOT notification at the completion of each +thread. The thread dispatcher and fixed functions in the 3D pipeline obtain EOT notification by snooping + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 8 + all message transmissions, regardless of the explicit destination, looking for messages which signal end- +of-thread. The Thread Spawner in the media pipeline does not snoop for EOT. As it is also a shared +function, all threads generated by Thread Spawner must send a message to Thread Spawner to explicity +signal end-of-thread. +The thread dispatcher, upon detecting an end-of-thread message, updates its accounting of resource +usage by that thread, and is free to issue a new thread to take the place of the ended thread. Fixed +functions require end-of-thread notification to maintain accounting as to which threads it issued have +completed and which remain outstanding, and their associated resources such as URB handles. +Unlike the thread dispatcher, fixed-functions discriminate end-of-thread messages, only acting upon those +from threads which they originated, as indicated by the 4b fixed-function ID present in R0 of end-of-thread +message payload. This 4b field is attached to the thread at new-thread dispatch time and is placed in its +designated field in the R0 contents delivered to the GRF. Thus to satisfy the inclusion of the fixed-function +ID, the typical end-of-thread message generally supplies R0 from the GRF as the first register of an end- +of-thread message. +As an optimization, an end-of-thread message may be overload upon another “productive” message, +saving the cost in execution and bandwidth of a dedicated end-of-thread message. Outside of the end-of- +thread message, most threads issue a message just prior to their termination (for instance, a Dataport +write to the framebuffer) so the overloaded end-of-thread is the common case. The requirement is that +the message contains R0 from the GRF (to supply the fixed-function ID), and that destination shared +function be either (a) the URB; (b) the Read or Write Dataport; or, (c) the Gateway, as these functions +reside on the O-Bus. In the case where the last real message of a thread is to some other shared +function, the thread must issue a separate message for the purposes of signaling end-of-thread to the +“null” shared function. + + +1.5.6 Performance +The Architecture imposes no requirement as to a shared function’s latency or throughput. Due to this as +well as factors such as message queuing, shared bus arbitration, implementation choices in bus +bandwidth, and instantaneous demand for that function, the latency in delivering and obtaining a +response to a message is non-deterministic. It is expected that an implementation has some notion of +fairness in transmission and servicing of messages so as to keep latency outliers to a minimum. +Other factors to consider with regard to performance: + +  A thread may choose to have multiple messages under construction in non-overlapping registers in + the MRF at the same time. +  Multiple messages are allowed to be enqueued for transmission at the same time, so long as their + MRF payload registers do not overlap. +  Messages may rely on the MRF registers being maintained across a send message, thus + constructing subsequent messages overlaid on portions of a previous message, +  Software prefetching techniques may be beneficial for long latency data fetches (i.e. issue a load + early in the thread for data that is required late in the thread). + + +1.5.7 Message Description Syntax +All message formats are defined in terms of DWords (32 bits). The message registers in all cases are 256 +bits wide, or 8 DWords. The registers and DWords within the registers are named as follows, where n is +the register number, and d is the DWord number from 0 to 7, from the least significant DWord at bits +[31:0] within the 256-bit register to the most significant DWord at bits [255:224], respectively. For + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 9 + writeback messages, the register number indicates the offset from the specified starting destination +register. +Dispatch Messages: Rn.d +Dispatch messages are sent by the fixed functions to dispatch threads. See the fixed function chapters in +the 3D and Media volume. +SEND Instruction Messages: Mn.d +These are the messages initiated by the thread via the SEND instruction to access shared functions. See +the chapters on the shared functions later in this volume. +Writeback Messages: Wn.d +These messages return data from the shared function to the GRF where it can be accessed by thread +that initiated the message. +The bits within each DWord are given in the second column in each table. + + +1.5.8 Message Errors +Messages are constructed via software, and not all possible bit encodings are legal, thus there is the +possibility that a message may be sent containing one or more errors in its descriptor or payload +contents. There are two points of error detection in the message passing system: (a) the message +delivery subsystem is capable of detecting bad FunctionIDs and some cases of bad message lengths; (b) +the shared functions contain various error detection mechanisms which identify bad sub-function codes, +bad message lengths, and other misc errors. The error detection capabilities are specific to each shared +function. The execution unit hardware itself does not perform message validation prior to transmission. +In both cases, information regarding the erroneous message is captured and made visible through MMIO +registers, and the driver notified via an interrupt mechanism . The set of possible errors is listed in +Message Errors with the associated outcome. + +Error Cases + Error Outcome +Bad Shared Function ID The message is discarded before reaching any shared function. If the message specified a + destination, those registers will be marked as in-flight, and any future usage by the thread of + those registers will cause a dependency which will never clear, resulting in a hung thread + and eventual time-out. + The destination shared function detects unknown opcodes (as specified in the ‘send’ + Unknown opcode + instructions field), and known opcodes where the message payload is either too long + Incorrect message or too short, and threats these cases as errors. When detected, the shared function latches + length and makes available via MMIO registers the following information: the EU and thread ID + which sent the message, the length of the message and expected response, and any + relevant portions of the first register (R0) of the message payload. The shared function alerts + the driver of an erroneous message through and interrupt mechanism , then continues + normal operation with the subsequent message. +Bad message contents Detection of bad data is an implementation decision of the shared function. Not all fields may +in payload be checked by the shared function, so an erroneous payload may return bogus data or no + data at all. If an erroneous value is detected by the shared function, it is free to discard the + message and continue with the subsequent message. If the thread was expecting a + response, the destination registers specified in the associated ‘send’ instruction are never + cleared potentially resulting in a hung thread and time-out. +Incorrect response + Case: too few registers specified – the thread may proceed with execution prior to all the +length + data returning from the shared function, resulting in the thread operating on bad data in the + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 10 + Error Outcome + GRF. + Case: too many registers specified – the message response does not clear all the registers + of the destination. In this case, if the thread references any of the residual registers, it may + hand and result in an eventual time-out. +Improper use of End- + Any ‘send’ instruction which specifies EOT must have a ‘null’ destination register. The EU +Of-Thread (EOT) + enforces this and, if detected, will not issue the ‘send’ instruction, resulting in a hung thread + and an eventual time-out. + The ‘send’ instruction specifies that EOT is only recognized if the field of the + instruction is an immediate. Should a thread attempt to end a thread using a + sourced from a register, the EOT bit will not be recognized. In this case, the thread will + continue to execute beyond the intended end of thread, resulting in a wide range of error + conditions. + +Two outstanding This is not checked by HW. Due to varying latencies between two messages, and out-of- +messages using order, non-contiguous writeback cycles, the outcome in the GRF is indeterminate; may be +overlapping GRF the result from the first message, or the result from the second message, or a combination of +destinations ranges both. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 11 + 2. Sampling Engine +The Sampling Engine provides the capability of advanced sampling and filtering of surfaces in memory. +The sampling engine function is responsible for providing filtered texture values to the Core in response +to sampling engine messages. The sampling engine uses SAMPLER_STATE to control filtering modes, +address control modes, and other features of the sampling engine. A pointer to the sampler state is +delivered with each message, and an index selects one of 16 states pointed to by the pointer. Some +messages do not require SAMPLER_STATE. In addition, the sampling engine uses SURFACE_STATE +to define the attributes of the surface being sampled. This includes the location, size, and format of the +surface as well as other attributes. +Although data is commonly used for “texturing” of 3D surfaces, the data can be used for any purpose +once returned to the execution core. +The following table summarizes the various subfunctions provided by the Sampling Engine. After the +appropriate subfunctions are complete, the 4-component (reduced to fewer components in some cases) +filtered texture value is provided to the Core in order to complete the sample instruction. + Subfunction Description +Texture Coordinate Any required operations are performed on the incoming pixel’s interpolated internal texture +Processing coordinates. These operations may include: cube map intersection. +Texel Address The Sampling Engine will determine the required set of texel samples (specific texel values +Generation from specific texture maps), as defined by the texture map parameters and filtering modes. + This includes coordinate wrap/clamp/mirror control, mipmap LOD computation and sample + and/or miplevel weighting factors to be used in the subsequent filtering operations. +Texel Fetch The required texel samples will be read from the texture map. This step may require + decompression of texel data. The texel sample data is converted to an internal format. +Texture Palette For streams which have “paletted” texture surface formats, this function uses the “index” values +Lookup read from the texture map to look up texel color data from the texture palette. +Shadow Pre-Filter + For shadow mapping, the texel samples are first compared to the 3 rd (R) component of the +Compare + pixel’s texture coordinate. The boolean results are used in the texture filter. + +Texel Filtering Texel samples are combined using the filter weight coefficients computed in the Texture + Address Generation function. This “combination” ranges from simply passing through a + “nearest” sample to blending the results of anisotropic filters performed on two mipmap levels. + The output of this function is a single 4-component texel value. +Texel Color Gamma Performs optional gamma decorrection on texel RGB (not A) values. +Linearization + Denoise/ Performs denoise and deinterlacing functions for video content () + Deinterlacer +8x8 Video Scaler + Performs scaling using an 8x8 filter () +Image Enhancement + Image Enhancement functions for video content () +Filter / Video Signal +Analysis + + + +2.1 Texture Coordinate Processing +The Texture Coordinate Processing function of the Sampling Engine performs any operations on the +texture coordinates that are required before physical addresses of texel samples can be generated. + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 12 + 2.1.1 Texture Coordinate Normalization +A texture coordinate may have normalized or unnormalized values. In this function, unnormalized +coordinates are normalized. +Normalized coordinates are specified in units relative to the map dimensions, where the origin is located +at the upper/left edge of the upper left texel, and the value 1.0 coincides with the lower/right edge of the +lower right texel . 3D rendering typically utilizes normalized coordinates. +Unnormalized coordinates are in units of texels and have not been divided (normalized) by the associated +map’s height or width. Here the origin is the located at the upper/left edge of the upper left texel of the +base texture map. Unnormalized coordinates delivered to the sampling engine are only supported with +the “ld” type messages. + +Normalized vs. Unnormalized Texture Coordinates + + + + +2.1.2 Texture Coordinate Computation +Cartesian (2D) and homogeneous (projected) texture coordinate values are projected from (interpolated) +screen space back into texture coordinate space by dividing the pixel’s S and T components by the Q +component. This operation is done as part of the pixel shader kernel in the Core. +Vector (cube map) texture coordinates are generated by first determining which of the 6 cube map faces +(+X, +Y, +Z, -X, -Y, -Z) the vector intersects. The vector component (X, Y or Z) with the largest absolute +value determines the proper (major) axis, and then the sign of that component is used to select between +the two faces associated with that axis. The coordinates along the two minor axes are then divided by the +coordinate of the major axis, and scaled and translated, to obtain the 2D texture coordinate ([0,1]) within +the chosen face. Note that the coordinates delivered to the sampling engine must already have been +divided by the component with the largest absolute value. +An illustration of this cube map coordinate computation, simplified to only two dimensions, is provided +below: + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 13 + Cube Map Coordinate Computation Example + + + + +2.2 Texel Address Generation +To better understand texture mapping, consider the mapping of each object (screen-space) pixel onto the +textures images. In texture space, the pixel becomes some arbitrarily sized and aligned quadrilateral. Any +given pixel of the object may “cover” multiple texels of the map, or only a fraction of one texel. For each +pixel, the usual goal is to sample and filter the texture image in order to best represent the covered texel +values, with a minimum of blurring or aliasing artifacts. Per-texture state variables are provided to allow +the user to employ quality/performance/footprint tradeoffs in selecting how the particular texture is to be +sampled. +The Texel Address Generation function of the Sampling Engine is responsible for determining how the +texture maps are to be sampled. Outputs of this function include the number of texel samples to be taken, +along with the physical addresses of the samples and the filter weights to be applied to the samples after +they are read. This information is computed given the incoming texture coordinate and gradient values, +and the relevant state variables associated with the sampler and surface. This function also applies the +texture coordinate address controls when converting the sample texture coordinates to map addresses. + + +2.2.1 Level of Detail Computation (Mipmapping) +Due to the specification and processing of texture coordinates at object vertices, and the subsequent +object warping due to a perspective projection, the texture image may become magnified (where a texel +covers more than one pixel) or minified (a pixel covers more than one texel) as it is mapped to an object. +In the case where an object pixel is found to cover multiple texels (texture minification), merely choosing +one (e.g., the texel sample nearest to the pixel’s texture coordinate) will likely result in severe aliasing +artifacts. +Mipmapping and texture filtering are techniques employed to minimize the effect of undersampling these +textures. With mipmapping, software provides mipmap levels, a series of pre-filtered texture maps of +decreasing resolutions that are stored in a fixed (monolithic) format in memory. When mipmaps are +provided and enabled, and an object pixel is found to cover multiple texels (e.g., when a textured object is + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 14 + located a significant distance from the viewer), the device will sample the mipmap level(s) offering a +texel/pixel ratio as close to 1.0 as possible. +The device supports up to 14 mipmap levels per map surface, ranging from 8192 x 8192 texels to a 1 X 1 +texel. Each successive level has ½ the resolution of the previous level in the U and V directions (to a +minimum of 1 texel in either direction) until a 1x1 texture map is reached. The dimensions of mipmap +levels need not be a power of 2. +Each mipmap level is associated with a Level of Detail (LOD) number. LOD is computed as the +approximate, log2 measure of the ratio of texels per pixel. The highest resolution map is considered LOD +0. A larger LOD number corresponds to lower resolution mip level. +The Sampler[]BaseMipLevel state variable specifies the LOD value at which the minification filter vs. the +magnification filter should be applied. +When the texture map is magnified (a texel covers more than one pixel), the base map (LOD 0) texture +map is accessed, and the magnification mode selects between the nearest neighbor texel or bilinear +interpolation of the 4 neighboring texels on the base (LOD 0) mipmap. + +2.2.1.1 Base Level Of Detail (LOD) +The per-pixel LOD is computed in an implementation-dependent manner and approximates the log2 of the +texel/pixel ratio at the given pixel. The computation is typically based on the differential texel-space +distances associated with a one-pixel differential distance along the screen x- and y-axes. These texel- +space distances are computed by evaluating neighboring pixel texture coordinates, these coordinates +being in units of texels on the base MIP level (multiplied by the corresponding surface size in texels). The +q coordinates represent the third dimension for 3D (volume) surfaces, this coordinate is a constant 0 for +2D surfaces. +The ideal LOD computation is included below. + + + + +2.2.1.2 LOD Bias +A biasing offset can be applied to the computed LOD and used to artificially select a higher or lower +miplevel and/or affect the weighting of the selected mipmap levels. Selecting a slightly higher mipmap +level will trade off image blurring with possibly increased performance (due to better texture cache reuse). +Lowering the LOD tends to sharpen the image, though at the expense of more texture aliasing artifacts. +The LOD bias is defined as sum of the LODBias state variable and the pixLODBias input from the input +message (which can be non-zero only for sample_b messages). The application of LOD Bias is +unconditional, therefore these variables must both be set to zero in order to prevent any undesired +biasing. +Note that, while the LOD Bias is applied prior to clamping and min/mag determination and therefore can +be used to control the min-vs-mag crossover point, its use has the undesired effect of actually changing +the LOD used in texture filtering. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 15 + 2.2.1.3 LOD Pre-Clamping +The LOD Pre-Clamping function can be enabled or disabled via the LODPreClampEnable state variable. +Enabling pre-clamping matches OpenGL semantics, while disabling it matches . +After biasing and/or adjusting of the LOD , the computed LOD value is clamped to a range specified by +the (integer and fractional bits of) MinLOD and MaxLOD state variables prior to use in Min/Mag +Determination. +MaxLOD specifies the lowest resolution mip level (maximum LOD value) that can be accessed, even +when lower resolution maps may be available. Note that this is the only parameter used to specify the +number of valid mip levels that be can be accessed, i.e., there is no explicit “number of levels stored in +memory” parameter associated with a mip-mapped texture. All mip levels from the base mip level map +through the level specified by the integer bits of MaxLOD must be stored in memory, or operation is +UNDEFINED. +MinLOD specifies the highest resolution mip level (minimum LOD value) that can be accessed, where +LOD==0 corresponds to the base map. This value is primarily used to deny access to high-resolution mip +levels that have been evicted from memory when memory availability is low. +MinLOD and MaxLOD have both integer and fractional bits. The fractional parts will limit the inter-level +filter weighting of the highest or lowest (respectively) resolution map. For example if MinLOD is 4.5 and +MipFilter is LINEAR, LOD 4 can contribute only up to 50% of the final texel color. + +2.2.1.4 Min/Mag Determination +The biased and clamped LOD is used to determine whether the texture is being minified (scaled down) or +magnified (scaled up). +The BaseMipLevel state variable is subtracted from the biased and clamped LOD. The BaseMipLevel +state variable therefore has the effect of selecting the “base” mip level used to compute Min/Map +Determination. (This was added to match OpenGL semantics). Setting BaseMipLevel to 0 has the effect +of using the highest-resolution mip level as the base map. +If the biased and clamped LOD is non-positive, the texture is being magnified, and a single (high- +resolution) miplevel will be sampled and filtered using the MagFilter state variable. At this point the +computed LOD is reset to 0.0. Note that LOD Clamping can restrict access to high-resolution miplevels. +If the biased LOD is positive, the texture is being minified. In this case the MipFilter state variable +specifies whether one or two mip levels are to be included in the texture filtering, and how that (or those) +levels are to be determined as a function of the computed LOD. + +2.2.1.5 LOD Computation Pseudocode +This section illustrates the LOD biasing and clamping computation in pseudocode, encompassing the +steps described in the previous sections. The computation of the initial per-pixel LOD value LOD is not +shown. + + +Bias:S4.8 +MinLod:U4.8 +MaxLod:U4.8 +Base:U4.1 +MIPCnt:U4 + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 16 + SurfMinLod: U4.8 +ResMinLod: U4.8 + + +AdjMaxLod = min(MaxLod, MIPCnt) +AdjMinLod = min(MinLod, MIPCnt) +AdjPR_minLOD = ResMinLod – SurfMinLod +AdjMinLod = max(AdjMinLod, AdjPR_minLOD) +Out_of_Bounds = AdjPR_minLOD > MIPCnt + + +if (sample_b) + LOD += Bias + bias_parameter +else if (sample_l or ld) + LOD = Bias + lod_parameter +else + LOD += Bias +PreClamp = LODPreClampEnable +If (PreClamp) + LOD = min(LOD, MaxLod) + LOD = max(LOD, MinLod) +MagMode = (LOD - Base <= 0) +MagClampMipNone = 1 +If ((MagMode && MagClampMipNone) or MipFlt = None) + LOD = 0 + LOD = min(LOD, ceil(AdjMaxLod)) + LOD = max(LOD, floor(AdjMinLod)) +else if (MipFlt = Nearest) + LOD = min(LOD, AdjMaxLod) + LOD = max(LOD, AdjMinLod) + LOD = min(LOD, AdjMaxLod) + LOD = max(LOD, AdjMinLod) + LOD +=0.5 + LOD = floor(LOD) +else// MipFlt = Linear + LOD = min(LOD, AdjMaxLod) + LOD = max(LOD, AdjMinLod) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 17 + TriBeta = frac(LOD) + LOD0 = floor(LOD) + LOD1 = LOD0 + 1 + +if (!lod)// “LOD” message type +Lod += SurfMinLod +If Out_of_Bounds is true, LOD is set to zero and instead of sampling the surface the texels are replaced +with zero in all channels, except for surface formats that don’t contain alpha, for which the alpha channel +is replaced with one. These texels then proceed through the rest of the pipeline. +Errata: Out of Bound true on surface format that doesn’t contain alpha will be forced to 0 instead of 1.0 for +the case the filet type is Anisotropic. +Errata: when AdjPR_minLOD > MIPCnt and MIPFILTER_LINEAR texel values will not force to zero. + +2.2.1.5.1 Inter-Level Filtering Setup +The MipFilter state variable determines if and how texture mip maps are to be used and combined. The +following table describes the various mip filter modes: + + MipFilter Value + Description +MIPFILTER_NONE Mipmapping is DISABLED. Apply a single filter on the highest resolution map available (after + LOD clamping). +MIPFILTER_NEAREST Choose the nearest mipmap level and apply a single filter to it. Here the biased LOD will be + rounded to the nearest integer to obtain the desired miplevel. LOD Clamping may further + restrict this miplevel selection. +MIPFILTER_LINEAR Apply a filter on the two closest mip levels and linear blend the results using the distance + between the computed LOD and the level LODs as the blend factor. Again, LOD Clamping + may further restrict the selection of miplevels (and the blend factor between them). + +When minifying and MIPFILTER_NEAREST is selected, the computed LOD is rounded to the nearest mip +level. +When minifying and MIPFILTER_LINEAR is selected, the fractional bits of the computed LOD are used to +generate an inter-level blend factor. The LOD is then truncated. The mip level selected by the truncated +LOD, and the next higher (lower resolution) mip level are determined. +Regardless of MipFilter and the min/mag determination, all computed LOD values (two for +MIPFILTER_LINEAR, otherwise one) are then unconditionally clamped to the range specified by the +(integer bits of) MinLOD and MaxLOD state variables. + + +2.2.2 Intra-Level Filtering Setup +Depending on whether the texture is being minified or magnified, the MinFilter or MagFilter state variable +(respectively) is used to select the sampling filter to be used within a mip level (intra-level, as opposed to +any inter-level filter). Note that for volume maps, this selection also applies to filtering between layers. +The processing at this stage is restricted to the selection of the filter type, computation of the number and +texture map coordinates of the texture samples, and the computation of any required filter parameters. +The filtering of the samples occurs later on in the Sampling Engine function. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 18 + The following table summarizes the intra-level filtering modes. + Sampler[]Min/MagFilter + value Description +MAPFILTER_NEAREST Supported on all surface types. The texel nearest to the pixel’s U,V,Q coordinate is + read and output from the filter. +MAPFILTER_LINEAR Not supported on buffer surfaces. The 2, 4, or 8 texels (depending on 1D, 2D/CUBE, or + 3D surface, respectively) surrounding the pixel’s U,V,Q coordinate are read and a + linear filter is applied to produce a single filtered texel value. +MAPFILTER_ANISOTROPIC Not supported on buffer or 3D surfaces. A projection of the pixel onto the texture map is + generated and “subpixel” samples are taken along the major axis of the projection + (center axis of the longer dimension). The outermost subpixels are weighted according + to closeness to the edge of the projection, inner subpixels are weighted equally. Each + subpixel samples a bilinear 2x2 of texels and the results are blended according to + weights to produce a filtered texel value. +MAPFILTER_MONO Supported only on 2D surfaces. This filter is only supported with the monochrome + (MONO8) surface format. The monochrome texel block of the specified size + surrounding the pixel is selected and filtered. + + +2.2.2.1 MAPFILTER_NEAREST +When the MAPFILTER_NEAREST is selected, the texel with coordinates nearest to the pixel’s texture +coordinate is selected and output as the single texel sample coordinates for the level. + +2.2.2.2 MAPFILTER_LINEAR +The following description indicates behavior of the MIPFILTER_LINEAR filter for 2D and CUBE surfaces. +1D and 3D surfaces follow a similar method but with a different number of dimensions available. +When the MAPFILTER_LINEAR filter is selected on a 2D surface, the 2x2 region of texels surrounding +the pixel’s texture coordinate are sampled and later bilinearly filtered. + +Bilinear Filter Sampling + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 19 + The four texels surrounding the pixel center are chosen for the bilinear filter. The filter weights each +texel’s contribution according to its distance from the pixel center. Texels further from the pixel center +receive a smaller weight. + +2.2.2.3 MAPFILTER_ANISOTROPIC +The MAPFILTER_ANISOTROPIC texture filter attempts to compensate for the anisotropic mapping of +pixels into texture map space. A possibly non-square set of texel sample locations will be sampled and +later filtered. The MaxAnisotropy state variable is used to select the maximum aspect ratio of the filter +employed, up to 16:1. +The algorithm employed first computes the major and minor axes of the pixel projection onto the texture +map. LOD is chosen based on the minor axis length in texel space. The anisotropic “ratio” is equal to the +ratio between the major axis length and the minor axis length. The next larger even integer above the +ratio determines the anisotropic number of “ways”, which determines how many subpixels are chosen. A +line along the major axis is determined, and “subpixels” are chosen along this line, spaced one texel +apart, as shown in the diagram below. In this diagram, the texels are shown in light blue, and the pixels +are in yellow. + + + + +Each subpixel samples a bilinear 2x2 around it just as if it was a single pixel. The result of each subpixel +is then blended together using equal weights on all interior subpixels (not including the two endpoint +subpixels). The endpoint subpixels have lesser weight, the value of which depends on how close the +“ratio” is to the number of “ways”. This is done to ensure continuous behavior in animation. + +2.2.2.4 MAPFILTER_MONO +When the MAPFILTER_MONO filter is selected, a block of monochrome texels surrounding the pixel +sample location are read and filtered using the kernel described below. The size of this block is controlled +by Monochrome Filter Height and Width (referred to here as Nv and Nu, respectively) state. Filters from +1x1 to 7x7 are supported (not necessarily square). +The figure below shows a 6x5 filter kernel as an example. The footprint of the filter (filter kernel samples) +is equal to the size of the filter and the pixel center lies at the exact center of this footprint. The position of +the upper left filter kernel sample (uf, vf) relative to the pixel center at (u, v) is given by the following: + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 20 + u and v are the fractional parts of uf and vf, respectively. The integer parts select the upper left texel for +the kernel filter, given here as T0,0. + +Sampling Using MAPFILTER_MONO + + + + +The formula for the final filter output F is given by the following. Since this is a monochrome filter, each +texel value (T) is a single bit, and the output F is an intensity value that is replicated across the color and +alpha channels. + + + + +2.2.3 Texture Address Control +The [TCX,TCY,TCZ]ControlMode state variables control the access and/or generation of texel data when +the specific texture coordinate component falls outside of the normalized texture map coordinate range +[0,1). + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 21 + Note: For Wrap Shortest mode, the setup kernel has already taken care of correctly interpolating the +texture coordinates. Software will need to specify TEXCOORDMODE_WRAP mode for the sampler that +is provided with wrap-shortest texture coordinates, or artifacts may be generated along map edges. + + TC[X,Y,Z] Control + Operation +TEXCOORDMODE_CLAMP Clamp to the texel value at the edge of the map. +TEXCOORDMODE_CLAMP_BORDER Use the texture map’s border color for any texel samples falling outside the + map. The border color is specified via a pointer in SAMPLER_STATE. +TEXCOORDMODE_HALF_BORDER Similar to CLAMP_BORDER except texels outside of the map are clamped to + a value halfway between the edge texel and the border color. +TEXCOORDMODE_WRAP Upon crossing an edge of the map, repeat at the other side of the map in the + same dimension. +TEXCOORDMODE_CUBE Only used for cube maps. Here texels from adjacent cube faces can be + sampled along the edges of faces. This is considered the highest quality + mode for cube environment maps. +TEXCOORDMODE_MIRROR Similar to the wrap mode, though reverse direction through the map each + time an edge is crossed. INVALID for use with unnormalized texture + coordinates. +TEXCOORDMODE_MIRROR_ONCE Similar to the wrap mode, though reverse direction through the map each + time an edge is crossed. INVALID for use with unnormalized texture + coordinates. + +Separate controls are provided for texture TCX, TCY, TCZ coordinate components so, for example, the +TCX coordinate can be wrapped while the TCY coordinate is clamped. Note that there are no controls +provided for the TCW component as it is only used to scale the other 3 components before addressing +modes are applied. +Maximum Wraps/Mirrors +The number of map wraps on a given object is limited to 32. Going beyond this limit is legal, but may +result in artifacts due to insufficient internal precision, especially evident with larger surfaces. Precision +loss starts at the subtexel level (slight color inaccuracies) and eventually reaches the texel level (choosing +the wrong texels for filtering). + +2.2.3.1 TEXCOORDMODE_MIRROR Mode +TEXCOORDMODE_MIRROR addressing mode is similar to Wrap mode, though here the base map is +flipped at every integer junction. For example, for U values between 0 and 1, the texture is addressed +normally, between 1 and 2 the texture is flipped (mirrored), between 2 and 3 the texture is normal again, +and so on. The second row of pictures in the figure below indicate a map that is mirrored in one direction +and then both directions. You can see that in the mirror mode every other integer map wrap the base map +is mirrored in either direction. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 22 + Texture Wrap vs. Mirror Addressing Mode + + + + +2.2.3.2 TEXCOORDMODE_WRAP Mode +In TEXCOORDMODE_WRAP addressing mode, the integer part of the texture coordinate is discarded, +leaving only a fractional coordinate value. This results in the effect of the base map ([0,1)) being +continuously repeated in all (axes-aligned) directions. Note that the interpolation between coordinate +values 0.1 and 0.9 passes through 0.5 (as opposed to WrapShortest mode which interpolates through +0.0). + +2.2.3.3 TEXCOORDMODE_MIRROR_ONCE Mode +The TEXCOORDMODE_MIRROR_ONCE addressing mode is a combination of Mirror and Clamp +modes. The absolute value of the texture coordinate component is first taken (thus mirroring about 0), +and then the result is clamped to 1.0. The map is therefore mirrored once about the origin, and then +clamped thereafter. This mode is used to reduce the storage required for symmetric maps. + +2.2.3.4 TEXCOORDMODE_CLAMP Mode +The TEXCOORDMODE_CLAMP addressing mode repeats the “edge” texel when the texture coordinate +extends outside the [0,1) range of the base texture map. This is contrasted to +TEXCOORDMODE_CLAMPBORDER mode which defines a separate texel value for off-map samples. +TEXCOORDMODE_CLAMP is also supported for cube maps, where texture samples will only be +obtained from the intersecting face (even along edges). +The figure below illustrates the effect of clamp mode. The base texture map is shown, along with a +texture mapped object with texture coordinates extending outside of the base map region. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 23 + Texture Clamp Mode + + + + +2.2.3.5 TEXCOORDMODE_CLAMPBORDER Mode +For non-cube map textures, TEXCOORDMODE_CLAMPBORDER addressing mode specifies that the +texture map’s border value BorderColor is to be used for any texel samples that fall outside of the base +map. The border color is specified via a pointer in SAMPLER_STATE. + +2.2.3.6 TEXCOORDMODE_CUBE Mode +For cube map textures TEXCOORDMODE_CUBE addressing mode can be set to allow inter-face +filtering. When texel sample coordinates that extend beyond the selected cube face (e.g., due to intra- +level filtering near a cube edge), the correct sample coordinates on the adjoining face will be computed. +This will eliminate artifacts along the cube edges, though some artifacts at cube corners may still be +present. + + +2.3 Texel Fetch +The Texel Fetch function of the Sampling Engine reads the texture map contents specified by the texture +addresses associated with each texel sample. The texture data is read either directly from the memory- +resident texture map, or from internal texture caches. The texture caches can be invalidated by the +Sampler Cache Invalidate field of the MI_FLUSH instruction or via the Read Cache Flush Enable bit of +PIPE_CONTROL. Except for consideration of coherency with CPU writes to textures and rendered +textures, the texture cache does not affect the functional operation of the Sampling Engine pipeline. +When the surface format of a texture is defined as being a compressed surface, the Sampler will +automatically decompress from the stored format into the appropriate [A]RGB values. The compressed +texture storage formats and decompression algorithms can be found in the Memory Data Formats +chapter. When the surface format of a texture is defined as being an index into the texture palette (format +names includiong “Px”), the palette lookup of the index determines the appropriate RGB values. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 24 + 2.3.1 Texel Chroma Keying +ChromaKey is a term used to describe a method of effectively removing or replacing a specific range of +texel values from a map that is applied to a primitive, e.g., in order to define transparent regions in an +RGB map. The Texel Chroma Keying function of the Sampling Engine pipeline conditionally tests texel +samples against a “key” range, and takes certain actions if any texel samples are found to match the key. + +2.3.1.1 Chroma Key Testing +ChromaKey refers to testing the texel sample components to see if they fall within a range of texel values, +as defined by ChromaKey[][High,Low] state variables. If each component of a texel sample is found to lie +within the respective (inclusive) range and ChromaKey is enabled, then an action will be taken to remove +this contribution to the resulting texel stream output. Comparison is done separately on each of the +channels and only if all 4 channels are within range the texel will be eliminated. +The Chroma Keying function is enabled on a per-sampler basis by the ChromaKeyEnable state variable. +The ChromaKey[][High,Low] state variables define the tested color range for a particular texture map. + +2.3.1.2 Chroma Key Effects +There are two operations that can be performed to “remove” matching texel samples from the image. The +ChromaKeyEnable state variable must first enable the chroma key function. The ChromaKeyMode state +variable then specifies which operation to perform on a per-sampler basis. +The ChromaKeyMode state variable has the following two possible values: +KEYFILTER_KILL_ON_ANY_MATCH: Kill the pixel if any contributing texel sample matches the key +KEYFILTER_REPLACE_BLACK: Here the sample is replaced with (0,0,0,0). . +The Kill Pixel operation has an effect on a pixel only if the associated sampler is referenced by a sample +instruction in the pixel shader program. If the sampler is not referenced, the chroma key compare is not +done and pixels cannot be killed based on it. + + +2.4 Shadow Prefilter Compare +When a sample_c message type is processed, a special shadow-mapping precomparison is performed +on the texture sample values prior to filtering. Specifically, each texture sample value is compared to the +“ref” component of the input message, using a compare function selected by ShadowFunction, and +described in the table below. Note that only single-channel texel formats are supported for shadow +mapping, and so there is no specific color channel on which the comparison occurs. + + ShadowFunction + Result +PREFILTEROP_ALWAYS 0.0 +PREFILTEROP_NEVER 1.0 +PREFILTEROP_LESS (texel < ref) ? 0.0 : 1.0 +PREFILTEROP_EQUAL (texel == ref) ? 0.0 : 1.0 +PREFILTEROP_LEQUAL (texel <= ref) ? 0.0 : 1.0 +PREFILTEROP_GREATER (texel > ref) ? 0.0 : 1.0 +PREFILTEROP_NOTEQUAL (texel != ref) ? 0.0 : 1.0 +PREFILTEROP_GEQUAL (texel >= ref) ? 0.0 : 1.0 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 25 + The binary result of each comparison is fed into the subsequent texture filter operation (in place of the +texel’s value which would normally be used). +Software is responsible for programming the ”ref” component of the input message such that it +approximates the same distance metric programmed in the texture map (e.g., distance from a specific +light to the object pixel). In this way, the comparison function can be used to generate “in shadow” status +for each texture sample, and the filtering operation can be used to provide soft shadow edges. +Programming Notes: + +  Refer to the Surface Formats table in the section SURFACE_STATE for most messages for the specific surface + formats that are supported with shadow mapping. + + + +2.5 Texel Filtering +The Texel Filtering function of the Sampling Engine performs any required filtering of multiple texel values +on and possibly between texture map layers and levels. The output of this function is a single texel color +value. +The state variables MinFilter, MagFilter, and MipFilter are used to control the filtering of texel values. The +MipFilter state variable specifies how many mipmap levels are included in the filter, and how the results of +any filtering on these separate levels are combined to produce a final texel color. The MinFilter and +MagFilter state variables specify how texel samples are filtered within a level. + + +2.6 Texel Color Gamma Linearization +This function is supported to allow pre-gamma-corrected texel RGB (not A) colors to be mapped back into +linear (gamma=1.0) gamma space prior to (possible) blending with, and writing to the Color Buffer. This +permits higher quality image blending by performing the blending on colors in linear gamma space. +This function is enabled on a per-texture basis by use of a surface format with “_SRGB” in its name. If +enabled, the pre-filtered texel RGB color to be converted from gamma=2.4 space to gamma=1.0 space +by applying a ^(1/2.4) = ^0.4167 exponential function. + + +2.7 Multisampled Surface Behavior +The ld message has added an additional parameter for sample index (si) to support unfiltered loading +from a multisampled surface. +The sampleinfo message returns specific parameters associated with a multisample surface. The resinfo +message returns the height, width, depth, and MIP count of the surface (in units of pixels, not samples). +Any of the other messages (sample*, LOD, load4) used with a (4x) multisampled surface would sample a +surface with double the height and width as indicated in the surface state. Each pixel position on the +original-sized surface is replaced with 2x2 samples that have the following arrangement: + sample 0 sample 2 + sample 1 sample 3 + +This behavior is useful when implementing the multisample resolve operation by selecting +MAPFILTER_LINEAR and rendering a full-screen rectangle half the size in each dimension of the source +texture map (multisampled surface). If pixel offsets are set correctly, each pixel is the average of the four +underlying samples. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 26 + 2.7.1 Multisample Control Surface +Three new messages have been defined for the sampling engine, ld_mcs, ld2dms, and ld2dss. A pixel +shader kernel sampling from an multisampled surface using an MCS must first sample from the MCS +surface using the ld_mcs message. This message behaves like the ld message, except that the surface is +defined by the MCS fields of SURFACE_STATE rather than the normal fields. The surface format is +effectively R8_UINT for 4x surfaces and R32_UINT for 8x surfaces, thus data is returned in unsigned +integer format. Following the ld_mcs, the kernel issues a ld2dms message to sample the surface itself. +The integer value from the MCS surface is delivered in the mcs parameter of this messages. +Since sample is no longer supported on multisampled surfaces, the multisample resolve must be done +using ld2dms. For surfaces with Multisampled Surface Storage Format set to MSFMT_MSS and MCS +Enable set to enabled, an optimization is available to enable higher performance for compressed pixels. +The ld2dss message can be used to sample from a particular sample slice on the surface. By examining +the MCS value, software can determine which sample slices to sample from. A simple optimization with +probable large return in performance is to compare the MCS value to zero (indicating all samples are on +sample slice 0), and sample only from sample slice 0 using ld2dss if MCS is zero. Sample slice 0 is the +pixel color in this case. If MCS is not zero, each sample is then obtained using ld2dms messages and the +results are averaged in the kernel after being returned. Refer to the multisample storage format in the +GPU Overview volume for more details. + + +2.8 Denoise/Deinterlacer +The Denoise/Deinterlacer function takes a 4:2:0 or 4:2:2 video stream and first applies a denoise filter to it +and then deinterlace it. +The denoise filter is applied before the deinterlacer. The denoise filter detects and tries to minimize noise +in the input field, while the deinterlacer takes a field consisting of every other lines converts a field into a +frame. This block also gathers statistics for a global noise estimate made in software at the end of the +frame which is used in following frames to tune the denoise filter and image enhancement filter. +The deinterlacer takes the top and bottom fields of each frame and converts them into two individual +frames. This block also gathers statistics for a film mode detector in software run at the end of the frame. +If the film mode detector for the previous frame concludes that the input is progressive rather than +interlaced then the fields will be put together in the best order rather than being interlaced. + + +2.8.1 Introduction + +2.8.1.1 Overview +This diagram shows how the Denoise/Deinterlacer fits in with the other functions of the video pipe. This is +only one possible usage model, other models are possible. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 27 + Block Diagram + + + + +2.8.1.2 Features +  Denoise Filter – detects noise and motion and filters the block with either a temporal filter when + little motion is detected or a spatial filter. Noise estimates are kept between frames and blended + together. Since the filter is before the deinterlacer it works on individual fields rather than frames. + This usually improves the operation since the deinterlacer can take a single pixel of noise and + spread it to an adjacent pixel, making it harder to remove. The denoise filter works the same whether + deinterlacing or progressive cadence reconstruction is being done. +  Block Noise Estimate (BNE) – part of the Global Noise Estimate (GNE) algorithm, this estimates + the noise over the entire block. The GNE will be calculated at the end of the frame by combining all + the BNEs. The final GNE value is used to control the denoise filter for the next frame. +  Film Mode Detection (FMD) Variances – FMD determines if the input fields were created by + sampling film and converting it to interlaced video. If so the deinterlacer is turned off in favor of + reconstructing the frame from adjacent fields. Various sum-of-absolute differences are calcluated per + block. The FMD algorithm is run at the end of the frame by looking at the variances of all blocks for + both fields in the frame. +  Deinterlacer – Estimates how much motion is occuring across the fields. Low motion scenes are + reconstructed by averaging pixels from fields from nearby times (temporal deinterlacer), while high + motion scenes are reconstructed by interpolating pixels from nearby space (spatial deinterlacer). +  Progressive Cadence Reconstruction – If the FMD for the previous frame determines that film + was converted into interlaced video, then this block reconstructs the original frame by directly putting + together adjacent fields. +  Chroma Upsampling – If the input is 4:2:0 then chroma will be doubled vertically to convert to + 4:2:2. Chroma will then either go through it’s own version of the deinterlacer or progressive cadence + reconstruction. + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 28 + When DI is enabled, the output for a 16x4 block is sent to the EU for further processing and writing to +memory. When DI is disabled and DN enabled the output for a 16x8 block is sent to the EU. +Formats supported are: +NV12 is supported for hardware video decode. +UYVY, YUY2 and NV12 are required for WHQL. +YV12 and I420 are supported for software video decode. +IMC3 and IMC4 are supported as internal temporary formats. +NV11 and P208 are not supported, since they have been removed from the WHQL logo requirement. + + +2.8.2 Denoise Algorithm + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 29 + 2.8.2.1 Motion Detection and Noise History Update +This block detection motion for the denoise filter, which it then combines with motion detected in the past +in the same part of the screen. The Denoise History is both saved to memory and also used to control the +temporal denoise filter. +The block calculates a number of values for updating the Denoise History. One value is calculated per +4x4 block (pixels from both fields, interleaved): +Block Sum of Temporal Absolute Difference: + + +BK_STAD = +Where curr(x,y) and prev(x,y) are lumas from the current and previous field. The previous field should +have already been run through the denoise filter. +Count of motion pixels: increment BK_Motion_Pixel for every pixel in the 4x4 for which: (abs(curr(x,y) – +prev(x,y)) >= temporal_diff_th. +Absolute Sum of Temporal Difference sums the differences without the initial absolute value, so that +random motions will tend to cancel out: + + + +BK_TASD = +Sum of Complexity Measure looks for differences in the spatial domain: + + + +BK_SHCM = // sum of 12 pixel pairs + + + +BK_SVCM = // sum of 12 pixel pairs +BK_SCM = BK_SHCM + BK_SVCM +Denoise Motion History Update (for an 8-bit motion history): +if (BK_STAD>dnmh_stad_th) or (BK_Motion_Pixel > dnmh_mp_th) { // Motion Block + motion_block = 1; + if (denoise_history >= 128) +new_denoise_history = denoise_history / 2; + else +new_denoise_history = 0; +} else { // static block + motion_block = 0; + if (denoise_history < 128) +new_denoise_history = 128; + else if (denoise_history < dnmh_history_max) +new_denoise_history = denoise_history + dnmh_delta; // default value 8 for delta + else +new_denoise_history = denoise_history; + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 30 + if ((BK_TASD > dnmh_tasd_th) and (BK_SCM < dnmh_scm_th)) +new_denoise_history = 128; +} + + +2.8.2.2 Temporal Filter +For each pixel we need to filter we look at the noise history for the associated 4x4. +temporal_denoised = (new_denoise_history * prev(x,y) + (256 – new_denoise_history) * curr(x,y) +128) +>> 8 + +2.8.2.3 Context Adaptive Spatial Filter +For each pixel in the local 3x3, compare it’s luma to the lumas of the pixel to be filtered. Each pixel for +which the absolute difference is less than or equal to good_neighbor_th is marked as a “good neighbor”: +The filtered pixel is then equal to: + spatial_denoised = ∑ Good_neighbor luma / num_good_neighbors +The divide is implemented as a multiply by a table lookup: + spatial_denoised = ((∑Good_neighbor luma + (num_good_neighbors >>1)) * +gn_q_table[num_good_neighbors-1]) >> 11 +Note: The number of good neighbors varies from 1 to 9 since the center pixel is always good. Gn_q_table +provides the reciprocal: + gn_q_table[9] = {2048, 1024, 682, 512, 409, 341, 292, 256, 227}; + +2.8.2.4 Denoise Blend +The denoise blend combines the temporal and spatial denoise outputs. +First we check to see if the temporal is out of the local range, if so we use the average of the denoised +and the local limit instead: +if (temporal_denoised >= block_max) + temporal_denoised=(temporal_denoised+block_max)>>1; +if (temporal_denoised < block_min) + temporal_denoised=(temporal_denoised+block_min)>>1; +Where block_max and block_min are the largest and smallest luma values in the local 3x3 (can be +shared with BNE calculation). +Next we decide between using the spatial and temporal denoise output: + t_diff = abs(curr(x,y) – prev(x,y); + if (t_diff < temporal_diff_th) { + if (motion_block==1) + denoise_out = spatial_denoised; + else { + if (t_diff < temp_diff_low) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 31 + denoise_out=temporal_denoised; + else { + denoise_out= + (spatial_denoised*(t_diff-temp_diff_low) + + temporal_denoised*(temporal_diff_th-t_diff)+ + (temporal_diff_th-temp_diff_low)/2 + ) * q_table[temporal_diff_th-temp_diff_low-1]) >> 10; + } + } else { + denoise_out = spatial_denoised; + } +Motion_block is defined in section Denoise Algorithm above. T_diff can be limited to 6-bits to minimize the +multipler gates required in the blend. A divide is eliminated by providing the reciprocal of the divisor in the +q_table which is defined: +q_table[16] = {1024,512,341,256,205,171,146,128,114,102,93,85,79,73,68,64} +The following restrictions also apply: + 1. Temporal_diff_th – temp_diff_low is limited in the state variable definition to the range 16 to 1. + 2. Since t_diff=temp_diff_low; (temporal_diff_th-t_diff) is less then or equal to 16. +The precision needed for spatial_denoised*(t_diff-temp_diff_low) is 8-bit times 4-bits to produce 12-bits. +The other multiply is 8 by 5 to produce 13-bits; the extra bit is needed for 16. The multiplier to implement +the divide will be a 13-bit times the 11-bit number out of q_table, but this could be reduced by +implementing a 13x9 bit multiplier with the top 2 bits controlling a mux since the only table entries that use +them are 1024 and 512. + + +2.8.3 Block Noise Estimate (part of Global Noise Estimate) +Edge detection is done on every pixel in the 16x4 (DI enabled) or 16x8 (DN only) by estimating a gradient +on the 3x3 neighborhood of pixels in the current field. The calculation only uses a multiply of 2, so shifts +and add are all that is needed. Currently only vertical and horizontal edges are detected, 45 degrees is a +potential improvement. +Hrz Edge = abs(c(x-1,y-1) +2*c(x,y-1) +c(x+1,y-1) –c(x-1,y+1) –2*c(x,y+1) –c(x+1,y+1)) +Vrt Edge = abs(c(x-1,y-1) +2*c(x-1,y) +c(x-1,y+1) –c(x+1,y-1) –2*c(x+1,y) –c(x+1,y+1)) +The Hrz_Edge and Vrt_Edge are added together and if the sum is greater than bne_edge_th then an +edge is detected: + ED = (Hrz_Edge +Vrt_Edge) >> 3 + +  median9 – the median of the 9 luma values for the 3x3 neighborhood pixels is used. Median5, the + median of the pixels above/below/right/left/center may be satisfactory as a lower gate count solution. +  for each pixel luma “y” in 3x3: noise_metric = sum(y – median9) +  noise_min = min(abs(y-median9)) - min of all 9 ys in 3x3 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 32 +  noise_max = max(abs(y-median9)) – max of all 9 ys in 3x3 +  noise_min_max = noise_max(x,y) – noise_min(x,y) +  pixel_noise_metric = noise_metric if (ED(x,y) < bne_edge_th) and (noise_max_min(x,y) < + bne_nn_th) block_noise_estimate = min of all pixel_noise_metrics that pass the if test in the 16x4 + (use 255 if no pixels pass the test) + +If the block_noise_estimate is less than 255 then it is added to a sum gathered across the entire frame. +The summation will need to be 23-bits wide to be able to sum 8-bit values for all 32,400 blocks in a +1920x1080 frame. In addition, there will be a count of the number of blocks in the sum. The data will be +written to memory at the end of the frame. Two sets of counters are needed to support 2 simultaneous +streams. The streams are distinguished by the dndi_stream_id state variable in the DI state. +The per block block_noise_estimate is also sent to the EU in the output message for possible use by the +video encoder. + + +2.8.4 Deinterlacer Algorithm +The overall goal of the motion adaptive deinterlacer is to convert an interlaced video stream made of +fields of alternating lines into a progressive video stream made of frames in which every line is provided. +If there is no motion in a scene, then the missing lines can be provided by looking at the previous or next +fields, both of which have the missing lines. If there is a great deal of motion in the scene, then objects in +the previous and next fields will have moved, so we can’t use them for the missing pixels. Instead we +have to interpolate from the neighboring lines to fill in the missing pixels. This can be thought of as +interpolating in time if there is no motion and interpolating in space if there is motion. +This idea is implemented by creating a measure of motion on a per 2 pixel basis called the Spatial- +Temporal Motion Measure (STMM). If this measure shows that there is little motion in an area around the +pixels, then the missing pixels are created by averaging the pixel values from the previous and next +frame. If the STMM shows that there is motion, then the missing pixels are filled in by interpolating from +neighboring lines with the Spatial Deinterlacer (SDI). The two different ways to interpolate the missing +pixels are blended for intermediate values of STMM to prevent sudden transitions. +The Deinterlacer uses two frames for reference. The current frame contains the field that we are +deinterlacing. The reference frame is the closest frame in time to the field that we are deinterlacing – if we +are working on the 1st field then it is the previous frame, if it is the 2nd field then it is the next frame. + +2.8.4.1 Spatial-Temporal Motion Measure +This algorithm combines a complexity measure with a estimate of motion. This prevents high complexity +scenes from incorrectly causing motion to be detected. It is calculated for a set of pixels 2 wide by 1 high. +Complexity is measured in the vertical and horizontal directions with the SVCM and SHCM. For each set +of 2 pixels which need to be interpolated, a window of pixels is used that is 4 wide and 5 high - +/-1 pixel +in X and +/- 2 pixels in Y. The pixels values are taken from both the current and previous field - for +example, if we are deinterlacing the top field then lines y+2,y, and y-2 will come from the top field; while +line y+1 and y-1 will come from the bottom field. +Spatial vertical complexity measure (SVCM) is a sum of all the differences in the vertical direction for a +window around the current pixels. If we take x,y=0,0 as the left pixel of our 2x1 then: + + + SVCM = + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 33 + Where c(x,y) is the luma value at that x,y location in the current frame. Note that we are skipping by + 2 in the Y direction to ensure that the compares are only done with lines from the same field. +Spatial horizontal complexity measure (SHCM) is a sum of differences in the horizontal direction. + + + + SHCM = +The vertical edge complexity measure (VECM) is a sum of difference in the horizontal direction similar to +SHCM, but uses different pixels from the window. + + + + VECM = >>5 +Temporal Difference Measure (TDM) is a measure of differences between pairs of fields with the same +lines. It uses filtered versions of c(x,y) from the current frame and r(x,y) from the reference frame (either +the previous or next frame). +The filter used is a cross filter which uses the pixels above, below, to the right and to the left of the +needed pixel in the same field. When denoise filter is enabled, the filter input c(x,y) is a denoised pixel +only if -2<=y<=6 for dndi_topfirst=1, and -3<=Y<=5 for dndi_topfirst=0. Note that r(x,y) is a denoised pixel +regardless of y. +c’(x,y) = (2*c(x,y) +c(x-1,y) +c(x+1,y) +2*c(x,y-2) +2*c(x,y+2)) >> 3 (Done for both c(x,y) and r(x,y)) + + + + TDM = +STMM is then calculated by : + STMM = ((TDM >>tdm_shift1)<> 4) + stmm_c2) + where SCM = max(0, SVCM+SHCM-VECM). Tdm_shift1 is used to quantize the STMM result, while + Tdm_shift2 is used to set the STMM range. Tdm_shift1 can range from 4 to 6; since TDM has 13 + bits this results in between 9 and 7 bits of precision. Tdm_shift2 can range from 6 to 8, producing a + value between 17 and 13 bits, of which only 9-bits are non-zero. The divide can be implemented by + a 8-bit reciprocal table followed by an 9 -bit x 8-bit multiply by the TDM value, which finally produces + an output of 8-bits. +STMM is then smoothed with an exponential moving average with the STMM saved from the +previous field: + if (STMM > stmm_md_th) + STMM2 = (stmm_trc1 * STMM_s + (256-stmm_trc1)*STMM) / 256 + else +STMM2 = (stmm_trc2 * STMM_s + (256-stmm_trc2)*STMM) / 256 + + with state variables stmm_trc1 (typical value 64), stmm_trc2 (typical value 200), and stmm_md_th. +This process prevent sudden changes in STMM, though STMM over a certain value uses a smaller +smoothing constant (c1) which allows it to change faster. STMM2 is stored to memory to be read as +STMM_s by the next frame. +One final step is used to prevent sudden drops in STMM in the horizontal direction – taking the maximum +of the STMM on the right and left sides: + STMM3(x) = max (STMM2(x-2), STMM2(x), STMM2(x+2)) + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 34 + The resulting STMM3 will be used as a blending factor between the spatial and temporal deinterlacer. + +2.8.4.2 Spatial Deinterlacer Angle Detection +Deciding the best pixels to interpolate in the current field is the job of the spatial deinterlacer. The +simplest method would be to interpolate directly from the pixels above and below the missing pixels, but +this can look bad; edges and lines particularly look jagged with this solution. +A better solution is to detect the direction of edges in the pixel neighborhood and interpolate along the +edge direction. + + + + +Edge detection is done per 2 pixels to lower the compute needed (may change in this implementation +depending on quality). Edge detection is done by taking a window of pixels around the pixels of interest +and comparing with a window offset in the direction being tested. The more simularity between the +windows the more likely it is that the movement is in the direction of an edge. +We test 9 different directions to pick the best edge: vertical, +/-45°, +/-27°, +/-18° and +/-11 degrees. The +window offset for 45° x+/-1, likewise the offset of 27° is x+/-2, 18° is x+/-3, and 11° is x+/-5. X+4 is not used because +the gap between 18° and 11° is too small to make it worth checking. + + + + +Use x,y=0,0 for the left pixel of the pair that we want to interpolate, and xoffset is the offset described in +the above paragraph. The equation for each angle checked is: + + + +AngleCost_6x3 = + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 35 + The above picture illustrates the 45 degree angle compution – taking the sum-of-absolute differences of +the two 6x3 blocks around the 2 pixels that need an angle estimated. Each block is offset by 1 in Y and X +in opposite direction. The offset in X is larger for the other angles, of course. Angle detection requires up +to 7 pixels (offset of 5 plus 2 to get all the pixels in the 6x3) on the right and left of the output block, +requiring the input to the deinterlacer from the denoise to be 16 + 7 + 7, or 30 pixels. +Once we have all the angle values, the final decision is done by comparing them with each other. In the +following diagram N45 indicates the AngleCost_6x3 for -45°, likewise P27 is the value for +27°, etc. Th +and D are constants used to fine tune the algorithm. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 36 + Any missing arcs in the above diagram use the default edge of 90 degrees; for example if the lower left +box has P11 >= Th then the default will be used. + +2.8.4.3 Angle Robustness Check +Three special checks are made to eliminate incorrect angle detection. +Fallback Mode 1 +Moving regions with fine details can confuse the angle detection. This fallback mode will detect fine +details and fall back to 90 degrees if they are detected. + + + + +SUM_H1(x,y) = +This sum is similar to SHCM, but over a horizontal line of -2 to +3 only. + + +SUM_H2(x,y) = + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 37 + if (SUM_H1(y-1) + SUM_H1(y+1) > SUM_H2(y-1) + SUM_H2(y+1) + sdi_t1 && + SUM_H1(y-1) + SUM_H1(y+1) >= sdi_t2)Then use 90 degree +The final decision for each pixel is done using the sums from above and below the current Y. +Fallback Mode 2 +Sometimes the 6x3 angle detection window makes mistakes due to pixels on the edge of the window. +Adding a check using a 2x1 window fixes these problems: +If( AngleCost_6x3(90 degree) + (AngleCost_2x1(90 degree)<<3) < +AngleCost_6x3(best angle) + ((AngleCost_2x1(best angle) + sdi_angle2x1)<<3)) then use 90 degree +AngleCost_2x1 is the same as AngleCost_6x3 with a much smaller window: + + + +AngleCost_2x1 = +AngleCost_2x1 can be collected during the calculation of AngleCost_6x3. +Horizontal Median +One final step is used to prevent sudden angle changes – the angle detected for the pixel pair is +compared to the angle detected for the pixels to the right and left and the median of the 3 is the angle +finally used: + angle_final(x) = median3(angle(x-2), angle(x), angle(x+2)) + +2.8.4.4 Spatial Deinterlacer Interpolation +Once the best angle is picked, the interpolation is done on a per pixel basis. Both the chroma and luma +need to be interpolated (see section Chroma Up Sampler for chroma). Only 422 output is needed, so +there will be a chroma pair for each 2 lumas. The interpolation itself is very simple: take a pixel from the +line above and the line below along one of the 9 possible angles, and average the 8-bit luma and chroma +values to get the result pixel. We will do 2 lumas per clock to get enough performance. + +2.8.4.5 Chroma Up-Sampler +The DN/DI block supports 4:2:0, 4:1:1 and 4:2:2 inputs, but only outputs 4:2:2. For 4:2:0 and 4:1:1 the +chroma needs to be up-sampled to 4:2:2 before interpolation. +The 4:2:0 input has chroma at ¼ the rate of the luma; ½ in the horizontal and ½ in the vertical directions. +The output needs to be 4:2:2, where chroma is ½ the rate of luma; ½ the horizontal but the same in the +vertical direction. Then chroma can be de-interlaced in the vertical direction. For luma we are working with +16x4 blocks, so for chroma we will have 8x2 in 4:2:0 and 8x4 in 4:2:2. +The 4:2:0 to 4:2:2 conversion requires doubling the chroma in the vertical direction to match the luma: + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 38 + The chroma is doubled by a simple interpolation in both time and space. In the following equations, pixel +locations are specified as u(field, x_location, y_location). Field=n would be from the current field, n-1 is +from the previous field, and n+1 is from the next field. The Cr and Cb X and Y values are ½ the luma +values to map to the smaller area. +temporal_cr = (cr(n-1,x,y) + cr(n+1,x,y)) / 2// Simple average in time +spatial_cr = (cr(n,x,y-1) + cr(n,x,y+1)) / 2// Simple average in vertical space +if (STMM3 < stmm_min) + new_cr = temporal_cr +else if (STMM > stmm_max) + new_cr = spatial_cr +else + new_cr = ((STMM3 – stmm_min) * spatial_cr + (stmm_max - STMM3) * temporal_cr) >> stmm_shift +Note that this simple chroma interpolation is not correct, since the chroma sample position is ¼ of a pixel +different between 420 and 422. The polyphase filter in the scaler will be used to correct this inprecision by +modifying the filter coefficients in software. +For performance a single Cr and Cb has to be produce per clock in this stage to match the 2 pixel per +clock performance goal. +4:1:1 also has chroma at ¼ the rate of luma; ¼ in the horizontal direction and the same in the vertical +direction. To convert to 4:2:2 we need to double the chroma horizontally. This will be done by averaging +the chromas to the right and left to produce the new chroma. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 39 + The above diagram shows how the existing chroma values (both U and V) are averaged between C0 and +C1 to produce the new C½. C0 is the chroma asociated with lumas L0 through L3, while C1 is associated +with L4 through L7. + +2.8.4.6 Chroma Deinterlace +The next step is to do the deinterlacing. Chroma uses the output of the luma angle decision, but reduces +the number of angles. The actual spatial deinterlace algorithm is a little different for chroma, since there +are only 1 chroma per 2 lumas: some of the chromas are missing and must be filled in. + + + + +The diagram shows the chromas used in red. Only 90°, -27° and 27° are directly available. The chromas +for +/-45° are derived by a simple average of the 90° and 27° chromas. +/-18° and +/-11° both use the +chroma for +/-27°. + +2.8.4.6.1 Static Image Fallback Mode +This algorithm has a problem with static images – alternate fields use different luma angle detections and +can select different angles, causing noticable flicker. Rather than calculating a separate set of angles for +chroma, we instead will blend with STMM so that a static image will use 90 degrees. +if (STMM3 < stmm_min) + chroma_sdi = chroma90degree +else if (STMM > stmm_max) + chroma_sdi = chroma_3angle +else + chroma_sdi = (chroma90degree * (stmm_max – STMM3) + chroma_3angle * (STMM3 – stmm_min)) >> +stmm_shift + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 40 + 2.8.4.7 Temporal Deinterlacer and Final Deinterlacer Blend +The temporal deinterlacer is a simple average between the previous and next field; when deinterlacing +the 1st field of current the average will be between the 2nd field of previous and the 2nd field of current. +The interpolation between spatial and temporal: +if (STMM3 < stmm_min) + deinterlace_out = tdi; +else if (STMM3 > stmm_max) + deinterlace_out = sdi; +else + deinterlace_out = (sdi * (STMM3 – stmm_min) + tdi * (stmm_max – STMM3)) >> stmm_shift + + +2.8.4.8 Progressive Cadence Reconstruction +When the FMD for the previous frame indicates that a progressive mode is being used rather than +interlaced, the luma and chroma will be taken from adjacent fields rather than spatially interpolated. The +exact fields needed depend on state variables written to memory by a thread at the end of the previous +frame. The thread will use the FMD variances written to memory via CSunit on the flush at the end of a +frame. +Since we are deinterlacing 2 fields at a time – one from the previous frame and one from the current +frame (see section Implementation Overview) we will need a state variable which says how each one +should be put together. In each case there are only two possibilities – either the field should be put +together with the matching field in the same frame or it should be put together with the adjacent field in +the other frame. +If we are deinterlacing the 2nd field from frame N and the 1st field from frame N+1, then the FMD decision +(which is made on frame boundaries) will be from frame N-1. +Chroma is reconstructed the same as luma – only the first step of doubling chroma is done in the chroma +upsampling block for the two needed fields. + +2.8.4.9 Motion Search +Motion will be estimated independently for each horizontal pair of pixels in the 16x4 block. The area +around each pixel pair will be compared to areas in adjacent fields with different X/Y offsets. 16 different +offsets, or motion vectors, will be examined in this order: +Y= -2, X = -1, 0, 1 +Y = 0, X = -6, -5, -4, -3, -2, 2, 3, 4, 5, 6 +Y = 2, X = -1, 0, 1 +The area to be compared around the pixel pair is a 6 wide by 5 high window - 2 pixels on right and left +and 2 lines above and below. The lines above and below are from both fields, so a total of 3 lines from +the same field and 2 lines from the complement field are compared to lines in 2 fields from an adjacent +frame. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 41 + The motion estimation equation for a pixel pair is: + + + + +Mx, My is the motion vector offset being tested, and x,y is the location of the leftmost pixel of the pair. The +motion vector with the smallest SAD is kept as the best motion estimate; if two motion vectors have the +same SAD then the last one tested will be kept. + +2.8.4.10 Robustness Checks +The motion estimate output goes through 2 checks to make sure it is not an aberration – a smoothness +check and a consistency check. + +2.8.4.10.1 Consistency Check +The consistency check is done per pixel and makes sure that the pixels we are interpolating for MC have +a lower delta than the ones that would be interpolated for spatial DI: + + + + +Here Edge is the delta found by SDI which corresponds to the best angle. MC_pixel_consistency_TH +(U6)is a state parameter. +PDI_cur is defined as: (same definition as in the motion compensation section) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 42 + 2.8.4.10.2 Smoothness Check +The smoothness check compares the motion vector found for neighboring pixel pairs. The neighbors are +different for different locations to make sure it stays within the local 4x4. Each pixel pair has 3 sets of +comparison with neighbor pixel pair within the 4 by 4: 2 sets of X/Y comparisons for the vertical direction +and one set of X/Y comparisons for the horizontal direction. +For lines 1 and 2 in the 16x4: + + + + +Where smooth_mv_th(U2) is a state parameter. +This equation ensures that the pixel pair 1 and 2 lines below have motion vector X and Y components +(MVx & MVy) that are within a threshold of the best motion vector for the current pixel pair. The compares +with y+1 use “+” rather than “-“ since they are comparing motion vectors in the opposite field, which have +motion vectors pointing in the opposite direction, since they are using the current field as their reference. +For example, if the current pixel has a motion vector of (4,2), the motion vector of x,y+1 would be the +same if it is (-4,-2). +For lines 3 and 4 in the 16x4: + + + + +For pixel pairs with the first pixel location x%4 == 0 (low X in the 4x4): + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 43 + For pixel pairs with the first pixel location x%4 != 0 (high X in 4x4): + + + + +When all 3 comparisons pass the threshold, the smoothness check is passed. + +2.8.4.11 Motion Comp +The MCDI output is an average done per pixel on pixels chosen from adjacent field. +There are 4 different equations depending on the motion vector (Mx, My): + +If (Mx%2 ==0) && (My == 0) then +If (Mx%2 ==1) && (My == 0) then + + + + +If (Mx%2==0) && abs(My) == 2 then + + + +If (Mx%2==1) & abs(My) == 2 then + + + + + For all these equations, if more vareties of My are used than -2,0,2 then we need to use (My/2)%2==0) +instead of My==0, and (My/2)%2==1 instead of abs(My)==2. + +2.8.4.12 Merge with TDI & SDI +The MADI equation used in Gen6 was: +if (STMM3 < stmm_min) +deinterlace_out = tdi; +else if (STMM3 > stmm_max) + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 44 + deinterlace_out = sdi; +Else +deinterlace_out = ((STMM3 – stmm_min) * sdi + (stmm_max - STMM3) * tdi) >> stmm_shift +Where STMM3 is a measure of the complexity of the scene and how much motion is in it. +The equation with MCDI is: +if (STMM3 < stmm_min) + Deinterlace_out = tdi; +else if (STMM3 > stmm_max) + deinterlace_out = DItemp; +else +deinterlace_out = ((STMM3 – stmm_min) * DItemp + (stmm_max - STMM3) * tdi) >> stmm_shift +Where DItemp is defined below: +Content Adaptive Thresholding: +We denote the best_ME_SAD as the minimal SAD value for the MV candidates. Best_ME_SAD and +Best_SAD_Angle_cost are measured based on the block of pixels. The new control equation with MCDI +is calculated per pixel: +If ((best_ME_SAD <= CAT_TH1) +If (Consistency check is passed && Smoothness check is passed) + DItemp = MCDI; +Else + DItemp = sdi; +Else if (CAT_TH1 SCM_B) +CAT_TH2 = SAD_THB; + +Else +CAT_TH2 = SCM / CAT_slope; + +Where CAT_slope (U4: default value 10). SAD_THA (U4, default 5) and SAD_THB (U4, default 10) are +state parameters, and SCM_A and SCM_B are derived parameters: + SCM_A = CAT_slope * SAD_THA;// 4-bit * 4-bit to produce 8-bit value + SCM_B = CAT_slope * SAD_THB;// 4-bit * 4-bit to produce 8-bit value + + +2.8.5 Field Motion Detector +The Field Motion Detector is generated in either the EU or in the driver with a set of differences gathered +across entire fields. It is used to detect when a non-interlaced source like a film has been converted to +interlaced video – in this case there will be pairs of fields which can be put back together to make frames +rather than interpolating. The variances for the block are sent to the VSCunit to be summed across the +entire frame. The results are available in MMIO registers. + +2.8.5.1 Simple Differences +The first set of variances are simply a sum of absolute pixel differences. The equations are done for every +pixel with an even y coordinate: +variance[0] += Diff_cTpT = (c(x,y) – p(x,y)) ^ 2; – difference between pixels from the top fields of the +current and previous frame. +variance[1] += Diff_cBpB = (c(x,y+1) – p(x,y+1)) ^ 2; – difference between pixels from the bottom fields +of the current and previous frame. +variance[2] += Diff_cTcB = (c(x,y) – c(x,y+1)) ^ 2; – difference between pixels from the top field and +bottom field in the current frame. +variance[3] += Diff_cTpB = (c(x,y) – p(x,y+1)) ^ 2; – difference between pixels from the top field of the +current frame and bottom field of previous frame. +variance[4] += Diff_cBpT = (c(x,y+1) – p(x,y)) ^ 2; – difference between pixels from the bottom field of +the current frame and top field of previous frame. +The variances summed for each 16x4 block are divided by 16 before adding them to the sum for the +frame to make sure the frame-level sum fits in a 32-bit register. + +2.8.5.2 Counter Variances +The rest of the variances are counters for variance conditions as described in the following code: +// Same field difference of the current frame +diff_cTcT = (c(x,y) – c(x,y+2)) ^ 2; + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 46 + diff_cBcB = (c(x,y-1) – c(x,y+1)) ^ 2; +// Same field difference of the previous frame +diff_pTpT = (p(x,y) – p(x,y+2)) ^ 2; +diff_pBpB = (p(x,y-1) – p(x,y+1)) ^ 2; +// Same field vertical smoothness of the current frame +diff_cT = ABS(c(x,y) – c(x,y-2)) + ABS(c(x,y) – c(x,y+2)) – ABS(c(x,y-2) + c(x,y+2)); +diff_cB = ABS( c(x,y+1) – c(x,y-1) ) + ABS( c(x,y+1) – c(x,y+3) ) – +ABS( c(x,y-1) + c(x,y+3) ); +if( diff_cTpT + diff_cBpB > fmd_tdiff ) {// if moving pixels, + + + // Fine tears for cadence detection except 2-2 detection + if( diff_cTcB > diff_cTcT + diff_cBcB)variance[5]++; + elsevariance[6]++; + // Find tears for 2-2 cadence detection + if( diff_cT < fmd_vdiff1 && diff_cB < fmd_vdiff1) {// if fields are vertically +smooth, +variance[7]++;// total moving pixels +// Find tears. (1st condition is to exclude very small variations) +if(diff_cTcB >=fmd_vdiff2 && diff_cTcB > diff_cTcT + diff_cBcB) TEAR1(x,y) = 1 +if(diff_cTpB >=fmd_vdiff2 && diff_cTpB > diff_cTcT + diff_pBpB) TEAR_2(x,y) = 1 +if(diff_cBpT>=fmd_vdiff2 && diff_cBpT > diff_pTpT + diff_cBcB) TEAR_3(x,y) = 1 + } +} + + +2.8.5.3 Tear Variances +The all 3 TEAR_N variables are compared to neighbors to eliminate strays: +if(TEAR_N(x-1,y) == 0 && + TEAR_N(x+1,y) == 0 && + TEAR_N(x,y-2) == 0 && + TEAR_N(x,y+2) == 0)TEAR_N(x,y) = 0;where N=1,2,3. +variance[8] = sum of TEAR1(x,y) +variance[9] = sum of TEAR_2(x,y) +variance[10] = sum of TEAR_3(x,y) +if (variance[8] > variance[9] && variance[8] > variance[10]) + variance[7] = variance[8] = variance[9] = variance[10] = 0 +if (variance[8] < fmd_thr_tear) variance[8] = 0 +if (variance[9] < fmd_thr_tear) variance[9] = 0 +if (variance[10] < fmd_thr_tear) variance[10] = 0 +The variances are summed for each block across the frame. The accumulators may require 24-bit adders +if the differences are 8-bits and there can be 128 (horizontally) * 256 (vertically) of them. The sums are +written to memory at the end of the frame. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 47 + Two sets of FMD variances are needed to support 2 simultaneous streams. The streams are +distinguished by the dndi_stream_id state variable in the DI state. +A-Stepping Erratum: TEAR_N compute doesn’t follow the equation above. Two signals were missing, +thus, it is incorrectly calculated as the following. Without the added protection of the N=-2 & N=4 +collection of feature, the robustness of 2:2 detection suffers. +if(TEAR_N(x-1,y) == 0 && + TEAR_N(x+1,y) == 0 && )TEAR_N(x,y) = 0;where N=1,2,3. + + +2.8.6 Implementation Overview + +2.8.6.1 Input and Output Frames +Two frames are needed to do deinterlacing, but for any two frames, two fields can be deinterlaced, +doubling the output for the same input bandwidth. This also allows the denoise filter to only filter a frame +once. + + + + +The above picture shows that two frames are read in, called current and previous. The two fields of the +next frame are denoised using adjacent fields. The 2nd field of previous can be deinterlaced using current +as the reference, and the 1st field of current can be deinterlaced using previous as reference. +Since we are producing 2 16x4 outputs, and the performance goal is to output 2 pixels per clock, we have +64 clocks to run 2 denoise filters and 2 deinterlacers. +The fields are referred to as 1st and 2nd because either the top or bottom field can be the first in the +sequence depending on a state variable. + +2.8.6.2 Statistics Surface Memory Format +The statistics memory page is used to store both STMM and Denoise history. The STMM and Denoise +history are stored in separate areas addressed by a single base address pointer: + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 48 + The STMM for any pixel pair is addressed by: + STMM_X = pixelX / 2 + STMM_Y = pixelY +The Denoise History for any 4x4 block is addressed by + DH_X = Pitch/2 + pixelX/4 + DH_Y = pixelY/4 +Where the pixelX/Y comes from the address of the left pixel for STMM and the upper-left pixel for the +Denoise History. The Pitch is from the surface state. +The read and write surfaces for each frame must be separate, since any individual block will not know if +the neighbor blocks have been updated yet. This can be implemented as a ping-pong buffer pair with the +write surface for each frame becoming the read surface for the next. + +2.8.6.3 First Frame Special Case +The first frame in the sequence is a special case for both denoise and deinterlace. Only data from the +current frame address is read, the previous frame, clean previous, statistics and control addresses are +ignored. Behavior for each function is as follows: + 1. Denoise – The denoise filter needs to use the spatial filter, since there is no previous frame + from which to do a temporal filter. + a. The Denoise Motion History is not read. + b. The blend between the temporal and spatial is forced to 100% spatial. + c. The Denoise Motion History output values are written to 0. + 1. BNE – The Block Noise Estimate only uses current frame values and so works normally. + 2. Deinterlacer – Only the 1st field of the current frame frame is deinterlaced in this case – the 2nd + of previous does not exist. + a. The spatial deinterlacer is used to produce the output. + b. The STMM input values are not read. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 49 + c. The STMM output values are written as a the maximum 255 value so that the next + frame is correctly told that spatial deinterlacing was used in this frame. + 3. FMD – variances between the top and bottom of the current field should be output correctly. + Variances that read from the previous field should indicate a maximum difference. + 4. Progressive Cadence Reconstruction – the FMD input is not read, so always assume + interlaced. + + +2.9 Adaptive Video Scaler +The adaptive video scaler consists of a pair of filters. The sharp filter is an 8x8 and the smooth filter is +bilinear. The results of the two filters are alpha blended together using an alpha factor determined +separately from an algorithm that examines the pixel values in the each vector. +There are a total of four different coefficient tables with two in each direction. For both directions is it +possible to use either of the two tables that are assigned to it or use both at once with one table for the Y +and the other table for the U/V. The coefficients are programmable by software and loaded via a new +command streamer instruction. The coefficients are considered to be nonpipelined state, with a full +pipeline flush being required before a new set of coefficients is loaded. + + + + +The above diagram shows two pixels (red and green) mapped onto a texture map, with the texel centers +blue. The red/green boxes around the pixels indicate the area where the pixel would choose the same +8x8 footprint for its filter, while the large transparent box indicates the footprint for each pixel. +The u/v addresses for each pixel (in texel space) are as follows: + red pixel: u=3.3, v=3.3 (betau=0.3, betav=0.3) + green pixel: u=4.3, v=4.7 (betau=0.3, betav=0.7) +The integer u/v address of the upper left pixel of the footprint is a function of the pixel u/v address as +follows: + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 50 + u(UL) = floor(u(pix)) – 3 + v(UL) = floor(v(pix)) – 3 +When the 8x8 filter is selected, the 8x8 texel block surrounding the pixel sample point is selected. The +blend factors "beta" (horizontal and vertical) are determined by the relative distance between the pixel +center and the nearest 4 texels (2x2). The betas are first truncated to 5 bits (i). +The beta value is used to look up two sets of 8 coefficients, one set of 8 for horizontal (called K h0..7), and +one set of 8 for vertical (called Kv0..7). + + +2.9.1 Filtering Operations +There are two separate filters, sharp and smooth, which are blended in an adaptive manner. + +2.9.1.1 Sharp +The following formula is used to compute the filtered texture color for the sharp filter: +R0 = T00*Kh0 + T01*Kh1 + T02*Kh2 + T03*Kh3 + T04*Kh4 + T05*Kh5 + T06*Kh6 + T07*Kh7 +R1 = T10*Kh0 + T11*Kh1 + T12*Kh2 + T13*Kh3 + T14*Kh4 + T15*Kh5 + T16*Kh6 + T17*Kh7 +R2 = T20*Kh0 + T21*Kh1 + T22*Kh2 + T23*Kh3 + T24*Kh4 + T25*Kh5 + T26*Kh6 + T27*Kh7 +R3 = T30*Kh0 + T31*Kh1 + T32*Kh2 + T33*Kh3 + T34*Kh4 + T35*Kh5 + T36*Kh6 + T37*Kh7 +R4 = T40*Kh0 + T41*Kh1 + T42*Kh2 + T43*Kh3 + T44*Kh4 + T45*Kh5 + T46*Kh6 + T47*Kh7 +R5 = T50*Kh0 + T51*Kh1 + T52*Kh2 + T53*Kh3 + T54*Kh4 + T55*Kh5 + T56*Kh6 + T57*Kh7 +R6 = T60*Kh0 + T61*Kh1 + T62*Kh2 + T63*Kh3 + T64*Kh4 + T65*Kh5 + T66*Kh6 + T67*Kh7 +R7 = T70*Kh0 + T71*Kh1 + T72*Kh2 + T73*Kh3 + T74*Kh4 + T75*Kh5 + T76*Kh6 + T77*Kh7 +F’ = R0*Kv0 + R1*Kv1 + R2*Kv2 + R3*Kv3 + R4*Kv4 + R5*Kv5 + R6*Kv6 + R7*Kv7 +F_sharp = Clamp F’ to [0.0, 1.0) +where: + +  Trc is the texel color in row r ([0..3]) and column c ([0..3]) of the 8x8 array of neighboring texel colors +  F_sharp is the final output color of the sharp filter. + +2.9.1.2 Smooth +The following formula is used to compute the filtered texture color for the smooth filter: +F_smooth = (T33 * (1-betaU) + T34 * betaU) * (1-betav) + (T43 * (1-betaU) + T44 * betaU) * betav + +2.9.1.3 Adaptive Filtering +The adaptive filter only supports RGB or YUV packed formats. For YUV formats, the alpha value is +determined only by the Y channel (green), with this alpha value being applied to all three channels. For +the RGB formats the alpha value is determined based on an average of all three channels with G having +double the weight as the other channels. +Each horizontal or vertical filter has 8 texels input which feeds into an eight tap filter. On the center two +there is a linear blend using the betaV. Then using the Y channel an adaptive part weight is calculated + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 51 + and the two filters are alpha blended. The adaptive part calculated on the Y channel is used on all three +channels. Only the 8 MSBs are used in these calculations. +The adaptive part is done to classify a pixel as prone to ringing or not. This is done by analyzing the 8 Y +samples from the interpolation window (Wy0… Wy7). + + +2.10 Image Enhancement Filter and Video Signal Analysis +The IEF module takes in the YUV 444 color space with 10 bit components. +The IEF can be configured to operate either detail filtering or smooth filtering. A 3x3 and a 5x5 +programmable filter are involved to achieve detail-enhanced or smooth effect. +VSA – Video Signal Analysis – analyzes the local Y environment of each pixel and outputs several values +that describe its nature (smooth, detailed, sharpening). Those values will be used by the IEF to decide +how the filter should be applied at each pixel location. +IEF – Image Enhancement Filter – The operations this filter performs are detail filter, smoothing and +sharpening on the Y component, according to the VSA outputs. +The IEF throughput is 2 pixels per clock. + +Block Diagram + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 52 + 2.10.1 Detail Filter Algorithm + +2.10.1.1 VSA for Detail Filter +VSA in IEF aims to analyze the local property of the content and it is achieved with the usage of Sobel +edge detection. For example, below detection kernel can be used to analyze 3x3 neighborhoods. + + + + +Statistics from Sobel filtering outputs are taken for setting different weights to the detail added. + + +EM(x) = |NH9(x) * E_h| + |NH9(x) * E_v| // where the input is 10 bits, EM is 6 bits (CLIP( (|NH9(x) * E_h| + +|NH9(x) * E_v|+4) >> 3 , 0 ,63)) +If (EM(x) > Strong_Edge_Threshold) local_adjust = Strong_Edge_Weight // local_adjust is 3bits +Else if (EM(x) > Weak_Edge_Threshold) local_adjust = Regular_Weight +Else local_adjust = Non_Edge_Weight +The Strong_Edge_Threshold, Weak_Edge_Threshold, Strong_Edge_Weight, Non_Edge_Weight +and Regular_Weight are the pipelined state variables to be specified by driver. +Strong_Edge_Threshold & Weak_Edge_Threshold are 6-bit length variables. + +2.10.1.2 Detail IEF +A programmable 3x3 and a 5x5 filter are provided to extract the detail information of the image. The detail +extracted is the combination of the convolution results from the 3x3 and the 5x5 filter. The amount of +detail added upon each pixel is determined by the weighting obtained from the VSA. + + +2.10.2 Skin-Tone Tuned IEF +The operation of IEF can be enhanced with the skin tone detection (STD). The STD unit detects the skin- +tone like colors and passes a grade of skin tone color to the IEF. The skin tone operation on the YUV +space, and the detected skin tone score will be recorded as a 5-bit number as per-pixel basis. The IEF +modifies the pixel value by adjusting the delta signal according to the detected skin tone score. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 53 + 2.10.2.1 Skin Tone Detection + +2.10.2.1.1 STD - Detection in the (U,V) sub-space +The STD operates on digital images in the YUV color space. In these spaces, the skin-tone region is +represented by the ellipse in the (U,V) subspace (chroma components), by a trapeze membership +function in the Y direction (luma component) and by a piece-wise linear classifier in the (V,Y) subspace. +The detection in each sub-space outputs a likelihood score (i.e., det_UV, det_Y, and det_VY) +representing how likely a pixel being a skin-tone pixel in that sub-space. Each score is represented with 5 +bits, and the final skin-tone detection score SkinToneFactor is taken as the minimum of (det_UV, det_Y, +det_VY). + + +2.10.3 Video Analytics Functions – Functional Description + +2.10.3.1 Convolve +The CONVOLVE instruction performs a convolution on the source matrix, using the specified kernel, and +stores the result in the destination matrix. The source input can either be 8bit UINT or 16bit UINT/SINT. + +The floating point coefficient (i.e., each element within mentioned in Sec. 1.3.1) could be scaled up by +before being loaded as the fixed point kernel for the convolve. The final result would need to be scaled +down by the same amount before clamping the result to the fixed point 16 bit format. This scaling is +helpful in getting more precision and hence near to accurate result of the floating point math. The scaling +supported is only in powers of 2, and this could be found as follows: +Assuming all coefficients will be less than the value 8. In case it is greater they would need to be scaled +down such that the max value is lesser than 8 before doing the following calculation. The scale up of the +resultant convolve value then would need to be done in the EUs appropriately. In case all coefficients are + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 54 + less than 1/2^7, then coefficients can be upscaled by driver and later the result from the convolve +operation will be down scaled by EU. + + +If((MAX(ABS(C[i])) <= 8) && (MAX(ABS(C[i])) >= 1/2^7) +Scale = Max_power_of_2(8/MAX(ABS(C[i]))) +C[i] = 2^(scale) * C[i] +Where the following are the functions: +MAX – Is the max of all the coefficients +Max_power_of_2 – Finds the Max power of 2 lower or equal to the input value. The Max_power_of_2 +output cannot be greater than 512. + + +CONVOLVE(src, kernel, scale, dest) + Src - 8bit UINT/ 16bit SINT/ 16bit UINT + Kernel - 16bit S3.12 + Dest – 16bit SINT + Scale – Range 0 to 10. The final result is shifted by this amount. + + +Pseudo Code: +// Example for kernel_widthxkernel_height below: +CONVOLVE src, kernel, dest +{ + (( + real tmp = 0; + for (m = 0; m < kernel_width; m++) + { + for (n = 0; n < kernel_height; n++) + { + int ii = i + m – ((kernel_width-1)>>1); + int jj = j + n – ((kernel_height-1)>>1); + + + if (ii < 0) { + if(clamp) ii = 0; + else ii = -ii - 1; // mirror + } + else if (ii > src.width - 1) { + if(clamp) ii = src.width – 1; + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 55 + else ii = 2*src.width - ii - 1; //mirror + } + if (jj < 0) { + if(clamp) jj = 0; + else jj = -jj - 1; // mirror + } + else if (jj > src.height - 1) { + if(clamp) jj = src.height – 1; + else jj = 2*src.height - jj - 1; //mirror + } + // handle matrix sizes smaller than the kernel, use null value in place of src[ii,jj] + if (ii < 0 || ii > src.width - 1 || jj < 0 || jj > src.height - 1) + val = 0; + else + val = src[jj,ii]; + + + //Note: that the driver does the kernel flipping already and hardware does the + following operation: + tmp += val * kernel[n,m]; + } + } + tmp = tmp <<1; + tmp = INT(tmp) >> scale + tmp = (tmp + 1)>>1; + dest[i,j] = Clamp(tmp, -2^16, 2^16-1); + )) +} + + +Even though the convolve is suppose to do kernel flipping, the kernel is actually flipped by driver, and the +hardware does not do any kernel flipping and operates using the kernel directly. Also the kernel is always +starting from (0,0) and depending on the kernel width and height the appropriate coefficients are picked +from the kernel coefficient stored. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 56 + 2.11 Mirror pixel at boundary edges for Media (sample_8x8 + messages) +Presently we support only Clamp mode for sample_8x8 messages. This is to extend mirror mode as +supported for 3D messages for sample_8x8 messages. The restriction here would be that the surface +width is in multiples of DWords in native L1 storage format. The following are the surfaces which would +need to be covered here: + 1. 32bpp format in Memory and L1 (for AVS only and sample_unorm): + a. 8: R10G10B10A2_UNORM + b. 9: R8G8B8A8_UNORM + c. 13: A8Y8U8V8_UNORM + d. 14: B8G8R8A8_UNORM + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 57 + 2. 16bpp format in Memory and 16bpp in L1 (for AVS only and sample_unorm): + a. 0: YCRCB_NORMAL + b. 1: YCRCB_SWAPUVY + c. 2: YCRCB_SWAPUV + d. 3: YCRCB_SWAPY + e. 10: R8B8_UNORM (CrCb) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 58 + 3. 8bpp format in Memory and 16bpp in L1 (for AVS only): +The pixel when read out from L1 would be replicated as what is shown above in the diagram for 16bpp. + a. 4: PLANAR_420_8 + b. 11: R8_UNORM (Cr/Cb) + c. 12:Y8_UNORM + 4. 64bpp format in Memory and L1 (for AVS only): + 15: R16G16B16A16 + This would be similar to the 32bpp except each pixel is 64bpp instead. + 5. 8bpp format in Memory and L1 (for VA only): + a. 5: PLANAR_Y8_UNORM + Each cell in the below figure is 8bits. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 59 + 6. 16bpp format in Memory and L1 (for VA only): +Same as the above except each cell is 16bpp. + a. 7:PLANAR_Y16_UNORM + b. 6 : PLANAR_Y16_SNORM + 7. 1bpp format (Boolean) in Memory and 32bpp in L1(for VA only) : +Will not support Mirror on this surface. Clamp will still happen on vertical direction. Clamp on horizontal +direction will not be taken care of in sampler for 1bpp format, but will be done in AVS unit. + a. 16: PLANAR_Y32_UNORM + + +2.11.1 Restriction when Mirror mode is enabled for Sample_8x8 + messages +When Function=AVS, ChromaKey is not supported with Mirror mode. In case ChromaKey needs to be +enabled, then the Address control needs to be Clamp mode only. + +2.11.1.1 For AVS +For AVS scaling, the following are the restrictions on the input image size: + Image Width > MAX((19*deltaU_nn + 139*ddu_nn + 7), 32) + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 60 + Image Height > MAX((19*deltaV_nn + 139*ddv_nn + 7), 32) +The non-normalized input co-ordinate should be in the following range: + -width < (U_nn+2*deltaU_nn+3*ddu_nn) < (2*width – U – 17*deltaU_nn – 136*ddu_nn – 7) + -height < (V_nn+2*deltaV_nn+3*ddv_nn) < (2*height – 17*deltaV_nn – 136*ddv_nn – 7) + Where + U_nn = U_normaized * width + V_nn = V_normaized * height + deltaU_nn = deltaU_normaized * width + deltaV_nn = deltaV_normaized * height + ddU_nn = ddU_normaized * width + ddV_nn = ddV_normaized * height + +2.11.1.2 For VA +For VA message (other than AVS scaling mode) the restriction is that the minimum input image size +should be 32x32. The normalized input co-ordinate should not be in the range of -1 to 2 not inclusive. + + +2.12 State + +2.12.1 BINDING_TABLE_STATE + + BINDING_TABLE_STATE + +Default Value: 0x00000000 +The binding table binds surfaces to logical resource indices used by shaders and other compute engine kernels. It is +stored as an array of up to 256 elements, each of which contains one dword as defined here. The start of each +element is spaced one dword apart. The first element of the binding table is aligned to a 32-byte boundary. + DWord Bit Description +0 31:5 Surface State Pointer + Format: SurfaceStateOffset[31:5] + This 32-byte aligned address points to a surface state block. This pointer is relative to the Surface + State Base Address. + + 4:0 Reserved + Format: MBZ + + + + +2.12.2 SURFACE_STATE +The surface state is stored as individual elements, each with its own pointer in the binding table. Each +surface state element is aligned to a 32-byte boundary. +Surface state defines the state needed for the following objects: + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 61 +  texture maps (1D, 2D, 3D, cube) read by the sampling engine +  buffers read by the sampling engine +  constant buffers read by the data cache via the data port +  render targets read/written by the render cache via the data port +  streamed vertex buffer output written by the render cache via the data port +  media surfaces read from the texture cache or render cache via the data port +  media surfaces written to the render cache via the data port + +2.12.2.1 SURFACE_STATE for most messages + + RENDER_SURFACE_STATE + +Exists If: (MessageType != 'Deinterlace') && (MessageType != 'Sample_8x8') +Default 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x00000000 +This is the normal surface state used by all messages that use SURFACE_STATE except deinterlace and +sample_8x8. + DWord Bit Description +0 31:29 Surface Type + Project: All + Format: U3 enumerated type + + + This field defines the type of the surface. + Value Name Description Project + 0h SURFTYPE_1D Defines a 1-dimensional map or array of maps All + 1h SURFTYPE_2D Defines a 2-dimensional map or array of maps. All + 2h SURFTYPE_3D Defines a 3-dimensional (volumetric) map. All + 3h SURFTYPE_CUBE Defines a cube map or array of cube maps. All + 4h SURFTYPE_BUFFER Defines an element in a buffer. All + 5h SURFTYPE_STRBUF Defines a structured buffer surface. All + 6h Reserved All + 7h SURFTYPE_NULL Defines a null surface. All + + + Programming Notes + A null surface is used in instances where an actual surface is not bound. When a write + message is generated to a null surface, no actual surface is written to. When a read message + (including any sampling engine message) is generated to a null surface, the result is all zeros. + Note that a null surface type is allowed to be used with all messages, even if it is not + specificially indicated as supported. All of the remaining fields in surface state are ignored for + null surfaces, with the following exceptions: Width, Height, Depth, LOD, and Render Target + View Extent fields must match the depth buffer’s corresponding state for all render target + surfaces, including null.All sampling engine and data port messages support null surfaces with + the above behavior, even if not mentioned as specifically supported, except for the following: + Data Port Media Block Read/Write messages. The Surface Type of a surface used as a render + target (accessed via the Data Port’s Render Target Write message) must be the same as the + Surface Type of all other render targets and of the depth buffer (defined in + 3DSTATE_DEPTH_BUFFER), unless either the depth buffer or render targets are + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 62 + RENDER_SURFACE_STATE + SURFTYPE_NULL. + 28 Surface Array + Project: All + Format: Enable + + + This field, if enabled, indicates that the surface is an array. + If this field is enabled, the Surface Type must be SURFTYPE_1D, SURFTYPE_2D, or + SURFTYPE_CUBE. If this field is disabled and Surface Type is SURFTYPE_1D, + SURFTYPE_2D, or SURFTYPE_CUBE, the Depth field must be set to zero. + 27 Reserved + Project: All + Format: MBZ + 26:18 Surface Format + Project: All + Format: SURFACE_FORMAT + Specifies the format of the surface or element within this surface. Refer to the table in section + 1.12.4.1.2 for the formats supported and their encodings. + Programming Notes + YUV (YCRCB) surfaces used as render targets can only be rendered to using + 3DPRIM_RECTLIST with even X coordinates on all of its vertices, and the pixel shader cannot + kill pixels. If Number of Multisamples is set to a value other than MULTISAMPLECOUNT_1, + this field cannot be set to the following formats: any format with greater than 64 bits per + element, if Number of Multisamples is MULTISAMPLECOUNT_8, any compressed texture + format (BC*), and any YCRCB* format. + This field cannot be a YUV (YCRCB*) format if the Surface Type is SURFTYPE_BUFFER or + SURFTYPE_STRBUF. + 17:16 Surface Vertical Alignment + Format: U2 enumerated type + + + + + Description Project + For Sampling Engine Uncompressed and Render Target Surfaces: This field specifies + the vertical alignment requirement for the surface. Refer to the “Memory Data Formats” + chapter for details on how this field changes the layout of the surface in memory. This + field applies to surface formats other than compressed formats. For other surfaces this + field is ignored. + A value of 1 is not supported for formats YCRCB_NORMAL (0x182), + YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), or YCRCB_SWAPY (0x190). + + + Value Name Description + 2h-3h Reserved Reserved + + + Programming Notes Project + This field is intended to be set to VALIGN_4 if the surface was rendered as a depth + buffer, for a + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 63 + RENDER_SURFACE_STATE + multisampled (4x) render target, or for a multisampled (8x) render target, since these + surfaces support only alignment of 4. + Use of VALIGN_4 for other surfaces is supported, but uses more memory. + This field must be set to VALIGN_4 for all tiled Y Render Target surfaces. + Value of 1 is not supported for format YCRCB_NORMAL (0x182), + YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY (0x190) + If Number of Multisamples is not MULTISAMPLECOUNT_1, this field must be set to + VALIGN_4. + + + Errata Description Project + VALIGN_4 is not supported for surface format R32G32B32_FLOAT. + 15 Surface Horizontal Alignment + Project: All + Format: U2 enumerated type + + + + + U2 enumerated type + For Sampling Engine Uncompressed and Render Target Surfaces: This field specifies the + horizontal alignment requirement for the surface. Refer to the “Memory Data Formats” chapter + for details on how this field changes the layout of the surface in memory. This field applies to + surface formats other than compressed formats. For other surfaces, this field is ignored. + + + Value Name Description Project + 0h HALIGN_4 Horizontal alignment factor j = 4 All + 1h HALIGN_8 Horizontal alignment factor j = 8 All + + + Programming Notes + This field is intended to be set to HALIGN_8 only if the surface was rendered as a depth buffer + with Z16 format or a stencil buffer, since these surfaces support only alignment of 8. Use of + HALIGN_8 for other surfaces is supported, but uses more memory. + This field must be set to HALIGN_4 if the Surface Format is BC*. + This field must be set to HALIGN_8 if the Surface Format is FXT1. + 14 Tiled Surface + Project: All + Format: U1 enumerated type + + + This field specifies whether the surface is tiled. + Value Name Description Project + 0h FALSE Linear surface All + 1h TRUE Tiled surface All + + + Programming Notes + Linear surfaces can be mapped to Main Memory (uncached) or System Memory (cacheable, + snooped). Tiled surfaces can only be mapped to Main Memory. The corresponding cache(s) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 64 + RENDER_SURFACE_STATE + must be invalidated before a previously accessed surface is accessed again with an altered + state of this bit. If Surface Type is SURFTYPE_BUFFER, this field must be FALSE (because + buffers are supported only in linear memory). If Surface Type is SURFTYPE_NULL, this field + must be TRUE. + 13 Tile Walk + Project: All + Format: U2 enumerated type + + + This field specifies the type of memory tiling (XMajor or YMajor) used to tile this surface. See + Memory Interface Functions for details on memory tiling and restrictions. + Value Name Description Project + 0b TILEWALK_XMAJOR X major tiling. All + 1b TILEWALK_YMAJOR Y major tiling. All + + + Programming Notes + Refer to Memory Data Formats for restrictions on TileWalk direction for the various buffer + types. (Of particular interest is the fact that YMAJOR tiling is not supported for display/overlay + buffers). The corresponding caches must be invalidated before a previously accessed surface + is accessed again with an altered state of this bit.This field is ignored when the surface is + linear. + + + Errata Description Project + Set Tile Walk to TILEWALK_XMAJOR if Tiled Surface is False. + 12 Vertical Line Stride + Project: All + Format: U1 in lines to skip between logically adjacent lines + + + + For 2D non-array surfaces accessed via the Sampling Engine or Data Port: Specifies the + number of lines (0 or 1) to skip between logically adjacent lines and supports interleaved + (field) surfaces as textures. + + For other surfaces, Vertical Line Stride must be zero. + Programming Notes + This bit must not be set if the surface format is a compressed type (BCn*). + If this bit is set on a sampling engine surface, the mip mode filter must be set to + MIPFILTER_NONE. + 11 Vertical Line Stride Offset + Project: All + Format: U1 in lines of initial offset (when Vertical Line Stride == 1) + + + + For 2D non-array Surfaces accessed via the Sampling Engine or Data Port: Specifies the + offset of the initial line from the beginning of the buffer. Ignored when Vertical Line Stride is 0. + + For other surfaces, Vertical Line Stride Offset must be zero. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 65 + RENDER_SURFACE_STATE + + 10 Surface Array Spacing + Project: All + Format: U1 enumerated type + + + For 1D Array, 2D Array, Cube, and 2D Multisampled Surfaces: This field specifies whether + space is reserved between array slices for additional LODs beyond LOD 0. Refer to the + “Memory Data Formats” chapter for details on how this field changes the QPitch equation used + to determine spacing between array slices in memory. For other surfaces, this field is ignored. + Value Name Description Project + 0h ARYSPC_FULL Memory space between array slices is reserved for all possible All + LOD’s. + 1h ARYSPC_LOD0 Memory space is optimized for surfaces which contain only LOD All + 0. + + + Programming Notes + If Multisampled Surface Storage Format is MSFMT_MSS and Number of Multisamples is not + MULTISAMPLECOUNT_1, this field must be set to ARYSPC_LOD0. + 9 Reserved + Project: All + Format: MBZ + 8 Render Cache Read Write Mode + Project: All + Format: U1 enumerated type + + + For Surfaces accessed via the Data Port to Render Cache: This field specifies the way Render + Cache treats a write request. If clear, Render Cache allocates a write-only cache line for a write + miss. If set, Render Cache allocates a read-write cache line for a write miss. For Surfaces + accessed via the Sampling Engine or Data Port to Texture Cache or Data Cache: This field is + reserved and MBZ. + Value Name Description Project + 0h Allocating write-only cache for a write miss All + 1h Allocating read-write cache for a write miss All + + + Programming Notes + This field is provided for performance optimization for Render Cache read/write accesses (from + EU’s point of view). + 7:6 Media Boundary Pixel Mode + Project: All + Format: U2 enumerated type + + + For 2D Non-Array Surfaces accessed via the Data Port Media Block Read Message: This field + enables control of which rows are returned on vertical out-of-bounds reads using the Data Port + Media Block Read Message. In the description below, frame mode refers to Vertical Line Stride + = 0, field mode is Vertical Line Stride = 1 in which only the even or odd rows are addressable. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 66 + RENDER_SURFACE_STATE + The frame refers to the entire surface, while the field refers only to the even or odd rows within + the surface. For other surfaces this field is reserved and MBZ. + Value Name Description Project + 0h NORMAL_MODE the row returned on an out-of-bound access is the All + closest row in the frame or field. Rows from the + opposite field are never returned. + 1h Reserved All + 2h PROGRESSIVE_FRAME the row returned on an out-of-bound access is the All + closest row in the frame, even if in field mode. + 3h INTERLACED_FRAME In field mode, the row returned on an out-of-bound All + access is the closest row in the field. In frame mode, + even out-of-bound rows return the nearest even row + while odd out-of-bound rows return the nearest odd + row. + 5:0 Cube Face Enables + Project: All + Format: U6 bit mask of enables + + + For SURFTYPE_CUBE Surfaces accessed via the Sampling Engine: Bits 5:0 of this field + enable the individual faces of a cube map. Enabling a face indicates that the face is present in + the cube map, while disabling it indicates that that face is represented by the texture map’s + border color. Refer to Memory Data Formats for the correlation between faces and the cube + map memory layout. Note that storage for disabled faces must be provided. For other surfaces + this field is reserved and MBZ. + Value Name + 1xxxxxb -X face + x1xxxxb +X face + xx1xxxb -Y face + xxx1xxb +Y face + xxxx1xb -Z face + xxxxx1b +Z face + + + Programming Notes + When TEXCOORDMODE_CLAMP is used when accessing a cube map, this field must be + programmed to 111111b (all faces enabled). This field is ignored unless the Surface Type is + SURFTYPE_CUBE. +1 31:0 Surface Base Address + Project: All + Format: GraphicsAddress[31:0] + Specifies the byte-aligned base address of the surface. + Programming Notes +  + For SURFTYPE_BUFFER render targets, this field specifies the base address of first + element of the surface. The surface is interpreted as a simple array of that single element + type. The address must be naturally-aligned to the element size (e.g., a buffer containing + R32G32B32A32_FLOAT elements must be 16-byte aligned) +  + For SURFTYPE_BUFFER non-rendertarget surfaces, this field specifies the base address of + the first element of the surface, computed in software by adding the surface base address to + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 67 + RENDER_SURFACE_STATE + the byte offset of the element in the buffer. +  + Mipmapped, cube and 3D sampling engine surfaces are stored in a "monolithic" (fixed) + format, and only require a single address for the base texture. +  + The Base Address for linear render target surfaces and surfaces accessed with the typed + surface read/write data port messages must be element-size aligned, for non-YUV surface + formats, or a multiple of 2 element-sizes for YUV surface formats. Other linear surfaces have + no alignment requirements (byte alignment is sufficient). +  + Linear depth buffer surface base addresses must be 64-byte aligned. Note that while render + targets (color) can be SURFTYPE_BUFFER, depth buffers cannot. +  + Tiled surface base addresses must be 4KB-aligned. Note that only the offsets from Surface + Base Address are tiled, Surface Base Address itself is not transformed using the tiling + algorithm. +  + For tiled surfaces, the actual start of the surface can be offset from the Surface Base + Address by the X Offset and Y Offset fields. +  + Certain message types used to access surfaces have more stringent alignment + requirements. Please refer to the specific message documentation for additional restrictions. + + 31:30 Reserved +2 Project: All + Format: MBZ + 29:16 Height + Project: All + Format: U14 + This field specifies the height of the surface. If the surface is MIP-mapped, this field contains + the height of the base MIP level. For buffers, this field specifies a portion of the buffer size. + Value Name Description + 0 SURFTYPE_1D: must be zero + [0,16383] SURFTYPE_2D: height of surface – 1 (y/v dimension) + [0,2047] SURFTYPE_3D: height of surface – 1 (y/v dimension) + [0,16383] SURFTYPE_CUBE: height of surface – 1 (y/v dimension) + [0,16383] SURFTYPE_BUFFER/STRBUF: contains bits [20:7] of the number of entries + in the buffer – 1 + + + Programming Notes + For typed buffer and structured buffer surfaces, the number of entries in the buffer ranges from + 1 to 227. For raw buffer surfaces, the number of entries in the buffer is the number of bytes + which can range from 1 to 230. After subtracting one from the number of entries, software must + place the fields of the resulting 27-bit value into the Height, Width, and Depth fields as + indicated, right-justified in each field. Unused upper bits must be set to zero.If Vertical Line + Stride is 1, this field indicates the height of the field, not the height of the frameThe Height of a + render target must be the same as the Height of the other render targets and the depth buffer + (defined in 3DSTATE_DEPTH_BUFFER), unless Surface Type is SURFTYPE_1D or + SURFTYPE_2D with Depth = 0 (non-array) and LOD = 0 (non-mip mapped). + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 68 + RENDER_SURFACE_STATE + If this surface in memory is accessed with Vertical Line Stride set to both 0 and 1, this field + must be an even value when Vertical Line Stride is 0. + If Media Pixel Boundary Mode is not set to NORMAL_MODE, this field must be an even value. + 15:14 Reserved + Project: All + Format: MBZ + 13:0 Width + Project: All + Format: U14-1 + + + This field specifies the width of the surface. If the surface is MIP-mapped, this field specifies + the width of the base MIP level. The width is specified in units of pixels or texels. For buffers, + this field specifies a portion of the buffer size. + For surfaces accessed with the Media Block Read/Write message, this field is in units of + DWords except when used for IECP and the output surface format is NV12 (R16_UNORM), + this field is in units of Words. + + + Value Name Description + [0, SURFTYPE_1D: width of surface – 1 (x/u dimension) + 16383] + [0, SURFTYPE_2D: width of surface – 1 (x/u dimension) + 16383] + [0, 2047] SURFTYPE_3D: width of surface – 1 (x/u dimension) + [0, SURFTYPE_CUBE: width of surface – 1 (x/u dimension) + 16383] + [0, 127] SURFTYPE_BUFFER/STRBUF: contains bits [6:0] of the number of entries in + the buffer – 1 + + + Programming Notes + For surface types other than SURFTYPE_BUFFER or STRBUF The Width specified by this + field must be less than or equal to the surface pitch (specified in bytes viathe Surface Pitch + field).For cube maps, Width must be set equal to the Height.For MONO8 textures, Width must + be a multiple of 32 texels.The Width of a render target must be the same as the Width of the + other render target(s) and the depth buffer (defined in 3DSTATE_DEPTH_BUFFER), unless + Surface Type is SURFTYPE_1D or SURFTYPE_2D with Depth = 0 (non-array) and LOD = 0 + (non-mip mapped).The Width of a render target with YUV surface format must be a multiple of + 2.For SURFTYPE_BUFFER: The low two bits of this field must be 11 if the Surface Format is + RAW (the size of the buffer must be a multiple of 4 bytes). +3 31:21 Depth + Project: All + Format: U11 + This field specifies the total number of levels for a volume texture or the number of array + elements allowed to be accessed starting at the Minimum Array Element for arrayed surfaces. + If the volume texture is MIP-mapped, this field specifies the depth of the base MIP level. For + buffers, this field specifies a portion of the buffer size. + Value Name Description + [0,2047] SURFTYPE_1D: number of array elements – 1 + [0,2047] SURFTYPE_2D: number of array elements – 1 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 69 + RENDER_SURFACE_STATE + [0,2047] SURFTYPE_3D: depth of surface – 1 (z/r dimension) + [0,2047] SURFTYPE_CUBE: number of array elements – 1 [see programming notes for + range] + [0,1023] SURFTYPE_BUFFER: contains bits [30:21] of the number of entries in the + buffer – 1 for Surface Format RAW. + [0,127] SURFTYPE_BUFFER: Contains bits [27:21] of the number of entries in the + buffer – 1 for other surface formats. + [0,63] SURFTYPE_STRBUF: contains bits [26:21] of the number of entries in the + buffer – 1 + + + Programming Notes + The Depth of a render target must be the same as the Depth of the other render target(s) and + of the depth buffer (defined in 3DSTATE_DEPTH_BUFFER).For SURFTYPE_CUBE:For + Sampling Engine Surfaces, the range of this field is [0,340], indicating the number of cube + array elements (equal to the number of underlying 2D array elements divided by 6). For other + surfaces, this field must be zero.For SURFTYPE_BUFFER: The range of this field is [0,63] + unless the Surface Format is RAW and Surface Ptich is 1 byte. + + + Errata Description Project + Errata: For SURFTYPE_CUBE sampling engine surfaces, the range of this field + is limited to [0,85]. + Errata: If Surface Array is enabled, and Depth is between 1024 and 2047, an + incorrect array slice may be accessed if the requested array index in the + message is greater than or equal to 4096. + 20:18 Reserved + + Format: MBZ + 17:0 Surface Pitch + Project: All + Format: U18 pitch in (#Bytes – 1) + + + This field specifies the surface pitch in (#Bytes - 1).For surfaces of type SURFTYPE_BUFFER + and SURFTYPE_STRBUF, this field indicates the size of the structure. + Value Name Description + [0,2047] For surfaces of type SURFTYPE_BUFFER: representing [1B, 2048B] + [0,2047] For surfaces of type SURFTYPE_STRBUF: representing [1B, 2048B] + [0,262143] For other linear surfaces: representing [1B, 256KB] + [511,262143] For X-tiled surface: representing [512B, 256KB] = [1 tile, 512 tiles] + [127,262143] For Y-tiled surfaces: representing [128B, 256KB] = [1 tile, 2048 tiles] + + + Programming Notes + For linear render target surfaces and surfaces accessed with the typed data port messages, + the pitch must be a multiple of the element size for non-YUV surface formats. Pitch must be a + multiple of 2 * element size for YUV surface formats. For linear surfaces with Surface Type of + SURFTYPE_STRBUF, the pitch must be a multiple of 4 bytes.For other linear surfaces, the + pitch can be any multiple of bytes.For tiled surfaces, the pitch must be a multiple of the tile + width. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 70 + RENDER_SURFACE_STATE + + Errata Description Project + Maximum pitch supported is 128KB for all surfaces +4 31 Reserved + Project: All + Exists If: [Surface Type] != SURFTYPE_STRBUF + Format: MBZ + 30:29 Render Target Rotation + Project: All + Exists If: [Surface Type] != SURFTYPE_STRBUF + Format: U2 enumerated type + + + For Render Target Surfaces: This field specifies the rotation of this render target surface when + being written to memory.For Other Surfaces:This field is ignored. + Value Name Description Project + 0h RTROTATE_0DEG No rotation (0 degrees) All + 1h RTROTATE_90DEG Rotate by 90 degrees All + 2h Reserved All + 3h RTROTATE_270DEG Rotate by 270 degrees All + + + Programming Notes + Rotation is not supported for render targets of any type other than simple, non-mip-mapped, + non-array 2D surfaces. The surface must be using tiled with X major.Width and Height fields + apply to the dimensions of the surface before rotation.For 90 and 270 degree rotated surfaces, + the Height (rather than the Width) must be less than or equal to the Surface Pitch (specified in + bytes).For 90 and 270 degree rotated surfaces, the actual Height and Width of the surface in + pixels (not the field value which is decremented) must both be even.Rotation is supported only + for surfaces with the following surface formats: B5G6R5_UNORM, B5G6R5_UNORM_SRGB, + R8G8B8[A|X]8_UNORM, R8G8B8[A|X]8_UNORM_SRGB, B8G8R8[A|X]8_UNORM, + B8G8R8[A|X]8_UNORM_SRGB, B10G10R10[A|X]2_UNORM, + B10G10R10A2_UNORM_SRGB, R10G10B10A2_UNORM, R10G10B10A2_UNORM_SRGB, + R16G16B16A16_FLOAT, R16G16B16X16_FLOAT.Rotation is not supported for typed UAV + messages + 31:27 Reserved + Project: All + Exists If: [Surface Type] == SURFTYPE_STRBUF + Format: MBZ + 28:18 Minimum Array Element + Project: All + Exists If: [Surface Type] != SURFTYPE_STRBUF + Format: U11 + For Sampling Engine, Render Target, and Typed 1D and 2D Surfaces:This field indicates the + minimum array element that can be accessed as part of this surface. This field is added to the + delivered array index before it is used to address the surface.For Render Target 3D + Surfaces:This field indicates the minimum ‘R’ coordinate on the LOD currently being rendered + to. This field is added to the delivered array index before it is used to address the surface.For + Sampling Engine Cube Surfaces:This field indicates the minimum array element in the + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 71 + RENDER_SURFACE_STATE + underlying 2D surface array that can be accessed as part of this surface (the cube array index + is multipled by 6 to compute this value, although this field is not restricted to only multiples of + 6). This field is added to the delivered array index before it is used to address the surface. + For Other Surfaces:This field must be set to zero. + Value Name Description + [0,2047] 1D/2D/cube surfaces + [0,2047] 3D surfaces + + + Errata Description Project + If Number of Multisamples is not MULTISAMPLECOUNT_1, this field must be + set to zero if this surface is used with sampling engine messages. + 17:7 Render Target View Extent + Project: All + Exists If: [Surface Type] != SURFTYPE_STRBUF + Format: U11 + For Render Target 3D Surfaces:This field indicates the extent of the accessible ‘R’ coordinates + minus 1 on the LOD currently being rendered to.For Render Target 1D and 2D Surfaces:This + field must be set to the same value as the Depth field.For Other Surfaces:This field is ignored. + Value Name Description + [0,2047] to indicate extent of [1,2048] + 6 Multisampled Surface Storage Format + Project: All + Exists If: [Surface Type] != SURFTYPE_STRBUF + Format: U1 enumerated type + + + This field indicates the storage format of the multisampled surface. + Value Name Description Project + 0h MSFMT_MSS Multsampled surface was/is rendered as a render All + target + 1h MSFMT_DEPTH_STENCIL Multisampled surface was rendered as a depth or All + stencil buffer + + + Programming Notes + All multisampled render target surfaces must have this field set to MSFMT_MSSIF this field is + MSFMT_DEPTH_STENCIL, the only sampling engine messages allowed are “ld2dms”, + “resinfo”, and “sampleinfo”. + This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1 + + + Errata Description Project + If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width is + >= 8192 (meaning the actual surface width is >= 8193 pixels), this field must be + set to MSFMT_MSS. + If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, + ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of + Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is > + 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field must + be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the following: + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 72 + RENDER_SURFACE_STATE + I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or + R24_UNORM_X8_TYPELESS. + 5:3 Number of Multisamples + Project: All + Exists If: [Surface Type] != SURFTYPE_STRBUF + Format: U3 enumerated type + + + This field indicates the number of multisamples on the surface. + Value Name Project + 0h MULTISAMPLECOUNT_1 All + 1h Reserved All + 2h MULTISAMPLECOUNT_4 All + 3h MULTISAMPLECOUNT_8 All + 4h-7h Reserved All + + + Programming Notes + If this field is any value other than MULTISAMPLECOUNT_1, the Surface Type must be + SURFTYPE_2D + This field must be set to MULTISAMPLECOUNT_1 unless the surface is a Sampling Engine + surface or Render Target surface. + This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when all RT channels are + not written + If this field is any value other than MULTISAMPLECOUNT_1, Surface Min LOD, Mip Count / + LOD, and Resource Min LOD must be set to zero + 26:0 Minimum Array Element + Project: All + Exists If: [Surface Type] == SURFTYPE_STRBUF + This field indicates the minimum array element that can be accessed as part of this surface. + This field is added to the delivered array index before it is used to address the surface. + Value Name + [0,226] + 2:0 Multisample Position Palette Index + + Exists If: [Surface Type] != SURFTYPE_STRBUF + Format: U3 + This field indicates the index into the sample position palette that the multisampled surface is + using. This field is only used as a return value for the sampleinfo message, and is otherwise + not used by hardware. + Value Name + [0,7] +5 31:25 X Offset + Project: All + Format: PixelOffset[8:2] + This field specifies the horizontal offset in pixels from the Surface Base Address to the start + (origin) of the surface. This field effectively loosens the alignment restrictions on the origin of + tiled surfaces. Previously, tiled surface origin was (by definition) located at the base address, + and thus needed to satisfy the 4KB base address alignment restriction. Now the origin can be + specified at a finer (4-wide x 2-high pixel) resolution. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 73 + RENDER_SURFACE_STATE + Value Name Description + [0,508] in multiples of 4 (low 2 bits missing) + + + Programming Notes + For linear surfaces, this field must be zero. + For surfaces accessed with the Data Port Media Block Read/Write message, the pixel size is + assumed to be 32 bits in width. + For Surface Format with other than 8, 16, 32, 64, or 128 bits per pixel, this field must be zero. + If Render Target Rotation is set to other than RTROTATE_0DEG, this field must be zero. + If Surface Type is SURFTYPE_STRBUF, this field must be zero. + This field must be zero if Surface Format is PLANAR*. For all other surfaces, Xoffset must be + programmed such that (max X of the draw rectangle)+Xoffset < 16K (max surface width) + For YUV422 surfaces, the pixel offset is in multiples of 2. Pixel offset specified in this case is + PixelOffset[7:1] + 24 Reserved + Project: All + Format: MBZ + 23:20 Y Offset + Project: All + Format: RowOffset[4:1] + This field specifies the vertical offset in rows from the Surface Base Address to the start of the + surface. (See additional description in the X Offset field) + Value Name Description + [0,30] in multiples of 2 (low bit missing) + + + Programming Notes + For linear surfaces, this field must be zero. For render targets in which the Render Target + Array Index is not zero, this field must be zero. For Surface Format with other than 8, 16, 32, + 64, or 128 bits per pixel, this field must be zero. If Render Target Rotation is set to other than + RTROTATE_0DEG, this field must be zero. For surfaces accessed in field mode (Vertical Line + Stride = 1 or equivalent Media Block Read/Write message override), this field must be set to a + multiple of 4. If Surface Type is SURFTYPE_STRBUF, this field must be zero. This field must + be zero if Surface Format is PLANAR*. For all other surfaces, Yoffset must be programmed + such that (Maximum Yof draw rectangle) + Yoffset < 16K (max surface height) + 19:16 Surface Object Control State + Project: All + Format: MEMORY_OBJECT_CONTROL_STATE + Specifies the memory object control state for this surface. + + 15:14 Reserved + + Format: MBZ + 13:8 Reserved + Project: All + Format: MBZ + 7:4 Surface Min LOD + Project: All + Format: U4 in LOD units + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 74 + RENDER_SURFACE_STATE + + + For Sampling Engine and Typed Surfaces:This field indicates the most detailed LOD that can + be accessed as part of this surface. This field is added to the delivered LOD (sample_l, ld, or + resinfo message types) before it is used to address the surface.For Other Surfaces:This field is + ignored. + Value Name + [0,14] + + + Programming Notes + This field must be zero if the Surface Format is MONO8 + 3:0 MIP Count / LOD + Project: All + Format: Sampling Engine and Typed Surfaces: U4 in (LOD units – 1)Render Target Surfaces: + U4 in LOD units + + + For Sampling Engine and Typed Surfaces:This field indicates the number of MIP levels allowed + to be accessed starting at Surface Min LOD, which must be less than or equal to the number of + MIP levels actually stored in memory for this surface. Force the mip map access to be between + the mipmap specified by the integer bits of the Min LOD and the ceiling of the value specified + here.For Render Target Surfaces:This field defines the MIP level that is currently being + rendered into. This is the absolute MIP level on the surface and is not relative to the Surface + Min LOD field, which is ignored for render target surfaces.For Other Surfaces:This field is + reserved : MBZ + Value Name Description Project + [0,14] Sampling Engine and Typed Surfaces: representing [1,15] MIP levels + [0,14] Render Target Surfaces: representing LOD + 0 Other Surfaces + 0h Disable All + 1h Enable All + + + Programming Notes + The LOD of a render target must be the same as the LOD of the other render target(s) and of + the depth buffer (defined in 3DSTATE_DEPTH_BUFFER). + For render targets with YUV surface formats, the LOD must be zero. + It is not legal to have more than one 1x1 mipmap. Software must ensure that MIP Count is set + to end on the first 1x1 mipmap (or before). +6 31:30 Reserved: MBZ + Project: All +This DW6 Exists If: [Surface Format] == PLANAR +appllies only if Format: MBZ +Surface 29:16 X Offset for UV Plane +Format is not Exists If: [Surface Format] == PLANAR +PLANAR* + Format: U14 Row Offset + + + This field specifies the horizontal offset in pixels from the Surface Base Address to the start + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 75 + RENDER_SURFACE_STATE + (origin) of the interleaved UV plane. This field is only used for PLANAR surface formats. + Programming Notes + This field must indicate an even number of pixels. + 15:14 Reserved + Project: All + Exists If: [Surface Format] == PLANAR + Format: MBZ + 31:12 MCS Base Address + Project: All + Exists If: ([Surface Format] != 'PLANAR') && ([MCS Enable] == 'Enabled') + Format: GraphicsAddress[31:12] + Specifies the 4kbyte-aligned base address of the MCS surface associated with the MSS + surface specified in other 32 fields. + Programming Notes + The MCS surface must be stored as Tile Y. + The MCS surface shares Height, Width, Depth, Surface Min LOD, MIP Count / LOD, Surface + Object Control State, Surface Array Spacing, and Minimum Array Element with the primary + surface. + 31:6 Append Counter Address + Project: All + Exists If: ([Surface Format] != 'PLANAR') && ([MCS Enable] == 'Disabled') + Format: GraphicsAddress[31:6] + Specifies the 64byte-aligned base address of the Append counter associated with this surface + specified in other SURFACE_STATE fields. + + 11:3 MCS Surface Pitch + Project: All + Exists If: ([Surface Format] != 'PLANAR') && ([MCS Enable] == 'Enabled') + Format: U9-1 pitch in #Tiles + + + This field specifies the MCS surface pitch in (#Tiles – 1). + Value Name Description + [0,511] representing [1 tile, 512 tiles] + 5:2 Reserved + Project: All + Exists If: ([Surface Format] != 'PLANAR') && ([MCS Enable] == 'Disabled') + Format: MBZ + 2:1 Reserved + Project: All + Exists If: ([Surface Format] != 'PLANAR') && ([MCS Enable] == 'Enabled') + Format: MBZ + 1 Append Counter Enable + Project: All + Exists If: ([Surface Format] != 'PLANAR') && ([MCS Enable] == 'Disabled') + Format: Enable + Enables the use of the Append Counter with this surface. If disabled, all other Append counter + fields are ignored. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 76 + RENDER_SURFACE_STATE + + 13:0 Y Offset for UV Plane + Exists If: [Surface Format] == PLANAR + Format: 14 Row Offset + + + This field specifies the vertical offset in rows from the Surface Base Address to the start (origin) + of the interleaved UV plane. This field is only used for PLANAR surface formats. + Programming Notes + This field must indicate an even number (bit 0 = 0). + 0 MCS Enable + Project: All + Format: Enable + Enables the use of the MCS with this surface. If disabled, all other MCS fields are ignored. + For Render Target and Sampling Engine Surfaces:If the surface is multisampled (Number of + Multisamples any value other than MULTISAMPLECOUNT_1), this field must be enabled. + For Other Surfaces:This field and the other MCS fields are ignored. + Programming Notes + When accessing a multisampled surface using the sampling engine, the MCS surface is read + in a separate pass and is considered by hardware to be an independent surface. + This same bitfield is used when MCS is enabled; also when disabled. + + + Errata Description Project + If this field is disabled and the sampling engine ld_mcs message is issued on + this surface, the MCS surface may be accessed. Software must ensure that the + surface is defined to avoid GTT errors. This same bitfield is used when MCS is + enabled; also when disabled. This field must be set to 0 for all SINT MSRTs + when all RT channels are not written + + When ld2dms from MCS on a subspan that some of the pixel on the pixel are + not valid, can lead to data corruption. +7 31 Red Clear Color + + Format: U1 enumerated type + + + For Sampling Engine Multisampled Surfaces and Render Targets:Specifies the clear value for + the red channel.For Other Surfaces:This field is ignored. + Value Name Description Project + 0 CC_ZERO Clear color value is 0.0, correctly interpreted based on surface format. All + 1 CC_ONE Clear color value is 1.0, correctly interpreted based on surface format. All + 30 Green Clear Color + + Format: U1 enumerated type + + + For Sampling Engine Multisampled Surfaces and Render Targets:Specifies the clear value for + the green channel.For Other Surfaces:This field is ignored. + Value Name Description Project + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 77 + RENDER_SURFACE_STATE + 0 CC_ZERO Clear color value is 0.0, correctly interpreted based on surface format. All + 1 CC_ONE Clear color value is 1.0, correctly interpreted based on surface format. All + 29 Blue Clear Color + + Format: U1 enumerated type + + + For Sampling Engine Multisampled Surfaces and Render Targets:Specifies the clear value for + the blue channel.For Other Surfaces:This field is ignored. + Value Name Description Project + 0 CC_ZERO Clear color value is 0.0, correctly interpreted based on surface format. All + 1 CC_ONE Clear color value is 1.0, correctly interpreted based on surface format. All + 28 Alpha Clear Color + + Format: U1 enumerated type + + + For Sampling Engine Multisampled Surfaces and Render Targets:Specifies the clear value for + the alpha channel.For Other Surfaces:This field is ignored. + Value Name Description Project + 0 CC_ZERO Clear color value is 0.0, correctly interpreted based on surface format. All + 1 CC_ONE Clear color value is 1.0, correctly interpreted based on surface format. All + 15:12 Reserved + Project: All + Format: MBZ + 11:0 Resource Min LOD + Project: All + Format: U4.8 in LOD units + + + For Sampling Engine Surfaces:This field indicates the most detailed LOD that is present in the + resource underlying the surface. Refer to the “LOD Computation Pseudocode” section for the + use of this field.For Other Surfaces:This field is ignored. + Value Name + [0,14] + + + Programming Notes + This field must be zero if the Surface Format is MONO8 + This field must be zero if the ChromaKey Enable is enabled in the associated sampler. + + + +2.12.2.1.1 Surface Formats +The following table is used ONLY when ASTC_ENABLE is set to 0, which indicates the supported surface +formats and the 9-bit encoding for each. Note that some of these formats are used not only by the +Sampling Engine, but also by the Data Port and the Vertex Fetch unit. When ASTC_ENABLE is set to 1, +please refer to SURFACE_STATE table on the surface format value and description. The name for all the +ASTC texture format is ASTC. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 78 + SURFACE_FORMAT +Project: All +Size (in bits): 9 +The following table indicates the supported surface formats and the 9-bit encoding for each. Note that some of these +formats are used not only by the Sampling Engine, but also by the Data Port and the Vertex Fetch unit. + Bits Per Element + Value Name (BPE) Description +000h R32G32B32A32_FLOAT 128 +001h R32G32B32A32_SINT 128 +002h R32G32B32A32_UINT 128 +003h R32G32B32A32_UNORM 128 +004h R32G32B32A32_SNORM 128 +005h R64G64_FLOAT 128 +006h R32G32B32X32_FLOAT 128 +007h R32G32B32A32_SSCALED 128 +008h R32G32B32A32_USCALED 128 +020h R32G32B32A32_SFIXED 128 +021h R64G64_PASSTHRU 128 +040h R32G32B32_FLOAT 96 +041h R32G32B32_SINT 96 +042h R32G32B32_UINT 96 +043h R32G32B32_UNORM 96 +044h R32G32B32_SNORM 96 +045h R32G32B32_SSCALED 96 +046h R32G32B32_USCALED 96 +050h R32G32B32_SFIXED 96 +080h R16G16B16A16_UNORM 64 +081h R16G16B16A16_SNORM 64 +082h R16G16B16A16_SINT 64 +083h R16G16B16A16_UINT 64 +084h R16G16B16A16_FLOAT 64 +085h R32G32_FLOAT 64 +086h R32G32_SINT 64 +087h R32G32_UINT 64 +088h R32_FLOAT_X8X24_TYPELESS 64 +089h X32_TYPELESS_G8X24_UINT 64 +08Ah L32A32_FLOAT 64 +08Bh R32G32_UNORM 64 +08Ch R32G32_SNORM 64 +08Dh R64_FLOAT 64 +08Eh R16G16B16X16_UNORM 64 +08Fh R16G16B16X16_FLOAT 64 +090h A32X32_FLOAT 64 +091h L32X32_FLOAT 64 +092h I32X32_FLOAT 64 +093h R16G16B16A16_SSCALED 64 +094h R16G16B16A16_USCALED 64 +095h R32G32_SSCALED 64 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 79 + SURFACE_FORMAT +096h R32G32_USCALED 64 +0A0h R32G32_SFIXED 64 +0A1h R64_PASSTHRU 64 +0C0h B8G8R8A8_UNORM 32 +0C1h B8G8R8A8_UNORM_SRGB 32 +0C2h R10G10B10A2_UNORM 32 +0C3h R10G10B10A2_UNORM_SRGB 32 +0C4h R10G10B10A2_UINT 32 +0C5h R10G10B10_SNORM_A2_UNORM 32 +0C7h R8G8B8A8_UNORM 32 +0C8h R8G8B8A8_UNORM_SRGB 32 +0C9h R8G8B8A8_SNORM 32 +0CAh R8G8B8A8_SINT 32 +0CBh R8G8B8A8_UINT 32 +0CCh R16G16_UNORM 32 +0CDh R16G16_SNORM 32 +0CEh R16G16_SINT 32 +0CFh R16G16_UINT 32 +0D0h R16G16_FLOAT 32 +0D1h B10G10R10A2_UNORM 32 +0D2h B10G10R10A2_UNORM_SRGB 32 +0D3h R11G11B10_FLOAT 32 +0D6h R32_SINT 32 +0D7h R32_UINT 32 +0D8h R32_FLOAT 32 +0D9h R24_UNORM_X8_TYPELESS 32 +0DAh X24_TYPELESS_G8_UINT 32 +0DDh L32_UNORM 32 +0DEh A32_UNORM 32 +0DFh L16A16_UNORM 32 +0E0h I24X8_UNORM 32 +0E1h L24X8_UNORM 32 +0E2h A24X8_UNORM 32 +0E3h I32_FLOAT 32 +0E4h L32_FLOAT 32 +0E5h A32_FLOAT 32 +0E6h X8B8_UNORM_G8R8_SNORM 32 +0E7h A8X8_UNORM_G8R8_SNORM 32 +0E8h B8X8_UNORM_G8R8_SNORM 32 +0E9h B8G8R8X8_UNORM 32 +0EAh B8G8R8X8_UNORM_SRGB 32 +0EBh R8G8B8X8_UNORM 32 +0ECh R8G8B8X8_UNORM_SRGB 32 +0EDh R9G9B9E5_SHAREDEXP 32 +0EEh B10G10R10X2_UNORM 32 +0F0h L16A16_FLOAT 32 +0F1h R32_UNORM 32 +0F2h R32_SNORM 32 +0F3h R10G10B10X2_USCALED 32 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 80 + SURFACE_FORMAT +0F4h R8G8B8A8_SSCALED 32 +0F5h R8G8B8A8_USCALED 32 +0F6h R16G16_SSCALED 32 +0F7h R16G16_USCALED 32 +0F8h R32_SSCALED 32 +0F9h R32_USCALED 32 +100h B5G6R5_UNORM 16 +101h B5G6R5_UNORM_SRGB 16 +102h B5G5R5A1_UNORM 16 +103h B5G5R5A1_UNORM_SRGB 16 +104h B4G4R4A4_UNORM 16 +105h B4G4R4A4_UNORM_SRGB 16 +106h R8G8_UNORM 16 +107h R8G8_SNORM 16 +108h R8G8_SINT 16 +109h R8G8_UINT 16 +10Ah R16_UNORM 16 +10Bh R16_SNORM 16 +10Ch R16_SINT 16 +10Dh R16_UINT 16 +10Eh R16_FLOAT 16 +10Fh A8P8_UNORM_PALETTE0 16 +110h A8P8_UNORM_PALETTE1 16 +111h I16_UNORM 16 +112h L16_UNORM 16 +113h A16_UNORM 16 +114h L8A8_UNORM 16 +115h I16_FLOAT 16 +116h L16_FLOAT 16 +117h A16_FLOAT 16 +118h L8A8_UNORM_SRGB 16 +119h R5G5_SNORM_B6_UNORM 16 +11Ah B5G5R5X1_UNORM 16 +11Bh B5G5R5X1_UNORM_SRGB 16 +11Ch R8G8_SSCALED 16 +11Dh R8G8_USCALED 16 +11Eh R16_SSCALED 16 +11Fh R16_USCALED 16 +122h P8A8_UNORM_PALETTE0 16 +123h P8A8_UNORM_PALETTE1 16 +124h A1B5G5R5_UNORM 16 +125h A4B4G4R4_UNORM 16 +126h L8A8_UINT 16 +127h L8A8_SINT 16 +140h R8_UNORM 8 +141h R8_SNORM 8 +142h R8_SINT 8 +143h R8_UINT 8 +144h A8_UNORM 8 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 81 + SURFACE_FORMAT +145h I8_UNORM 8 +146h L8_UNORM 8 +147h P4A4_UNORM_PALETTE0 8 +148h A4P4_UNORM_PALETTE0 8 +149h R8_SSCALED 8 +14Ah R8_USCALED 8 +14Bh P8_UNORM_PALETTE0 8 +14Ch L8_UNORM_SRGB 8 +14Dh P8_UNORM_PALETTE1 8 +14Eh P4A4_UNORM_PALETTE1 8 +14Fh A4P4_UNORM_PALETTE1 8 +150h Y8_UNORM 8 +152h L8_UINT 8 +153h L8_SINT 8 +154h I8_UINT 8 +155h I8_SINT 8 +180h DXT1_RGB_SRGB 0 +181h R1_UNORM 1 +182h YCRCB_NORMAL 0 +183h YCRCB_SWAPUVY 0 +184h P2_UNORM_PALETTE0 2 +185h P2_UNORM_PALETTE1 2 +186h BC1_UNORM 0 (DXT1) +187h BC2_UNORM 0 (DXT2/3) +188h BC3_UNORM 0 (DXT4/5) +189h BC4_UNORM 0 +18Ah BC5_UNORM 0 +18Bh BC1_UNORM_SRGB 0 (DXT1_SRGB) +18Ch BC2_UNORM_SRGB 0 (DXT2/3_SRGB) +18Dh BC3_UNORM_SRGB 0 (DXT4/5_SRGB) +18Eh MONO8 1 +18Fh YCRCB_SWAPUV 0 +190h YCRCB_SWAPY 0 +191h DXT1_RGB 0 +192h FXT1 0 +193h R8G8B8_UNORM 24 +194h R8G8B8_SNORM 24 +195h R8G8B8_SSCALED 24 +196h R8G8B8_USCALED 24 +197h R64G64B64A64_FLOAT 256 +198h R64G64B64_FLOAT 192 +199h BC4_SNORM 0 +19Ah BC5_SNORM 0 +19Bh R16G16B16_FLOAT 48 +19Ch R16G16B16_UNORM 48 +19Dh R16G16B16_SNORM 48 +19Eh R16G16B16_SSCALED 48 +19Fh R16G16B16_USCALED 48 +1A1h BC6H_SF16 0 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 82 + SURFACE_FORMAT +1A2h BC7_UNORM 0 +1A3h BC7_UNORM_SRGB 0 +1A4h BC6H_UF16 0 +1A5h PLANAR_420_8 0 +1A8h R8G8B8_UNORM_SRGB 24 +1A9h ETC1_RGB8 0 +1AAh ETC2_RGB8 0 +1ABh EAC_R11 0 +1ACh EAC_RG11 0 +1ADh EAC_SIGNED_R11 0 +1AEh EAC_SIGNED_RG11 0 +1AFh ETC2_SRGB8 0 +1B0h R16G16B16_UINT 48 +1B1h R16G16B16_SINT 48 +1B2h R32_SFIXED 32 +1B3h R10G10B10A2_SNORM 32 +1B4h R10G10B10A2_USCALED 32 +1B5h R10G10B10A2_SSCALED 32 +1B6h R10G10B10A2_SINT 32 +1B7h B10G10R10A2_SNORM 32 +1B8h B10G10R10A2_USCALED 32 +1B9h B10G10R10A2_SSCALED 32 +1BAh B10G10R10A2_UINT 32 +1BBh B10G10R10A2_SINT 32 +1BCh R64G64B64A64_PASSTHRU 256 +1BDh R64G64B64_PASSTHRU 192 +1C0h ETC2_RGB8_PTA 0 +1C1h ETC2_SRGB8_PTA 0 +1C2h ETC2_EAC_RGBA8 0 +1C3h ETC2_EAC_SRGB8_A8 0 +1C8h R8G8B8_UINT 24 +1C9h R8G8B8_SINT 24 +1FFh RAW 0 + + + + +NOTE: “RAW” is supported only with buffers and structured buffers accessed via the untyped surface +read/write and untyped atomic operation messages, which do not have a column in the table. +Errata : RT format of A8_UNORM, R32_UINT, R32_SINT, R32G32_SINT,R32G32_UINT are not +supported in MSAA 4x/8x mode. +Errata : BC6H_SF16, BC6H_UF16, and BC7_SRGB are not supported and may result in data corruption +if used. + +2.12.2.1.2 Sampler Output Channel Mapping +The following table indicates the mapping of the channels from the surface to the channels output from +the sampling engine. Formats with all four channels (R/G/B/A) in their name map each surface channel to +the corresponding output, thus those formats are not shown in this table. + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 83 + Some formats are supported only in DX10/OGL Border Color Mode. Those formats have only that mode +indicated. Formats that behave the same way in both Border Color Modes are indicated by that column +being blank. + Borde + Border r + Filterin Shado Chrom Color Color + Surface Format Name g w Map a Key Mode R G B A Mode R G B A +R32G32B32A32_FLOAT R G B A +R32G32B32A32_SINT R G B A +R32G32B32A32_UINT R G B A +R32G32B32X32_FLOAT R G B 1.0 +R32G32B32_FLOAT R G B 1.0 +R32G32B32_SINT R G B 1.0 +R32G32B32_UINT DX10/O R G B 1.0 + GL +R16G16B16A16_UNORM R G B A +R16G16B16A16_SNORM R G B A +R16G16B16A16_SINT R G B A +R16G16B16A16_UINT R G B A +R16G16B16A16_FLOAT R G B A +R32G32_FLOAT DX10/O R G 0.0 1.0 DX9 R G 1.0 1.0 + GL +R32G32_SINT DX10/O R G 0.0 1.0 + GL +R32G32_UINT DX10/O R G 0.0 1.0 + GL +R32_FLOAT_X8X24_TYPELE DX10/O R 0.0 0.0 1.0 +SS GL +X32_TYPELESS_G8X24_UIN DX10/O 0.0 G 0.0 1.0 +T GL +L32A32_FLOAT DX10/O L L L A + GL +R16G16B16X16_UNORM R G B 1.0 +R16G16B16X16_FLOAT R G B 1.0 +A32X32_FLOAT 0.0 0.0 0.0 A +L32X32_FLOAT L L L 1.0 +I32X32_FLOAT I I I I +B8G8R8A8_UNORM R G B A +B8G8R8A8_UNORM_SRGB R G B A +R10G10B10A2_UNORM R G B A +R10G10B10A2_UNORM_SRG R G B A +B +R10G10B10A2_UINT R G B A +R10G10B10_SNORM_A2_UN R G B A +ORM +R8G8B8A8_UNORM R G B A +R8G8B8A8_UNORM_SRGB R G B A +R8G8B8A8_SNORM R G B A +R8G8B8A8_SINT R G B A +R8G8B8A8_UINT R G B A +R16G16_UNORM DX10/O R G 0.0 1.0 DX9 R G 1.0 1.0 + GL +R16G16_SNORM DX10/O R G 0.0 1.0 DX9 R G 1.0 1.0 + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 84 + Borde + Border r + Filterin Shado Chrom Color Color + Surface Format Name g w Map a Key Mode R G B A Mode R G B A + GL +R16G16_SINT DX10/O R G 0.0 1.0 + GL +R16G16_UINT DX10/O R G 0.0 1.0 + GL +R16G16_FLOAT DX10/O R G 0.0 1.0 DX9 R G 1.0 1.0 + GL +B10G10R10A2_UNORM R G B A +B10G10R10A2_UNORM_SRG R G B A +B +R11G11B10_FLOAT R G B 1.0 +R32_SINT DX10/O R 0.0 0.0 1.0 + GL +R32_UINT DX10/O R 0.0 0.0 1.0 + GL +R32_FLOAT DX10/O R 0.0 0.0 1.0 DX9 R 1.0 1.0 1.0 + GL +R24_UNORM_X8_TYPELESS DX10/O R 0.0 0.0 1.0 + GL +X24_TYPELESS_G8_UINT DX10/O 0.0 G 0.0 1.0 + GL +L16A16_UNORM L L L A +I24X8_UNORM I I I I +L24X8_UNORM L L L 1.0 +A24X8_UNORM 0.0 0.0 0.0 A +I32_FLOAT I I I I +L32_FLOAT L L L 1.0 +A32_FLOAT 0.0 0.0 0.0 A +B8G8R8X8_UNORM R G B 1.0 +B8G8R8X8_UNORM_SRGB R G B 1.0 +R8G8B8X8_UNORM R G B 1.0 +R8G8B8X8_UNORM_SRGB R G B 1.0 +R9G9B9E5_SHAREDEXP R G B 1.0 +B10G10R10X2_UNORM R G B 1.0 +L16A16_FLOAT L L L A +B5G6R5_UNORM R G B 1.0 +B5G6R5_UNORM_SRGB R G B 1.0 +B5G5R5A1_UNORM R G B A +B5G5R5A1_UNORM_SRGB R G B A +B4G4R4A4_UNORM R G B A +B4G4R4A4_UNORM_SRGB R G B A +R8G8_UNORM DX10/O R G 0.0 1.0 DX9 R G 1.0 1.0 + GL +R8G8_SNORM DX10/O R G 0.0 1.0 DX9 R G 1.0 1.0 + GL +R8G8_SINT DX10/O R G 0.0 1.0 + GL +R8G8_UINT DX10/O R G 0.0 1.0 + GL + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 85 + Borde + Border r + Filterin Shado Chrom Color Color + Surface Format Name g w Map a Key Mode R G B A Mode R G B A +R16_UNORM DX10/O R 0.0 0.0 1.0 + GL +R16_SNORM DX10/O R 0.0 0.0 1.0 + GL +R16_SINT DX10/O R 0.0 0.0 1.0 + GL +R16_UINT DX10/O R 0.0 0.0 1.0 + GL +R16_FLOAT DX10/O R 0.0 0.0 1.0 DX9 R 1.0 1.0 1.0 + GL +A8P8_UNORM_PALETTE0 R G B A +A8P8_UNORM_PALETTE1 R G B A +I16_UNORM I I I I +L16_UNORM L L L 1.0 +A16_UNORM 0.0 0.0 0.0 A +L8A8_UNORM L L L A +I16_FLOAT I I I I +L16_FLOAT L L L 1.0 +A16_FLOAT 0.0 0.0 0.0 A +L8A8_UNORM_SRGB L L L A +R5G5_SNORM_B6_UNORM R G B 1.0 +P8A8_UNORM_PALETTE0 R G B A +P8A8_UNORM_PALETTE1 R G B A +R8_UNORM DX10/O R 0.0 0.0 1.0 + GL +R8_SNORM DX10/O R 0.0 0.0 1.0 + GL +R8_SINT DX10/O R 0.0 0.0 1.0 + GL +R8_UINT DX10/O R 0.0 0.0 1.0 + GL +A8_UNORM 0.0 0.0 0.0 A +I8_UNORM I I I I +L8_UNORM L L L 1.0 +P4A4_UNORM_PALETTE0 R G B A +A4P4_UNORM_PALETTE0 R G B A +P8_UNORM_PALETTE0 R G B A +L8_UNORM_SRGB L L L 1.0 +P8_UNORM_PALETTE1 R G B A +P4A4_UNORM_PALETTE1 R G B A +A4P4_UNORM_PALETTE1 R G B A +DXT1_RGB_SRGB R G B 1.0 +R1_UNORM R 0.0 0.0 1.0 +YCRCB_NORMAL Cr Y Cb 1.0 +YCRCB_SWAPUVY Cr Y Cb 1.0 +P2_UNORM_PALETTE0 R G B A +P2_UNORM_PALETTE1 R G B A +BC1_UNORM R G B A +BC2_UNORM R G B A + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 86 + Borde + Border r + Filterin Shado Chrom Color Color + Surface Format Name g w Map a Key Mode R G B A Mode R G B A +BC3_UNORM R G B A +BC4_UNORM DX10/O R 0.0 0.0 1.0 + GL +BC5_UNORM DX10/O R G 0.0 1.0 + GL +BC1_UNORM_SRGB R G B A +BC2_UNORM_SRGB R G B A +BC3_UNORM_SRGB R G B A +MONO8 N/ N/ N/ N/ + A A A A +YCRCB_SWAPUV Cr Y Cb 1.0 +YCRCB_SWAPY Cr Y Cb 1.0 +DXT1_RGB R G B 1.0 +FXT1 R G B A +BC4_SNORM DX10/O R 0.0 0.0 1.0 + GL +BC5_SNORM DX10/O R G 0.0 1.0 + GL +R16G16B16_FLOAT R G B 1.0 +BC6H_SF16 R G B 1.0 +BC7_UNORM R G B A +BC7_UNORM_SRGB R G B A +BC6H_UF16 R G B 1.0 + + +2.12.2.2 SURFACE_STATE for deinterlace, sample_8x8, and VME + + MEDIA_SURFACE_STATE + +Exists If: (MessageType == 'Deinterlace') || (MessageType == 'Sample_8x8') +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +This is the SURFACE_STATE used by only deinterlace, sample_8x8, and VME messages. +DWord Bit Description +0 31:0 Surface Base Address + + Format: GraphicsAddress[31:0] + Specifies the byte-aligned base address of the surface + Programming Notes + For SURFTYPE_BUFFER render targets, this field specifies the base address of first element of the + surface. The surface is interpreted as a simple array of that single element type. The address must be + naturally-aligned to the element size (e.g., a buffer containing R32G32B32A32_FLOAT elements must + be 16-byte aligned).For SURFTYPE_BUFFER non-rendertarget surfaces, this field specifies the base + address of the first element of the surface, computed in software by adding the surface base address + to the byte offset of the element in the buffer. Mipmapped, cube and 3D sampling engine surfaces are + stored in a “monolithic” (fixed) format, and only require a single address for the base texture.Linear + render target surface base addresses must be element-size aligned, for non-YUV surface formats, or a + multiple of 2 element-sizes for YUV surface formats. Other linear surfaces have no alignment + requirements (byte alignment is sufficient.)Linear depth buffer surface base addresses must be 64-byte + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 87 + MEDIA_SURFACE_STATE + aligned. Note that while render targets (color) can be SURFTYPE_BUFFER, depth buffers + cannot.Tiled surface base addresses must be 4KB-aligned. Note that only the offsets from Surface + Base Address are tiled, Surface Base Address itself is not transformed using the tiling algorithm.Tiled + surface base addresses must be 4KB-aligned. Note that only the offsets from Surface Base Address + are tiled, Surface Base Address itself is not transformed using the tiling algorithm.For tiled surfaces, + the actual start of the surface can be offset from the Surface Base Address by the X Offset and Y + Offset fields.Certain message types used to access surfaces have more stringent alignment + requirements. Please refer to the specific message documentation for additional restrictions. +1 31:18 Height + Format: U14 + This field specifies the height of the surface in units of pixels. For PLANAR surface formats, this field + indicates the height of the Y (luma) plane. + Value Name Description + [0,16383] representing heights [1,16384] + + + Programming Notes + Height (field value + 1) must be a multiple of 2 for PLANAR_420 surfaces.If Vertical Line Stride is 1, + this field indicates the height of the field, not the height of the frame. + 17:4 Width + Format: U14 + This field specifies the width of the surface in units of pixels. For PLANAR surface formats, this field + indicates the width of the Y (luma) plane. + Value Name Description + [0,16383] representing widths [1,16384] + + + Programming Notes +  The Width specified by this field multiplied by the pixel size in bytes must be less than or equal to + the surface pitch (specified in bytes via the Surface Pitch field). +  Width (field value + 1) must be a multiple of 2 for PLANAR_420, PLANAR_422, and all YCRCB_* + and PLANAR_Y16_UNORM surfaces, and must be a multiple of 4 for PLANAR_411 and + PLANAR_Y8_UNORM surfaces. +  For deinterlace messages, the Width (field value + 1) must be a multiple of 8. + + 3:2 Picture Structure + Specifies the encoding of the current picture. + Value Name + 00b Frame Picture + 01b Top Field Picture + 10b Bottom Field Picture + 11b Invalid, not allowed + 1:0 Cr(V)/Cb(U) Pixel Offset V Direction + Format: U0.2 + Specifies the distance to the U/V values with respect to the even numbered Y channels in the V + direction + Programming Notes + This field is ignored for all formats except PLANAR_420_8 +2 31:28 Surface Format + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 88 + MEDIA_SURFACE_STATE + Specifies the format of the surface. All of the Y and G channels will use table 0 and all of the Cr/Cb/R/B + channels will use table 1 + Value Name Description + 0 YCRCB_NORMAL + 1 YCRCB_SWAPUVY + 2 YCRCB_SWAPUV + 3 YCRCB_SWAPY + 4 PLANAR_420_8 + 5 PLANAR_411_8 Deinterlace only + 6 PLANAR_422_8 Deinterlace only + 7 STMM_DN_STATISTICS Deinterlace only + 8 R10G10B10A2_UNORM Sample_8x8 only + 9 R8G8B8A8_UNORM Sample_8x8 only + 10 R8B8_UNORM (CrCb) Sample_8x8 only + 11 R8_UNORM (Cr/Cb) Sample_8x8 only + 12 Y8_UNORM + 15 Reserved + 27 Interleave Chroma + + Format: Enable + This field indicates that the chroma fields are interleaved in a single plane rather than stored as two + separate planes. This field is only used for PLANAR surface formats. + + 26 Reserved + + Format: MBZ + 25:22 Surface Object Control State (MEMORY_OBJECT_CONTROL_STATE) + + + This 4-bit field is used in various state commands and indirect state objects to define LLC cacheability + including graphics data type for memory objects. + 21 Reserved + + Format: MBZ + 20:3 Surface Pitch + Format: U18-1 pitch in Bytes + + + This field specifies the surface pitch in (#Bytes - 1). + Value Name Description + [0,2047] For surfaces of type SURFTYPE_BUFFER: representing [1B, 2048B] + [0,2047] For surfaces of type SURFTYPE_STRBUF: representing [1B, 2048B] + [0,524287] For other linear surfaces: representing [1B, 256KB] + [511, 131071] For X-tiled surface: representing [512B, 256KB] = [1 tile, 512 tiles] + [127, 131071] For Y-tiled surfaces: representing [128B, 256KB] = [1 tile, 2048 tiles] + + + Programming Notes + For tiled surfaces, the pitch must be a multiple of the tile widthIf Half Pitch for Chroma is set, this field + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 89 + MEDIA_SURFACE_STATE + must be a multiple of two tile widths for tiled surfaces, or a multiple of 2 bytes for linear surfaces.The + Surface Pitches of current picture and reference picture should be declared as the identical type in VDI + mode with identical Height, Width and Format. + 2 Half Pitch for Chroma + Format: Enable + This field indicates that the chroma plane(s) will use a pitch equal to half the value specified in the + Surface Pitch field. This field is only used for PLANAR surface formats. + + 1:0 Tile Mode + Format: U2 enumerated type + + + This field specifies the type of memory tiling (Linear, WMajor, XMajor, or YMajor) employed to tile this + surface. See Memory Interface Functions for details on memory tiling and restrictions. + Value Name Description Project + 0h TILEMODE_LINEAR Linear mode (no tiling) All + 1h Reserved Reserved All + 2h TILEMODE_XMAJOR X major tiling All + 3h TILEMODE_YMAJOR Y major tiling All + + + Programming Notes +  Refer to Memory Data Formats for restrictions on TileMode direction for the various buffer types. + (Of particular interest is the fact that YMAJOR tiling is not supported for display/overlay buffers). +  The corresponding cache(s) must be invalidated before a previously accessed surface is + accessed again with an altered state of this field. +  Linear surfaces can be mapped to Main Memory (uncached) or System Memory (cacheable, + snooped). Tiled (X/Y/W) surfaces can only be mapped to Main Memory. + +3 31:30 Reserved + Project: All + Format: MBZ + 29:16 X Offset for U(Cb) + Format: U14 Pixel Offset + + + For Planar surfaces this field specifies the horizontal offset in pixels from the Surface Base Address to + the start (origin) of the U(Cb) plane or the interleaved UV plane if Interleave Chroma is enabled. For + non planar surfaces this field specifies the horizontal offset in pixels from the Surface Base Address to + the start (origin) of the surface + Programming Notes + For PLANAR_420 and PLANAR_422 surface formats, this field must indicate an even number of + pixels. + 15 Reserved + Format: MBZ + 14:0 Y Offset for U(Cb) + Format: U15 Row Offset + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 90 + MEDIA_SURFACE_STATE + For Planar surfaces this field specifies the vertical offset in rows from the Surface Base Address to the + start (origin) of the U(Cb) plane or the interleaved UV plane if Interleave Chroma is enabled. For non + planar surfaces this field specifies the vertical offset in pixels from the Surface Base Address to the + start (origin) of the surface + Programming Notes Project + This field must indicate an even number (bit 0 = 0). +4 31:30 Reserved + Project: All + Format: MBZ + 29:16 X Offset for V(Cr) + Format: U14 Pixel Offset + + + + + Programming Notes + For PLANAR_420 and PLANAR_422 surface formats, this field must indicate an even number of + pixels. + 15 Reserved + Project: All + Format: MBZ + 14:0 Y Offset for V(Cr) + Format: U15 Row Offset + + + This field specifies the veritical offset in rows from the Surface Base Address to the start (origin) of the + V(Cr) plane. This field is only used for PLANAR surface formats with Interleave Chroma disabled. + Value Name + 0,16380 + + + Programming Notes Project + This field must indicate an even number (bit 0 = 0). +5 31:30 Reserved + Project: + Format: MBZ + 29:7 Reserved + Format: MBZ + 6:0 Reserved + + Format: MBZ + + + + +2.12.3 SAMPLER_STATE +SAMPLER_STATE has different formats, depending on the message type used: + +  For , the sample_8x8 and deinterlace messages use a different format of SAMPLER_STATE as + detailed in the corresponding sections. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 91 +  For The Min LOD and Max LOD fields need range increased from [0.0,13.0] to [0.0,14.0] and + fractional bits increased from 6 to 8. This requires a few fields to be moved as indicated in the text. + +2.12.3.1 Sampler_State for Most Messages + + SAMPLER_STATE + +Exists If: (MessageType != 'Deinterlace') && (MessageType != 'Sample_8x8') +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000 +This is the normal sampler state used by all messages that use SAMPLER_STATE except sample_8x8 and +deinterlace. The sampler state is stored as an array of up to 16 elements, each of which contains the dwords +described here. The start of each element is spaced 4 dwords apart. The first element of the sampler state array is +aligned to a 32-byte boundary. +DWord Bit Description +0 31 Sampler Disable + Project: All + Format: Disable + This field allows the sampler to be disabled. If disabled, all output channels will return 0. + + 30 Reserved + Project: All + Format: MBZ + 29 Texture Border Color Mode + Project: All + Format: U1 enumerated type + + + For some surface formats, the 32 bit border color is decoded differently based on the border color + mode. In addition, the default value of channels not included in the surface may be affected by this + field. Refer to the “Sampler Output Channel Mapping” table for the values of these channels, and for + surface formats that may only support one of these modes. Also refer to the definition of + SAMPLER_BORDER_COLOR_STATE for more details on the behavior of the two modes defined by + this field. + Value Name Description Project + 0h DX10/OGL DX10/OGL mode for interpreting the border color All + 1h DX9 DX9 and earlier mode for interpreting the border color All + + + Programming Notes + If this bit changes for a given map with surface format R8G8_SNORM or R16_FLOAT, there must be + two different SURFACE_STATE pointers for Texture Border Color Mode = 0 and 1. This is done to + prevent an aliasing problem in the L1 cache with the default value for the missing channels changing. + Alternately there could be a flush every time this changes. + This field must be set to DX9 mode when used with surfaces that have Surface Format P4A4_UNORM + or A4P4_UNORM. + This field must be set to DX10/OGL mode when used with surfaces that have Surface Format + YCRCB_SWAPUV or YCRCB_SWAPY. + This field must be set to DX10/OGL mode if Surface Format for the associated surface is UINT OR + SINT. + This field must be set to DX10/OGL mode if REDUCTION_MINIMUM or REDUCTION_MAXIMUM or + message type is sample_min or sample_max. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 92 + SAMPLER_STATE + This field must be set to DX10/OGL mode if either Min or Mag Mode Filter is set to + MAPFILTER_FLEXIBLE. + 28 LOD PreClamp Enable + + Format: U1 enumerated type + + + + When enabled, the computed LOD is clamped to [max,min] mip level before the mag-vs-min + determination is performed. This is how the OpenGL API currently performs min/mag determination, + and therefore it is expected that an OpenGL driver would need to set this bit. + Value Name Description + 1h OGL OGL Mode (LOD PreClamp enabled) + 27 Reserved + + Format: MBZ + 26:22 Base Mip Level + + Format: U4.1 + + + Range: [0.0, 14.0] + Specifies which mip level is considered the “base” level when determining mag-vs-min filter and + selecting the “base” mip level. + 21:20 Mip Mode Filter + Project: All + Format: U2 enumerated type + + + This field determines if and how mip map levels are chosen and/or combined when texture filtering. + Value Name Description Project + 0h MIPFILTER_NONE Disable mip mapping – force use of the mipmap level All + corresponding to Min LOD. + 1h MIPFILTER_NEAREST Nearest, Select the nearest mip map All + 2h Reserved All + 3h MIPFILTER_LINEAR Linearly interpolate between nearest mip maps (combined with All + linear min/mag filters this is analogous to “Trilinear” filtering). + + + Programming Notes + MIPFILTER_LINEAR is not supported for surface formats that do not support “Sampling Engine + Filtering” as indicated in the Surface Formats table unless using the sample_c message type or + minimum/maximum operation. + 19:17 Mag Mode Filter + Project: All + Format: U2 enumerated type + + + This field determines how texels are sampled/filtered when a texture is being “magnified” (enlarged). + For volume maps, this filter mode selection also applies to the 3rd (inter-layer) dimension. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 93 + SAMPLER_STATE + Value Name Description Project + 0h MAPFILTER_NEAREST Sample the nearest texel All + 1h MAPFILTER_LINEAR Bilinearly filter the 4 nearest texels All + 2h MAPFILTER_ANISOTROPIC Perform an “anisotropic” filter on the chosen mip level All + 4h-5h Reserved All + 6h MAPFILTER_MONO Perform a monochrome convolution filter All + 7h Reserved All + + + Programming Notes + Only MAPFILTER_NEAREST and MAPFILTER_LINEAR are supported for surfaces of type + SURFTYPE_3D. + Only MAPFILTER_NEAREST is supported for surface formats that do not support “Sampling Engine + Filtering” as indicated in the Surface Formats table unless using the sample_c message type or + minimum/maximum operation. + MAPFILTER_MONO: Only CLAMP_BORDER texture addressing mode is supported. . Both Mag + Mode Filter and Min Mode Filter must be programmed to MAPFILTER_MONO. Mip Mode Filter must + be MIPFILTER_NONE. Only valid on surfaces with Surface Format MONO8 and with Surface Type + SURFTYPE_2D. + MAPFILTER_FLEXIBLE: The Surface Type of the surface being sampled must be SURFTYPE_2D. + MAPFILTER_ANISOTROPIC may cause artifacts at cube edges if enabled for cube maps with the + TEXCOORDMODE_CUBE addressing mode. + MAPFILTER_ANISOTROPIC will be overridden to MAPFILTER_LINEAR when using a sample_l or + sample_l_c message type or when Force LOD to Zero is set in the message header. + + + Errata Description Project + MAPFILTER_ANISOTROPIC may have data corruption when sampled from surface + with BC6H_UF16 or BC6H_SF16 + 16:14 Min Mode Filter + Project: All + Format: U2 enumerated type + + + This field determines how texels are sampled/filtered when a texture is being “minified” (shrunk). For + volume maps, this filter mode selection also applies to the 3rd (inter-layer) dimension.See Mag Mode + Filter + + 13:1 Texture LOD Bias + Project: All + Format: S4.8 2’s complement + + + + + Range: [-16.0, 16.0) + This field specifies the signed bias value added to the calculated texture map LOD prior to min-vs-mag + determination and mip-level clamping. Assuming mipmapping is enabled, a positive LOD bias will + result in a somewhat blurrier image (using less-detailed mip levels) and possibly higher performance, + while a negative bias will result in a somewhat crisper image (using more-detailed mip levels) and may + lower performance. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 94 + SAMPLER_STATE + + Programming Notes + There is no requirement or need to offset the LOD Bias in order to produce a correct LOD for texture + filtering (as was required for correct bilinear and anisotropic filtering in some legacy devices). + 0 Anisotropic Algorithm + Project: All + Format: U1 enumerated type + + + Controls which algorithm is used for anisotropic filtering. Generally, the EWA approximation algorithm + results in higher image quality than the legacy algorithm. + Value Name Description Project + 0h LEGACY Use the legacy algorithm for anisotropic filtering All + 1h EWA Approximation Use the new EWA approximation algorithm for anisotropic filtering All +1 31:20 Min LOD + Project: All + Format: U4.8 in LOD units + + + + + Range: [0.0, 14.0], where the upper limit is also bounded by the Max LOD. + This field specifies the minimum value used to clamp the computed LOD after LOD bias is applied. + Note that the minification-vs.-magnification status is determined after LOD bias and before this + maximum (resolution) mip clamping is applied.The integer bits of this field are used to control the + “maximum” (highest resolution) mipmap level that may be accessed (where LOD 0 is the highest + resolution map). The fractional bits of this value effectively clamp the inter-level trilinear blend factor + when trilinear filtering is in use. + + + Programming Notes + If Min LOD is greater than Max LOD, Min LOD takes precedence, i.e. the resulting LOD will always be + Min LOD. + This field must be zero if the Min or Mag Mode Filter is set to MAPFILTER_MONO + 19:8 Max LOD + Project: All + Format: U4.8 in LOD units + + + + + Range: [0.0, 14.0] + This field specifies the maximum value used to clamp the computed LOD after LOD bias is applied. + Note that the minification-vs.-magnification status is determined after LOD bias and before this + minimum (resolution) mip clamping is applied.The integer bits of this field are used to control the + “minimum” (lowest resolution) mipmap level that may be accessed.The fractional bits of this value + effectively clamp the inter-level trilinear blend factor when trilinear filtering is in use.Force the mip map + access to be between the mipmap specified by the integer bits of the Min LOD and the ceiling of the + value specified here. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 95 + SAMPLER_STATE + 7:4 Reserved + + Format: MBZ + 3:1 Shadow Function + Project: All + Format: U3 enumerated type + + + This field is used for shadow mapping support via the sample_c message type, and specifies the + specific comparison operation to be used. The comparison is between the texture sample red channel + (except for alpha-only formats which use the alpha channel), and the “ref” value provided in the input + message. + Value Name Project + 0h PREFILTEROP_ALWAYS All + 1h PREFILTEROP_NEVER All + 2h PREFILTEROP_LESS All + 3h PREFILTEROP_EQUAL All + 4h PREFILTEROP_LEQUAL All + 5h PREFILTEROP_GREATER All + 6h PREFILTEROP_NOTEQUAL All + 7h PREFILTEROP_GEQUAL All + 0 Cube Surface Control Mode + Project: All + Format: U1 enumerated type + + + When sampling from a SURFTYPE_CUBE surface, this field controls whether the TC* Address Control + Mode fields are interpreted as programmed or overridden to TEXCOORDMODE_CUBE. + Value Name Project + 0h CUBECTRLMODE_PROGRAMMED All + 1h CUBECTRLMODE_OVERRIDE All + + + Programming Notes + This field must be set to CUBECTRLMODE_PROGRAMMED +2 31:5 Border Color Pointer + + Format: DynamicStateOffset[31:5] + + + Description Project + This field specifies the pointer to SAMPLER_BORDER_COLOR_STATE, which contains the + “border” color to be used when accessing texels not contained within the texture map. + This pointer is relative to the Dynamic State Base Address. + Field definition if Flexible Filter Mode = FLEX_NONSEP: + + + Errata Description Project + In order to ensure correct data sampling, it must be ensured that the bits of this field with + three LSBs of zero appended do not match the offset (without base address added) of + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 96 + SAMPLER_STATE + any instance of BINDING_TABLE_STATE (includes each 32-bit entry) used by the + sampling engine between texture cache invalidations. + 4:0 Reserved + + Format: MBZ +3 31:26 Reserved + + Format: MBZ + 25 ChromaKey EnableFormat: Enable + This field enables the chroma key function. + Programming Notes + Supported only on a specific subset of surface formats. See section “Surface Formats” for supported + formats.This field must be disabled if min or mag filter is MAPFILTER_MONO or + MAPFILTER_ANISOTROPIC.This field must be disabled if used with a surface of type + SURFTYPE_3D. + 24:23 ChromaKey Index + + Format: U2 + This field specifies the index of the ChromaKey Table entry associated with this Sampler. This field is a + “don’t care” unless ChromaKey Enable is ENABLED. + Value Name + [0,3] + 22 ChromaKey Mode + + Format: U1 Enumerated Type + + + This field specifies the behavior of the device in the event of a ChromaKey match. This field is ignored + if ChromaKey is disabled.KEYFILTER_KILL_ON_ANY_MATCH:In this mode, if any contributing texel + matches the chroma key, the corresponding pixel mask bit for that pixel is cleared. The result of this + operation is observable only if the Killed Pixel Mask Return flag is set on the input message. + KEYFILTER_REPLACE_BLACK:In this mode, each texel that matches the chroma key is replaced with + (0,0,0,0) (black with alpha=0) prior to filtering. For YCrCb surface formats, the black value is A=0, + R(Cr)=0x80, G(Y)=0x10, B(Cb)=0x80. This will tend to darken/fade edges of keyed regions. Note that + the pixel pipeline must be programmed to use the resulting filtered texel value to gain the intended + effect, e.g., handle the case of a totally keyed-out region (filtered texel alpha==0) through use of alpha + test, etc. + Value Name Project + 0h KEYFILTER_KILL_ON_ANY_MATCH All + 1h KEYFILTER_REPLACE_BLACK All + 21:19 Maximum Anisotropy + Project: All + Format: U3 enumerated type + + + This field clamps the maximum value of the anisotropy ratio used by the MAPFILTER_ANISOTROPIC + filter (Min or Mag Mode Filter). + Value Name Description Project + 0h ANISORATIO_2 At most a 2:1 aspect ratio filter is used All + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 97 + SAMPLER_STATE + 1h ANISORATIO_4 At most a 4:1 aspect ratio filter is used All + 2h ANISORATIO_6 At most a 6:1 aspect ratio filter is used All + 3h ANISORATIO_8 At most a 8:1 aspect ratio filter is used All + 4h ANISORATIO_10 At most a 10:1 aspect ratio filter is used All + 5h ANISORATIO_12 At most a 12:1 aspect ratio filter is used All + 6h ANISORATIO_14 At most a 14:1 aspect ratio filter is used All + 7h ANISORATIO_16 At most a 16:1 aspect ratio filter is used All + 18:13 Address Rounding Enable + Project: All + Format: 6-bit mask of enables + + + Controls whether the U/V/R texture address is rounded or truncated before being used to select texels + to sample. Each bit provides independent control of rounding on one texture address dimension + (U/V/R) in either mag or min filter mode. + Value Name + 1xxxxxb U address mag filter + x1xxxxb U address min filter + xx1xxxb V address mag filter + xxx1xxb V address min filter + xxxx1xb R address mag filter + xxxxx1b R address min filter + + + Programming Notes Project + Hardware will force rounding enable to 0 when message is gather4, gather4_po, gather4_c, + or gather4_po_c. + 12:11 Trilinear Filter Quality + Project: All + Format: U2 enumerated type + + + Selects the quality level for the trilinear filter. + Value Name Description Project + 0 TRIQUAL_FULL Full Quality. Both mip maps are sampled under all circumstances. All + 2 TRIQUAL_MED Medium Quality. If the contribution of one mip map is less than 25%, All + only the other mip map contributes. + 3 TRIQUAL_LOW Low Quality. If the contribution of one mip map is less than 37.5%, only All + the other mip map contributes. + 10 Non-normalized Coordinate Enable + Project: All + Format: Enable + This field, if enabled, specifies that the input coordinates (U/V/R) are in non-normalized space, where + each integer increment is one texel on LOD 0. If disabled, coordinates are normalized, where the range + 0 to 1 spans the entire surface. + Programming Notes + + The following state must be set as indicated if this field is enabled: +  TCX/Y/Z Address Control Mode must be TEXCOORDMODE_CLAMP, + TEXCOORDMODE_HALF_BORDER, or TEXCOORDMODE_CLAMP_BORDER. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 98 + SAMPLER_STATE +  Surface Type must be SURFTYPE_2D or SURFTYPE_3D. +  Mag Mode Filter must be MAPFILTER_NEAREST or MAPFILTER_LINEAR. +  Min Mode Filter must be MAPFILTER_NEAREST or MAPFILTER_LINEAR. +  Mip Mode Filter must be MIPFILTER_NONE. +  Min LOD must be 0. +  Max LOD must be 0. +  MIP Count must be 0. +  Surface Min LOD must be 0. +  Texture LOD Bias must be 0. + + 9 Reserved + + Format: MBZ + 8:6 TCX Address Control Mode + Project: All + Format: U3 enumerated type + + + Controls how the 1st (TCX, aka U) component of input texture coordinates are mapped to texture map + addresses – specifically, how coordinates “outside” the texture are handled (wrap/clamp/mirror). The + setting of this field is subject to being overridden by the Cube Surface Control Mode field when + sampling from a SURFTYPE_CUBE surface. + Value Name Description Project + 0h TEXCOORDMODE_WRAP Map is repeated in the U direction All + 1h TEXCOORDMODE_MIRROR Map is mirrored in the U direction All + 2h TEXCOORDMODE_CLAMP Map is clamped to the edges of the accessed All + map + 3h TEXCOORDMODE_CUBE For cube-mapping, filtering in edges access All + adjacent map faces + 4h TEXCOORDMODE_CLAMP_BORDER Map is infinitely extended with the border color All + 5h TEXCOORDMODE_MIRROR_ONCE Map is mirrored once about origin, then clamped All + 7h Reserved All + + + Programming Notes Project + When using cube map texture coordinates, only TEXCOORDMODE_CLAMP and + TEXCOORDMODE_CUBE settings are valid, and each TC component must have the same + Address Control mode. + When TEXCOORDMODE_CUBE is not used accessing a cube map, the map’s Cube Face + Enable field must be programmed to 111111b (all faces enabled). + MAPFILTER_MONO: Texture addressing modes must all be set to + TEXCOORDMODE_CLAMP_BORDER. The Border Color is ignored in this mode, a constant + value of 0 is used for border color. Software must pad the border texels within the map itself + with 0. + 5:3 TCY Address Control Mode + Project: All + Format: U3 enumerated type + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 99 + SAMPLER_STATE + + Controls how the 2nd (TCY, aka V) component of input texture coordinates are mapped to texture map + addresses – specifically, how coordinates “outside” the texture are handled (wrap/clamp/mirror). See + Address TCX Control Mode above for details + Programming Notes + If this field is set to TEXCOORDMODE_CLAMP_BORDER or TEXCOORDMODE_HALF_BORDER + and a 1D surface is sampled, incorrect blending with the border color in the vertical direction may + occur. + 2:0 TCZ Address Control Mode + Project: All + Format: U3 enumerated type + + + + + Description Project + Controls how the 3rd (TCZ) component of input texture coordinates are mapped to texture map + addresses – specifically, how coordinates “outside” the texture are handled + (wrap/clamp/mirror).See Address TCX Control Mode above for details + If this field is set to TEXCOORDMODE_CLAMP_BORDER for 3D maps on formats without an + alpha channel, samples straddling the map in the Z direction may have their alpha channels off + by 1. + + + + 2.12.3.2 SAMPLER_STATE for Sample_8x8 Message + + SAMPLER_STATE for Sample_8x8 Message + + Default Value: 0x00000000, 0x00000000, 0x0D090801, 0x721A03C6 + . This state definition is used only by the sample_8x8 message. This state is stored as an array of up to 16 elements, + each of which contains the dwords described here. The start of each element is spaced 4 dwords apart. The first + element of the array is aligned to a 32-byte boundary. + The index with range 0-15 that selects which element is being used to determine the Sampler Index in the message + descriptor. + Programming Notes + + IEF Filter Type was dropped and is assumed to be Detailed filter + + IEF Filter Size was dropped and assumed to be 5x5. + + IEF bypass must always be forced to 1, if Y/G-channel is masked. + + + DWord Bit Description + 0 31:30 Reserved + Format: MBZ + 29 IEF Bypass + Format: MBZ + + + + + Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 100 + SAMPLER_STATE for Sample_8x8 Message + Causes IEF function to be bypassed, VSA will output neutral values. + + 28:19 Reserved + Format: MBZ + 18 ChromaKey Enable + Format: Enable + This field enables chroma keying when accessing this particular texture map. + Programming Notes + +  + For sample_8x8 instructions KEYFILTER_REPLACE_BLACK is assumed if chromakey is + enabled. +  + For 10 bit formats only the 8 MSBs will be compared. + + 17:16 ChromaKey Index + Format: U2 + This field specifies the index of the ChromaKey Table entry associated with this Sampler. This field + is a “don’t care” unless ChromaKey Enable is ENABLED. + Value Name + [0,3] + 15:8 Reserved + Format: MBZ + 7:0 Global Noise Estimation + Format: U8 + Global noise estimation of previous frame. + +1 31:5 Sampler 8x8 State Pointer + + Format: DynamicStateOffset[31:5] + This field specifies the pointer to the SAMPLER_8x8_STATE structure. This pointer is relative to the + Dynamic State Base Address. + Programming Notes +  + This field must be set to the same value in all sample_8x8 type SAMPLER_STATE instances + applied to a given primitive. +  + PIPE_CONTROL with State/Instruction Cache Invalidate set and the CS Stall field set is required + between primitives that use different values of this field. + + 4:0 Reserved + Format: MBZ +2 31 Reserved + Format: MBZ + 30:26 R5c Coefficient + Default Value: 3 + Format: U0.5 + IEF smoothing coefficient, see IEF map. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 101 + SAMPLER_STATE for Sample_8x8 Message + 25:21 R5x Coefficient + Default Value: 8 + Format: U0.5 + IEF smoothing coefficient, see IEF map. + + 20:16 R5c Coefficient + Default Value: 9 + Format: U0.5 + IEF smoothing coefficient, see IEF map. + + 15:14 Reserved + Format: MBZ + 13:8 Strong Edge Threshold + Default Value: 8 + Format: U6 + If EM > Strong Edge Threshold, the basic VSA detects a strong edge. + + 7:6 Reserved + Format: MBZ + 5:0 Weak Edge Threshold + Default Value: 1 + Format: U6 + If Strong Edge Threshold > EM > Weak Edge Threshold, the basic VSA detects a weak edge. + +3 31 IEF4Smooth Enable + Value Name Description + 1 IEF is operating as a content adaptive smooth filter based on 3x3 region + 0 [Default] IEF is operating as a content adaptive detail filter based on 5x5 region + 30:28 Strong Edge Weight + Default Value: 7 + Format: U3 + Sharpening strength when a strong edge is found in basic VSA.. + + 27 Reserved + Format: MBZ + 26:24 Regular Weight + Default Value: 2 + Format: U3 + Sharpening strength when a weak edge is found in basic VSA. + + 23 Reserved + Format: MBZ + 22:20 Non Edge Weight + Default Value: 1 + Format: U3 + Sharpening strength when no edge is found in basic VSA. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 102 + SAMPLER_STATE for Sample_8x8 Message + 19:14 Gain Factor + Default Value: 40 + Format: U6 + User control sharpening strength. + + 13:11 Reserved + Format: MBZ + 10:6 R3c Coefficient + Default Value: 15 + Format: 0.5 + IEF smoothing coefficient, see IEF map. + + 5 Reserved + Format: MBZ + 4:0 R3x Coefficient + Default Value: 6 + Format: U6 + IEF smoothing coefficient, see IEF map. + + + + +2.12.3.3 For Deinterlace Message + + DEINTERLACE_SAMPLER_STATE + +Exists If: MessageType == 'Deinterlace' +Default 0x00000800, 0x00000000, 0x04950100, 0x407D0000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x005064A5 +This state definition is used only by the deinterlace message. This state is stored as an array of up to 8 elements, +each of which contains the dwords described here. The start of each element is spaced 8 dwords apart. The first +element of the array is aligned to a 32-byte boundary. The index with range 0-7 that selects which element is being +used is multiplied by 2 to determine the Sampler Index in the message descriptor. +DWord Bit Description +0 31:24 Denoise STAD Threshold + Threshold for denoise sum of temporal absolute differences. + 23:16 Denoise Maximum History + Maximum allowed value for denoise history. + Value Name Description + 128-240 + 15 Reserved + Format: MBZ + 14 VDI Walker Frame Sharing Enable + Format: U1 enumerated type + + + For a GT2 system with 2 half-slices, this field controls how the frame is shared by the two deinterlacer + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 103 + DEINTERLACE_SAMPLER_STATE + walkers. + Value Name + 0 There is only a single deinterlacer which must walk the entire frame. VDI Walker Y Stride is + ignored. + 1 The screen is shared by the two deinterlacers as controlled by the VDI Walker Y Stride + 13:12 VDI Walker Y Stride + Format: U2 enumerated type + + + This field controls if the VDI walker skips pixels as it goes down the screen. This is used when a pair + of VDI'S are splitting the frame between them. The stride also implies the offset used by the 2nd half- + slice. + Value Name + 0 Stride of 1 block (where a block is 4x4 when DI is enabled and 4x8 when DN only), offset for + the 2nd half-slice is � the surface height. + 1 Stride of 2 blocks (every other row of blocks calculated by this VDI), offset for the 2nd half-slice + is 1 block. + 2 Stride of 4 blocks (2 vertical blocks calclated by this VDI, then skip 2), offset for the 2nd half- + slice is 2 blocks. + 3 Stride of 8 blocks (4 vertical blocks calculated by this VDI, then skip 4), offset for the 2nd half- + slice is 4 blocks. + 11:8 Denoise History Delta + Default Value: 8 + Amount that denoise_history is increased. + + 7:0 Denoise ASD Threshold + Threshold for denoise absolute sum of differences. + Value Name Description + 0-63 +1 31:30 Reserved + Format: MBZ + 29:24 Temporal Difference Threshold + Programming Notes + The difference between Temporal Difference Threshold and Low Temporal Difference Threshold + must be larger than 0 and less than or equal to 16, except when both thresholds are set to 0. + 23:22 Reserved + Format: MBZ + 21:16 Low Temporal Difference Threshold + Programming Notes + The difference between Temporal Difference Threshold and Low Temporal Difference Threshold + must be larger than 0 and less than or equal to 16, except when both thresholds are set to 0. + 15:13 STMM C2 + Bias for divisor in STMM equation. The range represents values [1,8] + Value Name Description + 0-7 + 12:8 Denoise Moving Pixel Threshold + Threshold for number of moving pixels to declare a block to be moving. + Value Name Description + 0-16 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 104 + DEINTERLACE_SAMPLER_STATE + 7:0 Denoise Threshold for Sum of Complexity Measure +2 31:30 Reserved + Format: MBZ + 29:24 Good Neighbor Threshold + Maximum difference from current pixel for neighboring pixels to be considered a good neighbor. + Value Name Description + 4 [Default] depending on GNE of previous frame + 23:20 CAT Slope + Format: U4-1 + Determines the slope of the Content Adaptive Threshold. +1 added internally to get CAT_slope. + Value Name Description + 9 [Default] CAT_slope value = 10 + 19:16 SAD Tight Threshold + Default Value: 5 + Format: U4 + 15:14 Smooth MV Threshold + Format: U2 + 13:12 Reserved + Format: MBZ + 11:8 BNE Edge Threshold + Default Value: 1 + Format: U4 + Threshold for detecting an edge in block noise estimate. + + 7:0 Block Noise Estimate Noise Threshold + Format: U8 + Threshold for noise maximum/minimum. + Value Name Description + 0-31 +3 31 STMM Blending Constant Select + Format: U1 + + + Value Name + 0 Use Minimum STMM for stmm_md_th + 1 Use Maximum STMM for stmm_md_th + 30:24 Blending constant across time for large values of STMM + Default Value: 64 + Format: U7 + 23:16 Blending constant across time for small values of STMM + Default Value: 125 + Format: U8 + 15:14 Reserved + Format: MBZ + 13:8 Multiplier for VECM + Format: U6 + Determines the strength of the vertical edge complexity measure. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 105 + DEINTERLACE_SAMPLER_STATE + + 7:0 Maximum STMM + Format: U8 + Largest allowed STMM in blending equations + +4 31:24 Minimum STMM + Format: U8 + Smallest allowed STMM in blending equations + + 23:22 STMM Shift Down + Format: U2 + Amount to shift STMM down (quantize to fewer bits) + Value Name + 0 Shift by 4 + 1 Shift by 5 + 2 Shift by 6 + 3 Reserved + 21:20 STMM Shift Up + Format: U2 + Amount to shift STMM up (set range). + Value Name + 0 Shift by 6 + 1 Shift by 7 + 2 Shift by 8 + 3 Reserved + 19:16 STMM Output Shift + Format: U4 + Amount to shift output of STMM blend equation + Value Name Description + 0-16 + + + Programming Notes + The value of this field must satisfy the following equation: stmm_max – stmm_min = 2 ^ + stmm_output_shift + 15:8 SDI Threshold + Format: U8 + Threshold for angle detection in SDI algorithm. + + 7:0 SDI Delta + Format: U8 + Delta value for angle detection in SDI algorithm. + +5 31:24 SDI Fallback Mode 1 T1 Constant + Format: U8 + 23:16 SDI Fallback Mode 1 T2 Constant + Format: U8 + 15:8 SDI Fallback Mode 2 Constant (Angle2x1) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 106 + DEINTERLACE_SAMPLER_STATE + Format: U8 + 7:0 FMD Temporal Difference Threshold + Format: U8 +6 31:24 FMD #1 Vertical Difference Threshold + Format: U8 + 23:16 FMD #2 Vertical Difference Threshold + Format: U8 + 15:14 CAT Threshold 1 + Default Value: 0 + Format: U2 + 13:8 FMD Tear Threshold + Format: U6 + 7 MCDI Enable + Use Motion Compensated Deinterlace algorithm. + Ignored if DI Enable is off. + 6 Progressive DN + Format: Enable + Indicates that the denoise algorithm should assume progressive input when filtering neighboring + pixels. DI Enable must be disabled when this field is enabled + Value Name + 0 DN assumes interlaced video and filters alternate lines together + 1 DN assumes progressive video and filters neighboring lines together + 5 DN/DI First Frame + Format: Enable + Indicates that this is the first frame of the stream, so previous clean is not available + Value Name + 0 Not first field; previous clean surface state is valid + 1 First field; previous clean surface state is invalid + 4 DN/DI Stream ID + Format: U1 + Distinguishes between the two simultaneous streams that are supported. Used to update the GNE and + FMD counters for that stream. + + 3 DN/DI Top First + Format: Enable + Indicates the top field is first in sequence, otherwise bottom is first + Value Name + 0 Bottom field occurs first in sequence + 1 Top field occurs first in sequence + 2 DI Partial + Format: Enable + If DI Enable and DI Partial are both enabled, the deinterlacer will output the partial VDI writeback + message. + Value Name + 0 Output normal VDI writeback message (only if DI Enable is enabled also) + 1 Output partial VDI writeback message (only if DI Enable is enabled also) + 1 DI Enable + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 107 + DEINTERLACE_SAMPLER_STATE + Format: Enable + Deinterlacer is bypassed if this is disabled: the output is the same as the input (same as a 2:2 + cadence). FMD and STMM are not calculated and the values in the response message are 0. + Value Name + 0 Do not calculate DI + 1 Calculate DI + + + Programming Notes + DI Enable and DN Enable cannot both be disabled + 0 DN Enable + Format: Enable + Denoise is bypassed if this is low � BNE is still calculated and output, but the denoised fields are not. + VDI does not read in the denoised previous frame but uses the pointer for the original previous frame. + Value Name + 0 Do not denoise frame + 1 Denoise frame + + + Programming Notes + DI Enable and DN Enable cannot both be disabled +7 31:23 Column Width Minus 1 + Format: U9 + This field specifies the (column width-1) / stride in units of blocks (Each blocks has width 16 pixels). + A column width * 16 that equals the width of the frame means the walker will walk to the end of the + frame. + The value of this field is interpreted as binary value + 1, so the range represents column widths of + [1,512]. + Value Name Description + 0-511 + 22:19 Neighbor Pixel Threshold + Default Value: 10 + Format: U4 + 18 VDI Walker Enable + Format: U1 + + + Value Name + 0 Walker Disabled. Use XY generated by Driver. + 1 Walker Enabled. Use XY generated by VDIunit. + + + Programming Notes + When enabled frame size should be aligned to 16x8 in DN only mode and 16x4 in DI enabled mode + When walker is enabled in a GT2 system, the MEDIA_OBJECT commands dispatching work to the + VDI must use the Half-Slice Destination Select field to split the work between the two half-slices; the + Half-Slice Destination Select must never be set to 00 (either half-slice). + 17:16 FMD for 2nd field of previous frame + Format: U2 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 108 + DEINTERLACE_SAMPLER_STATE + + Value Name + 0 Deinterlace (not progressive output) + 1 Put together with previous field in sequence (1st field of previous frame) + 2 Put together with next field in sequence (1st field of current frame) + 15:10 MC Pixel Consistency Threshold + Default Value: 25 + Format: U6 + 9:8 FMD for 1st field of current frame + Format: U2 + + + Value Name + 0 Deinterlace (not progressive output) + 1 Put together with previous field in sequence (2nd field of previous frame) + 2 Put together with next field in sequence (2nd field of current frame) + 7:4 SAD Threshold B + Default Value: 10 + Format: U4 + 3:0 SAD Threshold A + Default Value: 5 + Format: U4 + + + + This state definition is used only by the deinterlace message. This state is stored as an array of up to 8 +elements, each of which contains the dwords described here. The start of each element is spaced 8 +dwords apart. The first element of the array is aligned to a 32-byte boundary. The index with range 0-7 +that selects which element is being used is multiplied by 2 to determine the Sampler Index in the +message descriptor. + +2.12.3.3.1 Restrictions +1. VDIWalker can be enabled only when frame is aligned to block size of 16x4 if DI is enabled + (interlaced) and 16x8 if DN only (Progressive). +2. When VDIWalker Frame Sharing is enabled driver should dispatch same number of Media Objects + to both half slice by explicitly programming half slice destination select as 01 and 10 alternately + (Note: Dispatch of threads should be in ping pong fashion to have load balance between both + Halfslice and better L3 utilization). +3. For VDIWalker disabled mode (when frame size is not aligned to 16x4 or 16x8) it is recommended to + have a simplified SW walker. Using Half Slice Destination Select 00 will affect performance + significantly. + +2.12.3.3.2 Dispatch of Media Object Commands for VDIWalker Enabled +1. Frame Sharing is Disabled: + a. Program all MO commands to have Half Slice destination select as either “01” or “10” + b. Y_stride programmed in Sampler State will be ignored + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 109 + 2. Frame Sharing Enabled: + a. if Frame_height (in blocks) % 2 = 0 (where block height = 4 when DI enabled, 8 when DN only) + dispatch MO in ping pong fashion + b. Y_Stride of 0,1,2,3 is valid and VDIwalker will divide frame into multiple slices based on stride + value + c. if Frame_height (in blocks) % 2 > 0, then dispatch MO in ping pong fashion and all threads for + blocks from residual row to be sent to Half Slice0 + +2.12.3.3.3 Psuedo Code for Media Object Dispatch +//Variables +Frame Height in pixels => frame_height +Frame Width in pixels => frame_width +Frame Height in Blocks => fh +Frame Width in Blocks => fw +Block Height in Pixels => block_height = Interlaced? 4 : 8 + + +//Code +fw = frame_width / 16; +fh = frame_height / block_height; + + +2.12.3.3.4 Calculate Residual Blocks +If ( fh % (2**stride) ) ≠ 0 { + Y_Blocks_Remainder = (fh % (2**stride)) + If (Y_Blocks_Remainder > (2**stride) / 2) { + + + Y_Blocks_Remainder_HS1 = (2**stride) / 2 + Y_Blocks_Remainder_HS2 = Y_Blocks_Remainder - (2**stride) / 2 + } + Else { + Y_Blocks_Remainder_HS1 = Y_Blocks_Remainder + Y_Blocks_Remainder_HS2 = 0 + } +} +Else { + Y_Blocks_Remainder_HS1 = 0 + Y_Blocks_Remainder_HS2 = 0 +} + + +2.12.3.3.5 Dispatch Media Object +total_media_obj_cnt = fw * fh; +reminder_media_obj_cnt_HS1 = fw * Y_Blocks_Remainder_HS1; +reminder_media_obj_cnt_HS2 = fw * Y_Blocks_Remainder_HS2; + + +ping_pong_media_obj_cnt = +total_media_obj_cnt – (reminder_media_obj_cnt_HS1 + reminder_media_obj_cnt_HS1); + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 110 + for ( i = 0; i < ping_pong_media_obj_cnt; i++) { + if ( i % 2 == 0) { + dispatch_media_object_hs1; + } + else { + dispatch_media_object_hs2; + } +} + + +for ( i = 0; i < reminder_media_obj_cnt_HS1; i++) { + dispatch_media_object_hs1; +} + + +for ( i = 0; i < reminder_media_obj_cnt_HS2; i++) { + dispatch_media_object_hs2; +} + + +2.12.4 SAMPLER_8x8_STATE + + SAMPLER_8x8_STATE + +Exists If: MessageType == 'Sample_8x8' +Default 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +The 8x8 coefficients and other state used by the sample_8x8 message are stored as indirect state, pointed to by a +field in SAMPLER_STATE. There are four different tables loaded using this structure (0X, 0Y, 1X, and 1Y). Each +table is stored as an array of 17 elements, each with either 4 or 8 coefficients. + DWord Bit Description +0 31:24 Table 0X Filter Coefficient[0,3] + Format: S1.6 In 2’s complement format + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 111 + SAMPLER_8x8_STATE + + + + Description Project + Range: [-2.0, +2.0) + 23:16 Table 0X Filter Coefficient[0,2] + Format: S1.6 In 2’s complement format + + + Range: [-1, +1) + + 15:8 Table 0X Filter Coefficient[0,1] + Format: S1.6 In 2’s complement format + + + Range = [-2-1, +2-1) + Programming Notes + Must be zero if the format is R10G10B10A2_UNORM or R8G8B8A8_UNORM. + 7:0 Table 0X Filter Coefficient[0,0] + Format: S1.6 In 2's complement format + + + Range = [-2-2, +2-2) + Programming Notes + Must be zero if the format is R10G10B10A2_UNORM or R8G8B8A8_UNORM +1 31:24 Table 0X Filter Coefficient[0,7] + Format: S1.6 In 2's complement format + + + Range = [-2-2, +2-2) + + 23:16 Table 0X Filter Coefficient[0,6] + Format: S1.6 In 2's complement format + + + Range = [-2-1, +2-1) + + 15:8 Table 0X Filter Coefficient[0,5] + Format: S1.6 In 2's complement format + + + Range: [-1, +1) + + 7:0 Table 0X Filter Coefficient[0,4] + Format: S1.6 In 2's complement format + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 112 + SAMPLER_8x8_STATE + Description Project + Range: [-2.0, +2.0) +2..3 31:24 Table 0Y Filter Coefficient[0,7] + Format: S1.6 In 2's complement format + + + Range = [-2-2, +2-2) + + 23:16 Table 0Y Filter Coefficient[0,6] + Format: S1.6 In 2's complement format + + + Range = [-2-1, +2-1) + + 15:8 Table 0Y Filter Coefficient[0,5] + Format: S1.6 In 2's complement format + + + Range: [-1, +1) + + 7:0 Table 0Y Filter Coefficient[0,4] + Format: S1.6 In 2's complement format + + + + + Description Project + Range: [-2.0, +2.0) +4 31:24 Table 1X Filter Coefficient[0,3] + Format: S1.6 In 2's complement format + + + Range: [0.0, +2.0) + + 23:16 Table 1X Filter Coefficient[0,2] + Format: S1.6 In 2's complement format + + + Range: [-1, +1) + + 15 Adaptive Filter for all channels + Only to be enabled if 8-tap Adaptive filter mode is on. Else it should be disabled. + Value Name + 1 Enable adaptive filter on UV/RB channels + 0 Disable adaptive filter on UV/RB channels + 14 Enable RGB Adaptive for RGB input only : + This should be always set to 0 for YUV input and can be enabled/disabled for RGB input. This + should be enabled only if we enable 8-tap adaptive filter for RGB input + Value Name + 1 Enable the RGB Adaptive filter using the equation (Y=(R+2G+B)>>2) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 113 + SAMPLER_8x8_STATE + 0 Disable the RGB Adaptive equation and use G-Ch directly for adaptive filter + 13:0 Reserved + Format: MBZ +5 31:16 Reserved + Format: MBZ + 15:8 Table 1X Filter Coefficient[0,5] + Format: S1.6 In 2's complement format + + + Range: [-1, +1) + + 7:0 Table 1X Filter Coefficient[0,4] + Format: S1.6 In 2's complement format + + + Range: [0.0, +2.0) + +6..7 31:16 Reserved + Format: MBZ + 15:8 Table 1Y Filter Coefficient[0,5] + Format: S1.6 In 2's complement format + + + Range: [-1, +1) + + 7:0 Table 1Y Filter Coefficient[0,4] + Format: S1.6 In 2's complement format + + + Range: [0.0, +2.0) + +8..15 31:0 Filter Coefficient[1,7:0] +16..23 31:0 Filter Coefficient[2,7:0] +24..31 31:0 Filter Coefficient[3,7:0] +32..39 31:0 Filter Coefficient[4,7:0] +40..47 31:0 Filter Coefficient[5,7:0] +48..55 31:0 Filter Coefficient[6,7:0] +56..63 31:0 Filter Coefficient[7,7:0] +64..71 31:0 Filter Coefficient[8,7:0] +72..79 31:0 Filter Coefficient[9,7:0] +80..87 31:0 Filter Coefficient[10,7:0] +88..95 31:0 Filter Coefficient[11,7:0] +96..103 31:0 Filter Coefficient[12,7:0] +104..111 31:0 Filter Coefficient[13,7:0] +112..119 31:0 Filter Coefficient[14,7:0] +120..127 31:0 Filter Coefficient[15,7:0] +128..135 31:0 Filter Coefficient[16,7:0] +136 31:24 Default Sharpness Level + Format: U8 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 114 + SAMPLER_8x8_STATE + When adaptive scaling is off, determines the balance between sharp and smooth scalers. + Value Name + 0 Contribute 1 from the smooth scalar + 255 Contribute 1 from the sharp scalar + 23:16 Max Derivative 4 Pixels + Format: U8 + Used in adaptive filtering to specify the lower boundary of the smooth 8 pixel area. + + 15:8 Max Derivative 8 Pixels + Format: U8 + Used in adaptive filtering to specify the lower boundary of the smooth 8 pixel area. + + 7 Reserved + Format: MBZ + 6:4 Transition Area with 4 Pixels + Format: U3 + Used in adaptive filtering to specify the width of the transition area for the 4 pixel calculation. + + 3 Reserved + Format: MBZ + 2:0 Transition Area with 8 Pixels + Format: U3 + Used in adaptive filtering to specify the width of the transition area for the 8 pixel calculation. + +137 31:23 Reserved + Format: MBZ + 22 Bypass X Adaptive Filtering + Format: Disable + When disabled, the X direction will use Default Sharpness Level to blend between the smooth + and sharp filters rather than the calculated value. + Value Name + 1 Disable X adaptive filtering + 0 Enable X adaptive filtering + 21 Bypass Y Adaptive Filtering + Format: Disable + When disabled, the Y direction will use Default Sharpness Level to blend between the smooth + and sharp filters rather than the calculated value. + Value Name + 1 Disable X adaptive filtering + 0 Enable X adaptive filtering + 20:2 Reserved + Format: MBZ + 1 Reserved + Project: + Format: MBZ + 0 Reserved + Project: + Format: MBZ + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 115 + 2.12.5 SAMPLER_BORDER_COLOR_STATE + + SAMPLER_BORDER_COLOR_STATE + +Default Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000 +This structure is pointed to by a field in SAMPLER_STATE. The interpretation of the border color depends on the +Texture Border Color Mode field in SAMPLER_STATE as follows:In DX9 mode, the border color is 8-bit UNORM +format, regardless of the surface format chosen. For surface formats with one or more channels missing (i.e. +R5G6R5_UNORM is missing the alpha channel), the value from the border color, if selected, will be used even for +the missing channels.In DX10/OGL mode, the format of the border color is R32G32B32A32_FLOAT, regardless of +the surface format chosen. For surface formats with one or more channels missing, the value from the border color is +not used for the missing channels, resulting in these channels resulting in the overall default value (0 for colors and 1 +for alpha) regardless of whether border color is chosen. The surface formats with “L” and “I” have special behavior +with respect to the border color. The border color value used for the replicated channels (RGB for “L” formats and +RGBA for “I” formats) comes from the red channel of border color. In these cases, the green and blue channels, and +also alpha for “I”, of the border color are ignored.The format of this state depends on the Texture Border Color Mode +field. + Programming Notes +  DX9 mode is not supported for surfaces with more than 16 bits in any channel, other than 32-bit float formats + which are supported. +  The conditions under which this color is used depend on the Surface Type – 1D/2D/3D surfaces use the + border color when the coordinates extend beyond the surface extent; cube surfaces use the border color for + “empty” (disabled) faces. +  The border color itself is accessed through the texture cache hierarchy rather than the state cache hierarchy. + Thus, if the border color is changed in memory, the texture cache must be invalidated and the state cache + does not need to be invalidated. +  MAPFILTER_MONO: The border color is ignored. Border color is fixed at a value of 0 by hardware. + + + DWord Bit Description +0 31:24 Border Color Alpha + Format: UNORM8 + Texture Border Color Mode = DX9 + + 23:16 Border Color Blue + Format: UNORM8 + Texture Border Color Mode = DX9 + + 15:8 Border Color Green + Format: UNORM8 + Texture Border Color Mode = DX9 + + 31:0 Border Color Red + Format: IEEE_FP + Texture Border Color Mode = DX10/OGL + + 7:0 Border Color Red + Format: UNORM8 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 116 + SAMPLER_BORDER_COLOR_STATE + Texture Border Color Mode = DX9 + +1 31:0 Border Color Green + Format: IEEE_FP + Texture Border Color Mode = DX10/OGL + +2 31:0 Border Color Blue + Format: IEEE_FP + Texture Border Color Mode = DX10/OGL + +3 31:0 Border Color Alpha + Format: IEEE_FP + Texture Border Color Mode = DX10/OGL + + + + +2.12.5.1 SAMPLER_BORDER_COLOR_STATE +For, if border color is used, all formats must be provided. Hardware will choose the appropriate format based +on Surface Format and Texture Border Color Mode. The values represented by each format should be +the same (other than being subject to range-based clamping and precision) to avoid unexpected +behavior. +DWord Bit Description + 0 31:24 + Border Color Alpha + Format = UNORM8 + 23:16 + Border Color Blue + Format = UNORM8 + 15:8 + Border Color Green + Format = UNORM8 + 7:0 + Border Color Red + Format = UNORM8 + + 1 31:0 + Border Color Red + Format = IEEE_FP + 2 31:0 + Border Color Green + Format = IEEE_FP + 3 31:0 + Border Color Blue + Format = IEEE_FP + 4 31:0 + Border Color Alpha + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 117 + DWord Bit Description + Format = IEEE_FP + 5 31:16 + Border Color Green + Format = FLOAT16 + + 15:0 + Border Color Red + Format = FLOAT16 + 6 31:16 + Border Color Alpha + Format = FLOAT16 + 15:0 + Border Color Blue + Format = FLOAT16 + 7 31:16 + Border Color Green + Format = UNORM16 + + 15:0 + Border Color Red + Format = UNORM16 + 8 31:16 + Border Color Alpha + Format = UNORM16 + 15:0 + Border Color Blue + Format = UNORM16 + 9 31:16 + Border Color Green + Format = SNORM16 + 15:0 + Border Color Red + Format = SNORM16 + 10 31:16 + Border Color Alpha + Format = SNORM16 + 15:0 + Border Color Blue + Format = SNORM16 + + 11 31:24 + Border Color Alpha + Format = SNORM8 + 23:16 + Border Color Blue + Format = SNORM8 + 15:8 + Border Color Green + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 118 + DWord Bit Description + Format = SNORM8 + 7:0 + Border Color Red + Format = SNORM8 + + + +2.12.6 3DSTATE_CHROMA_KEY + + 3DSTATE_CHROMA_KEY +Project: All +Source: RenderCS +Length Bias: 2 +The 3DSTATE_CHROMA_KEY instruction is used to program texture color/chroma-key key values. A table +containing four set of values is supported. The ChromaKey Index sampler state variable is used to select which table +entry is associated with the map. Texture chromakey functions are enabled and controlled via use of the ChromaKey +Enable texture sampler state variable.Texture Color Key (keying on a paletted texture index) is not supported. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: Opcode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: Opcode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE + Format: Opcode + 23:16 3D Command Sub Opcode + Default Value: 04h 3DSTATE_CHROMA_KEY + Format: Opcode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 2h Excludes DWord (0,1) + Format: =n + Total Length - 2 + +1 31:30 ChromaKey Table Index + Project: All + Format: U2 index + + + Selects which entry in the ChromaKey table is to be loaded + Value Name + [0,3] + 29:0 Reserved + Project: All + Format: MBZ + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 119 + 3DSTATE_CHROMA_KEY +2 31:0 ChromaKey Low Value + This field specifies the “low” (minimum) value of the chroma key range. Texel samples are considered + “matching the key” if each component of the texel falls within the (inclusive) chroma range.See + ChromaKey High Value for further format, programming info. +3 31:0 ChromaKey High Value + This field specifies the “high” (maximum) value of the chroma key range. Texel samples are considered + “matching the key” if each component of the texel falls within the (inclusive) chroma range. + Programming Notes + ChromaKey values are specified using 8-bit channels. When using surface formats with less than 8 + bits per channel, the device will expand channels by replicating the required number of MSBs into the + LSBs of each channel. Software must account for this conversion when it programs Chromakey + Low/High Values (e.g., by performing the same replication). + For channels that do not exist in the actual surface (e.g., Alpha channel for non-ARGB maps), software + must explicitly program full range high/low values (High=FFh, Low=0h for formats using unsigned + chroma key values, High=7Fh, Low=FFh for formats using sign magnitude chroma key values) in order + to effectively remove the comparison of that field from the ChromaKey function. + For channels in SNORM format in the surface format, the value in the high/low value for that channel is + interpreted in sign magnitude format. Negative zero value is not supported (use positive zero instead). + For channels with mixed UNORM/SNORM formats (i.e. R5G5_SNORM_B6_UNORM), the ChromaKey + is programmed as if all channels are SNORM. + YUV ChromaKey will use an interpolated chrominance value from the map for comparison to the + chroma key values for those texels without chrominance due to downsampling. The chrominance value + used is the average of values to the left and right of the texel in question. + It is UNDEFINED to program any component of the ChromaKey High Value to be less than the + corresponding component of ChromaKey Low Value. + Format = interpreted according to associated texel format “class”: + Only the surface formats listed as supported for chroma key in the surface formats table can be used + with this feature. Use of any other surface format with chroma key enabled is UNDEFINED. + Surface Format 31:24 23:15 16:8 7:0 + ARGB and BC (DXT) formats A R G B + YCrCb formats A Cr Y Cb + + + + +2.12.7 3DSTATE_SAMPLER_PALETTE_LOAD0 + + 3DSTATE_SAMPLER_PALETTE_LOAD0 +Project: All +Source: RenderCS +Length Bias: 2 + Description Project +The 3DSTATE_SAMPLER_PALETTE_LOAD0 instruction is used to load 32-bit values into the first texture +palette. The texture palette is used whenever a texture with a paletted format (containing “Px [palette0]”) is +referenced by the sampler. +This instruction is used to load all or a subset of the 256 entries of the first palette. Partial loads always start +from the first (index 0) entry. + DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: Opcode + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 120 + 3DSTATE_SAMPLER_PALETTE_LOAD0 + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: Opcode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE + Format: Opcode + 23:16 3D Command Sub Opcode + Default Value: 02h 3DSTATE_SAMPLER_PALETTE_LOAD0 + Format: Opcode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Format: =n + Total Length - 2 + +1..n 31:24 Palette Alpha[0:N-1] + Project: All + Format: U8 + Alpha channel loaded into the Nth entry of the texture color palette. + + 23:16 Palette Red[0:N-1] + Project: All + Format: U8 + Alpha channel loaded into the Nth entry of the texture color palette. + + 15:8 Palette Green[0:N-1] + Project: All + Format: U8 + Alpha channel loaded into the Nth entry of the texture color palette. + + 7:0 Palette Blue[0:N-1] + Project: All + Format: U8 + Alpha channel loaded into the Nth entry of the texture color palette. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 121 + 2.12.8 3DSTATE_MONOFILTER_SIZE + + 3DSTATE_MONOFILTER_SIZE + +Source: RenderCS +Length Bias: 2 +This state specifies the size of the filter which is used when filtering in MAPFILTER_MONO mode. +DWord Bit Description +0 31:29 Command Type + Default Value: 3h GFXPIPE + Format: OpCode + 28:27 Command SubType + Default Value: 3h GFXPIPE_3D + Format: OpCode + 26:24 3D Command Opcode + Default Value: 1h 3DSTATE_NONPIPELINED + Format: OpCode + 23:16 3D Command Sub Opcode + Default Value: 11h 3DSTATE_MONOFILTER_SIZE + Format: OpCode + 15:8 Reserved + Project: All + Format: MBZ + 7:0 DWord Length + Default Value: 0h Excludes DWord (0,1) + Project: All + Format: =n + Total Length - 2 + +1 31:6 Reserved + Project: All + Format: MBZ + 5:3 Monochrome Filter Width + Project: All + Format: U3 + This field specifies the width of the monochrome filter. It is ignored if the monochrome filter is not + enabled. + Value Name + [1,7] + 2:0 Monochrome Filter Height + Project: All + Format: U3 + This field specifies the height of the monochrome filter. It is ignored if the monochrome filter is not + enabled. + Value Name + [1,7] + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 122 + 2.13 Messages +Restrictions: + +  Use of any message to the Sampling Engine function with the End of Thread bit set in the message + descriptor is not allowed. + + +2.13.1 Initiating Message +Execution Mask +SIMD16. The 16-bit execution mask forms the valid pixel signals. This determines which pixels are +sampled and results returned to the GRF registers. Samples for invalid pixels are not overwritten in the +GRF. However, if LOD needs to be computed for a subspan based on the message type and MIP filter +mode and at least one pixel in the subspan being valid, the sampling engine assumes that the +parameters for the upper left, upper right, and lower left pixels in the subspan are valid regardless of the +execution mask, as these are needed for the LOD computation. +SIMD8. The lower 8 bits of the execution mask forms the valid pixel signals. If LOD needs to be +computed based on MIP filter mode and at least one pixel in the subspan being valid, the sampling +engine assumes that the parameters for the upper left, upper right, and lower left pixels in the subspan +are valid regardless of the execution mask, since these are needed for the LOD computation. +SIMD4x2. The lower 8 bits of the execution mask is interpreted in groups of four. If any of the high 4 bits +are asserted, that sample is valid. If any of the low 4 bits are asserted, that sample is valid. The Write +Channel Mask rather than the execution mask determines which channels are written back to the GRF. +SIMD32. The execution mask is ignored, all pixels are considered valid and all channels are returned +regardless of the execution mask. + +2.13.1.1 Message Descriptor + + Bit Description + 19 + Header Present: Specifies whether the message includes a header phase. If the header is not present (this + field is zero), all of the fields normally contained in the header are assumed to be 0. + Format = Enable +18:17 + SIMD Mode: Specifies the SIMD mode of the message being sent. + Format = U2 + 0 = SIMD4x2 + 1 = SIMD8 + 2 = SIMD16 + 3 = SIMD32/64 +16:12 + Message Type: Specifies the type of message being sent. + Format = U5 + Refer to the table in section Payload Parameter Definition for encoding details. +11:8 + Sampler Index: Specifies the index into the sampler state table. Ignored for “ld”, “resinfo”, “sampleinfo” and + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 123 + Bit Description + “cache_flush”type messages. + Format = U4 + Range = [0,15] + Programming Notes: +  for the deinterlace message, this field must be a multiple of 2 (even) +  for the sample_8x8 message, this field must be a multiple of 4 + + 7:0 + Binding Table Index: Specifies the index into the binding table. Ignored for “cache_flush” type messages. + Format = U8 + Range = [0,255] + + +2.13.1.2 Message Header +The message header for the sampling engine is the same regardless of the message type. If the header +is not present (only), behavior is as if the message was sent with all fields in the header set to zero (write +channel masks are all enabled and offsets are zero). When Response length is 0 for sample_8x8 +message then the data from sampler is directly written out to memory using media write message. +DWord Bit Description + M0.7 31:0 + M0.6 31:0 + M0.5 31:5 Reserved + 4:0 Reserved + M0.4 31:0 Reserved + M0.3 31:5 + Sampler State Pointer: Specifies the 32-byte aligned pointer to the sampler state table. This field is + ignored for “ld” and “resinfo” message types. This pointer is relative to the General State Base + Address. + Format = GeneralStateOffset[31:5] + Ignored + 4:0 Ignored + M0.2 31:24 Ignored + 23 Reserved + 21:20 Ignore + 19:18 + SIMD32/64 Output Format Control + The contents of this field are ignored. The “16 bit Full” mode is always selected. + 17 + 17:16 + Gather4 Source Channel Select: Selects the source channel to be sampled in the gather4* + messages. Ignored for other message types. + 0: Red channel + 1: Green channel + 2: Blue channel + 3: Alpha channel + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 124 + DWord Bit Description + Programming Note: +  For gather4*_c messages, this field must be set to 0 (Red channel). + + 16 + Force LOD to Zero: If this bit is enabled, the calculated LOD is replaced with zero. The LOD is + replaced just before entering the pseudocode in section LOD Computation Pseudocode, therefore the + LOD is still subject to bias, overriding by sample_l delivered LOD, and clamping. + Format = Enable + Ignored + + 15 + Alpha Write Channel Mask: Enables the alpha channel to be written back to the originating thread. + 0: Alpha channel will be written back + 1: Alpha channel will not be written back + Programming Notes: +  a message with all four channels masked is not allowed. +  this field is ignored for the sample_unorm*. The write channel mask is generated from the + message type itself. +  this field is ignored for the deinterlace message. +  this field must be set to zero for sample_8x8 in VSA mode. + + 14 + Blue Write Channel Mask: See Alpha Write Channel Mask + + 13 + Green Write Channel Mask: See Alpha Write Channel Mask + + 12 + Red Write Channel Mask: See Alpha Write Channel Mask + + 11:8 + U Offset: the u offset from the _aoffimmi modifier on the “sample” or “ld” instruction in DX10. Must be + zero if the Surface Type is SURFTYPE_CUBE or SURFTYPE_BUFFER. Must be set to zero if + _aoffimmi is not specified. Format is S3 2’s complement. + Programming Note: +  this field is ignored for the sample_unorm*, sample_8x8, and deinterlace messages +  this field is ignored if the “offu” parameter is included in the gather4* messages + + 7:4 + V Offset: the v offset from the _aoffimmi modifier on the “sample” or “ld” instruction in DX10. Must be + zero if the Surface Type is SURFTYPE_CUBE or SURFTYPE_BUFFER. Must be set to zero if + _aoffimmi is not specified. Format is S3 2’s complement. + Programming Note: +  this field is ignored for the sample_unorm*, sample_8x8, and deinterlace messages +  this field is ignored if the “offu” parameter is included in the gather4* messages + + 3:0 + R Offset: the r offset from the _aoffimmi modifier on the “sample” or “ld” instruction in DX10. Must be + zero if the Surface Type is SURFTYPE_CUBE or SURFTYPE_BUFFER. Must be set to zero if + _aoffimmi is not specified. Format is S3 2’s complement. + Programming Note: +  this field is ignored for the sample_unorm*, sample_8x8, and deinterlace messages + +M0.1 31:0 Ignored + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 125 + DWord Bit Description + M0.0 31:0 Ignored + + +2.13.1.3 Payload Parameter Definition +The table below shows all of the messages supported by the sampling engine. The message type field in +the message descriptor in combination with the message length determines which message is being sent. +The table defines all of the parameters sent for each message type. The position of the parameters in the +payload is given in the section following corresponding to the SIMD mode given in the table. The +instruction column indicates the DX10 shader instructions expected to be translated to each message +type. +All parameters are of type IEEE_Float, except those in the ld and resinfo instruction message types, +which are of type S31. Any parameter indicated with a blank entry in the table is unused. A message +register containing only unused parameters not included as part of the message. The response lengths +given below assume all channels are unmasked. SIMD16 messages with masked channels will have +reduced response length. + +2.13.1.3.1 Payload Parameter Definition +The table below shows all of the message types supported by the sampling engine. The Message Type +field in the message descriptor determines which message is being sent. The SIMD Mode field +determines the number of instances (i.e. pixels) and the formatting of the initiating and writeback +messages. The Header Present field determines whether a header is delivered as the first phase of the +message or the default header from R0 of the thread’s dispatch is used. The Message Length field is +used to vary the number of parameters sent with each message. Higher-numbered parameters are +optional, and default to a value of 0 if not sent but needed for the surface being sampled. +The message lengths are computed as follows, where “N” is the number of parameters (“N” is rounded up +to the next multiple of 4 for SIMD4x2), and “H” is 1 if the header is present, 0 otherwise. The maximum +message length allowed to the sampler is 11. + + SIMD Mode Message Length + + SIMD4x2 H + (N/4) + SIMD8* H+N + SIMD16 H + (2*N) + +The response lengths are computed as follows: + + SIMD Mode Response Length + +SIMD4x2 1 + sample+killpix 5 + SIMD8 + all other message types 4 +SIMD16 8* + +* For SIMD16, phases in the response length are reduced by 2 for each channel that is masked. +SIMD16 messages with six or more parameters exceed the maximum message length allowed, in which +case they are not supported. This includes some forms of sample_b_c, sample_l_c, and gather4_po_c +message types. Note that even for these messages, if 5 or fewer parameters are included in the +message, the SIMD16 form of the message is allowed. SIMD16 forms of sample_d and sample_d_c are +not allowed, regardless of the number of parameters sent. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 126 + SIMD8 and SIMD16 Messages: + +Message Type mnemonic parameters + + 0 1 2 3 4 5 6 7 8 9 10 + +00000 sample u v r ai mlod* +00001 sample_b bias u v r ai mlod* +00010 sample_l lod u v r ai +00011 sample_c ref u v r ai mlod* +00100 sample_d u dudx dudy v dvdx dvdy r drdx drdy ai mlod* +00101 sample_b_c ref bias u v r ai +00110 sample_l_c ref lod u v r ai +00111 ld u lod v r +00111 ld † u v lod r +01000 gather4 u v r ai +01001 LOD u v r ai +01010 resinfo lod +01011 sampleinfo +01011 sampleinfo † x +01100 sample+killpix u v r +10000 gather4_c ref u v r ai +10001 gather4_po u v offu offv r +10010 gather4_po_c ref u v offu offv r +10100 sample_d_c ref u dudx dudy v dvdx dvdy r drdx drdy ai +11100 ld2dms_w si mcsl mcsh u v r lod * +10110 sample_min u v +10111 sample_max u v +11101 ld_mcs u v r lod * +11110 ld2dms si mcs u v r lod * +11111 Id2dss ssi u v r lod * +11000 sample_lz u v r ai +11001 sample_c_lz ref u v r ai + +11010 ld_lz u v r + +SIMD4x2 Messages: + +Message Type mnemonic parameters + + 0 1 2 3 4 5 6 7 8 9 10 + + 00010 sample_l u v r ai lod + 00100 sample_d u v r ai dudx dudy dvdx dvdy drdx drdy mlod* + 00110 sample_l_c u v r ai ref lod + 00111 ld u v r lod + 01000 gather4 u v r ai + 01010 resinfo lod + 01011 sampleinfo + 10000 gather4_c u v r ai ref + 10001 gather4_po u v r ai offu offv + 10010 gather4_po_c u v r ref offu offv + 10100 sample_d_c u v r ai dudx dudy dvdx dvdy drdx drdy ref + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 127 + 11100 ld2dms_w u v r lod * si mcsl mcsh + 11101 ld_mcs u v r lod * + 11110 ld2dms u v r lod * si mcs + +SIMD32/SIMD64 Messages: + +Message Type mnemonic Payload Layout Message Length Response Length + + 00000 sample_unorm Pixel Shader H+1 8 ** + 00010 sample_unorm+killpix Pixel Shader H+1 9 ** + 00011 sample_8x8 Pixel Shader H+1 16 * + 01000 deinterlace Pixel Shader H+1 † + 01100 sample_unorm Media H+1 8 ** + 01010 sample_unorm+killpix Media H+1 9 ** + 01011 sample_8x8 Media H+1 16 * + 11111 cache_flush no payload 1 1 + +* For sample_8x8, phases in the response length are reduced by 4 for each channel that is masked. +** For sample_unorm, phases in the response length are reduced by 2 for each channel that is masked. +† For deinterlace, response length depending on certain state fields. Refer to writeback message +definition for details. + +2.13.1.4 Message Types +The behavior of each message type is as follows: + Message Type Description +sample + The surface is sampled using the indicated sampler state. LOD is computed using gradients + between adjacent pixels. One, two, or three parameters may be specified depending on how + many coordinate dimensions the indicated surface type uses. Extra parameters specified are + ignored. Missing parameters are defaulted to 0. + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE1D, SURFTYPE_2D, + SURFTYPE_3D, or SURFTYPE_CUBE. +  The Surface Format of the associated surface cannot be MONO8. +  If the Surface Format of the associated surface is UINT or SINT, the Surface Type cannot + be SURFTYPE_3D or SURFTYPE_CUBE and Address Control Mode cannot be + CLAMP_BORDER or HALF_BORDER. +  sample is not supported in SIMD4x2 mode. +  :Number of Multisamples on the associated surface must be MULTISAMPLECOUNT_1. + + +sample+killpix The surface is sampled as in the sample message type. An additional register is returned after + the sample results which contains the kill pixel mask. This message type is required to allow the + result of a chroma key enabled sampler in KEYFILTER_KILL_ON_ANY_MATCH mode to affect + the final pixel mask. + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE1D, SURFTYPE_2D, + SURFTYPE_3D, or SURFTYPE_CUBE. +  The Surface Format of the associated surface cannot be MONO8. +  If the Surface Format of the associated surface is UINT or SINT, the Surface Type cannot + be SURFTYPE_3D or SURFTYPE_CUBE and Address Control Mode cannot be + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 128 + Message Type Description + CLAMP_BORDER or HALF_BORDER. +  sample+killpix is supported only in SIMD8 mode. +  Number of Multisamples on the associated surface must be MULTISAMPLECOUNT_1. + +sample_b + The surface is sampled using the indicated sampler state. LOD is computed using gradients + between adjacent pixels, then the value in the parameter is added to the LOD for each pixel. + The LOD bias delivered in the bias parameter is restricted to a range of [-16.0, +16.0). Values + outside this range produce undefined results. + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE1D, SURFTYPE_2D, + SURFTYPE_3D, or SURFTYPE_CUBE. +  The Surface Format of the associated surface cannot be MONO8 +  If the Surface Format of the associated surface is UINT or SINT, the Surface Type + cannot be SURFTYPE_3D or SURFTYPE_CUBE and Address Control Mode cannot be + CLAMP_BORDER or HALF_BORDER +  sample_b is not supported in SIMD4x2 mode. +  Number of Multisamples on the associated surface must be + MULTISAMPLECOUNT_1. + +sample_l The surface is sampled using the indicated sampler state. LOD is not computed, but instead is + taken from the lod parameter. +sample_lz + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE1D, SURFTYPE_2D, + SURFTYPE_3D, or SURFTYPE_CUBE. +  If the Surface Format of the associated surface is UINT or SINT, the Surface Type + cannot be SURFTYPE_3D or SURFTYPE_CUBE and Address Control Mode cannot be + CLAMP_BORDER or HALF_BORDER. +  Number of Multisamples on the associated surface must be + MULTISAMPLECOUNT_1. + +sample_c The surface is sampled using the indicated sampler state. All four coordinates must be + specified, however v and r may not be used depending on the indicated surface type. The ai +sample_c_lz + parameter indicates the array index for a cube surface.The ref parameter specifies the + reference value that is compared against the red channel of the sampled surface, and the texel + is replaced with either white or black depending on the result of the comparison. + The WGF sample_c_lz instruction is implemented by issuing the sample_c message with Force + LOD to Zero enabled in the message header or by issuing the sample_l_c message with the + LOD parameter set to zero. + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE1D, SURFTYPE_2D, + or SURFTYPE_CUBE. +  The Surface Format of the associated surface must be indicated as supporting shadow + mapping as indicated in the surface format table. +  With sample_c, MIPFILTER_LINEAR, MAPFILTER_LINEAR, + MAPFILTER_ANISOTROPIC are allowed even for surface formats that are listed as not + supporting filtering in the surface formats table. +  Use of the SIMD4x2 form of sample_c without Force LOD to Zero enabled in the + message header is not allowed, as it is not possible for the hardware to compute LOD for + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 129 + Message Type Description + SIMD4x2 messages. For, sample_c is not supported in SIMD4x2 mode. +  Use of sample_c with DX9 Texture Border Color Mode and either of the following is + undefined: +  any applicable Address Control Mode (depending on Surface Type) is set to + TEXCOORDMODE_CLAMP_BORDER or TEXCOORDMODE_HALF_BORDER +  Surface Type is SURFTYPE_CUBE and any Cube Face Enable is disabled +  Use of sample_c with SURFTYPE_CUBE surfaces is undefined with the following + surface formats: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, I32_FLOAT, + L32_FLOAT, A32_FLOAT. +  Number of Multisamples on the associated surface must be + MULTISAMPLECOUNT_1. + +sample_b_c + This is a combination of sample_b and sample_c. Both the LOD bias and reference values are + delivered. All restrictions applying to both sample_b and sample_c must be honored. + +sample_l_c + This is a combination of sample_l and sample_c. Both the LOD and reference values are + delivered. All restrictions applying to both sample_l and sample_c must be honored. However, + unlike sample_c, sample_l_c is allowed as a SIMD4x2 message. + + + Programming Notes: + + sample_g The surface is sampled using the indicated sampler state. LOD is computed using the gradients + present in the message. The r coordinate and its gradients are required only for surface types + sample_d + that use the third coordinate. Usage of this message type on cube surfaces assumes that the u, + v, and gradients have already been transformed onto the appropriate face, but still in [-1,+1] + range. The r coordinate contains the faceid, and the r gradients are ignored by hardware. + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE1D, SURFTYPE_2D, + SURFTYPE_3D, or SURFTYPE_CUBE. +  The Surface Format of the associated surface cannot be MONO8. +  If the Surface Format of the associated surface is UINT or SINT, the Surface Type + cannot be SURFTYPE_3D or SURFTYPE_CUBE and Address Control Mode cannot be + CLAMP_BORDER or HALF_BORDER. +  Number of Multisamples on the associated surface must be + MULTISAMPLECOUNT_1. + + This is a combination of sample_g and sample_c. Both the gradients for calculating LOD and + sample_g_c + reference values are delivered. All restrictions applying to both sample_g and sample_c must be + sample_d_c honored. However, unlike sample_c, sample_g_c is allowed as a SIMD4x2 message. +resinfo + The surface indicated in the surface state is not sampled. Instead, the width, height, depth, and + MIP count of the surface are returned as indicated in the table below. The format of the returned + data is UINT32 for. The width, height, and depth may be shifted right, per pixel, by the LOD + value provided in the lod parameter to give the dimensions of the specified mip level. The lod + parameter is an unsigned 32-bit integer in this mode (note that sending a signed 32-bit integer + always has the same effect, as negative values are out-of-range when interpreted as unsigned + integers). The Sampler State Pointer and Sampler Index are ignored. + + surface type red green blue alpha + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 130 + Message Type Description + SURFTYPE1D (Width+1)>>LOD 0 MIPCount + Surface Array? + Depth+1 : 0 + + SURFTYPE_2D (Width+1)>>LOD (Height+1)>>LOD MIPCount + : + Surface Array? + Depth+1 : 0 + SURFTYPE_3D (Width+1)>>LOD (Height+1)>>LOD (Depth+1)>>LOD MIPCount + SURFTYPE_CUBE (Width+1)>>LOD (Height+1)>>LOD MIPCount + Depth==0 ? 0 : + Depth+1 + : + Surface Array ? + Depth+1 : 0 + undefined undefined undefined + SURFTYPE_BUFFER undefined + SURFTYPE_STRBUF + Buffer size (from + combined + Depth/Height/Width) + SURFTYPE_NULL 0 0 0 0 + +ld The surface is sampled using a default sampler state, indicated below. The lod parameter + contains the LOD of the mip map to be sampled. If the message doesn’t include an lod +ld2dms + parameter, the message samples from LOD 0. The parameter si contains the sample index, +Id2dms_w + which is clamped to the number of samples on the surface (supported by some messages on +ld_mcs only). The v and r channel may be ignored depending on the indicated surface type. All + incoming values are unsigned 32-bit integers in this mode. The u, v, and r parameters contain +Id2dss integer texel addresses on the LOD indicated in the parameter. The Sampler State Pointer and +ld_lz Sampler Index are ignored. + For these message types, the sampler state is defaulted as follows: + •min, mag, and mip filter modes are “nearest” + •all address control modes are “zero” (a special mode in which any texel off the map or + outside the MIP range of the surface has a value of zero in all channels, except for + surface formats without an alpha channel, which will return a value of one in the alpha + channel) + Errata:Address offset needs to be zero for ld2dms/ld2dss messages + The mcs parameter in the ld2dms message defines the multisample control data and is used + only to sample from a multisampled surface. + The ld_mcs message uses the MCS Base Address and MCS Surface Pitch fields in + SURFACE_STATE to determine the base address and pitch of the surface. Surface Format is + overridden to R8_UINT if Number of Multisamples is 4, or R32_UINT if Number of Multisamples + is 8. This message cannot be used on a non-multisampled surface. Otherwise, ld_mcs behaves + like the ld message. If ld_mcs is issued on a surface with MCS disabled, this message returns + zeros in all channels. + The ssi parameter in the Id2dss message defines the sample slice that will be sampled from. + Refer to the multisample storage format in the GPU Overview volume for more details. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 131 + Message Type Description + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE1D, SURFTYPE_2D, + SURFTYPE_3D, or SURFTYPE_BUFFER for the ld message. +  The Surface Type of the associated surface must be SURFTYPE_2D for the ld_mcs , + ld2dms , and Id2dss messages. +  The Surface Format of the associated surface cannot be MONO8. +  Number of Multisamples on the associated surface must be + MULTISAMPLECOUNT_1 for the ld message type. +  Errata: Surface formats R32G32B32X32_FLOAT, X32_TYPELESS_G8X24_UINT, + R16G16B16X16_UNORM, R16G16B16X16_FLOAT, X24_TYPELESS_G8_UINT, + L24X8_UNORM, L32_FLOAT, B8G8R8X8_UNORM, B8G8R8X8_UNORM_SRGB, + R8G8B8X8_UNORM, R8G8B8X8_UNORM_SRGB, B10G10R10X2_UNORM, + B5G6R5_UNORM, B5G6R5_UNORM_SRGB, L16_UNORM, + R5G5_SNORM_B6_UNORM, L8_UNORM, L8_UNORM_SRGB, R1_UNORM, + BC4_UNORM (DXT4/5) will return zero in the alpha channel, for out of bound case. + +sampleinfo + only: The surface indicated in the surface state is not sampled. Instead, the number of samples + (UINT32) and the sample position palette index (UINT32) for the surface are returned in the red + and alpha channels respectively as UINT32 values. The sample position palette index returned + in alpha is incremented by one from its value in the surface state. The Sampler State Pointer + and Sampler Index are ignored. + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE_2D or + SURFTYPE_NULL + +LOD + only: The surface indicated in the surface state is not sampled. Instead, LOD is computed as if + the surface will be sampled, using the indicated sampler state, and the clamped and unclamped + LOD values are returned in the red and green channels, respectively, in FLOAT32 format. The + blue and alpha channels are undefined, and can be masked to avoid returning them. LOD is + computed using gradients between adjacent pixels. Three parameters are always specified, + with extra parameters not needed for the surface being ignored. + + + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE1D, SURFTYPE_2D, + SURFTYPE_3D, or SURFTYPE_CUBE. +  The Surface Format of the associated surface cannot be MONO8 +  The Surface Format of the associated surface cannot be any UINT or SINT format. +  LOD is not supported in SIMD4x2 mode. +  Number of Multisamples on the associated surface must be + MULTISAMPLECOUNT_1. + +gather4 The surface is sampled using bilinear filtering, regardless of the filtering mode specified in the + sampler state. For SURFTYPE_2D LOD is forced to zero before sampling. The samples are not +gather4_po + filtered, but instead the four samples are returned directly in the sample’s corresponding four +(load4) channels as follows: + upper left sample = alpha channel upper right sample = blue channel + lower left sample = red channel lower right sample = green channel + Two or three parameters may be specified depending on how many coordinate dimensions the + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 132 + Message Type Description + indicated surface type uses. Extra parameters specified are ignored. Missing parameters + default to 0. + + + The gather4_po message has offu and offv parameters, which contain texel-space offsets that + override the U/V Offset fields in the message header. Unlike the message header fields + however, these offsets have a wider range [-32,+31], and can differ per pixel or sample. The + format of the data is 32-bit 2’s complement signed integer, but hardware only interprets the + least significant 6 bits of each value, treating it as a 6-bit 2’s complement signed integer. + + + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE_2D or + SURFTYPE_CUBE. If the message type is gather4_po, only SURFTYPE_2D is allowed. +  The Surface Format of the associated surface cannot be MONO8 +  The Surface Format of the associated surface cannot be any UINT or SINT format. +  The channel selected is determined by the Gather4 Source Channel Select field in the + message header. +  Mip Mode Filter must be set to MIPFILTER_NONE +  Number of Multisamples on the associated surface must be + MULTISAMPLECOUNT_1. +  Use of gather4 or gather4_po with DX9 Border Color Mode and either of the following is + underfined: + o any applicable Address Control Mode (depending on Surface Type) is set to + TEXCOORDMODE_CLAMP_BORDER or TEXCOORDMODE_HALF_BORDER + o Surface Type is SURFTYPE_CUBE and any Cube Face Enable is disabled + + + +gather4_c only: The surface is sampled using bilinear filtering, regardless of the filtering mode specified in + the sampler state. For SURFTYPE_2D LOD is forced to zero before sampling. The samples are +gather4_po_c + not filtered, but instead the four samples are returned, after being compared with the ref + paramater as in the sample_c message. Each texel is replaced with either white or block + depending on the result of the comparison. The four samples are returned in the sample’s + corresponding four channels in the same mapping as the gather4 message. The offu and offv + parameters in the gather4_po_c message cause offset override behavior as described in the + gather4 message. + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE_2D or + SURFTYPE_CUBE. If the message type is gather4_po_c, only SURFTYPE_2D is + allowed. +  The Surface Format of the associated surface must be one of the following: + R32_FLOAT_X8X24_TYPELESS, R32_FLOAT, R24_UNORM_X8_TYPELESS, + R16_UNORM. +  The channel selected is determined by the Gather4 Source Channel Select field in the + message header. +  Mip Mode Filter must be set to MIPFILTER_NONE +  Use of gather4_c or gather4_po_c with DX9 Border Color Mode and either of the + following is underfined: + o Surface Type is SURFTYPE_CUBE and any Cube Face Enable is disabled + o any applicable Address Control Mode (depending on Surface Type) is set to + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 133 + Message Type Description + TEXCOORDMODE_CLAMP_BORDER or TEXCOORDMODE_HALF_BORDER +  Number of Multisamples on the associated surface must be + MULTISAMPLECOUNT_1. + +sample_unorm + only: The surface is sampled using the indicated sampler state. 32 contiguous pixels in a 8-wide + by 4-high arrangement are sampled. The U and V addresses for the upper left pixel is delivered + in this message along with a Delta U and Delta V parameter. Given a pixel at (x,y) relative to + the upper left pixel (where (0,0) is the upper left pixel), the U and V for that pixel are computed + as follows: + U(x,y) = U(0,0) + DeltaU * x + V(x,y) = V(0,0) + DeltaV * y + + + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE_2D +  The Surface Format of the associated surface must be UNORM with <= 8 bits per channel +  The MIP Count, Depth, Surface Min LOD, and Min Array Element of the associated surface + must be 0 +  The Min and Mag Mode Filter must be MAPFILTER_NEAREST or MAPFILTER_LINEAR +  The Mip Mode Filter must be MIPFILTER_NONE +  The TCX and TCY Address Control Mode cannot be + TEXCOORDMODE_CLAMP_BORDER + TEXCOORDMODE_HALF_BORDER + TEXCOORDMODE_MIRROR + TEXCOORDMODE_MIRROR_ONCE + TEXCOORDMODE_WRAP + +  DeltaU * Width of the associated surface must be less than or equal to 3.0 +  DeltaV * Height of the associated surface must be less than or equal to 3.0 +  Number of Multisamples on the associated surface must be MULTISAMPLECOUNT_1. + +sample_unorm_R +G ++killpix + +sample_unorm only: This message is identical to the sample_unorm message except it returns a kill pixel mask + in addition to the selected channels in the writeback message. This message type is required to ++killpix + allow the result of a chroma key enabled sampler in KEYFILTER_KILL_ON_ANY_MATCH + mode to affect the final pixel mask. All restrictions of the sample_unorm message apply to this + message also. + +sample_8x8 + only:The surface is sampled using an optional 8x8 filter followed by an optional image + enhancement filter, using state defined in SAMPLER_STATE and SAMPLER_8x8_STATE. The + input consists of 64 contiguous pixels in an 16-wide by 4-high arrangement. The address + control mode behaves as clamp mode. The U and V addresses for the upper left pixel are + delivered in this message along with a Delta U and Delta V parameter. Given a pixel at (x,y) + relative to the upper left pixel (where (0,0) is the upper left pixel), the U and V for that pixel are + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 134 + Message Type Description + computed as follows: + U(x,y) = U(0,0) + DeltaU * x + U_2nd_Derivative * x * (x - 1)/2 + V(x,y) = V(0,0) + DeltaV * y + V_2nd_Derivative * y * (y - 1)/2 + Programming Notes: +  The Surface Type of the associated surface must be SURFTYPE_2D +  The Surface Format of the associated surface must be UNORM with <= 10 bits per + channel +  DeltaV * Height of the associated surface must be less than 16.0 +  Map Width must be >= 4 +  :Errata IEF_OFF YUV |U_2nd_Derivative| < 0.02/MapWidth +  :Errata IEF_OFF RGB |U_2nd_Derivative| < 0.05/MapWidth +  :Errata for IEF_OFF set DeltaU = DeltaU + 2x U_2nd_Derivative + +deinterlace + to The surface is deinterlaced and/or denoised, using state defined in SAMPLER_STATE. The + U and V addresses for the upper left pixel are delivered in this message. + + + Programming Notes: + +Programming Notes: + +  For surfaces of type SURFTYPE_CUBE, the sampling engine requires u, v, and r parameters that + have already been divided by the absolute value of the parameter (u, v, or r) with the largest + absolute value. + +2.13.1.5 Parameter Types +sample*, LOD, and gather4 messages +For all of the sample*, LOD, and gather4 message types, all parameters are 32-bit floating point, except +the ‘mcs’, ‘offu’, and ‘offv’ parameters. Usage of the u, v, and r parameters is as follows based on +Surface Type. Normalized values range from [0,1] across the surface, with values outside the surface +behaving as specified by the Address Control Mode in that dimension. Unnormalized values range from +[0,n-1] across the surface, where n is the size of the surface in that dimension, with values outside the +surface being clamped to the surface. + + Surface Type u v r ai + +SURFTYPE1D normalized ‘x’ unnormalized array ignored ignored + coordinate index + +SURFTYPE_2D normalized ‘x’ normalized ‘y’ unnormalized array ignored + coordinate coordinate index + +SURFTYPE_3D normalized ‘x’ normalized ‘y’ normalized ‘z’ ignored + coordinate coordinate coordinate + +SURFTYPE_CUBE normalized ‘x’ normalized ‘y’ normalized ‘z’ unnormalized array + coordinate coordinate coordinate index + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 135 + mcs parameter +The ‘mcs’ parameter delivers the multisample control data. The format of this parameter is always a 32-bit +unsigned integer. Refer to the section titled “Multisampled Surface Behavior” for details on this parameter. +Ld* messages +For the ld message types, all parameters are 32-bit signed integers, except the ‘mcs’ parameter. Usage +of the u, v, and r parameters is as follows based on Surface Type. Unnormalized values range from [0,n- +1] across the surface, where n is the size of the surface in that dimension. Input of any value outside of +the range returns zero. + + Surface Type u v r + +SURFTYPE1D unnormalized ‘x’ coordinate unnormalized array index ignored + +SURFTYPE_2D unnormalized ‘x’ coordinate unnormalized ‘y’ coordinate unnormalized array index + +SURFTYPE_3D unnormalized ‘x’ coordinate unnormalized ‘y’ coordinate unnormalized ‘z’ coordinate + +SURFTYPE_BUFFER unnormalized ‘x’ coordinate ignored ignored + + +2.13.1.6 SIMD16 Payload +The payload of a SIMD16 message provides addresses for the sampling engine to process 16 entities +(examples of an entity are vertex and pixel). The number of parameters required to sample the surface +depends on the state that the sampler/surface is in. Each parameter takes two message registers, with 8 +entities, each a 32-bit floating point value, being placed in each register. Each parameter always takes a +consistent position in the input payload. The length field can be used to send a shorter message, but +intermediate parameters cannot be skipped as there is no way to signal this. For example, a 2D map +using “sample_b” needs only u, v, and bias, but must send the r parameter as well. +DWord Bit Description + M1.7 31:0 + Subspan 1, Pixel 3 (lower right) Parameter 0 + Specifies the value of the pixel’s parameter 0. The actual parameter that maps to parameter 0 is given + in the table in section Payload Parameter Definition. + Format = IEEE Float for all sample* message types, U32 for ld and resinfo message types. + M1.6 31:0 + Subspan 1, Pixel 2 (lower left) Parameter 0 + + M1.5 31:0 + Subspan 1, Pixel 1 (upper right) Parameter 0 + + M1.4 31:0 + Subspan 1, Pixel 0 (upper left) Parameter 0 + + M1.3 31:0 + Subspan 0, Pixel 3 (lower right) Parameter 0 + + M1.2 31:0 + Subspan 0, Pixel 2 (lower left) Parameter 0 + + M1.1 31:0 + Subspan 0, Pixel 1 (upper right) Parameter 0 + + M1.0 31:0 + Subspan 0, Pixel 0 (upper left) Parameter 0 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 136 + DWord Bit Description + M2.7 31:0 + Subspan 3, Pixel 3 (lower right) Parameter 0 + + M2.6 31:0 + Subspan 3, Pixel 2 (lower left) Parameter 0 + + M2.5 31:0 + Subspan 3, Pixel 1 (upper right) Parameter 0 + + M2.4 31:0 + Subspan 3, Pixel 0 (upper left) Parameter 0 + + M2.3 31:0 + Subspan 2, Pixel 3 (lower right) Parameter 0 + + M2.2 31:0 + Subspan 2, Pixel 2 (lower left) Parameter 0 + + M2.1 31:0 + Subspan 2, Pixel 1 (upper right) Parameter 0 + + M2.0 31:0 + Subspan 2, Pixel 0 (upper left) Parameter 0 + + M3 – Repeat packets 1 and 2 to cover all required parameters + Mn + + +2.13.1.7 SIMD8 Payload +This message is intended to be used in a SIMD8 thread, or in pairs from a SIMD16 thread. Each +message contains sample requests for just 8 pixels. +DWord Bit Description + M1.7 31:0 + Subspan 1, Pixel 3 (lower right) Parameter 0 + Specifies the value of the pixel’s parameter 0. The actual parameter that maps to parameter 0 is given + in the table in section Payload Parameter Definition. + Format = IEEE Float for all sample* message types, U32 for ld and resinfo message types. + M1.6 31:0 + Subspan 1, Pixel 2 (lower left) Parameter 0 + + M1.5 31:0 + Subspan 1, Pixel 1 (upper right) Parameter 0 + + M1.4 31:0 + Subspan 1, Pixel 0 (upper left) Parameter 0 + + M1.3 31:0 + Subspan 0, Pixel 3 (lower right) Parameter 0 + + M1.2 31:0 + Subspan 0, Pixel 2 (lower left) Parameter 0 + + M1.1 31:0 + Subspan 0, Pixel 1 (upper right) Parameter 0 + + M1.0 31:0 + Subspan 0, Pixel 0 (upper left) Parameter 0 + + M2 – Repeat packet 1 to cover all required parameters + Mn + + +2.13.1.8 SIMD8D Payload +This message is intended to be used in a SIMD8 thread, or in pairs from a SIMD16 thread. Each +message contains sample requests for just 8 pixels. The “u” and “v” parameters are delivered in double +precision floating point, and thus it takes two message phases to deliver 8 values. These are labeled in + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 137 + the Payload Parameter Definition table as “u0”, “u1”, “v0”, and “v1”. The number after the u/v indicate +which subspan is contained in that parameter. +Parameters “u0”, “u1”, “v0”, or “v1”: + +DWord Bit Description + + Mn.7 31:0 + Pixel 3 (lower right) Parameter n – upper 32 bits + Specifies the value of the pixel’s parameter n. The actual parameter that maps to parameter n is given + in the table in section Payload Parameter Definition. + Format = Double precision IEEE Float, upper 32 bits + Mn.6 31:0 + Pixel 3 (lower right) Parameter n – lower 32 bits + Format = Double precision IEEE Float, lower 32 bits + + Mn.5 31:0 Pixel 2 (lower left) Parameter n – upper 32 bits + Mn.4 31:0 Pixel 2 (lower left) Parameter n – lower 32 bits + Mn.3 31:0 Pixel 1 (upper right) Parameter n – upper 32 bits + Mn.2 31:0 Pixel 1 (upper right) Parameter n – lower 32 bits + Mn.1 31:0 Pixel 0 (upper left) Parameter n – upper 32 bits + Mn.0 31:0 Pixel 0 (upper left) Parameter n – lower 32 bits + +All other parameters: + +DWord Bit Description + + Mn.7 31:0 + Subspan 1, Pixel 3 (lower right) Parameter n + Specifies the value of the pixel’s parameter n. The actual parameter that maps to parameter n is given + in the table in section Payload Parameter Definition. + Format = IEEE Float + Mn.6 31:0 Subspan 1, Pixel 2 (lower left) Parameter n + Mn.5 31:0 Subspan 1, Pixel 1 (upper right) Parameter n + Mn.4 31:0 Subspan 1, Pixel 0 (upper left) Parameter n + Mn.3 31:0 Subspan 0, Pixel 3 (lower right) Parameter n + Mn.2 31:0 Subspan 0, Pixel 2 (lower left) Parameter n + Mn.1 31:0 Subspan 0, Pixel 1 (upper right) Parameter n + Mn.0 31:0 Subspan 0, Pixel 0 (upper left) Parameter n + + +2.13.1.9 SIMD4x2 Payload +DWord Bit Description + M1.7 31:0 + Sample 1 Parameter 3 + Specifies the value of the pixel’s parameter 3. The actual parameter that maps to parameter 3 is given in + the table in section Payload Parameter Definition. + Format = IEEE Float for all sample* message types, U32 for ld and resinfo message types. + + M1.6 31:0 + Sample 1 Parameter 2 + + M1.5 31:0 + Sample 1 Parameter 1 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 138 + DWord Bit Description + M1.4 31:0 + Sample 1 Parameter 0 + + M1.3 31:0 + Sample 0 Parameter 3 + + M1.2 31:0 + Sample 0 Parameter 2 + + M1.1 31:0 + Sample 0 Parameter 1 + + M1.0 31:0 + Sample 0 Parameter 0 + + M2 Parameters 4-7 if present + M3 Parameters 8-11 if present + + +2.13.1.10 SIMD32/64 Payload + +2.13.1.10.1 Pixel Shader +This position of Delta U/V in the pixel shader payload layout is to allow the register delivered in the pixel +shader dispatch containing the coefficients for the texture coordinates to be left in their original position +(Delta U = Cxs, Delta V = Cyt). The values for U and V are computed in the pixel shader into the unused +positions in this register. +DWord Bit Description + M1.7 31:0 Ignored + M1.6 31:0 + Pixel 0 V Address + Format: + sample_unorm* and sample_8x8: IEEE_Float in normalized space + deinterlace: U32 (Range: [0,2046]) + M1.5 31:0 + Delta V: defines the difference in V for adjacent pixels in the Y direction. + Programming Notes: +  Delta V multiplied by Height in SURFACE_STATE must be less than or equal to 3 for + sample_unorm* message types. +  Delta V multiplied by Height in SURFACE_STATE must be less than 16 for the sample_8x8 + message type. +  This field is ignored for the deinterlace message type. + + Format = IEEE_Float in normalized space + 31:0 Ignored + M1.4 + M1.3 31:0 Ignored + M1.2 31:0 + Pixel 0 U Address + Format: + sample_unorm* and sample_8x8: IEEE_Float in normalized space + deinterlace: U32 (Range: [0,4095]) + M1.1 31:0 + U 2nd Derivative + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 139 + DWord Bit Description + Defines the change in the delta U for adjacent pixels in the X direction. + Programming Notes: +  This field is ignored for messages other than sample_8x8. + + Format = IEEE_Float in normalized space + Ignored + M1.0 31:0 + Delta U: defines the difference in U for adjacent pixels in the X direction. + Programming Notes: +  Delta U multiplied by Width in SURFACE_STATE must be less than or equal to 3 for + sample_unorm* message types. +  This field is ignored for the deinterlace message type. + + Format = IEEE_Float in normalized space + + +2.13.1.10.2 Media +DWord Bits Description + M1.7 31:0 + Group ID Number + Used to group messages for reorder for sample_8x8 messages. All messages with the same Group ID + must have the following in common: SURFACE_STATE, SAMPLER_STATE, destination register on + send instruction, M0, and M1 except for Horizontal and Vertical Block Number. + + M1.6 31:0 + U 2nd Derivative + Defines the change in the delta U for adjacent pixels in the X direction. + Programming Notes: +  This field is ignored for messages other than sample_8x8. +  (64 – (2*du))/35 >= ddu >= -du/18 + + Format = IEEE_Float in normalized space. + 31:0 + M1.5 Delta V: defines the difference in V for adjacent pixels in the Y direction. + Programming Notes: +  Delta V multiplied by Height in SURFACE_STATE must be less than or equal to 3 for + sample_unorm* message types. +  Delta V multiplied by Height in SURFACE_STATE must be less than 16 for the sample_8x8 + message type. +  This field is ignored for the deinterlace message type. +  Negative Delta V are not supported and should be clamped to 0. + + Format = IEEE_Float in normalized space. + + M1.4 31:0 + Delta U: defines the difference in U for adjacent pixels in the X direction. + Programming Notes: +  Delta U multiplied by Width in SURFACE_STATE must be less than or equal to 3 for + sample_unorm* message types. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 140 + DWord Bits Description +  Delta U multiplied by Width in SURFACE_STATE must be less than 16 for the sample_8x8 + message type. +  This field is ignored for the deinterlace message type. +  Negative Delta U are not supported and should be clamped to 0. + + Format = IEEE_Float in normalized space. +M1.3 31:0 + Pixel 0 V Address + Format: sample_unorm* and sample_8x8: IEEE_Float in normalized space. + Deinterlace: U32 (Range: [0,2046]) + Specifies the address for the pixel at the top left of the group and not the top of the message block sent + in. +M1.2 31:0 + Pixel 0 U Address + Format: sample_unorm* and sample_8x8: IEEE_Float in normalized space. + Deinterlace: U32 (Range: [0,4095]) + Specifies the address for the pixel at the top left of the group and not the top of the message block sent + in. + WA for Sample_8x8 messages only: + //Only for YUV packed surfaces, NV12 and Y-channel only for Planar surfaces + if (((int)(u_left*width + 5.0/256) > (int)(uleft*width)) + { + modified_u_coord = u_coord – 5.0/(256*width); //floating point + } + else if(((int)(u_left*width + 255.0/256) == (int)(u_left*width)) + { + modified_u_coord = u_coord + 1.0/(256*width); //floating point + } + Else{ + modified_u_coord = u_coord; + } + Where u_left = u – 2*du + 3*ddu for IEF On + And u_left = u for IEF Off case + u_coord is the intended Pixel 0 U address and Modified_u_coord is what is sent in this field. + +M1.1 31:0 + Vertical Block Number + Specifies the vertical block offset for the 8x8 block being sent for the sample_8x8 message. This will be + equal to the vertical pixel offset from the given address pixel 0 V address divided by 8. + Format: U9 +M1.0 31:0 Ignored + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 141 + 2.13.2 Writeback Message +Corresponding to the four input message definitions are four writeback messages. Each input message +generates a corresponding writeback message of the same type (SIMD16, SIMD8, SIMD4x2, or +SIMD32/64). + + +2.13.2.1 SIMD16 +A SIMD16 writeback message consists of up to 8 destination registers. Which registers are returned is +determined by the write channel mask received in the corresponding input message. Each asserted write +channel mask results in both destination registers of the corresponding channel being skipped in the +writeback message, and all channels with higher numbered registers being dropped down to fill in the +space occupied by the masked channel. For example, if only red and alpha are enabled, red is sent to +regid+0 and regid+1, and alpha to regid+2 and regid+3. The pixels written within each destination +register is determined by the execution mask on the “send” instruction. + +DWord Bit Description + W0.7 31:0 + Subspan 1, Pixel 3 (lower right) Red: Specifies the value of the pixel’s red channel. + Format = IEEE Float, S31 signed 2’s comp integer, or U32 unsigned integer. Format depends on the + Data Return Format programmed for the surface being sampled. + + W0.6 31:0 + Subspan 1, Pixel 2 (lower left) Red + + W0.5 31:0 + Subspan 1, Pixel 1 (upper right) Red + + W0.4 31:0 + Supspan 1, Pixel 0 (upper left) Red + + W0.3 31:0 + Subspan 0, Pixel 3 (lower right) Red + + W0.2 31:0 + Subspan 0, Pixel 2 (lower left) Red + + W0.1 31:0 + Subspan 0, Pixel 1 (upper right) Red + + W0.0 31:0 + Supspan 0, Pixel 0 (upper left) Red + + W1.7 31:0 + Subspan 3, Pixel 3 (lower right) Red + + W1.6 31:0 + Subspan 3, Pixel 2 (lower left) Red + + W1.5 31:0 + Subspan 3, Pixel 1 (upper right) Red + + W1.4 31:0 + Supspan 3, Pixel 0 (upper left) Red + + W1.3 31:0 + Subspan 2, Pixel 3 (lower right) Red + + W1.2 31:0 + Subspan 2, Pixel 2 (lower left) Red + + W1.1 31:0 + Subspan 2, Pixel 1 (upper right) Red + + W1.0 31:0 + Supspan 2, Pixel 0 (upper left) Red + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 142 + DWord Bit Description + W2 + Subspans 1 and 0 of Green: See W0 definition for pixel locations + + W3 + Subspans 3 and 2 of Green: See W1 definition for pixel locations + + W4 + Subspans 1 and 0 of Blue: See W0 definition for pixel locations + + W5 + Subspans 3 and 2 of Blue: See W1 definition for pixel locations + + W6 + Subspans 1 and 0 of Alpha: See W0 definition for pixel locations + + W7 + Subspans 3 and 2 of Alpha: See W1 definition for pixel locations + +W8.7:1 Reserved (not written): W8 is only delivered when Pixel Fault Mask Enable is enabled. +W8.0 31:16 Reserved: always written as 0xffff + 15:0 Pixel Fault Mask: This field has the bit for all pixels set to 1 except those pixels in which a page fault + has occurred. + + +2.13.2.2 SIMD8/SIMD8D +This writeback message consists of four registers, or five in the case of sample+killpix. As opposed to the +SIMD16 writeback message, channels that are masked in the write channel mask are not skipped, all four +channels are always returned. The masked channels, however, are not overwritten in the destination +register. +For the sample+killpix message types, an additional register (W4) is included after the last channel +register. +DWord Bits Description + W0.7 31:0 + Subspan 1, Pixel 3 (lower right) Red: Specifies the value of the pixel’s red channel. + Format = IEEE Float, S31 signed 2’s comp integer, or U32 unsigned integer. Format depends on the + Data Return Format programmed for the surface being sampled. + +W0.6 31:0 + Subspan 1, Pixel 2 (lower left) Red + +W0.5 31:0 + Subspan 1, Pixel 1 (upper right) Red + +W0.4 31:0 + Supspan 1, Pixel 0 (upper left) Red + +W0.3 31:0 + Subspan 0, Pixel 3 (lower right) Red + +W0.2 31:0 + Subspan 0, Pixel 2 (lower left) Red + +W0.1 31:0 + Subspan 0, Pixel 1 (upper right) Red + +W0.0 31:0 + Supspan 0, Pixel 0 (upper left) Red + + W1 + Subspans 1 and 0 of Green: See W0 definition for pixel locations + + W2 + Subspans 1 and 0 of Blue: See W0 definition for pixel locations + + W3 + Subspans 1 and 0 of Alpha: See W0 definition for pixel locations + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 143 + DWord Bits Description +W4.7:1 + Reserved (not written) : This W4 is only delivered for the sample+killpix message type + +W4.0 31:16 + Dispatch Pixel Mask: This field is always 0xffff to allow dword-based ANDing with the R0 header in + the pixel shader thread. + + 15:0 + Active Pixel Mask: This field has the bit for all pixels set to 1 except those pixels that have been killed + as a result of chroma key with kill pixel mode. Since the SIMD8 message applies to only 8 pixels, only + the low 8 bits within this field are used. The high 8 bits are always set to 1. + Errata: Active Pixel Mask needs to be ORed with the inverse of the EMask before it is ANDed with the + DMask. Also if the sample instruction is within a conditional then the active pixel mask will be + overwritten with the partial mask on each different sample instruction so this will have to be done for + each instance of the sample instruction not just as the end. +W4.7:1 Reserved (not written): This W4 is only delivered when Pixel Fault Mask Enable is enabled. +W4.0 31:8 Reserved: always written as 0xffffff + 7:0 Pixel Fault Mask: This field has the bit for all pixels set to 1 except those pixels in which a page fault + has occurred. + + +2.13.2.3 SIMD4x2 +A SIMD4x2 writeback message always consists of a single message register containing all four channels +of each of the two “pixels” (called “samples” here, as they are not really pixels) of data. The write channel +mask bits as well as the execution mask on the “send” instruction are used to determine which of the +channels in the destination register are overwritten. If any of the four execution mask bits for a sample is +asserted, that sample is considered to be active. The active channels in the write channel mask will be +written in the destination register for that sample. If the sample is inactive (all four execution mask bits +deasserted), none of the channels for that sample will be written in the destination register. +DWord Bit Description + W0.7 31:0 + Sample 1 Alpha: Specifies the value of the pixel’s alpha channel. + Format = IEEE Float, S31 signed 2’s comp integer, or U32 unsigned integer. Format depends on the + Data Return Format programmed for the surface being sampled. + +W0.6 31:0 + Sample 1 Blue + +W0.5 31:0 + Sample 1 Green + +W0.4 31:0 + Sample 1 Red + +W0.3 31:0 + Sample 0 Alpha + +W0.2 31:0 + Sample 0 Blue + +W0.1 31:0 + Sample 0 Green + +W0.0 31:0 + Sample 0 Red + +W1.7:1 Reserved (not written) : W4 is only delivered when Pixel Fault Mask Enable is enabled. +W1.0 31:2 Reserved: always written as 0x3fffffff + 1:0 Pixel Fault Mask: This field has the bit for all samples set to 1 except those pixels in which a page fault + has occurred. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 144 + 2.13.2.4 SIMD32/64 + +2.13.2.4.1 Sample_unorm* +Pixels are numbered as follows: + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + +Which registers are returned is determined by the write channel mask received in the corresponding input +message. Each asserted write channel mask results in both destination registers of the corresponding +channel being skipped in the writeback message, and all channels with higher numbered registers being +dropped down to fill in the space occupied by the masked channel. For example, if only red and alpha are +enabled, red is sent to regid+0 and regid+1, and alpha to regid+2 and regid+3 (using 16 bit Full mode as +an example). +“16 bit Full” Output Format Control Mode +DWord Bit Description + W0.7 31:16 + Pixel 15 Red + Format = 16-bit UNORM with an 8-bit range (the value FF00h maps to a real value of 1.0) + Range = [0000h:FF00h] + 15:0 + Pixel 14 Red + +W0.6 + Pixel 13 & 12 Red + +W0.5 + Pixel 11 & 10 Red + +W0.4 + Pixel 9 & 8 Red + +W0.3 + Pixel 7 & 6 Red + +W0.2 + Pixel 5 & 4 Red + +W0.1 + Pixel 3 & 2 Red + +W0.0 + Pixel 1 & 0 Red + +W1.7 + Pixel 31 & 30 Red + +W1.6 + Pixel 29 & 28 Red + +W1.5 + Pixel 27 & 26 Red + +W1.4 + Pixel 25 & 24 Red + +W1.3 + Pixel 23 & 22 Red + +W1.2 + Pixel 21 & 20 Red + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 145 + DWord Bit Description + W1.1 + Pixel 19 & 18 Red + +W1.0 + Pixel 17 & 16 Red + + W2 + Pixels 15:0 Green + + W3 + Pixels 31:16 Green + + W4 + Pixels 15:0 Blue + + W5 + Pixels 31:16 Blue + + W6 + Pixels 15:0 Alpha + + W7 + Pixels 31:16 Alpha + +“16 Bit Chrominance Downsampled” Output Format Control Mode +In this mode the odd pixel red & blue channels are not included. +DWord Bit Description + W0.7 31:16 + Pixel 30 Red + Format = 16-bit UNORM with an 8-bit range (the value FF00h maps to a real value of 1.0) + Range = [0000h:FF00h] + 15:0 + Pixel 28 Red + +W0.6 + Pixel 26 & 24 Red + +W0.5 + Pixel 22 & 20 Red + +W0.4 + Pixel 18 & 16 Red + +W0.3 + Pixel 14 & 12 Red + +W0.2 + Pixel 10 & 8 Red + +W0.1 + Pixel 6 & 4 Red + +W0.0 + Pixel 2 & 0 Red + +W1.7 31:16 + Pixel 15 Green + + 15:0 + Pixel 14 Green + +W1.6 + Pixel 13 & 12 Green + +W1.5 + Pixel 11 & 10 Green + +W1.4 + Pixel 9 & 8 Green + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 146 + DWord Bit Description + W1.3 + Pixel 7 & 6 Green + +W1.2 + Pixel 5 & 4 Green + +W1.1 + Pixel 3 & 2 Green + +W1.0 + Pixel 1 & 0 Green + +W2.7 + Pixel 31 & 30 Green + +W2.6 + Pixel 29 & 28 Green + +W2.5 + Pixel 27 & 26 Green + +W2.4 + Pixel 25 & 24 Green + +W2.3 + Pixel 23 & 22 Green + +W2.2 + Pixel 21 & 20 Green + +W2.1 + Pixel 19 & 18 Green + +W2.0 + Pixel 17 & 16 Green + +W3.7 31:16 + Pixel 30 Blue + + 15:0 + Pixel 28 Blue + +W3.6 + Pixel 26 & 24 Blue + +W3.5 + Pixel 22 & 20 Blue + +W3.4 + Pixel 18 & 16 Blue + +W3.3 + Pixel 14 & 12 Blue + +W3.2 + Pixel 10 & 8 Blue + +W3.1 + Pixel 6 & 4 Blue + +W3.0 + Pixel 2 & 0 Blue + +W4.7 31:16 + Pixel 15 Alpha + + 15:0 + Pixel 14 Alpha + +W4.6 + Pixel 13 & 12 Alpha + +W4.5 + Pixel 11 & 10 Alpha + +W4.4 + Pixel 9 & 8 Alpha + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 147 + DWord Bit Description + W4.3 + Pixel 7 & 6 Alpha + +W4.2 + Pixel 5 & 4 Alpha + +W4.1 + Pixel 3 & 2 Alpha + +W4.0 + Pixel 1 & 0 Alpha + +W5.7 + Pixel 31 & 30 Alpha + +W5.6 + Pixel 29 & 28 Alpha + +W5.5 + Pixel 27 & 26 Alpha + +W5.4 + Pixel 25 & 24 Alpha + +W5.3 + Pixel 23 & 22 Alpha + +W5.2 + Pixel 21 & 20 Alpha + +W5.1 + Pixel 19 & 18 Alpha + +W5.0 + Pixel 17 & 16 Alpha + +“8 Bit Full” Output Format Control Mode +DWord Bit Description + W0.7 31:24 + Pixel 31 Red + Format = 8-bit UNORM + Range = [00h:FFh] + 23:16 + Pixel 30 Red + + 15:8 + Pixel 29 Red + + 7:0 + Pixel 28 Red + +W0.6 + Pixel 27:24 Red + +W0.5 + Pixel 23:20 Red + +W0.4 + Pixel 19:16 Red + +W0.3 + Pixel 15:12 Red + +W0.2 + Pixel 11:8 Red + +W0.1 + Pixel 7:4 Red + +W0.0 + Pixel 3:0 Red + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 148 + DWord Bit Description + W1 + Pixels 31:0 Green + + W2 + Pixels 31:0 Blue + + W3 + Pixels 31:0 Alpha + +“8 Bit Chrominance Downsampled” Output Format Control Mode +If either red or blue channel (but not both) are masked, the W0 register is included in the payload but the +masked channel is not written to the GRF. If both are masked, W0 is not included in the payload +(reducing the response length by one). +DWord Bit Description + W0.7 31:24 + Pixel 30 Red + Format = 16-bit UNORM with an 8-bit range (the value FF00h maps to a real value of 1.0) + Range = [0000h:FF00h] + 23:16 + Pixel 28 Red + + 15:8 + Pixel 26 Red + + 7:0 + Pixel 24 Red + +W0.6 + Pixel 22, 20, 18, 16 Red + +W0.5 + Pixel 14, 12, 10, 8 Red + +W0.4 + Pixel 6, 4, 2, 0 Red + +W0.3 + Pixel 30, 28, 26, 24 Blue + +W0.2 + Pixel 22, 20, 18, 16 Blue + +W0.1 + Pixel 14, 12, 10, 8 Blue + +W0.0 + Pixel 6, 4, 2, 0 Blue + +W1.7 31:24 + Pixel 31 Green + + 23:16 + Pixel 30 Green + + 15:8 + Pixel 29 Green + + 7:0 + Pixel 28 Green + +W1.6 + Pixel 27:24 Green + +W1.5 + Pixel 23:20 Green + +W1.4 + Pixel 19:16 Green + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 149 + DWord Bit Description + W1.3 + Pixel 15:12 Green + + W1.2 + Pixel 11:8 Green + + W1.1 + Pixel 7:4 Green + + W1.0 + Pixel 3:0 Green + + W2.7 + Pixel 31:28 Alpha + + W2.6 + Pixel 27:24 Alpha + + W2.5 + Pixel 23:20 Alpha + + W2.4 + Pixel 19:16 Alpha + + W2.3 + Pixel 15:12 Alpha + + W2.2 + Pixel 11:8 Alpha + + W2.1 + Pixel 7:4 Alpha + + W2.0 + Pixel 3:0 Alpha + +Additional Writeback Phase for sample_unorm+killpix +For the sample_unorm+killpix messages, an additional writeback phase is returned. The value of “n” +depends on which channels are enabled for return and the Output Format Control Mode, this register +will immediately follow the first part of the writeback message. +DWord Bit Description +Wn.7:1 Reserved (not written) + Wn.0 31:0 + Active Pixel Mask: This field has the bit for all pixels set to 1 except those pixels that have been killed + as a result of chroma key with kill pixel mode. + + + The bits in this mask correspond to the pixels as follows and they are listed from upper left (MSB) lower + right LSB: + 31 30 29 28 27 26 25 24 + 23 22 21 20 19 18 17 16 + 15 14 13 12 11 10 9 8 + 7 6 5 4 3 2 1 0 + + +2.13.2.5 Sample_8x8 Writeback Messages + +2.13.2.5.1 Sample_8x8 Writeback Messages +The writeback message for sample_8x8 consists of up to 16 destination registers. Which registers are +returned is determined by the write channel mask received in the corresponding input message. Each +asserted write channel mask results in all four destination registers of the corresponding channel being + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 150 + skipped in the writeback message, and all channels with higher numbered registers being dropped down +to fill in the space occupied by the masked channel. +Pixels are numbered as follows: + 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 + +“16 bit Full” Output Format Control Mode + +DWord Bit Description + + W0.7 31:16 + Pixel 15 Red + Format = 16-bit UNORM with an 8-bit range (the value FF00h maps to a real value of 1.0) + Range = [0000h:FF00h] + 15:0 + Pixel 14 Red + + W0.6 + Pixel 13 & 12 Red + + W0.5 + Pixel 11 & 10 Red + + W0.4 + Pixel 9 & 8 Red + + W0.3 + Pixel 7 & 6 Red + + W0.2 + Pixel 5 & 4 Red + + W0.1 + Pixel 3 & 2 Red + + W0.0 + Pixel 1 & 0 Red + + W1 + Pixel 31:16 Red + + W2 + Pixels 47:32 Red + + W3 + Pixels 63:33 Red + + W4 + Pixels 15:0 Green + + W5 + Pixels 31:16 Green + + W6 + Pixels 47:32 Green + + W7 + Pixels 63:33 Green + + W8 + Pixels 15:0 Blue + + W9 + Pixels 31:16 Blue + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 151 + W10 + Pixels 47:32 Blue + + W11 + Pixels 63:33 Blue + + W12 + Pixels 15:0 Alpha + + W13 + Pixels 31:16 Alpha + + W14 + Pixels 47:32 Alpha + + W15 + Pixels 63:33 Alpha + +“16 Bit Chrominance Downsampled” Output Format Control Mode +In this mode the odd pixel red & blue channels are not included. + +DWord Bit Description + + W0.7 31:16 + Pixel 30 Red + Format = 16-bit UNORM with an 8-bit range (the value FF00h maps to a real value of 1.0) + Range = [0000h:FF00h] + 15:0 + Pixel 28 Red + + W0.6 + Pixel 26 & 24 Red + + W0.5 + Pixel 22 & 20 Red + + W0.4 + Pixel 18 & 16 Red + + W0.3 + Pixel 14 & 12 Red + + W0.2 + Pixel 10 & 8 Red + + W0.1 + Pixel 6 & 4 Red + + W0.0 + Pixel 2 & 0 Red + + W1.7 + Pixel 62 & 60 Red + + W1.6 + Pixel 58 & 56 Red + + W1.5 + Pixel 54 & 52 Red + + W1.4 + Pixel 50 & 48 Red + + W1.3 + Pixel 46 & 44 Red + + W1.2 + Pixel 42 & 40 Red + + W1.1 + Pixel 38 & 36 Red + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 152 + W1.0 + Pixel 34 & 32 Red + + W2.7 31:16 + Pixel 15 Green + + 15:0 + Pixel 14 Green + + W2.6 + Pixel 13 & 12 Green + + W2.5 + Pixel 11 & 10 Green + + W2.4 + Pixel 9 & 8 Green + + W2.3 + Pixel 7 & 6 Green + + W2.2 + Pixel 5 & 4 Green + + W2.1 + Pixel 3 & 2 Green + + W2.0 + Pixel 1 & 0 Green + + W3 + Pixel 31:16 Green + + W4 + Pixel 47:32 Green + + W5 + Pixel 63:48 Green + + W6.7 31:16 + Pixel 30 Blue + + 15:0 + Pixel 28 Blue + + W6.6 + Pixel 26 & 24 Blue + + W6.5 + Pixel 22 & 20 Blue + + W6.4 + Pixel 18 & 16 Blue + + W6.3 + Pixel 14 & 12 Blue + + W6.2 + Pixel 10 & 8 Blue + + W6.1 + Pixel 6 & 4 Blue + + W6.0 + Pixel 2 & 0 Blue + + W7.7 + Pixel 62 & 60 Blue + + W7.6 + Pixel 58 & 56 Blue + + W7.5 + Pixel 54 & 52 Blue + + W7.4 + Pixel 50 & 48 Blue + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 153 + W7.3 + Pixel 46 & 44 Blue + + W7.2 + Pixel 42 & 40 Blue + + W7.1 + Pixel 38 & 36 Blue + + W7.0 + Pixel 34 & 32 Blue + + W8.7 31:16 + Pixel 15 Alpha + + 15:0 + Pixel 14 Alpha + + W8.6 + Pixel 13 & 12 Alpha + + W8.5 + Pixel 11 & 10 Alpha + + W8.4 + Pixel 9 & 8 Alpha + + W8.3 + Pixel 7 & 6 Alpha + + W8.2 + Pixel 5 & 4 Alpha + + W8.1 + Pixel 3 & 2 Alpha + + W8.0 + Pixel 1 & 0 Alpha + + W9 + Pixel 31:16 Alpha + + W10 + Pixel 47:32 Alpha + + W11 + Pixel 63:48 Alpha + +“8 Bit Full” Output Format Control Mode + +DWord Bit Description + + W0.7 31:24 + Pixel 31 Red + Format = 8-bit UNORM + Range = [00h:FFh] + + 23:16 + Pixel 30 Red + + 15:8 + Pixel 29 Red + + 7:0 + Pixel 28 Red + + W0.6 + Pixel 27:24 Red + + W0.5 + Pixel 23:20 Red + + W0.4 + Pixel 19:16 Red + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 154 + W0.3 + Pixel 15:12 Red + + W0.2 + Pixel 11:8 Red + + W0.1 + Pixel 7:4 Red + + W0.0 + Pixel 3:0 Red + + W1.7 + Pixel 63:60 Red + + W1.6 + Pixel 59:56 Red + + W1.5 + Pixel 55:52 Red + + W1.4 + Pixel 51:48 Red + + W1.3 + Pixel 47:44 Red + + W1.2 + Pixel 43:40 Red + + W1.1 + Pixel 39:36 Red + + W1.0 + Pixel 35:52 Red + + W2 + Pixels 31:0 Green + + W3 + Pixels 63:32 Green + + W4 + Pixels 31:0 Blue + + W5 + Pixels 63:32 Blue + + W6 + Pixels 31:0 Alpha + + W7 + Pixels 63:32 Alpha + +“8 Bit Chrominance Downsampled” Output Format Control Mode + +DWord Bit Description + + W0.7 31:24 + Pixel 62 Red + Format = 8-bit UNORM + Range = [00h:FFh] + 23:16 + Pixel 60 Red + + 15:8 + Pixel 58 Red + + 7:0 + Pixel 56 Red + + W0.6 + Pixel 54, 52, 50, 48 Red + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 155 + W0.5 + Pixel 46, 44, 42, 40 Red + + W0.4 + Pixel 38, 36, 34, 32 Red + + W0.3 + Pixel 30, 28, 26, 24 Red + + W0.2 + Pixel 22, 20, 18, 16 Red + + W0.1 + Pixel 14, 12, 10, 8 Red + + W0.0 + Pixel 6, 4, 2, 0 Red + + 31:24 + W1.7 Pixel 31 Green + + 23:16 + Pixel 30 Green + + 15:8 + Pixel 29 Green + + 7:0 + Pixel 28 Green + + W1.6 + Pixel 27:24 Green + + W1.5 + Pixel 23:20 Green + + W1.4 + Pixel 19:16 Green + + W1.3 + Pixel 15:12 Green + + W1.2 + Pixel 11:8 Green + + W1.1 + Pixel 7:4 Green + + W1.0 + Pixel 3:0 Green + + W2 + Pixel 63:32 Green + + W3.7 31:24 + Pixel 62 Blue + + 23:16 + Pixel 60 Blue + + 15:8 + Pixel 58 Blue + + 7:0 + Pixel 56 Blue + + W3.6 + Pixel 54, 52, 50, 48 Blue + + W3.5 + Pixel 46, 44, 42, 40 Blue + + W3.4 + Pixel 38, 36, 34, 32 Blue + + W3.3 + Pixel 30, 28, 26, 24 Blue + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 156 + W3.2 + Pixel 22, 20, 18, 16 Blue + + W3.1 + Pixel 14, 12, 10, 8 Blue + + W3.0 + Pixel 6, 4, 2, 0 Blue + + W4.7 31:24 + Pixel 31 Alpha + + 23:16 + Pixel 30 Alpha + + 15:8 + Pixel 29 Alpha + + 7:0 + Pixel 28 Alpha + + W4.6 + Pixel 27:24 Alpha + + W4.5 + Pixel 23:20 Alpha + + W4.4 + Pixel 19:16 Alpha + + W4.3 + Pixel 15:12 Alpha + + W4.2 + Pixel 11:8 Alpha + + W4.1 + Pixel 7:4 Alpha + + W4.0 + Pixel 3:0 Alpha + + W5 + Pixel 63:32 Alpha + + + +2.13.2.6 Deinterlace +The deinterlace message has three different writeback messages, depending on the DI Enable and DI +Partial fields of SAMPLER_STATE. +Pixels are indicated by an (X, Y) pair. The following tables indicate the format of common Luma, +Chroma, STMM, and Block Noise Estimate/Denoise History blocks defined as portions of the specific +writeback messages defined in the following sections. Each block defines one register. +Luma block definition: +DWord Bit Description + Wn.7 31:24 + Luma (15,1) + Format = U8 + 23:16 + Luma (14,1) + + 15:8 + Luma (13,1) + + 7:0 + Luma (12,1) + +Wn.6 31:0 + Luma (11:8,1) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 157 + DWord Bit Description + Wn.5 31:0 + Luma (7:4,1) + +Wn.4 31:0 + Luma (3:0,1) + +Wn.3 31:0 + Luma (15:12,0) + +Wn.2 31:0 + Luma (11:8,0) + +Wn.1 31:0 + Luma (7:4,0) + +Wn.0 31:0 + Luma (3:0,0) + +Chroma block definition: +DWord Bit Description + Wp.7 31:24 + Cb (14,1) + Format = U8 + + 23:16 + Cr (14,1) + Format = U8 + 15:8 + Cb (12,1) + + 7:0 + Cr (12,1) + +Wp.6 31:0 + Cr & Cb (10:8,1) + +Wp.5 31:0 + Cr & Cb (6:4,1) + +Wp.4 31:0 + Cr & Cb (2:0,1) + +Wp.3 31:0 + Cr & Cb (14:12,0) + +Wp.2 31:0 + Cr & Cb (10:8,0) + +Wp.1 31:0 + Cr & Cb (6:4,0) + +Wp.0 31:0 + Cr & Cb (2:0,0) + +STMM block definition: +DWord Bit Description + Wr.7 31:24 + STMM (14,3) + Format = U8 + 23:16 + STMM (12,3) + + 15:8 + STMM (10,3) + + 7:0 + STMM (8,3) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 158 + DWord Bit Description + Wr.6 31:0 + STMM (6:0,3) + + Wr.5 31:0 + STMM (14:8,2) + + Wr.4 31:0 + STMM (6:0,2) + + Wr.3 31:0 + STMM (14:8,1) + + Wr.2 31:0 + STMM (6:0,1) + + Wr.1 31:0 + STMM (14:8,0) + + Wr.0 31:0 + STMM (6:0,0) + +Block Noise Estimate/Denoise History block definition: [prior to Gen6] +DWord Bit Description + Wq.7 31:0 Reserved : MBZ + Wq.6 31:0 Reserved : MBZ + Wq.5 31:0 Reserved : MBZ + Wq.4 31:0 Reserved : MBZ + Wq.3 31:0 Reserved : MBZ + Wq.2 31:0 Reserved : MBZ + Wq.1 31:8 Reserved : MBZ + Wq.1 7:0 + Block Noise Estimate + Format = U8 +Wq.0 31:24 + Denoise History for 4x4 at Y = 15 to 12, X = 3 to 0 + Format = U8 +Wq.0 23:16 + Denoise History for 4x4 at Y = 11 to 8, X = 3 to 0 + +Wq.0 15:8 + Denoise History for 4x4 at Y = 7 to 4, X = 3 to 0 + +Wq.0 7:0 + Denoise History for 4x4 at Y = 3 to 0, X = 3 to 0 + +Block Noise Estimate/Denoise History block definition: [ Gen6] +Wq.7 31:16 + Y[15:0] - For a 1080 screen & 4 high blocks we need 9-bits + +Wq.7 15:0 + X[15:0] – for a 2048 screen & 16 wide block we need 7-bits + + 31:24 +Wq.6 STAD0 – Sum in time of absolute differences for 16x8 (DN only) or 16x4 (DN/DI) + Format = U8 + 23:16 +Wq.6 STAD1 + +Wq.6 15:8 + STAD2 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 159 + Wq.6 7:0 + STAD3 + + 31:24 +Wq.5 SHCM0 – Sum horizontaly of absolute differences + + 23:16 +Wq.5 SHCM1 + +Wq.5 15:8 + SHCM2 + +Wq.5 7:0 + SHCM3 + + 31:24 +Wq.4 SVCM0 – Sum vertically of absolute differences. + + 23:16 +Wq.4 SVCH1 + + 15:8 +Wq.4 SVCH2 + + 7:0 +Wq.4 SVCH3 + +Wq.3 31:16 FMD Variance[0] - Diff_cTpT – difference in top fields of current and previous frame + Format = U16 + +Wq.3 15:0 FMD Variance[1] – Diff_cBpB – difference in bottom field of current and previous frame + +Wq.2 31:16 FMD Variance[2] – Diff_cTcB – difference between top and bottom field in current frame. +Wq.2 + 15:0 FMD Variance[3] – Diff_cTpB – difference between current top and previous bottom + +Wq.1 31:16 FMD Variance[4] – Diff_cBpT – difference between current bottom and previous top. +Wq.1 15:8 + FMD Variance[7] – sum of pixels that are moving (different above a threshold) + Format = U8 + +Wq.1 +Wq.0 +Wq.0 +Wq.0 +Wq.0 + +Block Noise Estimate/Denoise History block definition: [Gen6 DI enabled] + +DWord Bit Description + + Wq.7 31:16 Y[15:0] – Location of 16x4 + Wq.7 15:0 X[15:0] - Location of 16x4 + Wq.6 31:24 + STAD0 - Sum in time of absolute differences for 4x4 + Format = U8 [STAD values are 0 if DN is disabled] + Wq.6 23:16 STAD1 + Wq.6 15:8 STAD2 + Wq.6 7:0 STAD3 (Ignore when both DN & DI are enabled) + Wq.5 31:24 + SHCM0 - Sum horizontally of absolute differences for 4x4 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 160 + Format = U8 [SHCM values are 0 if DN is disabled] + Wq.5 23:16 SHCM1 + Wq.5 15:8 SHCM2 + Wq.5 7:0 SHCM3 (Ignore when both DN & DI are enabled) + Wq.4 31:24 + SVCM0 Sum Vertically of absolute differences for 4x4 + Format = U8 [SVCM values are 0 if DN is disabled] + Wq.4 23:16 SVCM1 + Wq.4 15:8 SVCM2 + Wq.4 7:0 SVCM3 (Ignore when both DN & DI are enabled) + Wq.3 31:16 + Diff_cTpT - difference in top fields of current and previous frame + Format = U16 + + Wq.3 15:0 Diff_cBpB - difference in bottom field of current and previous frame + Wq.2 31:16 Diff_cTcB - difference between top and bottom field in current frame. + Wq.2 15:0 Diff_cTpB - difference between current top and previous bottom + Wq.1 31:16 Diff_cBpT - difference between current bottom and previous top. + Wq.1 15:8 + Motion_Count - number of pixels that are moving (different above a threshold) + Format = U8 + Wq.1 7:0 + Block Noise Estimate for 16x4 (Valid only if DN is enabled) + Wq.0 31:24 + Denoise History for 4x4 at Y = 15 to 12, X = 3 to 0 + Format = U8 + Wq.0 23:16 + Denoise History for 4x4 at Y = 11 to 8, X = 3 to 0 + + Wq.0 15:8 + Denoise History for 4x4 at Y = 7 to 4, X = 3 to 0 + + Wq.0 7:0 + Denoise History for 4x4 at Y = 3 to 0, X = 3 to 0 + +Block Noise Estimate/Denoise History block definition: [Gen6 DI disabled] + +DWord Bit Description + + Wq.7 31:16 Y[15:0] – Location of 16x4 + Wq.7 15:0 X[15:0] - Location of 16x4 + Wq.6 31:24 + STAD0 - Sum in time of absolute differences for 4x8 + Format = U8 + Wq.6 23:16 STAD1 + Wq.6 15:8 STAD2 + Wq.6 7:0 STAD3 + Wq.5 31:24 SHCM0 - Sum horizontally of absolute difference for 4x8 + Wq.5 23:16 SHCM1 + Wq.5 15:8 SHCM2 + Wq.5 7:0 SHCM3 + Wq.4 31:24 SVCM0 Sum Vertically of absolute difference for 4x8 + Wq.4 23:16 SVCM1 + Wq.4 15:8 SVCM2 + Wq.4 7:0 SVCM3 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 161 + Wq.3 31:16 Reserved + Wq.3 15:0 Reserved + Wq.2 Reserved + 31:8 + Wq.2 Block Noise Estimate for 16x8 + 7:0 + Wq.1 31:24 + Denoise History for 4x4 at X = 15 to 12, Y = 7 to 4 + Format = U8 + + Wq.1 23:16 + Denoise History for 4x4 at X = 11 to 8, Y = 7 to 4 + + Wq.1 15:8 + Denoise History for 4x4 at X = 7 to 4, Y = 7 to 4 + + Wq.1 7:0 + Denoise History for 4x4 at X = 15 to 12, Y = 3 to 0 + + Wq.0 31:24 + Denoise History for 4x4 at Y = 15 to 12, X = 3 to 0 + Format = U8 + + Wq.0 23:16 + Denoise History for 4x4 at Y = 11 to 8, X = 3 to 0 + + Wq.0 15:8 + Denoise History for 4x4 at Y = 7 to 4, X = 3 to 0 + + Wq.0 7:0 + Denoise History for 4x4 at Y = 3 to 0, X = 3 to 0 + +Block Noise Estimate/Denoise History block definition: [Gen7 +] DI Enabled +DWord Bit Description + Wq.7 31:16 Y[15:0] + Wq.7 15:0 X[15:0] + Wq.6 31:16 + STAD - Sum in time of absolute differences for 16x4 – value is 0 if DN disabled. + Format = U16 + Wq.6 + 15:0 SHCM - Sum horizontaly of absolute differences – value is 0 if DN is disabled. + Format = U16 + Wq.5 + 31:16 SVCM - Sum vertically of absolute differences – value is 0 if DN is disabled.. + Format = U16 + + Wq.5 + 15:0 Diff_cTpT - sum of differences in top fields of current and previous frame + Format = U16 + Wq.4 + 31:16 Diff_cBpB - sum of differences in bottom field of current and previous frame + Format = U16 + Wq.4 + 15:0 Diff_cTcB -sum of differences between top and bottom field in current frame. + Format = U16 + + Wq.3 31:16 + Diff_cTpB - sum of differences between current top and previous bottom + Format = U16 + Wq.3 15:0 + Diff_cBpT - sum of differences between current bottom and previous top. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 162 + DWord Bit Description + Format = U16 + Wq.2 31:0 Reserved + Wq.1 + 31:24 Tearing_Count - number of pixels that have (diff_cTcB > diff_cTcT + diff_cBcB) + Format = U8 + + Wq.1 23:16 + Fitting_Count - number of pixels that have (diff_cTcB<=diff_cTcT + diff_cBcB) + Format = U8 + Wq.1 15:8 + Motion_Count - number of pixels that are moving (different above a threshold) + Format = U8 + Wq.1 7:0 + Block Noise Estimate + Format = U8 + Wq.0 31:24 + Denoise History for 4x4 at Y = 15 to 12, X = 3 to 0 + Format = U8 + + Wq.0 23:16 + Denoise History for 4x4 at Y = 11 to 8, X = 3 to 0 + + Wq.0 15:8 + Denoise History for 4x4 at Y = 7 to 4, X = 3 to 0 + + Wq.0 7:0 + Denoise History for 4x4 at Y = 3 to 0, X = 3 to 0 + +Block Noise Estimate/Denoise History block definition: [Gen7+] DI Disabled: +DWord Bit Description + Wq.7 31:16 Y[15:0] + Wq.7 15:0 X[15:0] + Wq.6 31:16 + STAD - Sum in time of absolute differences for top 16x4 + Format = U16 + Wq.6 15:0 + SHCM - Sum horizontaly of absolute differences for top 16x4 + Format = U16 + + Wq.5 31:16 + SVCM - Sum vertically of absolute differences for top 16x4 + Format = U16 + Wq.5 15:0 + STAD - Sum in time of absolute differences for bottom 16x4 + Format = U16 + Wq.4 31:16 + SHCM - Sum horizontaly of absolute differences for bottom 16x4 + Format = U16 + Wq.4 15:0 + SVCM - Sum vertically of absolute differences for bottom 16x4 + Format = U16 + + Wq.3 31:0 Reserved + Wq.2 31:8 Reserved + Wq.2 7:0 + Block Noise Estimate + Format = U8 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 163 + DWord Bit Description + Wq.1 31:24 + Denoise History for 4x4 at X = 15 to 12, Y = 7 to 4 + Format = U8 +Wq.1 23:16 Denoise History for 4x4 at X = 11 to 8, Y = 7 to 4 +Wq.1 15:8 Denoise History for 4x4 at X = 7 to 4, Y = 7 to 4 +Wq.1 7:0 Denoise History for 4x4 at X = 3 to 0, Y = 7 to 4 +Wq.0 31:24 + Denoise History for 4x4 at X = 15 to 12, Y = 3 to 0 + Format = U8 + +Wq.0 23:16 + Denoise History for 4x4 at X = 11 to 8, Y = 3 to 0 +Wq.0 15:8 + Denoise History for 4x4 at X = 7 to 4, Y = 3 to 0 +Wq.0 7:0 + Denoise History for 4x4 at X = 3 to 0, Y = 3 to 0 + +DI Enabled (Only) +This writeback message is returned when the DI Enable field in SAMPLER_STATE is enabled. The +response length possibilities are: +  DN Enabled & surface_format == 4:2:2 packed: 12 +  DN Enabled & surface_format != 4:2:2 packed: 11 +  DN Disabled: 10 +DWord Bit Description + W0 + Previous 2nd Field Deinterlaced Luma for Y=0,1 + Refer to Luma block above for definition. + W1 + Previous 2nd Field Deinterlaced Luma for Y=2,3 + + W2 + Previous 2nd Field Deinterlaced Chroma for Y=0,1 + Refer to Chroma block above for definition. + W3 + Previous 2nd Field Deinterlaced Chroma for Y=2,3 + + W4 + Current 1st Field Deinterlaced Luma for Y=0,1 + + W5 + Current 1st Field Deinterlaced Luma for Y=2,3 + + W6 + Current 1st Field Deinterlaced Chroma for Y=0,1 + + W7 + Current 1st Field Deinterlaced Chroma for Y=2,3 + + W8 + STMM + Refer to STMM block above for definition. + W9 + Block Noise Estimate/Denoise History + Refer to Block Noise Estimate/Denoise History block above for definition. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 164 + DWord Bit Description + W10 nd + Current 2 Field Luma for 16x2 + This register is only included if DN Enable is enabled. + + W11 + Current 2nd Field Chroma + This register is only included if DN Enable is enabled. + Only valid if input surface format is 4:2:2 + +The denoised luma for both the current 1st and 2nd field needs to be written out, but only the 2nd field has a +dedicated location. This is because the denoised data for the 1st field is in the deinterlaced output for the +1st field – Y=0 and Y=2 are the denoised data, while Y=1 and Y=3 either the deinterlaced lines or copied +from the previous or current frame if progressive. +DI Disabled +This writeback message is returned when the DI Enable field in SAMPLER_STATE is disabled. The DN +with DI disabled responses with a 16x8 block rather than a 16x4 with a response length of 9 for a 4:2:2 +input format, or 5 for other formats. Two denoised luma and chroma fields are combined into an +interleaved top/bottom format. + Description + W0 Luma for Y=0 & 1 + Refer to Luma block above for definition. + + W1 Luma for Y=2 & 3 + Refer to Luma block above for definition, but add 2 to Y to get location + + W2 Luma for Y=4 & 5 + + W3 Luma for Y=6 & 7 + +W4.7 31:16 Y[15:0] + Y co-ordinate of the current block within the frame + +W4.7 15:0 X[15:0] + X co-ordinate of the current block within the frame + +W4.6 31:24 STAD0 – Sum in time of absolute differences for the 1st 4x8 + Format = U8 + +W4.6 23:16 STAD1– Sum in time of absolute differences for the 2nd 4x8 +W4.6 + 15:8 STAD2 – Sum in time of absolute differences for the 3rd 4x8 +W4.6 + 7:0 STAD3 – Sum in time of aboslute differences for the 4th 4x8 + +W4.5 31:24 SHCM0 – Sum horizontaly of absolute differences + +W4.5 23:16 SHCM1 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 165 + Description +W4.5 + 15:8 SHCM2 +W4.5 + 7:0 SHCM3 + +W4.4 31:24 SVCM0 – Sum vertically of absolute differences. + +W4.4 23:16 SVCH1 + +W4.4 15:8 SVCH2 + +W4.4 7:0 SVCH3 + + Reserved : MBZ +W4.3 31:0 + + Reserved : MBZ +W4.2 31:8 + + 7:0 Block Noise Estimate + Format = U8 + +W4.1 31:24 Denoise History for 4x4 at X = 15 to 12, Y = 7 to 4 + + 23:16 Denoise History for 4x4 at X = 11 to 8, Y = 7 to 4 + + 15:8 Denoise History for 4x4 at X = 7 to 4, Y = 7 to 4 + + 7:0 Denoise History for 4x4 at X = 3 to 0, Y = 7 to 4 + +W4.0 31:24 Denoise History for 4x4 at X = 15 to 12, Y = 3 to 0 + + 23:16 Denoise History for 4x4 at X = 11 to 8, Y = 3 to 0 + + 15:8 Denoise History for 4x4 at X = 7 to 4, Y = 3 to 0 + + 7:0 Denoise History for 4x4 at X = 3 to 0, Y = 3 to 0 + + W5 Chroma for Y=0 & 1 + Refer to Chroma block above for definition. + Only delivered if input surface format is 4:2:2 + + W6 Chroma for Y=2 & 3 + Refer to Chroma block above for definition, but add 2 to Y to get location. + Only delivered if input surface format is 4:2:2 + + W7 Chroma for Y=4 & 5 + Only valid if input surface format is 4:2:2 + + W8 Chroma for Y=6 & 7 + Only sent if input surface format is 4:2:2 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 166 + 3. Shared Functions – Data Port +The Data Port provides all memory accesses for the subsystem other than those provided by the +sampling engine. These include render target writes, constant buffer reads, scratch space reads/writes, +and media surface accesses. +The diagram below shows the three parts of the Data Port (Sampler Cache, Constant Cache, and Render +Cache) and how they connect with the caches and memory subsystem. The execution units and sampling +engine are shown for clarity. + + + + +The kernel programs running in the execution units communicate with the data port via messages, the +same as for the other shared function units. The three data ports are considered to be separate shared +functions, each with its own shared function identifier. +The diagram below shows the four parts of the Data Port (Sampler Cache, Constant Cache, Data Cache +and Render Cache) and how they connect with the caches and memory subsystem. The execution units +and sampling engine are shown for clarity. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 167 + The kernel programs running in the execution units communicate with the data port via messages, the +same as for the other shared function units. The four data ports are considered to be separate shared +functions, each with its own shared function identifier. + + +3.1 Cache Agents +The data port allows access to memory via various caches. The choice of which cache to use for a given +application is dictated by its restrictions, coherency issues, and how heavily that cache is used for other +purposes. +The cache to use is selected by the shared function accessed. + + +3.1.1 Render Cache +The render cache is intended to be used for the following surfaces: + +  3D render target surfaces +  destination surfaces for media applications +  intermediate working surfaces for media applications +  scratch space buffers +  streamed vertex buffers + +The render cache is a read/write cache that supports 3D render target surfaces, media read/write +surfaces, and typed read/write surfaces. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 168 + 3.1.2 Data Cache +The data cache is a read/write cache that is coherent across the physical instances of this cache. It is +intended to be used for the following surfaces: + +  constant buffers +  destination surfaces for media applications +  intermediate working surfaces for media applications +  scratch space buffers +  general read/write access of surfaces +  atomic operations +  shared memory for GPGPU thread groups + +The data cache can be accessed via the Data Cache Data Port shared function, and via the load and +store EU messages. Ordering from a single thread is maintained when accessing the data cache using +only one of these mechanisms, but is not maintained when using both of these mechanisms from the +same thread. In these instances, software must ensure ordering by utilizing write commits and/or waiting +for read data to be returned. + + +3.1.3 Sampler Cache +The sampler cache is a read-only cache that supports both linear and tiled memory. In addition to being +used by the sampling engine (via the sampling engine messages), the sampler cache is intended to be +used for source surfaces in media applications via the data port. The same application may use the +sampler cache via the sampling engine and data port without flushing the pipeline between accesses. + + +3.2 Surfaces +The data elements accessed by the data port are called “surfaces”. There are two models used by the +data port to access these surfaces: surface state model and stateless model. + + +3.2.1 Surface State Model +The data port uses the binding table to bind indices to surface state, using the same mechanism used by +the sampling engine. The surface state model is used when a Binding Table Index (specified in the +message descriptor) of less than 255 is specified. In this model, the Binding Table Index is used to index +into the binding table, and the binding table entry contains a pointer to the SURFACE_STATE. +SURFACE_STATE contains the parameters defining the surface to be accessed, including its location, +format, and size. +This model is intended to be used for constant buffers, render target surfaces, and media surfaces. + + +3.2.2 Stateless Model +The stateless model is used when a Binding Table Index (specified in the message descriptor) of 255 is +specified. In this model, the binding table is not accessed, and the parameters that define the surface +state are overloaded as follows: + +  Surface Type = SURFTYPE_BUFFER +  Surface Format = R32G32B32A32_FLOAT + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 169 +  Vertical Line Stride = 0 +  Surface Base Address = General State Base Address + Immediate Base Address +  Buffer Size = checked only against General State Access Upper Bound +  Surface Pitch = 16 bytes +  Utilize Fence = false +  Tiled = false + +This model is primarily intended to be used for scratch space buffers. + + +3.2.3 Shared Local Memory (SLM) +The shared local memory (SLM) is a high bandwidth memory that is not backed up by system memory. It +is enabled by configuring the L3 cache to use a portion of its space for the SLM. One SLM is present in +each half slice, and its contents are shared between all of the active threads in that half slice. Its contents +are uninitialized after creation, and its contents disappear when deallocated. +The SLM is accessed when a Binding Table Index (specified in the message descriptor) of 254 is +specified. The binding table is not accessed, and the parameters that define the surface state are +overloaded as follows: + +  Surface Type = SURFTYPE_BUFFER +  Surface Format = RAW +  Surface Base Address = points to the start of the internal SLM (no memory address is applicable) +  Surface Pitch = 1 byte + +Due to the predefined surface state attributes for the SLM, only a subset of the data port messages can +be used. This includes the Byte Scattered Read/Write, Untyped Surface Read/Write, and Untyped Atomic +Operation messages. In addition, only the data cache data port is supported, the other data ports treat +Binding Table Index 254 as a normal surface state access. +Programming Note: Accesses to SLM don’t have any bounds checking. Addresses beyond the size +(64KB) of the SLM will wrap around. + + +3.3 Write Commit +For write messages, an optional write commit writeback message can be requested via the Send Write +Commit Message bit in the message descriptor. This bit causes a return message to the thread indicating +when the write has been committed to the in-order cache pipeline and it is safe to issue another access to +the same data with the assurance that it will happen after the first write. A read issued after the write +commit ensures that the read will get the newly written data, and another write issued after the write +commit will be the last to modify the data. "Committed" does not guarantee that the data has been +actually written to the memory subsystem, but only that the write has been scheduled and cannot be +passed by another read or write issued subsequently. +If Send Write Commit Message is used on a Flush Render Cache message, the write commit is sent +only when the render cache has completed its flush to memory. A read issued to another cache after the +write commit is received will be guaranteed to retrieve the “new” data that was written before the Flush +Render Cache message was issued. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 170 + The write commit does not modify the destination register, but merely clears the dependency associated +with the destination register. Thus, a simple “mov” instruction using the register as a source is sufficient to +wait for the write commit to occur. The following code sequence indicates this: +send r12 m1 DPWRITE; issue write to render cache +mov m1 r3; assemble read message +mov r12 r12; block on write commit +send r13 m1 DPREAD; read same location as write +Prior to End of Thread with a URB_WRITE, the kernel must ensure all writes are complete by sending the +final write as a committed write for all non-pixel shaders. + + +3.4 Read/Write Ordering +Reads and writes issued from the same thread are guaranteed to be processed in the same order as they +are issued. Software mechanisms must still ensure ordering of accesses issued from different threads. + + +3.5 Accessing Buffers +There are four data port messages used to access buffers. Three of these are used for both constant +buffers and scratch space buffers, the fourth is used by the geometry shader kernel to write to streamed +vertex buffers. All of these messages support only buffers, and can use the surface state model as well +as the stateless model. +The following table indicates the intended applications of each of the buffer messages. + Message Applications + OWord Block  constant buffer reads of a single constant or multiple contiguous constants + Read/Write +  scratch space reads/writes where the index for each pixel/vertex is the same +  block constant reads, scratch memory reads/writes for media + + OWord Dual  SIMD4x2 constant buffer reads where the indices of each vertex/pixel are different +Block Read/Write (if there are two indices and they are the same, hardware will optimize the cache + accesses and do only one cache access) +  SIMD4x2 scratch space reads/writes where the indices are different. + +DWord Scattered  SIMD8/16 constant buffer reads where the indices of each pixel are different (read + Read/Write one channel per message) +  SIMD8/16 scratch space reads/writes where the indices are different (read/write one + channel per message) +  general purpose DWord scatter/gathering, used by media + +Streamed Vertex  geometry shader streaming vertex data out + Buffer Write + +These messages generally ignore the surface format field of the state and perform no format conversion. +The exception is the Streamed Vertex Buffer Write, which uses the surface format field to determine only +how many channels are to be written. The data contained in each channel is still not converted in any +way. + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 171 + 3.6 Accessing Media Surfaces +The Media Block Read/Write message is intended to be used to access 2D media surfaces. The +message specifies an X/Y coordinate into the 2D surface as input. Since this message only supports 2D +surfaces, the stateless model cannot be used with this message. + + +3.6.1 Color Processing +The image enhancement color processing pipe, known as IECP or shortly CP. The pipe contains a couple +of functions: + +  Packer with 422 to 444 converter. +  Skin Tone detection & Enhancement (STDE). +  Color Gamut Compression (CGC) (added for +  TCCE - Automatic Contrast Enhancement (ACE) & Total Color Control (TCC). +  Procamp. +  Color Space Converter (CSC). +  repacker with 444 to 422 converter + +Since these functions are performed on per-pixel basis, IECP is integrated in Render Cache Pixel +Backend (RCPB). The operation of each functionality could be on/off through the enable bit of each +function. + Surface Format Name +R16G16B16A16_UNORM +B8G8R8A8_UNORM +R10G10B10A2_UNORM +R10G10B10A2_UNORM_SRGB +R8G8B8A8_UNORM +R8G8B8A8_UNORM_SRGB +B10G10R10A2_UNORM +B10G10R10A2_UNORM_SRGB +B8G8R8X8_UNORM +R16_UNORM +YCRCB_NORMAL +YCRCB_SWAPUVY +YCRCB_SWAPUV +YCRCB_SWAPY + + +3.6.1.1 Overview of color processing pipeline +The input message to IECP is 256 bits data from RCPB (contains 2 lines X 2 pixels per clock); along with +256 bits color enhancement state from ISC (State Arbitator for). This unpacker converts 256b into two +pixels per clock, 36 bits each. In case of 422 inputs the UV are the same for the two pixels in the pair (422 +to 444 conversion). +The Re-packer (the CSC) delivers 2 pixels in parallel, 36 bits each. The 2x2 message pixels are packed +again to 256b and sent with the outgoing message. The 256 bits are organized according to the data type +(422/444, 8/16 bits). In case of 422 output, the UV is the average of two adjacent pixels. Also the pipe +itself is 12bis/pixel component, in the output message it will be either 8 bit/pixel component (while taking +only the 8 MSB) or 16 bits/pixel component (while adding 0000 at the LSB). + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 172 + There is statistic information from ACE block (10 bit histogram, 1 bit aoi and 1bit skin pixel) to be sent to +VSC (Video Statistic Counter). VSC will process on these data and output the maximum and minimum +value of the luma values ( Ymax and Ymin) and the number of total skin pixels through MMIO. The +Software development can access these data through MMIO and performs the SW part of the color +processing algorithms. + + + + +The color-processing enables the user to customize visual quality of video playback on the PC platform. +The seven functions main goals can be summarized as: + +  422 to 444 converter and the 444 to 422 converter functions enable us some flexibility in the data + format input and output. +  Skin Tone Detection/Enhancement function detects skin like color and attempts to change the tone + based on user specified parameters to make it more palatable to the user. +  Automatic Contrast Enhancement increases details in dark and bright areas by changing the + contrast function in relation to frames luma histogram. +  Total color control allows the user to increase or decrease the color saturation of the six basic colors + (Red, Green, Blue, Magenta, Cyan, Yellow). +  Procamp enables the user to control the Brightness, Contrast, Saturation and the Hue. +  Color Space Converter enables the user to convert color space from YUV format to RGB. + +The module of color gamut compression is added among STDE and TCC/ACE in the below diagram. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 173 + The performance of IVB IECP pipe is improved to 4 pixels per clock for input video of 4:2:2 format and +maintained at 2 pixels per clock for input video of 4:4:4 format. +With this performance improvement for 4:2:2 input, there are a couple of addition/modification of IVB pipe +to the existing IECP pipe of GT. +The following changes are being done: +Unpacker : +The input format 4:2:2 and 4:4:4 are supported for unpacker. Input video of 4:2:2 format by default is +operating at 4 pixels per clock. Input video of 4:4:4 format by default is dependent of an auto UV detection +logic to determine if it is operating at 2 pixels per clock, or it could be operating at 4 pixels per clock if +detection logic identifies the “true” 4:2:2 format is contained. +A by default auto UV detection logic for the input video of 4:4:4 format tests the MSB 8-bits of the U, V +channel value. With the pixel layout below: + Pix_0 Pix_1 + Pix_2 Pix_3 + +The 4:2:2 format is detected if the below conditions are observed +U_pixel_0 = U_pixel_1 +U_pixel_2 = U_pixel_3 +V_pixel_0 = V_pixel_1 +V_pixel_2 = V_pixel_3 +When the 4:2:2 format is detected from the input video of 4:4:4 format, the performance improved mode +at 4 pixels per clock is applicable. Thus, the average of the U, V values in horizontal direction is used as +the U, V output to the remaining pipe. If UV detection logic cannot detect the input as 4:2:2 format, it will +operate as 4:4:4 mode. +There is a flag bit as the state parameters to force the operation in 4:2:2 mode () +when the input video is of 4:4:4 format. In this case, the horizontal average of U, V pixel values is taken +as the output values to the remaining pipe. A flag bit of state parameter,, is provided +to ensure the 4:4:4 operation for the input of 4:4:4 format. There is also a flag bit of state parameter to +force the operation in 4:4:4 mode () when the input video is of 4:2:2 format. In this +case, U, V pixel values are horizontally replicated as the output values to the remaining pipe. It is 2 + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 174 + pixel/clk when oris enabled and is 4 pixel/clk when +is enabled.. +In 4:2:2 mode, all the four Y-channels and two U, V channels in the 422 format as is to STD. No +sequencing. An example of the values Y_p0, Y_p1, Y_p2, Y_p3, U_p01, V_p01, U_p23, V_p23 are the +pixel values being sent to the pipe. +In 4:4:4 mode, 2 pixels (two Y, U, V, A channels) are forwarded per clock to STD. Sequencing is done +across two clocks. To keep the pipe with minimum changes the corresponding channels are sent like +below example: +Y_p0, X, Y_p1, X, U_p0, V_p0, U_p1, V_p1 are the pixel values which are sent to the pipe. Where “X” is +don’t care. +Skin tone detection /enhancement +For both 4:2:2/4:4:4 the detection in UV space is done for the two UV values independently. i.e. both the +rectangle and diamond std factor are calculated in similar way for both 4:2:2/4:4:4 format. Satnew and +HueNew are also calculated based on the two UV values based out of the PWL. +For the Y-factor calculation is done for 4 pixels. In case of 4:2:2 all four pixels are valid, but for 4:4:4 only +two pixels are valid. The factor calculated on UV space in step 1 is replicated for the horizontal pixels and +we get the effective four STD factors out of this step. +In VY-factor calculation, the V is replicated for the horizontal pixels i.e. pixel0 and pixel1 will use the same +V pixel01 value and pixel2 and pixel3 will use the same V pixel23 value. We will get four STD factors out +of this stage. For 4:2:2 mode, two resultant STD factors can be produced for skin tone enhancement or +later stage based on the horizontal minimum, maximum, or average of the STD factors, which can +specified via the state parameters  +In skin tone enhancement module, based on Y-channel, MVdark and MVbright are calculated for 4 pixels. +Then for 4:2:2 mode, the horizontal minimum, maximum, or average of MVdark values, which could be +specified via the state parameters  can be used to effect the new +Satnew and Huenew values. In 4:4:4, we use the corresponding MVdark/bright and discard the other i.e. +no averaging. +Delta U/V : For 4:2:2 mode, the two resultant STD factors froom step iii are used to derive Delta U/V. For +4:4:4 mode, the corresponding pixel STD factor is used. Out of this stage we always get two Delta U/V +values. +Finally only two updated U/V values using the above delta U/V values come out of the STDE pipe. +Color Gamut Compression: +For 4:2:2 mode, only two U/V values are received, and thus two Hue index are calculated and only two +vertex point (Lv, Cv) lookups is checked. +For both 4:2:2/4:4:4, there are 4pixel Y channels so 4 parallel out pixel detection occurs based on the +vertex points(Lv, Cv), U, V values. Four SF (scaling factor) are produced. +In 4:4:4 mode, only two of the above are valid and the rest two are discarded. Only the corresponding SF +is used to calculate the new U/V values. +In 4:2:2 mode, two SF values are produced based on the horizontal minimum, maximum, or average +value of SF, which could be specified via the state parameters . 4 updated Y +values and 2 U/V values are produced out of Gamut compression +TCC works on 2 UV values received from gamut compression and is 2wide for 4:2:2 mode. +ACE works on 4 Y pixel received from Gamut compression and is 4 wide + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 175 + Procamp optimizes and has 4pixel Y and 2pixel UV values and output the same in 4:2:2 mode +CSC optimized the UV portion and then uses the same result out for the 2 horizontal pixels and adds the +result to the individual Ypixels. From CSC we will get 4pixel out for 4:2:2 mode. +Repacker pack sends the data 4 pixels for 4:2:2 mode as is to RCPB, but in the case of 4:4:4 it will +combine the 2pixels received from CSC across 2 clocks before outputting the 4pixels to RCPB. + +3.6.1.2 Skin Tone Detection/Enhancement (STD/E) +The STD/E unit, composed of the Skin Tone Detection (STD) and Skin Tone Enhancement (STE) units, is +part of color processing pipe located at the Render Cache Pixel Backend (RCBP). +The main goal of the STD/E is to reproduce the skin colors in a way that is more palatable to the +observer, and by that to increase the sensed image quality. It may also pass indication of skin tones to +the TCC and ACE. +The STD unit detects the skin like colors and passes a grade of skin tone color to the STE. The STE +modify the saturation and Hue of the pixel. Both the STD and STE are per-pixel basis. The input pixels +are required to be on the YUV space. +The skin tone detected factor will be recorded as a 5-bit number and it will be passed to the module of +ACE and TCC to indicate the strength of skin tone likelihood. + +3.6.1.2.1 STD +The STD operates on digital images in the YUV color space. In these space the skin-tone region is +represented by the ellipse in the (U,V) subspace (chroma components), by a trapeze membership +function in the Y direction (luma component) and by a piece-wise linear classifier in the (V,Y) subspace. +U,V data is transformed into Hue and Saturation space through shifting and rotation +Step 1: shift rectangle +U_center = U –  + V_center = V -  +Step 2: rotate rectangle +Sat = -(U_center *  - V_center * ) + Hue = -(U_center *  + V_center * ) +Where: Sin =   and Cos =   +Rectangle skin-tone measure determination + +Skin-tone detection is described by a continue score on the [0,1] range, where a level 0 means not a skin +(SkinToneFactor = 0) , and a level 1 (SkinToneFactor = 1) means a full skin. In between, (0,1) region, we +have partial skin-tone detection. This partial skin-tone detection is controlled by a margin parameter, +which will be denoted by “”. The SkinToneFactor is expressed by 5 bits, and thus have values +in the [0,31] range. +if( abs(Sat) <= SatMax && abs(Hue) <= HueMax) +{ + if(HS_margin >= 5) + { + Sat_Factor = (Sat_max-abs(Sat)) / 2(HS_margin - 5); + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 176 + Hue_Factor = (Hue_max-abs(Hue)) / 2(HS_margin - 5); + } + else + { + Sat_Factor = (Sat_max-abs(Sat)) * 2(HS_margin - 5); + Hue_Factor = (Hue_max-abs(Hue)) * 2(HS_margin - 5); + } //end of if(HS_margin >= 5) + } +else +{ + Sat_Factor = 0; + Hue_Factor = 0; +} //end of if( abs(Sat) <= SatMax && abs(Hue) <= HueMax) +Sat_Factor = min(Sat_Factor,31); +Hue_Factor = min(Hue_Factor,31); +Rectagle_SkinToneFactor = min(Sat_Factor, Hue_Factor); +Rhombus skin tone detection determination + +Similar to the rectangle skin-tone measure, a rhombus-margin () is introduced. This +introduces a new rhombus region, inner to the original rhombus, in a similar happened with the rectangle. +There are two regions such that: outside the original rhombus a SkinToneFactor = 0 (not a skin); inside +the inner rhombus SkinToneFactor = 1 (full skin); in between 0 < SkinToneFactor < 1 indicating a partial +skin-tone detection. As in the rectangle case, the SkinToneFactor is expressed by 5 bits, and thus have +values in the [0,31] range. +A Diamond SkinToneFactor calculations algorithm is: +Dist = abs(Sat – Diamond_du) + Diamond_alpha(1/tan( )) * abs(Hue – +Diamond_dv); +//outside the diamond +if(Dist >= Diamond_TH) +{ + D_Factor = 0; //the point is out of the large rhombus +} +else if(Dist < (Diamond_TH - Diamond_margin)) + { + D_Factor = 31; //the point is inside the inner rhombus + } + else //the point is inbetween the outer and the inner rhombuses + { + if(Diamond_margin >= 5) + { + D_Factor = (Diamond_TH - Dist) / 2(Diamond_margin - 5); + } + else + { + D_Factor = (Diamond_TH - Dist) * 2(Diamond_margin - 5); + } // end of if(Diamond_margin >= 5) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 177 + } // if(D < (Diamond_TH - Diamond_margin)) + Diamond_SkinToneFactor = D_factor; + + + +Finally the level of the skin-tone detection in the (U,V) subspace is given by: + UV_SkinToneFactor = min(Rectangle_SkinToneFactor, Diamond_SkinToneFactor); +Detection in Y direction +The detection based on the Y-values, is given by a piece-wise linear membership function, which is +defined with 4 points ) (x=1, 2, 3, and 4). +if(Y >= Y_Point_0 && in_Y < Point_1) + Y_Factor = (Y – Y_Point_0) * Y_Slope_1; +else if(Y >= Point_1 && Y < Point_2) + Y_Factor = 31; + else if(Y >= Point_2 && Y < Point_3) + Y_Factor = (Point_3 - Y) * Y_Slope_2 + else + Y_Factor = 0; + +At the end of the process a double (min,max) clipping is applied: + Y_Factor = min(31,max(Y_Factor,0)); +The final Skin-Tone detection is is given by: + SkinToneFactor = min(UV_SkinToneFactor, Y_factor); +Detection in the VY plane (3D-like DTD) +The operation of the detection in VY plane is particularly enabled by  bit +It is known that the application of a three-dimensional (3D) classifier in the (Y,U,V) space, instead of a two +dimensional (2D) skin-tone detector in the (U,V) plane, is resulted in a better detection. Implementation +complexity of the full 3D classifier is too high, and forces us to approximate the classifier by more simple, +but useful methods. Skin-tone data distribution implies (it is almost convex, and has a predominate +directions) that the 3D classifier could be approximated by the intersection of the three 2D classifiers in +(U,V), (U,Y), and (V,Y) subspaces. The (U,V) subspace is the most important one it is already +approximated by the ellipse, as was described previously. Our study implies that the (V,Y) subspace is +the next most important one. Although the (U,Y) space carries the STD information, it is heavily +redundant and has the reduced importance. +Thus the approximation of 3D classifier is an intersection of (U,V) and (V,Y) two-dimensional classifiers. +The (V,Y) classifier is given by two piece-wise linear functions (PWLF), Each PWLF is composed of four +straight segments. Each segment is described by the three parameters (Point, Slope and bias). Thus a +single PWLF (lower or upper) is described by 12 parameters (4 points, 4 biases, 4 slopes). + The parameters of lower part are: 4 point PxL (x=0, 1, 2, 3), 4 bias BxL (x=0, 1, 2, 3) and 4 slope + SxL (x=0, 1, 2, 3). + + The parameters of upper part are: 4 point PxU (x=0, 1, 2, 3), 4 bias BxU (x=0, 1, 2, 3) and 4 slope + SxU (x=0, 1, 2, 3). + +There is Programming Restrictions to specify the parameters +The points must be in the non-decreasing order: P0 <= P1 <= P2 <= P3. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 178 + The parts must be continues on they ends. Thus the user: + (a). must set: P0L = P0U (continuity at the leftmost points). + (b). must care for continuity at the rightmost points. +Margin for the detection in the VY plane (3D-like DTD) +Vertical margins of each part were introduced to provide a “soft” continuous detection over the classifier +boundaries. There are two parameters defined +  - the margin of the lower (blue) part. +  - the margin of the upper (red) part. +Consider a pixel with coordinates (Y,V) = (P2L,V1),. This pixel has a Y coordinate exactly as of the point +P2, and a V coordinate equal V1. For this pixel the detection relative to the Lower Part will be: + detL = Min (Max ((V1 – B2L) / MarginVYL, 0), 1) +The identical calculations are made for the Upper Line as well: + detU = Min (Max ((VU – V1) / MarginVYU, 0) , 1) +Where: + detL - is a detection relative to the Lower Part + detU - is a detection relative to the Upper Part + VU - is a V value of the Upper PWLF correspond to the Y=P2L + BU - is a V value of the Lower PWLF correspond to the Y=P2L +The inverse operation of (1/ MarginVYL), and (1/ MarginVYU) is specified by the parameters +INV_ and . +Both detections (detL, detU) are reduced to 5 bit representations, and the overal detection in the (V,Y)- +plane is given by: + det_VY = min(detL, detU) +The final Skin-Tone Detection is given by the minimum of the previously calculated STD in the (U,V)- +plane (9), and the current one: + SkinToneFactor = min(SkinToneFactor, det_VY) +This value is represented with 5 bits, and has a [0,31] range. + +3.6.1.2.2 STE +The enhancement step is performed on the pixels which were detected as the skin-tone pixels only by the +previous (STD) step. This step is divided into two sub-steps: saturation correction enhancemen and hue +correction enhancement +STE – Saturation Correction Enhancement +The enhancement is performed by the transformation SatNew = FSat(SatOld), which is realized by the piece- +wise linear function (PWLF) with a 4 straight segments. +The parameters of this PWLF are: + +  Points: + +SATP0 = -SatMax + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 179 + (x=1,2,3) – defined by the user +SATP4 = SatMax + +  Biases: + +SATB0 = -SatMax + (x=1,2,3) – defined by the user +SATB4 = SatMax + +  Slopes: + + (x=0,1,2,3) – defined by the user +There is Programming Restrictions to specify the parameters +The point Sat = -SatMax maps to itself: (-SatMax) (-SatMax). +The point Sat = SatMax maps to itself: (SatMax) (SatMax). +The correction function is continuous. +The correction function is non-decreasing. +SatOld +SatNew +(-SatMax ,-SatMax) +(SatMax ,SatMax) +Identity +transformation +Fig.. General form of the Saturation correction PWLF. +Correction Function +STE – Hue Correction Enhancement +The enhancement is performed by the transformation HueNew = FSat(HueOld), which is realized by the piece- +wise linear function (PWLF) with a 4 straight segments. +The parameters of this PWLF are: + +  Points: + +HUEP0 = -HueMax +(x=1,2,3) – defined by the user +HUEP4 = HueMax + +  Biases: + +HUEB0 = -HueMax + (x=1,2,3) – defined by the user +HUEB4 = HueMax + +  Slopes: + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 180 +  (x=0,1,2,3) – defined by the user +There are Programming Restrictions to specify the parameters +The point Hue = -HueUEMax maps to itself: (-HueMax) (-HueMax). +The point Hue = HueMax maps to itself: (HueMax) (HueMax). +The correction function is continuous. +The correction function is non-decreasing. +HueOld +HueNew +(-HueMax,-HueMax) +(HueMax ,HueMax) +Identity +transformation +Fig. General form of the Hue correction PWLF. +Correction Function +STE – Skin Type Correction Enhancement +The operation of this mode is enabled by the control parameter . +The Saturation and Hue enhancement processes are basic STE procedure. The advanced mode to +adjust the enhacement based on the skin type define the second set of the Sat and the Hue +enhancement parameters, which has an identical structure as the previous one (Points, Biases, Slopes) +but having different values. We will refer one set of parameters to the Bright skin (Bs), and the other to +the Dark skin (Ds). Each pixel is referred as belongs to the Bright, the Dark, or to the both skin types with +a different membership values. The Dark/Bright skin classifier is defined by the two parameters: +, and . It works on the luma (Y) values. +The parameters related are +Points: +(x=1,2,3) – defined by the user +(x=1,2,3) – defined by the user +Biases: + (x=1,2,3) – defined by the user + (x=1,2,3) – defined by the user +Slopes: + (x=0,1,2,3) – defined by the user + (x=0,1,2,3) – defined by the user +For the luma value Y, we define + YA = skinTypesThesh - skinTypesMargin + YB = skinTypesThesh + skinTypesMargin + MVDark = 1 , if Y < YA + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 181 + = 0, if Y > YB + = (YB – Y) / (2* skinTypesMargin), if YA <= Y <= YB + MVBright = 1 - mVDark +Where MVDark and MVBright are the membership value of the Dark and Bright skin (belongnes). (Note: the +membership values represent the “belongness” of the skin pixel to the different skin types). Also, we mark +that the inversee operation of 1/(2* Skin_types_margin) wil be specified by the parameter +. +In previous sections the procedure for the calculation of the Sat New and HueNew values was described. We +calculate these values for the two skin types and thus get SatNew B, HueNew B, and SatNew D, HueNew D values , +where and subscribes “B” and “D” stands for the Bright and the Dark skin types, respectively. (In this +case, the parameters with “_DARK” extension are used to work out SatNew D and HueNew D, and the other +set of the parameter could be reloaded with the parameters to work out SatNew D, HueNew D.)The final values +of the enhanced pixel will be given by: +SatNew = MVDark * SatNew D + MVBright * SatNew B +HueNew = MVDark * HueNew D + MVBright * HueNew B +STE – (Sat, Hue) to (U, V) transformation +In prior session,, the (U,V) (Sat,Hue) transformation was proceeded by the two steps:  and +. Thus the backward transformation should be done in the inverse order: a , and then a +. + // Rotate back: + U_Center_New = (Sat_New * Cos) + (Hue_New * Sin) + V_Center_New = -(Sat_New * Sin) + (Hue_New * Cos) + // Shift: + U_New = U_Center_New + U_mid + + V_New = V_Center_New + V_mid +The (U_new, V_new) are the (SatNew, HueNew) values in transformed to the original (U,V) coordinates. +Let denote the original (U,V) values of the pixel by (U_in,V_in). Thus the difference between the corrected +and the original values are: + DU = U_new – U_in + DV = V_new – V_in +The final correction must be depended by the SkinToneFactor value, and therefore DU, DV are corrected +by: +DU = DU * STD_ Likelihood_Factor + +DV = DV * STD_ Likelihood_Factor +Where: +STD_ Likelihood_Factor = (SkinToneFactor / 32) +(Remember that the 0 <= SkinToneFactor <= 31). +After the DU and DV were corrected by the STD likelihood factor, the final (U,V) will be calculated by: +U = U_in + DU + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 182 + V = V_in + DV + + +3.6.1.2.3 STD Score Output +This mode outputs the STD score, which is controlled by the state bit “Output STD Decisions” instead of +the pixel values. In this mode, the STD should be enabled and other functions in the IECP after STDE in +the pipe should be disabled. Only ACE can be enabled to collect the histogram of the STD score values. +The output when “Output STD Decision” is enabled should be as follows: +Y = 0x7FF + + (STD_Score <<6) +U = 0x7FF +V = 0x7FF +In this mode, a histogram of skin tone distribution can be obtained in ACE module, and a special ACE +PWLF curve (step function) can be configurated to produce a bi-level picture to illustrate the pixels based +on the level of skin tone detection. + +3.6.1.3 Adaptive Contrast Enhancement (ACE) +The Automatic Contrast Enhancement (ACE) is a part of the color processing pipe, which located at the +render cache in the RCPB block. +The main goals of the ACE is to improve the overall contrast of the image, and emphasizing details when +relevant (such as in dark areas). +The ACE algorithm analyzes the image, and consequently changes contrast of the image according to its +characteristics. It works in YCbCr color space, where analysis and changes are performed over the Y +component. The result of ACE is a 1d (1 dimension) look up table (1D LUT) operating on Y. The ACE +follows the skin tone enhancement module in the pipe. +The ACE is receiving skin information from the STD block. When the frame includes skin the affect of the +ACE is reduced in the skin area. +The ACE operation is divided into three stages: + +  Collecting information on Y and building the picture histogram. (Hardware) +  Analysis on the collected data. (Software/Kernel) +  Modification of the Y component. (Hardware) + +The major steps of ACE can be divided into the following steps and depict in the below diagram. +1. Histogram calculation of the Y values. +2. Limiting extremely large histogram’s bins. +3. Calculate the Image’s gray level mean value (Ymean). +4. Calculate the Image’s “Dark Factor” by the Ymean and external transfer function. +5. Find the PWLF anchor input and output points according to the “Portion Values” and the “Destination + Points” of the Bright and the Dark images. +6. Find the PWLF anchor Input points by the blending of the Dark and Bright anchor input points, + according to the Dark Factor calculated previously. +7. Find the PWLF anchor Output points by the blending of the Dark and Bright anchor output points, + according to the Dark Factor calculated previously. +8. Limit Slopes between the anchor points. This stage’s output is the current’s image ACE PWLF. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 183 + 9. “Soften” the ACE PWLF by blending I with the Identity Transformation. +10. Blend the current PWLF with the PWLF of the previous image (History blend). +11. Apply the final PWLF, and get the Yout values. +Note: Step 1 & step 11 are done in HW and steps 2-10 are done in software. +The main ACE goals are overall contrast improvement, and details emphasizing. ACE algorithm +generates a Piece-wise Linear Function (PWLF), and the final gray values, Yout, are calculated by Yout = +PWLF(Yin). +The HW compares the input pixels to the  to determine if the target pixel is a skin pixel or +not. It operates on all of the input pixels if the  flag is defined. (to ignore the AOI +flag). HW output the histogram of luma pixel value to VSC, and at VSC, the maximum and minimum value +of luma pixels (Ymax, Ymin) ans the number of skin pixels is determined to be made available to the +software development via MMIO register. +An eleven-segment (12 points) was established to implement PWLF via the state parameters (Points: +, Bias: , Slope: ). + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 184 + 3.6.1.4 Total Color Control (TCC) +The TCC allows users to choose different grades of saturation for each of the six basic colors (Red, +Green, Blue, Magenta, Yellow and Cyan) in order to custom the color scheme. The TCC algorithm +operates on the UV-color components in the YUV color space. It operates in the pixel-wise mode, without +considering any neighborhood information. +Its input is: + +  U,V color components (10 bit) +  Skin-tone detection value (5 bit) +  External control parameters + +Its output is the new U, V values (10 bit). +The motivation to implement this block in HW is to reduce the power of the system and therefore the +battery life. +The pixel TPT (throughput) is two pixels per clock. The pipeline works in YUV formats only – 10bit pixels. +The TCC block is control by state only and does not require any memory access. The TCC block runs at +the same frequency of the existing RCPBunit. + + + + +There are two paths in parallel to support the requirement of two pixels per clock. Valid out is a signal +which high when the pixels are valid. +The TCC block includes three sub blocks. +Angle_calculator +This block receive pixel U and V and perform division of abs|v| by abs|u| using Divider ROM with pipeline. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 185 + The division result is used to calculated arctan of the V/U. This result is used to calculate the angle called +θ, by using approximation equation. This angle is defined as a 10bit. +To simplify this calculation the “arctangent” function is approximated in the [0,45] o region by the second +order polynomial: + = arctan(x) = -0.2880x2 + 1.0797x - 0.005; (0 <= x <= 1) +The resulted is given in radians with the maximal error of 0.005 rad. (0.286 deg.) This approximation is +calculated by the minimizing the mean squared error (mse) between the actual “arctan” function, and its +polynomial approximation, and thus represents the optimal mse-approximation in the [0, /4] region. The + for the all regions is calculated by: + 0.25 ; for region I, (0 <= x <= 1), + /2 – 0.25 ; for region II, (1 < (V/U) < infinity) + /2 + 0.25 ; for region III, (-infinity < (V/U) < -1) + = - 0.25 ; for region IV, (-1 <= (V/U) < 0) + + 0.25 ; for region V, (0 <= (V/U) <= 1) + 3 - 0.25 ; for region VI, (1 < (V/U) < infinity) + 3 + 0.25 ; for region VII, (-infinity < (V/U) < -1) + 2 - 0.25 ; for region VIII, (-1 <= (V/U) < 0) +Whereas x = (V/U), and the 0.25 is given by the above equation. +Saturation_Factor_Calculator +This block is using the angle θ, locate where it is in the color wheel, find the appropriate base colors and +calculate the proportional distance from the adjacent base color. The result called . Alpha ( ) +represent the distance from the two relevant base color. +Calculate the saturation by using the appropriate user parameters. The result is the Saturation factor. +This block considering also the threshold and the maximum UV values, and considering also correction +for gray colors to minimize the possible noise. In addition the saturation skipping doing saturation when +the color is skin and doing alpha blending according the skin factor called STDscore. +This block requires several external parameters such: + – Six basic user defined colors. + – Six basic saturation change user defined factors. + – Six calculation result of 1/(BaseColorX – BaseColorY) +ColorBias1,…, ColorBias6 – Six color bias. +STDscore – Skin-tone Detection score (from STD/E). +The result of SF is a number of 8bits. +There are four major steps to derive the saturation factor. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 186 + The Interpolated Basic SFs1 +With the calculated angle , which lies in the [ , + Ci Ci+1 ] interval, the Interpolated Basic SFs1 will be: +SFs1 = (1-  i +  i+1 +Whereas is calculated by: + = Min{Max[(  i)* i – i, 0], +1} +Over Saturation Limiter SFs2 +Over Saturation Limiter block is used to avoid saturation boosting of the already high saturated pixels. +The SFs2 is calculated by: +SFs1 , for (SF1 <= 1) +SFs2 = 1 + (SFs1 – 1)(MaxColor – UVmax)/MaxColor, for (1 < SF1 <= 2) AND (UVmax <= ) + 1, for (UVmax > ) +Where the UVmax = max(|U|,|V|), and  is an external parameter which in the case of YUV +color space is equal to 448 in 10bit representation.  was used for the inverse +calculation of 1/UVMaxColor. +Note: The last condition (UVmax > UVMaxColor) is associated with the illegal colors, and usually hasn’t to +appea (Can this be OK for wide gamut mapping?). +GrayPixels Saturation LimiterSFs3 +This block limits the saturation of the almost gray pixels. The reason for this limiter is to prevent the noise +amplification by the Saturation increase process. The result of this block is: + SFs3 = 1 + dSF * CLF + +Where: + dSF = SFs2 – 1; + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 187 + And the CLF is called Color Limiting Factor and ranges from 0 to 1. The calculation of the CLF is given +by: + = 1; for (SFs2 <= 1) AND ( any UVmax) +CLF = 0; for (UVmax <= ) + = (UVmax – UV_Threshold) / 2UV_Threshold_Bits ; for (UV_Threshold < UVmax < (UV_Threshold+2UV_Threshold_Bits) ) +Skin-tone Saturation LimiterSFs4 +The last block effects TCC strength operation of the Skin-tone pixels. Uncontrolled enhancement of the +skin pixels could lead to appearing of artifacts and to undesired results. The final SFs4 is calculated by a +linear blending: + SFs4 = (128*STEfactor + (256 - STEfactor) SFs3 ) / 256 +Where the STEfactor is called Skin Tone factor and is calculated by: + diff = (STDscore – ) * 23 +Note: the STDscore (from STD) and the STE_Threshold are presented with 5 bits. The multiplication by 23 +is in order to raise the “diff” to 8 bits. + STEfactor = Min {Max [(diff * 2 STE_SlopeBits ), 0], 255} + +The STDscore is a result of the Skin-tone Detection module. It is represented with 5 bits, where the values 0 +and 31 mean no skin-tone, and full skin-tone detection, respectively. The STEfactor is given by 8 bits, where +the value 256 represents the number 1. +It is evident that for the high values of STEfactor the resulted SFs4 is close to 1, which means a weak TCC +action of this pixel (SFs4 = 1 actually means TCC is off). + – The input pixels are multiple by the saturation factor. The results are the output pixels. +SF final is the final saturation factor which actually resulted from the forth SFcalculation block: +SFfinal = SFs4 +The calculation of the Unew, and Vnew output values. They are calculated below: +Unew = U * SFfinal + +Vnew = V * SFfinal + +Whereas (U,V) are the original input color components, +Because these pixels are represented in the unbiased form, which is the result of substraction of the +value 512 from the original [U,V] values, the final [Uout, Vout] values are given by: + Uout = Unew + 512 + Vout = Vnew + 512 +This is the final TCC output represented with 10 bits. + +3.6.1.5 ProcAmp +The PROCAMP block modifies the brightness, contrast, hue and saturation of an image in YCbCr color +space (or similar). + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 188 + The algorithm itself uses 8-16 bits per color. +Y Processing: 256 is subtracted from the Y values to position the black level at zero. This removes the +DC offset so that adjusting the contrast does not vary the black level. Since Y values may be less than +256, negative Y values should be supported at this point. Contrast is adjusted by multiplying the YUV +pixel values by a constant. If U and V are adjusted, a color shift will result whenever the contrast is +changed. The brightness property value is added (or subtracted) from the contrast adjusted Y values; this +is done to avoid introducing a DC offset due to adjusting the contrast. Finally the value 64 is added to +reposition the black level at 256. The equation for processing of Y values is: +Y’ = ((Y-256) x C) + B + 256, +where C is the Contrast value and B is the Brightness value. +UV Processing: 2048 is first subtracted from both U and V values to position the range around zero. The +hue property is implemented by mixing the U and V values together: +U’ = (U-2048) x Cos(H) + (V-2048) x Sin(H) +V’ = (V-2048) x Cos(H) – (U-2048) x Sin(H) +Where H represents the desired Hue angle; Saturation is adjusted by multiplying both U and V by a +constant. +Finally, the value 2048 is added to both U and V. The combined processing of Hue and Saturation on the +UV data is: +U’ = (((U-2048) x Cos(H) + (V-2048) x Sin(H)) x C x S) + 2048 +V’ = (((V-2048) x Cos(H) - (U-2048) x Sin(H)) x C x S) + 2048 +Where C is the contrast, H is Hue angle and S is the Saturation and the combination of Cos(H)*C*S and +Sin(H)*C*S is specified by parameters Cos_c_s and Sin_c_s. + +3.6.1.6 Color Space Conversion +The CSC block enables linear conversion between color spaces using vector shift, matrix multiplication, +and additional shift. +The CSC algorithm is a linear coordinate transformation, comprising of the following stages: +Shifting the input color coordinate. +Multiply by 3*3 matrix + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 189 + Shifting the output color coordinate +Formula representation of last 3 steps: + + + + +Where is +aij are the matrix elements, i.e., the transform coefficients:  +vin_i is the input pixel color components +v0_i is the input offset vector, i.e., ,  +u0_1_i is the output offset vector. i.e.,  +Clipping the output to ensure each component is in allowed range. +The parameters is used to set input to be RGB format and is uased to set output to be +RGB format +Notes about Repacker: +There are two states to be used in the repacker:  and . The +last module in the IECP pipeline. +If Alpha from State Select is set, the Y, U ,V is packed with the information from color pipe alpha, and +then the data is sent out to RCPB. +Otherwise, “0” is inserted in the 4LSB (alpha) and the packed data is sent out to RCPB. + +3.6.1.7 Color Gamut Compression + +3.6.1.7.1 Background of Color Gamut Compression +While most photography today complies with the sRGB standard color space, which covers around 72% +of color perceived by human being, this 72% content looks incorrect/unnatural on wide gamut displays, +which can extend more than 100%. Therefore, a gamut mapping (GM) algorithm is required to adjust +when the input gamut range is different to the output gamut range such as the input sRGB color space to +be displayed onto the WG display, or to adjust the wide gamut content to be displayed onto the traditional +lower gamut display. +The easiest compression method applied to displaying wider gamut content on lower gamut displays is to +clip the out of range primary values to the valid range (i.e., 0-1). Although this simple clipping procedure +leads to acceptable visual appearance in most cases, loss of color depth can be observed in the video +containing out-of-range pixels. The reason behind this effect should be the uniform quantization process +applied to out-of-range values (e.g., two distinct out-of-range red colors are mapped to the same +boundary red color). Moreover, the simple clipping method treats each color channel independently. This +may lead to unexpected perceptual loss since the composite ratios of three primaries have been +changed. An approach which takes these two factors into account while scaling down the out of range +values can possibly maintain the detail information of the image. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 190 + 3.6.1.7.2 Usage Models +There are two usage models depending on the set up of bit: +Basic mode: fixed-hue color gamut clipping mode +Advanced mode: fixed-hue full range mapping mode +The application of basic mode of the fixed-hue color gamut clipping is preferred when the content having +the smaller percentage of out-of-range pixels in the scene. The advanced mode of fixed-hue full range +mapping mode may also change the in-range pixels and is thus preferred when the percentage of out-of- +range pixel is large. The outcome of the in/out range pixel percentage is derived from the out-of range +color gamut detection module to provide an indicator to operate among basic mode and advanced mode. + +3.6.1.7.3 Gamut compression module overview +The main goal of color gamut compression module algorithm is to compress out-of-range pixel values +while keeping their hue values same as it is before compression. A block diagram to color gamut +compress the xv Color video into sRGB format is shown below. + + + + +AT the pipeline level, the input into Gamut compression unit is from STDE unit and the output from the +Gamut compression goes to TCCE unit. The Gamut compression comprises of the following stages: +xvYCC decoding +YUV2LCH color space conversion +Out of range Gamut pixel detection +Scaling factor calculation +Find out the Euclidean distance for the out of range pixel for advance mode +Fixed-hue Gamut compression +Bring the out of range pixel to the boundary for basic mode +Bring the out of range pixel depending on the distance and apply uniform quantization process in advance +mode +xvYCC encoding + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 191 + 3.6.1.7.4 xvYCC decoding +The non-linear YCbCr values (i.e.,Y’Cb’Cr’, or Y’UV) is decoded from an example of 8-bit/channel below: + + + + + . +For 12-bit/channel the above equation can be re-written as follows: + + + + +3.6.1.7.5 YUV2LCH +The parameters for scaling the out-of-range pixel values are determined in LCHuv space, which is the +cylindrical version of LUV space. For every input pixel, (Y_in = Y” , U_in = Cb” , V_in = Cr” ) we find its +chrominance value (i.e., C) and hue value (i.e., H) + + , + + + , + + + + +The approximation of hue angle calculation is described in the TCC session. + +3.6.1.7.6 Out-of-range gamut pixel detection + +An input pixel is denoted as in the LCH color space. If , the pixel can be +outputted without pixel value change. +Every input pixel is associated with a hue value in LCH space. From the calculated hue value, we can +read a corresponding vertex point from the pre-calculated table which contained the 512-entry vertex +points of the below color triangle in LCH space with the designated hue value derived off-line. Note that +with the symmetric property of the lightness vertex, only vertices in need to be stored in the pre- +calculated LUT. Therefore, the 512x2 components in the LUT correspond to the information of 512 +equally-distributed hue angles in the range of . Moreover, the vertex value of a certain hue angle +is dependent of the color space (e.g., BT. 709 or BT. 601). Here, the vertex point V for a hue angle is +denoted as + + .(3) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 192 + Left: The RGB boundary corresponding to hue value H. Right: the RGB boundary in left projected on the +luminance-chrominance plane. +Vertex point look up table: + +Utilizing the hue angle calculation module in TCC, the equally-spaced, discrete hue angle ranging from 0 +to is represented with an integer (i.e., angle index) in [0~1023]. Since the LUT in color compression +only stores vertices in [0~ ), a mapping procedure is required to remap angles in to +before indexing the LUT: +if((angle_index < 512) && (angle_index > =0)) +angle_index = angle_index; +else + angle_index = angle_index – 512; +With the properly remapped angle index for accessing the LUT, the information of the vertex point can be +obtained as below. +Sat_Vertex = m_SatVertex[angle_index]; // Sat Vertex form the LUT +Luma1 = m_LumaVertex[angle_index]; // lightness vertex in [0~pi) +Luma2 = denorm-Luma1; // symmetric lightness vertex; denorm = 4096 in 12 bit representation +Note that the lightness vertex is symmetric in uv/ CbCr-plane (i.e., Luma1 + Luma2 = denom), and the +lightness vertex stored in the LUT correspond to those in . Thus, one has to check the hue side +(i.e., whether this pixel is originally in or in of the current pixel to acquire the correct +lightness vertex for this pixel: +if(srcV == 0)// 0 or 180 degree + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 193 + { +if (srcU > 0)// srcU == 0 Cp = 0 +Luma_Vertex = Luma1; +else + +Luma_Vertex = Luma2; +} + else + { +if(srcV > 0) + +Luma_Vertex = Luma1; + +else +Luma_Vertex = Luma2; + +} + + +An input pixel is detected as an out-of-range pixel if the below condition is true. + + + + (4) +A statistics parameter, , is incremented if the above equation is true. The + will be collected at picture level through VSC unit to assess the property +of a picture to determine the strategy of ways to do gamut compression. + +Note: If is an in-range pixel, the pixel will be outputted according to equation (13). + +3.6.1.7.7 Scaling factor – Basic mode +The slope of a compression line is defined from the vertex point table. + + + , with  default +to be 3.(5) + + in the above equation is the slope of the compression line while represents the slope of the +line perpendicular to the RGB boundary line: + + + + , and(6) + + + + + where .(7) + +The intersection between the compression line for pixel and the L-axis is denoted as + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 194 + , then + + , and(8) + + + + +The point nearest to the input pixel on the RGB boundary along the compression direction (i.e., + +intersection between the compression line and the RGB boundary) be , then + + , with + + + + + , and (9) + + . +Scaling factor is denoted as + + + + .(10) +For the usage of Basic mode - fixed-hue color gamut clipping mode, all out-of-range pixels will be clipped +to the boundary, which means + + (11) +And the luma is mapped at along the compression line to hit the boundary line at + + (12) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 195 + 3.6.1.7.8 Fixed-hue compression +The output of fixed compression is based on the scaling factor and the property of pixel. + + + + + , if or , else + + + + + . (13) + +3.6.1.7.9 Scaling factor – Advanced mode +The out-of-range pixel values can be mapped inwards according to how far they are from the boundary +from the following equation: + + + + + .(14) + + + + . + +Where is coming from the reference point as the origin of the linear transformation for compressing + +pixel as +Denote the reference point + + + + + (15) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 196 + 3.6.1.7.10 xvYCC encoding +The output of Y, Cb and Cr values are scaled back through xvYCC encoding process, and the example +for the 12bit format is provided below: + + + + +3.6.2 Boundary Behavior +The table below summarizes the behavior of the Media Boundary Pixel Mode field (SURFACE_STATE) +in combination with the Vertical Line Stride and Vertical Line Stride Offset fields (both of which are +subject to being overridden by the Data Port message descriptor fields). The Behavior column illustrates +behavior for a surface with four rows numbered 0 to 3. The bold indicators are off-surface behavior and +the non-bold indicators are on-surface behavior. Input row addresses range from -3 to +7 going left to +right. + +Media Boundary Pixel + Mode + Vertical Line Stride Vertical Line Stride Offset Usage Model Behavior +0 0 X normal frame 000001233333 +0 1 0 normal field even 000002222222 +0 1 1 normal field odd 111113333333 +2 0 X frame / progressive 000001233333 +2 1 0 field even / progressive 000002333333 +2 1 1 field odd / progressive 000013333333 +3 0 X frame / interlaced 010101232323 +3 1 0 field even / interlaced 000002222222 +3 1 1 field odd / interlaced 111113333333 + + + +3.7 Accessing Render Targets +Render targets are the surfaces that the final results of pixel shaders are written to. The render targets +support a large set of surface formats (refer to surface formats table in Sampling Engine for details) with + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 197 + hardware conversion from the format delivered by the thread. The render target message also causes +numerous side effects, including potentially alpha test, depth test, stencil test, alpha blend (which +normally causes a read of the render target), and other functions. These functions are covered in the +Windower chapter as some of them (depth/stencil test) are also partially done in the Windower. +The render target write messages are specifically for the use of pixel shader threads that are spawned by +the windower, and may not be used by any other threads. This is due to the pixel scoreboard side-effects +that sending of this message entails. The pixel scoreboard ensures that incorrect ordering of reads and +writes to the same pixel does not occur. + + +3.7.1 Single Source +The “normal” render target messages are single source. There are two forms, SIMD16 and SIMD8, +intended for the equivalent-sized pixel shader threads. A single color (4 channels) is delivered for each of +the 16 or 8 pixels in the message payload. Optional depth, stencil, and antialias alpha information can +also be delivered with these messages. +The pixel scoreboard bits corresponding to the dispatched pixel mask (or half of the mask in the case of +SIMD8 messages) are cleared only if the Last Render Target Select bit is set in the message descriptor. +The single source message will not cause a write to the render target if Dual Source Blend Enable in +3DSTATE_WM is enabled. However, if Last Render Target Select is set, the message will still cause +pixel scoreboard clear and depth/stencil buffer updates if enabled. + + +3.7.2 Dual Source +The dual source render target messages only have SIMD8 forms due to maximum message length +limitations. SIMD16 pixel shaders must send two of these messages to cover all of the pixels. Each +message contains two colors (4 channels each) for each pixel in the message payload. In addition to the +first source, the second source can be selected as a blend factor (BLENDFACTOR_*_SRC1_* options in +the blend factor fields of COLOR_CALC_STATE or BLEND_STATE). Optional depth, stencil, and +antialias alpha information can also be delivered with these messages. +Each dual source message delivered will clear the corresponding pixel scoreboard bits if the Last Render +Target Select bit in the message descriptor is set. +The dual source message will revert to a single source message using source 0 if Dual Source Blend +Enable in 3DSTATE_WM is disabled. + + +3.7.3 Replicate Data +The replicate data render target message is used for “fast clear” functionality in cases where the color +data for each pixel is identical. This message performs better than the other messages due to its smaller +message length. This message does not support depth, stencil, or antialias alpha data being sent with it. +This message must target only tiled memory. Access of linear memory using this message type is +UNDEFINED. The depth buffer can be cleared through the “early depth” function in conjunction with a +pixel shader using this message. Refer to the Windower chapter for more details on the early depth +function. +The pixel scoreboard bits corresponding to the dispatched pixel mask are cleared only if the Last Render +Target Select bit is set in the message descriptor. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 198 + 3.7.4 Multiple Render Targets (MRT) +Multiple render targets are supported with the single source and replicate data messages. Each render +target is accessed with a separate Render Target Write message, each with a different surface indicated +(different binding table index). The depth buffer is written only by the message(s) to the last render target, +indicated by the Last Render Target Select bit set to clear the pixel scoreboard bits. +MRT is not supported when one or more RTs have this surface formats: YCRCB_SWAPUVY, +YCRCB_SWAPUV, YCRCB_SWAPY, YCRCB_NORMAL + + +3.8 State + +3.8.1 BINDING_TABLE_STATE +The data port uses the binding table to retrieve surface state. Refer to Statein the Sampling Engine +section for the definition of this state. + + +3.8.2 SURFACE_STATE +The data port uses the surface state for constant buffers, render targets, and media surfaces. Refer to +SURFACE_STATE in the Sampling Engine section for the definition of this state. + + +3.8.3 COLOR_PROCESSING_STATE +The following state structures contain different states used by the color processing function. + + COLOR_PROCESSING_STATE - STD/STE State + +Default 0x9A6E39F0, 0x400C0000, 0x00001180, 0xFE2F2E00, 0x000000FF, 0x00140000, 0xD82E0000, +Value: 0x8285ECEC, 0x00008282, 0x00000000, 0x02117000, 0xA38FEC96, 0x00008CC8, 0x00000000, + 0x01478000, 0x0007C300, 0x00000000, 0x00000000, 0x1C180000, 0x00000000, 0x00000000, + 0x00000000, 0x0007CF80, 0x00000000, 0x00000000, 0x1C080000, 0x00000000, 0x00000000, + 0x00000000 +This state structure contains the STD/STE state used by the color processing function. + DWord Bit Description +0 31:24 V_Mid + Default Value: 154 + Format: U8 + Rectangle middle-point V coordinate + + 23:16 U_Mid + Default Value: 110 + Format: U8 + Rectangle middle-point U coordinate + + 15:10 Hue Max + Default Value: 14 + Format: U6 + Rectangle half width + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 199 + COLOR_PROCESSING_STATE - STD/STE State + + 9:4 Sat Max + Default Value: 31 + Format: U6 + Rectangle half length. + + 3 Reserved + Format: MBZ + 2 Output Control + Value Name + 0 Output Pixels [Default] + 1 Output STD Decisions + 1 STE Enable + Format: Enable + 0 STD Enable + Format: Enable +1 31 Reserved + Format: MBZ + 30:28 Diamond Margin + Default Value: 4 + Format: U3 + 27:21 Diamond du + Default Value: 0 + Format: S7 2’s complement + + + Rhombus center shift in the sat-direction, relative to the rectangle center. + + 20:18 HS Margin + Default Value: 3 + Format: U3 + 17:10 Cos(α) + Format: S0.7 2's Compliment + + + The default is 79/128 + + 9:8 Reserved + Format: MBZ + 7:0 Sin(α) + Format: S0.7 2's Compliment + + + The default is 101/128 + +2 31:21 Reserved + Format: MBZ + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 200 + COLOR_PROCESSING_STATE - STD/STE State + 20:13 Diamond Alpha + Format: U2.6 + 1 / tan(β) + The default is 100/64 + + 12:7 Diamond Th + Default Value: 35 + Format: U6 + Half length of the rhombus axis in the sat-direction. + + 6:0 Diamond dv + Default Value: 0 + Format: S6 2’s complement + + + +3 31:24 Y_point_3 + Default Value: 254 + Format: U8 + Third point of the Y piecewise linear membership function. + + 23:16 Y_point_2 + Default Value: 47 + Format: U8 + Second point of the Y piecewise linear membership function. + + 15:8 Y_point_1 + Default Value: 46 + Format: U8 + First point of the Y piecewise linear membership function. + + 7 VY_STD_Enable + Format: Enable + Enables STD in the VY subspace. + + 6:0 Reserved + Format: MBZ +4 31:18 Reserved + Format: MBZ + 17:13 Y_Slope_2 + Format: U2.3 + Slope between points Y3 and Y4. + The default is 31/8. + + 12:8 Y_Slope_1 + Format: U2.3 + Slope between points Y1 and Y2. + The default is 31/8. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 201 + COLOR_PROCESSING_STATE - STD/STE State + 7:0 Y_point_4 + Default Value: 255 + Format: U8 + Fourth point of the Y piecewise linear membership function + +5 31:16 INV_skin_types_margin + Format: U0.16 + 1/(2* Skin_types_margin) + Value Name Description + 20 [Default] Skin_Type_margin + 15:0 Inverse Margin VYL + Format: U0.16 + 1 / Margin_VYL + The default is 3300/65536 + +6 31:24 P1L + Default Value: 216 + Format: U8 + Y Point 1 of the lower part of the detection PWLF. + + 23:16 P0L + Default Value: 46 + Format: U8 + Y Point 0 of the lower part of the detection PWLF. + + 15:0 Inverse Margin VYU + Format: U0.16 + 1 / Margin_VYU + The default is 1600/65536. + +7 31:24 B1L + Default Value: 130 + Format: U8 + V Bias 1 of the lower part of the detection PWLF. + + 23:16 B0L + Default Value: 133 + Format: U8 + V Bias 0 of the lower part of the detection PWLF. + + 15:8 P3L + Default Value: 236 + Format: U8 + Y Point 3 of the lower part of the detection PWLF. + + 7:0 P2L + Default Value: 236 + Format: U8 + Y point 2 of the lower part of the detection PWLF. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 202 + COLOR_PROCESSING_STATE - STD/STE State + +8 31:27 Reserved + Format: MBZ + 26:16 S0L + Format: S2.8 2's complement + + + Slope 0 of the lower part of the detection PWLF. + The default is -5/256. + + 15:8 B3L + Default Value: 130 + Format: U8 + V Bias 3 of the lower part of the detection PWLF. + + 7:0 B2L + Default Value: 130 + Format: U8 + V Bias 2 of the lower part of the detection PWLF. + +9 31:22 Reserved + Format: MBZ + 21:11 S2L + Format: S2.8 2's complement + + + Slope 2 of the lower part of the detection PWLF. + The default is 0/256. + + 10:0 S1L + Format: S2.8 2's complement + + + Slope 1 of the lower part of the detection PWLF. + The default is 0/256. + +10 31:27 Reserved + Format: MBZ + 26:19 P1U + Default Value: 66 + Format: U8 + Y Point 1 of the upper part of the detection PWLF. + + 18:11 P0U + Default Value: 46 + Format: U8 + Y Point 0 of the upper part of the detection PWLF. + + 10:0 S3L + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 203 + COLOR_PROCESSING_STATE - STD/STE State + Format: S2.8 2's complement + + + Slope 3 of the lower part of the detection PWLF. + The default is 0/256. + +11 31:24 B1U + Default Value: 163 + Format: U8 + V Bias 1 of the upper part of the detection PWLF. + + 23:16 B0U + Default Value: 143 + Format: U8 + V Bias 0 of the upper part of the detection PWLF. + + 15:8 P3U + Default Value: 236 + Format: U8 + Y Point 3 of the upper part of the detection PWLF. + + 7:0 P2U + Default Value: 150 + Format: U8 + Y Point 2 of the upper part of the detection PWLF. + +12 31:27 Reserved + Format: MBZ + 26:16 S0U + Format: S2.8 2's complement + + + Slope 0 of the upper part of the detection PWLF. + The default is 256/256. + + 15:8 B3U + Default Value: 140 + Format: U8 + V Bias 3 of the upper part of the detection PWLF. + + 7:0 B2U + Default Value: 200 + Format: U8 + V Bias 2 of the upper part of the detection PWLF. + +13 31:22 Reserved + Format: MBZ + 21:11 S2U + Format: S2.8 2's complement + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 204 + COLOR_PROCESSING_STATE - STD/STE State + + + Slope 2 of the upper part of the detection PWLF. + The default is -179/256. + + 10:0 S1U + Format: S2.8 2's complement + + + Slope 1 of the upper part of the detection PWLF. + The default is -113/256. + +14 31:28 Reserved + Format: MBZ + 27:20 Skin Types Margin + Default Value: 20 + Format: U8 + Skin types Y margin. + + 19:12 Skin Types Thresh + Default Value: 120 + Format: U8 + Skin types Y threshold. + + 11 Skin Type Enable + Format: Enable + Treat differently bright and dark skin types. + Value Name Description + 0 [Default] Disable + 10:0 S3U + Format: S2.8 2's complement + + + Slope 3 of the upper part of the detection PWLF. + The default is 0/256. + +15 31 Reserved + Format: MBZ + 30:21 SATB1 + Format: S7.2 2's complement + + + First bias for the saturation PWLF (bright skin). + The default is -8/4. + + 20:14 SATP3 + Default Value: 31 + Format: S6 2's complement + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 205 + COLOR_PROCESSING_STATE - STD/STE State + + Third point for the saturation PWLF (bright skin). + + 13:7 SATP2 + Default Value: 6 + Format: S6 2's complement + + + Second point for the saturation PWLF (bright skin). + + 6:0 SATP1 + Format: S6 2's complement + + + First point for the saturation PWLF (bright skin). + The default is -6. + +16 31 Reserved + Format: MBZ + 30:20 SATS0 + Format: U3.8 + Zeroth slope for the saturation PWLF (bright skin). + The default is 297/256. + + 19:10 SATB3 + Format: S7.2 2's complement + + + Third bias for the saturation PWLF (bright skin). + The default is 124/4. + + 9:0 SATB2 + Format: S7.2 2's complement + + + Second bias for the saturation PWLF (bright skin). + The default is 8/4. + +17 31:22 Reserved + Format: MBZ + 21:11 SATS2 + Format: U3.8 + Second slope for the saturation PWLF (bright skin). + The default is 297/256. + + 10:0 SATS1 + Format: U3.8 + First slope for the saturation PWLF (bright skin). + The default is 85/256. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 206 + COLOR_PROCESSING_STATE - STD/STE State + +18 31:25 HUEP3 + Default Value: 14 + Format: S6 2's complement + + + Third point for the hue PWLF (bright skin) + + 24:18 HUEP2 + Default Value: 6 + Format: S6 2's complement + + + Second point for the hue PWLF (bright skin) + + 17:11 HUEP1 + Format: S6 2's complement + + + First point for the hue PWLF (bright skin). + The default is -6. + + 10:0 SATS3 + Format: U3.8 + Thrid slope for the saturation PWLF (bright skin). + The default is 256/256. + +19 31:30 Reserved + Format: MBZ + 29:20 HUEB3 + Format: S7.2 2's complement + + + Third bias for the hue PWLF (bright skin). + The default is 56/4. + + 19:10 HUEB2 + Format: S7.2 2's complement + + + Second bias for the hue PWLF (bright skin). + The default is 8/4. + + 9:0 HUEB1 + Format: S7.2 2's complement + + + First bias for the hue PWLF (bright skin). + The default is -8/4. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 207 + COLOR_PROCESSING_STATE - STD/STE State +20 31:22 Reserved + Format: MBZ + 21:11 HUES1 + Format: U3.8 + First slope for the hue PWLF (bright skin) + The default is 85/256. + + 10:0 HUES0 + Format: U3.8 + Zeroth slope for the hue PWLF (bright skin) + The default is 384/256. + +21 31:22 Reserved + Format: MBZ + 21:11 HUES3 + Format: U3.8 + Third slope for the hue PWLF (bright skin) + The default is 256/256. + + 10:0 HUES2 + Format: U3.8 + Second slope for the hue PWLF (bright skin) + The default is 384/256. + +22 31 Reserved + 30:21 SATB1_DARK + Format: S7.2 2's complement + + + First bias for the saturation PWLF (dark skin) + The default is 0/4. + + 20:14 SATP3_DARK + Default Value: 31 + Format: S6 2's complement + + + Third point for the saturation PWLF (dark skin) + + 13:7 SATP2_DARK + Default Value: 31 + Format: S6 2's complement + + + Second point for the saturation PWLF (dark skin) + + 6:0 SATP1_DARK + Format: S6 2's complement + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 208 + COLOR_PROCESSING_STATE - STD/STE State + + First point for the saturation PWLF (dark skin). + The default is -11. + +23 31 Reserved + Format: MBZ + 30:20 SATS0_DARK + Format: U3.8 + Zeroth slope for the saturation PWLF (dark skin). + The default is 397/256. + + 19:10 SATB3_DARK + Format: S7.2 2's complement + + + Third bias for the saturation PWLF (dark skin). + The default is 124/4. + + 9:0 SATB2_DARK + Format: S7.2 2's complement + + + Second bias for the saturation PWLF (dark skin). + The default is 124/4. + +24 31:22 Reserved + Format: U3.8 + 21:11 SATS2_DARK + Format: U3.8 + Second slope for the saturation PWLF (dark skin). + The default is 256/256. + + 10:0 SATS1_DARK + Format: U3.8 + First slope for the saturation PWLF (dark skin). + The default is 189/256. + +25 31:25 HUEP3_DARK + Default Value: 14 + Format: S6 2's complement + + + Third point for the hue PWLF (dark skin). + + 24:18 HUEP2_DARK + Default Value: 2 + Format: S6 2's complement + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 209 + COLOR_PROCESSING_STATE - STD/STE State + Third point for the hue PWLF (dark skin). + + 17:11 HUEP1_DARK + Default Value: 0 + Format: S6 2's complement + + + Third point for the hue PWLF (dark skin). + + 10:0 SATS3_DARK + Format: U3.8 + Third slope for the saturation PWLF (dark skin). + The default is 256/256. + +26 31:30 Reserved + Format: MBZ + 29:20 HUEB3_DARK + Format: S7.2 2's complement + + + Third bias for the hue PWLF (dark skin). + The default is 56/4. + + 19:10 HUEB2_DARK + Format: S7.2 2's complement + + + Second bias for the hue PWLF (dark skin). + The default is 0/4. + + 9:0 HUEB1_DARK + Format: S7.2 2's complement + + + First bias for the hue PWLF (dark skin). + The default is 0/4. + +27 31:22 Reserved + Format: MBZ + 21:11 HUES1_DARK + Format: U3.8 + First slope for the hue PWLF (dark skin). + The default is 0/256. + + 10:0 HUES0_DARK + Format: U3.8 + Zeroth slope for the hue PWLF (dark skin). + The default is 256/256. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 210 + COLOR_PROCESSING_STATE - STD/STE State +28 31:22 Reserved + Format: MBZ + 21:11 HUES3_DARK + Format: U3.8 + Third slope for the hue PWLF (dark skin). + The default is 256/256. + + 10:0 HUES2_DARK + Format: U3.8 + Second slope for the hue PWLF (dark skin). + The default is 299/256. + + + + + COLOR_PROCESSING_STATE - ACE State + +Default 0x00000068, 0x4C382410, 0x9C887460, 0xEBD8C4B0, 0x604C3824, 0xB09C8874, 0x0000D8C4, +Value: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 +This state structure contains the ACE state used by the color processing function. + DWord Bit Description +29 31:7 Reserved + Format: MBZ + 6:2 Skin Threshold + Format: U5 + Used for Y analysis (min/max) for pixels which are higher than skin threshold. + Value Name + 1-31 + 26 [Default] + 1 Full Image Histogram + Default Value: 0 + Format: Enable + Used to ignore the area of interest for full image histogram. + + 0 ACE Enable + Format: Enable +30 31:24 Y3 + Default Value: 76 + Format: U8 + The value of the y_pixel for point 3 in PWL. + + 23:16 Y2 + Default Value: 56 + Format: U8 + The value of the y_pixel for point 2 in PWL. + + 15:8 Y1 + Default Value: 36 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 211 + COLOR_PROCESSING_STATE - ACE State + Format: U8 + The value of the y_pixel for point 1 in PWL. + + 7:0 Ymin + Default Value: 16 + Format: U8 + The value of the y_pixel for point 0 in PWL. + +31 31:24 Y7 + Default Value: 156 + Format: U8 + The value of the y_pixel for point 7 in PWL. + + 23:16 Y6 + Default Value: 136 + Format: U8 + The value of the y_pixel for point 6 in PWL. + + 15:8 Y5 + Default Value: 116 + Format: U8 + The value of the y_pixel for point 5 in PWL. + + 7:0 Y4 + Default Value: 96 + Format: U8 + The value of the y_pixel for point 4 in PWL. + +32 31:24 Ymax + Default Value: 235 + Format: U8 + The value of the y_pixel for point 11 in PWL. + + 23:16 Y10 + Default Value: 216 + Format: U8 + The value of the y_pixel for point 10 in PWL. + + 15:8 Y9 + Default Value: 196 + Format: U8 + The value of the y_pixel for point 9 in PWL. + + 7:0 Y8 + Default Value: 176 + Format: U8 + The value of the y_pixel for point 8 in PWL. + +33 31:24 B4 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 212 + COLOR_PROCESSING_STATE - ACE State + Default Value: 96 + Format: U8 + The value of the bias for point 4 in PWL. + + 23:16 B3 + Default Value: 76 + Format: U8 + The value of the bias for point 3 in PWL. + + 15:8 B2 + Default Value: 56 + Format: U8 + The value of the bias for point 2 in PWL. + + 7:0 B1 + Default Value: 36 + Format: U8 + The value of the bias for point 1 in PWL. + +34 31:24 B8 + Default Value: 176 + Format: U8 + The value of the bias for point 8 in PWL. + + 23:16 B7 + Default Value: 156 + Format: U8 + The value of the bias for point 7 in PWL. + + 15:8 B6 + Default Value: 136 + Format: U8 + The value of the bias for point 6 in PWL. + + 7:0 B5 + Default Value: 116 + Format: U8 + The value of the bias for point 5 in PWL. + +35 31:16 Reserved + Format: MBZ + 15:8 B10 + Default Value: 216 + Format: U8 + The value of the bias for point 10 in PWL. + + 7:0 B9 + Default Value: 196 + Format: U8 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 213 + COLOR_PROCESSING_STATE - ACE State + The value of the bias for point 9 in PWL. + +36 31:27 Reserved + Format: MBZ + 26:16 S1 + Format: U1.10 + The value of the slope for point 1 in PWL. + The default is 1024/1024. + + 15:11 Reserved + Format: MBZ + 10:0 S0 + Format: U1.10 + The value of the slope for point 0 in PWL. + The default is 1024/1024. + +37 31:27 Reserved + Format: MBZ + 26:16 S3 + Format: U1.10 + The value of the slope for point 3 in PWL. + The default is 1024/1024. + + 15:11 Reserved + Format: MBZ + 10:0 S2 + Format: U1.10 + The value of the slope for point 2 in PWL. + The default is 1024/1024. + +38 31:27 Reserved + Format: MBZ + 26:16 S5 + Format: U1.10 + The value of the slope for point 5 in PWL. + The default is 1024/1024. + + 15:11 Reserved + Format: MBZ + 10:0 S4 + Format: U1.10 + The value of the slope for point 4 in PWL. + The default is 1024/1024. + +39 31:27 Reserved + Format: MBZ + 26:16 S7 + Format: U1.10 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 214 + COLOR_PROCESSING_STATE - ACE State + The value of the slope for point 7 in PWL. + The default is 1024/1024. + + 15:11 Reserved + Format: MBZ + 10:0 S6 + Format: U1.10 + The value of the slope for point 6 in PWL. + The default is 1024/1024. + +40 31:27 Reserved + Format: MBZ + 26:16 S9 + Format: U1.10 + The value of the slope for point 9 in PWL. + The default is 1024/1024. + + 15:11 Reserved + Format: MBZ + 10:0 S8 + Format: U1.10 + The value of the slope for point 8 in PWL. + The default is 1024/1024. + +41 31:11 Reserved + Format: MBZ + 10:0 S10 + Format: U1.10 + The value of the slope for point 10 in PWL. + The default is 1024/1024. + + + + + COLOR_PROCESSING_STATE - TCC State + +Default 0xDCDCDC00, 0xDCDCDC00, 0x1E34CC91, 0x3E3CCE91, 0x02E80195, 0x0197046B, 0x01790174, +Value: 0x00096000, 0x00000000, 0x03030000, 0x009201C0 +This state structure contains the TCC state used by the color processing function. + DWord Bit Description +42 31:24 SatFactor3 + Default Value: 220 + Format: U1.7 + The saturation factor for yellow. + + 23:16 SatFactor2 + Default Value: 220 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 215 + COLOR_PROCESSING_STATE - TCC State + Format: U1.7 + The saturation factor for red. + + 15:8 SatFactor1 + Default Value: 220 + Format: U1.7 + The saturation factor for magenta. + + 7 TCC Enable + Format: Enable + 6:0 Reserved + Format: MBZ +43 31:24 SatFactor6 + Default Value: 220 + Format: U1.7 + The saturation factor for blue. + + 23:16 SatFactor5 + Default Value: 220 + Format: U1.7 + The saturation factor for cyan. + + 15:8 SatFactor4 + Default Value: 220 + Format: U1.7 + The saturation factor for green. + + 7:0 Reserved + Format: MBZ +44 31:30 Reserved + Format: MBZ + 29:20 Base Color 3 + Default Value: 483 + Format: U10 + 19:10 Base Color 2 + Default Value: 307 + Format: U10 + 9:0 Base Color 1 + Default Value: 145 + Format: U10 +45 31:30 Reserved + Format: MBZ + 29:20 Base Color 6 + Default Value: 995 + Format: U10 + 19:10 Base Color 5 + Default Value: 819 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 216 + COLOR_PROCESSING_STATE - TCC State + Format: U10 + 9:0 Base Color 4 + Default Value: 657 + Format: U10 +46 31:16 Color Transit Slope 23 + Default Value: 744 + Format: U0.16 + The calculation result of 1 / (BC3 – BC2) [1/62] + + 15:0 Color Transit Slope 12 + Default Value: 405 + Format: U0.16 + The calculation result of 1 / (BC2 – BC1) [1/57] + +47 31:16 Color Transit Slope 45 + Default Value: 407 + Format: U0.16 + The calculation result of 1 / (BC5 – BC4) [1/57] + + 15:0 Color Transit Slope 34 + Default Value: 1131 + Format: U0.16 + The calculation result of 1 / (BC4 – BC3) [1/61] + +48 31:16 Color Transit Slope 61 + Default Value: 377 + Format: U0.16 + The calculation result of 1 / (BC1 – BC6) [1/62] + + 15:0 Color Transit Slope 56 + Default Value: 372 + Format: U0.16 + The calculation result of 1 / (BC6 – BC5) [1/62] + +49 31:22 Color Bias 3 + Default Value: 0 + Format: U2.8 + Color bias for BaseColor3. + + 21:12 Color Bias 2 + Default Value: 150 + Format: U2.8 + Color bias for BaseColor2. + + 11:2 Color Bias 1 + Default Value: 0 + Format: U2.8 + Color bias for BaseColor1. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 217 + COLOR_PROCESSING_STATE - TCC State + 1:0 Reserved + Format: MBZ +50 31:22 Color Bias 6 + Default Value: 0 + Format: U2.8 + Color bias for BaseColor6. + + 21:12 Color Bias 5 + Default Value: 0 + Format: U2.8 + Color bias for BaseColor5. + + 11:2 ColorBias4 + Default Value: 0 + Format: U2.8 + Color bias for BaseColor4. + + 1:0 Reserved + Format: MBZ +51 31 Reserved + Format: MBZ + 30:24 UV Threshold + Default Value: 3 + Format: U7 + Low UV threshold. + + 23:19 Reserved + Format: MBZ + 18:16 UV Threshold Bits + Default Value: 3 + Format: U3 + Low UV transition width bits. + + 15:13 Reserved + Format: MBZ + 12:8 STE Threshold + Default Value: 0 + Format: U5 + Skin tone pixels enhancement threshold. + + 7:3 Reserved + Format: MBZ + 2:0 STE Slope Bits + Default Value: 0 + Format: U3 + Skin tone pixels enhancement slope bits. + +52 31:16 Inverse UVMax Color + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 218 + COLOR_PROCESSING_STATE - TCC State + Default Value: 146 + Format: U0.16 + 1 / UVMaxColor. Used for the SFs2 calculation. + + 15:9 Reserved + Format: MBZ + 8:0 UVMax Color + Default Value: 448 + Format: U9 + The maximum absolute value of the legal UV pixels. Used for the SFs2 calculation. + + + + + COLOR_PROCESSING_STATE - PROCAMP State + +Default Value: 0x00020001, 0x01000000 +This state structure contains the PROCAMP state used by the color processing function. + DWord Bit Description +53 31:28 Reserved + Format: MBZ + 27:17 Contrast + Default Value: 1 + Format: U4.7 + Contrast magnitude. + + 16:13 Reserved + Format: MBZ + 12:1 Brightness + Default Value: 0 + Format: S7.4 2's complement + + + Brightness magnitude. + + 0 PROCAMP Enable + Default Value: 1 + Format: Enable +54 31:16 Cos_c_s + Default Value: 256 + Format: S7.8 2's complement + + + UV multiplication cosine factor. + + 15:0 Sin_c_s + Default Value: 0 + Format: S7.8 2's complement + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 219 + COLOR_PROCESSING_STATE - PROCAMP State + + + UV multiplication sine factor. + + + + + COLOR_PROCESSING_STATE - CSC State + +Default 0x00002000, 0x00000000, 0x00000400, 0x00000000, 0x000004B4, 0x00000000, 0x00000000, +Value: 0x00000000, 0x00000000 +This state structure contains the CSC state used by the color processing function. + DWord Bit Description +55 31:29 Reserved + Format: MBZ + 28:16 C1 + Default Value: 0 + Format: S2.10 2's complement + + + Transform coefficient + + 15:3 C0 + Default Value: 1024 + Format: S2.10 2's complement + + + Transform coefficient + + 2 YUV_IN + Default Value: 0 + Format: YUV + CSC input offset enable. + + 1 YUV_OUT + Default Value: 0 + Format: RGB + CSC output offset enable. + + 0 Transform Enable + Format: Enable +56 31:26 Reserved + Format: MBZ + 25:13 C3 + Default Value: 0 + Format: S2.10 2's complement + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 220 + COLOR_PROCESSING_STATE - CSC State + Transform coefficient. + + 12:0 C2 + Default Value: 0 + Format: S2.10 2's complement + + + Transform coefficient. + +57 31:26 Reserved + Format: MBZ + 25:13 C5 + Default Value: 0 + Format: S2.10 2's complement + + + Transform coefficient. + + 12:0 C4 + Default Value: 1024 + Format: S2.10 2's complement + + + Transform coefficient. + +58 31:26 Reserved + Format: MBZ + 25:13 C7 + Default Value: 0 + Format: S2.10 2's complement + + + Transform coefficient. + + 12:0 C6 + Default Value: 0 + Format: S2.10 2's complement + + + Transform coefficient. + +59 31:13 Reserved + Format: MBZ + 12:0 C8 + Default Value: 1204 + Format: S2.10 2's complement + + + Transform coefficient. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 221 + COLOR_PROCESSING_STATE - CSC State + +60 31:20 Reserved + Format: MBZ + 19:10 Offset out 1 + Default Value: 0 + Format: S9 2's complement + + + Offset Out for Y/R. + + 9:0 Offset In 1 + Default Value: 0 + Format: S9 2's complement + + + Offset in for Y/R. + +61 31:20 Reserved + Format: MBZ + 19:10 Offset out 2 + Default Value: 0 + Format: S9 2's complement + + + Offset out for U/G. + + 9:0 Offset in 2 + Default Value: 0 + Format: S9 2's complement + + + Offset in for U/G. + +62 31:20 Reserved + Format: MBZ + 19:10 Offset out 3 + Default Value: 0 + Format: S9 2's complement + + + Offset out for V/B. + + 9:0 Offset in 3 + Default Value: 0 + Format: S9 2's complement + + + Offset in for V/B. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 222 + COLOR_PROCESSING_STATE - CSC State +63 31:17 Reserved + Format: MBZ + 16 Alpha from State Select + Format: U1 Enumerated Type + + + + + Value Name Description + 0 Alpha is taken from message + 1 Alpha is taken from state + 15:0 Color Pipe Alpha + Format: U16 + + + + + COLOR_PROCESSING_STATE - CGC State + +Default Value: 0x0CD2911F, 0x30000334, 0x8A800000 +This state structure contains the CGC state used by the color processing function. +DWord Bit Description +64 31 Color Gamut Compression Enable + 30 Full Range Mapping Enable + Value Name + 0 Basic Mode [Default] + 1 Advanced Mode + 29:20 d(in,default) + Default Value: 205 + Format: U10 + din.defaultInnerTriangleMappingLength + + 19:10 d(out,default) + Default Value: 164 + Format: U10 + dout.defaultOuterTriangleMappingLength + + 9:0 d1(out) + Default Value: 287 + Format: U10 + d1outOuterTriangleMappingLengthBelow + +65 31 Reserved + Format: MBZ + 30:28 Compression Line Shift + Value Name + 0-4 + 3 [Default] + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 223 + COLOR_PROCESSING_STATE - CGC State + 27:10 Reserved + Format: MBZ + 9:0 d1(in) + Default Value: 820 + Format: U10 + d1inInnerTriangleMappingLengthBelow + +66 31 xvYcc Decode Encode Enable + Value Name Description + 1 [Default] Both xvYcc decode and xvYcc encode are enabled + 0 Disable both xvYcc decode and xvYcc encode + + + Programming Notes + This bit is valid only when ColorGamutCompressionnEnable is on. + 30 Forced 444 for 444 + Default Value: 0 + Force the 4:4:4 operation when input video of 4:4:4 format + + 29 Forced 422 for 444 + Default Value: 0 + Force the 4:2:2 operation when input video of 4:4:4 format + + 28 Forced 444 for 422 + Default Value: 0 + Force the 4:4:4 operation when input video of 4:2:2 format + + 27:26 STD Factor Mode + Value Name Description + 00b STDMin Select the minimum value of the STD factors + 01b STDMax Select the maximum value of the STD factors + 10b STDAve [Default] Select the average value of the STD factors + 11b Reserved + + + Programming Notes + This field is only valid for input of 4:2:2 (Forced444_for 422 is disabled), or when (Forced422_for444 + is enabled). + 25:24 MV Dark Factor Mode + Value Name Description + 00b MVDarkMin Select the minimum value of the MVDark factors + 01b MVDarkMax Select the maximum value of the MVDark factors + 10b MVDarkAve [Default] Select the average value of the MVDark factors + 11b Reserved + + + Programming Notes + This field is only valid for input of 4:2:2 (Forced444_for 422 is disabled), or when (Forced422_for444 + is enabled). + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 224 + COLOR_PROCESSING_STATE - CGC State + 23:22 Scaling Factor Mode + This mode is for color gamut compression module + Value Name Description + 00b SFMin Select the minimum value of the Scaling Factors + 01b SFMax Select the maximum value of the Scaling Factors + 10b SFAve [Default] Select the average value of the Scaling Factors + 11b Reserved + + + Programming Notes + This field is only valid for input of 4:2:2 (Forced444_for 422 is disabled), or when (Forced422_for444 + is enabled). + 21:5 Reserved + Format: Reserved + 4 Override Saturation Equal Zero + Format: MBZ + + + Programming Notes + This bit should always be 0. + 3:0 Display Color Space Mode + Value Name + 0 BT709 + 1 BT601 + 2-15 Reserved + + + + +3.9 Messages + +3.9.1 Global Definitions +For data port messages, part of the message descriptor is used to determine the message type. This field +is documented here. The remainder of the message descriptor is defined differently depending on the +message type, and is documented in the section for the corresponding message. +The Data Port is actually three separate targets, DataPort Sampler Cache, DataPort Constant Cache, +and Data Port Render Cache, each with its own target unit ID. Each target has its own set of message +type encodings as shown below. +Restrictions: +Data port messages may not have the End of Thread bit set in the message descriptor other than the +following exeptions: +The Render Target Write message may have End of Thread set for pixel shader threads dispatched by +the windower in non-contiguous dispatch mode. +The Render Target UNORM Write message may have End of Thread set for pixel shader threads +dispatched by the windower in contiguous dispatch mode. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 225 + The Media Block Write message may have End of Thread set for pixel shader threads dispatched by the +windower in contiguous dispatch mode. + + +3.9.2 Data Port Messages +Most of the messages have an existing definition that is not expected to change. There are several new +messages that are documented here. + +Data Cache Data Port Message Summary + Shared Local Memory Stateless Address Vector + Message Type Header Required Support Support Modes Width +OWord Block Read yes no yes global 1 +OWord Block Write yes no yes global 1 +Unaligned OWord Block yes no yes global 1 +Read +OWord Dual Block no yes global + offset 2 +Read + no for stated + yes for + stateless +OWord Dual Block no yes global + offset 2 +Write + no for stated + yes for + stateless +DWord Scattered Read no yes global + offset 8, 16 + no for stated + yes for + stateless +DWord Scattered Write no yes global + offset 8, 16 + no for stated + yes for + stateless +Byte Scattered Read yes global + offset 8, 16 + no for stated + yes for + stateless +Byte Scattered Write yes global + offset 8, 16 + no for stated + yes for + stateless +Untyped Surface Read yes 1D or 2D 2, 8, 16 + no for stated + yes for + stateless +Untyped Surface Write yes 1D or 2D 2, 8, 16 + no for stated + yes for + stateless + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 226 + Shared Local Memory Stateless Address Vector + Message Type Header Required Support Support Modes Width +Untyped Atomic yes 1D or 2D 8, 16 +Operation + no for stated + yes for + stateless +Scratch Block Read yes no yes (only) Imm_Buf + + offset +Scratch Block Write yes no yes (only) Imm_Buf + + offset +Memory Fence yes N/A N/A N/A N/A + +“global” is the Global Offset in the message header (if header is not present, Global Offset is zero). +“imm_buf” is the Immediate Buffer Base Address provided in message header register M0.5. +“offset” is in the message payload, and is per-slot. +“handle” is the handle address in the message header. +“URBoffset” is the Global Offset field in the URB message descriptor. +“1D” and “2D” are the address payload. +Render Cache Data Port Message Summary + Message Type Header Required Address Modes Vector Width +Media Block Read yes 2D 1 +Media Block Write yes 2D 1 +Render Target Write 2D + RTAI 8, 16 + No + 1 + + + +Typed Surface Read yes 1D, 2D, 3D, 4D 8 +Typed Surface Write yes 1D, 2D, 3D, 4D 8 +Typed Atomic Operation yes 1D, 2D, 3D, 4D 8 +Memory Fence yes N/A N/A + +“4D” address refers to U/V/R/LOD for mip-mapped surfaces +“2D + RTAI” address refers to a basic 2D address with render target array index for the third dimension + +3.9.2.1 Message Descriptor +The following message descriptor applies to. +DATA PORT SAMPLER DATA PORT CONSTANT DATA PORT RENDER CACHE +CACHE CACHE +Bit Description Bit Description Bit Description +19 + Header Present. If set, indicates that the message includes the header. Refer to Render + Target Write message section for more details on this field. + Programming Notes: + The header must be present unless the message type is Render Target Write + Format = Enable +18 Ignored +17:16 Ignored 17:16 Ignored 17 + Send Write Commit Message. Indicates + that a write commit message will be sent + back to the thread when the write has + been committed. See section Write + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 227 + DATA PORT SAMPLER DATA PORT CONSTANT DATA PORT RENDER CACHE +CACHE CACHE + Commit for more details. This field is + ignored on read message types. + Format = Enable +15:13 15:13 16:13 + Message Message Message Type + Type Type + 0000: OWord Block Read + 000: OWord 000: OWord + 0001: Render Target UNORM Read + Block Read Block Read + 0010: OWord Dual Block Read + 010: OWord 010: OWord + Dual Block Dual Block 0100: Media Block Read + Read Read + 0101: Unaligned OWord Block Read + 100: Media 110: DWord + 0110: DWord Scattered Read + Block Read Scattered + Read 0111: DWord Atomic write message + 101: + Unaligned All other 1000: OWord Block Write + OWord Block encodings + 1001: OWord Dual Block Write + Read are reserved. + 1010: Media Block Write + 110: DWord + Scattered 1011: DWord Scattered Write + Read + 1100: Render Target Write + All other + 1101: Streamed Vertex Buffer Write + encodings + are reserved. 1110: Render Target UNORM Write + All other encodings are reserved. +12:8 + Message Specific Control. Refer to the specific message section for the definition of these bits. + +7:0 + Binding Table Index. Specifies the index into the binding table for the specified surface. A + binding table index of 255 indicates that a stateless model is to be used. The stateless model + is allowed only with the render cache data port. Refer to section 2.2.2 for details on the + stateless model. + Format = U8 + Range = [0,255] + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 228 + 3.9.2.1.1 Message Descriptor +The following message descriptor applies to. + SAMPLER CACHE DATA PORT RENDER CACHE DATA PORT + Bit Description Bit Description +19 + Header Present. If set, indicates that the message includes the header. + + Programming Notes: + + For the Render Cache Data Port, the header must be present for the following message + types: + Typed Surface Read/Write + Typed Surface Atomic Operation + Memory Fence + For the Sampler Cache Data Port, the header must be present for the following message + types: + Unaligned OWord Block Read + Media Block Read. + Format = Enable +18 Ignored 18 Ignored +17:14 17:14 + Message Type Message Type + 0001: Unaligned OWord Block Read 0100: Media Block Read + 0100: Media Block Read 0101: Typed Surface Read + All other encodings are reserved. 0110: Typed Atomic Operation + 0111: Memory Fence + 1010: Media Block Write + 1100: Render Target Write + 1101: Typed Surface Write + All other encodings are reserved. +13:8 + Message Specific Control. Refer to the specific message section for the definition of these bits. + +7:0 + Binding Table Index. Specifies the index into the binding table for the specified surface. + Format = U8 + Range = [0,255] + + + CONSTANT CACHE DATA PORT DATA CACHE DATA PORT + Bit Description Bit Description +19 + Header Present. If set, indicates that the message includes the header. + Programming Notes: + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 229 + CONSTANT CACHE DATA PORT DATA CACHE DATA PORT + Bit Description Bit Description + For the Data Cache Data Port, the header must be present for the following message types: + OWord Block Read/Write + Unaligned OWord Block Read + Memory Fence + Scratch read/write + For the Constant Cache Data Port, the header must be present for the following message + types: + OWord Block Read + Unaligned OWord Block Read. + Format = Enable +18 Ignored 18 + Category + 0: Legacy DAP-DC messages + 1: Scratch Block Read/Write messages +17:14 17:14 + Message Type Category=0 (legacy dataport) + 0000: OWord Block Read Message Type + 0001: Unaligned OWord Block Read 0000: OWord Block Read + 0010: OWord Dual Block Read 0001: Unaligned OWord Block Read + 0011: DWord Scattered Read 0010: OWord Dual Block Read + All other encodings are reserved. 0011: DWord Scattered Read + 0100: Byte Scattered Read + 0101: Untyped Surface Read + 0110: Untyped Atomic Operation + 0111: Memory Fence + 1000: OWord Block Write + 1010: OWord Dual Block Write + 1011: DWord Scattered Write + 1100: Byte Scattered Write + 1101: Untyped Surface Write + All other encodings are reserved. + Category=1 (scratch) + [17]: 0=Read; 1=write + [16]:Type; + 0=Oword, 1= Dword + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 230 + CONSTANT CACHE DATA PORT DATA CACHE DATA PORT + Bit Description Bit Description + [15]:Invalidate after read; + [14]: + [13:12]: Block Size + 11: 4 registers + 10: + 01: 2 registers + 00: 1 register + [11:0]: Addr offset (Hword based) +13:8 + Message Specific Control. Refer to the specific message section for the definition of these + bits. +7:0 + Binding Table Index. Specifies the index into the binding table for the specified surface. + For the data cache data port, two binding table indexes are used to select special surfaces: + 254: A binding table index of 254 indicates that the shared local memory (SLM) is to be used. + The SLM is only supported with the Byte Scattered Read/Write, Untyped Surface Read/Write, + and Untyped Atomic Operation messages. Refer to the “Shared Local Memory” section + earlier in this chapter for further details on its behavior. + 255: A binding table index of 255 indicates that a stateless model is to be used. Stateless + model is only supported with the OWord Block Read/Write, Unaligned OWord Block Read, + Dual OWord Block Read/Write and DWord Scattered Read/Write messages. Refer to section + “Stateless Model” section for details on the stateless model. + Format = U8 + Range = [0,255] + + +3.9.2.2 Message Header +This header applies to the following data port messages: + +  OWord Block Read/Write +  Unaligned OWord Block Read +  OWord Dual Block Read/Write +  DWord Scattered Read/Write +  Byte Scattered Read/Write +  Scratch Block Read/Write + +The header definitions for the other data port messages is in the section for each message. +DWord Bit Description +M0.7 31:0 +M0.6 31:0 +M0.5 31:10 + Immediate Buffer Base Address. Specifies the surface base address for messages in + which the Binding Table Index is 255 (stateless model), otherwise this field is ignored. + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 231 + DWord Bit Description + This pointer is relative to the General State Base Address. + Format = GeneralStateOffset[31:10] + 9:8 Ignored + 7:0 + Dispatch ID. This ID is assigned by the fixed function unit and is a unique identifier for + the thread. It is used to free up resources used by the thread upon thread completion. +M0.4 31:0 Ignored (reserved for hardware delivery of binding table pointer) +M0.3 31:4 Ignored + 3:0 + Programming Notes: + This amount is available to the kernel for information only. It will be passed verbatim (if + not altered by the kernel) to the Data Port in any scratch space access messages. The + data port will use this to bounds check scratch space messages. Writes out of bounds + will be ignored. Reads out of bounds will return 0. + Format = U4 + Range = [0,11] indicating [1k bytes, 2M bytes] in powers of two +M0.2 31:0 + Global Offset. + : + Specifies the global element offset into the buffer. + For the Unaligned OWord messages, this offset is in units of Bytes but must be DWord + aligned (bits 1:0 MBZ) + For the other OWord messages, this offset is in units of OWords + For the DWord messages, this offset is in units of DWords + For the Byte messages, this offset is in units of Bytes + Format = U32 + Range = [0,FFFFFFFCh] for Unaliged OWord messages + Range = [0,0FFFFFFFh] for other OWord messages + Range = [0,3FFFFFFFh] for DWord messages + Range = [0,FFFFFFFFh] for Byte messages +M0.1 31:0 Ignored +M0.0 31:0 Ignored + + +3.9.2.3 Write Commit Writeback Message +The writeback message is only sent on Data Port Write messages if the Send Write Commit Message +bit in the message descriptor is set. The destination register is not modified. Write messages without the +Send Write Commit Message bit set will not return anything to the thread (response length is 0 and +destination register is null). +DWord Bit Description +W0.7:0 Reserved + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 232 + 3.9.3 OWord Block Read/Write +This message takes one offset (Global Offset), and reads or writes 1, 2, 4, or 8 contiguous OWords +starting at that offset. +Restrictions: +1. the only surface type allowed is SURFTYPE_BUFFER. +2. the surface format is ignored, data is returned from the constant buffer to the GRF without format + conversion. +3. the surface pitch is ignored, the surface is treated as a 1-dimensional surface. An element size + (pitch) of 16 bytes is used to determine the size of the buffer for out-of-bounds checking if using the + surface state model. +4. the surface cannot be tiled +5. the surface base address must be OWord aligned +6. the Render Cache Read Write Mode field in SURFACE_STATE must be set to read/write mode + when using this message with the render cache in the surface state model +7. the Stateless Render Cache Read-Write Mode field in the SVG_WORK_CTL register must be set + to read/write mode when using this message with the render cache in the stateless model +Applications: +Constant buffer reads of a single constant or multiple contiguous constants. +Scratch space reads/writes where the index for each pixel/vertex is the same. +Block constant reads, scratch memory reads/writes for media. +Execution Mask. The low 8 bits of the execution mask are used to enable the 8 channels in the first and +third GRF registers returned (W0, W2) for read, or the first and third write registers sent (M1, M3). The +high 8 bits are used similarly for the second and fourth (W1, W3 or M2, M4). For reads, any mask bit +asserted within a group of four will cause the entire OWord to be read and returned to the destination +GRF register. For writes, each mask bit is considered for its corresponding DWord written to the +destination surface. +For the 1-OWord messages, only the low 8 bits of the execution mask are used. Either the low 4 bits or +the high 4 bits, depending on the position of the OWord to be read or written, is used as the single group +of four with behavior following that in the preceding paragraph. +The above behavior enables a SIMD16 thread to use the 8-OWord form of this message to access two +channels (red and green) of a single scratch register across 16 pixels. A second message would access +the other two channels (blue and alpha). The execution mask is used to ensure that data associated with +inactive pixels are not overwritten. +Out-of-Bounds Accesses. Reads to areas outside of the surface return 0. Writes to areas outside of the +surface are dropped and will not modify memory contents. + +3.9.3.1 Message Descriptor +Bit Description +13 + Invalidate After Read Enable + This field, if enabled, causes all lines in the L3 cache accessed by the message to be + invalidated after the read occurs, regardless of whether the line contains modified data. It is + intended as a performance hint indicating that the data will no longer be used to avoid writing + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 233 + Bit Description + back data to memory. This field is ignored for write messages. + Enabling this field is intended for scratch and spill/fill, where the memory is used only by a + single thread and thus does not need to be maintained after the thread completes. + Format = Enable +12 + Ignored +11 + Ignored +10:8 + Block Size. Specifies the number of contiguous OWords to be read or written + + 000: 1 OWord, read into or written from the low 128 bits of the destination register + 001: 1 OWord, read into or written from the high 128 bits of the destination register + 010: 2 OWords + 011: 4 OWords + 100: 8 OWords + all other encodings are reserved. + Programming Notes: + + The 6 OWord block size is valid only with Data Port Constant Cache. + + +3.9.3.2 Message Payload (Write) +For the write operation, the message payload consists of one, two, or four registers (not including the +header) depending on the Block Size specified in the message. For the one-constant case, data is taken +from either the high or low half of the payload register depending on the half selected in Block Size. In +this case, the other half of the payload register is ignored. +The Offset referred to below is the Global Offset and is in units of OWords. The OWord array index is +also in units of OWords. +DWord Bit Description +M1.7:4 127:0 + OWord[Offset + 1]. If the block size is 1 OWord to be written from the high 128 bits of + the destination, OWord[Offset] will appear in this location +M1.3:0 127:0 OWord[Offset] +M2.7:4 127:0 OWord[Offset+3] +M2.3:0 127:0 OWord[Offset+2] +M3.7:4 127:0 OWord[Offset+5] +M3.3:0 127:0 OWord[Offset+4] +M4.7:4 127:0 OWord[Offset+7] +M4.3:0 127:0 OWord[Offset+6] + + +3.9.3.3 Writeback Message (Read) +For the read operation, the writeback message consists of one, two, three, or four registers depending on +the Block Size specified in the message. For the one-constant case, data is placed in either the high or + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 234 + low half of the returned register depending on the half selected in Block Size. In this case, the other half +of the register is not changed. +The Offset referred to below is the Global Offset and is in units of OWords. The OWord array index is +also in units of OWords. +DWord Bit Description +W0.7:4 127:0 + OWord[Offset + 1]. If the block size is 1 OWord to be loaded into the high 128 bits of + the destination, OWord[Offset] will appear in this location +W0.3:0 127:0 OWord[Offset] +W1.7:4 127:0 OWord[Offset+3] +W1.3:0 127:0 OWord[Offset+2] +W2.7:4 127:0 OWord[Offset+5] +W2.3:0 127:0 OWord[Offset+4] +W3.7:4 127:0 OWord[Offset+7] +W3.3:0 127:0 OWord[Offset+6] + + +3.9.4 Unaligned OWord Block Read +This message takes one DWord aligned offset (Global Offset), and reads 1, 2, 4, or 8 contiguous +OWords starting at that offset. This message is identical to the OWord Block Read message except the +offset alignment. For read/write cache, only the read path supports this unaligned OWord Block access. +Restrictions: +1. the only surface type allowed is SURFTYPE_BUFFER. +2. the surface format is ignored, data is returned from the constant buffer to the GRF without format + conversion. +3. the surface pitch is ignored, the surface is treated as a 1-dimensional surface. An element size + (pitch) of 16 bytes is used to determine the size of the buffer for out-of-bounds checking if using the + surface state model. +4. the surface cannot be tiled +5. the surface base address must be OWord aligned +6. the Render Cache Read Write Mode field in SURFACE_STATE must be set to read/write mode + when using this message with the render cache in the surface state model +7. the Stateless Render Cache Read-Write Mode field in the SVG_WORK_CTL register must be set + to read/write mode when using this message with the render cache in the stateless model +Applications: +Reads with offset that is not aligned with data size, such as row store usage in media +Execution Mask. The execution mask is ignored by this message. +Out-of-Bounds Accesses. Reads to areas outside of the surface return 0. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 235 + 3.9.4.1 Message Descriptor + Bit Description + 13 + Ignored +12:11 Ignored + 10:8 + Block Size. Specifies the number of contiguous OWords to be read + + 000: 1 OWord, read into the low 128 bits of the destination register + 001: 1 OWord, read into the high 128 bits of the destination register + 010: 2 OWords + 011: 4 OWords + 100: 8 OWords + all other encodings are reserved. + + +3.9.4.2 Writeback Message (Read) +For the read operation, the writeback message consists of one, two, or four registers depending on the +Block Size specified in the message. For the one-constant case, data is placed in either the high or low +half of the returned register depending on the half selected in Block Size. In this case, the other half of +the register is not changed. +The Global Offset is in units of Bytes, aligned to DWord (two LSBs set to zero). The OWordX array in +units of OWord starts at Global Offset. +DWord Bit Description +W0.7:4 127:0 + OWord1 = *(&OWord0 + 1). If the block size is 1 OWord to be loaded into the high 128 + bits of the destination, OWord0 will appear in this location +W0.3:0 127:0 OWord0 = Buffer[Global Offset] +W1.7:4 127:0 OWord3 = *(&OWord2 + 1) +W1.3:0 127:0 OWord2 = *(&OWord1 + 1) +W2.7:4 127:0 OWord5= *(&OWord4 + 1) +W2.3:0 127:0 OWord4 = *(&OWord3 + 1) +W3.7:4 127:0 OWord7 = *(&OWord6 + 1) +W3.3:0 127:0 OWord6 = *(&OWord5 + 1) + + +3.9.5 OWord Dual Block Read/Write +This message takes two offsets, and reads or writes 1 or 4 contiguous OWords starting at each offset. +The Global Offset is added to each of the specific offsets. + The message header is no longer required for the OWord Dual Block Read/Write messages if sent to the data +cache data port. If header is not sent, the Global Offset field is assumed to be zero. The header is required, +however, if the binding table index is 255 (stateless model), as the Immediate Buffer Base Address field is +required. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 236 + Programming Restrictions: Writes to overlapping addresses will have undefined write ordering. +Restrictions: +1. The only surface type allowed is SURFTYPE_BUFFER. +2. The surface format is ignored, data is returned from the constant buffer to the GRF without format + conversion. +3. The surface pitch is ignored, the surface is treated as a 1-dimensional surface. An element size + (pitch) of 16 bytes is used to determine the size of the buffer for out-of-bounds checking if using the + surface state model. +4. The surface cannot be tiled +5. The surface base address must be OWord aligned +6. The Render Cache Read Write Mode field in SURFACE_STATE must be set to read/write mode + when using this message with the render cache in the surface state model +7. the Stateless Render Cache Read-Write Mode field in the SVG_WORK_CTL register must be set + to read/write mode when using this message with the render cache in the stateless model +Applications: +SIMD4x2 constant buffer reads where the indices of each vertex/pixel are different (if there are two +indices and they are the same, hardware will optimize the cache accesses and do only one cache +access) +SIMD4x2 scratch space reads/writes where the indices are different +Execution Mask. The low 8 bits of the execution mask are used to enable the 8 channels in the GRF +registers returned for read, or each of the write registers sent. For reads, any mask bit asserted within a +group of four will cause the entire OWord to be read and returned to the destination GRF register. For +writes, each mask bit is considered for its corresponding DWord written to the destination surface. +Out-of-Bounds Accesses. Reads to areas outside of the surface return 0. Writes to areas outside of the +surface are dropped and will not modify memory contents. + +3.9.5.1 Message Descriptor + Bit Description + 13 + Invalidate After Read Enable + This field, if enabled, causes all lines in the L3 cache accessed by the message to be + invalidated after the read occurs, regardless of whether the line contains modified data. It is + intended as a performance hint indicating that the data will no longer be used to avoid writing + back data to memory. This field is ignored for write messages. + Enabling this field is intended for scratch and spill/fill, where the memory is used only by a + single thread and thus does not need to be maintained after the thread completes. + Format = Enable + 12 + Ignored +11:10 + Ignored + 9:8 + Block Size: Specifies the number of OWords in each block to be read or written + 00: 1 OWord + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 237 + Bit Description + 10: 4 OWords + all other encodings are reserved. + + +3.9.5.2 Message Payload +DWord Bit Description + M1.7 31:0 Ignored + M1.6 31:0 Ignored + M1.5 31:0 Ignored + M1.4 31:0 + Block Offset 1. + Specifies the OWord offset of OWord Block 1 into the surface. + Format = U32 + Range = [0,0FFFFFFFh] + M1.3 31:0 Ignored + M1.2 31:0 Ignored + M1.1 31:0 Ignored + M1.0 31:0 Block Offset 0 + + +3.9.5.3 Additional Message Payload (Write) +For the write operation, the message payload consists of one or four registers (not including the header or +the first part of the payload) depending on the Block Size specified in the message. +The Offset1/0 referred to below is the Global Offset added to the corresponding Block Offset 1/0 and is +in units of OWords . The OWord array index is also in units of OWords. +DWord Bit Description +M2.7:4 127:0 OWord[Offset1] +M2.3:0 127:0 OWord[Offset0] +M3.7:4 127:0 OWord[Offset1+1] +M3.3:0 127:0 OWord[Offset0+1] +M4.7:4 127:0 OWord[Offset1+2] +M4.3:0 127:0 OWord[Offset0+2] +M4.7:4 127:0 OWord[Offset1+3] +M4.3:0 127:0 OWord[Offset0+3] + + +3.9.5.4 Writeback Message (Read) +For the read operation, the writeback message consists of one or four registers depending on the Block +Size specified in the message. +The Offset1/0 referred to below is the Global Offset added to the corresponding Block Offset 1/0 and is +in units of Owords. The OWord array index is also in units of OWords. + DWord Bit Description +W0.7:4 127:0 OWord[Offset1] +W0.3:0 127:0 OWord[Offset0] +W1.7:4 127:0 OWord[Offset1+1] +W1.3:0 127:0 OWord[Offset0+1] + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 238 + DWord Bit Description +W2.7:4 127:0 OWord[Offset1+2] +W2.3:0 127:0 OWord[Offset0+2] +W3.7:4 127:0 OWord[Offset1+3] +W3.3:0 127:0 OWord[Offset0+3] + + +3.9.6 Media Block Read/Write +The read form of this message enables a rectangular block of data samples to be read from the source +surface and written into the GRF. The write form enables data from the GRF to be written to a rectangular +block. +Restrictions: +1. The only surface type allowed is non-arrayed, non-mipmapped SURFTYPE_2D. Because of this, the + stateless surface model is not supported with this message. +2. The surface format is used to determine the pixel structure for boundary clamp, the raw data from + the surface is returned to the thread without any format conversion nor filtering operation +3. The target cache cannot be the data cache +4. The surface base address must be 32-byte aligned +5. When a surface is XMajor tiled, (tilewalk field in the surface state is set to TILEWALK_XMAJOR), a + memory area mapped through the Render Cache cannot be read and/or wrote in mixed frame and + field modes. For example, if a memory location is first written with a zero Vertical Line Stride (frame + mode), and later on (without render cache flush) read back using Vertical Line Stride of one (field + mode), the read data stored in GRF are uncertain. +6. The block width and offset should be aligned to the size of pixels stored in the surface. For a surface + with 8bpp pixels for example, the block width and offset can be byte aligned. For a surface with + 16bpp pixels, it is word aligned. +7. For YUV422 formats, the block width and offset must be pixel pair aligned (i.e. dword aligned). +8. The write form of message has the additional restriction that both X Offset and Block Width must + be DWord aligned. +9. Pitch must be a multiple of 64 bytes when the surface is linear. +Applications: +Block reads/writes for media +Execution Mask. The execution mask on the send instruction for this type of message is ignored. The +data that is read or written is determined completely by the block parameters. +Out-of-Bounds Accesses. Reads outside of the surface results in the address being clamped to the +nearest edge of the surface and the pixel in the position being returned. Writes outside of the surface are +dropped and will not modify memory contents. +Determining the boundary pixel value depends on the surface format. Surface format definitions can be +found in the Surface Formats Section of the Sampling Engine Chapter. +For a surface with 8bpp pixels, the boundary byte is replicated. For example, for a boundary dword +B0B1B2B3, to replicate the left boundary byte pixel, the out of bound dwords have the format of +B0B0B0B0, and that for right boundary is B3B3B3B3. +This rule applies to all surface formats with BPE of 8. As the data port does not perform format +conversion, the most likely used surface formats are R8_UINT and R8_SINT. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 239 + For any other surfaces with 16bpp pixels, boundary pixel replication is on words. For example, for a +boundary dword B0B1B2B3, to replicate the left boundary word pixel, the out of bound dwords have the +format of B0B1B0B1, and that for right boundary is B2B3B2B3. +This rule applies to all surface formats with BPE of 16. As the data port does not perform format +conversion, only the formats with integer data types may be useful in practice. +For special surfaces with 16bpp pixels YUV422 packed format, there are two basic cases depending on +the Y location: YUYV (surface format YCRCB_NORMAL) and UYVY (surface format YCRCB_SWAPY). +Boundary handling for YVYU (surface format YCRCB_SWAPUV) is the same as that for YUYV. Similarly, +boundary handling for VYUY (surface format YCRCB_SWAPUVY) is the same as that for UYVY. Note +that these four surface formats have 16bpp pixels, even though the BPE fields are set to zero according +to the table in the Surface Formats Section. +For a boundary dword Y0U0Y1V0, to replicate the left boundary, we get Y0U0Y0V0, and to replicate the +right boundary, we get Y1U0Y1V0. +For a boundary dword U0Y0V0Y1, to replicate the left boundary, we get U0Y0V0Y0, and to replicate the +right boundary, we get U0Y1V0Y1. +For a surface with 32bpp pixels, the boundary dword pixel is replicated. +This rule applies to all surface formats with BPE of 32. As the data port does not perform format +conversion, some of the formats may not be useful in practice. +Hardware behavior for any other surface types is undefined. +When Color Processing Enable is set to 1 and the IECP output surface to be written is NV12 format +(R16_UNORM surface format 0x10A, should be used if the output surface is NV12 format). +NV12 surface state : The width of the surface should be always multiples of 4pixels. For 16bpp input +message (422 8-bit) the width will always need to be in multiples of 8bytes and for 32bpp input message +(422 16-bit or 444 8-bit) the width should be in multiples of 16bytes. Height should be in multiples of +2pixel high. (presently the MFX restriction is that width should be in multiples of 2pixels). +y-offset of the media block write from the EU should be always even +x-offset of the media block write from the EU should be in multiples of 4 pixel. +The media block dword write can have only the following combinations (for IECP when NV12 output +format is used): + +  8pixel wide for 422 8-bit mode +  4pixel wide for 422 8-bit mode +  4pixel wide for 422 16-bit +  4pixel wide for 444 8-bit. +  444 16-bit input format cannot be supported when the output format is NV12 (s/w should not use this + combination). +  It has to be in multiples of 2pixel high for all above modes. + +If 444-format is used then we use only the pixel_0 UV values of the 2x2 pixel and the rest are dropped +and in case of 422-format the top UV values are used and the bottom UV values is dropped if the output +format is NV12 format. +Assuming IECP messages will always have vertical stride = 0. (since this is only for pre-processing before +the encoder). + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 240 + 3.9.6.1 Message Descriptor +Bit Description +13 + Reserved: MBZ +12 + Reserved : MBZ +11 + Reserved : MBZ +10 + Vertical Line Stride Override + Specifies whether the Vertical Line Stride and Vertical Line Stride Offset fields in the surface + state should be replaced by bits 9 and 8 below. + If this field is 1, Height in the surface state (see SURFACE_STATE section of Sampling Engine + chapter) is modified according the following rules: + + Vertical Line Derived 1-based surface height + Stride + (As a function of the 0-based Height in surface state) + (in surface state) Override Vertical Line + Stride + 0 0 + Height + 1 + (Normal) + 0 1 + (Height +1) / 2 + Restriction: (Height + 1) must be an even + number. + 1 0 (Height + 1) * 2 + 1 1 + Height + 1 + (Normal) + + For example, for a 720x480 standard resolution video buffer, if Vertical Line Stride in surface + state is 0, i.e. a frame, Height (of the frame) should be 479. When accessing the bottom field of + this frame video buffer, both Override Vertical Line Stride and Override Vertical Line Stride + Offset will be set to 1, then the derived surface height (of the field) will be 240 ((Height + 1) / 2). + In contrary, if Vertical Line Stride in surface state is 1 and Vertical Line Stride Offset in surface + state is 0, the surface state represents the top field of the video buffer. In this case, Height (of + the top field) should be programmed as 239. Accessing the bottom video field will use the same + surface height of 240. Accessing the video frame (with Override Vertical Line Stride and + Override Vertical Line Stride Offset set to 0) will result in a derived surface height of 480 + ((Height + 1) * 2). + 0 -- Use parameters in the surface state and ignore bits 9:8 + 1 -- Use bits 9:8 to provide the Vertical Line Stride and Vertical Line Stride Offset + + +9 Override Vertical Line Stride + Specifies number of lines (0 or 1) to skip between logically adjacent lines – provides support of + interleaved (field) surfaces as textures. + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 241 + Bit Description + Format = U1 in lines to skip between logically adjacent lines + +8 Override Vertical Line Stride Offset + Specifies the offset of the initial line from the beginning of the buffer. Ignored when Override + VerticalLine Stride is 0. + + Format = U1 in lines of initial offset (when Vertical Line Stride == 1) + + +3.9.6.2 Message Header +DWord Bit Description +M0.7 31:0 +M0.6 31:0 +M0.5 31:8 Ignored + 7:0 + FFTID. This ID is assigned by the fixed function unit and is a unique identifier for the + thread. It is used to free up resources used by the thread upon thread completion. +M0.4 31:0 Ignored (reserved for hardware delivery of binding table pointer) +M0.3 31:5 + Color Processing State Pointer. Defines the pointer to COLOR_PROCESSING_STATE. + Ignored on read messages and when Color Processing Enable is not set. This pointer is + relative to the General State Base Address. + + Programming Notes: + This pointer is not delivered via state variables like most other pointers are delivered. It + must be delivered via another software-defined mechanism such as CURBE. + Format = GeneralStateOffset[31:5] + 4 + Message Mode + This field selects the mode of this message as follows: + 0: NORMAL. The Block Height and Block Width fields are set in M0.2. The Pixel Mask + is not explicitly set but behaves as if it is set to all ones. + 1: PIXEL_MASK: The Pixel Mask field is set in M0.2. The Block Height and Block Width + are not explicitly set but behave as if they are set to 4 rows and 32 bytes, respectively. + 3:2 + Message Format. Defines the format of the message if Color Processing Enable is set. + + 0: YUV 4:2:2, 8 bits per channel + 1: YUV 4:4:4, 8 bits per channel + 2: YUV 4:2:2, 16 bits per channel + 3: YUV 4:4:4, 16 bits per channel + 1 + Area of Interest. This field controls whether the statistic for the luma pixels is collected at VSC + for ACE histogram. This field is effective only when the state variable Full_image_histogram is + disabled. + 0 + Color Processing Enable. This field controls whether color processing is enabled on a + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 242 + DWord Bit Description + media block write message. + Format = Enable + This bit must be set to zero on a Media Block Read to the Render Cache. + + The following M0.2 definition applies only if the Message Mode field is set to NORMAL: +M0.2 31:29 Ignored + 28:24 + Programming Notes: + Sub-Register Offset must be aligned to BasePitch (therefore will be a multiple of + DWords as well). + When Register Pitch Control = 0, Sub-Register Offset must align to BasePitch*Block + Height and the output fits in a single GRF register. + + In general (and specifically when Sub-Register Offset is greater than 0), when the + resulting data cross GRF register boundary, the data must be placed symmetrically + between GRF registers. + Sub-Register Offset and Register Pitch Control allow software to assembly multiple + media block reads directly into a shared GRF register set. For example, if both are set + to zero, the read data are written to GRF registers, aligning to the least significant bits + of the first register, and the register pitch is equal to the next power-of-2 that is greater + than or equal to the Block Width. If Register Pitch Control is non-zero, multiple media + block read messages sharing the same Register Pitch Control but with different Sub- + Register Offset can fill in the same set of GRF registers with media block data line + interleaved. + Format = U5 + Range = [0, 28] (Only a multiple of BasePitch, including 0, is valid) + Programming Note: This field must be zero for Render Cache Data Port. + + 21:16 + Block Height. Height in rows of block being accessed. + + Programming Notes: + The Block Height is restricted to the following maximum values depending on the + Block Width: + Block Width (bytes) Maximum Block Height (rows) + 1-4 64 + 5-8 32 + 9-16 16 + 17-32 8 + + Format = U6 + Range = [0,63] representing 1 to 64 rows + + 15:10 Ignored + 9:8 + Programming Notes: + Register Pitch Control is only allowed to be non-zero, if Block Width is a multiple of + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 243 + DWord Bit Description + DWords. The effective register pitch must be less than or equal to 32 bytes (to fit in a + single GRF register). + Defining BasePitch as the next power-of-2 that is greater than or equal to the Block + Width, Register Pitch Control set the register pitch in term of BasePitch as the following. + + Range = [0,3] representing 1 to 4 BasePitch + Programming Note: This field must be zero for Render Cache Data Port. + + 7:5 Ignored + 4:0 + Block Width. Width in bytes of the block being accessed. + + Programming Notes: + Must be DWord aligned for the write form of the message. +The following M0.2 definition applies only if the Message Mode field is set to PIXEL_MASK: +MO.2 31:0 + Pixel Mask. One bit per pixel (each pixel being a DWord) indicating which pixels are to + be written. This field is ignored by the read message, all pixels are always returned.. + The bits in this mask correspond to the pixels (DWords) as follows: + 0 1 4 5 16 17 20 21 + 2 3 6 7 18 19 22 23 + 8 9 12 13 24 25 28 29 + 10 11 14 15 26 27 30 31 +M0.1 31:0 + Y offset. The Y offset of the upper left corner of the block into the surface. + + Format = S31 + Programming Notes: + If Message Mode is set to PIXEL_MASK, this field must be a multiple of 4 +M0.0 31:0 + X offset. The X offset of the upper left corner of the block into the surface. + + Must be DWord aligned (Bits 1:0 MBZ) for the write form of the message. + The X offset field defines the offset in the input message block. This may differ from + the offset in the surface if Color Processing is enabled due to format conversion. + Programming Notes: + If Message Mode is set to PIXEL_MASK, this field must be a multiple of 32 + +Programming Note: The legal combinations of block width, pitch control, sub-register offset and block +height are given below: +Block Height for given block width, pitch control, subreg offsets + sub-register offsets +block width pitch control 0 1 2 3 4 5 6 7 +1-4 00 1-64 1 1 1 1 1 1 1 + 01 1-64 1-64 illegal illegal 1-2 1-2 illegal illegal + 10 illegal illegal illegal illegal illegal illegal illegal illegal + 11 1-64 1-64 1-64 1-64 illegal illegal illegal illegal +5-8 00 1-32 illegal 1 illegal 1 illegal 1 illegal + 01 1-32 illegal 1-32 illegal illegal illegal illegal illegal + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 244 + 10 illegal illegal illegal illegal illegal illegal illegal illegal + 11 1-32 illegal 1-32 illegal 1-32 illegal 1-32 illegal +9-16 00 1-16 illegal illegal illegal 1 illegal illegal illegal + 01 1-16 illegal illegal illegal 1-16 illegal illegal illegal + 10 illegal illegal illegal illegal illegal illegal illegal illegal + 11 1-16 illegal illegal illegal 1-16 illegal illegal illegal +7-32 00 1-8 illegal illegal illegal illegal illegal illegal illegal + 01 1-8 illegal illegal illegal illegal illegal illegal illegal + 10 illegal illegal illegal illegal illegal illegal illegal illegal + 11 1-8 illegal illegal illegal illegal illegal illegal illegal + + +3.9.6.3 Message Payload (Write) +DWord Bit Description +M1:n + Write Data. The format of the write data depends on the Block Height and Block Width. + The data is aligned to the least significant bits of the first register, and the register pitch is + equal to the next power-of-2 that is greater than or equal to the Block Width. + +If Color Processing Enable is enabled, the write data is divided into pixels according to the Message +Format field. The fields within each pixel are defined below. For the 4:2:2 modes, each pixel position +includes channels for two pixels. +Message Format 31:24 23:16 15:8 7:0 +YUV 4:2:2, 8 bits per channel Cr (V) right pixel lum (Y1) Cb (U) left pixel lum (Y0) +YUV 4:4:4, 8 bits per channel alpha (A) luminance (Y) Cb (U) Cr (V) + 63:48 47:32 31:16 15:0 +YUV 4:2:2, 16 bits per channel Cr (V) right pixel lum (Y1) Cb (U) left pixel lum (Y0) +YUV 4:4:4, 16 bits per channel alpha (A) Cr (V) luminance (Y) Cb (U) + + +3.9.6.4 Writeback Message (Read) +DWord Bit Description +W0:n + Read Data. The format of the read data depends on the Block Height and Block Width. The data + is aligned to the least significant bits of the first register, and the register pitch is equal to the next + power-of-2 that is greater than or equal to the Block Width. + + . + + + +3.9.7 DWord Scattered Read/Write +This message takes a set of offsets, and reads or writes 8 or 16 scattered DWords starting at each offset. +The Global Offset is added to each of the specific offsets. +The message header is no longer required for the OWord DWord Scattered Read/Write messages if sent +to the data cache data port. If header is not sent, the Global Offset field is assumed to be zero. The +header is required, however, if the binding table index is 255 (stateless model), as the Immediate Buffer +Base Address field is required. +Programming Restrictions: Writes to overlapping addresses will have undefined write ordering. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 245 + For read messages with X/Y offsets that are outside the bounds of the surface, the address is clamped to +the nearest edge of the surface. For write messages with X/Y offsets that are outside the bounds of the +surface, the behavior is undefined. +Hardware does check for and optimize for cases where offsets are equal or contiguous, however for +optimal performance in some these cases a different message may provide higher performance. +Restrictions: +The only surface type allowed is SURFTYPE_BUFFER. +The surface format is ignored, data is returned from the constant buffer to the GRF without format +conversion. +The surface pitch is ignored, the surface is treated as a 1-dimensional surface. An element size (pitch) of 16 bytes is +used to determine the size of the buffer for out-of-bounds checking if using the surface state model. +The surface cannot be tiled +The surface base address must be DWord aligned +The Render Cache Read Write Mode field in SURFACE_STATE must be set to read/write mode when +using this message with the render cache in the surface state model +The Stateless Render Cache Read-Write Mode field in the SVG_WORK_CTL register must be set to +read/write mode when using this message with the render cache in the stateless model +Applications: +SIMD8/16 constant buffer reads where the indices of each pixel are different (read one channel per +message) +SIMD8/16 scratch space reads/writes where the indices are different (read/write one channel per +message) +general purpose DWord scatter/gathering, used by media +Execution Mask. Depending on the block size, either the low 8 bits or all 16 bits of the execution mask +are used to determine which DWords are read into the destination GRF register (for read), or which +DWords are written to the surface (for write). +Out-of-Bounds Accesses. Reads to areas outside of the surface return 0. Writes to areas outside of the +surface are dropped and will not modify memory contents. + +3.9.7.1 Message Descriptor + Bit Description + 13 + Invalidate After Read Enable + + This field, if enabled, causes all lines in the L3 cache accessed by the message to be + invalidated after the read occurs, regardless of whether the line contains modified data. It is + intended as a performance hint indicating that the data will no longer be used to avoid writing + back data to memory. This field is ignored for write messages. + Enabling this field is intended for scratch and spill/fill, where the memory is used only by a + single thread and thus does not need to be maintained after the thread completes. + Format = Enable +12:10 Reserved + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 246 + Bit Description + 9:8 + Block Size. Specifies the number of DWords to be read or written + + 10: 8 DWords + 11: 16 DWords + All other encodings are reserved. + + +3.9.7.2 Message Payload +DWord Bit Description +M1.7 31:0 + Offset 7. + Specifies the DWord offset of DWord 7 into the surface. + Format = U32 + Range = [0,3FFFFFFFh] +M1.6 31:0 Offset 6 +M1.5 31:0 Offset 5 +M1.4 31:0 Offset 4 +M1.3 31:0 Offset 3 +M1.2 31:0 Offset 2 +M1.1 31:0 Offset 1 +M1.0 31:0 Offset 0 +M2.7 31:0 + Offset 15. This message register is included only if the block size is 16 DWords. + +M2.6 31:0 Offset 14 +M2.5 31:0 Offset 13 +M2.4 31:0 Offset 12 +M2.3 31:0 Offset 11 +M2.2 31:0 Offset 10 +M2.1 31:0 Offset 9 +M2.0 31:0 Offset 8 + + +3.9.7.3 Additional Message Payload (Write) +For the write operation, either one or two additional registers (depending on the block size) of payload +contain the data to be written. +The Offsetn referred to below is the Global Offset added to the corresponding Offset n and is in units of +DWords . The DWord array index is also in units of DWords. +DWord Bit Description +M3.7 31:0 DWord[Offset7] +M3.6 31:0 DWord[Offset6] +M3.5 31:0 DWord[Offset5] +M3.4 31:0 DWord[Offset4] +M3.3 31:0 DWord[Offset3] +M3.2 31:0 DWord[Offset2] +M3.1 31:0 DWord[Offset1] +M3.0 31:0 DWord[Offset0] + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 247 + DWord Bit Description +M4.7 31:0 + DWord[Offset15]. This message register is included only if the block size is 16 DWords + +M4.6 31:0 DWord[Offset14] +M4.5 31:0 DWord[Offset13] +M4.4 31:0 DWord[Offset12] +M4.3 31:0 DWord[Offset11] +M4.2 31:0 DWord[Offset10] +M4.1 31:0 DWord[Offset9] +M4.0 31:0 DWord[Offset8] + + +3.9.7.4 Writeback Message (Read) +For the read operation, the writeback message consists of either one or two registers depending on the +block size. +The DWord array index is also in units of DWords. +DWord Bit Description +W0.7 31:0 DWord[Offset7] +W0.6 31:0 DWord[Offset6] +W0.5 31:0 DWord[Offset5] +W0.4 31:0 DWord[Offset4] +W0.3 31:0 DWord[Offset3] +W0.2 31:0 DWord[Offset2] +W0.1 31:0 DWord[Offset1] +W0.0 31:0 DWord[Offset0] +W1.7 31:0 + DWord[Offset15]. This writeback message register is included only if the block size is 16 + DWords. +W1.6 31:0 DWord[Offset14] +W1.5 31:0 DWord[Offset13] +W1.4 31:0 DWord[Offset12] +W1.3 31:0 DWord[Offset11] +W1.2 31:0 DWord[Offset10] +W1.1 31:0 DWord[Offset9] +W1.0 31:0 DWord[Offset8] + + +3.9.8 Byte Scattered Read/Write +These messages are supported on only. +These messages take a set of offsets, and read or write 8 or 16 scattered and possibly misaligned bytes, +words, or dwords starting at each offset. The Global Offset from the message header is added to each of +the specific offsets. +Restrictions: +The only surface type allowed is SURFTYPE_BUFFER. +The surface format is ignored, data is returned from the buffer to the GRF without format conversion. +The surface pitch is ignored, the surface is treated as a 1-dimensional surface. An element size (pitch) of 4 bytes is +used to determine the size of the buffer for out-of-bounds checking if using the surface state model. +The surface cannot be tiled + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 248 + The surface base address must be DWord aligned +The stateless model is not supported. +Applications: +Byte aligned buffer accesses in compute shaders +Execution Mask. Depending on the block size, either the low 8 bits or all 16 bits of the execution mask +are used to determine which slots are read into the destination GRF register (for read), or which slots are +written to the surface (for write). +Out-of-Bounds Accesses. Reads to areas outside of the surface return 0. Writes to areas outside of the +surface are dropped and will not modify memory contents. +Programming Restrictions: Writes to overlapping addresses will have undefined write ordering. + +3.9.8.1 Message Descriptor + Bit Description +13:12 Ignored +11:10 + Data Size. Specifies the data size for each slot. + + 0: 1 byte + 1: 2 bytes + 2: 4 bytes + 3: Reserved + 9 Ignored + 8 + SIMD Mode. Specifies the SIMD mode of the message (number of slots processed). + + 0: SIMD8 + 1: SIMD16 + + +3.9.8.2 Message Payload +DWord Bit Description +M1.7 31:0 + Offset 7. + Specifies the byte offset of DWord 7 into the surface. + Format = U32 + Range = [0,FFFFFFFFh] +M1.6 31:0 Offset 6 +M1.5 31:0 Offset 5 +M1.4 31:0 Offset 4 +M1.3 31:0 Offset 3 +M1.2 31:0 Offset 2 +M1.1 31:0 Offset 1 +M1.0 31:0 Offset 0 +M2.7 31:0 + Offset 15. This message register is included only if the SIMD Mode is SIMD16. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 249 + DWord Bit Description +M2.6 31:0 Offset 14 +M2.5 31:0 Offset 13 +M2.4 31:0 Offset 12 +M2.3 31:0 Offset 11 +M2.2 31:0 Offset 10 +M2.1 31:0 Offset 9 +M2.0 31:0 Offset 8 + + +3.9.8.3 Additional Message Payload (Write) +For the write operation, either one or two additional registers (depending on the block size) of payload +contain the data to be written. +The Offsetn referred to below is the Global Offset added to the corresponding Offset n and is in units of +bytes. The length of Data written depends on the Data Size and is right-justified within the 32-bit field. +The upper bits are ignored for 1 byte and 2 byte Data Size. +DWord Bit Description +M3.7 31:0 Data[Offset7] +M3.6 31:0 Data[Offset6] +M3.5 31:0 Data[Offset5] +M3.4 31:0 Data[Offset4] +M3.3 31:0 Data[Offset3] +M3.2 31:0 Data[Offset2] +M3.1 31:0 Data[Offset1] +M3.0 31:0 Data[Offset0] +M4.7 31:0 + Data[Offset15]. This message register is included only if the SIMD Mode is SIMD16. + +M4.6 31:0 Data[Offset14] +M4.5 31:0 Data[Offset13] +M4.4 31:0 Data[Offset12] +M4.3 31:0 Data[Offset11] +M4.2 31:0 Data[Offset10] +M4.1 31:0 Data[Offset9] +M4.0 31:0 Data[Offset8] + + +3.9.8.4 Writeback Message (Read) +For the read operation, the writeback message consists of either one or two registers depending on the +block size. +The Offsetn referred to below is the Global Offset added to the corresponding Offset n and is in units of +bytes. The length of Data written depends on the Data Size and is right-justified within the 32-bit field and +only the requeted bytes are written to the GRF. +DWord Bit Description +W0.7 31:0 Data[Offset7] +W0.6 31:0 Data[Offset6] +W0.5 31:0 Data[Offset5] +W0.4 31:0 Data[Offset4] +W0.3 31:0 Data[Offset3] +W0.2 31:0 Data[Offset2] +W0.1 31:0 Data[Offset1] + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 250 + DWord Bit Description +W0.0 31:0 Data[Offset0] +W1.7 31:0 + Data[Offset15]. This message register is included only if the SIMD Mode is SIMD16. + +W1.6 31:0 Data[Offset14] +W1.5 31:0 Data[Offset13] +W1.4 31:0 Data[Offset12] +W1.3 31:0 Data[Offset11] +W1.2 31:0 Data[Offset10] +W1.1 31:0 Data[Offset9] +W1.0 31:0 Data[Offset8] + + +3.9.9 Typed/Untyped Surface Read/Write and Typed/Untyped Atomic + Operation +Six data port messages (Typed Surface Read, Typed Surface Write, Typed Atomic Operation, Untyped +Surface Read, Untyped Surface Write, and Untyped Atomic Operation) allow direct read/write accesses to +surfaces. These messages support three major categories of surfaces: +Typed surfaces. These surfaces are of type SURFTYPE_1D, 2D, 3D, or BUFFER and have a supported +surface format other than RAW. Supported via the render cache data port. +Programming Restriction: Vertical stride & Vertical Offset fields of the surface state object is only +supported for 2D non-array surfaces. +Raw buffer (untyped). These surfaces are of type SURFTYPE_BUFFER and have a surface format of +RAW and a surface pitch of 1 byte. Supported via the data cache data port. All SLM accesses are in this +category. +Structured buffer (untyped). These surfaces are of type SURFTYPE_STRBUF and have a surface +format of RAW. Supported via the data cache data port. +A typed surface uses U, V, R, and LOD address parameters (number of parameters utilized depends on +surface type), and performs conversion of type to/from the selected surface format as follows: +Surface formats with UINT require the message data in U32 format +Surface formats with SINT require the message data in S32 format +All other surface formats require the message data in FLOAT32 format +The untyped surface categories, both of which use the RAW surface format, perform no type conversion. +A raw buffer uses just the U address parameter, which specifies the byte offset into the surface, which +must be a multiple of 4. A structured buffer uses the U address parameter as an array index and the V +address parameter as a byte offset into the array element (which also must be a multiple of 4). +For both raw and structured buffers, up to 4 dwords are accessed beginning at the byte address +determined. These 4 dwords correspond to the red, green, blue, and alpha channels in that order with red +mapping to the lowest order dword. The atomic operation messages will only access the first dword +(corresponding to the red channel for typed messages). +The atomic operation messages causes atomic read-modify-write operations on the “destination” location +addressed. In the table below, the new value of the destination (new_dst) is computed as indicated based +on the old value of the destination (old_dst) and up to two sources included in the message (src0 and +src1). Optionally, a value can be returned by the message (ret). + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 251 + The atomic operations guarantee that the read and the write are performed atomically, meaning that no +read or write to the same memory location from this thread or any other thread can occur between the +read and the write. +The following atomic operations are available, along with the specific operation performed for each and +the return value: +Atomic Operation new_dst ret +AOP_AND old_dst & src0 old_dst +AOP_OR old_dst | src0 old_dst +AOP_XOR old_dst ^ src0 old_dst +AOP_MOV src0 old_dst +AOP_INC old_dst + 1 old_dst +AOP_DEC old_dst – 1 old_dst +AOP_ADD old_dst + src0 old_dst +AOP_SUB old_dst – src0 old_dst +AOP_REVSUB src0 – old_dst old_dst +AOP_IMAX imax(old_dst, src0) old_dst +AOP_IMIN imin(old_dst, src0) old_dst +AOP_UMAX umax(old_dst, src0) old_dst +AOP_UMIN umin(old_dst, src0) old_dst +AOP_CMPWR (src0 == old_dst) ? src1 : old_dst old_dst +AOP_PREDEC old_dst – 1 new_dst +AOP_CMPWR8B (src08B == old_dst8B) ? src18B : old_dst8B old_dst8B + +Programming Note: src08B is 8 bytes, src18B is 8 Bytes and old_dst8B is 8 bytes in length. +Programming Note: AOP_CMPWR8B is not supported for SLM. +Programming Note: AOP_CMPWR8B addresses must be QWORD aligned. +Note: imax/imin assume operands are signed integers, umax/umin assume operands are unsigned +integers. All other operations treat all values as 32-bit unsigned integers. Add and subtract operations will +wrap without any special indication. +These messages are supported on only. +Restrictions: +For untyped messages, the Surface Format must be RAW and the Surface Type must be +SURFTYPE_BUFFER or SURFTYPE_STRBUF. +For typed messages, the Surface Type must be SURFTYPE_1D, 2D, 3D, or BUFFER. +Surface Format Name +R32_SINT +R32_UINT +R32_FLOAT + +The Surface Format for typed surface writes must be + Surface Format Name +R32G32B32A32_FLOAT +R32G32B32A32_SINT +R32G32B32A32_UINT +R16G16B16A16_UNORM +R16G16B16A16_SNORM +R16G16B16A16_SINT + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 252 + Surface Format Name +R16G16B16A16_UINT +R16G16B16A16_FLOAT +R32G32_FLOAT +R32G32_SINT +R32G32_UINT +B8G8R8A8_UNORM +R10G10B10A2_UNORM +R10G10B10A2_UINT +R8G8B8A8_UNORM +R8G8B8A8_SNORM +R8G8B8A8_SINT +R8G8B8A8_UINT +R16G16_UNORM +R16G16_SNORM +R16G16_SINT +R16G16_UINT +R16G16_FLOAT +B10G10R10A2_UNORM +R11G11B10_FLOAT +R32_SINT +R32_UINT +R32_FLOAT +B5G6R5_UNORM +B5G5R5A1_UNORM +B4G4R4A4_UNORM +R8G8_UNORM +R8G8_SNORM +R8G8_SINT +R8G8_UINT +R16_UNORM +R16_SNORM +R16_SINT +R16_UINT +R16_FLOAT +B5G5R5X1_UNORM +R8_UNORM +R8_SNORM +R8_SINT +R8_UINT +A8_UNORM + +The Surface Format for typed atomic operations must be R32_UINT or R32_SINT. +For untyped messages accessing SURFTYPE_STRBUF, the V address (byte offset) must be DWord +aligned (low 2 bits must be zero). +For untyped messages accessing SURFTYPE_BUFFER, the U address (byte offset) must be DWord +aligned (low 2 bits must be zero). +Typed messages only support SIMD8. +The stateless model support is limited to untyped messages. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 253 + Execution Mask: +SIMD16: The 16 bits of the execution mask are ANDed with the 16 bits of the Pixel/Sample Mask from +the message header and the resulting mask is used to determine which slots are read into the destination +GRF register (for read), or which slots are written to the surface (for write). If the header is not present, +only the execution mask is used. +SIMD8: The low 8 bits of the execution mask are ANDed with 8 bits of the Pixel/Sample Mask from the +message header. For the typed messages, the Slot Group in the message descriptor selects either the +low or high 8 bits. For the untyped messages, the low 8 bits are always selected. The resulting mask is +used to determine which slots are read into the destination GRF register (for read), or which slots are +written to the surface (for write). If the header is not present, only the low 8 bits of the execution mask are +used. +SIMD4x2: Each group of 4 bits within the low 8 bits of the execution mask are ORed together to create +two bits which are used to determine which slots are read into the destination GRF register. +Out–of–Bounds Accesses: Reads to areas outside of the surface return 0, except for the Typed Surface +Read message which returns 1 in the alpha channel and 0 in the other channels. Writes to areas outside +of the surface are dropped and will not modify memory contents. +Errata: The Typed Surface Read returns 0 in all channels for out-of-bounds accesses. +Programming Restrictions: Writes to overlapping addresses will have undefined write ordering. +The following table summarizes the SIMD Mode support for each message type: + Untyped Typed + Read Write Atomic Read Write Atomic +SIMD16 x x x +SIMD8 x x x x x x + +The following table indicates the hardware interpretation of each input parameter based on surface type. +Parameters with blank entries are ignored by hardware if delivered. +Surface Type“Surface Array” field in U Address V Address R Address LOD + SURFACE_STATE +SURFTYPE_1D disabled X pixel address LOD + enabled X pixel address array LOD + index +SURFTYPE_2D disabled X pixel address Y pixel LOD + address + enabled X pixel address Y pixel array LOD + address index +SURFTYPE_3D disabled X pixel address Y pixel Z pixel LOD + address address +SURFTYPE_BU disabled buffer index +FFER +SURFTYPE_ST disabled buffer index byte offset +RBUF + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 254 + 3.9.9.1 Typed Surface Read/Write Message Descriptor +Bit Description +13 + Slot Group + This field controls which 8 bits of Pixel/Sample Mask in the message header are ANDed with + the execution mask to determine which slots are accessed. This field is ignored if the header is + not present. + Format = U1 + 0: Use low 8 slots + 1: Use high 8 slots +12 Ignored +11 + Alpha Channel Mask + For the read message, indicates that alpha will be included in the writeback message. For the + write message, indicates that alpha is included in the message payload, and that alpha will be + written to the surface. + 0: Alpha channel included + 1: Alpha channel not included + Programming Notes: + At least one of the channels must be unmasked (the 4-bit channel mask cannot be 1111b). +10 Blue Channel Mask +9 Green Channel Mask +8 Red Channel Mask + + +3.9.9.2 Untyped Surface Read/Write Message Descriptor + Bit Description +13:12 + SIMD Mode + + Format = U2 + 0: SIMD4x2 (valid for read message only) (valid for read message only) , + 1: SIMD16 + 2: SIMD8 + 3: Reserved + 11 + Alpha Channel Mask + + For the read message, indicates that alpha will be included in the writeback message. For the + write message, indicates that alpha is included in the message payload, and that alpha will be + written to the surface. + 0: Alpha channel included + 1: Alpha channel not included + Programming Notes: + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 255 + Bit Description + For the Untyped Surface Write message, each channel mask cannot be 0 unless all of the lower + mask bits are also zero. This means that the only 4-bit channel mask values allowed are + 0000b, 1000b, 1100b, and 1110b. Other messages allow any combination of channel masks. + For the Untyped Surface Read message, at least one of the channels must be unmasked (the + 4-bit channel mask cannot be 1111b). + 10 Blue Channel Mask + 9 Green Channel Mask + 8 Red Channel Mask + + +3.9.9.3 Typed Atomic Operation Message Descriptor +Bit Description +13 + Return Data Control + Specifies whether return data is sent back to the thread. + Format = Enable +12 + Slot Group + This field controls which 8 bits of Pixel/Sample Mask in the message header are ANDed with + the execution mask to determine which slots are accessed. + Format = U1 + 0: Use low 8 slots + 1: Use high 8 slots +11:8 + Atomic Operation Type + Specifies the atomic operation to be performed. + 0000: Reserved + 0001: AOP_AND + 0010: AOP_OR + 0011: AOP_XOR + 0100: AOP_MOV + 0101: AOP_INC + 0110: AOP_DEC + 0111: AOP_ADD + 1000: AOP_SUB + 1001: AOP_REVSUB + 1010: AOP_IMAX + 1011: AOP_IMIN + 1100: AOP_UMAX + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 256 + Bit Description + 1101: AOP_UMIN + 1110: AOP_CMPWR + 1111: AOP_PREDEC + + +3.9.9.4 Typed Atomic Operation SIMD4x2 Message Descriptor +Bit Description +13 + Return Data Control + Specifies whether return data is sent back to the thread. + Format = Enable + 12 Reserved +11:8 + Atomic Operation Type + Specifies the atomic operation to be performed. + 0000: reserved + 0001: AOP_AND + 0010: AOP_OR + 0011: AOP_XOR + 0100: AOP_MOV + 0101: AOP_INC + 0110: AOP_DEC + 0111: AOP_ADD + 1000: AOP_SUB + 1001: AOP_REVSUB + 1010: AOP_IMAX + 1011: AOP_IMIN + 1100: AOP_UMAX + 1101: AOP_UMIN + 1110: AOP_CMPWR + 1111: AOP_PREDEC + + +3.9.9.5 Untyped Atomic Operation Message Descriptor +Bit Description +13 + Return Data Control + Specifies whether return data is sent back to the thread. + Format = Enable + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 257 + Bit Description +12 + SIMD Mode + Format = U1 + 0: SIMD16 + 1: SIMD8 +11:8 + Atomic Operation Type + Specifies the atomic operation to be performed. + 0000: 0000: AOP_CMPWR8B + 0001: AOP_AND + 0010: AOP_OR + 0011: AOP_XOR + 0100: AOP_MOV + 0101: AOP_INC + 0110: AOP_DEC + 0111: AOP_ADD + 1000: AOP_SUB + 1001: AOP_REVSUB + 1010: AOP_IMAX + 1011: AOP_IMIN + 1100: AOP_UMAX + 1101: AOP_UMIN + 1110: AOP_CMPWR + 1111: AOP_PREDEC + + +3.9.9.6 Untyped Atomic Operation SIMD4x2 Message Descriptor +Bit Description +13 + Return Data Control + Specifies whether return data is sent back to the thread. + Format = Enable + 12 Reserved +11:8 + Atomic Operation Type + Specifies the atomic operation to be performed. + 0000: AOP_CMPWR8B + 0001: AOP_AND + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 258 + Bit Description + 0010: AOP_OR + 0011: AOP_XOR + 0100: AOP_MOV + 0101: AOP_INC + 0110: AOP_DEC + 0111: AOP_ADD + 1000: AOP_SUB + 1001: AOP_REVSUB + 1010: AOP_IMAX + 1011: AOP_IMIN + 1100: AOP_UMAX + 1101: AOP_UMIN + 1110: AOP_CMPWR + 1111: AOP_PREDEC + + +3.9.9.7 Atomic Counter Operation Message Descriptor +Bit Description +13 + Return Data Control + Specifies whether return data is sent back to the thread. + Format = Enable +12 + SIMD Mode + Format: U1 + 0: SIM16 + 1: SIM8 (low 8 slots) +11:8 + Atomic Operation Type + Specifies the atomic operation to be performed. + 0000: Reserved + 0001: AOP_AND + 0010: AOP_OR + 0011: AOP_XOR + 0100: AOP_MOV + 0101: AOP_INC + 0110: AOP_DEC + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 259 + Bit Description + 0111: AOP_ADD + 1000: AOP_SUB + 1001: AOP_REVSUB + 1010: AOP_IMAX + 1011: AOP_IMIN + 1100: AOP_UMAX + 1101: AOP_UMIN + 1110: AOP_CMPWR + 1111: AOP_PREDEC + +For Append Counter Operations there is no address payload as the address is provided by the append +counter field in the surface state. The write data payloads are the same as untyped atomic. The write +back are the same as untyped atomic. +When accessing a surface with the Append Counter Operation, if the Append Counter enable field of the +surface state is not 1, it the access will be treated as out of bounds, w/ the writes being ignored and the +reads returning 0. + +3.9.9.8 Atomic Counter Operation SIMD4x2 Message Descriptor +Bit Description +13 + Return Data Control + Specifies whether return data is sent back to the thread. + Format = Enable + 12 Reserved +11:8 + Atomic Operation Type + Specifies the atomic operation to be performed. + 0000: Reserved + 0001: AOP_AND + 0010: AOP_OR + 0011: AOP_XOR + 0100: AOP_MOV + 0101: AOP_INC + 0110: AOP_DEC + 0111: AOP_ADD + 1000: AOP_SUB + 1001: AOP_REVSUB + 1010: AOP_IMAX + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 260 + Bit Description + 1011: AOP_IMIN + 1100: AOP_UMAX + 1101: AOP_UMIN + 1110: AOP_CMPWR + 1111: AOP_PREDEC + +For Append Counter Operations there is no address payload as the address is provided by the append +counter field in the surface state. The write data payloads are the same as untyped atomic 4x2. The write +back are the same as untyped atomic 4x2. +When accessing a surface with the Append Counter Operation, if the Append Counter enable field of the +surface state is not 1, it the access will be treated as out of bounds, w/ the writes being ignored and the +reads returning 0. + +3.9.9.9 Message Header +The message header for the untyped messages only needs to be delivered for pixel shader threads, +where the execution mask may indicate pixels/samples that are enabled only due to derivative (LOD) +calculations, but the corresponding slot on the surface must not be accessed. Typed messages (which go +to render cache data port) must include the header. +DWord Bit Description +M0.7 31:16 Ignored + 15:0 + Pixel/Sample Mask. This field contains the 16-bit pixel/sample mask to be used for + SIMD16 and SIMD8 messages. All 16 bits are used for SIMD16 messages. For typed + SIMD8 messages, Slot Group selects with 8 bits of this field are used. For untyped + SIMD8 messages, the low 8 bits of this field are used. + If the header is not delivered, this field defaults to all ones. The field is ignored for + SIMD4x2 messages. +M0.6 31:0 Ignored +M0.5 31:0 + Format = GeneralStateOffset[31:10] +M0.4 31:0 Ignored (reserved for hardware delivery of binding table pointer) +M0.3 31:0 Ignored +M0.2 31:0 Ignored +M0.1 31:0 Ignored +M0.0 31:0 Ignored + + +3.9.9.10 Message Payload +The message payload consists of the following: + +  For the read messages, only an address payload is delivered +  For the write messages, an address payload is followed by the write data payload +  For the atomic operation messages, an address payload is followed by the source payload +  For SIMD16 and SIMD8 messages, the message length is used to determine how may address + parameters are included in the message. The number of message registers in the write data payload + is determined by the number of channel mask bits that are enabled, and the number of message + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 261 + registers in the source payload is determined by the atomic operation operation. Thus, one or neither + of these two values (depending on the message type), plus one for the header, can be subtracted + from the message length to determine the number of message registers in the address payload, + from which the number of address parameters can be determined. + +3.9.9.10.1 SIMD16 Address Payload +The payload of a SIMD16 message provides address parameters to process 16 slots. The possible +address parameters are U and V (since SIMD16 is only supported with untyped messages). The number +of parameters required depends on the surface type being accessed. Each parameter takes two message +registers. Each parameter always takes a consistent position in the input payload. The length field can be +used to send a shorter message, but intermediate parameters cannot be skipped as there is no way to +signal this. + + +DWord Bit Description +M1.7 31:0 + Slot 7 U Address + Specifies the U Address for slot 7. + Format = U32 +M1.6 31:0 Slot 6 U Address +M1.5 31:0 Slot 5 U Address +M1.4 31:0 Slot 4 U Address +M1.3 31:0 Slot 3 U Address +M1.2 31:0 Slot 2 U Address +M1.1 31:0 Slot 1 U Address +M1.0 31:0 Slot 0 U Address +M2.7 31:0 Slot 15 U Address +M2.6 31:0 Slot 14 U Address +M2.5 31:0 Slot 13 U Address +M2.4 31:0 Slot 12 U Address +M2.3 31:0 Slot 11 U Address +M2.2 31:0 Slot 10 U Address +M2.1 31:0 Slot 9 U Address +M2.0 31:0 Slot 8 U Address +M3 Slots 7:0 V Address +M4 Slots 15:8 V Address + + +3.9.9.10.2 SIMD16 Source Payload (Atomic Operation message only) +The source payload follows the address payload for atomic operation messages. Depending on the +atomic operation, zero, one, or two sources are required. If the source is not required, it must not be +included. Message registers given here could be a lower number if some of the address parameters are +not included. +The following atomic operations require no sources, thus the source payload is not delivered: AOP_INC, +AOP_DEC, AOP_PREDEC +The following atomic operations require both Source0 and Source1: AOP_CMPWR +All of the remaining atomic operations require Source0 only. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 262 + DWord Bit Description +M5.7 31:0 + Slot 7 Source0 + Specifies Source0 for slot 7. + Format = S31 for AOP_IMAX and AOP_IMIN, U32 for all other operations +M5.6 31:0 Slot 6 Source0 +M5.5 31:0 Slot 5 Source0 +M5.4 31:0 Slot 4 Source0 +M5.3 31:0 Slot 3 Source0 +M5.2 31:0 Slot 2 Source0 +M5.1 31:0 Slot 1 Source0 +M5.0 31:0 Slot 0 Source0 +M6.7 31:0 Slot 15 Source0 +M6.6 31:0 Slot 14 Source0 +M6.5 31:0 Slot 13 Source0 +M6.4 31:0 Slot 12 Source0 +M6.3 31:0 Slot 11 Source0 +M6.2 31:0 Slot 10 Source0 +M6.1 31:0 Slot 9 Source0 +M6.0 31:0 Slot 8 Source0 +M7 Slots 7:0 Source1 +M8 Slots 15:8 Source1 + + +3.9.9.10.3 SIMD16 Source Payload (AOP_CMPWR8B only) +DWord Bit Description +M5.7 31:0 + Slot 7 Source0[31:0] + Specifies Source0[31:0] for slot 7. + Format = U32 +M5.6 31:0 Slot 6 Source0[31:0] +M5.5 31:0 Slot 5 Source0[31:0] +M5.4 31:0 Slot 4 Source0[31:0] +M5.3 31:0 Slot 3 Source0[31:0] +M5.2 31:0 Slot 2 Source0[31:0] +M5.1 31:0 Slot 1 Source0[31:0] +M5.0 31:0 Slot 0 Source0[31:0] +M6.7 31:0 Slot 15 Source0[31:0] +M6.6 31:0 Slot 14 Source0[31:0] +M6.5 31:0 Slot 13 Source0[31:0] +M6.4 31:0 Slot 12 Source0[31:0] +M6.3 31:0 Slot 11 Source0[31:0] +M6.2 31:0 Slot 10 Source0[31:0] +M6.1 31:0 Slot 9 Source0[31:0] +M6.0 31:0 Slot 8 Source0[31:0] +M7 Slots 7:0 Source0[63:32] +M8 Slots 15:8 Source0[63:32] +M9 Slots 7:0 Source1[31:0] +M10 Slots 15:8 Source1[31:0] +M11 Slots 7:0 Source1[63:32] + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 263 + DWord Bit Description +M12 Slots 15:8 Source1[63:32] + + +3.9.9.10.4 SIMD16 Write Data Payload (Write message only) +The write data payload follows the address payload for write messages. Actual position within the +message may vary if some of the parameters are not included or if some of the channel mask bits are +asserted. Any parameter or write channel not included in the payload is skipped, with message phases +below it being renumbered to take up the vacated space. +DWord Bit Description +M5.7 31:0 + Slot 7 Red + Specifies the value of the red channel to be written for slot 7. + Format = 32 bits raw data. +M5.6 31:0 Slot 6 Red +M5.5 31:0 Slot 5 Red +M5.4 31:0 Slot 4 Red +M5.3 31:0 Slot 3 Red +M5.2 31:0 Slot 2 Red +M5.1 31:0 Slot 1 Red +M5.0 31:0 Slot 0 Red +M6.7 31:0 Slot 15 Red +M6.6 31:0 Slot 14 Red +M6.5 31:0 Slot 13 Red +M6.4 31:0 Slot 12 Red +M6.3 31:0 Slot 11 Red +M6.2 31:0 Slot 10 Red +M6.1 31:0 Slot 9 Red +M6.0 31:0 Slot 8 Red +M7 Slots 7:0 Green +M8 Slots 15:8 Green +M9 Slots 7:0 Blue +M10 Slots 15:8 Blue +M11 Slots 7:0 Alpha +M12 Slots 15:8 Alpha + + +3.9.9.10.5 SIMD8 Address Payload +The payload of a SIMD8 message provides address parameters to process 8 slots. The possible address +parameters are U, V, R, and LOD. The number of parameters required depends on the surface type +being accessed. Each parameter takes one message register. Each parameter always takes a consistent +position in the input payload. The length field can be used to send a shorter message, but intermediate +parameters cannot be skipped as there is no way to signal this. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 264 + DWord Bit Description +M1.7 31:0 + Slot 7 U Address + Specifies the U Address for slot 7. + Format = U32 +M1.6 31:0 Slot 6 U Address +M1.5 31:0 Slot 5 U Address +M1.4 31:0 Slot 4 U Address +M1.3 31:0 Slot 3 U Address +M1.2 31:0 Slot 2 U Address +M1.1 31:0 Slot 1 U Address +M1.0 31:0 Slot 0 U Address +M2 Slots 7:0 V Address +M3 + Slots 7:0 R Address + Programming Notes: + This register can only be delivered for the Typed message types. +M4 + Slots 7:0 LOD + Programming Notes: + This register can only be delivered for the Typed message types. + + +Errata: Overlapping addresses (identical U/V/R/LOD ) in the same simd8 message is not supported for typed (non- +atomic) writes to tiled surfaces. + + +3.9.9.10.6 SIMD8 Source Payload (Atomic Operation message only) +The source payload follows the address payload for atomic operation messages. Depending on the +atomic operation, zero, one, or two sources are required. If the source is not required, it must not be +included. Message registers given here could be a lower number if some of the address parameters are +not included. +The following atomic operations require no sources, thus the source payload is not delivered: AOP_INC, +AOP_DEC, AOP_PREDEC +The following atomic operations require both Source0 and Source1: AOP_CMPWR +All of the remaining atomic operations require Source0 only. +DWord Bit Description +M5.7 31:0 + Slot 7 Source0 + Specifies Source0 for slot 7. + Format = S31 for AOP_IMAX and AOP_IMIN, U32 for all other operations +M5.6 31:0 Slot 6 Source0 +M5.5 31:0 Slot 5 Source0 +M5.4 31:0 Slot 4 Source0 +M5.3 31:0 Slot 3 Source0 +M5.2 31:0 Slot 2 Source0 + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 265 + DWord Bit Description +M5.1 31:0 Slot 1 Source0 +M5.0 31:0 Slot 0 Source0 +M6 Slots 7:0 Source1 + + +3.9.9.10.7 SIMD8 Write Data Payload (Write message only) +The write data payload follows the address payload for write messages. Actual position within the +message may vary if some of the parameters are not included or if some of the channel mask bits are +asserted. Any parameter or write channel not included in the payload is skipped, with message phases +below it being renumbered to take up the vacated space. +DWord Bit Description +M5.7 31:0 + Slot 7 Red + Specifies the value of the red channel to be written for slot 7. + For Untyped messages: + Format = 32 bits raw data. + For Typed messages: + Format = IEEE Float, S31, or U32 depending on the Surface Format of the surface being + accessed. SINT formats use S31, UINT formats use U32, and all other formats use + Float. +M5.6 31:0 Slot 6 Red +M5.5 31:0 Slot 5 Red +M5.4 31:0 Slot 4 Red +M5.3 31:0 Slot 3 Red +M5.2 31:0 Slot 2 Red +M5.1 31:0 Slot 1 Red +M5.0 31:0 Slot 0 Red +M6 Slots 7:0 Green +M7 Slots 7:0 Blue +M8 Slots 7:0 Alpha + + +3.9.9.10.8 SIMD8 Write Data Payload (Tile W Write message only) +The write data payload follows the address payload for write messages. Actual position within the +message may vary if some of the parameters are not included. +DWord Bit Description +M5.7 31:8 Ignored + 7:0 + Slot 7 Red + Specifies the value of the red channel to be written for slot 7. + For Typed messages: + Format = U8 +M5.6 31:8 Ignored + 7:0 Slot 6 Red +M5.5 31:8 Ignored + 7:0 Slot 5 Red + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 266 + DWord Bit Description +M5.4 31:8 Ignored + 7:0 Slot 4 Red +M5.3 31:8 Ignored + 7:0 Slot 3 Red +M5.2 31:8 Ignored + 7:0 Slot 2 Red +M5.1 31:8 Ignored + 7:0 Slot 1 Red +M5.0 31:8 Ignored + 7:0 Slot 0 Red + + +3.9.9.10.9 SIMD4x2 Address Payload +The payload of a SIMD4x2 message provides address parameters to process 2 slots. +DWord Bit Description +M1.7 31:0 + Programming Notes: + This register can only be delivered for the Typed message types. +M1.6 31:0 + Programming Notes: + This register can only be delivered for the Typed message types. +M1.5 31:0 + Slot 1 V Address + Format = U32 +M1.4 31:0 + Slot 1 U Address + Format = U32 +M1.3 31:0 +M1.2 31:0 +M1.1 31:0 Slot 0 V Address +M1.0 31:0 Slot 0 U Address + + +3.9.9.10.10 SIMD4x2 Source Payload (Atomic Operation message only) +The source payload follows the address payload for atomic operation messages. Depending on the +atomic operation, zero, one, or two sources are required. If the source is not required, it must not be +included. Message registers given here could be a lower number if some of the address parameters are +not included. +The following atomic operations require no sources, thus the source payload is not delivered: AOP_INC, +AOP_DEC, AOP_PREDEC +The following atomic operations require both Source0 and Source1: AOP_CMPWR +All of the remaining atomic operations require Source0 only. +DWord Bit Description +M2.7 31:0 Ignored +M2.6 31:0 Ignored +M2.5 31:0 + Slot 1 Source1 + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 267 + DWord Bit Description + Specifies Source1 for slot 1. + Format = S31 for AOP_IMAX and AOP_IMIN, U32 for all other operations +M2.4 31:0 Slot 1 Source0 +M2.3 31:0 Ignored +M2.2 31:0 Ignored +M2.1 31:0 Slot 0 Source1 +M2.0 31:0 Slot 0 Source0 + + +3.9.9.10.11 SIMD4x2 Source Payload ((AOP_CMPWR8B only) +DWord Bit Description +M2.7 31:0 Slot 1 Source1 [63:32] +M2.6 31:0 Slot 1 Source1 [31:0] +M2.5 31:0 Slot 1 Source0 [63:32] +M2.4 31:0 Slot 1 Source0 [31:0] +M2.3 31:0 Slot 0 Source1 [63:32] +M2.2 31:0 Slot 0 Source1 [31:0] +M2.1 31:0 Slot 0 Source0 [63:32] +M2.0 31:0 Slot 0 Source0 [31:0] + + +3.9.9.10.12 SIMD4x2 Write Data Payload (Write message only) +The write data payload follows the address payload for write messages. +DWord Bit Description +M2.7 31:0 + Slot 1 Alpha + Specifies the value of the red channel to be written for slot 7. + For Untyped messages: + Format = 32 bits raw data. + For Typed messages: + Format = IEEE Float, S31, or U32 depending on the Surface Format of the surface being + accessed. SINT formats use S31, UINT formats use U32, and all other formats use + Float. +M2.6 31:0 Slot 1 Blue +M2.5 31:0 Slot 1 Green +M2.4 31:0 Slot 1 Red +M2.3 31:0 Slot 0 Alpha +M2.2 31:0 Slot 0 Blue +M2.1 31:0 Slot 0 Green +M2.0 31:0 Slot 0 Red + + +3.9.9.11 Writeback Message + +3.9.9.11.1 SIMD16 Read +A SIMD16 writeback message consists of up to 8 destination registers. Which registers are returned is +determined by the channel mask in the message descriptor. Each asserted channel mask results in the + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 268 + destination register of the corresponding channel being skipped in the writeback message, and all +channels with higher numbered registers being dropped down to fill in the space occupied by the masked +channel. For example, if only red and alpha are enabled, red is sent to regid+0 and regid+1, and alpha to +regid+2 and regid+3. The slots written within each destination register is determined by the execution +mask on the “send” instruction. +DWord Bit Description +W0.7 31:0 + Slot 7 Red: Specifies the value of the red channel for slot 7. + + Format = 32 bits raw data. +W0.6 31:0 Slot 6 Red +W0.5 31:0 Slot 5 Red +W0.4 31:0 Slot 4 Red +W0.3 31:0 Slot 3 Red +W0.2 31:0 Slot 2 Red +W0.1 31:0 Slot 1 Red +W0.0 31:0 Slot 0 Red +W1.7 31:0 Slot 15 Red +W1.6 31:0 Slot 14 Red +W1.5 31:0 Slot 13 Red +W1.4 31:0 Slot 12 Red +W1.3 31:0 Slot 11 Red +W1.2 31:0 Slot 10 Red +W1.1 31:0 Slot 9 Red +W1.0 31:0 Slot 8 Red +W2 Slots 7:0 Green +W3 Slots 15:8 Green +W4 Slots 7:0 Blue +W5 Slots 15:8 Blue +W6 Slots 7:0 Alpha +W7 Slots 15:8 Alpha + + +3.9.9.11.2 SIMD8 Read +A SIMD8 writeback message consists of up to 4 destination registers. Which registers are returned is +determined by the channel mask in the message descriptor. Each asserted channel mask results in the +destination register of the corresponding channel being skipped in the writeback message, and all +channels with higher numbered registers being dropped down to fill in the space occupied by the masked +channel. For example, if only red and alpha are enabled, red is sent to regid+0, and alpha to regid+1. +The slots written within each destination register is determined by the execution mask on the “send” +instruction. +DWord Bit Description +W0.7 31:0 + Slot 7 Red: Specifies the value of the red channel for slot 7. + + For Untyped messages: + Format = 32 bits raw data. + For Typed messages: + Format = IEEE Float, S31, or U32 depending on the Surface Format of the surface being + accessed. SINT formats use S31, UINT formats use U32, and all other formats use + Float. + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 269 + DWord Bit Description +W0.6 31:0 Slot 6 Red +W0.5 31:0 Slot 5 Red +W0.4 31:0 Slot 4 Red +W0.3 31:0 Slot 3 Red +W0.2 31:0 Slot 2 Red +W0.1 31:0 Slot 1 Red +W0.0 31:0 Slot 0 Red +W1 Slots 7:0 Green +W2 Slots 7:0 Blue +W3 Slots 7:0 Alpha + + +3.9.9.11.3 SIMD8 Read (Tile W) +The slots written within each destination register is determined by the execution mask on the “send” +instruction. +DWord Bit Description +M5.7 31:8 Reserved (0) + 7:0 + Slot 7 Red + Specifies the value of the red channel to be written for slot 7. + For Typed messages: + Format = U8 +M5.6 31:8 Reserved (0) + 7:0 Slot 6 Red +M5.5 31:8 Reserved (0) + 7:0 Slot 5 Red +M5.4 31:8 Reserved (0) + 7:0 Slot 4 Red +M5.3 31:8 Reserved (0) + 7:0 Slot 3 Red +M5.2 31:8 Reserved (0) + 7:0 Slot 2 Red +M5.1 31:8 Reserved (0) + 7:0 Slot 1 Red +M5.0 31:8 Reserved (0) + 7:0 Slot 0 Red + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 270 + 3.9.9.11.4 SIMD4x2 Read +A SIMD4x2 writeback message always consists of a single message register containing all four color +channels of each of the two slots. The channel mask bits as well as the execution mask on the “send” +instruction are used to determine which of the channels in the destination register are overwritten. If any +of the four execution mask bits for a slot is asserted, that slot is considered to be active. The active +channels in the channel mask will be written in the destination register for that slot. If the slot is inactive +(all four execution mask bits deasserted), none of the channels for that slot will be written in the +destination register. +DWord Bit Description +W0.7 31:0 + Slot 1 Alpha: Specifies the value of the pixel’s alpha channel. + + Format = 32 bits raw data. +W0.6 31:0 Slot 1 Blue +W0.5 31:0 Slot 1 Green +W0.4 31:0 Slot 1 Red +W0.3 31:0 Slot 0 Alpha +W0.2 31:0 Slot 0 Blue +W0.1 31:0 Slot 0 Green +W0.0 31:0 Slot 0 Red + + +3.9.9.11.5 SIMD16 Atomic Operation +A writeback message is only returned for an Atomic Operation message if the Send Return Data field in +the message descriptor is enabled. The execution mask on the “send” instruction indicates which +channels in the destination registers are overwritten. +DWord Bit Description +W0.7 31:0 + Slot 7 Return Data: Specifies the value of the return data for slot 7. + + Format = U32 +W0.6 31:0 Slot 6 Return Data +W0.5 31:0 Slot 5 Return Data +W0.4 31:0 Slot 4 Return Data +W0.3 31:0 Slot 3 Return Data +W0.2 31:0 Slot 2 Return Data +W0.1 31:0 Slot 1 Return Data +W0.0 31:0 Slot 0 Return Data +W1.7 31:0 Slot 15 Return Data +W1.6 31:0 Slot 14 Return Data +W1.5 31:0 Slot 13 Return Data +W1.4 31:0 Slot 12 Return Data +W1.3 31:0 Slot 11 Return Data +W1.2 31:0 Slot 10 Return Data +W1.1 31:0 Slot 9 Return Data +W1.0 31:0 Slot 8 Return Data + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 271 + 3.9.9.11.6 SIMD16 Atomic Operation (AOP_CMPWR8B only) +A writeback message is only returned for an Atomic Operation AOP_CMPWR8B message if the Send +Return Data field in the message descriptor is enabled. The execution mask on the “send” instruction +indicates which channels in the destination registers are overwritten. +DWord Bit Description +W0.7 31:0 + Slot 7 Return Data[31:0]: Specifies the value of the return data for slot 7. + + Format = U32 +W0.6 31:0 Slot 6 Return Data[31:0] +W0.5 31:0 Slot 5 Return Data[31:0] +W0.4 31:0 Slot 4 Return Data[31:0] +W0.3 31:0 Slot 3 Return Data[31:0] +W0.2 31:0 Slot 2 Return Data[31:0] +W0.1 31:0 Slot 1 Return Data[31:0] +W0.0 31:0 Slot 0 Return Data[31:0] +W1.7 31:0 Slot 15 Return Data[31:0] +W1.6 31:0 Slot 14 Return Data[31:0] +W1.5 31:0 Slot 13 Return Data[31:0] +W1.4 31:0 Slot 12 Return Data[31:0] +W1.3 31:0 Slot 11 Return Data[31:0] +W1.2 31:0 Slot 10 Return Data[31:0] +W1.1 31:0 Slot 9 Return Data[31:0] +W1.0 31:0 Slot 8 Return Data[31:0] +W2 Slot 7:0 Return Data[63:32] +W3 Slot 15:8 Return Data[63:32] + + +3.9.9.11.7 SIMD8 Atomic Operation +A writeback message is only returned for an Atomic Operation message if the Send Return Data field in +the message descriptor is enabled. The execution mask on the “send” instruction indicates which +channels in the destination registers are overwritten. +DWord Bit Description +W0.7 31:0 + Slot 7 Return Data: Specifies the value of the return data for slot 7. + Format = U32 +W0.6 31:0 Slot 6 Return Data +W0.5 31:0 Slot 5 Return Data +W0.4 31:0 Slot 4 Return Data +W0.3 31:0 Slot 3 Return Data +W0.2 31:0 Slot 2 Return Data +W0.1 31:0 Slot 1 Return Data +W0.0 31:0 Slot 0 Return Data + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 272 + 3.9.9.11.8 SIMD8 Atomic Operation (AOP_CMPWR8B only) +A writeback message is only returned for an Atomic Operation AOP_CMPWR8B message if the Send +Return Data field in the message descriptor is enabled. The execution mask on the “send” instruction +indicates which channels in the destination registers are overwritten. +DWord Bit Description +W0.7 31:0 + Slot 7 Return Data[31:0]: Specifies the value of the return data for slot 7. + + Format = U32 +W0.6 31:0 Slot 6 Return Data[31:0] +W0.5 31:0 Slot 5 Return Data[31:0] +W0.4 31:0 Slot 4 Return Data[31:0] +W0.3 31:0 Slot 3 Return Data[31:0] +W0.2 31:0 Slot 2 Return Data[31:0] +W0.1 31:0 Slot 1 Return Data[31:0] +W0.0 31:0 Slot 0 Return Data[31:0] +W1.7 31:0 Slot 7 Return Data[63:32] +W1.6 31:0 Slot 6 Return Data[63:32] +W1.5 31:0 Slot 5 Return Data[63:32] +W1.4 31:0 Slot 4 Return Data[63:32] +W1.3 31:0 Slot 3 Return Data[63:32] +W1.2 31:0 Slot 2 Return Data[63:32] +W1.1 31:0 Slot 1 Return Data[63:32] +W1.0 31:0 Slot 0 Return Data[63:32] + + +3.9.9.11.9 SIMD4x2 Atomic Operation +A writeback message is only returned for an Atomic Operation message if the Send Return Data field in +the message descriptor is enabled. The execution mask on the “send” instruction indicates which +channels in the destination registers are overwritten. +DWord Bit Description +W0.7 31:0 reserved – not written to GRF +W0.6 31:0 reserved – not written to GRF +W0.5 31:0 reserved – not written to GRF +W0.4 31:0 + Slot 1 Return Data: Specifies the value of the return data for slot 1. + + Format = U32 +W0.3 31:0 reserved – not written to GRF +W0.2 31:0 reserved – not written to GRF +W0.1 31:0 reserved – not written to GRF +W0.0 31:0 Slot 0 Return Data + + +3.9.9.11.10 SIMD4x2 Atomic Operation (AOP_CMPWR8B only) +A writeback message is only returned for an Atomic Operation AOP_CMPWR8B message if the Send +Return Data field in the message descriptor is enabled. The execution mask on the “send” instruction +indicates which channels in the destination registers are overwritten. +DWord Bit Description +W0.7 31:0 reserved – not written to GRF +W0.6 31:0 reserved – not written to GRF + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 273 + DWord Bit Description +W0.5 31:0 Slot 1 Return Data: [63:32] +W0.4 31:0 Slot 1 Return Data: [31:0] +W0.3 31:0 reserved – not written to GRF +W0.2 31:0 reserved – not written to GRF +W0.1 31:0 Slot 0 Return Data: [63:32] +W0.0 31:0 Slot 0 Return Data[31:0] + + +3.9.10 Scratch Block Read/Write +This message performs a read or write operation of between 1 and 4 simd-8 registers to a Hword aligned +offset to scratch memory. The Hword offset into the scratch memory is provided in the message +descriptor, allowing a single instruction read|write block operation in a single source instruction. 12b are +provided for the Hword offset, allowing addressing of 4K Hword locations (128KB). +Two modes of channel-enable interpretation are provided: Dword, which support a simd-8 or simd-16 +dword channel-serial view of a register, and Oword, which supports a simd-4x2 view of a register. For +operations under conditions of simd-32 processing, two messages should be used, with one of them +indicating ‘H2’ to select the upper 16b of execution mask. +This message type can only be used with stateless model memory access. Thus binding table entry 0xFF +is hard-coded into the execution of this message. +Applications: +scratch space reads/writes for register spill/fill operations. +Execution Mask. The low 8 bits of the execution mask are used to enable the 8 channels in the first and +third GRF registers returned (W0, W2) for read, or the first and third write registers sent (M1, M3). The +high 8 bits are used similarly for the second and fourth (W1, W3 or M2, M4). +For Dword mode, the execution mask delivered with the message dictates dword-based control of read or +write operations. For Oword mode, any one or more asserted bits within the Oword’s corresponding +execution mask nibble causes read or write operations to occur across all four dwords of the Oword +regardless of the setting of any particular dword’s bit. +Out-of-Bounds Accesses. Reads to areas outside of the surface return 0. Writes to areas outside of the +surface are dropped and will not modify memory contents. + +3.9.10.1 Message Descriptor +Bits Description + 17 Operation Type: 0 = Read, 1 = write + 16 + Channel Mode: + 0: Oword – Channel enables in effect at the time of ‘send’ are interpreted such if one or more + are enabled, the read or write operation occurs on all four dwords. + 1: Dword – Channel enables in effect at the time of the ‘send’ are used as dword enables, + causing the read or write operation to occur only on the dwords whose corresponding channel + enable is set.. + 15 + Invalidate after read – Indicates the cache line should invalidated after the read. + 1: Invalidate cache line + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 274 + Bits Description + 0: no Invalidate + 14 Reserved - MBZ +13:12 + Block Size – indicates the number of simd-8 registers to be read|written. + + 11: 4 registers + 10: + 01: 2 registers + 00: 1 register +11:0 + Offset – A 12b Hword offset into the memory Immediate Memory buffer as specified by + binding table 0xFF. + + +3.9.10.2 Message Header +DWord Bit Description +M0.7 31:16 Ignored + 15:0 Ignored +M0.6 31:0 Ignored +M0.5 31:0 + Immediate Buffer Base Address. Specifies the surface base address for messages in + which the Binding Table Index is 255 (stateless model), otherwise this field is ignored. + This pointer is relative to the General State Base Address. + Format = GeneralStateOffset[31:10] +M0.4 31:0 Ignored +M0.3 31:0 Ignored +M0.2 31:0 Ignored +M0.1 31:0 Ignored +M0.0 31:0 Ignored + + +3.9.10.3 Message Payload (Write) +The listing below illustrates the write payload for a message of block size = 4; +DWord Bit Description +M1.7:0 255:0 HWord[Offset] +M2.7:0 255:0 HWord[Offset+1] +M3.7:0 255:0 HWord[Offset+2] +M3.7:0 255:0 HWord[Offset+3] + + +3.9.10.4 Message Payload (Read) +Only required a message header. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 275 + 3.9.10.5 Writeback Message (Read) +The table below illustrates an example where 4 Hwords are read through a scratch block read. +DWord Bit Description +W0.7:0 255:0 HWord[Offset] +W1.7:0 255:0 HWord[Offset+1] +W2.7:0 255:0 HWord[Offset+2] +W3.7:0 255:0 HWord[Offset+3] + + +3.9.11 Render Target Write +This message takes four subspans of pixels for write to a render target. Depending on parameters +contained in the message and state, it may also perform a depth and stencil buffer write and/or a render +target read for a color blend operation. Additional operations enabled in the Color Calculator state will +also be initiated as a result of issuing this message (depth test, alpha test, logic ops, etc.). This message +is intended only for use by pixel shader kernels for writing results to render targets. +Restrictions: +All surface types, except SURFTYPE_STRBUF, are allowed. +For SURFTYPE_BUFFER and SURFTYPE_1D surfaces, only the X coordinate is used to index into the +surface. The Y coordinate must be zero. +For SURFTYPE_1D, 2D, 3D, and CUBE surfaces, a Render Target Array Index is included in the input +message to provide an additional coordinate. The Render Target Array Index must be zero for +SURFTYPE_BUFFER. +The surface format is restricted to the set supported as render target. If source/dest color blend is +enabled, the surface format is further restricted to the set supported as alpha blend render target. +The last message sent to the render target by a thread must have the End Of Thread bit set in the +message descriptor and the dispatch mask set correctly in the message header to enable correct clearing +of the pixel scoreboard. +The stateless model cannot be used with this message (Binding Table Index cannot be 255). +This message can only be issued from a kernel specified in WM_STATE or 3DSTATE_WM (pixel shader +kernel), dispatched in non-contiguous mode. Any other kernel issuing this message will cause undefined +behavior. +The dual source message cannot be used if the Render Target Rotation field in SURFACE_STATE is set +to anything other than RTROTATE_0DEG. +This message cannot be used on a surface in field mode (Vertical Line Stride = 1) +If multiple SIMD8 Dual Source messages are delivered by the pixel shader thread, each SIMD8_DUALSRC_LO +message must be issued before the SIMD8_DUALSRC_HI message with the same Slot Group Select setting. + +SIMD8 Image Write: Out of bounds write to SURFTYPE_BUFFER with more than 8K elements is +undefined. +Execution Mask. The execution mask for render target messages is ignored. Control of which pixels are +active is controlled by the Pixel/Sample Enables fields in the message header. +Out-of-Bounds Accesses. Accesses to pixels outside of the surface are dropped and will not modify +memory contents. However, if the Render Target Array Index is out of bounds, it is set to zero and the +surface write is not surpressed. + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 276 + The following table indicates the surface formats that are supported by this message. + Surface Format Name +R32G32B32A32_FLOAT +R32G32B32A32_SINT +R32G32B32A32_UINT +R16G16B16A16_UNORM +R16G16B16A16_SNORM +R16G16B16A16_SINT +R16G16B16A16_UINT +R16G16B16A16_FLOAT +R32G32_FLOAT +R32G32_SINT +R32G32_UINT +B8G8R8A8_UNORM +B8G8R8A8_UNORM_SRGB +R10G10B10A2_UNORM +R10G10B10A2_UINT +R8G8B8A8_UNORM +R8G8B8A8_UNORM_SRGB +R8G8B8A8_SNORM +R8G8B8A8_SINT +R8G8B8A8_UINT +R16G16_UNORM +R16G16_SNORM +R16G16_SINT +R16G16_UINT +R16G16_FLOAT +B10G10R10A2_UNORM +B10G10R10A2_UNORM_SRGB +R11G11B10_FLOAT +R32_SINT +R32_UINT +R32_FLOAT +B5G6R5_UNORM +B5G6R5_UNORM_SRGB +B5G5R5A1_UNORM +B5G5R5A1_UNORM_SRGB +B4G4R4A4_UNORM +B4G4R4A4_UNORM_SRGB +R8G8_UNORM +R8G8_SNORM +R8G8_SINT +R8G8_UINT +R16_UNORM +R16_SNORM +R16_SINT +R16_UINT +R16_FLOAT +B5G5R5X1_UNORM +B5G5R5X1_UNORM_SRGB +R8_UNORM +R8_SNORM + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 277 + Surface Format Name +R8_SINT +R8_UINT +A8_UNORM +YCRCB_NORMAL +YCRCB_SWAPUVY +YCRCB_SWAPUV +YCRCB_SWAPY + + + + +3.9.11.1 Subspan/Pixel to Slot Mapping +The following table indicates the mapping of subspans, pixels, and samples to slots in the pixel shader +dispatch depending on the number of samples and message size. This table applies to all devices, +however NumSamples = 4X is supported only on, and NumSamples = 8X is supported only on. +Pixels are numbered as follows within a subspan: +0 = upper left +1 = upper right +2 = lower left +3 = lower right +sspi = Starting Sample Pair Index (from the message header) + Dispatch Size Num Samples + Slot Mapping + (SSPI = Starting Sample Pair Index) + 1X + SIMD32 Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[1].Pixel[3:0].Sample[0] + Slot[11:8] = Subspan[2].Pixel[3:0].Sample[0] + Slot[15:12] = Subspan[3].Pixel[3:0].Sample[0] + Slot[19:16] = Subspan[4].Pixel[3:0].Sample[0] + Slot[23:20] = Subspan[5].Pixel[3:0].Sample[0] + Slot[27:24] = Subspan[6].Pixel[3:0].Sample[0] + Slot[31:28] = Subspan[7].Pixel[3:0].Sample[0] + 2X + Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[1] + Slot[11:8] = Subspan[1].Pixel[3:0].Sample[0] + Slot[15:12] = Subspan[1].Pixel[3:0].Sample[1] + Slot[19:16] = Subspan[2].Pixel[3:0].Sample[0] + Slot[23:20] = Subspan[2].Pixel[3:0].Sample[1] + Slot[27:24] = Subspan[3].Pixel[3:0].Sample[0] + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 278 + Dispatch Size Num Samples + Slot Mapping + (SSPI = Starting Sample Pair Index) + Slot[31:28] = Subspan[3].Pixel[3:0].Sample[1] + 4X + Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[1] + Slot[11:8] = Subspan[0].Pixel[3:0].Sample[2] + Slot[15:12] = Subspan[0].Pixel[3:0].Sample[3] + Slot[19:16] = Subspan[1].Pixel[3:0].Sample[0] + Slot[23:20] = Subspan[1].Pixel[3:0].Sample[1] + Slot[27:24] = Subspan[1].Pixel[3:0].Sample[2] + Slot[31:28] = Subspan[1].Pixel[3:0].Sample[3] + SIMD16 8X + Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[1] + Slot[11:8] = Subspan[0].Pixel[3:0].Sample[2] + Slot[15:12] = Subspan[0].Pixel[3:0].Sample[3] + Slot[19:16] = Subspan[0].Pixel[3:0].Sample[4] + Slot[23:20] = Subspan[0].Pixel[3:0].Sample[5] + Slot[27:24] = Subspan[0].Pixel[3:0].Sample[6] + Slot[31:28] = Subspan[0].Pixel[3:0].Sample[7] + 1X + Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[1].Pixel[3:0].Sample[0] + Slot[11:8] = Subspan[2].Pixel[3:0].Sample[0] + Slot[15:12] = Subspan[3].Pixel[3:0].Sample[0] + 2X + Slot[3:0] = Subspan[0].Pixel[3:0].Sample[0] + Slot[7:4] = Subspan[0].Pixel[3:0].Sample[1] + Slot[11:8] = Subspan[1].Pixel[3:0].Sample[0] + Slot[15:12] = Subspan[1].Pixel[3:0].Sample[1] + +Restriction: +When SIMD32 or SIMD16 PS threads send render target writes with multiple SIMD8 and SIMD16 +messages, the following must hold: +All the slots (as described above) must have a corresponding render target write irrespective of the slot's +validity. A slot is considered valid when at least one sample is enabled. For example, a SIMD16 PS +thread must send two SIMD8 render target writes to cover all the slots. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 279 + PS thread must send SIMD render target write messages with increasing slot numbers. For example, +SIMD16 thread has Slot[15:0] and if two SIMD8 render target writes are used, the first SIMD8 render +target write must send Slot[7:0] and the next one must send Slot[15:8]. + +3.9.11.2 Message Descriptor + + Message Descriptor - Render Target Write + +Default Value: 0x00000000 +DWord Bit Description +0 31 Reserved + Format: MBZ + 29:14 Reserved + Format: MBZ + 13 Reserved + + Format: MBZ + 12 Last Render Target Select + This bit must be set on the last render target write message sent for each group of pixels. For single + render target pixel shaders, this bit is set on all render target write messages. For multiple render target + pixel shaders, this bit is set only on messages sent to the last render target. This bit must be zero for + SIMD8 Image Write message. + Programming Notes + In general, when threads are not launched by 3D FF, this bit must be zero. + 11 Slot Group Select + This field selects whether slots 15:0 or slots 31:16 are used for bypassed data. + Bypassed data includes the antialias alpha, multisample coverage mask, and if the header is not + present also includes the X/Y addresses and pixel enables. For 8- and 16-pixel dispatches, + SLOTGRP_LO must be selected on every message. For 32-pixel dispatches, this field must be set + correctly for each message based on which slots are currently being processed. + Value Name Description + 0 SLOTGRP_LO choose bypassed data for slots 15:0 + 1 SLOTGRP_HI choose bypassed data for slots 31:16 + + + Programming Notes + For SIMD8 Image Write message thsi field MBZ. + 10:8 Message Type + This field specifies the type of render target message. + For the SIMD8_DUALSRC_xx messages, the low bit indicates which slots to use for the pixel enables, + X/Y addresses, and oMask. + Value Name Description + 000b SIMD16 SIMD16 single source message + 001b SIMD16_REPDATA SIMD16 single source message with replicated data + 010b SIMD8_DUALSRC_LO SIMD8 dual source message, use slots 7:0 + 011b SIMD8_DUALSRC_HI SIMD8 dual source message, use slots 15:8 + 100b SIMD8_LO SIMD8 single source message, use slots 7:0 + 111b SIMD16_REPDATA It's only supported when accessing Tiled Memory. Using this Message + Type to access linear (Untiled) memory is UNDEFINED. + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 280 + Message Descriptor - Render Target Write + + Programming Notes Project + the above slots indicated are within the 16 slots selected by Slot Group Select. If + SLOTGRP_HI is selected, the SIMD8 message types above reference slots 23:16 or 31:24 + instead of 7:0 or 15:8, respectively. + SIMD16 messages are not supported for 8X MSAA when PS outputs depth. + SIMD16_REPDATA message must not be used in SIMD8 pixel-shaders. + 7:0 Reserved + Format: MBZ + + + +3.9.11.3 Message Header +The render target write message has a two-register message header. +If the header is not present, behavior is as if the message was sent with most fields set to the same value +that was delivered in R0 and R1 on the pixel shader thread dispatch. The following fields, which are not +delivered in the pixel shader dispatch, behave as if they are set to zero: +Render Target Index +Source0 Alpha Present to Render Target +DWord Bits Description + M0.7 31:0 + M0.6 31:0 + M0.5 31:10 Ignored + 9:8 + Color Code: This ID is assigned by the Windower unit and is used to track + synchronizing events. + Format: Reserved for HW Implementation Use. + 7:0 + FFTID. The Fixed Function Thread ID is assigned by the fixed function unit and is a + unique identifier for the thread. It is used to free up resources used by the thread upon + thread completion. + M0.4 31:0 Ignored (reserved for hardware delivery of binding table pointer) + M0.3 31:0 Ignored + M0.2 31:3 Ignored + 2:0 + Render Target Index. Specifies the render target index that will be used to select blend + state from BLEND_STATE. + Format = U3 + M0.1 31:6 + ColorCalculatorState Pointer. Specifies the 64-byte aligned pointer to the color + calculator state. This pointer is relative to the General State Base Address. + Format = GeneralStateOffset[31:6] + 5:0 Ignored +M0.0 31 Ignored + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 281 + DWord Bits Description + 30:27 + Viewport Index. Specifies the index of the viewport currently being used. + + Format = U4 + Range = [0,15] + 26:16 + Render Target Array Index. Specifies the array index to be used for the following + surface types: + SURFTYPE_1D: specifies the array index. Range = [0,511] + SURFTYPE_2D: specifies the array index. Range = [0,511] + SURFTYPE_3D: specifies the “z” or “r” coordinate. Range = [0,2047] + SURFTYPE_CUBE: specifies the face identifier. Range = [0,5] + SURFTYPE_BUFFER: must be zero. + face Render Target Array Index + +x 0 + -x 1 + +y 2 + -y 3 + +z 4 + -z 5 + + Format = U11 + The Render Target Array Index used by hardware for access to the Render Target is + overridden with the Minimum Array Element defined in SURFACE_STATE if it is out of + the range between Minimum Array Element and Depth. For cube surfaces, a depth + value of 5 is used for this determination. + + 15 + Front/Back Facing Polygon. Determines whether the polygon is front or back facing. + Used by the render cache to determine which stencil test state to use. + 0: Front Facing + 1: Back Facing + 14 + Ignored + + 14 + 13 + Source Depth Present to Render Target. Indicates that source depth is included in the + message. + 12 + oMask to Render Target + This bit indicates that oMask data is present in the message and is to be used to mask + off samples. + 11 + Source0 Alpha Present to RenderTarget. This bit indicates that Source0 Alpha (aka + o0.a) data is included in RTWrite message. If present, these alpha values are used as + inputs to AlphaTest and AlphaToCoverage functions. This is required to meet the API + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 282 + DWord Bits Description + rules when writing to multiple render targets (MRTs). + Programming Notes: + This bit should not be set when writing to RT0, though sending and using redundant + alpha will provide the correct results (at lower performance). + This bit is not supported on Dual-Source Blend message types, as source0 alpha is + already included in those messages. + This bit is not supported on replicated data message types. + 10:9 Ignored + 8:6 + Starting Sample Pair Index: indicates the index of the first sample pair of the dispatch + + Format = U3 + Range = [0,3] + 5:0 Ignored +M1.7 31:16 + Dispatched Pixel/Sample Enables. One bit per pixel (or sample within pixel) indicating + which pixels/samples were originally enabled when the thread was dispatched. This + field is only required for the end-of-thread message and on all dual-source messages. + The Dispatched Pixel/Sample Enablesmust be unmodified from the ones sent when the + pixel shader thread was initiated. If the Dispatched Pixel/Sample Enables are modified, + behavior is undefined. + Multisample Note: + When operating in PERSAMPLE mode these bits correspond to samples, not pixels. + Each subspan slot (4 bits) corresponds to a specific sample location for the subspan. + Note that in NUMSAMPLES_1 mode, a pixel and sample are synonomous. + When operating in PERPIXEL mode, this field is ignored, and instead the + SampleEnableMask (obtained via bypass) are used to clear the Depth Scoreboard. + 15:0 + Pixel/Sample Enables. One bit per pixel/sample indicating which pixels/samples are still + lit based on kill instruction activity in the pixel shader. This mask is used to control + actual writes to the color buffer. + Multisample Note: + When operating in PERSAMPLE mode these bits correspond to samples, not pixels, + as the PS is run per-sample. Each subspan slot (4 bits) corresponds to a specific + sample location for the subspan. + When operating in PERPIXEL mode, these bits still correspond to pixels, as the PS is + run per-pixel. Each pixel’s mask bit is replicated according to Number of Multisamples + and combined with other masks to control writes to the multisample locations. +M1.6 31:0 Ignored +M1.5 31:16 + Y3. Y coordinate for upper-left pixel of subspan 3 (slot 12) + + Format = U16 + 15:0 + X3. X coordinate for upper-left pixel of subspan 3 (slot 12) + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 283 + DWord Bits Description + Format = U16 + M1.4 31:16 Y2 + 15:0 X2 + M1.3 31:16 Y1 + 15:0 X1 + M1.2 31:16 Y0 + 15:0 X0 + M1.1 31:0 Ignored + M1.0 31:0 Ignored + + +3.9.11.4 Source 0 Alpha Payload +The source 0 alpha registers, if included, appear in M2 and M3, immediately following the header (if +present). +For the SIMD8 single source message, only slot 7:0 data is sent (M2). The source 0 alpha phases are not +supported for dual source messages. +DWord Bit Description +M2.7 31:0 + Source 0 Alpha for Slot 7 + Format = IEEE_Float + This and the next register is only included if Source 0 Alpha Present bit is set. +M2.6 31:0 Source 0 Alpha for Slot 6 +M2.5 31:0 Source 0 Alpha for Slot 5 +M2.4 31:0 Source 0 Alpha for Slot 4 +M2.3 31:0 Source 0 Alpha for Slot 3 +M2.2 31:0 Source 0 Alpha for Slot 2 +M2.1 31:0 Source 0 Alpha for Slot 1 +M2.0 31:0 Source 0 Alpha for Slot 0 +M3.7 31:0 Source 0 Alpha for Slot 15 +M3.6 31:0 Source 0 Alpha for Slot 14 +M3.5 31:0 Source 0 Alpha for Slot 13 +M3.4 31:0 Source 0 Alpha for Slot 12 +M3.3 31:0 Source 0 Alpha for Slot 11 +M3.2 31:0 Source 0 Alpha for Slot 10 +M3.1 31:0 Source 0 Alpha for Slot 9 +M3.0 31:0 Source 0 Alpha for Slot 8 + + +3.9.11.5 oMask Payload () +The oMask payload, if present, follows source 0 alpha. The value of ‘p’ depends on whether the header +and source 0 alpha are present. +Sample “n” for that pixel will be killed (not written to the render target or depth buffer) if bit “n” of the +oMask is zero. Bits numbers where “n” is larger than the number of multisamples are ignored. +For the SIMD8 messages, only slots 7:0 data is used, or only slots 15:8 depending on the Message Type +encoding. +DWord Bit Description + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 284 + DWord Bit Description +Mp.7 31:16 + oMask for Slot 15 + Format = 16-bit mask + This register is only included if oMask Present bit is set. + 15:0 oMask for Slot 14 +Mp.6 31:16 oMask for Slot 13 + 15:0 oMask for Slot 12 +Mp.5 31:16 oMask for Slot 11 + 15:0 oMask for Slot 10 +Mp.4 31:16 oMask for Slot 9 + 15:0 oMask for Slot 8 +Mp.3 31:16 oMask for Slot 7 + 15:0 oMask for Slot 6 +Mp.2 31:16 oMask for Slot 5 + 15:0 oMask for Slot 4 +Mp.1 31:16 oMask for Slot 3 + 15:0 oMask for Slot 2 +Mp.0 31:16 oMask for Slot 1 + 15:0 oMask for Slot 0 + + +3.9.11.6 Color Payload: SIMD16 Single Source + +3.9.11.6.1 Color Payload +This payload is included if the Message Type is SIMD16 single source. The value of ‘m’ depends on +whether the header, source 0 alpha, and oMask are present. + DWord Bit Description +Mm.7 31:0 + Slot 7 Red. Specifies the value of the slot’s red component. + + Format = IEEE Float, S31, or U32 depending on the Surface Format of the surface + being accessed. SINT formats use S31, UINT formats use U32, and all other formats + use Float. +Mm.6 31:0 Slot 6 Red +Mm.5 31:0 Slot 5 Red +Mm.4 31:0 Slot 4 Red +Mm.3 31:0 Slot 3 Red +Mm.2 31:0 Slot 2 Red +Mm.1 31:0 Slot 1 Red +Mm.0 31:0 Slot 0 Red +M(m+1).7 31:0 Slot 15 Red +M(m+1).6 31:0 Slot 14 Red +M(m+1).5 31:0 Slot 13 Red +M(m+1).4 31:0 Slot 12 Red +M(m+1).3 31:0 Slot 11 Red +M(m+1).2 31:0 Slot 10 Red +M(m+1).1 31:0 Slot 9 Red +M(m+1).0 31:0 Slot 8 Red +M(m+2) + Slot[7:0] Green. See Mm definition for slot locations + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 285 + DWord Bit Description +M(m+3) + Slot[15:8] Green. See M(m+1) definition for slot locations + +M(m+4) + Slot[7:0] Blue. See Mm definition for slot locations + +M(m+5) + Slot[15:8] Blue. See M(m+1) definition for slot locations + +M(m+6) + Slot[7:0] Alpha. See Mm definition for slot locations + +M(m+7) + Slot[15:8] Alpha. See M(m+1) definition for slot locations + + + +3.9.11.7 Color Payload: SIMD8 Single Source +This payload is included if the Message Type is SIMD8 single source or SIMD8 Image Write. For , the +value of ‘m’ depends on whether the header, source 0 alpha, and oMask are present. +DWord Bit Description +Mm.7 31:0 + Slot 7 Red. Specifies the value of the slot’s red component. + + Format = IEEE Float, S31, or U32 depending on the Surface Format of the surface + being accessed. SINT formats use S31, UINT formats use U32, and all other formats + use Float. +Mm.6 31:0 Slot 6 Red +Mm.5 31:0 Slot 5 Red +Mm.4 31:0 Slot 4 Red +Mm.3 31:0 Slot 3 Red +Mm.2 31:0 Slot 2 Red +Mm.1 31:0 Slot 1 Red +Mm.0 31:0 Slot 0 Red +M(m+1) + Slot[7:0] Green. See Mm definition for slot locations + +M(m+2) + Slot[7:0] Blue. See Mm definition for slot locations + +M(m+3) + Slot[7:0] Alpha. See Mm definition for slot locations + + + +3.9.11.8 Color Payload: SIMD16 Replicated Data +This payload is included if the Message Type specifies single source message with replicated data. One +set of R/G/B/A data is included in the message, and this data is replicated to all 16 pixels. +This message is legal with color data only (for , oMask is also legal with this message). The registers for +depth, stencil, and antialias alpha data cannot be included with this message, and the corresponding bits +in the message header must indicate that these registers are not present. +Programming Notes: +This message is allowed only on tiled surfaces +DWord Bit Description +Mm.7:4 31:0 Reserved + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 286 + DWord Bit Description +Mm.3 31:0 + Alpha. Specifies the value of all slots’ alpha channel. + + Format = IEEE Float, S31, or U32 depending on the Surface Format of the surface + being accessed. SINT formats use S31, UINT formats use U32, and all other formats + use Float. +Mm.2 31:0 Blue +Mm.1 31:0 Green +Mm.0 31:0 Red + + +3.9.11.9 Message Sequencing Summary +This section summarizes the sequencing that occurs for each legal render target write message. All +messages have the M0 and M1 header registers if the header is present. If the header is not present, all +registers below are renumbered starting with M0 where M2 appears. All cases not shown in this table are +illegal. +Key: +s0, s1 = source 0, source 1 +1/0 = slots 15:8 +3/2 = slots 7:0 +sZ = source depth +oM = oMask +Messag oMask Source Source M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 +e Type Presen Depth 0 + t Presen Alpha + t Presen + t +000 0 0 0 1/0R 3/2R 1/0G 3/2G 1/0B 3/2B 1/0A 3/2A +000 0 0 1 1/0s0 3/2s0 1/0R 3/2R 1/0G 3/2G 1/0B 3/2B 1/0A 3/2A + A A +000 0 1 0 1/0R 3/2R 1/0G 3/2G 1/0B 3/2B 1/0A + 3/2A 1/0sZ 3/2s + Z +000 0 1 1 1/0s0 3/2s0 1/0R 3/2R 1/0G 3/2G 1/0B 3/2B 1/0A 3/2A 1/0s 3/2s + A A Z Z +000 1 0 0 oM 1/0R 3/2R 1/0G 3/2G 1/0B 3/2B 1/0A 3/2A +000 1 0 1 1/0so 3/2s0 oM 1/0R 3/2R 1/0G 3/2G 1/0B 3/2B 1/0A 3/2A + A A +000 1 1 0 oM 1/0R 3/2R 1/0G 3/2G 1/0B 3/2B 1/0A 3/2A 1/0s 3/2s + Z Z +000 1 1 1 1/0s0 3/2s0 oM 1/0R 3/2R 1/0G 3/2G 1/0B 3/2B 1/0A 3/2A 1/0s 3/2s + A A Z Z +001 0 0 0 RGBA +001 1 0 0 oM RGBA +010 0 0 0 1/0s0 1/0s0 1/0s0 1/0s0 1/0s1 1/0s1 1/0s1 1/0s1 + R G B A R G B A +010 0 1 0 1/0s0 1/0s0 1/0s0 1/0s0 1/0s1 1/0s1 1/0s1 1/0s1 1/0sZ + R G B A R G B A +010 1 0 0 oM 1/0s0 1/0s0 1/0s0 1/0s0 1/0s1 1/0s1 1/0s1 1/0s1 + R G B A R G B A + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 287 + Messag oMask Source Source M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 +e Type Presen Depth 0 + t Presen Alpha + t Presen + t +010 1 1 0 oM 1/0s0 1/0s0 1/0s0 1/0s0 1/0s1 1/0s1 1/0s1 1/0s1 1/0s + R G B A R G B A Z +011 0 0 0 3/2s0 3/2s0 3/2s0 3/2s0 3/2s1 3/2s1 3/2s1 3/2s1 + R G B A R G B A +011 0 1 0 3/2s0 3/2s0 3/2s0 3/2s0 3/2s1 3/2s1 3/2s1 3/2s1 3/2sZ + R G B A R G B A +011 1 0 0 oM 3/2s0 3/2s0 3/2s0 3/2s0 3/2s1 3/2s1 3/2s1 3/2s1 + R G B A R G B A +011 1 1 0 oM 3/2s0 3/2s0 3/2s0 3/2s0 3/2s1 3/2s1 3/2s1 3/2s1 3/2s + R G B A R G B A Z +100 0 0 0 R G B A +100 0 0 1 s0A R G B A +100 0 1 0 R G B A sZ +100 0 1 1 s0A R G B A sZ +100 1 0 0 oM R G B A +100 1 0 1 s0A oM R G B A +100 1 1 0 oM R G B A sZ +100 1 1 1 s0A oM R G B A sZ + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 288 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V4 Pt 1 – 05 12 5/31/2012 289 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol4_part2.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol4_part2.txt new file mode 100644 index 0000000..d8d7b35 --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol4_part2.txt @@ -0,0 +1,5172 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 4 Part 2: Shared Functions – +Message Gateway, URB, Video Motion +Estimation, Pixel Interpolator (Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 + Contents +1. Shared Functions - Message Gateway ................................................................................................ 5 + 1.1 Messages ............................................................................................................................................. 5 + 1.1.1 Message Descriptor ........................................................................................................................ 6 + 1.1.2 OpenGateway Message ................................................................................................................. 7 + 1.1.3 CloseGateway Message ................................................................................................................. 8 + 1.1.4 GetTimeStamp Message .............................................................................................................. 11 + 1.1.5 BarrierMsg Message .................................................................................................................... 13 + 1.1.6 MMIOReadWrite Message ........................................................................................................... 15 +2. Shared Functions - Unified Return Buffer (URB) ............................................................................. 17 + 2.1 URB Size ............................................................................................................................................ 17 + 2.2 URB Access ....................................................................................................................................... 17 + 2.3 State ................................................................................................................................................... 18 + 2.4 URB Messages .................................................................................................................................. 18 + 2.4.1 Execution Mask ............................................................................................................................ 19 + 2.4.2 Message Descriptor ...................................................................................................................... 19 + 2.4.3 URB_WRITE* and URB_READ* .................................................................................................. 20 + 2.4.4 URB_ATOMIC* ............................................................................................................................. 32 +3. Shared Functions – Video Motion Estimation .................................................................................. 34 + 3.1 Theory of Operation ........................................................................................................................... 34 + 3.1.1 Shape Decision ............................................................................................................................ 34 + 3.1.2 Integer Motion Estimation ............................................................................................................. 39 + 3.1.3 Fractional Motion Estimation ........................................................................................................ 44 + 3.1.4 BME and Weighted Prediction...................................................................................................... 45 + 3.1.5 Skip Check.................................................................................................................................... 46 + 3.1.6 Intra Prediction Estimation ............................................................................................................ 48 + 3.1.7 Transform Adjusted SAD .............................................................................................................. 48 + 3.1.8 Early Decisions ............................................................................................................................. 50 + 3.1.9 Performance Information .............................................................................................................. 51 + 3.1.10 VME Changes............................................................................................................................. 52 + 3.2 Surfaces ............................................................................................................................................. 52 + 3.3 State ................................................................................................................................................... 52 + 3.3.1 BINDING_TABLE_STATE............................................................................................................ 52 + 3.3.2 SURFACE_STATE ....................................................................................................................... 52 + 3.3.3 VME_STATE ................................................................................................................................ 53 + 3.4 Change Details ................................................................................................................................... 56 + 3.4.1 Record Stream-out and Stream-in ............................................................................................... 56 + 3.4.2 MV Definitions and Precision........................................................................................................ 57 + 3.4.3 Expanded MV Costs ..................................................................................................................... 58 + 3.4.4 Remove Skip MV Restriction ........................................................................................................ 59 + 3.4.5 Bilinear Interpolation ..................................................................................................................... 59 + 3.4.6 AVC Intra Mode Mask .................................................................................................................. 59 + 3.5 Messages ........................................................................................................................................... 59 + 3.5.1 VME Motion Search Request ....................................................................................................... 60 + 3.5.2 Message Descriptor ...................................................................................................................... 60 + 3.5.3 Input Message .............................................................................................................................. 61 + 3.5.4 Writeback Message ...................................................................................................................... 80 + 3.5.5 Stream-in\Stream-out Message.................................................................................................... 90 +4. Shared Functions Pixel Interpolater .................................................................................................. 93 + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 3 + 4.1 Messages ........................................................................................................................................... 93 + 4.1.1 Initiating Message ......................................................................................................................... 93 + 4.1.2 Writeback Message ...................................................................................................................... 98 + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 4 + 1. Shared Functions - Message Gateway +The Message Gateway shared function provides a mechanism for active thread-to-thread communication. +Such thread-to-thread communication is based on direct register access. One thread, a requester +thread, is capable of writing into the GRF register space of another thread, a recipient thread. Such +direct register access between two threads in a multi-processor environment some time is referred to as +remote register access. Remote register access may include read or write. The architecture supports +remote register write, but not remote register read (natively). Message Gateway facilitates such remote +register write via message passing. The requester thread sends a message to Message Gateway +requesting a write to the recipient thread’s GRF register space. Message Gateway sends a writeback +message to the recipient thread to complete the register write on behave of the requester. The requester +thread and the recipient thread may be on the same EU or on different EUs. +When Bypass Gateway Control is set to 1, commands OpenGateway and CloseGateway are no longer +used, the gateway parameters are taking the default values as the following: + +  RegBase = 0 +  Gateway Size check and Key check are bypassed. +  Gateway Open (an internal signal that is used to be set by OpenGateway message) check is + bypassed + +A separate Gateway exists per half-slice in the architecture. For ForwardMsg this is handled +transparently, but barriers can only be accessed by threads in the local half-slice. This means that all +threads that access a shared barrier need to use the half-slice select in GPGPU_OBJECT and +MEDIA_OBJECT to stay on a single half-slice. GPGPU_WALKER handles this automatically. + + +1.1 Messages +Message Gateway supports such thread-to-thread communication with the following three messages: + +  OpenGateway: opens a gateway for a requester thread. Once a thread successfully opens its + gateway, it can be a recipient thread to receive remote register write. +  CloseGateway: closes the gateway for a requester thread. Once a thread successfully closes its + gateway, Message Gateway will block any future remote register writes to this thread. +  ForwardMsg: forwards a formatted message (remote register write) from a requester thread to a + recipient thread. +  GetTimeStamp: reads absolute and relative timestamps for a requester thread. +  BarrierMsg: A set of threads sends this message to the Gateway. When all threads in a group have + sent the message, a reply (both a register write and an N0 notification) is sent to each member of + the group. +  UpdateGatewayState: updates the internal state of the Message Gateway. + One example usage is to allow a control thread to change Barrier Byte to convey dynamic state + information. This may be used to support interrupt when persistent compute/worker threads are + synchronized using Barrier. +  MMIO Read/Write: allows a message to read or write an MMIO register. The MEDIA_VFE_STATE + command has a field which limits the accesses for security. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 5 + 1.1.1 Message Descriptor +The following message descriptor applies to all messages supported by Message Gateway. + Bit Description + 19 + Header Present + This bit must be set to zero for all Message Gateway messages. + (this bit is not part of the shared function specific message descriptor) + +18:17 + Ignored (these bits are not part of the shared function specific message descriptor) +16:15 + Notify. Send Notification Signal. + This is a two-bit field indicating which notify event is sent. + 00: No notify + 01: Increment recipient thread’s N0 notification counter + 10: Increment recepient thread’s N2 notification counter + 11: Reserved + This field is only valid for a ForwardMsg message. It is ignored for other messages. The BarrierMsg message + always increments the N0 notification counter. + 14 + AckReq. Acknowledgment Required. When this bit is set, an acknowledgment return message is required. + Message Gateway will send a writeback message containing the error code to the requester thread using the + post destination register address. When this bit is not set, no writeback message is sent to the requesting + thread by Message Gateway, even if an error occurs. + This field is valid for OpenGateway, CloseGateway, ForwardMsg and BarrierMsg messages. + When this bit is set, post destination register must be valid and the response length must be 1. + When this bit is not set, post destination register must be null and the response length must be 0. + This bit cannot be set when EOT is set; otherwise, hardware behavior is undefined. + 0 = No Acknowledgement is required. + 1 = Acknowledgement is required. +13:3 Reserved: MBZ + 2:0 + SubFuncID. Identify the supported sub-functions by Message Gateway. Encodings are: + 000 = OpenGateway. Open the gateway for the requester thread. + 001 = CloseGateway. Close the gateway for the requester thread. + 010 = ForwardMsg. Forward the formatted message to the recipient thread with the given offset from the + recipient’s register base. + 011 = GetTimeStamp. Read absolute and relative timestamps. + 100 = BarrierMsg. Record an additional thread reaching the barrier. + 101 = UpdateGatewayState. Update the barrier byte for a barrier. + 110 = MMIO Read/Write + Others are reserved + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 6 + 1.1.2 OpenGateway Message +The OpenGateway message opens a communication channel between the requesting thread and other +threads. It specifies a key for other threads to access its gateway, as well as the GRF register range +allowed to be written. The message consists of a single 256-bit message payload. +If the AckReq bit is set, a single 256-bit payload writeback message is sent back to the requesting thread +after completion of the OpenGateway function. Only the least significant DWord in the post destination +register is overwritten. +If the EOT is set for this message, Message Gateway will ignore this message; instead, it will close the +gateway for the requesting thread regardless of the previous state of the gateway. +It is software’s policy to determine how to generate the key. + +1.1.2.1 Message Payload +DWord Bit Description + M0.7 31:0 + Reserved + + M0.6 31:0 + Reserved + + 31:29 + M0.5 Reserved: MBZ + + 28:21 + RegBase: The register base address to be stored in the Message Gateway. It is used to compute the + destination GRF register address from the offset field in ForwardMsg. RegBase contains 256-bit GRF + aligned register address. + Note 1: This field aligns with bits [28:21] of the Offset field of the message payload for ForwardMsg. + Note 2: the most significant bit of this field must be zero. + Format = U8 + Range = [0,127] + + 20:11 + Reserved: MBZ + + 10:8 + Gateway Size: The range limit for messages through the Message Gateway. The maximal allowed + Gateway Size is 32 GRF registers. + 000: 1 GRF Register + 001: 2 GRF Registers + 010: 4 GRF Registers + 011: 8 GRF Registers + 100: 16 GRF Registers + 101: 32 GRF Registers + 7:0 + Dispatch ID: This ID is assigned by the fixed function unit and is a unique identifier for the thread. It is + used to free up resources used by the thread upon thread completion. + This field is ignored by Message Gateway + This field is only required for a thread that is created by a fixed function (therefore, not a child thread) + and EOT bit is set for the message. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 7 + DWord Bit Description + 31:16 + M0.4 Reserved: MBZ + + 15:0 + Reserved: MBZ + +M0.3:0 Ignored + + +1.1.2.2 Writeback Message to Requester Thread +The writeback message is only sent if the AckReq bit in the message descriptor is set. +DWord Bit Description +W0.7:1 Reserved (not overwritten) + W0.0 31:20 Reserved + 19:16 + Shared Function ID: Contains the message gateway’s shared function ID. + + 15:3 Reserved + 2:0 + Error Code + 000: Successful. No Error (Normal) + 101: Opcode Error. Attempt to send a message which is not either open/close/forward + other codes: Reserved + + + +1.1.3 CloseGateway Message +The CloseGateway message closes a communication channel for the requesting thread that was +previously opened with OpenGateway. Each thread is allowed to have only one open gateway at a time, +thus no additional information in the message payload is required to close the gateway. The message +consists of a single 256-bit message payload.is +If the AckReq bit is set, a single 256-bit payload writeback message is sent back to the requesting thread +after completion of the CloseGateway function. Only the least significant DWord in the post destination +register is overwritten. + +1.1.3.1 Message Payload +DWord Bit Description +M0.7:6 Ignored + 31:8 Ignored + M0.5 + 7:0 + Dispatch ID: This ID is assigned by the fixed function unit and is a unique identifier for the thread. It is + used to free up resources used by the thread upon thread completion. + This field is ignored by Message Gateway + This field is only required for a thread that is created by a fixed function (therefore, not a child thread) + and EOT bit is set for the message. +M0.4:0 Ignored + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 8 + 1.1.3.2 Writeback Message to Requester Thread +The writeback message is only sent if the AckReq bit in the message descriptor is set. +DWord Bit Description +W0.7:1 Reserved (not overwritten) + W0.0 31:20 Reserved + 19:16 + Shared Function ID: Contains the message gateway’s shared function ID. + + 15:3 Reserved + 2:0 + Error Code + 000: Successful. No Error (Normal) + 101: Opcode Error. Attempt to send a message which is not either open/close/forward + other codes: Reserved + + +1.1.3.3 ForwardMsg Message +The ForwardMsg message gives the ability for a requester thread to write a data segment in the form of +a byte, a dword, 2 dwords, or 4 dwords to a GRF register in a recipient thread. The message consists of a +single 256-bit message payload, which contains the specially formatted data segment. +The ForwardMsg message utilizes a communication channel previously opened by the recipient thread. +The recipient thread has communicated its EUID, TID, and key to the requester thread previously via +some other mechanism. Generally, this is done through the thread spawn message from parent to child +thread, allowing each child (requester) to then communicate with its parent through a gateway opened by +the parent (recipient). The child could then use ForwardMsg message to communicate its own EUID, TID, +and key back to the parent to enable bi-directional communication after opening its own gateway. +If the AckReq bit is set, a single 256-bit payload writeback message is sent back to the requester thread +after completion of the ForwardMsg function. Only the least significant DWord in the post destination +register is overwritten. +If the Notify bit in the message descriptor is set, a ‘notification’ is sent to the recipient thread in order to +increment the recipient thread’s notification counter. This allows multiple messages to be sent to the +recipient without waking up the recipient thread. The last message, having this bit set, will then wake up +the recipient thread. + +1.1.3.4 Message Payload +DWord Bit Description + M0.7 31:0 + Reserved + + M0.6 31:0 + Reserved + + 31:29 Reserved: MBZ + M0.5 + 28:16 + Offset: It provides the destination register position in the recipient thread GRF register space as the + offset from the RegBase stored in the recipient thread’s gateway entry. The offset is in unit of byte, + such that bits [28:21] is the 256-bit aligned register offset and bits [4:0] is the sub-register offset. The + sub-register offset must be aligned to the Length field in bits [10:8]. The subfields of Offset are further + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 9 + DWord Bit Description + illustrated as the following. + Offset[28:21]: Register offset from the gateway base (Range [0, 127]: bit 12 MBZ) + Offset[20:18]: DW offset + Offset[17:16]: Byte offset (must be 00 for all DW length cases) + Programming restriction: R0 can not be used as destination GRF register for ForwardMsg. NULL + register is also not allowed as destination. + 15:11 Reserved: MBZ + 10:8 + Length: The length of the data segment. + 000: 1 byte + 001: 1 word + 010: 1 dword + 011: 2 dwords + 100: 4 dwords + 101-111: Reserved + + 7:0 + Dispatch ID: This ID is assigned by the fixed function unit and is a unique identifier for the thread. It is + used to free up resources used by the thread upon thread completion. + This field is ignored by Message Gateway + This field is only required for a thread that is created by a fixed function (therefore, not a child thread) + and EOT bit is set for the message. + 31:30 Ignored + M0.4 + 29 + 28 + 31:30 + 29:28 + 27:24 + EUID: The Execution Unit ID as part of the Recipient field is used to identify the recipient thread to + whom the message is forwarded. + 23:19 Ignored + 18:16 + TID: The Thread ID as part of the Recipient field is used to identify the recipient thread to whom the + message is forwarded. + + 15:0 + Key + The key to match with the one stored in the recipient thread’s entry in Message Gateway. + Ignored +M0.3 31:0 + Data Segment DWord 3: valid only for the 4-DWord data segment length + +M0.2 31:0 + Data Segment DWord 2: valid only for the 4-DWord data segment length + +M0.1 31:0 + Data Segment Dword 1: valid only for the 2- and 4-DWord data segment lengths + + 31:24 + M0.0 Data Segment Byte 0: the same byte must be copied to all Data Segment Dword 0: valid only for + four positions within this DWord. Valid only for the 1-Byte the 1-, 2- and 4-Dword data segment + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 10 + DWord Bit Description + data segment length. lengths + 23:16 + Data Segment Byte 0 + + 15:8 + Data Segment Byte 0 + + 7:0 + Data Segment Byte 0 + + + +1.1.3.5 Writeback Message to Requester Thread +The writeback message is only sent if the AckReq bit in the message descriptor is set. +DWord Bit Description +W0.7:1 Reserved (not overwritten) + W0.0 31:20 Reserved + 19:16 + Shared Function ID: Contains the message gateway’s shared function ID. + + 15:3 Reserved + 2:0 + Error Code + 000: Successful. No Error (Normal) + 001: Reserved + 010: Gateway Closed. Attempt to send a message through a closed gateway + 101: Opcode Error. Attempt to send a message which is not either open/close/forward + 110: Invalid Message Size. Attempt to forward a message with length greater than 4 DW + 111: Reserved + + +1.1.3.6 Writeback Message to Recipient Thread +This message contains the byte or dwords data segment indicated in the message written to the GRF +register offset indicated. Only the byte/dword(s) will be enabled, all other data in the GRF register is +untouched. + + +1.1.4 GetTimeStamp Message +The GetTimeStamp message gives the ability for a requester thread to read the timestamps back from +the message gateway. The message consists of a single 256-bit message payload. +AbsoluteTimeLap is based on an absolute wall clock in unit of nSec/uSec that is independent of context +switch or GPU frequency adjustment. Message Gateway shares the same GPU timestamp. Details can +be found in the TIMESTAMP register section in vol1c Memory Interface and Command Stream. +RelativeTimeLap is based on a relative time count that is counting the GPU clocks for the context. The +relative time count is saved/restored during context switch. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 11 + 1.1.4.1 Message Payload +DWord Bit Description + M0.7 31:0 + Reserved + + M0.6 31:0 + Reserved + + 31 + M0.5 Return to High GRF: + 0: the return 128-bit data goes to the first half of the destination GRF register + 1: the return 128-bit data goes to the second half of the destination GRF register + 30:8 Reserved : MBZ + 7:0 + Dispatch ID: This ID is assigned by the fixed function unit and is a unique identifier for the thread. It is + used to free up resources used by the thread upon thread completion. + This field is ignored by Message Gateway + This field is only required for a thread that is created by a fixed function (therefore, not a child thread) + and EOT bit is set for the message. + M0.4 31:0 Ignored + M0.3 31:0 Ignored + M0.2 31:0 Ignored + M0.1 31:0 Ignored + M0.0 31:0 Ignored + + +1.1.4.2 Writeback Message to Requester Thread +As the writeback message is only sent if the AckReq bit in the message descriptor is set, AckReq bit +must be set for this message. +Only half of the destination GRF register is updated (via write-enables). The other half of the register is +not changed. This is determined by the Return to High GRF control field. +Writeback Message if Return to High GRF is set to 0: +DWord Bit Description +W0.7:4 Reserved (not overwritten) + W0.3 31:0 + RelativeTimeLapHigh: This field returns the MSBs of time lap for the relative clock since the previous + reset. This field represents 1.024 uSec increment of the time stamp. Hardware handles the + wraparound (over 64 bit boundary) of the timestamp. + Format: U12 + + 31:20 + W0.2 RelativeTimeLapLow: This field returns the LSBs of time lap for the relative clock since the previous + reset. This field represents 1/4 nSec increment of the time stamp. Hardware handles the wraparound + (over 64 bit boundary) of the timestamp. + Format: U12 + 19:0 Reserved : MBZ + W0.1 31:0 + AbsoluteTimeLapHigh: This field returns the MSBs of time lap for the absolute clock since the + previous reset. This field represents 1.024 uSec increment of the time stamp. Hardware handles the + wraparound (over 64 bit boundary) of the timestamp. + Format: U12 + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 12 + DWord Bit Description + 31:20 + W0.0 AbsoluteTimeLapLow: This field returns the LSBs of time lap for the absolute clock since the + previous reset. This field represents 1/4 nSec increment of the time stamp. Hardware handles the + wraparound (over 64 bit boundary) of the timestamp. + Format: U12 + 19:0 Reserved : MBZ + +Writeback Message if Return to High GRF is set to 1: +DWord Bit Description + W0.7 31:0 + RelativeTimeLapHigh + + 31:20 + W0.6 RelativeTimeLapLow + + 19:0 Reserved : MBZ + W0.5 31:0 + AbsoluteTimeLapHigh + + 31:20 + W0.4 AbsoluteTimeLapLow + + 19:0 Reserved : MBZ +W0.3:0 Reserved : MBZ + + +1.1.5 BarrierMsg Message +The BarrierMsg message gives the ability for multiple threads to synchronize their progress. This is useful +when there are data shared between threads. The message consists of a single 256-bit message +payload. +Upon receiving one such message, Message Gateway increments the Barrier counter and mark the +Barrier requester thread. There is no immediate response from the Message Gateway. When the counter +value equates Barrier Thread Count, Message Gateway will send response back to all the Barrier +requesters. + +1.1.5.1 Message Payload +DWord Bit Description + M0.7 31:0 + Reserved + + M0.6 31:0 + Reserved + + M0.5 31:0 Ignored + M0.4 31:0 Ignored + M0.3 31:0 Ignored + 31:28 Ignored + M0.2 + 27:24 + BarrierID. This field indicates which one from the 16 Barrier States is updated. + Format: U4 + Note: this field location matches with that of R0 header. + 23:16 + Barrier.Offset. This is the offset for the Barrier to indicate the offset from the requester’s RegBase. + Regbase is 0 if Bypass Gateway Control is 1. Barrier.Offset + RegBase must be in the valid GRF + range, but not point to r0. Otherwise, hardware behavior is undefined. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 13 + DWord Bit Description + It is in unit of 256-bit GRF register. + The most significant bit of this field must be zero. + Format = U8 + Range = [0,127] + 15:0 Ignored +M0.1 31:0 Ignored +M0.0 31:4 Ignored + + +1.1.5.2 Message Payload +DWord Bit Description + M0.7 31:0 + Ignored + + M0.6 31:0 + Ignored + + M0.5 31:0 Ignored + M0.4 31:0 Ignored + M0.3 31:0 + Ignored + + 31 + M0.2 Ignored + + 30:28 Ignored + 27:24 + BarrierID. This field indicates which one from the 16 Barrier States is updated. + Format: U4 + Note: this field location matches with that of R0 header. + 23:16 + Ignored + + 15 + Barrier Count Enable: Allows the message to reprogram the barrier count. + If set, the current value of the barrier state is compared to the Barrier Count field + (below). If these values are equal, the barrier is considered satisfied, barrier responses + are sent to the waiting thread(s) including the sending thread, and the barrier state is + reset to 0. If these values are not equal, the barrier state is incremented and the + sending thread is added to the list of threads waiting on this barrier. + If clear, the Message Gateway increments the Barrier counter and marks the Barrier + requester thread. There is no immediate response from the Gateway. When the + counter value equates Barrier Thread Count, Gateway will send response back to all + the Barrier requesters. + Format: Enable + 14:9 + Barrier Count: + If Barrier Count Enable is set, this field specifies the terminating barrier count. + Otherwise this field is ignored. All threads that belong to a single barrier must deliver + the same value for this field for a particular barrier iteration. + + 8:0 Ignored + M0.1 31:0 Ignored + M0.0 31:4 Ignored + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 14 + 1.1.5.3 Writeback Message to Requester Thread +The writeback message is only sent if the AckReq bit in the message descriptor is set. + DWord Bit Description + W0.7:1 Reserved (not overwritten) + W0.0 31:20 Reserved + 19:16 Shared Function ID: Contains the message gateway’s shared function ID. + 15:3 Reserved + 2:0 + Error Code + 000: Successful. No Error (Normal) + 001: Error (Barrier is inactive). + Other encodings are reserved. + + +1.1.5.4 Broadcast Writeback Message +When the count for a Barrier reaches Barrier.Count, the Message Gateway sends the notification bit N0 +to each EU/Thread that reached the barrier. A Barrier Return Byte is not sent. +DWord Bit Description +W0.7:1 Reserved (not overwritten) + 31:16 Reserved (not overwritten) + W0.0 + 15:8 Reserved (not overwritten) + 7:0 + Reserved (not overwritten) + + + +1.1.6 MMIOReadWrite Message + +1.1.6.1 Message Payload +DWord Bit Description + M0.7 31:0 + Reserved + + M0.6 31:0 + Reserved + + M0.5 31:0 Ignored + M0.4 31:0 Ignored + M0.3 31:1 Ignored + 0 + MMIO R/W: + 0 – MMIO Read – a response will be sent to the EU with read data + 1 – MMIO Write – no response is sent to EU (unless acknowledge requested in sideband) + 31:28 Ignored + M0.2 + 22:2 + MMIO Address: + The MMIO DWord address to be accessed. + 1:0 Ignored + M0.1 31:0 Ignored + M0.0 31:0 MMIO Write Data (Only if MMIO R/W = 1, otherwise ignored). + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 15 + 1.1.6.2 Writeback Message to Requester Thread (MMIO Read Only) +DWord Bit Description + R0.7 31:0 Ignored + R0.6 31:0 Ignored + R0.5 31:0 Ignored + R0.4 31:0 Ignored + R0.3 31:0 Ignored + R0.2 31:0 Ignored + R0.1 31:0 Ignored + R0.0 31:0 + MMIO Read Data + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 16 + 2. Shared Functions - Unified Return + Buffer (URB) +The Unified Return Buffer (URB) is a general-purpose buffer used for sending data between different +threads, and, in some cases, between threads and fixed-function units (or vice-versa). A thread accesses +the URB by sending messages. + + +2.1 URB Size +A URB entry is a logical entity within the URB, referenced by an entry handle and comprised of some +number of consecutive rows. A row corresponds in size to a 256-bit EU GRF register. Read/write access +to the URB is generally supported on a row-granular basis. +URB Size URB Rows URB Rows when SLM Enabled +128k 4096 2048 +256k 8096 4096 + + + +2.2 URB Access +The URB can be written by the following agents: + +  Command Stream (CS) can write constant data into Constant URB Entries (CURBEs) as a result of + processing CONSTANT_BUFFER commands. +  The Video Front End (VFE) fixed-function unit of the Media pipeline can write thread payload data in + to its URB entries. +  The Vertex Fetch (VF) fixed-function unit of the 3D pipeline can write vertex data into its URB entries +  Threads can write data into URB entries via URB_WRITE messages sent to the URB shared + function. + +The URB can be read by the following agents: + +  The Thread Dispatcher (TD) is the main source of URB reads. As a part of spawning a thread, + pipeline fixed-functions provide the TD with a number of URB handles, read offsets, and lengths. + The TD reads the specified data from the URB and provide that data in the thread payload pre- + loaded into GRF registers. +  The Geometry Shader (GS) and Clipper (CLIP) fixed-function units of the 3D pipeline can read + selected parts of URB entries to extract vertex data required by the pipeline. +  The Windower (WM) FF unit reads back depth coefficients from URB entries written by the Strip/Fan + unit. + +Note that the CPU can not read the URB directly. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 17 + 2.3 State +The URB function is stateless, with all information required to perform a function being passed in the write +message. +See URB Allocation (Graphics Processing Engine ) for a discussion of how the URB is divided amongst the +various fixed functions. + + +2.4 URB Messages +This section documents the global aspects of the URB messages. The actual data stored in URB entries +differs for each fixed function – refer to 3D Pipeline and the fixed-function chapters or details on 3D URB +data formats and Media for media-specific URB data formats. +URB Handles: Unlike prior products where the URB handle contents was not specified for software use, +URB handles are now specified as offsets into the URB partition in the L3 cache, in 512-bit units. Thus, +kernels are now allowed to perform math operations on URB handles. + +  The End of Thread bit in the message descriptor may be set on URB messages only in threads + dispatched by the vertex shader (VS), hull shader (HS), domain shader (DS), and geometry shader + (GS). The End of Thread bit cannot be set on URB_READ* or URB_ATOMIC* messages. + +Execution Mask. The low 8 bits of the execution mask on the send instruction determines which DWords +from each write data phase are written or which DWords from each read phase are written to the +destination GRF register. The execution mask is ignored on URB_ATOMIC* messages, since this is a +scalar operation that is always enabled. +Out-of-Bounds Accesses. Reads to addresses outside of the URB region allocated in the L3 cache +return 0. Writes to addresses outside of the URB region are dropped and will not modify any URB data. + Header Shared Local Memory Stateless Vector + Message Type Required Support Support Address Modes Width +URB Read yes N/A N/A 1, 2 +HWORD + handle + URBoffset + or + handle + URBoffset + + offset +URB Write yes N/A N/A 1, 2 +HWORD + handle + URBoffset + or + handle + URBoffset + + offset +URB Read yes N/A N/A 1, 2 +OWORD + handle + URBoffset + or + handle + URBoffset + + offset +URB Write yes N/A N/A 1, 2 +OWORD + handle + URBoffset + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 18 + Header Shared Local Memory Stateless Vector +Message Type Required Support Support Address Modes Width + or + handle + URBoffset + + offset +URB Atomic yes N/A N/A handle + URBoffset 1 +MOV +URB Atomic INC yes N/A N/A handle + URBoffset 1 + + “offset” is in the message payload, and is per-slot. +“handle” is the handle address in the message header. +“URBoffset” is the Global Offset field in the URB message descriptor. + + +2.4.1 Execution Mask +The Execution Mask specified in the ‘send’ instruction determines which DWords within each message +register are read/written to the URB. + + +2.4.2 Message Descriptor + Bit Description + 19 Header Present + This bit must be set to one for all URB messages. + +18:17 Ignored + 16 + Per Slot offset: If clear, the slot offset fields in the header are ignored. + + If set the slot offset fields are added to the global offset to obtain the overall offset. + Programming Notes: +  This bit must be 0 for URB_ATOMIC_* messages. + + 15 + Complete + + For URB_WRITE*, URB_SIMD8_WRITE and URB_ATOMIC*: This bit is ignored. + For URB_READ* and URB_SIMD8_READ: If set, this signals that the thread is finished reading from the + URB entry(s) referenced by the handles(s), causing the entry(s) to be deallocated. + This bit is strictly control information passed to snooping FF units. The URB shared function + itself does not use this bit for any purpose. + 14 + Swizzle Control. This field is used to specify which “swizzle” operation is to be performed on the write + data. It indirectly specifies whether one or two handles are valid. + 0: URB_NOSWIZZLE + The message accesses a single URB entry (using URB Handle 0). + + 1: URB_INTERLEAVED + The message accesses two URB entries. The data is interleaved such that the upper DWords (7:4) of + each 256-bit unit contain data associated with URB Handle 1, and the lower DWords (3:0) contain data + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 19 + Bit Description + associated with URB Handle 0. + +13:3 + Global Offset. This field specifies a destination offset (in 256-bit units) from the start of the URB entry(s), + as referenced by URB Handle n, at which the data (if any) will be written to or read from. + + When URB_INTERLEAVED is used, this field provides a 256-bit granular offset applied to both + URB entries. + If the Per Slot Offset bit is set, this offset is added to the per-slot offsets in the header to obtain the + overall offset. + For the URB_*_OWORD messages, this offset is in 128-bit units instead of 256-bit units. + For the URB_ATOMIC* messages, this offset is in 32-bit units instead of 256-bit units. + Format = U11 + Range = [0, 1023] for URB_*_HWORD messages. + Range = [0, 2047] for URB_*_OWORD messages. + Range = [0, 2047] for URB_ATOMIC* messages. + 2:0 + URB Opcode + + 0: URB_WRITE_HWORD + 1: URB_WRITE_OWORD + 2: URB_READ_HWORD + 3: URB_READ_OWORD + 4: URB_ATOMIC_MOV + 5: URB_ATOMIC_INC + 6-7: Reserved + + + +2.4.3 URB_WRITE* and URB_READ* +The URB_WRITE* and URB_READ* messages share the same header definition. URB_WRITE has +additional payload containing the write data, but has no writeback message. URB_READ has no payload +beyond the header (message length is always one), but always has a writeback message. +URB_WRITE_SIMD4x2 has a single-phase payload with the per-slot offsets followed by the write data, +and has no writeback message. URB_READ_SIMD4x2 has a single phase payload containing the per- +slot offsets. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 20 + 2.4.3.1 Message Header +M0.5[7:0] bits in message header are used for enabling DWs in cull test, at HDC unit by HS kernel, while +writing TF data using URB write messages. Cull test is performed on outside TF and HS kernel set the +appropriate DW enable, which carry the TF for different domain types. When DW is enabled and if cull +test is positive, HS stage will be informed by HDC unit, to cull the HS handle early at HS stage itself. + DWord Bits Description + M0.7 31:0 + Reserved + + M0.6 31:0 + Reserved + + M0.5 31:17 Ignored + 16 + High OWORD Enable + + For URB_READ_OWORD and URB_WRITE_OWORD with + NOSWIZZLE indicates whether the 128 bits of the GRF + register is used. + 0: 1 OWord, read into or written from the low 128 bits of the + GRF register + 1: 1 OWord, read into or written from the high 128 bits of the + GRF register + 15 + Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask + When Swizzle Control = URB_INTERLEAVED this bit controls + Vertex 1 DATA[3], when Swizzle Control = URB_NOSWIZZLE + this bit controls Vertex 0 DATA[7]. This bit is ANDed with the + corresponding channel enable to determine the final channel + enable. For the URB_READ_OWORD & + URB_READ_HWORD messages, when final channel enable + is 1 it indicates that Vertex 1 DATA [3] will be included in the + writeback message. For the URB_WRITE_OWORD & + URB_WRITE_HWORD messages, when final channel enable + is 1 it indicates that Vertex 1 DATA [3] will be written to the + surface. + 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included + 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included + 14 + Vertex 1 DATA [2] Channel Mask + + 13 + Vertex 1 DATA [1] Channel Mask + + 12 + Vertex 1 DATA [0] Channel Mask + + 11 + Vertex 0 DATA [3] Channel Mask + + 10 + Vertex 0 DATA [2] Channel Mask + + 9 + Vertex 0 DATA [1] Channel Mask + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 21 + DWord Bits Description + 8 + Vertex 0 DATA [0] Channel Mask + + 7:0 + Reserved + + M0.4 31:0 + Slot 1 Offset. This field, after adding to the Global Offset field in + the message descriptor, specifies the offset (in 256-bit units) + from the start of the URB entry, as referenced by URB Handle + 1, at which the data will be accessed. This field is ignored + unless Swizzle Control is set to URB_INTERLEAVED. + For the URB_*_OWORD messages, this offset is in 128-bit + units instead of 256-bit units. + Format = U32 + Range = [0, 1023] for URB_*_HWORD messages. The range + of the calculated offset must fall within the range [0, 1023] or + behavior is undefined. + Range = [0, 2047] for URB_*_OWORD messages. The range + of the calculated offset must fall within the range [0, 2047] or + behavior is undefined. + M0.3 31:0 + Slot 0 Offset. This field, after adding to the Global Offset field in + the message descriptor, specifies the offset (in 256-bit units) + from the start of the URB entry, as referenced by URB Handle + 0, at which the data will be accessed. + + For the URB_*_OWORD messages, this offset is in 128-bit + units instead of 256-bit units. + Format = U32 + Range = [0, 1023] for URB_*_HWORD messages. The range + of the calculated offset must fall within the range [0, 1023] or + behavior is undefined. + Range = [0, 2047] for URB_*_OWORD messages. The range + of the calculated offset must fall within the range [0, 2047] or + behavior is undefined. + 31:16 + M0.2 : GS Number of Output Vertices for Slot 1. Indicates the number + of vertices output for geometry shader slot 1 primitive. This + field is only defined if end-of-thread is set on the message. It is + ignored for all messages from non-GS threads. + Format = U16 + + 15:0 : GS Number of Output Vertices for Slot 0. Indicates the number + of vertices output for geometry shader slot 0 primitive. This + field is only defined if end-of-thread is set on the message. It is + ignored for all messages from non-GS threads. + Format = U16 + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 22 + DWord Bits Description + M0.1 31:16 + : Handle ID 1. This ID is assigned by the fixed function unit and + links the work in channel 1 to a specific entry within the fixed + function unit. This field is ignored unless Swizzle Control + indicates Interleave mode. + 15:0 + URB Handle 1. This is the URB handle where channel 1’s + results are to be written or read. This field is ignored unless + Swizzle Control indicates interleave mode. + + M0.0 31:16 + Handle ID 0. This ID is assigned by the fixed function unit and + links the work in channel 0 to a specific entry within the fixed + function unit. + 15:0 + URB Handle 0. This is the URB handle where channel 0’s + results are to be written or read. + + +2.4.3.2 URB_WRITE_HWORD Write Data Payload +For the URB_WRITE_HWORD messages, the message payload will be written to the URB entries +indicated by the URB return handles in the message header. + Payload Usage +URB_NOSWIZZLE + The message payload contains data to be written to a single URB entry (e.g., + one Vertex URB entry). The Swizzle Control field of the message descriptor must + be set to ‘NoSwizzle’. +URB_INTERLEAVED + The message payload contains data to be written to two separate URB entries. + The payload data is provided in a high/low interleaved fashion. The Swizzle + Control field of the message descriptor must be set to ‘Interleave’. + + +2.4.3.2.1 URB_NOSWIZZLE +URB_NOSWIZZLE is used to simply write data into consecutive URB locations (no data swizzling +applied). +Programming Notes: + +  The URB function will use (not ignore) the Channel Enables associated with this message. + +When URB_NOSWIZZLE is used to write vertex data, the following table shows an example layout of a +URB_NOSWIZZLE payload containing one (non-interleaved) vertex containing n pairs of 4-DWord vertex +elements (where for the example, n is >2). +DWord Bit Description + M1.7 31:0 + Vertex Data [7] + + M1.6 31:0 + Vertex Data [6] + + M1.5 31:0 + Vertex Data [5] + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 23 + DWord Bit Description + M1.4 31:0 + Vertex Data [4] + +M1.3 31:0 + Vertex Data [3] + +M1.2 31:0 + Vertex Data [2] + +M1.1 31:0 + Vertex Data [1] + +M1.0 31:0 + Vertex Data [0] + +M2.7 31:0 + Vertex Data [15] + +M2.6 31:0 + Vertex Data [14] + +M2.5 31:0 + Vertex Data [13] + +M2.4 31:0 + Vertex Data [12] + +M2.3 31:0 + Vertex Data [11] + +M2.2 31:0 + Vertex Data [10] + +M2.1 31:0 + Vertex Data [9] + +M2.0 31:0 + Vertex Data [8] + + … + … + +Mn.7 31:0 + Vertex Data [8(n-1)+7] + +Mn.6 31:0 + Vertex Data [8(n-1)+6] + +Mn.5 31:0 + Vertex Data [8(n-1)+5] + +Mn.4 31:0 + Vertex Data [8(n-1)+4] + +Mn.3 31:0 + Vertex Data [8(n-1)+3] + +Mn.2 31:0 + Vertex Data [8(n-1)+2] + +Mn.1 31:0 + Vertex Data [8(n-1)+1] + +Mn.0 31:0 + Vertex Data [8(n-1)+0] + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 24 + 2.4.3.2.2 URB_INTERLEAVED +The following table shows an example layout of a URB_INTERLEAVED payload containing two +interleaved vertices, each containing n 4-DWord vertex elements (n>1). +Programming Restrictions: + +  The URB function will use (not ignore) the Channel Enables associated with this message. +  Writes to overlapping addresses of vertex0 and vertex1 will have undefined write ordering. +DWord Bit Description + M1.7 31:0 + Vertex 1 Data [3] + + M1.6 31:0 + Vertex 1 Data [2] + + M1.5 31:0 + Vertex 1 Data [1] + + M1.4 31:0 + Vertex 1 Data [0] + + M1.3 31:0 + Vertex 0 Data [3] + + M1.2 31:0 + Vertex 0 Data [2] + + M1.1 31:0 + Vertex 0 Data [1] + + M1.0 31:0 + Vertex 0 Data [0] + + M2.7 31:0 + Vertex 1 Data [7] + + M2.6 31:0 + Vertex 1 Data [6] + + M2.5 31:0 + Vertex 1 Data [5] + + M2.4 31:0 + Vertex 1 Data [4] + + M2.3 31:0 + Vertex 0 Data [7] + + M2.2 31:0 + Vertex 0 Data [6] + + M2.1 31:0 + Vertex 0 Data [5] + + M2.0 31:0 + Vertex 0 Data [4] + + … + … + + Mn.7 31:0 + Vertex 1 Data [4(n-1)+3] + + Mn.6 31:0 + Vertex 1 Data [4(n-1)+2] + + Mn.5 31:0 + Vertex 1 Data [4(n-1)+1] + + Mn.4 31:0 + Vertex 1 Data [4(n-1)+0] + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 25 + DWord Bit Description + Mn.3 31:0 + Vertex 0 Data [4(n-1)+3] + + Mn.2 31:0 + Vertex 0 Data [4(n-1)+2] + + Mn.1 31:0 + Vertex 0 Data [4(n-1)+1] + + Mn.0 31:0 + Vertex 0 Data [4(n-1)+0] + + + +2.4.3.3 URB_READ_HWORD Writeback Message +For the URB_READ_HWORD messages, the URB entries indicated by the URB handles in the message +header are read and returned in the writeback message. The amount of read data returned is determined +by the Response Length field. +While GS threads will read one vertex at a time to the URB, the VS will read two interleaved vertices. The +description of the URB read messages will refer to the per-vertex DWords described in the Vertex URB +Entry Formats section of the 3D Overview chapter. + Payload Usage +URB_NOSWIZZLE + The writeback message contains data read from a single URB entry (e.g., one + Vertex URB entry). The Swizzle Control field of the message descriptor must be + set to ‘NoSwizzle’. +URB_INTERLEAVED + The writeback message contains data read from two separate URB entries. The + data is provided in a high/low interleaved fashion. The Swizzle Control field of the + message descriptor must be set to ‘Interleave’. + + +2.4.3.3.1 URB_NOSWIZZLE +URB_NOSWIZZLE is used to simply read data into consecutive URB locations (no data interleaving +applied). +When URB_NOSWIZZLE is used to read vertex data, the following table shows an example layout of a +URB_NOSWIZZLE writeback message containing one (non-interleaved) vertex containing n pairs of 4- +DWord vertex elements (where for the example, n is >2). +DWord Bit Description + W0.7 31:0 + Vertex Data [7] + +W0.6 31:0 + Vertex Data [6] + +W0.5 31:0 + Vertex Data [5] + +W0.4 31:0 + Vertex Data [4] + +W0.3 31:0 + Vertex Data [3] + +W0.2 31:0 + Vertex Data [2] + +W0.1 31:0 + Vertex Data [1] + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 26 + DWord Bit Description + W0.0 31:0 + Vertex Data [0] + +W1.7 31:0 + Vertex Data [15] + +W1.6 31:0 + Vertex Data [14] + +W1.5 31:0 + Vertex Data [13] + +W1.4 31:0 + Vertex Data [12] + +W1.3 31:0 + Vertex Data [11] + +W1.2 31:0 + Vertex Data [10] + +W1.1 31:0 + Vertex Data [9] + +W1.0 31:0 + Vertex Data [8] + + … + … + +Wn.7 31:0 + Vertex Data [8n+7] + +Wn.6 31:0 + Vertex Data [8n+6] + +Wn.5 31:0 + Vertex Data [8n+5] + +Wn.4 31:0 + Vertex Data [8n+4] + +Wn.3 31:0 + Vertex Data [8n+3] + +Wn.2 31:0 + Vertex Data [8n+2] + +Wn.1 31:0 + Vertex Data [8n+1] + +Wn.0 31:0 + Vertex Data [8n+0] + + +2.4.3.3.2 URB_INTERLEAVED +The following table shows an example layout of a URB_INTERLEAVED payload containing two +interleaved vertices, each containing n 4-DWord vertex elements (n>1). +DWord Bit Description + W0.7 31:0 + Vertex 1 Data [3] + +W0.6 31:0 + Vertex 1 Data [2] + +W0.5 31:0 + Vertex 1 Data [1] + +W0.4 31:0 + Vertex 1 Data [0] + +W0.3 31:0 + Vertex 0 Data [3] + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 27 + DWord Bit Description + W0.2 31:0 + Vertex 0 Data [2] + +W0.1 31:0 + Vertex 0 Data [1] + +W0.0 31:0 + Vertex 0 Data [0] + +W1.7 31:0 + Vertex 1 Data [7] + +W1.6 31:0 + Vertex 1 Data [6] + +W1.5 31:0 + Vertex 1 Data [5] + +W1.4 31:0 + Vertex 1 Data [4] + +W1.3 31:0 + Vertex 0 Data [7] + +W1.2 31:0 + Vertex 0 Data [6] + +W1.1 31:0 + Vertex 0 Data [5] + +W1.0 31:0 + Vertex 0 Data [4] + + … + … + +Wn.7 31:0 + Vertex 1 Data [4n+3] + +Wn.6 31:0 + Vertex 1 Data [4n+2] + +Wn.5 31:0 + Vertex 1 Data [4n+1] + +Wn.4 31:0 + Vertex 1 Data [4n+0] + +Wn.3 31:0 + Vertex 0 Data [4n+3] + +Wn.2 31:0 + Vertex 0 Data [4n+2] + +Wn.1 31:0 + Vertex 0 Data [4n+1] + +Wn.0 31:0 + Vertex 0 Data [4n+0] + + + +2.4.3.4 URB_WRITE_OWORD Write Data Payload +For the URB_WRITE_OWORD messages, the message payload will be written to the URB entries +indicated by the URB return handles in the message header. + Payload Usage +URB_NOSWIZZLE + The message payload contains data to be written to a single URB entry (e.g., + one Vertex URB entry). The Swizzle Control field of the message descriptor must + be set to ‘NoSwizzle’. +URB_INTERLEAVED + The message payload contains data to be written to two separate URB entries. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 28 + Payload Usage + The payload data is provided in a high/low interleaved fashion. The Swizzle + Control field of the message descriptor must be set to ‘Interleave’. + + +2.4.3.4.1 URB_NOSWIZZLE +URB_NOSWIZZLE is used to simply write data into a single 128-bit URB location (no data swizzling +applied). +Programming Notes: + +  The URB function will use (not ignore) the Channel Enables associated with this message. + +When URB_NOSWIZZLE is used to write vertex data, the following table shows an example layout of a +URB_NOSWIZZLE payload containing one (non-interleaved) vertex containing 4-DWord vertex elements +and HIGH OWORD ENABLE is 0. +DWord Bit Description + M1.7 31:0 Ignored + M1.6 31:0 Ignored + M1.5 31:0 Ignored + M1.4 31:0 Ignored + M1.3 31:0 + Vertex 0 Data [3] + + M1.2 31:0 + Vertex 0 Data [2] + + M1.1 31:0 + Vertex 0 Data [1] + + M1.0 31:0 + Vertex 0 Data [0] + +When URB_NOSWIZZLE is used to write vertex data, the following table shows an example layout of a +URB_NOSWIZZLE payload containing one (non-interleaved) vertex containing 4-DWord vertex elements +and HIGH OWORD ENABLE is 1. +DWord Bit Description + M1.7 31:0 + Vertex 0 Data [3] + + M1.6 31:0 + Vertex 0 Data [2] + + M1.5 31:0 + Vertex 0 Data [1] + + M1.4 31:0 + Vertex 0 Data [0] + + M1.3 31:0 Ignored + M1.2 31:0 Ignored + M1.1 31:0 Ignored + M1.0 31:0 Ignored + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 29 + 2.4.3.4.2 URB_INTERLEAVED +The following table shows an example layout of a URB_INTERLEAVED payload containing two +interleaved vertices, each containing 4-DWord vertex elements. +Programming Restrictions: + +  The URB function will use (not ignore) the Channel Enables associated with this message. +  Writes to overlapping addresses of vertex0 and vertex1 will have undefined write ordering. +DWord Bit Description + M1.7 31:0 + Vertex 1 Data [3] + + M1.6 31:0 + Vertex 1 Data [2] + + M1.5 31:0 + Vertex 1 Data [1] + + M1.4 31:0 + Vertex 1 Data [0] + + M1.3 31:0 + Vertex 0 Data [3] + + M1.2 31:0 + Vertex 0 Data [2] + + M1.1 31:0 + Vertex 0 Data [1] + + M1.0 31:0 + Vertex 0 Data [0] + + + +2.4.3.5 URB_READ_OWORD Writeback Message +For the URB_READ_HWORD messages, the URB entries indicated by the URB handles in the message +header are read and returned in the writeback message. The amount of read data returned is determined +by the Response Length field. +Programming Restrictions: + +  Response Length must be set to 1. + +While GS threads will read one vertex at a time to the URB, the VS will read two interleaved vertices. The +description of the URB read messages will refer to the per-vertex DWords described in the Vertex URB +Entry Formats section of the 3D Overview chapter. + Payload Usage +URB_NOSWIZZLE + The writeback message contains data read from a single URB entry (e.g., one + Vertex URB entry). The Swizzle Control field of the message descriptor must be + set to ‘NoSwizzle’. +URB_INTERLEAVED + The writeback message contains data read from two separate URB entries. The + data is provided in a high/low interleaved fashion. The Swizzle Control field of the + message descriptor must be set to ‘Interleave’. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 30 + 2.4.3.5.1 URB_NOSWIZZLE +URB_NOSWIZZLE is used to simply read data into consecutive URB locations (no data interleaving +applied). +When URB_NOSWIZZLE is used to read vertex data, the following table shows an example layout of a +URB_NOSWIZZLE writeback message containing one (non-interleaved) vertex containing 4-DWord +vertex elements and HIGH OWORD ENABLE is 0. +DWord Bit Description + W0.7 31:0 Reserved (not written to GRF) + W0.6 31:0 Reserved (not written to GRF) + W0.5 31:0 Reserved (not written to GRF) + W0.4 31:0 Reserved (not written to GRF) + W0.3 31:0 + Vertex Data [3] + +W0.2 31:0 + Vertex Data [2] + +W0.1 31:0 + Vertex Data [1] + +W0.0 31:0 + Vertex Data [0] + +When URB_NOSWIZZLE is used to read vertex data, the following table shows an example layout of a +URB_NOSWIZZLE writeback message containing one (non-interleaved) vertex containing 4-DWord +vertex elements and HIGH OWORD ENABLE is 1. +DWord Bit Description + W0.7 31:0 + Vertex Data [3] + +W0.6 31:0 + Vertex Data [2] + +W0.5 31:0 + Vertex Data [1] + +W0.4 31:0 + Vertex Data [0] + +W0.3 31:0 Reserved (not written to GRF) +W0.2 31:0 Reserved (not written to GRF) +W0.1 31:0 Reserved (not written to GRF) +W0.0 31:0 Reserved (not written to GRF) + + +2.4.3.5.2 URB_INTERLEAVED +The following table shows an example layout of a URB_INTERLEAVED payload containing two +interleaved vertices, each containing 4-DWord vertex elements. +DWord Bit Description + W0.7 31:0 + Vertex 1 Data [3] + +W0.6 31:0 + Vertex 1 Data [2] + +W0.5 31:0 + Vertex 1 Data [1] + +W0.4 31:0 + Vertex 1 Data [0] + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 31 + DWord Bit Description + W0.3 31:0 + Vertex 0 Data [3] + +W0.2 31:0 + Vertex 0 Data [2] + +W0.1 31:0 + Vertex 0 Data [1] + +W0.0 31:0 + Vertex 0 Data [0] + + + +2.4.4 URB_ATOMIC* +The URB_ATOMIC messages implement atomic operations on a single DWord in the URB. The location +of the DWord within the URB is specified by the single URB handle and the Global Offset field in the +message descriptor, which for these messages is a DWord offset from the URB handle. The DWord +selected will be operated on according to the following table: + +URB Opcode new_dst ret +URB_ATOMIC_MOV + src0 none + +URB_ATOMIC_INC + old_dst + 1 old_dst + + + +The previous contents of the DWord are returned in the destination register for the URB_ATOMIC_INC. +The URB_ATOMIC_MOV opcode does not return data (response length must be zero). +The URB_ATOMIC* messages consist only of the header. A single URB handle is specified. + +2.4.4.1 Message Header +DWord Bit Description + M0.7 31:0 + M0.6 31:0 + M0.5 31:0 Ignored + M0.4 31:0 Ignored + M0.3 31:0 Ignored + M0.2 31:0 + Source0 Data + + Specifies the source 0 data for the atomic operation. This field is ignored for the + URB_ATOMIC_INC message. + Format = U32 + M0.1 31:0 Ignored + M0.0 31:16 Ignored + 15:0 + URB Handle. This specifies the URB handle to be accessed. + + + +2.4.4.2 Writeback Message +A writeback message is only returned for the URB_ATOMIC_INC message. Only the low 32 bits of the +destination GRF register are overwritten with the return data. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 32 + DWord Bit Description +W0.7:1 Reserved (not written to GRF) + W0.0 31:0 + Return Data + + Specifies the value of the return data for the atomic operation. + Format = U32 + +Here is a description of the 3DMark11 usage model (from their func spec): +4.4.1 Depth of Field +The effect is computed using the following procedure: +1. Circle of confusion radius is computed for all screen pixels and stored in a full resolution +DXGI_FORMAT_R16_FLOAT texture. +2. Half and quarter resolution versions are made from the radius texture and the original illumination texture. +3. Positions of out-of-focus pixels whose circle of confusion radius exceeds a predefined threshold are appended to +a buffer. +4. The position buffer is used as point primitive vertex data and, utilizing Geometry Shader (GS), image of hexagon- +shaped bokeh is splatted to positions of these vertices. Splatting is done to a +DXGI_FORMAT_R16G16B16A16_FLOAT texture. Multiple viewports are used to partition the texture to regions with +different sizes. First region is screen size and the rest are a series of halved regions down to size 1x1 texels. The +radius of the splatted bokeh determines the used viewport. The larger the radius the smaller the used viewport. +5. Steps 3 and 4 are done separately for full, half, and quarter resolution image data with different radius thresholds. +Larger bokehs are generated from lower resolution image data. +6. The different regions of the splatting texture are combined by up-scaling the data in the smaller regions to the +screen size region. +7. The combined splatted out-of-focus illumination is combined with the original illumination. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 33 + 3. Shared Functions – Video Motion + Estimation +The Video Motion Estimation (VME) engine is a shared function that provides motion estimation services. +It includes motion estimation for various block sizes and also standard specific operations such as + +  Motion estimation and mode decision for AVC +  Intra prediction and mode decision for AVC +  Motion estimation and mode decision for MPEG2 +  Motion estimation and mode decision for VC1 + +The motion estimation engine may also be used for other coding standards or other video processing +applications. + + +3.1 Theory of Operation +VME performs a sequence of operations to find the best mode for a given macroblock. Each operation +step can be enabled/disabled through the control of the income message. Early termination, skipping of +subsequent operation steps, is also supported when certain search criteria are met. +VME contains the following operation steps: + 1. Skip check + 2. IME: Integer motion estimation + 3. FME: Fractional motion estimation + 4. BME: Bidirectional motion estimation + 5. IPE: Intra prediction estimation (AVC only) + + +3.1.1 Shape Decision +As a terminology, we call sub-block shapes: 8x4, 4x8, and 4x4 minor shapes (corresponding to sub- +partitions of 8x8 sub-macroblock), and 16x16, 16x8, 8x16, and 8x8 major shapes (corresponding to sub- +macroblocks of a 16x16 macroblock). +If the maximal allowed number of motion vectors MaxNumMVs (MaxNumMVs = +MaxNumMVsMinusOne + 1) is less than 4, we will set minor MV flag off: MinorMVsFlag = 0, i.e. no +minor motion vectors will be generated. +The reason of having this parameter MaxNumMVs is due to high level AVC conformance restrictions for +certain profiles: the total number of motion vectors of any two consecutive macroblocks not exceeding 16 (or 32) . +The mechanism here allows a reasonable degree of user control. In disable cases, MaxNumMVs should +be set to 32. +In the coding process of VME, the shape decision is done in multiple locations: + 1) After IME and before FME, intermediate shape decision is performed to reduce the FME searching + candidates + 2) After FME and before BME, existing shape decision is revised among the remaining candidates and + to see if there is further reduction. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 34 + 3) Final shape decision is done after BME. +Partition decision before BME uses unidirectional motion vector count to meet MaxNumMVs requirement. +Adding BME for the partition candidates may exceed MaxNumMVs. As BME is performed on a block by +block basis using the block order for a given partition, BME step for a given block is skipped and the best +unidirectional motion vectors are used for the block if the overall motion vector count exceeds +MaxNumMVs when that particular block is switched to bidirectional. The process continues to the last +block of the partition. +Note: This is a sub-optimal solution to simplify the hardware implementation. For some cases, +bidirectional modes with larger sub-partitions might be better than unidirectional modes with finer sub- +partitions. +The VME implementation has the following restriction: Multiple partition candidates are only enabled if +PartCandidateEn is set. And this only applies to source block of size 16x16. +If PartCandidateEn is not set, only the best partition is kept in state 1 (after IME) above and carried +through FME and BME. In other words, FME if enabled only operates on one partition candidate, and +BME if enabled only operates on one partition candidate. Bidirectional mode check only applies to the +partition candidates that meet the bidirectional restriction provided by BiSubMbPartMask. For example, if +a minor partition determined based on best unidirectional cost function is not 8x8 but one of 4x8, 8x4 or +4x4, VME skips the bidirectional mode check. +If PartCandidateEn is set, up to two sets of candidates are maintained by VME hardware, if the second +best partition candidate is within PartToleranceThrhd from the best one. The second best partition is +selected only from the two major partition candidates based on the unidirectional motion vector count, +subject to that the major partition is enabled: + +  1MV: The 16x16 partition +  4MV: The 4x(8x8) partition with no minor shape + +The following partitions are not supported as alternative partition. + +  2MV: The best of 2x(16x8) and 2x(8x16) partitions +  More than 4MV: The best of all 4x(8x8) partitions with at least one 8x8 having minor shape of 8x4, + 4x8 or 4x4 + +3.1.1.1 Minor Shape Decision Prior to FME +If any minor shapes are selected, we decide the best minor first. +For each 8x8 sub-block, before performing bidirectional, we reduce code candidates to no more than +three based on the best unidirectional motion search results (best of the forward and backward): + 0) One MV, i.e. the best in shape of 8x8. + 1) Up to two MVs, i.e. the best in shapes 8x8, 8x4, or 4x8. And + 2) Up to four MVs, i.e. the best for the sub-block 8x8. +Now for the first and the second sub-blocks, we can merge them into up to six candidates of 2, 3, 4, 5, 6, +and 8 possible motion vectors. +Do the same to the third and the fourth sub-blocks, we have similarly up to six candidates. +Now we further combine these two groups, and find the best solution under the constraint of not +exceeding the number of motion vectors more than MaxNumMVs. (see pseudo-code below for detail.) + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 35 + Consequently, we have the best combined 8x8 solutions with N motion vectors for some N less or equal +to MaxNumMVs. +Assume distA[k][s] is the cost-adjusted distortion of the best forward or backward motion vector mix of +the k-th 8x8 sub-block of the sub-shape s, where s=0,1,2, and 3 represent shape partitioning 8x8, 8x4, +4x8, and 4x4 respectively. Assume distA[k][s] is the bidirectional one of the corresponding bus-block +and sub-shape. And assume some large number, say 128x16=2048 is assigned to the variable, if there +were no valid corresponding codes. Hence, the following pseudo-code explains the code selection +algorithm. +Let’s first explain the case MaxNumMVs is disbled, i.e.MaxNumMVs16: +void SelectBestCombinedMinors( +short *distA, +short*MinorShape, +short*MinorDisto +){ +shorts[4], d[4]; + s = ShapeList; + d = DistoList; + for(int k=0;k<4;k++){ +s[k] = 0;d[k] = distA[k][0]; +if(distA[k][1])=16){ // it should use unrestricted code selection +SelectBestCombinedMinors(DistA,MinorShape,MinorDisto); +return; + } +short*s, ShapeList[18]; +short*d, DistoList[18]; + s = ShapeList; + d = DistoList; + for(k=0;k<4;k++){ +s[0] = 0;// 1 mv +d[0] = distA[k][0]; +s[4] = (distA[k][2]d[ 4]) d[ 6] = d[ 4]; +if(d[ 8]>d[ 6]) d[ 8] = d[ 6]; +if(d[10]>d[ 8]) d[10] = d[ 8]; +if(d[12]>d[10]) d[12] = d[10]; +d[14] = d[12]; +if(d[16]>d[12]) d[16] = d[12]; +s ++; d ++; + } + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 37 + s = ShapeList; + d = DistoList; +*MinorDisto = 2048; + for(k=0;k<8;k++){ +n = MaxNumMVs – k; +if(n>=2 && n<=8)<2){ +dist = d[(k<<1)+1]+d[n<<1]; +if(dist<*MinorDisto){ +*MinorDisto = dist; +best0 = (n<<1); +best1 = (k<<1)+1; +} +} + } + while(best0>1 && d[best0]==d[best0-2]) best0 -= 2; + while(best1>1 && d[best1]==d[best1-2]) best1 -= 2; + *MinorShape = s[best0]|((s[best1]<<2); +} + + +3.1.1.2 Major Shape Decision Prior to FME +Now considering the best of each 8x8 is done, and we have the total cost-adjusted-distortion for this sub- +block level partition. Now among the four choices: the resulting 8x8 sub-partitioning, one 16x16, two +16x8, and two 8x16, the one gives the best cost-adjusted-distortion, will determine the final decision of +partitioning shape. Any among these four, if its cost-adjusted-distortion is within the intermediate +tolerance (which is a predefined system state) from the best distortion will be marked as candidate +shapes. +Notice that, when the intermediate tolerance is set to 0, only the best shape will be selected as the +candidate. When the intermediate tolerance is large, all four shapes will become candidates. +Assume we have all the distortions for majors enumerated in DistoMajor[k], where k = 0, 1, 2, 3, 4, and +5, for 16x16, 16x8, 8x16, the combined minors, 16x8 field, and 8x8 field respectively. Assume BestDisto +is equal to the minimal of the six values DistoMajor[k], for k = 0, …5. Assume the intermediate +tolerance is IntTol, the major shape k is a candidate shape if and only if +DistoMajor[k]<=BestDisto+IntTol. + +3.1.1.3 Shape Update after FME +Among all the candidate shapes, we recheck the distortion, if any of them is no longer with in the +intermediate tolerance DistortionTolerance from the best choice; we drop it for reduced calculation. + +3.1.1.4 Final Code Decision after BME +For any given candidate shape, for each motion vector, if we do have improved distortion by switch from +the single direction to bi-direction, then we do it, unless the increased number of motion vectors hits +above MaxNumMVs; in this case, we take as many as possible first the ones generate the most +improvement. +Then, we choose the best among the improved candidate shapes. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 38 + 3.1.2 Integer Motion Estimation +IME, the integer motion estimation, is the most key part of VME. In our current design, the minimal +functional block is to do a full search over a search unit. This functional block is then called via two +distinctive methods: +1) Via a predefined searching path of search units. +2) Via a dynamic process based on the previous results. +This section will describe both. + +3.1.2.1 Reference Window and Search Units +The reference window is a rectangular region fetched put in the reference cache for VME. Either one or +two reference windows are allowed to be loaded into the reference cache. In the case of dual windows, +both windows follow a common search path or different paths (relative to their corresponding Start +Center) depending on the dual search path option flag. +The total reference cache is limited to 2K bytes and only the luma component searching is performed. For +example, we may select the reference windows to be one of the following sample choices: one 64x32 +area, one 48x40 area, two 40x24 areas, or two 32x32 areas, where the possible reference address will +cover an area of 48x16, 32x24, 24x8, and 16x16. +As a convention, we will call the valid reference addressing region the reference region, and its width and +height are called the reference window width and height respectively. So the reference loading region of +VME has therefore 16 more columns and 16 more rows. +It is not efficient for hardware to search one location at a time due to reference cache access bandwidth and +latency constraints. Thus, possible reference search locations are grouped in a predefined pattern, and all +locations within the same group must be either all are chosen or all are skipped. These predefined groups +are called search unit (SU). Reference Window and Search Units shows a sample of grouping search locations +into searching units. The reference window in the figure has a dimension of 32x20, and assuming the +source block is 8x8, the dark dots indicate all legitimate reference locations for motion searching. It shows +a partitioning of SUs of 16 locations. +In general, the indices of SUs are given by counting rows and units within the row. + + + + +Example of Search Units in a reference window +Given a fixed reference cache access latency, SU size is determined solely based on the source block +size as shown in Reference Window and Search Units. Note that SU sizes for both 16x8 and 8x16 source +blocks are both 8x4, which gives a preference for motions along horizontal direction. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 39 + Determination of Search Unit size based on Source Block dimension + Source Block Dimension Search Unit (SU) Size (X x Y) GT Support + 16x16 4x4 Y + 16x8 8x4 Y + 8x16 8x4 N + 8x8 8x8 Y + +To keep tracking on whether a SU has been searched or not, an equivalent hardware process is +implemented performing as a search record that marks whether any search units being searched is a bit- +plan of the bit-length equal to the maximal index of SUs. Before searching starts, the search record must +be reset which sets the value 0 (= yet-to-be-searched) to all legitimate SU indices, and the value 1 (= no +longer available) for other SUs that are not intended to be searched. +Given a search window, unique indices are assigned to all SUs. A search path (SP), is a sequence of such +indices. The number of SUs in a SP is called the length of the walker (denoted by LenSP here), which shall be +a number more than one. Instead of storing the absolute indices of a search path, relative search unit deltas +are sent instead. In the current VME a search unit delta is a 8 bit index consisting of a pair of 4-bit signed +integers in [-8,8). + +Given start center in a pair of 4-bit unsigned integer (sx, sy), and denote a search path described in SU deltas +(dx[i],dy[i]). The first search unit SU[0] will be the search unit which has the first reference address (sx*4, +sy*4) in integer-pel relative to the reference origin., i.e. + +SU[0].x = sx*4, and SU[0].y = sy*4. + +The second search unit SU[1] is derived by adding (dx[0],dy[0]): + +SU[1].x = SU[0].x + dx[0]*4, and SU[1].y = SU[0].y + dy[0]*4. +In general, we have: +SU[i+1].x = SU[i].x + dx[i]*4, and SU[i+1].y = SU[i].y + dy[i]*4. + +When SU[i] is out of range, it is either always skipped or always wrapped depending on the SU wrapping flag. +When the SU wrapping flag is on, it is equivalent to as we perform +SU[i].x = SU[i].x(mod ref_win_width), and + +SU[i].y = SU[i].y(mod ref_win_height), +As a convention, a NULL delta marks the end of the search path. + +3.1.2.2 Fixed and Adaptive Search Paths +A fixed pattern motion search algorithm is an algorithm following some predefined SP with the designated +MaxNumSU (maximal number of search units) less or equal to LenSP (the fixed search path length). This is +referred to as fixed pattern searching or predetermined searching. +When MaxNumSU > LenSP, (the maximal number of SU is more than what are given by the SP), the +searching continues unless reaching a local minimum, which is called dynamic searching or adaptive +searching or gradient searching. In this case, the current best result is used. If it is located in some SU +boundary, the neighborhood SUs are checked and any one of them that is yet-to-be-searched will be the +next SU to be searched. If all neighbor SU’s are done, the process of IME is done. Fixed and Adaptive +Search paths illustrates on how neighbor SUs are defined for dynamic search. + +Hardware maintains one scoreboard per reference to keep track of the state of SUs, whether being +searched or yet-to-be-searched. When dual records are enabled on a single reference, both records will +share the same scoreboard for the reference. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 40 + Sample neighborhood SUs in a dynamic search + + +Fixed and Adaptive Search paths shows the algorithm of this integrated solution. In order to hide the decision +logic of dynamic walking, the one-step-delayed-queue is implemented. So when searching the current +SU, the next SU will be put in the queue. If there are more SUs yet to be searched in the current SP, the +next SU will be the next SU according to SP; if there is no more SU from SP, the first unsearched +neighbor SU (in some predefined order) based on the current best result will be put instead, and if there is +no more unsearched neighbor SU, the integer searching terminates. +To reduce the one-step-delay, and to support bidirectional, we create the dual mode that allows the +above algorithm to be ping-pong-ed between two search paths. Fixed and Adaptive Search paths illustrates +this case. +In both figures, the best MVs refer to the best resulting motion vectors so far. There are potentially total +41 motion vectors (1 for 16x16, 2 for 16x8, 2 for 8x16, 4 for 8x8, and 32 more for 8x4, 4x8 and 4x4 +cases). The current hardware implementation only considers the four 8x8 MVs. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 41 + VME in single SP mode + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 42 + VME in Dual SP mode + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 43 + 3.1.3 Fractional Motion Estimation +Instead of following the exact interpolation as specified by the individual video standards, 4 tap +interpolation is used for the Fractional Motion Estimation (FME) step in the VME engine. It is expected to +be adjusted according to different standards. + +3.1.3.1 Interpolations +Instead of following the exact interpolation as specified by the individual video standards, fixed 4 tap +interpolation is used in the VME engine, as defined below: +1) (-1,5,5,-1)/8 for ½-pel, i.e. s = (P1+P2*5+P3*5P4+4)/8 and + +2) (-1,13,5,-1)/16 for ¼-pel position, i.e. c = (P1+P2*13+P3*5P4+8)/16. + + + + +Fractional pixel locations +The quarter-pels are actually the averages of its nearest integer and half pixel values. +It is not hard to see our suggested interpolation formulas are very much the good approximations of the +formulas from various standards +For AVC, they should be the following 6-tap formulas in theory: +1) (1, -5,20,20,-5,1)/32 for ½-pel, i.e. s = ((P2+P3)*20(P1+P4)*5+(F0+F6), and +2) (1,-5,52,20-5,-1)/64 for ¼-pel position.. n. +For VC-1, the 4-tap filters are precisely defined: +1) (-1,9,9,-1)/16 for ½-pel, and +2) (-4,53,18,-3)/64 for ¼-pel position. +In general, bilinear interpolation is accepted too: +3) (0,1,1,0)/2 for ½-pel (as used in MPEG2), and +4) (0,3,1,0)/4 for ¼-pel position. +After IME is done, if the best Inter result is too bad, we may decide to stop the Inter-search to not waste +the effort further computationally. If we decided to continue, we have the option to decide shape first to +cut down FME calculation or to perform FME for all possible configurations. +VME performs the sub-block level intermediate shape decision first (see Shape Decision section for detail), +then perform FME only for the reduced candidate shapes. In this way, the computation is reduced +significantly with tunable small quality hit. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 44 + 3.1.3.2 8+8 vs. 7x7 +With a given sub-block of motion vector search, we also have multiple options to pursue the searching. +Name two common extremes: 7x7 and 8+8. +Given an integer motion vector location, surrounding it there are 48 surrounding quarter-pel locations, and +among them there are 8 are in half-pel grids. So we may check all 48, which covers the 7x7 region, for +the best, or we may adopt a two-step approach by considering the half-pel grids first then followed by the +second step of the quarter-pel refinement. +The one step method is named as 7x7, and the two step method called 8+8 as only 16 block comparisons +are performed as shown in the next figure. +VME hardware follows the 8+8 approach. + + + + + 7x7 8+8 + + +7x7 vs. 8+8, whereas the 8+8 method is used by VME + +3.1.3.3 Partitioning Refinement +When the partitioning refinement is enabled, the FME refinement results will be propagated to or sub- +blocks as well, and a shape partitioning will be redone after the completion of both half-pel and quarter- +pel searching for a possible better choice. +In the case when alternative candidate is enabled, both half-pel refinements are done in parallel, and then +records are combined. Then, both quarter-pel refinements are done again in parallel, and combined again +prior to the final repartitioning. In HW implementation, we do the coarser on first, and the finer one later to +achieve the above equivalence. + + +3.1.4 BME and Weighted Prediction +Bidirectional searching is performed to all candidate shapes. +A weighted bidirectional search is supported particularly for AVC implicit weighted prediction. Only a +common subset of frame relations, which falls into linear interpolation with positive weight, is + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 45 + implemented. The weight between forward and backward is approximated into 5 cases only: 16 (quarter +distance like Rf B X X Rb), 21 (one third distance like Rf B X Rb), 32 (half distance like Rf B Rb), 43 (two +third distance like Rf X B Rb), and 48 (three quarter distance like RXXBR). Here the notation is for +bidirectional prediction with display picture order, whereas Rf stands for forward reference, Rb for +backward reference, B for the current bidirectional predicted picture and X is another picture in the +sequence. +So if the forward prediction is {Ref0[i]}, and the corresponding backward reference is {Ref1[i]}, then +the combined bidirectional motion prediction is calculated as the following: + Ref[i] = ((64-alpha)*Ref0[i] + alpha*Ref1[0] + 32)>>6; +where, alpha is one of the 5 weighting numbers mentioned above. + + +3.1.5 Skip Check +There are two SKIP modes: + +  SKIP_1MVP – one MV pair for 16x16 macroblock, and +  SKIP_4MVP – four MV pairs for four 8x8 subblocks. + +Otherwise, when Skip Check is enabled and the skip MV number does not exceed MaxMumMV, VME will +first perform the fractional motion estimation at the skip centers provided by the motion vector pairs as +specified by the corresponding mode. In this case the following distortions will be calculated: + 1. RawSkipDist – (intended for AVC PB_Skip) the raw SAD/HAAR distortion calculated from the + skip motion vectors with no costing added. + 2. NonSkipDist – (intended for AVC B_Direct16x16) the adjusted non-skip distortion is defined by + adding optionally the zero motion vector cost and 16x16 Inter mode penalty to RawSkipDist. + And + 3. NonSkip8x8Dist[4] – (intended for AVC B_Direct8x8) the four adjusted non-skip distortions for + four individual 8x8 subblocks with the ZMV cost and 8x8q Inter mode penalty optionally added. + (Note: This case may produce partitions with 8x8 subblock even if the 8x8 subblock shape is + disabled.) +“Optional” implies whether add or not is purely depende on two enabling input bits: NonSkipModeAdded +and NonSkipMvAdded. It should be also noted that MODE_INTER_BWD is not added to NonSkipDist +or NonSkip8x8Dist[] even though a skip center contains backward motion vector (this is for a direct +mode, whether the motion vector for a block is forward, backward or bidirection is derived from its spatial +or temporal predictor and there is no coding cost). +If RawSkipDist is less than or equal to EarlySkipSuccess threshold, MinDist will be set to RawSkipDist +if the skip MV number does not exceed MaxMumMV. + +  If EarlySuccessEn flag is on, VME exits immediately afer setting MbSkipFlag on, and + Direct8x8Pattern = Fh. +  If EarlySuccessEn flag is off, VME continue the IME, FME, BME, and Direct8x8 searching + after setting MbSkipFlag on and Direct8x8Pattern = Fh. VME will choose the skip output + unless another better choice of code with less adjusted distortion is found. + +If RawSkipDist is greater than EarlySkipThreshold, MinDist will be set to NonSkipDist if the skip MV +number does not exceed MaxMumMV. MbSkipFlag will be always set to off. VME continue the IME, +FME, BME, and Direct8x8 searchings. VME will still choose the skip output (with MbSkipFlag off) unless +another better choice of code with less adjusted distortion is found. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 46 + 3.1.5.1 Direct 8x8 Search +Direct8x8 Searching and then possible replacement is performed ONLY for 16x16 source block. +Direct8x8 Searching is performed only for Skip_4MVP mode when skip check is on to candidates of +MbType in a partition that is in the Inter shape of 8x8 or minors, after IME, FME, and BME searchings. +For each candidate in 8x8 or smaller partition, and for each 8x8 sub-block, the corresponding codes will +be replaced by the skip motion vector (pair) of the same 8x8 subblock, if all of the following requirements +are satisfied: + +  The non-skip 8x8 distortion NonSkip8x8Dist[k] is less than or equal to the adjusted 8x8 + distortion of the corresponding codes. +  The merge does not violate uni-mix and bi-mix rules (the violating cases are skipped). +  The number of MVs used for the cadidate adding the number of subblocks of the shape 8x8 + must be less than or equal to MaxNumMV. Or otherwise it does not replace a uni-directional + 8x8 MV with a true bi-directional skip MV pair. + +Note that, during all of the above comparisons, we skip the process whenever the MV numbers +exceeding the MaxNumMV. +If either UniMixDisable or BiMixDis is set, then there would be no direct8x8 block level replacement. + +3.1.5.2 Skip Check Only Mode +VME supports the skip check only mode, when Intra is set off, Inter and Skip are enabled, and all 7 inter +shapes (SubMbPartMask): 16x16, 16x8, 8x16, 8x8, 8x4, 4x8, and 4x4 are set to 1 (all sub partitions are +turned off). That indicates that none of the partition and sub partitions are valid for IME. Therefore IME is +not performed, and no subsequent FME/BME is performed. This is another performance optimization +choice if the intended usage is to check the skip centers only. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 47 + 3.1.6 Intra Prediction Estimation +Intra Prediction Estimation state supports all Intra16x16, Intra8x8, and Intra4x4 modes. All predictions are +based on original frame pixels for quick performance, as widely adopted in HW industry. There is a known +quality drop. +For supporting AVS as well as providing finer knobs for AVC, five enabling flags are defined: + +  Enable Intra16x16: whether Intra16x16 shall be performed. +  Enable Intra8x8: Enable all Intra8x8 modes, and the next flag determines which ones are actually + performed. +  AVS Intra8x8 Flag: whether should perform the subset of 5 AVS modes or perform the super set of 8 + AVC modes. +  Enable Intra4x4: Enable all Intra4x4 modes, and the next flag determines which ones are actually + performed. +  AVS Intra4x4 Flag: whether should perform the subset of 5 AVS modes or perform the super set of 8 + AVC modes. + + +3.1.7 Transform Adjusted SAD +A simple Wavelet transform, Haar transform, is used to refine the cost function measure of SAD. The per +pixel difference goes through a 4x4 Haar transform. Then the SAD is replaced by the sum of the absolute +values the transform domain coefficients (L1 norm) in the cost function. Haar transform here is used as a +coarse estimation of the integer transform. +Assume the a 4x4 block Blk is given in the following order: + 0 1 2 3 + 4 5 6 7 + 8 9 10 11 +12 13 14 15 + +The 4x4 Haar transform is performed using cascaded 2x2 Haar filters of the following steps: + +  Four 4-tap row filter +  Two 4-tap column filter +  Two 2-tap row filter +  Two 2-tap column filter + +Where the 2x2 Haar transform is give as + 1 1 + 1 -1 + + x00 x01 x02 x03 1 0 1 0 + x10 x11 x12 x13 1 0 -1 0 + x20 x21 x22 x23 0 1 0 1 + x30 x31 x32 x33 0 1 0 -1 + + 1 1 0 0 t00 t01 h08 h09 + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 48 + 0 0 1 1 t02 t03 h10 h11 + 1 -1 0 0 t04t05 h12 h13 + 0 0 1 -1 t06t07 h14 h15 + + t00 t01 1 1 + 1 -1 + t02 t03 + h04 h05 + h06 h07 + + 1 1 t00 h02 + 1 -1 + t01 h03 + + h00 + h01 + +This is equivalent to the following pseudo codes: +void Haar(short Blk4x4[16], short Haar4x4[16]) +{ + shortTmp[16]; + //First level 4-element horizontal Haar for 4 rows + For(int i=0;i<8;i++) { + Haar4x4[8+i] = (Blk4x4[i*2]-Blk4x4[i*2+1]); + // Storing LP 2x4 in scan order + Tmp[i] = (Blk4x4[i*2]+Blk4x4[i*2+1])); + } + //First level 4-element vertical Haar for 2 columns + Haar4x4[4] = (Tmp[0]-Tmp[2]); + Haar4x4[5] = (Tmp[1]-Tmp[3]); + Haar4x4[6] = (Tmp[4]-Tmp[6]); + Haar4x4[7] = (Tmp[5]-Tmp[7]); + Tmp[0] = (Tmp[0]+Tmp[2]); //Storing LP 2x2 in scan order + Tmp[1] = (Tmp[1]+Tmp[3]); + Tmp[2] = (Tmp[4]+Tmp[6]); + Tmp[3] = (Tmp[5]+Tmp[7]); + //Second level 2-element horizontal Haar for 2 columns + Haar4x4[3] = (Tmp[0]-Tmp[1]); + Haar4x4[2] = (Tmp[2]-Tmp[3]); + Tmp[0] = (Tmp[0]+Tmp[2]); //Storing LP 1x2 + Tmp[1] = (Tmp[1]+Tmp[3]); + //Second level 2-element vertical Haar + Haar4x4[1] = (Tmp[0]-Tmp[1]); + Haar4x4[0] = (Tmp[0]+Tmp[1]); +} +int AdjustedSAD(BYTE Src[16], BYTE Ref[16]){ + short diff[16], diffH[16]; + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 49 + for(int i=0;i<16;i++) diff[i] = r[i]-s[i]; + Haar(diff,diffH); + intasad = 0; + for(int i=0;i<16;i++) asad += (diff[i]<0?-diff[i]:diff[i]); + asad >>= (12-DISTBIT4X4); + return (asad); +} + +Thus instead of calculating the SAD of the actual pixel values, now we apply SAD to the after +transformation values. +As the Haar transform basis vectors have a magnitude of ½, instead of the normalized Haar of 1/sqrt(2), +the resulting transformed coefficients maintain the same bit precision as the input. Thus the sum tree has +the same precision as without the transform adjustment. However, this version of Haar transform has low +weightings on the DC and low AC terms, which may not be optimal as a motion-search cost function. + + +3.1.8 Early Decisions +There are 5 programmable early decision states are available for fine control of the VME process. All +stored in one byte of U4U4 format to representing a value of (B<>p, else if dx = 2p+k, for + any p<6 and k<.2p, and + Costing_penalty_x = min (LUT_MV[7] + int(dx)– 64, 255), else if dx > 64. + +The total costing penalty for a motion vector is + Costing_penalty = Costing_penalty_x + Costing_penalty_y +As a convention, a (0,0) relative search path distance (meaning a repeat search path location) is treated +as the ending of the search path. Or the search path may also end when Max Predetermined Search +Path Length is reached, or one of the Early Success conditions is reached. +Software must program the search path to terminate with at least one (0,0). + + +3.4 Change Details + +3.4.1 Record Stream-out and Stream-in + +3.4.1.1 Overview +VME internally keeps track of the best motion vectors for all shapes and sub-shapes, totaling 41 for each +record of the two records (forward and backward). Once IME is finished, each record is mined for the best +combination of shapes (i.e. the combination of the least distortion). The return message from VME to the +EU contains only the best shape combination and the remainder of the record is discarded. +For cases when the user wants to search beyond the VME window limits (64x32 for single reference, +32x32 for dual reference) the user must call VME multiple times. Since only partial information is returned +to the kernel, extracting the best shape combination across multiple calls is impossible. The best +workarounds require the kernel to limit the types of shapes VME is allowed to return and then the kernel +will manually merge shapes from multiple calls, cumbersome and suboptimal with respect to quality. +By returning more of the record to the kernel and allowing the kernel to feed in that information on +subsequent calls as initialization information, the process of searching beyond VME size limitations is +vastly improved. Now the merging of best shapes will occur inside VME and the global best shape +combination is more optimized. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 56 + If both records are returned in their entirety, this would require 16 additional message phases (each +shape requires 3 DWs, total of 82 shapes) for both input and output messages. A compromise to reduce +this burden yet still gain the bulk of the improvement is to stream-out only the best major shapes (9 +shapes, one 16x16, two 16x8, two 8x16, and four 8x8) for both records. This adds only 4 additional +message phases (when under search control == 111b, otherwise 2 additional phases) and carries the +most important shape data across multiple calls. + +3.4.1.2 Implementation Details +In essence this feature creates 2 types of records inside VME, a local and a global record. The local +record contains the best shapes within a single call to VME, i.e. the current call only. The global record is +carried via stream-in and stream-out, containing the best major shapes. +VME should only consider the local record during IME and FME, finding the local call’s optimal shapes +independent of the global record. For purposes of partitioning, the merging of the global record’s shapes +into the local record should occur after FME is finished on the current call and prior to repartitioning. +Otherwise local shapes identified during IME might not be considered for FME if the global shape was +superior to the IME result. +There is a new stage immediately following FME where the local record major shapes are compared to the +stream-in data, replacing the local record’s major shapes with the stream-in shape if it has a lower distortion. +Steps following this (repartitioning, BME, final mode decision) proceed like the previous generation. +As a part of the final stage, the stream-out record is generated simply taking the 9 major shapes out of +the local record (which was merged with local record earlier). +The merging of global and local motion vectors prior to BME could allow the winning shape combination +to not have all of its corresponding pixels in the SC (since the SC would only have local motion vector +pixels). Hence, a simple check is required prior to performing BME that ensures the motion vectors are +from the local call only, passing cases will perform BME and failing cases will not (test is applied on a per- +shape basis). +No native support within VME for multi-reference unidirectional surface mixing, the kernel can implement +a workaround if required, but there is no justification for such feature in the HW at this time. + + +3.4.2 MV Definitions and Precision + +3.4.2.1 Overview +Given that VME is trying to natively support larger search windows with stream-in, due to both necessity +and general improvements a number of input and output vectors (aka centers) must grow in precision. At +the same time, the points from which they are relative to are also being redefined. In most cases for the +previous generation (motion vectors, skip centers, cost centers) were defined relative to the reference +window origin, requiring the kernel to calculate the necessary offsets from the source MB location. Now +all vectors are defined relative to the source MB location (and the source MB is defined relative to the +picture origin). + +3.4.2.2 Implementation Details +The following diagrams provide details regarding the precision, range, and origin of all input (4 types), +output (1 type), and internal vectors (first shown all together, then individually). Many vectors are +composed from input or other internal vectors (via addition or subtract) and those equations are present. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 57 + 3.4.3 Expanded MV Costs + +3.4.3.1 Overview +Given that VME will be searching larger areas with the Record Stream-out feature, it is also necessary +that we revisit our MV costing methodology. Given this is calculated in terms of quarter-pel units, this +allows the user to provide variable costing penalty for a maximum distance of 16 pixels away from the +cost center. +We would like to expand this range by implementing a variable scaling factor (i.e. right shift, binary divide) of +the MV distance prior to comparison to the user-defined intervals (where VME previously looked at the lsbs +only). This will be provided to VME as a 2 bit value, specifying the shift amount (0: qpel, 1: hpel, 2: +single-pel, 3: two-pel). For instance, if the user a selects the MV cost scaling to be “3”, this expands the +maximum MV costing interval to a distance of 128 pixels. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 58 + 3.4.4 Remove Skip MV Restriction + +3.4.4.1 Overview +We will remove this restriction and allow the 8 skip centers to be located anywhere within the legal AVC +motion vector definitions (“Horizontal motion vector range does not exceed the range of -2048 to 2047.75, +inclusive, in units of luma samples.” And “Vertical MV component range MaxVmvR (luma frame samples) = [-512, ++511.75]”). + +This restriction was originally imposed to reduce the complexity and cost of the hardware for processing +skips and directs require pixels beyond that of the reference window used for IME, FME and BME. + +3.4.4.2 Implementation Details +Skips must still be associated with the same surface state as their corresponding reference window (4 +skip centers are for ref0, 4 are for ref1). +Skip centers are still bound as pairs. Hence, if the fwd x-component was 0xff, that meant this skip center +pair was unidirectional and only in the bwd direction. If neither x-component are 0xff, then this is a +bidirectional pair. +However, mv.x = 0xff is now a legal motion vector value and thus we cannot overload this field to control the +skip center pair’s type.We will incorporate a new 8b field, “Skip Center Enables” (M1-DW7-31:24), to +control which of the 8 skip center pairs is valid. At least 1 of the skip centers for each pair must be valid +when in 4MVP mode (in 1MVP mode only 1 of the skip centers for the 1st pair must be valid). + + +3.4.5 Bilinear Interpolation + +3.4.5.1 Overview +Since MPEG2 only allows for half-pel interpolation, implementation of this bilinear filter is required only for +half-pel mode. However, if there are no HW concerns implementing bilinear for quarter-pel also, please +go ahead as there could be users who prefer it over our general purpose filter. + + +3.4.6 AVC Intra Mode Mask + +3.4.6.1 Overview +AVC has 9 different intra modes for both 4x4 and 8x8 transforms and 4 modes for 16x16 transform. For a +mask will be feed into VME (9b+9b+4b), telling it which modes cannot be selected as output candidates. This +will be a 9 bit field, disabling a given mode for the entire macroblock. + + + +3.5 Messages +Request message bearing SFID of VME is routed to VME engine. +Programming Note: + +  Use of any message to the Video Motion Estimation function with the End of Thread bit set in the + message descriptor is not allowed. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 59 + 3.5.1 VME Motion Search Request +Restrictions: + +  the only surface type allowed is SURFTYPE_BUFFER. +  the surface format is ignored, data is returned from the constant buffer to the GRF without format + conversion. +Applications: + +  Motion search for video encoding +  Motion search for video processing such as deinterlace, frame rate conversion, etc. +Execution Mask. The execution mask is ignored. +Out-of-Bounds Accesses. Pixel replication is invoked for reads to areas outside of the surface. + + +3.5.2 Message Descriptor + Same as Prev. + Bit Description Gen? + 19 yes + Header Present. If set, indicates that the message includes the header. This bit + must be set to one for all VME messages + Format = Enable + Reserved: MBZ + 18:17 yes + 16 no + Stream-in Enable. If set, additional message phases of record stream-in will be + present with the input: 4 additional phases only when search control (M0.3 10:8) + is 111b (dual reference & dual record) and 2 additional phases otherwise. + Format = Enable + 15 no + Stream-out Enable. If set, additional message phases of record stream-out will + be present with the output: 4 additional phases only when search control (M0.3 + 10:8) is 111b (dual reference & dual record) and 2 additional phases otherwise. + Format = Enable + +14:13 yes + Message Type + 00: Reserved + 01: Inter-search only + 10: Intra-search only + 11: Inter- and intra-search enabled +12:11 yes + LUT_SUBINDEX. Specifies the index into the RDLUT state table. + + 10:8 yes + VME_SEARCH_PATH_LUT State Index. Specifies the index into the + VME_SEARCH_PATH_LUT state table. When dual records are used, both + records share the same predetermined search path. + 7:0 yes + Binding Table Index. Specifies the index into the binding table for the current + surface. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 60 + Same as Prev. + Bit Description Gen? + Forward reference surface is implied as [Binding Table Index + 1] and + the backward reference surface is implied as [Binding Table Index + 2] + Format = U8 + Range = [0,254] + + + +3.5.3 Input Message + +3.5.3.1 Message Header and Payload +The message header and payload size is determined based on the Message Type: + Message Type Mnemonic Message Length Response Length + 01 Inter-search only 5 + (stream-in) 6 + (stream-out) + 10 Intra-search only 5 1 + 11 Inter- and intra-search enabled 5 + (stream-in) 6 + (stream-out) + +When stream-in is enabled: + +  If (search control == 111b), the message length is +4 for total of 9 phases. +  Else (search control != 111b), the message length is +2 for total of 7 phases. + +When stream-out is enabled: + +  If (search control == 111b), the response length is +4 for total of 10 phases. +  Else (search control != 111b), the response length is +2 for total of 8 phases. + +For Message Type of 01, the VME request message contains the following two phases: + Same as + DWord Bit Description Prev. Gen? + M0.7 31:0 yes + Reserved + + M0.6 31:0 yes + Reserved + + M0.5 31:24 yes + Reference Region Height (RefHeight): This field specifies the reference region + height in pixels. When bidirectional search is enabled, this applies to both search + regions. Minus 16 provides the number of search point in vertical direction. + The value must be a multiple of 4. + Format = U8 + Range = [20, 64] + + 23:16 yes + Reference Region Width (RefWidth): This field specifies the search region width + in pixels. When bidirectional search is enabled, this applies to both search + regions. Minus 16 provides the number of search point in horizontal direction. + The value must be a multiple of 4. + Format = U8 + Range = [20, 64] + Note: Please make sure the reference windows are not completely outside of the + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 61 + Same as + DWord Bit Description Prev. Gen? + video frame, in that case, VME behavior is undefined. + + Ignored + 15:8 yes + 7:0 yes + Dispatch ID. This ID is assigned by the fixed function unit and is a unique + identifier for the thread. It is used to free up resources used by the thread upon + thread completion. + M0.4 + 31:0 Ignored yes + M0.3 + 31 Reserved : MBZ yes + (for Bidirectional Mirror mode, which is used for AVS mode. 0: disable for non- + AVS mode; 1: enabled: the best forward and the best backward MV will be + mirrored for AVS bidirectional search. Notice that, the mv cost penalty shall be + applied only for one set of mvs in this case.) + + 30:24 yes + Sub-Macroblock Sub-Partition Mask (SubMbPartMask): This field defines the + bit-mask for disabling sub-partition and sub-macroblock modes. + The lower 4 bits are for the major partitions (sub-macroblock) and the higher 3 + bits for minor partitions (with sub-partition for 4x(8x8) sub-macroblocks. + xxxxxx1 : 16x16 sub-macroblock disabled + xxxxx1x : 2x(16x8) sub-macroblock within 16x16 disabled + xxxx1xx : 2x(8x16) sub-macroblock within 16x16 disabled + xxx1xxx : 1x(8x8) sub-partition for 4x(8x8) within 16x16 disabled + xx1xxxx : 2x(8x4) sub-partition for 4x(8x8) within 16x16 disabled + x1xxxxx : 2x(4x8) sub-partition for 4x(8x8) within 16x16 disabled + 1xxxxxx : 4x(4x4) sub-partition for 4x(8x8) within 16x16 disabled + Usage note: one example usage of only enabling 4x(4x4) sub-partition while all + other partitions are disabled is for video processing, whereas parallel motion + searches are performed for 16 4x4 blocks. For that no further block combination + (into larger sub-partitions/sub-macroblocks) is needed. + + 23:22 yes + Intra SAD Measure Adjustment (IntraSAD): This field specifies distortion + measure adjustments used for the motion search SAD comparison. + This field must be set to 00 if Source Block Field Mode is 1 (interleaved). + 00 : none + 01 : Reserved + Better set to 00 if Source Block Field Mode is 1 (interleaved). + 21:20 yes + Inter SAD Measure Adjustment (InterSAD): This field specifies distortion + measure adjustments used for the motion search SAD comparison. + 00 : none + 01 : Reserved + 10 : Haar transform adjusted + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 62 + Same as + DWord Bit Description Prev. Gen? + 11 : Reserved + Better set to 00 if Source Block Field Mode is 1 (interleaved). + + M0.3 19 yes + Block-Based Skip Enabled: when this field is set on the skip thresholding + passing criterion will be based on the maximal distortion of individual blocks + (8x8’s or 4x4’s) instead of their sum (i.e. the distortion of 16x16). The block size is + 8x8 if and only if the Transform 8x8 Flag is set to ON and the source size is + 16x16.. + 18 no + Not implemented. + Reserved: MBZ + 17 yes + Disable Aligned VME Source Fetch: This field, when set disables the VMEunit + functionality that aligns source data requests to 16 pixels. (This bit is ignored if + SrcX and SrcSize are such that requests for source data cannot be aligned to 16 + pixels. The source data requests will be misaligned in these cases) + 16 yes + Disable Aligned VME Reference Fetch: This field, when set disables the + VMEunit functionality that fragments reference data requests which are not + aligned to 16 pixels into 16 pixel aligned requests. This may be used when the + surface is not a multiple of 16 pixels and a portion of the reference data is outside + the surface. + + 15 yes + Disable Field Cache Allocation: This field, when set to 1, disables the optimized + field cache line method in the Sampler Cache for reference block data when + RefAccess is 1 (field based). It is ignored by hardware if RefAccess is 0. + 0 – frame cache lines + 1 – field cache lines + 14 yes + Skip Mode Type (SkipType): + For B_DIRECT_16x16, both motion vectors of the skip center pair 0 are used. + For B_DIRECT_8x8s, all four skip center pairs are fully used (VME will never try + to combine them with non-skip shapes from IME, FME or BME). + 0 : SKIP_1MVP – one MV pair for 16x16 + 1 : SKIP_4MVP – Four MV pairs for 8x8s ( in this case and only this case, + SkipCenter Delta 1-3 will be used) + Note: SkipTypeMode should be programmed to 1MVP for non-16x16 Source size + 13:12 yes + Sub-Pel Mode (SubPelMode):This field defines the half/quarter pel modes. The + mode is inclusive, ie., higher precision mode samples lower precision locations. + 00 : integer mode searching + 01 : half-pel mode searching + 10 : reserved + 11 : quarter-pel mode searching + 11 yes + Dual Search Path Option: Used only for dual record cases, this field flags + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 63 + Same as + DWord Bit Description Prev. Gen? + whether two searching records uses the same or the different paths. + 0: use the same path as specified by the Search Path Location array + 1: use the different paths, the first one uses the even entries of the Search Path + Location array and the second one uses the odd entries of the Search Path + Location array. + + 10:8 yes + Search Control (SearchCtrl): This field specifies how the motion search is + performed. + The following table shows the valid encodings. Other encodings are reserved. + + Code Mode + 000 + Single reference, single record + and single start. + Search is performed only on + reference 0; only cost center 0 and + start 0 are used. There is only one + record. Adaptive search is also + allowed. However, when + AdaptiveEn is on, LenSU must be + at least 2 as the adaptive search in + VME is one-step delayed. + This is the common single + directional motion search mode. + 001 + Single reference, single record + and dual start. + Search is performed only on + reference 0; only cost center 0 is + used. There is only one record. + Search performs first on start 0 + and then on start 1. Then if LenSP + is not reached, the predetermined + search path will start on start 1 + with increment added to start 1 + location. It then is followed by + adaptive search. + This is used for single direction + adaptive search. + + 011 + Single reference, dual record + (and implied dual start). + Search is performed only on + reference 0; both cost center 0 + and 1 and start 0 and 1 are used. + Two records are used for both + paths during IME. + When integer search is complete, + the two records are combined to + find the best search. Sub-pel + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 64 + Same as + DWord Bit Description Prev. Gen? + refinement is only performed from + the best one. + This may be used for search for + multiple motion search + candidates/predicators. + 111 + Dual reference, dual record (and + implied dual start). + Search is performed on references + 0/1 with both cost centers 0/1 and + starts 0/1. Two records are used + for both paths during IME. + When integer search is complete, + and then sub-pel refinement is + also performed separately, the two + records are combined to find the + best search on a subblock basis. + This may be used for bidirectional + motion search, or multi-reference + P search. Whether bidirectional is + enabled or not depends on the + bidirection sub-macroblock mask. + If BiSubMbPartMask is set to + 1111’b, bidirectional search is + disabled. VME will output only the + best unidirectional search results. + Otherwise, BME will be performed. + Note that bidirectional search + and sub-pel refinement are + orthogonal features that can be + enabled indepdently. + 7 yes + Reference Access (RefAccess): This field defines how the reference blocks are + accessed from the reference frames. It indicates if the source picture is a frame + picture or a field picture. + Programming Note: For all known video coding standards, reference + pictures always have the same picture type as the source picture. + Therefore, this field should be programmed to be the same as SrcAccess. + 0 : frame based + 1 : field based + + 6 yes + Source Access (SrcAccess): This field defines how the source block is + accessed from the source frame. It indicates if the source picture is a frame + picture or a field picture. It is similar to the Picture Type used in video standards. + 0 : frame based + 1 : field based + 5:4 yes + Inter MbType Remap (MbTypeRemap): This field controls the mapping of the + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 65 + Same as + DWord Bit Description Prev. Gen? + output MbType when the VME output is an Inter (IntraMbFlag = INTER). The + intended usage, for example, is for two forward (or backward) references or for + two search regions from the same reference picture in one VME call. Hardware + ignores this field if the VME output is an intra type (IntraMbFlag = INTRA). + 00 : no remapping + 01 : remapping MbType to forward only (1-3 mapped to 1, even numbers in [4- + 14h] mapped to 4, odd numbers in [5-15h] mapped to 5, and 16h is unchanged) + 10 : remapping MbType to backward only (1-3 mapped to 2, even numbers in [4- + 14h] mapped to 6, odd numbers in [5-15h] mapped to 7, and 16h is unchanged) + 11 : reserved + + 3 yes + Reserved: MBZ + + 2 yes + Reserved : MBZ + + 1:0 yes + Source Block Size (SrcSize): This field defines how the 16x16 source block is + formed. When Source Block Size is less than 16x16, SU larger than 4x4 will be + used. + 00: 16x16 + 01: 16x8 + 10: Reserved (for 8x16) + 11: 8x8 + M0.2 31:16 no + Source Y (SrcY): This field defines the vertical position (of the block’s upper-left + pixel) in unit of pixels for the source block in the source picture (relative to picture + origin, not frame origin). + For field source (SrcAccess=1), the SrcFieldPolarity (M1.7-19), is required by + hardware to identify if this is top or bottom field of an interleaved memory surface. + The resulting Y address in the reference picture must be in even line aligned + within the reference picture. Specifically, if the reference picture is a frame picture. + the resulting Y address must be 2-line aligned; if the reference picture is a field + picture within a frame storage, and the resulting Y address must be 2-line aligned + within the field. i.e. it must be an even number for the frame case, and must be + equal to 0 or 1 modulo 4 for the field case. + Format = U16 + + 15;0 yes + Source X (SrcX): This field defines the horizontal position (of the block’s upper- + left pixel) in unit of pixels for the source block in the source picture. + The source block must be within the source picture starting at any integer grid. + Format = U16 + M0.1 31:16 no + Reference 1 Y Delta (Ref1Y): This field defines the vertical position (of the + upper-left corner of the reference region) in unit of pixels for Reference 1 region + relative to the source MB Y value on its respective picture. + For field reference (RefAccess=1), the Ref1FieldPolarity (M1.7-21), is required by + hardware to identify if this is top or bottom field of an interleaved memory surface. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 66 + Same as + DWord Bit Description Prev. Gen? + The resulting Y address in the reference picture must be in even line aligned + within the reference picture. Specifically, if the reference picture is a frame picture. + the resulting Y address must be 2-line aligned; if the reference picture is a field + picture within a frame storage, and the resulting Y address must be 2-line aligned + within the field. i.e. it must be an even number for the frame case, and must be + equal to 0 or 1 modulo 4 for the field case. + Note: For search control=3, this must equal Ref0Y. + Format = S15 + Hardware Range: [-2048 to 2047] + + 15;0 no + Reference 1 X Delta (Ref1X): This field defines the horizontal position (of the + upper-left corner of the reference region) in unit of pixels for Reference 1 region + relative to the source MB X value on its respective picture. + The resulting reference region is allowed to be outside the picture. Pixel + replication is applied to generate out of bound reference pixels. + This field is only valid when dual reference mode is selected + Note: For search control=3, this must equal Ref0X. + Format = S15 + Hardware Range: [-2048 to 2047] + M0.0 31:16 no + Reference 0 Y Delta (Ref0Y): This field defines the vertical position (of the + upper-left corner of the reference region) in unit of pixels for Reference 0 region + relative to the source MB Y value on its respective picture. + For field reference (RefAccess=1), the Ref0FieldPolarity (M1.7-20), is required by + hardware to identify if this is top or bottom field of an interleaved memory surface. + The resulting Y address in the reference picture must be in even line aligned + within the reference picture. Specifically, if the reference picture is a frame picture. + the resulting Y address must be 2-line aligned; if the reference picture is a field + picture within a frame storage, and the resulting Y address must be 2-line aligned + within the field. i.e. it must be an even number for the frame case, and must be + equal to 0 or 1 modulo 4 for the field case. + Format = S15 + Hardware Range: [-2048 to 2047] + 15;0 no + Reference 0 X Delta (Ref0X): This field defines the horizontal position (of the + upper-left corner of the reference region) in unit of pixels for Reference 0 region + relative to the source MB X value on its respective picture. + The resulting reference region is allowed to be outside the picture. Pixel + replication is applied to generate out of bound reference pixels. + Format = S15 + Hardware Range: [-2048 to 2047] + + 31:24 no + M1.7 Skip Center Enable Mask (SkipCenterMask): + [bit 31…24] + xxxx xxx1: Ref0 Skip Center 0 is enabled [corresponds to M2.0] + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 67 + Same as + DWord Bit Description Prev. Gen? + xxxx xx1x: Ref1 Skip Center 0 is enabled [corresponds to M2.1] + xxxx x1xx: Ref0 Skip Center 1 is enabled [corresponds to M2.2] + xxxx 1xxx: Ref1 Skip Center 1 is enabled [corresponds to M2.3] + xxx1 xxxx: Ref0 Skip Center 2 is enabled [corresponds to M2.4] + xx1x xxxx: Ref1 Skip Center 2 is enabled [corresponds to M2.5] + x1xx xxxx: Ref0 Skip Center 3 is enabled [corresponds to M2.6] + 1xxx xxxx: Ref1 Skip Center 3 is enabled [corresponds to M2.7] + Illegal cases: + Disable both Ref0 and Ref1 Skip Center 0 in case of Skip_1MVP. + Disable both Ref0 and Ref1 for any Skip Center pair in case of Skip_4MVP. + + Reserved: MBZ + 23:22 yes + 21 no + Reference1 Field Polarity Select (Ref1FieldPolarity): + If RefAccess = 1 (M0.3-7), meaning field based, than the hardware requires this + value is to derive the correct location on the reference surface in memory to fetch + pixels. This is because the reference is stored as a frame picture with both fields + interleaved in memory and the Ref1Y (M0.1-31:16) is relative to the SrcY location + on a field picture. + Hence, the starting y-pixel coordinate that will be fetched from the memory will be: + (SrcY+Ref1Y) * 2 + Ref1FieldPolarity + Else, this field is ignored by the hardware. + Format = U1 + 20 no + Reference0 Field Polarity Select (Ref0FieldPolarity): + If RefAccess = 1 (M0.3-7), meaning field based, than the hardware requires this + value is to derive the correct location on the reference surface in memory to fetch + pixels. This is because the reference is stored as a frame picture with both fields + interleaved in memory and the Ref0Y (M0.0-31:16) is relative to the SrcY location + on a field picture. + Hence, the starting y-pixel coordinate that will be fetched from the memory will be: + (SrcY+Ref0Y) * 2 + Ref0FieldPolarity + Else, this field is ignored by the hardware. + Format = U1 + 19 no + Source Field Polarity Select (SrcFieldPolarity): + If SrcAccess = 1 (M0.3-6), meaning field based, than the hardware requires this + value is to derive the correct location on the source surface in memory to fetch + pixels. This is because the source is stored as a frame picture with both fields + interleaved in memory and the SrcY value (M0.2-31:16) is the location on the field + picture (in other words, it does not convey the field polarity). + Hence, the starting y-pixel coordinate that will be fetched from the memory will be: + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 68 + Same as + DWord Bit Description Prev. Gen? + SrcY* 2 + SrcFieldPolarity + Else, this field is ignored by the hardware. + Format = U1 + + 18 no + Bilinear Filter Enable (BilinearEnable): + If set, the fractional filter will implement a simple bilinear interpolation filter instead + of the 4-tap filter. Note: this is supported for both hpel and qpel interpolation. + Format = Enable + 17:16 no + MV Cost Scaling Factor (MVCostScaleFactor): + This term allows the user to redefine the precision of the lookup into the LUT_MV + based on the MV cost difference from the cost center. The piecewise linear cost + function is defined from 0 to 64 in powers of 2 intervals, and the precision of the + difference is set by this field. There are 4 precision choices: + 00: qpel [Qpel difference between MV and cost center: eff cost range 0-15pel] + 01: hpel [Hpel difference between MV and cost center: eff cost range 0-31pel] + 10: pel [Pel difference between MV and cost center: eff cost range 0-63pel] + 11: 2pel [2Pel difference between MV and cost center: eff cost range 0-127pel] + Format = U2 + 15:8 yes + Macroblock Intra Structure (MbIntraStruct): This is a bitmask specifies + neighbor macroblock availability. This allows software to constrain intra prediction + mode search. + Note: user must set Bit6=Bit5. + Bits MotionVerticalFieldSelect Index + 7 + Reserved : MBZ + + 6 + Reserved : MBZ + + 5 + IntraPredAvailFlagE/A – A (Left + neighbor or Left bottom half) + + 4 + IntraPredAvailFlagB – B (Upper + neighbor) + 3 + IntraPredAvailFlagC – C (Upper + left neighbor) + 2 + IntraPredAvailFlagD – D (Upper + right neighbor) + 1:0 + Reserved : MBZ + + 7 yes + Luma Intra Source Corner Swap (IntraCornerSwap): This field specifies the + format of the intra luma neighbor pixel format in the message. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 69 + Same as + DWord Bit Description Prev. Gen? + 0: top neighbors are in sequential order + 1: Left-top corner is swapped with the last left-edge neighbor + + 6 yes + Non Skip MB Mode Cost Added (NonSkipModeAdded): This field indicates + that the distortion of the survived motion vectors will become non-skip, and the + MB mode cost will be added to its distortion. + 5 yes + Non Skip Zero MV Cost Added (NonSkipZMvAdded): This field indicates that + the distortion of the survived motion vectors will become non-skip, and the zero + MV component costs will be added to its distortion. + 4:0 yes + Luma Intra Partition Mask (IntraPartMask): This field specifies which Luma + Intra partition is enabled/disabled for intra mode decision. + xxxx1 : luma_intra_16x16 disabled + xxx1x : luma_intra_8x8 disabled + xx1xx : luma_intra_4x4 disabled + Bits [4:3] MBZ + M1.6 Reserved: MBZ + 31:0 no + + 31:16 no + M1.5 CostCenter 1 Delta Y (CostCenter0Y): This field defines the Y value for the + second cost center (associated with the second start) relative to the picture + source MB Y value. + Format = S13.2 (2’s comp) + Hardware Range: [-512.00 to 511.75] + 15:0 no + CostCenter 1 Delta X (CostCenter1X): This field defines the X value for the + second cost center (associated with the second start) relative to the picture + source MB X value. + Format = S13.2 (2’s comp) + Hardware Range: [-2048.00 to 2047.75] + 31:16 no + M1.4 CostCenter 0 Delta Y (CostCenter0Y): This field defines the Y value for the first + cost center (associated with the first start) relative to the picture source MB Y + value. + Format = S13.2 (2’s comp) + Hardware Range: [-512.00 to 511.75] + 15:0 no + CostCenter 0 Delta X (CostCenter0X): This field defines the X value for the first + cost center (associated with the first start) relative to the picture source MB X + value. + Format = S13.2 (2’s comp) + Hardware Range: [-2048.00 to 2047.75] + + M1.3 31:24 yes + IME Success & FME/BME Bypass Threshold (ImeTooGood): This field + specifies the threshold value for the ME distortion computes above which sub-pel + refinement search and bidirectional search are skipped (as the integer-pel + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 70 + Same as + DWord Bit Description Prev. Gen? + distortion is deemed to be good enough). + This value, if used, should be set to be greater than Early Success Threshold. + Format = U4U4 (encoded value should fit in 14-bits) + + 23:16 yes + Quit Inter Search Threshold (ImeTooBad): This field specifies the threshold + value for the ME distortion computes above which sub-pel refinement search and + bidirectional search are skipped (as the integer-pel distortion is deemed to be too + bad). + This value, if used, should be set to be greater than Early Success Threshold. + Format = U4U4 (encoded value should fit in 14-bits) + 15:8 yes + Partition Distortion Tolerance Threshold (PartToleranceThrhd): defines the + distortion tolerance used in the intermediate shape decision. (See Shape Decision + for more detail). + This field is only valid when PartCandidateEn is set. + Format = U4U4 (encoded value should fit in 14-bits) + 7:0 no + FME/BME Pruning Tolerance Threshold (FBPrunThrhd): This field specifies + the threshold when a normalized absolute difference of the two uni-directional + distortions is bigger than that, FME is skipped for the losing direction and BME is + skipped as well if bidirectional is enabled. The difference is normalized by the + number of 4x4 pixels in the tested partition. For example, for an 8x8 partition, the + absolute difference of the distortions is divided by 4 (right shifted by 2); and for a + 16x16 partition, it is right shifted by 4. With the unsigned byte, this field provides a + control of per pixel distortion difference with a large range from 1/16 to 16. + This field is only valid when FBPrunEn is set to 1 (and for Search Control set to + 111 - dual reference and dual record). + Format = U4U4 (encoded value should fit in 14-bits) + + M1.2 31:28 yes + Start Center 1 Y (Start1Y): This field defines the Y position of Search Path 1 + relative to the reference Y location. It is in unit of SU. + Format = U4 + + 27:24 yes + StartCenter 1 (Start1X): This field defines the X position of Search Path 1 + relative to the reference X location. It is in unit of SU. + The corresponding reference block must be fully within the reference region. + Format = U4 + 23:20 yes + Start Center 0 Y (Start0Y): This field defines the Y position of Search Path 1 + relative to the reference Y location. It is in unit of SU. + Format = U4 + 19:16 yes + StartCenter 0 X (Start0X): This field defines the X position of Search Path 1 + relative to the reference X location. It is in unit of SU. + The corresponding reference block must be fully within the reference region. + Format = U4 + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 71 + Same as + DWord Bit Description Prev. Gen? + 15:8 yes + Maximum Search Path Length (MaxNumSU): This field defines the maximum + number of SUs per reference including the predetermined SUs and the adaptively + generated SUs. + Note: every SU in fixed path will be counted (including the out-bound ones and + repeated ones), and in addition for adaptive SUs only the ones actually searched + will be added. + Format = U8, with valid range of [1,63] + + 7:0 yes + Max Fixed Search Path Length (LenSP): This field defines the maximum + number of SUs per reference which are evaluated by the predetermined SUs. + When adaptive walk is enabled, adaptive walk starts when this number is + reached. + Note: every SU in fixed path will be counted (including the out-bound ones and + repeated ones) + Format = U8, with valid range of [1,63] + M1.1 31 yes + Extented FME Repartition Enable (RepartEn): This field specifies whether the + repartitioning after FME as described in 6.1.3.3 is enabled. + 0 : disable + 1 : enable + 30 no + FME/BME Pruning Enable (FBPrunEn): This field specifies whether FME/BME + pruning is enabled. This is used to speedup the VME operation with low quality + impact. + This field is only valid for dual reference case (when Search Control is 111). + Otherwise, it must be set to zero. + 0 : disable + 1 : enable + Reserved: MBZ + 29 yes + AdaptiveValidationControl: if it is on, during adaptive IME searching, VME will + not pipeline SUs. In other words, VME will have only 1 SU in-flight and will wait + until all results are updated prior to deciding which SU to move to next. When this + is off (non-validation mode), VME’s pipeline will have at most 2 SUs in-flight to + enhance performance, but the out-of-order SU completion behavior will make + validation efforts exceedingly complex. + + 28 yes + Unidirectional Mix Disable (UniMixDisable): if it is on, all unidirectional resulting + motion vectors must share the same direction, i.e. either all are forward, or all are + backward. If this field is off, each partition, down to 8x8 subblock, may have a + different mix of forward and backward motion vectors. (Within each 8x8 subblock, + only one common choice is allowed.) + This field is MBZ except for cases of Search Control = 111’b (e.g. 7, dual + reference). + 27:24 yes + Bidirectional Sub-Macroblock and Sub-Partition Mask (BiSubMbPartMask): + This field defines the bit-mask for disabling sub-macroblock and sub-partition + modes. The enabled ones must be a subset of that enabled by SubMbPartMask. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 72 + Same as + DWord Bit Description Prev. Gen? + Note that 16x8 and 8x16 share the same bit and all sub-partitions share the same + bit. + xxx1 : 16x16 disabled + xx1x : 2x(16x8) and 2x(8x16) within 16x16 disabled + x1xx : 4x(8x8) within 16x16 disabled + 1xxx: sub-partitions 2x(8x4) and 2x(4x8) and 4x(4x4) within 8x8 are disabled + + 23:22 Reserved: MBZ yes + 21:16 yes + Bidirectional Weight (BiWeight): This field defines the weighting for the + backward and forward terms to generate the bidirectional term. This field is only + valid for bidirectional search (SearchCtrl = 111). + Format = U6 + Valid Values: [16, 21, 32, 43, 48] + + 15:6 Reserved: MBZ yes + 5:0 yes + Maximum Number of Motion Vectors (MaxNumMVs): This field specifies the + maximum number of motion vectors allowed for the current macroblock. This field + affects the macroblock partition decision. VME will return the best partition with + MvQuantity not exceeding MaxNumMVs. MaxNumMVs = 0 will only allow skip + as a valid Inter mode. + Note: This value is used ONLY for 16x16 source MB mode. + Usage Example: Certain profiles/levels for AVC standard have restriction + for the maximum number of motion vectors allowed for two consecutive + macroblocks (MaxMvsPer2Mb may be 16 or 32). + Format = U6 + Note: When skip is enabled, MaxNumMVs must be greater or equal to the + number of skip MVs. + M1.0 31:24 yes + Early IME Successful Stop Threshold (EarlyImeStop): This field specifies the + threshold value for the IME distortion computes of single 16x16 mode below + which no more search will be performed within the IME unit. + This field only takes effect if EarlyImeSuccessEn is set. + Note: Early IME exit only looks at ref0, and uses 8x8 for source 8x8 and 16x8 0 + for source 16x8. + Format = U4U4 (encoded value should fit in 14-bits) + 23:16 yes + Early Fme Success Threshold (EarlyFmeSuccess): Applying after fractional + ME, this field defines the threshold value for the ME distortion computes below + which the search process will exit early. + This field only takes effect if EarlySuccessEn is set. + This field only looks at primary candidate + Format = U4U4 (encoded value should fit in 14-bits) + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 73 + Same as + DWord Bit Description Prev. Gen? + 15:8 yes + Skip Success Threshold (SkipSuccess): Applying after skip mode checking (if + enabled), this field defines the threshold value for the ME distortion computes + below which the search process will exit early. + This threshold is always used for setting MbSkipFlag, when the corresponding + raw distortion is less than or equal to the threshold. + This field causes early VME termination only if EarlySuccessEn is set to 1. + Format = U4U4 (encoded value should fit in 14-bits) + + 7 yes + Transform 8x8 Flag For Inter Enable (T8x8FlagForInterEn): This field specifies + whether Transform8x8Flag is updated for inter mode according the resulting inter- + mode sub-partition size. + 0 : disable + 1 : enable + 6 yes + Quit Inter Search Enable (QuitInterEn): This field specifies whether the inter + search may be prematurely terminated after IME when the IME distortion is worse + than the predetermined threshold QuitInterThrhd. When this field is not set, if + early out does occur on full-pel location, hardware switches to local sub-pel + refinement search. When this field is set, however, the local sub-pel refinement + step is skipped. + This field takes effect independent of EarlySuccessEn. + 0 : disable + 1 : enable + 5 yes + Early IME Success Enable (EarlyImeSuccessEn): This field specifies whether + the Early Success may terminate on full-pel precision. When this field is not set, if + early out does occur on full-pel location, hardware continues to local sub-pel + refinement search and so on. When this field is set, however, the local sub-pel + refinement step is skipped and intra search is also skipped. + This field only takes effect if EarlySuccessEn is set. + Usage example: This may be used for cases with large static area where + (0,0) motion vector delivers very good results that no FME refinement is + needed and also intra check is also skipped. This may also be used in + place of Skip Mode Checking when the skip center(s) happens to be an + integer location inside the SU of the Start Center(s). + 0 : disable + 1 : enable + + 4 yes + Early Success Enable (EarlySuccessEn): This field enables Early Success of + the motion search when the ME distortion is below EarlySuccessThrhd. Early + Success may occur during skip mode check, integer search and sub-pel search + stages. Termination directly out of integer search is controlled by the + EarlySuccessImeEn field. + 0 : disable + 1 : enable + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 74 + Same as + DWord Bit Description Prev. Gen? + 3 yes + Partition Candidates Enable (PartCandidateEn): This field enables multiple + partition candidates (VME hardware supports only up to two candidates). When it + is set, a second partition candidate that is within PartToleranceThrhd from the + best partition is kept for subsequent inter-search operations. + This field is only allowed to be set to 1 if SrcSize is 16x16. + 0: a single partition is determined by IME + 1: multiple partition candidates are allowed + + 2 yes + Bidirectional Mix Disable (BiMixDis): if it is on, all resulting motion vectors must + share the same direction, i.e. either all are unidirectional (i.e. forward or + backward), or all bidirectional. If this field is off, each partition may have different + search direction (forward, backward or bidirectional). + Usage Example: MPEG2 bidirectional decision is at whole macroblock level, + while AVC decision is at subblock level. + 0: bidirectional decision on subblock level that bidirectional mode is enabled + 1: bidirectional decision on whole macroblock + 1 yes + Adaptive Search Enable (AdaptiveEn): This field defines whether adaptive + searching is enabled for IME. When Adaptive Search is enabled, there must be at + least two search steps preceded. It is either from a single start with step of >=2 or + from a dual-start. + 0 : disable + 1 : enable + 0 yes + Skip Mode Enable (SkipModeEn): This field specifies whether the skip mode + checking is performed before the motion search. If this field is set, Skip Center, + which may have a sub-pel precision, is first tested before IME. + 0 : disable + 1 : enable + Note: It must be 0 if Inter is not ON in Message Type or if SrcType!=00 (less + than 16x16) + M2.7 31:0 no + Ref1 SkipCenter 3 Delta XY (for definition see M2.0) + + M2.6 31:0 no + Ref0 SkipCenter 3 Delta XY (for definition see M2.0) + + M2.5 31:0 no + Ref1 SkipCenter 2 Delta XY (for definition see M2.0) + + M2.4 31:0 no + Ref0 SkipCenter 2 Delta XY (for definition see M2.0) + + M2.3 31:0 no + Ref1 SkipCenter 1 Delta XY (for definition see M2.0) + + M2.2 31:0 no + Ref0 SkipCenter 1 Delta XY (for definition see M2.0) + + M2.1 31:0 no + Ref1 SkipCenter 0 Delta XY (for definition see M2.0) + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 75 + Same as + DWord Bit Description Prev. Gen? + 31:16 no + M2.0 Ref0 Skip Center 0 Delta Y: + This field defines the Y value for the forward skip center relative to the 8x8 block + offset from the source MB Y location in quarter-pel precision associated with + Ref0. + To match the relative 8x8 block location, the HW will add fixed offsets to the 4 + skip centers in each direction to generate the correct pixel location to fetch the + data. + For SkipCenter 0: VME will add 0 to the user-input Y value. + For SkipCenter 1: VME will add 0 to the user-input Y value. + For SkipCenter 2: VME will add 32 to the user-input Y value. + For SkipCenter 3: VME will add 32 to the user-input Y value. + Format = S13.2 (2’s comp) + Hardware Range: [-512.00 to 511.75] + + 15:0 no + Ref0 SkipCenter 0 Delta X: + This field defines the X value for the forward skip center relative to the 8x8 block + offset from the source MB X location in quarter-pel precision associated with + Ref0. + To match the relative 8x8 block location, the HW will add fixed offsets to the 4 + skip centers in each direction to generate the correct pixel location to fetch the + data. + For SkipCenter 0: VME will add 0 to the user-input X value. + For SkipCenter 1: VME will add 32 to the user-input X value. + For SkipCenter 2: VME will add 0 to the user-input X value. + For SkipCenter 3: VME will add 32 to the user-input X value. + Format = S13.2 (2’s comp) + Hardware Range: [-2048.00 to 2047.75] + +For Message Type of 10 and 11, the VME request message has additional two phases to deliver the +neighbor macroblock pixels for intra prediction. Here the neighbor pixel location [x, y] is relative to the +current 16x16 macroblock, with [x,y] = [-1, -1] for the upper-left corner edge pixel in neighbor D, [-1, +0…15] for the left edge pixels in neighbor A, and [0…15…23, -1] for the upper and upper-right edge +pixels in neighbors B and C. +Note that for Message Type of 10, which is intra-search only mode, the fields regarding reference +windows and inter-prediction control in the command are ignored by hardware (and no pixels are fetched +from the reference window(s)). + To help with vector data access in software, horizontal neighbor pixels from D, B, and C are stored in +one register in raster order with 8 pixel alignment. Vertical neighbor pixels from A are stored in a separate +register. + Same as + Prev. + DWord Bit Description Gen? + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 76 + Same as + Prev. + DWord Bit Description Gen? + M3.7 31:0 yes, but + Neighbor pixel Luma value [23, -1] to [20, -1]. Upper-right pixels from neighbor + was M2 + macroblock C + M3.6 31:0 yes, but + Neighbor pixel Luma value [19, -1] to [16, -1]. Upper-right edge pixels from + was M2 + neighbor macroblock C + M3.5 31:0 yes, but + Neighbor pixel Luma value [15, -1] to [12, -1]. Top edge pixels from neighbor + was M2 + macroblock B + M3.4 31:0 yes, but + Neighbor pixel Luma value [11, -1] to [8, -1]. Top edge pixels from neighbor + was M2 + macroblock B + + M3.3 31:0 yes, but + Neighbor pixel Luma value [7, -1] to [4, -1]. Top edge pixels from neighbor + was M2 + macroblock B + M3.2 31:24 yes, but + Neighbor pixel Luma value [3, -1]. Fourth top edge pixel from neighbor macroblock + was M2 + B + 23:16 yes, but + Neighbor pixel Luma value [2, -1]. Third top edge pixel from neighbor macroblock + was M2 + B + 15:8 yes, but + Neighbor pixel Luma value [1, -1]. Second top edge pixel from neighbor + was M2 + macroblock B + + 7:0 yes, but + Neighbor pixel Luma value [0, -1]. First top edge pixel from neighbor macroblock B + was M2 + 31:24 yes, but + M3.1 Corner Neighbor pixel 0. Its content depends on IntraCornerSwap field. It swaps + was M2 + with Corner Neighbor pixel 1. + Neighbor pixel Luma value [-1, -1]. The one upper-left edge pixel from neighbor + macroblock D, which is the right most edge pixel of D, if IntraCornerSwap field is 0. + Or + Neighbor pixel Luma value [-1, 15]. The last left edge pixel from neighbor + macroblock A, which is the left most edge pixel of D, if IntraCornerSwap field is 1. + + Reserved: MBZ (Hardware ignores this field) + 23:4 no + 3:0 no + AVC Intra 16x16 Mode Mask (Intra16x16ModeMask): + Disables given intra mode as follows. + xxx1: + xx1x: + x1xx: + 1xxx: + + Reserved: MBZ (Hardware ignores this field) + M3.0 31:25 no + 24:16 no + AVC Intra 8x8 Mode Mask (Intra16x16ModeMask): + Disables given intra mode as follows. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 77 + Same as + Prev. + DWord Bit Description Gen? + x xxxx xxx1: + x xxxx xx1x: + x xxxx x1xx: + x xxxx 1xxx: + x xxx1 xxxx: + x xx1x xxxx: + x x1xx xxxx: + x 1xxx xxxx: + 1 xxxx xxxx: + Reserved: MBZ (Hardware ignores this field) + 15:9 no + 8:0 no + AVC Intra 4x4 Mode Mask (Intra16x16ModeMask): + Disables given intra mode as follows. + x xxxx xxx1: + x xxxx xx1x: + x xxxx x1xx: + x xxxx 1xxx: + x xxx1 xxxx: + x xx1x xxxx: + x x1xx xxxx: + x 1xxx xxxx: + 1 xxxx xxxx: + M4.7 Reserved: MBZ + 31:0 no + + M4.6 Reserved: MBZ + 31:0 no + M4.5 Reserved: MBZ + 31:0 no + M4.4 31:28 yes, but + Intra Predictor Mode for Neighbor B15 (IntraMxMPredModeB15): This field + was M3 + carries the intra prediction mode of the fourth bottom 4x4 block (Block 15 in + Numbers of Block4x4 in a 16x16 region) of the top neighbor macroblock B. Definition + of the term is according to Sections 8.3.1 and 8.3.2 of the AVC specification. + 27:24 yes, but + Intra Predictor Mode for Neighbor B14 (IntraMxMPredModeB14): This field + was M3 + carries the intra prediction mode of the third bottom 4x4 block (Block 14 in Numbers + of Block4x4 in a 16x16 region) of the top neighbor macroblock B. Definition of the + term is according to Sections 8.3.1 and 8.3.2 of the AVC specification. + + 23:20 yes, but + Intra Predictor Mode for Neighbor B11 (IntraMxMPredModeB11): This field + was M3 + carries the intra prediction mode of the second bottom 4x4 block (Block 11 in + Numbers of Block4x4 in a 16x16 region) of the top neighbor macroblock B. Definition + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 78 + Same as + Prev. + DWord Bit Description Gen? + of the term is according to Sections 8.3.1 and 8.3.2 of the AVC specification. + 19:16 yes, but + Intra Predictor Mode for Neighbor B10 (IntraMxMPredModeB10): This field + was M3 + carries the intra prediction mode of the first bottom 4x4 block (Block 10 in Numbers + of Block4x4 in a 16x16 region)of the top neighbor macroblock B. Definition of the + term is according to Sections 8.3.1 and 8.3.2 of the AVC specification. + 15:12 yes, but + Intra Predictor Mode for Neighbor A15 (IntraMxMPredModeA15): This field + was M3 + carries the intra prediction mode of the fourth rightmost 4x4 block (Block 15 in + Numbers of Block4x4 in a 16x16 region) of the left neighbor A. Definition of the term + is according to Sections 8.3.1 and 8.3.2 of the AVC specification. + 11:8 yes, but + Intra Predictor Mode for Neighbor A13 (IntraMxMPredModeA13): This field + was M3 + carries the intra prediction mode of the third rightmost 4x4 block (Block 13 in + Numbers of Block4x4 in a 16x16 region) of the left neighbor A. Definition of the term + is according to Sections 8.3.1 and 8.3.2 of the AVC specification. + + 7:4 yes, but + Intra Predictor Mode for Neighbor A7 (IntraMxMPredModeA7): This field carries + was M3 + the intra prediction mode of the second rightmost 4x4 block (Block 7 in Numbers of + Block4x4 in a 16x16 region) of the left neighbor A. + 3:0 yes, but + Intra Predictor Mode for Neighbor A5 (IntraMxMPredModeA5): This field carries + was M3 + the intra prediction mode of the first rightmost 4x4 block (Block 5 in Numbers of + Block4x4 in a 16x16 region) of the left neighbor A. Definition of the term is according + to Sections 8.3.1 and 8.3.2 of the AVC specification. + Intra Predictor Modes for Neighbor A and B are only used if + MODE_INTRA_NOPRED is not zero. + For intra mode selection, bias is applied to the predicted mode if a predictor is + present for a partition. This is achieved by applying a penalty term + MODE_INTRA_NONPRED defined in the VME state to the cost functions for non- + predicted modes. + The predictor for a given partition is from its left neighbor and top neighbor. The intra + decision for a partition serves as the predictor for the next partition in the partition + order as defined in Numbers of Block4x4 in a 16x16 region and Numbers of + Block4x4 in an 8x8 region or numbers of Block8x8 in a 16x16 region. + This set of intra predictor mode for neighbor macroblocks are only used for + INTRA8x8 and INTRA4x4 modes. + Format : U4 (The value of this field is defined in Definition of Intra4x4PredMode + which is the same as that in Definition of Intra8x8PredMode.) + M4.3 31:24 yes, but + Corner Neighbor pixel 1. Its content depends on IntraCornerSwap field. It swaps + was M3 + with Corner Neighbor pixel 0. + Neighbor pixel Luma value [-1, -1]. The one upper-left edge pixel from neighbor + macroblock D, which is the right most edge pixel of D, if IntraCornerSwap field is 1. + Or + Neighbor pixel Luma value [-1, 15]. The last left edge pixel from neighbor + macroblock A, which is the left most edge pixel of D, if IntraCornerSwap field is 0. + + 23:0 yes, but + Neighbor pixel Luma value [-1, 14] to [-1, 12]. Left edge pixels from neighbor + was M3 + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 79 + Same as + Prev. + DWord Bit Description Gen? + macroblock A + M4.2 31:0 yes, but + Neighbor pixel Luma value [-1, 11] to [-1, 8]. Left edge pixels from neighbor + was M3 + macroblock A + M4.1 31:0 yes, but + Neighbor pixel Luma value [-1, 7] to [-1, 4]. Left edge pixels from neighbor + was M3 + macroblock A + M4.0 31:24 yes, but + Neighbor pixel Luma value [-1, 3]. Fourth left edge pixel from neighbor macroblock + was M3 + A + + 23:16 yes, but + Neighbor pixel Luma value [-1, 2]. Third left edge pixel from neighbor macroblock + was M3 + A + 15:8 yes, but + Neighbor pixel Luma value [-1, 1]. Second left edge pixel from neighbor + was M3 + macroblock A + 7:0 yes, but + Neighbor pixel Luma value [-1, 0]. First left edge pixel from neighbor macroblock A + was M3 + + +3.5.4 Writeback Message +In order to minimize kernel software overhead, the PLACEMENTS of the bit-fields as well as the +words/dwords are specifically designed to match with the inline data of the MFC_PAK_OBJECT +command of MFX. + Same as + Prev. + DWord Bit Description Gen? + W0.7 31:28 yes + VME Decisions – Other: These 4 bits are used to expose internal behavior of VME to + the kernel, specifically whether or not FME or BME had a positive impact, whether or + not the ExtraCandidate adds any value to be checked, and whether or not the MaxMV + value limited partitioning to a larger shape decision. + xxx1: After FME, the primary candidate’s distortion was improved. + xx1x: After BME, the primary candidate’s distortion was improved. + x1xx: When VME concludes, the ExtraCandidate ends up beating the initial + primary candidate. + 1xxx: The MaxMV value restricted the final partition decision (VME would have + picked a more detailed shape, but couldn’t due to motion vector constraint). ). + This field only applies to the final partition decision of the main partitioning or + candidate and not the alternate candidate. It is only valid incase of SrcSize 16x16. + Otherwise it is MBZ. + 27:23 yes + VME Decisions – Early Exit Conditions: These 5 bits expose to the kernel that VME + finished prior to completing all subfunctions and for what early exit criteria this + occurred. Note, these values are only set when the VmeFlag “EarlySuccess” is + enabled. + xxxx1: EarlySkipExit Occurred + xxx1x: EarlyImeStop Occurred + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 80 + Same as + Prev. + DWord Bit Description Gen? + xx1xx: ImeTooGood Occurred + x1xxx: ImeTooBad Occurred + 1xxxx: EarlyFmeExit Occurred + 22:16 yes + VME Decisions – Sub-Functions Performed: These 7 bits expose to the kernel + which sub-functions VME performed. Also, each sub-function is explicitly listed for + primary or extra candidate for FME and BME. There is some redundancy with respect + to Skipcheck and Intra based on input state to VME. + xxxxxx1: Performed Skipcheck + xxxxx1x: Performed IME + xxxx1xx: Performed FME on primary + xxx1xxx: Performed FME on extra candidate + xx1xxxx: Performed BME on primary + x1xxxxx: Performed BME on extra candidate + 15:8 yes + Sub-Macroblock Prediction Mode (SubMbPredMode): If InterMbMode is + INTER8x8, this field describes the prediction mode of the sub-partitions in the four 8x8 + sub-macroblock. It contains four subfields each with 2-bits, corresponding to the four + 8x8 sub-macroblocks in sequential order. + This field is derived from sub_mb_type for a BP_8x8 macroblock. + This field is derived from MbType for a non-BP_8x8 inter macroblock, and carries + redundant information as MbType). + If InterMbMode is INTER16x16, INTER16x8 or INTER8x16, this field carries the + prediction modes of the sub macroblock (one 16x16, two 16x8 or two 8x16). The + unused bits are set to zero. + Bits [1:0]: SubMbPredMode[0] + Bits [3:2]: SubMbPredMode[1] + Bits [5:4]: SubMbPredMode[2] + Bits [7:6]: SubMbPredMode[3] + 7:0 yes + Sub-Macroblock Shape (SubMbShape): This field describes the subdivision of the + four 8x8 sub-macroblocks. It contains four subfields each with 2-bits, corresponding to + the four 8x8 sub macroblocks in sequential order. + This field is derived from sub_mb_type for a BP_8x8 or equivalent macroblock. + This field is forced to 0 for a non-BP_8x8 inter macroblock, and effectively carries + redundant information as MbType). + This field is only valid If InterMbMode is INTER8x8, Otherwise, it is set to zero. + Bits [1:0]: SubMbShape[0] + Bits [3:2]: SubMbShape[1] + Bits [5:4]: SubMbShape[2] + Bits [7:6]: SubMbShape[3] + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 81 + Same as + Prev. + DWord Bit Description Gen? + W0.6 31:26 yes + Alternate Search Path Length: Counts the number of unique search units computed + by VME for the alternate search path for dual reference or dual search path. If the + search path would return to a previously processed SU, it would not be reprocessed + and hence not recounted. The value of [W0.1 15:8] is the overall total search units + processed from both paths whereas this value is the contribution only from the second + search path. Note: Whenever VME is in a mode that processes only a single search + path, this field will be 0x0. + Format: U6, Range of 0-48 + 25:16 yes + Total VME Stalled Clocks by 16: Counts the number of clocks VME is + stalled\starved while processing this request, due to cache misses. The result is + returned in units of 16 clock intervals. If the maximum value is returned, the full range + was exceeded and the value clipped to the max (this is very unlikely). + Format: U10, Range of 0-1023 [logical range of 0-16383 in 16 clock intervals] + + 15:8 yes + Total VME Compute Clocks by 16: Counts the number of clocks VME is processing + this request, but not stalled\starved as a result of cache misses. The result is returned + in units of 16 clock intervals. If the maximum value is returned, the full range was + exceeded and the value clipped to the max (this is very unlikely). + 7:0 yes + Macroblock Intra Structure (MbIntraStruct): This is a bitmask specifies neighbor + macroblock availability. This allows software to constrain intra prediction mode search. + This field is simply copied from the input message (to reduce software overhead of + forming the output message to PAK). + Bits MotionVerticalFieldSelect Index + 7 + Reserved : MBZ (for + IntraPredAvailFlagF – F (pixel[- + 1,7] available for MbAff) + 6 + Reserved : MBZ (for + IntraPredAvailFlagA/E – A (left + neighbor top half for MbAff) + 5 + IntraPredAvailFlagE/A – A (Left + neighbor or Left bottom half) + 4 + IntraPredAvailFlagB – B (Upper + neighbor) + 3 + IntraPredAvailFlagC – C (Upper + left neighbor) + 2 + IntraPredAvailFlagD – D (Upper + right neighbor) + + 1:0 + Reserved : MBZ (for + ChromaIntraPredMode) + + W0.5 31:16 yes + LumaIntraPredModes[3] + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 82 + Same as + Prev. + DWord Bit Description Gen? + Specifies the Luma Intra Prediction mode for four 4x4 sub-block of a MB, 4-bit each. + 15:0 yes + LumaIntraPredModes[2] + Specifies the Luma Intra Prediction mode for four 4x4 sub-block of a MB, 4-bit each. + W0.4 31:16 yes + LumaIntraPredModes[1] + Specifies the Luma Intra Prediction mode for four 4x4 sub-block of a MB, 4-bit each. + 15:0 yes + LumaIntraPredModes[0] + Specifies the Luma Intra Prediction mode for four 4x4 sub-block, four 8x8 block or one + intra16x16 of a MB. + 4-bit per 4x4 sub-block (Transform8x8Flag=0, Mbtype=0 and intraMbFlag=1) or 8x8 + block (Transform8x8Flag=1, Mbtype=0, MbFlag=1), since there are 9 intra modes. + 4-bit for intra16x16 MB (Transform8x8Flag=0, Mbtype=1 to 24 and intraMbFlag=1), + but only the LSBit[1:0] is valid, since there are only 4 intra modes. + + W0.3 yes + 31:28 Direct8x8Pattern + This field indicates whether each of the four 8x8 sub macroblocks is using the + predicted MVs and will not be explicitly coded in the bitstream (the sub macroblock will + be coded as direct mode). It contains four 1-bit subfields, corresponding to the 4 sub + macroblocks in sequential order. The whole macroblock may be actually coded as + B_Direct_16x16 or B_Skip, according to the macroblock type conversion rules + described in a later sub section. + This field is only valid for a B slice. It is ignored by hardware for a P slice. + 0 in a bit – Corresponding MVs are sent in the bitstream + 1 in a bit – Corresponding MVs are not sent in the bitstream + Reserved: MBZ + 27:14 yes + 13:0 yes + BestIntraDistortion + The IntraMbMode will indicate if this is a 16x16/8x8/4x4 distortion. + Format = U14 + W0.2 Reserved: MBZ + 31 yes + + 30 yes + SkipRawDistortionInvalid + Format = U14 + 29:16 yes + SkipRawDistortion + Format = U14 + Reserved: MBZ + 15:14 yes + 13:0 yes + InterDistortion + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 83 + Same as + Prev. + DWord Bit Description Gen? + Format = U14 + W0.1 Reserved: MBZ + 31:30 yes + 29:16 yes + Minimal Distortion: This field contains the overall distortion for the source block + associated with the winning MbType, which could be one of intra or inter modes. + Format = U14 + 15:8 yes + Search Path Length: This field returns the number of SU it takes in the integer + search. It includes predetermined search path and dynamic search path. + Format: U8 + + 7:4 yes + Reference 1 border reached: bitmask indicating whether any border of reference 1 is + reached by one or more motion vectors in the winning inter mode. + xxx1: left border reached + xx1x: right border reached + x1xx: top border reached + 1xxx: bottom border reached + 3:0 yes + Reference 0 border reached: bitmask indicating whether any border of reference 0 is + reached by one or more motion vectors in the winning inter mode. + xxx1: left border reached + xx1x: right border reached + x1xx: top border reached + 1xxx: bottom border reached + W0.0 + 31 ExtendedForm (IVB only) yes + This field specifies that LumaIntraMode’s are fully replicated in 4x4 sub-blocks + respectively. And motion vectors must be in unpacked form as well. This non-DXVA + form is used for optimal kernel performance. + + 30:29 Reserved: MBZ + 28:24 yes + MvQuantity + Specify the number of MVs in packed format (in unit of motion vectors). + Note: this field is provided to help with software to meet conformance requirements + such as maximum number of motion vectors for two consecutive macroblocks. + Format: U5, valid from 0 to 32 + + 23 Reserved : MBZ yes + (reserved for ExternalMvBufFlag. It is always 0 in this case, since MV’s are + included) + 22:20 yes + MvSize (Motion Vector Size). This field specifies the size and format of the output + motion vectors. + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 84 + Same as + Prev. + DWord Bit Description Gen? + This field is reserved (MBZ) when the output signal IntraMbFlag = 1. + The valid encodings are: + 000 = 0: No motion vector + 100 = 8MV: Four 8x8 motion vector pairs + 110 = 32MV: 16 4x4 motion vector pairs + Others are reserved. + (The following encodings are intended for future usages: + 001 = 1MV: one 16x16 motion vector + 010 = 2MV: One 16x16 motion vector pair + 011 = 4MV: Four 8x8 motion vectors + 101 = 16MV: 16 4x4 motion vectors + 111 = Packed, number of MVs is given by MvQuantity.) + 19 yes + DcBlockCodedYFlag. This field specifies if the Luma DC sub-block is coded. + 1 – the 4x4 DC-only Luma sub-block of the Intra16x16 coded MB is present; it is still + possible that all DC coefficients are zero. + 0 – no 4x4 DC-only Luma sub-block is present; either not in Intra16x16 MB mode or + all DC coefficients are zero. + VME hardware forces this output to be 1. + 18 yes + DcBlockCodedCbFlag. This field specifies if the Chroma Cb DC sub-block is coded. + 1 – the 2x2 DC-only Chroma Cb sub-block of all coded MB (any type) is present; it is + still possible that all DC coefficients are zero. + 0 – no 2x2 DC-only Chroma Cb sub-block is present; all DC coefficients are zero. + VME hardware forces this output to be 1. + 17 yes + DcBlockCodedCrFlag. This field specifies if the Chroma Cb DC sub-block is coded. + 1 – the 2x2 DC-only Chroma Cr sub-block of all coded MB (any type) is present; it is + still possible that all DC coefficients are zero. + 0 – no 2x2 DC-only Chroma Cr sub-block is present; all DC coefficients are zero. + VME hardware forces this output to be 1. + + Reserved: MBZ + 16 yes + 15 yes + Transform8x8Flag (Transform 8x8 Flag) + This field indicates that 8x8 transform is recommended. + It is set to 1 if IntraMbFlag = INTRA and IntraMbMode = INTRA_8x8. + For IntraMbFlag = INTER. If T8x8FlagForInterEn = 0, this field is set to 0 by VME + hardware. If T8x8FlagForInterEn = 1, this field is set to 1 if there is no sub + macroblock size less than 8x8 (noSubMbPartSizeLessThan8x8Flag = 1). + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 85 + Same as + Prev. + DWord Bit Description Gen? + 0: 4x4 integer transform + 1: 8x8 integer transform + Note: This bit will be always 0 for non-16x16 source block cases. + 14 yes + FieldMbFlag + This field indicates the inter prediction result is field or frame. + It is always set to SrcAccess. + 0: frame macroblock + 1: field macroblock + 13 yes + IntraMbFlag + This field specifies whether the current macroblock is an Intra (I) macroblock. Even + though I_PCM is considered as Intra MB, VME hardware cannot generate I_PCM + output. + For I-picture MB (IntraPicFlag =1), this field must be set to 1. + This flag must be set in consistent with the interpretation of MbType (inter or intra + modes). + 0: INTER (inter macroblock) + 1: INTRA (intra macroblock) + 12:8 yes + MbType + This field is encoded to match with the best macroblock type determined as described + in the next section. It follows an unified encoding for inter and intra macroblocks + according to AVC Spec. + + 7 yes + FieldMbPolarityFlag + This field indicates the field polarity of the current macroblock. + Unique for AVC standard, within an MbAff frame picture, this field may be different per + macroblock and is set to 1 only for the second macroblock in an MbAff pair if + FieldMbFlag is set. Otherwise, it is set to 0. + Within a field picture in most coding standard, this field is a constant for the whole field + picture. It is set to 1 if the current picture is the bottom field picture. Otherwise, it is set + to 0. + This field is reserved and MBZ for a progressive frame picture. + VME hardware set this field to 1 if the source block is a field block from the bottom + field and otherwise sets it to 0. This is accomplished by the following equation using + input signals SrcAccess and SrcY: SrcAccess && (bit0(SrcY) ==1). + 0 = Current macroblock is a field macroblock from the top field + 1 = Current macroblock is a field macroblock from the bottom field + + Reserved: MBZ + 6 yes + 5:4 yes + IntraMbMode + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 86 + Same as + Prev. + DWord Bit Description Gen? + This field is provided to carry redundant information as that in MbType. The full + extended definition of this field allows kernel software to help update the MbType field + when outputting controls to the MFX PAK encoding. + VME outputs this field regardless of MbIntraFlag value if intra mode is enabled. + Reserved: MBZ + 3 yes + 2 yes + MbSkipFlag + As an output of VME, this bit indicates whether one skip center (possibly of several + skip centers for each partition) is the winning motion vector position. + VME outputs this field regardless of MbIntraFlag value. + Note that the meaning of this field in VME is not the same as that used in PAK. + + yes + 1:0 InterMbMode + This field is provided to carry redundant information as that in MbType. The full + extended definition of this field allows kernel software to help update the MbType field + when outputting controls to the MFX PAK encoding. + VME outputs this field regardless of MbIntraFlag value if inter mode is enabled. + +W1.7 to 31:0 no + MVb[3] to MVb[1]. Motion vectors 3 to 1 for Reference 1, and + W1.2 Each + MVa[3] to MVa[1]. Motion vectors 3 to 1 for Reference 0 + + 31:16 no + W1.1 MVb[0].y: returning the y-coordinate of Motion Vector 0 for Reference 1, relative to + source MB location. + Format = S13.2 (2’s comp) + Hardware Range: [-512.00 to 511.75] + 15:0 no + MVb[0].x: returning the x-coordinate of Motion Vector 0 (co-located w/ + sublbock_4x4_0) for Reference 1, relative to source MB location. Its meaning is + determined by MbType. + Format = S13.2 (2’s comp) + Hardware Range: [-2048.00 to 2047.75] + 31:16 no + W1.0 MVa[0].y: returning the y-coordinate of Motion Vector 0 for Reference 0, relative to + source MB location. + Format = S13.2 (2’s comp) + Hardware Range: [-512.00 to 511.75] + + 15:0 no + MVa[0].x: returning the x-coordinate of Motion Vector 0 (co-located w/ + sublbock_4x4_0) for Reference 0, relative to source MB location. Its meaning is + determined by MbType. + The returned motion vectors are placed in a fixed data format, with up to 16 motion + vectors for one reference and the motion vectors from reference 0 and 1 interleaved. + Format = S13.2 (2’s comp) + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 87 + Same as + Prev. + DWord Bit Description Gen? + Hardware Range: [-2048.00 to 2047.75] +W2.7 to 31:0 no + MVb[7] to MVb[4]. Motion vectors 7 to 4 for Reference 1, and + W2.0 Each + MVa[7] to MVa[4]. Motion vectors 7 to 4 for Reference 0 + +W3.7 to 31:0 no + MVb[11] to MVb[8]. Motion vectors 11 to 8 for Reference 1, and + W3.0 Each + MVa[11] to MVa[8]. Motion vectors 11 to 8 for Reference 0 + +W4.7 to 31:0 no + MVb[15] to MVb[12]. Motion vectors 15 to 12 for Reference 1, and + W4.0 Each + MVa[15] to MVa[12]. Motion vectors 15 to 12 for Reference 0 + +W5.7 to yes, but + 31:0 InterDistortion[15] to InterDistortion[2]. Inter-prediction-distortion associated with + W5.1 was M3 + motion vector 15 to 2. Its meaning is determined by sub-shape. + Each + W5.0 Reserved: MBZ + 31:30 yes, but + was M3 + 29:16 yes, but + InterDistortion[1]. Inter-prediction-distortion with motion vector 1 (co-located with + was M3 + subblock_4x4_1). Its meaning is determined by sub-shape. + Format = U14 + Reserved: MBZ + 15:14 yes, but + was M3 + + 13:0 yes, but + InterDistortion[0]. Inter-prediction-distortion associated with motion vector 0 (co- + was M3 + located with subblock_4x4_0). Its meaning is determined by sub-shape. It must be + zero if the corresponding sub-shape is not chosen. + This field may be associated with MVa[0] and/or MVb[0], depending on the resulting + prediction mode for the sub-block. If the corresponding MV field is created by + “duplication”, this field must be zero. + Format = U14 + + 1. mv_format_pic = vin_mv_format * vin_codec_select + 2. Change vin_mvunpackenable to (vin_mvunpackenable + mv_format_pic) on all location. + 3. extended_form_pic = vin_extended_form * vin_codec_select + 4. (vctrl_it_Transform8x8Flag * !extended_form_pic) ? “h000” & + vctrl_it_lumaintrapredmode0[15:12] & “h000” & vctrl_it_lumaintrapredmode0[11:8] & “h000” & + vctrl_it_lumaintrapredmode0[7:4] & “h000” & vctrl_it_lumaintrapredmode0[3:0] : + vctrl_it_lumaintrapredmode3[15:0] & vctrl_it_lumaintrapredmode2 +MV Fub: + +Mux Output Table + ref_index_rep_size[3:0] + Select: + +Value Output Input Description + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 88 + 0001 enc_refidx_L0addr_B0_int[4:0] enc_mode_bind_fwd_B0[4:0] +0001 enc_refidx_L0addr_B1_int[4:0] enc_mode_bind_fwd_B1[4:0] +0001 enc_refidx_L0addr_B2_int[4:0] enc_mode_bind_fwd_B2[4:0] +0001 enc_refidx_L0addr_B3_int[4:0] enc_mode_bind_fwd_B3[4:0] +0001 enc_refidx_L1addr_B0_int[4:0] enc_mode_bind_bkd_B0[4:0] +0001 enc_refidx_L1addr_B1_int[4:0] enc_mode_bind_bkd_B1[4:0] +0001 enc_refidx_L1addr_B2_int[4:0] enc_mode_bind_bkd_B2[4:0] +0001 enc_refidx_L1addr_B3_int[4:0] enc_mode_bind_bkd_B3[4:0] +0010 enc_refidx_L0addr_B0_int[4:0] enc_mode_bind_fwd_B0[4:0] +0010 enc_refidx_L0addr_B1_int[4:0] enc_mode_bind_fwd_B1[4:0] +0010 enc_refidx_L0addr_B2_int[4:0] enc_mode_bind_fwd_B0[4:0] +0010 enc_refidx_L0addr_B3_int[4:0] enc_mode_bind_fwd_B1[4:0] +0010 enc_refidx_L1addr_B0_int[4:0] enc_mode_bind_bkd_B0[4:0] +0010 enc_refidx_L1addr_B1_int[4:0] enc_mode_bind_bkd_B1[4:0] +0010 enc_refidx_L1addr_B2_int[4:0] enc_mode_bind_bkd_B0[4:0] +0010 enc_refidx_L1addr_B3_int[4:0] enc_mode_bind_bkd_B1[4:0] +0100 enc_refidx_L0addr_B0_int[4:0] enc_mode_bind_fwd_B0_ext[4:0] +0100 enc_refidx_L0addr_B1_int[4:0] enc_mode_bind_fwd_B0_ext[4:0] +0100 enc_refidx_L0addr_B2_int[4:0] enc_mode_bind_fwd_B1_ext[4:0] +0100 enc_refidx_L0addr_B3_int[4:0] enc_mode_bind_fwd_B1_ext[4:0] +0100 enc_refidx_L1addr_B0_int[4:0] enc_mode_bind_bkd_B0_ext[4:0] +0100 enc_refidx_L1addr_B1_int[4:0] enc_mode_bind_bkd_B0_ext[4:0] +0100 enc_refidx_L1addr_B2_int[4:0] enc_mode_bind_bkd_B1_ext[4:0] +0100 enc_refidx_L1addr_B3_int[4:0] enc_mode_bind_bkd_B1_ext[4:0] +1000 enc_refidx_L0addr_B0_int[4:0] enc_mode_bind_fwd_B0[4:0] +1000 enc_refidx_L0addr_B1_int[4:0] enc_mode_bind_fwd_B0[4:0] +1000 enc_refidx_L0addr_B2_int[4:0] enc_mode_bind_fwd_B0[4:0] +1000 enc_refidx_L0addr_B3_int[4:0] enc_mode_bind_fwd_B0[4:0] +1000 enc_refidx_L1addr_B0_int[4:0] enc_mode_bind_bkd_B0[4:0] +1000 enc_refidx_L1addr_B1_int[4:0] enc_mode_bind_bkd_B0[4:0] +1000 enc_refidx_L1addr_B2_int[4:0] enc_mode_bind_bkd_B0[4:0] +1000 enc_refidx_L1addr_B3_int[4:0] enc_mode_bind_bkd_B0[4:0] + +Combinatorial Signals Table + Signal Equation +extended_form_pic vin_extended_form * vin_codec_selectR +enc_mode_bind_fwd_B0_ext[4:0] + extended_form_pic? + enc_mode_bind_fwd_B0[4:0] : enc_mode_bind_fwd_B0[4:0] + +enc_mode_bind_fwd_B1_ext[4:0] + extended_form_pic? + enc_mode_bind_fwd_B2[4:0] : enc_mode_bind_fwd_B1[4:0] +enc_mode_bind_bkd_B0_ext[4:0] + extended_form_pic? + enc_mode_bind_bkd_B0[4:0] : enc_mode_bind_bkd_B0[4:0] +enc_mode_bind_bkd_B1_ext[4:0] + extended_form_pic? + enc_mode_bind_bkd_B2[4:0] : enc_mode_bind_bkd_B1[4:0] + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 89 + 3.5.5 Stream-in\Stream-out Message +Each reference will require 2 message phases when performing multi-call. These phases will be added +onto the basic input or output message. Hence, the first stream-in or stream-out message phase +location is variable and represented below by M(X+?), where X equals the number of phases present in +the input or output message, respectively. +When both records are being streamed in or out, phases M+0 and M+1 will contain record0 (associated +with RefA) and M+2 and M+3 will contain record1 (associated with RefB). If there is only one reference +being searched (SearchControl != 111b) then only one record will be streamed in or out, specifically, only +M+0 and M+1 will be present. + DWord Bit Description + M(X+0).7 Reserved MBZ + 31:0 + + M(X+0).6 Reserved MBZ + 31:0 + 31:16 + M(X+0).5 Rec0 Shape 16x16 Y (relative to source MB) + Format = S13.2 (2’s comp) + Hardware Range: [-512.00 to 511.75] + 15:0 + Rec0 Shape 16x16 X (relative to source MB) + Format = S13.2 (2’s comp) + Hardware Range: [-2048.00 to 2047.75] + Reserved MBZ + M(X+0).4 31:16 + + Reserved MBZ + 15:14 + 13:0 + Rec0 Shape 16x16 Distortion + Format = U14 + 31:16 + M(X+0).3 Rec0 Shape 8x8_3 Distortion + Hardware only uses 14 bits. Upper bits ignored (True for all 8x8_X Distortions). + 15:0 Rec0 Shape 8x8_2 Distortion + 31:16 Rec0 Shape 8x8_1 Distortion + M(X+0).2 + 15:0 Rec0 Shape 8x8_0 Distortion + 31:16 + M(X+0).1 Rec0 Shape 8x16_1 Distortion + Hardware only uses 15 bits. Upper bits ignored (True for all 8x16_X Distortions). + + 15:0 Rec0 Shape 8x16_0 Distortion + 31:16 + M(X+0).0 Rec0 Shape 16x8_1 Distortion + Hardware only uses 15 bits. Upper bits ignored (True for all 16x8_X Distortions). + 15:0 Rec0 Shape 16x8_0 Distortion + 31:16 Rec0 Shape 8x8_3 Y (relative to source MB) + M(X+1).7 + 15:0 Rec0 Shape 8x8_3 X (relative to source MB) + 31:16 Rec0 Shape 8x8_2 Y (relative to source MB) + M(X+1).6 + 15:0 Rec0 Shape 8x8_2 X (relative to source MB) + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 90 + DWord Bit Description + 31:16 Rec0 Shape 8x8_1 Y (relative to source MB) + M(X+1).5 + 15:0 Rec0 Shape 8x8_1 X (relative to source MB) + 31:16 Rec0 Shape 8x8_0 Y (relative to source MB) + M(X+1).4 + 15:0 Rec0 Shape 8x8_0 X (relative to source MB) + 31:16 Rec0 Shape 8x16_1 Y (relative to source MB) + M(X+1).3 + 15:0 Rec0 Shape 8x16_1 X (relative to source MB) + 31:16 Rec0 Shape 8x16_0 Y (relative to source MB) + M(X+1).2 + 15:0 Rec0 Shape 8x16_0 X (relative to source MB) + 31:16 Rec0 Shape 16x8_1 Y (relative to source MB) + M(X+1).1 + 15:0 Rec0 Shape 16x8_1 X (relative to source MB) + 31:16 Rec0 Shape 16x8_0 Y (relative to source MB) + M(X+1).0 + 15:0 Rec0 Shape 16x8_0 X (relative to source MB) + M(X+2).7 Reserved MBZ + 31:0 + M(X+2).6 Reserved MBZ + 31:0 + + 31:16 + M(X+2).5 Rec1 Shape 16x16 Y (relative to source MB) + Format = S13.2 (2’s comp) + Hardware Range: [-512.00 to 511.75] + 15:0 + Rec1 Shape 16x16 X (relative to source MB) + Format = S13.2 (2’s comp) + Hardware Range: [-2048.00 to 2047.75] + Reserved MBZ + M(X+2).4 31:16 + Reserved MBZ + 15:14 + + 13:0 + Rec1 Shape 16x16 Distortion + Format = U14 + M(X+2).3 31:16 + Rec1 Shape 8x8_3 Distortion + Hardware only uses 14 bits. Upper bits ignored (True for all 8x8_X Distortions). + 15:0 Rec1 Shape 8x8_2 Distortion + M(X+2).2 31:16 Rec1 Shape 8x8_1 Distortion + 15:0 Rec1 Shape 8x8_0 Distortion + M(X+2).1 31:16 + Rec1 Shape 8x16_1 + Hardware only uses 15 bits. Upper bits ignored (True for all 8x16_X Distortions). + 15:0 Rec1 Shape 8x16_0 Distortion + M(X+2).0 31:16 + Rec1 Shape 16x8_1 Distortion + Hardware only uses 15 bits. Upper bits ignored (True for all 16x8_X Distortions). + + 15:0 Rec1 Shape 16x8_0 Distortion + M(X+3).7 31:16 Rec1 Shape 8x8_3 Y (relative to source MB) + 15:0 Rec1 Shape 8x8_3 X (relative to source MB) + M(X+3).6 31:16 Rec1 Shape 8x8_2 Y (relative to source MB) + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 91 + DWord Bit Description + 15:0 Rec1 Shape 8x8_2 X (relative to source MB) + M(X+3).5 31:16 Rec1 Shape 8x8_1 Y (relative to source MB) + 15:0 Rec1 Shape 8x8_1 X (relative to source MB) + M(X+3).4 31:16 Rec1 Shape 8x8_0 Y (relative to source MB) + 15:0 Rec1 Shape 8x8_0 X (relative to source MB) + M(X+3).3 31:16 Rec1 Shape 8x16_1 Y (relative to source MB) + 15:0 Rec1 Shape 8x16_1 X (relative to source MB) + M(X+3).2 31:16 Rec1 Shape 8x16_0 Y (relative to source MB) + 15:0 Rec1 Shape 8x16_0 X (relative to source MB) + M(X+3).1 31:16 Rec1 Shape 16x8_1 Y (relative to source MB) + 15:0 Rec1 Shape 16x8_1 X (relative to source MB) + M(X+3).0 31:16 Rec1 Shape 16x8_0 Y (relative to source MB) + 15:0 Rec1 Shape 16x8_0 X (relative to source MB) + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 92 + 4. Shared Functions Pixel Interpolater +The Pixel Interpolator provides barycentric parameters at various offsets relative to the pixel location. +These barycentric parameters are in the same format and layout as those received in the pixel shader +dispatch. Please refer to the “Windower” chapter in the “3D Pipeline” volume for more details on +barycentric parameters. +Barycentric parameters delivered in the pixel shader payload are at pre-defined positions based on +Barycentric Interpolation Mode bits selected in 3DSTATE_WM. The pixel interpolator allows +barycentric parameters to be computed at additional locations. + + +4.1 Messages +The following is the message definition for the Pixel Interpolator shared function. +Restrictions: + +  Pixel Interpolator messages can only be delivered by pixel shader kernels. +  [ivbgt2 pre-K0] Hang possible if linear PI message when Barycentric Interpolation mode has any + perspective bits set, or Pixel Shader Uses Source W is set. +  [ivbgt2 pre-K0] Hang possible if perspective PI message when Barycentric Interpolation mode has + any non-perspective bits set. + +Execution Mask. Each bit in the execution mask enables the corresponding slot’s barycentric parameter +return to the destination registers. + + +4.1.1 Initiating Message + +4.1.1.1 Message Descriptor + + Bit Description + 19 + Header Present: Specifies whether the message includes a header phase. Must be zero for all + Pixel Interpolator messages. + + Format = Enable +18:17 Ignored + 16 + SIMD Mode. Specifies the SIMD mode of the message being sent. + + Format = U1 + 0: SIMD8 mode + 1: SIMD16 mode + 15 Ignored + 14 + Interpolation Mode. Specifies which interpolation mode is to be used. + + Format = U1 + 0: Perspective Interpolation + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 93 + Bit Description + 1: Linear Interpolation + Programming Notes: +  This field cannot be set to “Linear Interpolation” unless Non-Perspective Barycentric Enable in + 3DSTATE_CLIP is enabled. + +13:12 + Message Type. Specifies the type of message being sent. + + Format = U2 + 0: Per Message Offset (eval_snapped with immediate offset) + 1: Sample Position Offset (eval_sindex) + 2: Centroid Position Offset (eval_centroid) + 3: Per Slot Offset (eval_snapped with register offset) + 11 + Slot Group Select. This field selects whether slots 15:0 or slots 31:16 are used for bypassed + data. + Bypassed data includes the X/Y addresses and centroid position. For 8- and 16-pixel + dispatches, SLOTGRP_LO must be selected on every message. For 32-pixel dispatches, this + field must be set correctly for each message based on which slots are currently being + processed. + 0: SLOTGRP_LO:choose bypassed data for slots 15:0 + 1: SLOTGRP_HI:choose bypassed data for slots 31:16 + Programming Notes: + This field must be set to SLOTGRP_LO for SIMD8 messages. SIMD8 messages always use bypassed data + for slots 7:0. + +10:8 Ignored + 7:0 + Message Specific Control. Refer to the sections below for the definition of these bits based on + Message Type. + + +4.1.1.1.1 “Per Message Offset” Message Descriptor +Bit Description +7:4 + Per Message Y Pixel Offset + + Specifies the Y Pixel Offset that applies to all slots. + Format = S4 2’s complement representing units of 1/16 pixel. + Range = [-8/16, +7/16] +3:0 + Per Message X Pixel Offset + + Specifies the X Pixel Offset that applies to all slots. + Format = S4 2’s complement representing units of 1/16 pixel. + Range = [-8/16, +7/16] + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 94 + 4.1.1.1.2 “Sample Position Offset” Message Descriptor +Bit Description +7:4 + Sample Index + + Specifies the sample index that applies to all slots. + Format = U4 + Range = [0,7 +3:0 Ignored + + +4.1.1.1.3 “Centroid Position” and “Per Slot Offset” Message Descriptor +Bit Description +7:0 Ignored + + +4.1.1.2 Message Payload for most messages +This message payload applies to the following message types: + +  Per Message Offset +  Sample Position Offset +  Centroid Position Offset +DWord Bit Description +M0.7:0 Ignored + + +4.1.1.3 SIMD8 Per Slot Offset Message Payload +This message payload applies only to the SIMD8 Per Slot Offset message type. The message length is 2. +DWord Bit Description + M0.7 31:0 + Slot 7 X Pixel Offset + + Specifies the X pixel offset for slot 7. + Format = S4 2’s complement representing units of 1/16 pixel. The upper 28 bits are + ignored. + Range = [-8/16, +7/16] + M0.6 31:0 + Slot 6 X Pixel Offset + + M0.5 31:0 + Slot 5 X Pixel Offset + + M0.4 31:0 + Slot 4 X Pixel Offset + + M0.3 31:0 + Slot 3 X Pixel Offset + + M0.2 31:0 + Slot 2 X Pixel Offset + + M0.1 31:0 + Slot 1 X Pixel Offset + + M0.0 31:0 + Slot 0 X Pixel Offset + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 95 + DWord Bit Description + M1.7 31:0 + Slot 7 Y Pixel Offset + + Specifies the Y pixel offset for slot 7. + Format = S4 2’s complement representing units of 1/16 pixel. The upper 28 bits are + ignored. + Range = [-8/16, +7/16] + M1.6 31:0 + Slot 6 Y Pixel Offset + + M1.5 31:0 + Slot 5 Y Pixel Offset + + M1.4 31:0 + Slot 4 Y Pixel Offset + + M1.3 31:0 + Slot 3 Y Pixel Offset + + M1.2 31:0 + Slot 2 Y Pixel Offset + + M1.1 31:0 + Slot 1 Y Pixel Offset + + M1.0 31:0 + Slot 0 Y Pixel Offset + + + +4.1.1.4 SIMD16 Per Slot Offset Message Payload +This message payload applies only to the SIMD16 Per Slot Offset message type. The message length is +4. +DWord Bit Description + M0.7 31:0 + Slot 7 X Pixel Offset + + Specifies the X pixel offset for slot 7. + Format = S4 2’s complement representing units of 1/16 pixel. The upper 28 bits are + ignored. + Range = [-8/16, +7/16] + M0.6 31:0 + Slot 6 X Pixel Offset + + M0.5 31:0 + Slot 5 X Pixel Offset + + M0.4 31:0 + Slot 4 X Pixel Offset + + M0.3 31:0 + Slot 3 X Pixel Offset + + M0.2 31:0 + Slot 2 X Pixel Offset + + M0.1 31:0 + Slot 1 X Pixel Offset + + M0.0 31:0 + Slot 0 X Pixel Offset + + M1.7 31:0 + Slot 15 X Pixel Offset + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 96 + DWord Bit Description + M1.6 31:0 + Slot 14 X Pixel Offset + +M1.5 31:0 + Slot 13 X Pixel Offset + +M1.4 31:0 + Slot 12 X Pixel Offset + +M1.3 31:0 + Slot 11 X Pixel Offset + +M1.2 31:0 + Slot 10 X Pixel Offset + +M1.1 31:0 + Slot 9 X Pixel Offset + +M1.0 31:0 + Slot 8 X Pixel Offset + +M2.7 31:0 + Slot 7 Y Pixel Offset + + Specifies the Y pixel offset for slot 7. + Format = S4 2’s complement representing units of 1/16 pixel. The upper 28 bits are + ignored. + Range = [-8/16, +7/16] +M2.6 31:0 + Slot 6 Y Pixel Offset + +M2.5 31:0 + Slot 5 Y Pixel Offset + +M2.4 31:0 + Slot 4 Y Pixel Offset + +M2.3 31:0 + Slot 3 Y Pixel Offset + +M2.2 31:0 + Slot 2 Y Pixel Offset + +M2.1 31:0 + Slot 1 Y Pixel Offset + +M2.0 31:0 + Slot 0 Y Pixel Offset + +M3.7 31:0 + Slot 15 Y Pixel Offset + +M3.6 31:0 + Slot 14 Y Pixel Offset + +M3.5 31:0 + Slot 13 Y Pixel Offset + +M3.4 31:0 + Slot 12 Y Pixel Offset + +M3.3 31:0 + Slot 11 Y Pixel Offset + +M3.2 31:0 + Slot 10 Y Pixel Offset + +M3.1 31:0 + Slot 9 Y Pixel Offset + +M3.0 31:0 + Slot 8 Y Pixel Offset + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 97 + 4.1.2 Writeback Message + +4.1.2.1 SIMD8 +The response length for all SIMD8 messages is 2. The data for each slot is written only if its +corresponding execution mask bit is set. +DWord Bit Description + 31:0 + W0.7 Barycentric[1] for Slot 7 + + Format = IEEE_Float + 31:0 + W0.6 Barycentric[1] for Slot 6 + + 31:0 + W0.5 Barycentric[1] for Slot 5 + + 31:0 + W0.4 Barycentric[1] for Slot 4 + + 31:0 + W0.3 Barycentric[1] for Slot 3 + + 31:0 + W0.2 Barycentric[1] for Slot 2 + + 31:0 + W0.1 Barycentric[1] for Slot 1 + + 31:0 + W0.0 Barycentric[1] for Slot 0 + + 31:0 + W1.7 Barycentric[2] for Slot 7 + + Format = IEEE_Float + 31:0 + W1.6 Barycentric[2] for Slot 6 + + 31:0 + W1.5 Barycentric[2] for Slot 5 + + 31:0 + W1.4 Barycentric[2] for Slot 4 + + 31:0 + W1.3 Barycentric[2] for Slot 3 + + 31:0 + W1.2 Barycentric[2] for Slot 2 + + 31:0 + W1.1 Barycentric[2] for Slot 1 + + 31:0 + W1.0 Barycentric[2] for Slot 0 + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 98 + 4.1.2.2 SIMD16 +The response length for all SIMD16 messages is 4. The data for each slot is written only if its +corresponding execution mask bit is set. +DWord Bit Description + 31:0 + W0.7 Barycentric[1] for Slot 7 + + Format = IEEE_Float + 31:0 + W0.6 Barycentric[1] for Slot 6 + + 31:0 + W0.5 Barycentric[1] for Slot 5 + + 31:0 + W0.4 Barycentric[1] for Slot 4 + + 31:0 + W0.3 Barycentric[1] for Slot 3 + + 31:0 + W0.2 Barycentric[1] for Slot 2 + + 31:0 + W0.1 Barycentric[1] for Slot 1 + + 31:0 + W0.0 Barycentric[1] for Slot 0 + + 31:0 + W1.7 Barycentric[2] for Slot 7 + + Format = IEEE_Float + 31:0 + W1.6 Barycentric[2] for Slot 6 + + 31:0 + W1.5 Barycentric[2] for Slot 5 + + 31:0 + W1.4 Barycentric[2] for Slot 4 + + 31:0 + W1.3 Barycentric[2] for Slot 3 + + 31:0 + W1.2 Barycentric[2] for Slot 2 + + 31:0 + W1.1 Barycentric[2] for Slot 1 + + 31:0 + W1.0 Barycentric[2] for Slot 0 + + Format = IEEE_Float + 31:0 + W2.7 Barycentric[1] for Slot 15 + + 31:0 + W2.6 Barycentric[1] for Slot 14 + + 31:0 + W2.5 Barycentric[1] for Slot 13 + + 31:0 + W2.4 Barycentric[1] for Slot 12 + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 99 + DWord Bit Description + 31:0 + W2.3 Barycentric[1] for Slot 11 + + 31:0 + W2.2 Barycentric[1] for Slot 10 + + 31:0 + W2.1 Barycentric[1] for Slot 9 + + 31:0 + W2.0 Barycentric[1] for Slot 8 + + 31:0 + W3.7 Barycentric[2] for Slot 15 + + 31:0 + W3.6 Barycentric[2] for Slot 14 + + 31:0 + W3.5 Barycentric[2] for Slot 13 + + 31:0 + W3.4 Barycentric[2] for Slot 12 + + 31:0 + W3.3 Barycentric[2] for Slot 11 + + 31:0 + W3.2 Barycentric[2] for Slot 10 + + 31:0 + W3.1 Barycentric[2] for Slot 9 + + 31:0 + W3.0 Barycentric[2] for Slot 8 + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 100 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V4 Pt 2 – 05 12 5/31/2012 101 + \ No newline at end of file diff --git a/docs/ivb_2012/txt/ivb_ihd_os_vol4_part3.txt b/docs/ivb_2012/txt/ivb_ihd_os_vol4_part3.txt new file mode 100644 index 0000000..65f352c --- /dev/null +++ b/docs/ivb_2012/txt/ivb_ihd_os_vol4_part3.txt @@ -0,0 +1,11706 @@ +Intel® OpenSource HD Graphics +Programmer’s Reference Manual (PRM) +Volume 4 Part 3: Execution Unit ISA +(Ivy Bridge) + + +For the 2012 Intel® Core™ Processor Family + + +May 2012 +Revision 1.0 + + +NOTICE: +This document contains information on products in the design phase of development, and Intel +reserves the right to add or remove product features at any time, with or without changes to this +open source documentation. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 + Creative Commons License +You are free to Share — to copy, distribute, display, and perform the work + +Under the following conditions: + +Attribution. You must attribute the work in the manner specified by the author or licensor (but not in any +way that suggests that they endorse you or your use of the work). + +No Derivative Works. You may not alter, transform, or build upon this work. + ® +INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO +LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL +PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR +ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS +SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND +EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES +AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM +OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH +MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS +NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY +OF ITS PARTS. + +Intel may make changes to specifications and product descriptions at any time, without notice. Designers +must not rely on the absence or characteristics of any features or instructions marked "reserved" or +"undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for +conflicts or incompatibilities arising from future changes to them. The information here is subject to +change without notice. Do not finalize a design with this information. + +The products described in this document may contain design defects or errors known as errata which +may cause the product to deviate from published specifications. Current characterized errata are +available on request. + +Implementations of the I2C bus/protocol may require licenses from various entities, including Philips +Electronics N.V. and North American Philips Corporation. + +Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. + +*Other names and brands may be claimed as the property of others. + + +Copyright © 2012, Intel Corporation. All rights reserved. + + + + +2 5/29/2012 Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 + Contents +1. Introduction............................................................................................................................................ 7 + 1.1 Introducing the Execution Unit ............................................................................................................. 7 + 1.2 EU Terms and Acronyms ..................................................................................................................... 9 + 1.3 EU Changes by Processor Generation .............................................................................................. 13 + 1.4 EU Notation ........................................................................................................................................ 13 +2. EU Data Types ..................................................................................................................................... 15 + 2.1 Fundamental Data Types ................................................................................................................... 15 + 2.2 Numeric Data Types .......................................................................................................................... 15 + 2.2.1 Integer Numeric Data Types......................................................................................................... 16 + 2.2.2 Floating-Point Numeric Data Types.............................................................................................. 17 + 2.2.3 Packed Signed Half-Byte Integer Vector ...................................................................................... 18 + 2.2.4 Packed UnSigned Half-Byte Integer Vector ................................................................................. 18 + 2.2.5 Packed Restricted Float Vector .................................................................................................... 19 + 2.3 Floating Point Modes ......................................................................................................................... 21 + 2.3.1 IEEE Floating Point Mode ............................................................................................................ 21 + 2.3.2 Alternative Floating Point Mode.................................................................................................... 25 + 2.4 Type Conversion ................................................................................................................................ 26 + 2.4.1 Float to Integer ............................................................................................................................. 26 + 2.4.2 Integer to Integer with Same or Higher Precision......................................................................... 27 + 2.4.3 Integer to Integer with Lower Precision ........................................................................................ 27 + 2.4.4 Integer to Float ............................................................................................................................. 27 + 2.4.5 Double Precision Float to Single Precision Float ......................................................................... 27 + 2.4.6 Single Precision Float to Double Precision Float ......................................................................... 28 +3. Execution Environment ...................................................................................................................... 29 + 3.1 EU Overview ...................................................................................................................................... 29 + 3.2 Primary Usage Models ....................................................................................................................... 30 + 3.2.1 AOS and SOA Data Structures .................................................................................................... 30 + 3.2.2 SIMD4 Mode of Operation ............................................................................................................ 32 + 3.2.3 SIMD4x2 Mode of Operation ........................................................................................................ 33 + 3.2.4 SIMD16 Mode of Operation .......................................................................................................... 34 + 3.2.5 SIMD8 Mode of Operation ............................................................................................................ 36 + 3.3 Registers and Register Regions ........................................................................................................ 36 + 3.3.1 Register Files ................................................................................................................................ 36 + 3.3.2 GRF Registers .............................................................................................................................. 36 + 3.3.3 ARF Registers .............................................................................................................................. 37 + 3.3.4 Immediate ..................................................................................................................................... 57 + 3.3.5 Region Parameters ....................................................................................................................... 57 + 3.3.6 Region Addressing Modes ........................................................................................................... 62 + 3.3.7 Access Modes .............................................................................................................................. 67 + 3.3.8 Execution Data Type .................................................................................................................... 68 + 3.3.9 Register Region Restrictions ........................................................................................................ 68 + 3.3.10 Destination Operand Description................................................................................................ 72 + 3.4 SIMD Execution Control ..................................................................................................................... 73 + 3.4.1 Predication .................................................................................................................................... 73 + 3.4.2 No Predication .............................................................................................................................. 74 + 3.4.3 Predication with Horizontal Combination ...................................................................................... 74 + 3.4.4 Predication with Vertical Combination .......................................................................................... 76 + 3.5 End of Thread .................................................................................................................................... 76 + 3.6 Assigning Conditional Flags ............................................................................................................... 77 + 3.7 Destination Hazard ............................................................................................................................. 79 + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 3 + 3.8 Non-present Operands....................................................................................................................... 80 + 3.9 Instruction Prefetch ............................................................................................................................ 80 +4. Exceptions ........................................................................................................................................... 81 + 4.1 Exception-Related Architecture Registers ......................................................................................... 81 + 4.2 System Routine .................................................................................................................................. 82 + 4.2.1 Invoking the System Routine ........................................................................................................ 82 + 4.2.2 Returning to the Application Thread ............................................................................................. 83 + 4.2.3 System IP (SIP) ............................................................................................................................ 84 + 4.2.4 System Routine Register Space................................................................................................... 84 + 4.2.5 System Scratch Memory Space ................................................................................................... 84 + 4.2.6 Conditional Instructions Within the System Routine .................................................................... 85 + 4.2.7 Use of NoDDClr ............................................................................................................................ 85 + 4.3 Exception Descriptions....................................................................................................................... 86 + 4.3.1 Illegal Opcode ............................................................................................................................... 86 + 4.3.2 Undefined Opcodes ...................................................................................................................... 86 + 4.3.3 Software Exception ....................................................................................................................... 86 + 4.3.4 Context Save and Restore ........................................................................................................... 87 + 4.4 Events That Do Not Generate Exceptions ......................................................................................... 87 + 4.4.1 Illegal Instruction Format .............................................................................................................. 87 + 4.4.2 Malformed Message ..................................................................................................................... 87 + 4.4.3 GRF Register Out of Bounds........................................................................................................ 87 + 4.4.4 Hung Thread ................................................................................................................................. 88 + 4.4.5 Instruction Fetch Out of Bounds ................................................................................................... 88 + 4.4.6 FPU Math Errors ........................................................................................................................... 88 + 4.4.7 Computational Overflow ............................................................................................................... 88 + 4.5 System Routine Example ................................................................................................................... 88 +5. Instruction Set Summary .................................................................................................................... 92 + 5.1 Instruction Set Characteristics ........................................................................................................... 92 + 5.1.1 5nstruction Operands and Register Regions ............................................................................... 92 + 5.1.2 Instruction Execution .................................................................................................................... 92 + 5.2 Instruction Machine Formats .............................................................................................................. 93 + 5.2.1 EU Instruction Formats ................................................................................................................. 96 + 5.2.2 Common Instruction Fields ......................................................................................................... 100 + 5.2.3 Instruction Operation Doubleword (DW0) .................................................................................. 105 + 5.2.4 Instruction Destination Doubleword (DW1) ................................................................................ 110 + 5.2.5 Instruction Source 0 Doubleword 2 (DW2) ................................................................................. 115 + 5.2.6 Instruction Source 1 Doubleword 3 (DW3) ................................................................................. 119 + 5.3 EU Compact Instructions ................................................................................................................. 122 + 5.3.1 EU Compact Instruction Format ................................................................................................. 123 + 5.4 Opcode Encoding ............................................................................................................................. 127 + 5.4.1 Move and Logic Instructions ....................................................................................................... 127 + 5.4.2 Flow Control Instructions ............................................................................................................ 128 + 5.4.3 Miscellaneous Instructions ......................................................................................................... 129 + 5.4.4 Parallel Arithmetic Instructions ................................................................................................... 130 + 5.4.5 Vector Arithmetic Instructions ..................................................................................................... 131 + 5.4.6 Special Instructions .................................................................................................................... 131 + 5.5 Native Instruction BNF ..................................................................................................................... 132 + 5.5.1 Instruction Groups ...................................................................................................................... 132 + 5.5.2 Destination Register ................................................................................................................... 134 + 5.5.3 Source Register .......................................................................................................................... 134 + 5.5.4 Address Registers ...................................................................................................................... 135 + 5.5.5 Register Files and Register Numbers ........................................................................................ 135 + 5.5.6 Relative Location and Stack Control .......................................................................................... 137 + 5.5.7 Regions ....................................................................................................................................... 137 + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 4 + 5.5.8 Types .......................................................................................................................................... 137 + 5.5.9 Write Mask .................................................................................................................................. 137 + 5.5.10 Swizzle Control ......................................................................................................................... 138 + 5.5.11 Immediate Values ..................................................................................................................... 138 + 5.5.12 Predication and Modifiers ......................................................................................................... 138 + 5.5.13 Instruction Options .................................................................................................................... 139 + 5.6 Instruction Set Summary Tables ...................................................................................................... 139 + 5.7 Accumulator Restrictions ................................................................................................................. 142 +6. Instruction Set Reference ................................................................................................................. 145 + 6.1 Conventions ..................................................................................................................................... 145 + 6.1.1 Pseudo Code Format ................................................................................................................. 145 + 6.1.2 General Macros and Definitions ................................................................................................. 145 + 6.2 Evaluate Write Enable...................................................................................................................... 146 + 6.3 Instruction Description ...................................................................................................................... 147 + 6.4 add – Addition .................................................................................................................................. 147 + 6.5 addc – Integer Addition with Carry ................................................................................................... 148 + 6.6 and – Logic And ............................................................................................................................... 149 + 6.7 asr – Arithmetic Shift Right .............................................................................................................. 150 + 6.8 avg – Average .................................................................................................................................. 151 + 6.9 bfe – Bit Field Extract ....................................................................................................................... 152 + 6.9.1 bfi1 – Bit Field Insert 1 ................................................................................................................ 153 + 6.10 bfi2 – Bit Field Insert 2 .................................................................................................................... 154 + 6.11 bfrev – Reverse Bits ....................................................................................................................... 155 + 6.12 brc – Branch Converging ................................................................................................................ 156 + 6.13 brd – Branch Diverging ................................................................................................................... 157 + 6.14 break – Break ................................................................................................................................. 159 + 6.15 call – Call ........................................................................................................................................ 160 + 6.16 cbit – Count Bits Set ....................................................................................................................... 162 + 6.17 cmp – Compare .............................................................................................................................. 163 + 6.18 cmpn – Compare NaN .................................................................................................................... 165 + 6.19 cont – Continue ............................................................................................................................... 166 + 6.20 dp2 – Dot Product 2 ........................................................................................................................ 167 + 6.21 dp3 – Dot Product 3 ........................................................................................................................ 168 + 6.22 dp4 – Dot Product 4 ........................................................................................................................ 169 + 6.23 dph – Dot Product Homogeneous .................................................................................................. 170 + 6.24 else – Else ...................................................................................................................................... 171 + 6.25 endif – End If ................................................................................................................................... 172 + 6.26 f16to32 – Half Precision Float to Single Precision Float ................................................................ 173 + 6.27 f32to16 – Single Precision Float to Half Precision Float ................................................................ 174 + 6.28 fbh – Find First Bit from MSB Side ................................................................................................. 175 + 6.29 fbl – Find First Bit from LSB Side ................................................................................................... 177 + 6.30 frc – Fraction ................................................................................................................................... 178 + 6.31 halt – Halt ........................................................................................................................................ 179 + 6.32 if – If ................................................................................................................................................ 180 + 6.33 illegal – Illegal ................................................................................................................................. 182 + 6.34 jmpi – Jump Indexed....................................................................................................................... 183 + 6.35 line – Line ....................................................................................................................................... 184 + 6.36 lrp – Linear Interpolation ................................................................................................................. 185 + 6.37 lzd – Leading Zero Detection .......................................................................................................... 186 + 6.38 mac – Multiply Accumulate ............................................................................................................. 187 + 6.39 mach – Multiply Accumulate High .................................................................................................. 188 + 6.40 mad – Multiply Add ......................................................................................................................... 189 + 6.41 math – Extended Math Function ..................................................................................................... 190 + 6.41.1 INV - Inverse ............................................................................................................................. 192 + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 5 + 6.41.2 LOG – Logarithm ...................................................................................................................... 192 + 6.41.3 EXP - Exponent ........................................................................................................................ 192 + 6.41.4 SQRT ........................................................................................................................................ 192 + 6.41.5 RSQ .......................................................................................................................................... 193 + 6.41.6 POW ......................................................................................................................................... 193 + 6.41.7 SIN ............................................................................................................................................ 194 + 6.41.8 COS .......................................................................................................................................... 194 + 6.41.9 INT DIV ..................................................................................................................................... 194 + 6.41.10 mov – Move ............................................................................................................................ 195 + 6.42 6movi – Move Indexed.................................................................................................................... 196 + 6.43 mul – Multiply .................................................................................................................................. 197 + 6.44 nop – No Operation ........................................................................................................................ 200 + 6.45 not – Logic Not ................................................................................................................................ 201 + 6.46 or – Logic Or ................................................................................................................................... 202 + 6.47 pln – Plane ...................................................................................................................................... 203 + 6.48 ret – Return ..................................................................................................................................... 204 + 6.49 rndd – Round Down ........................................................................................................................ 205 + 6.50 rnde – Round to Nearest or Even ................................................................................................... 206 + 6.51 rndu – Round Up ............................................................................................................................ 208 + 6.52 rndz – Round to Zero ...................................................................................................................... 209 + 6.53 sad2 – Sum of Absolute Difference 2 ............................................................................................. 211 + 6.54 sada2 – Sum of Absolute Difference Accumulate 2 ....................................................................... 212 + 6.55 sel – Select ..................................................................................................................................... 213 + 6.56 send Message ................................................................................................................................ 214 + 6.57 sendc – Conditional Send Message ............................................................................................... 218 + 6.58 shl – Shift Left ................................................................................................................................. 219 + 6.59 shr – Shift Right .............................................................................................................................. 220 + 6.60 subb – Integer Subtraction with Borrow.......................................................................................... 221 + 6.61 wait – Wait Notification ................................................................................................................... 222 + 6.62 while – While ................................................................................................................................... 223 + 6.63 xor – Logic Xor ................................................................................................................................ 224 +7. EU Programming Guide .................................................................................................................... 225 + 7.1 Assembler Pragmas ......................................................................................................................... 225 + 7.2 Declarations ..................................................................................................................................... 225 + 7.2.1 Defaults and Defines .................................................................................................................. 225 + 7.2.2 Example Pragma Usages ........................................................................................................... 226 + 7.2.3 Assembly Programming Guideline ............................................................................................. 228 + 7.3 Usage Examples .............................................................................................................................. 228 + 7.3.1 Vector Immediate ....................................................................................................................... 228 + 7.3.2 Destination Mask for DP4 and Destination Dependency Control ............................................... 230 + 7.3.3 Null Register as the Destination ................................................................................................. 231 + 7.3.4 Use of LINE Instruction ............................................................................................................... 231 + 7.3.5 Mask for SEND Instruction ......................................................................................................... 232 + 7.3.6 Flow Control Instructions ............................................................................................................ 235 + 7.3.7 Execution Masking ..................................................................................................................... 237 + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 6 + 1. Introduction +This chapter contains these sections that introduce this volume. + +  Introducing the Execution Unit +  EU Terms and Acronyms +  EU Changes by Processor Generation +  EU Notation + +Subsequent chapters cover: + +  EU Data Types +  Execution Environment +  Exceptions +  Instruction Set Summary +  Instruction Set Reference +  EU Programming Guide + +The EU Programming Guide provides some useful examples and information but is not a complete or +comprehensive programming guide. + + +1.1 Introducing the Execution Unit +This section introduces the Execution Unit (EU), a simple and capable processor within the GPU that +supports graphics processing within the graphics pipelines, can do general purpose computing (GPGPU), +and responds to exceptional conditions via the System Routine. +The EU provides parallelism at two levels: thread and data element. Multiple threads can execute on the +EU; the number executing concurrently depends on the processor and is transparent to EU code. Each +thread has its own registers (GRF and ARF, described below). Most EU instructions operate on arrays of +data elements; the number of data elements is normally the ExecSize (execution size) or number of +channels for the instruction. A channel is a logical unit of execution for data element access, masking, +and flow control within instructions. The number of channels is independent of the number of physical +ALUs or FPUs for a particular graphics processor. +EU native instructions are 128 bits (16 bytes) wide. Some combinations of instruction options can use +compact instruction formats that are 64 bits (8 bytes) wide. Identifying instructions that can be compacted +and creating the compact representations is done by software tools, including compilers and assemblers. +Data manipulation instructions have a destination operand (dst) and one, two, or three source operands +(src0, src1, or src2). The instruction opcode determines the number of source operands. An instruction's +last source operand can be an immediate value rather than a register. +Data read or written by a thread is generally in the thread's GRF (General Register File), 128 general +registers, each 32 bytes. A data element address within the GRF is denoted by a register number (r0 to +r127) and a subregister number. In the instruction syntax, subregister numbers are in units of data +element size. For example, a :d (Signed Doubleword Integer) element can be in subregister 0 to 7, +corresponding to byte numbers in the instruction encoding of 0, 4, ... 28. +Note: The EU cannot directly read or write data in system memory. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 7 + Specialized registers used to implement the ISA are in a distinct per thread Architecture Register File +(ARF). Each such register or group of related registers has its own distinct name. For example, ip is the +instruction pointer and f0 is a flags register. An ARF register can be a src0 or dst operand but not a src1 +or src2 operand. There are restrictions on how particular ARF registers are accessed that should be +understood before directly reading or writing those registers. See the ARF Registers section for more +information. +The EU supports both integer and floating-point data types, as described in the Numeric Data Types +section. +For EU flow control, each channel has its own per-channel instruction pointer (PcIP[n]) and only executes +an instruction when IP == PcIP[n] and any other masks enable the channel. Most flow control instructions +use signed offsets from the current instruction address to reference their targets. Unconditional branches +are done using mov with IP as the destination. Flow control can also use SPF (Single Program Flow) +mode to execute with a single instruction pointer (IP). +The EU ISA supports predication, masking, regioning, swizzling, some type conversions, source +modification, saturation, accumulator updates, and flag updates as part of instruction execution: + +  Predication creates a bit mask (PMask) to enable or disable channels for a particular instruction + execution. Pmask is derived from flag register and subregister values using boolean formulas + determined by the PredCtrl (Predicate Control) and PredInv (Predicate Inversion) instruction fields. + See the Predication section. +  Masking is the overall process of determining which channels execute for a given instruction based + on five factors: +  Number of channels (only channels in [0, ExecSize - 1] can execute) +  Execution mask (EMask) +  Whether the channel is on the instruction (if not in Single Program Flow mode and MaskCtrl is not + NoMask) +  Predicate mask (PMask) +  In Align16 mode, any enabling of channels using the Dst.ChanEn instruction field (if MaskCtrl is + not NoMask). +  Regioning specifies an array of data elements contained in one or two registers, with options for + scattering, interleaving, or repeating data elements in registers using width and stride values, subject + to significant constraints. Regioning also includes access mode (Align1 or Align16) and addressing + mode (Direct or Indirect). See the Registers and Register Regions section. +  Swizzling allows small scale reordering of data elements within groups of four at the input using the + modulo 4 channel names x, y, z, and w. For example, a swizzle of .wzyx with an ExecSize of 8 reads + execution channels 0 to 7 from these input channels: 3, 2, 1, 0, 7, 6, 5, and 4. Swizzling is only + available in the Align16 access mode, described in the Execution Environment chapter. +  Type Conversions do any needed conversion from source data type to execution data type and from + execution data type to destination data type. See Execution Data Type for more information. Each + instruction description indicates what combinations of data types are supported. +  Source Modification modifies a source operand just before doing the requested operation. For a + numeric operation, the choices are: +  No modification (normal). +  - indicating negation. +  (abs) indicating absolute value. +  -(abs) indicating a forced negative value. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 8 + Source modification logically occurs after any conversion from source data type to execution data + type. Each instruction description indicates whether it supports source modification. +  Saturation clamps result values to the nearest value within a saturation range determined by the + destination type. For a floating-point type, the saturation range is [0.0, 1.0]. For an integer type, the + saturation range is the entire range for that type, for example [0, 65535] for the UW (Unsigned Word) + type. Each instruction description indicates whether it supports saturation. +  Accumulator Updates optionally update the accumulator register or registers in the ARF with + destination values as a side effect of instruction execution. The AccWrCtrl instruction field enables + accumulator updates. The Accumulator Disable flag in control register 0 (cr0) can be used to disable + accumulator updates, regardless of AccWrCtrl values; for example, this flag may be used in the + System Routine. +  Flag Updates optionally update a flags register and subregister (f0.0, f0.1, f1.0, or f1.1) with + conditional flags based on the CondModifier (Condition Modifier) instruction field. For example, a + CondModifier of .nz (not zero) assigns flag bits based on whether result elements are not zero (1) or + zero (0). Each instruction description indicates whether it supports the Condition Modifier and any + restrictions on the values supported. + +Note: The EU is not required to execute steps in its internal pipeline sequentially or in order, so long as it +produces correct results. +The assembler syntax uses spaces between operands and encloses ExecSize and any predicate in +parentheses. Instruction mnemonics, register names, conditional modifiers, predicate controls, and type +designators use lowercase. Function names used with the math instruction are UPPERCASE. +( pred ) inst cmod sat ( exec_size ) dst src0 src1 { inst_opt, ... } + +General register destination regions use the syntax rm.n:type. General register directly +addressed source regions use the syntax rm.n:type. You need to +understand more about register regioning to understand all of these terms. +The following example assembly language instruction adds two packed 16-element single-precision Float +arrays in r4/r5 and r2/r3 writing results to r0/r1, only on those channels enabled by the predicate in f0.0 +along with any other applicable masks. + (f0.0) add (16) r0.0<1>:f r2.0<8;8,1>:f r4.0<8;8,1>:f + + + + +1.2 EU Terms and Acronyms +This section provides three tables describing EU general terms and acronyms, EU data types, and EU +selected ARF registers. + +EU General Terms and Acronyms + Term Description + ALT mode A floating-point execution mode that maps +/- inf to +/- fmax, +/- denorm to +/-0, and NaN to +0 at the + FPU inputs and never produces infinities, denormals, or NaN values as outputs. See IEEE mode. + ALU Arithmetic Logic Unit. A functional block that performs integer arithmetic and logic operations, as + distinct from instruction fetch and decode, floating-point operations (see FPU), or messaging. + AOS Array Of Structures. Also see SOA. + ARF Architecture Register File, a distinct register file containing registers used to implement specific ISA + features. For example the Instruction Pointer and condition flags are in ARF registers. See GRF. + byte An 8-bit value aligned on an 8-bit boundary and the basic unit of addressing. Bits within a byte are + denoted 0 to 7 from LSB to MSB. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 9 + Term Description + channel + A logical unit of SIMD data parallel execution within a thread and within the EU. The number of + physical ALUs or FPUs is not directly related to the number of channels. + Supports up to 16 channels. + Supports up to 32 channels. + compact A 64-bit instruction encoded as described in the EU Compact Instructions section. Only some + instruction combinations of instruction parameters can be encoded as compact instructions. See native + instruction. + compressed An instruction that writes to two destination registers. For example a SIMD16 instruction with Float + instruction operands can write channels 0 to 7 to one 32-byte general register and channels 8 to 15 to a second, + consecutive 32-byte general register. + denorm A very small but nonzero number in IEEE mode, with a magnitude less than the smallest normalized + floating-point number representable in a particular floating-point format. Denormals lose precision as + their values approach zero, called gradual underflow. + DWord Doubleword. A 32-bit (4-byte) value aligned on a 32-bit (4-byte) boundary. Bits within a DWord are + denoted 0 to 31 from LSB to MSB. + EOT End of Thread. A flag set on a send or sendc instruction to terminate a thread's execution on the EU. + EU Execution Unit. The single GPU unit described in this volume. This volume describes individual data + parallel execution paths within a thread in the EU as channels. A few fields, like EUID, use EU to refer + to a particular hardware resource used to implement the overall EU. + exception An error or interrupt condition that arises during execution that may transfer control to the System + Routine. Some exceptions can be disabled, preventing such transfers. As defined in this volume, + some errors do not produce exceptions. + ExecSize The number of execution channels for a particular instruction. Channels within that number are + enabled or disabled by various masks. + floating-point Numeric types that allow fractional values and often a wider range than integer types. The EU + supports binary floating-point types including the single precision type and the double precision + typedefined by the IEEE 754 standard. + GEN GEN is sometimes used to refer to Intel's mainstream GPU architecture integrated with recent CPU + generations. + GRF General Register File, a distinct register file containing 128 general registers, r0 to r127. Each general + register is 256 bits (32 bytes), can contain any type of data, and can be accessed with any valid + combination of addressing mode, access mode, and region parameters. A general register is directly + addressed using a register number and subregister number, or indirectly addressed using an address + subregister (index register) and an address immediate offset. + IEEE mode A floating-point execution mode that supports all the kinds of floating-point values described by the + IEEE 754 standard: normalized finite nonzero binary floating-point numbers, signed zeros, signed + infinities, signed denormals that are closer to zero than any normalized value but still nonzero, and + NaN (not a number) values. See ALT mode. +index register An address subregister when used for indirect addressing. + inf Infinity, +inf or -inf, as a floating-point value in IEEE mode. + instruction In this volume, instruction always refers to an EU instruction. + ISA Instruction Set Architecture, processor aspects visible to programs and programmers and independent + of a particular implementation, including data types, registers, memory access, addressing modes, + exceptions, instruction encodings, and the instruction set itself. An ISA does not include instruction + timing, hardware pipeline details, or the number of physical resources (ALUs, FPUs, instruction + decoders) mapped to logical constructs (threads, channels). This volume also includes a + recommended assembly language syntax, closely related to the ISA but logically distinct from it. + LSB Least significant bit. + message A data structure transmitted from a thread to another thread, to a shared function, or to a fixed + function. Message passing is the primary communication mechanism of the GEN architecture. + MSB Most significant bit. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 10 + Term Description + NaN Not a Number. A non-numeric value allowed in the standard single precision and double precision + floating-point number formats. Quiet NaNs propagate through calculations and signaling NaNs cause + exceptions. NaNs are not used in the ALT floating-point mode. + native A 128-bit instruction, the regular instruction format that allows all defined instruction parameters and + instruction options. Some instructions can also be encoded using a 64-bit compact instruction format. + OWord Octword. A 128-bit (16-byte) value aligned on a 128-bit (16-byte) boundary. Bits within an OWord are + denoted 0 to 127 from LSB to MSB. This term is used rarely and may be dropped from future versions + of this volume. + packed + A register region is described as packed if its elements are adjacent in memory, with no intervening + space, no overlap, and no replicated values. If there is more than one element in a row, elements + must be adjacent. If there is more than one row, rows must be adjacent. When two registers are + used, the registers must be adjacent and both must exist. + The immediate vector data types are all described as Packed because each such type packs several + small data elements into a 32-bit immediate value. + + QWord Quadword. A 64-bit (8-byte) value aligned on a 64-bit (8-byte) boundary. Bits within a QWord are + denoted 0 to 63 from LSB to MSB. + region A collection of data locations in registers and subregisters for a source or destination operand. The + associated regioning parameters allow regions to be arrays with various layouts. + register Part of the directly accessible state of an EU program, such as a general register in the GRF or an + architecture register in the ARF. Note that system memory is not directly accessible. + SIMD Single Instruction Multiple Data. Each EU instruction can operate on multiple data elements in parallel, + as specified by the instruction's ExecSize. + SIP System Instruction Pointer, the starting IP value for the System Routine. + SOA Structure of Arrays. Also see AOS. + SPF Single Program Flow. A mode in which every execution channel uses the common instruction pointer, + IP in the ip register. The SPF bit in the control register is 1 to enable SPF and 0 to disable it. If SPF is + disabled, then each execution channel n has its own instruction pointer, PcIP[n] and each channel n is + only eligible to execute, subject to other masking, when PcIP[n] == IP. + swizzle Rearrange data elements within a vector. The EU supports modulo four swizzling of register source + operands at the input in the Align16 access mode. + System A global EU exception handling routine. Any enabled exception from any EU thread transfers control + Routine to this routine. + thread An instance of a program executing on the EU. The life cycle for a thread on the EU starts with the first + instruction after being dispatched to the EU by the Thread Dispatcher and ends after executing a send + or sendc instruction with EOT set, signaling thread termination. Threads can be independent or can + communicate with each other via the Message Gateway shared function. + word A 16-bit (2-byte) value aligned on a 16-bit (2-byte) boundary. Bits within a word are denoted 0 to 15 + from LSB to MSB. Word has denoted a 16-bit unit for Intel processors since the 8086 and 8088 + processors were introduced in 1978. + +The next table lists all EU numeric data types. See the Numeric Data Types section for more information +about each data type. + +EU Numeric Data Types (Listed Alphabetically by Short Name) + Size Size Integral +Short Assembler Long in in or +Name Syntax Name Bytes Bits Float Description + B :b Signed Byte Integer 1 8 I Signed integer in the range -128 to 127. + D :d Signed Doubleword 4 32 I Signed integer in the range -231 to 231 - 1. + Integer + DF :df Double Float 8 64 F Double precision floating-point number. + F :f Float 4 32 F Single precision floating-point number. + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 11 + Size Size Integral +Short Assembler Long in in or +Name Syntax Name Bytes Bits Float Description + UB :ub Unsigned Byte Integer 1 8 I Unsigned integer in the range 0 to 255. + UD :ud Unsigned Doubleword 4 32 I Unsigned integer in the range 0 to 232 - 1. + Integer + UV :uv Packed Unsigned Half 4 32 I Eight 4-bit unsigned integer values each in the + Byte Integer Vector range 0 to 15. Only used as an immediate value. + UW :uw Unsigned Word Integer 2 16 I Unsigned integer in the range 0 to 65,535. + V :v Packed Signed Half Byte 4 32 I Eight 4-bit signed integer values each in the range - + Integer Vector 8 to 7. Only used as an immediate value. + VF :vf Packed Restricted Float 4 32 F Four 8-bit restricted float values. Only used as an + Vector immediate value. + W :w Signed Word Integer 2 16 I Signed integer in the range -32,768 to 32,767. + +The next table lists the seven ARF registers that you should understand first, omitting several others. See +the ARF Registers section for more information, including descriptions of additional registers not listed +below. + +EU Selected ARF Registers (Listed Alphabetically by Name) + Assembler + Name Syntax Description +Accumulators acc0, acc1 + Data registers that can hold integer or floating-point values of various sizes. Many + instructions can implicitly update accumulators with a copy of destination values, done + by setting the AccWrCtrl instruction option. A few instructions, like mac (Multiply + Accumulate), use the accumulators as an implicit source operand, useful for some + iterative calculations. + Address a0.s + Holds subregisters primarily used for indirect addressing. Each subregister is a 16-bit + Register + UW (Unsigned Word) value. For an indirectly addressed operand or element, the + subregister value plus an AddrImm signed offset field determines the byte address + (RegNum and SubRegNum) within the register file (GRF ). + There are 8 address subregisters. + + Control cr0.s Contains bit fields for floating-point modes, flow control modes, and exception + Register enable/disable. Also contains exception indicator flags and saves the AIP (Application + Instruction Pointer) on transferring control to the System Routine to handle an exception. + Flags fr.s Used as the outputs for various channel conditional signals, such as equality/zero or + overflow. Used as the inputs for predication. There are two 32-bit flags registers each + containing two 16-bit subregisters. + Instruction ip + References the current instruction in memory, as an unsigned offset from the General + Pointer + State Base Address. IP is the thread's overall instruction pointer. Each channel n can + (IP) + have its own instruction pointer (PcIP[n]). If not in Single Program Flow mode (SPF is 0) + then only those channels where PcIP[n] == IP are eligible to execute the instruction, if + enabled by all other applicable masks. +Null Register null + Indicates a non-existent operand. Unused operands in the instruction format, like the + unused second source operand field in a mov instruction, are encoded as null. + For present source operands, reading a null source operand returns undefined values. + For null destination operands, results are discarded but any implicit updates to + accumulators or flags still occur. +State Register sr0.s Contains thread identification and scheduling fields, and mask fields for enabling or + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 12 + Assembler + Name Syntax Description + disabling channels. + + + +1.3 EU Changes by Processor Generation +This section describes how the EU changes for particular processor generations. Instruction compaction +tables can differ for each generation, so that is not mentioned in these lists. Particular readers and +audiences can see only certain content in this section. Errata and workarounds for particular generations, +SKUs, or steppings are not included in these lists. Some small changes in instruction layouts are not +included in these lists. +Ivy Bridge +These features or behaviors are added , continuing to later generations: + +  The maximum ExecSize increases to 32, for byte or word operands. +  Increase the number of flag registers from one to two. +  Add the NibCtrl field, used with QtrCtrl to select groups of channels or flags. +  Add the DF (Double Float) data type, the first time an 8-byte data type is supported. DF only + supports the IEEE floating-point mode and not the ALT floating-point mode. +  Add a shared source data type field and a destination data type field for instructions with three + source operands, allowing F (Float), DF (Double Float), D (Signed Doubleword Integer), or UD + (Unsigned Doubleword Integer) types to be specified. +  Add bit manipulation instructions: bfi1, bfi2, bfrev, cbit, fbh, and fbl. +  Add the integer addc (Add with Carry) and subb (Subtract with Borrow) instructions. +  Add the brc (Branch Converging) and brd (Branch Diverging) instructions. +  For the cmp and cmpn instructions, relax the accumulator restrictions. +  For the sel instruction, remove the accumulator restriction. +  Add the Rounding Mode and Double Precision Denorm Mode fields in Control Register 0. + +These features or behaviors are specific to and may not continue to later generations: + +  Each DF (Double Float) operand uses an element size of 4 rather than 8 and all regioning + parameters are twice what the values would be based on the true element size: ExecSize, Width, + HorzStride, and VertStride. Each DF operand uses a pair of channels and all masking and swizzling + should be adjusted appropriately. +  The f16to32 and f32to16 instructions convert between half-precision float and Float. +  The mul instruction limits integer multiplication involving DWords so that only the low 16 bits of src1 + are used even if src1 is a DWord. +  The sel (Select) instruction does not support an ExecSize of 32. +  SIMD16 execution on DWords is not allowed when an accumulator is an explicit source or + destination operand. + + +1.4 EU Notation +The Courier New font is used for code examples and for the Syntax, Format, and Pseudocode sections +in the instruction reference. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 13 + The italic font style is used for instruction mnemonics outside of code (e.g., the send instruction), for +syntactic production names, for key values in algorithms (ExecSize), and to emphasize a word or phrase. +For example: When bit 10 is set, the destination register scoreboard is not cleared. +The bold font weight is used for the short name and long name of a bit field being described, for value +names being defined, for syntactic terminals, for unnumbered subheadings, and for the terms Note, +Erratum/Errata, or Workaround used to introduce a paragraph. +Bit field names and value names used where not being defined and not as syntactic terminals are in plain +text. +Bit field values in hex use the 0x prefix. The BSpec currently uses the 0x prefix for hex in some parts and +the h suffix for hex in other parts. For single bits, values appear as simply 0 or 1. For multi-bit binary +values, the appropriate number of binary digits appears with a b suffix. +Instruction mnemonics are lowercase. Function names invoked using the math instruction are +UPPERCASE. For example, SQRT. +Tables describing bit field layouts or registers proceed from most significant to least significant bits. +Figures showing bit fields or registers show most significant bits on the left and least significant bits on the +right. +Any bit, field, or register described as Reserved should be regarded as undefined and unpredictable. +Such bits should be treated as follows: + +  When testing values, do not depend on the state of reserved bits. Mask out or otherwise ignore such + bits. +  Sometimes software must initialize reserved bits. For example, a compiler must write complete + instruction values when creating an instruction stream, including reserved bits. In such cases, write + reserved bits as zeros unless otherwise indicated. +  Do not use reserved bits as extra storage for software-defined values; put nothing in such bits. +  When saving state and restoring state, save and restore any reserved bits as well. +  Do not assume that reserved bits are invariant between explicit writes. Software should function + even if reserved bits change in undefined and unpredictable ways. + +Any value, encoding, or combination of values or encodings described as Reserved must not be used. +The EU's behavior is undefined in this case. +When a combination of instruction parameters or an EU state is described as producing undefined results +or behavior, do not assume that undefined results or behavior are confined to specific instructions, +operands, registers, or channels. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 14 + 2. EU Data Types +2.1 Fundamental Data Types +The fundamental data types in the GEN architecture are halfbyte, byte, word, doubleword (DW), +quadword (QW), double quadword (DQ) and quad quadword (QQ). They are defined based on the +number of bits of the data type, ranging from 4 bits to 256 bits. As shown in Fundamental Data Types, a +halfbyte contains 4 bits, a byte contains 8 bits, a word contains two bytes, and a doubleword (dword) +contains two words, and so on. Halfbyte is a special data type such that it cannot be accessed directly as +standalone data element. It is only allowed as a subfield of the numeric data type of “packed signed +halfbyte integer vector” described in the next section. + +Fundamental data types + + + + +With the exception of halfbyte, the access of a data element to/from a GEN register or to/from memory +must be aligned on the natural boundaries of the data type. The natural boundary for a word has an even- +numbered address in unit of byte. The natural boundary for a doubleword has an address divisible by 4 +bytes. Similarly, the natural boundary for a quadword, double quadword and quad quadword has an +address divisible by 8, 16, and 32 bytes, respectively. Quadword, double quadword and quad quadword +do not have corresponding numeric data type. Instead, they are used to describe a group (a vector) of +numeric data elements of smaller size align to larger natural boundaries. + + +2.2 Numeric Data Types +The numeric data types defined in the GEN architecture include signed and unsigned integers and +floating-point numbers (floats) of various sizes. These numeric data types are described below. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 15 + 2.2.1 Integer Numeric Data Types +The Execution Unit supports the following integer data types. Signed integer types use two's complement +representation for negative numbers. + +UB: Unsigned Byte, 8-bit Unsigned Integer +7 0 + + + +B: Byte, 8-bit Signed Integer +76 0 +S + +UW: Unsigned Word, 16-bit Unsigned Integer +1 +5 0 + + + +W: Word, 16-bit Signed Integer +11 +54 0 +S + +UD: Unsigned Doubleword, 32-bit Unsigned Integer +3 +1 0 + + + +D: Doubleword, 32-bit Signed Integer +33 +10 0 +S + +UV: Packed Unsigned Half-Byte Integer Vector, 8 x 4-Bit Unsigned Integer +3 2 2 2 2 2 1 1 1 1 1 +1 8 7 4 3 0 9 6 5 2 1 8 7 4 3 0 + + + + +V: Packed Signed Half-Byte Integer Vector, 8 x 4-Bit Signed Integer +3 2 2 2 2 2 1 1 1 1 1 +1 8 7 4 3 0 9 6 5 2 1 8 7 4 3 0 +S S S S S S S S + + +The following table summarizes the EU integer data types. + +Execution Unit Integer Data Types +Notation Size in Bits Name Range + UB 8 Unsigned Byte Integer [0, 255] + B 8 Signed Byte Integer [-128, 127] + UW 16 Unsigned Word Integer [0, 65535] + W 16 Signed Word Integer [-32768, 32767] + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 16 + Notation Size in Bits Name Range + UD 32 Unsigned Doubleword Integer [0, 232 – 1] + D 32 Signed Doubleword Integer [–231, 231 – 1] + UV 32 Packed Unsigned Half-Byte [0, 15] in each of eight 4-bit immediate vector elements. + Integer Vector + V 32 Packed Signed Half-Byte [-8, 7] in each of eight 4-bit immediate vector elements. + Integer Vector + +Restriction: Only a raw move using the mov instruction supports a packed byte destination register +region. For information about raw moves, refer to the Description in mov – Move. + + +2.2.2 Floating-Point Numeric Data Types +The Execution Unit supports the following floating-point data types. The Float and Double Float types use +the single precision and double precision formats specified in IEEE Standard 754-1985 for Binary +Floating-Point Arithmetic. In the ALT floating-point mode, representations for infinities, denorms, and +NaNs within those formats are not used. The EU does not support the double extended precision (80-bit) +floating-point format found in the x86/x87/Intel 64 floating-point registers. All floating-point formats are +signed using signed magnitude representation (a distinct sign bit, separate from the magnitude +information). +The F (Float) type supports both the ALT and IEEE floating-point modes, controlled by the Single +Precision Floating-Point Mode bit in the Control Register. +In IEEE mode, F calculations flush denormalized values to zero and gradual underflow is not supported. +The DF (Double Float) type only supports the IEEE floating-point mode. Whether DF calculations support +denorms or flush denormalized values to zero is controlled by the Double Precision Denorm Mode bit in +the Control Register. + +F: Float, 32-bit Single-Precision Floating-Point Number +3 3 2 2 +1 0 3 2 0 +S biased fraction + exponent + +DF: Double Float, 64-bit Double-Precision Floating-Point Number+ +6 6 5 5 +3 2 2 1 0 +S biased exponent fraction + +VF: Packed Restricted Float Vector, 4 x 8-Bit Restricted Precision Floating-Point Number +3 3 2 2 2 2 2 2 1 1 1 1 1 1 +1 0 8 7 4 3 2 0 9 6 5 4 2 1 8 7 6 4 3 0 +S b. exp. frac. S b. exp. frac. S b. exp. frac. S b. exp. frac. + + +The following table summarizes the EU floating-point data types. + +Execution Unit Floating-Point Data Types + Size in +Notation Bits Name Range + F 32 Float + Single precision, 1 sign bit, 8 bits for the biased exponent, and 23 bits for the + significand: + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 17 + Size in +Notation Bits Name Range + [–(2–2-23)127…–2-149, 0.0, 2-149… (2–2-23)127] + + DF 64 Double Float + Double precision, 1 sign bit, 11 bits for the biased exponent, and 52 bits for the + significand: + [–(2–2-52)1023…–2-1074, 0.0, 2-1074… (2–2-52)1023] + VF 32 Packed + Restricted precision. Each of four 8-bit immediate vector elements has 1 sign + Restricted + bit, + Float Vector + 3 bits for the biased exponent (bias of 3), and 4 bits for the significand: + [–31…–0.125, 0, 0.125… 31] + + + +2.2.3 Packed Signed Half-Byte Integer Vector +A packed signed halfbyte integer vector consists of 8 signed halfbyte integers contained in a doubleword. +Each signed halfbyte integer element has a range from -8 to 7 with the sign on bit 3. This numeric data +type is only used by an immediate source operand of doubleword in a GEN instruction. It cannot be used +for the destination operand or a non-immediate source operand. GEN hardware converts the vector into +an 8-element signed word vector by sign extension. This is illustrated in Numeric Data Types. +The short hand format notation for a packed signed half-byte vector is V. + +Converting a Packed Half-Byte Vector to a 128-bit Signed Integer Vector + + + + +2.2.4 Packed UnSigned Half-Byte Integer Vector +A packed unsigned halfbyte integer vector consists of 8 unsigned halfbyte integers contained in a +doubleword. Each unsigned halfbyte integer element has a range from 0 to 15. This numeric data type is +only used by an immediate source operand of doubleword in a GEN instruction. It cannot be used for the + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 18 + destination operand or a non-immediate source operand. GEN hardware converts the vector into an 8- +element signed word vector. + + + + +2.2.5 Packed Restricted Float Vector +A packed restricted float vector consists of 4 8-bit restricted floats contained in a doubleword. Each +restricted float has the sign at bit 7, a 3-bit coded exponent in bits 4 to 6, a 4-bit fraction in bits 0 to 3, and +an implied integer 1. The exponent is in excess-3 format – having a bias of 3. Restricted float provides +zero, positive/negative normalized numbers with a small range (3-bit exponent) and small precision (4-bit +fraction). This numeric data type is only used by an immediate source operand of doubleword in a GEN +instruction. It cannot be used for the destination operand, or a non-immediate source operand. +The following figure shows how to convert an 8-bit restricted float into a single precision float. Converting +a 3-bit exponent with a bias of 3 to an 8-bit exponent with a bias of 127 is by adding 4, or equivalently +copying bit 2 to bit 7 and putting the inverted bit 2 to bits 6:2. A special logic is also needed to take care of +positive/negative zeros. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 19 + Conversion from a Restricted 8-bit Float to a Single-Precision Float + + + + +The following table shows all possible numbers of the restricted 8-bit float. Only normalized float numbers +can be represented, including positive and negative zero, and positive and negative finite numbers. +Normalized infinites, NaN, and denormalized float numbers cannot be represented by this type. It should +be noted that this 8-bit floating point format does not follow IEEE-754 convention in describing numbers +with small magnitudes. Specifically, when the exponent field is zero and the fraction field is not zero, an +implied one is still present instead of taking a denormalized form (without an implied one). This results in +a simple implementation but with a smaller dynamic range – the magnitude of the smallest non-zero +number is 0.125. + +Examples of Restricted 8-bit Float Numbers + Extended Floating Number + Class Hex # Sign [7] Exponent [6:4] Fraction [3:0] 8-bit Exponent in Decimal +Positive Normalized Float 0x70-0x7F 0 111 0000 … 1111 1000 0011 16 … 31 + 0x60-0x6F 0 110 0000 … 1111 1000 0010 8 … 15.5 + 0x50-0x5F 0 101 0000 … 1111 1000 0001 4 … 7.75 + 0x40-0x4F 0 100 0000 … 1111 1000 0000 2 … 3.875 + 0x30-0x3F 0 011 0000 … 1111 0111 1111 1 … 1.9375 + 0x20-0x2F 0 010 0000 … 1111 0111 1110 0.5 … 0.96875 + 0x10-0x1F 0 001 0000 … 1111 0111 1101 0.25 … 0.484375 + 0x01-0x0F 0 000 0001 … 1111 0111 1100 0.125 … 0.2421875 + 0x00 0 000 0000 0000 0000 0 (+zero) +Negative Normalized Float 0xF0-0xFF 1 111 0000 … 1111 1000 0011 -16 … -31 + 0xE0-0xEF 1 110 0000 … 1111 1000 0010 -8 … -15.5 + 0xD0-0xDF 1 101 0000 … 1111 1000 0001 -4 … -7.75 + 0xC0-0xCF 1 100 0000 … 1111 1000 0000 -2 … -3.875 + 0xB0-0xBF 1 011 0000 … 1111 0111 1111 -1 … -1.9375 + 0xA0-0xAF 1 010 0000 … 1111 0111 1110 -0.5 … -0.96875 + 0x90-0x9F 1 001 0000 … 1111 0111 1101 -0.25 … -0.484375 + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 20 + Extended Floating Number + Class Hex # Sign [7] Exponent [6:4] Fraction [3:0] 8-bit Exponent in Decimal + 0x81-0x8F 1 000 0001 … 1111 0111 1100 -0.125 … -0.2421875 + 0x80 1 000 0000 0000 0000 -0 (-zero) + +The following figure shows the conversion of a packed exponent-only float to a 4-element vector of single +precision floats. +The shorthand format notation for a packed signed half-byte vector is VF. + + + + +2.3 Floating Point Modes +GEN architecture supports two floating point operation modes, namely IEEE floating point mode (IEEE +mode) and alternative floating point mode (ALT mode). Both modes follow mostly the requirements in +IEEE-754 but with different deviations. The deviations will be described in details in later sections. The +primary difference between these modes is on the handling of Infs, NaNs and denorms. The IEEE floating +point mode may be used to support newer versions of 3D graphics API Shaders and the alternative +floating point mode may be used to support early Shader versions. +These two modes are supported by all units that perform floating point computations, including GEN +execution units, GEN shared functions like Extended Math, the Sampler and the Render Cache color +calculator, and fixed functions like VF, Clipper, SF and WIZ. Host software sets floating point mode +through the fixed function state descriptors for 3D pipeline and the interface descriptor for media pipeline. +Therefore different modes may be associated with different threads running concurrently. Floating point +mode control for EU and shared functions are based on the floating point mode field (bit 0) of cr0 register. + + +2.3.1 IEEE Floating Point Mode + +2.3.1.1 Partial Listing of Honored IEEE-754 Rules +Here is a summary of expected 32-bit floating point behaviors in GEN architecture. Refer to IEEE-754 for +topics not mentioned. + +  INF – INF = NaN +  0 * (+/–)INF = NaN +  1 / (+INF) = +0 and 1 / (–INF) = –0 + o (+/–)INF / (+/–)INF = NaN as A/B = A * (1/B) + +  INV (+0) = RSQ (+0) = +INF, INV (–0) = RSQ (–0) = –INF, and SQRT (–0) = –0 +  RSQ (–finite) = SQRT (–finite) = NaN + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 21 +  LOG (+0) = LOG (–0) = –INF, LOG (–finite) = LOG (–INF) = NaN +  NaN (any OP) any-value = NaN with one exception for min/max mentioned below. Resulting NaN + may have different bit pattern than the source NaN. +  Normal comparison with conditional modifier of EQ, GT, GE, LT, LE, when either or both operands is + NaN, returns FALSE. Normal comparison of NE, when either or both operands is NaN, returns + TRUE. + o Note: Normal comparison is either a cmp instruction or an instruction with conditional + modifier + +  Special comparison cmpn with conditional modifier of EQ, GT, GE, LT, LE, when the second source + operand is NaN, returns TRUE, regardless of the first source operand, and when the second source + operand is not NaN, but first one is, returns FALSE. Cmpn of NE, when the second source operand + is NaN, returns FALSE, regardless of the first source operand, and when the second source operand + is not NaN, but first one is, returns TRUE. + o This is used to support the proposed IEEE-754R rule on min or max operations. For + which, if only one operand is NaN, min and max operations return the other operand + as the result. + +  Both normal and special comparisons of any non-NaN value against +/– INF return exact result + according to the conditional modifier. This is because that infinities are exact representation in the + sense that +INF = +INF and –INF = –INF. + o NaN is unordered in the sense that NaN != NaN. + +  IEEE-754 requires floating point operations to produce a result that is the nearest representable + value to an infinitely precise result, known as "round to nearest even" (RTNE). 32-bit floating point + operations must produce a result that is within 0.5 Unit-Last-Place (0.5 ULP) of the infinitely precise + result. This applies to addition, subtraction, and multiplication. +  All arithmetic floating point instructions does Round To Nearest Even at the end of the computation, + except the round instructions. + +2.3.1.2 Complete Listing of Deviations or Additional Requirements vs. IEEE- + 754 +For a result that cannot be represented precisely by the floating point format, the EU uses rounding to +nearest or even to produce a result that is within 0.5 Unit-Last-Place(0.5 ULP) of the infinitely precise +result. +The rounding mode is specified by the Rounding Mode field in the Control Register. +The EU can report floating point overflow and NaN into conditional flags. Hewever, there is no support for +floating point exceptions, status bits, or traps. +] handle denorms as follows: + +  Single precision (F, Float) denorms are flushed to sign-preserved zero on input and output of any + floating-point mathematical operation. +  Double precision (DF, Double Float) denorms are kept or flushed in mathematical operations based + on the Double Precision Denorm Mode in the Control Register. +  Denorms are not flushed for format conversions, irrespective of any denorm mode. +  Denorms are not flushed for raw mov operations. For information about raw mov operations, refer to + the Description in mov – Move. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 22 +  Input denorms are not flushed for half precision to single precision floating-point conversion. + +Other information regarding floating-point behaviors: + +  NaN input to an operation always produces NaN on output, however the exact bit pattern of the NaN + is not required to stay the same (unless the operation is a raw “mov” instruction which does not alter + data at all.) +  x*1.0f must always result in x (except denorm flushed and possible bit pattern change for NaN). +  x +/- 0.0f must always result in x (except denorm flushed and possible bit pattern change for NaN). + But -0 + 0 = +0. +  Fused operations (such as mac, dp4, dp3, etc.) may produce intermediate results out of 32-bit float + range, but whose final results would be within 32-bit float range if intermediate results were kept at + greater precision. In this case, implementations are permitted to produce either the correct result, or + else ±inf. Thus, compatibility between a fused operation, such as mac, with the unfused equivalent, + mul followed by add in this case, is not guaranteed. +  As the accumulator registers have more precision than 32-bit float, any instruction with accumulator + as a source/destination operand may produce a different result than that using GRF registers. +  API Shader divide operations are implemented as x*(1.0f/y). With the two-step method, x*(1.0f/y), + the multiply and the divide each independently operate at the 32-bit floating point precision level + (accuracy to 1 ULP). +  See the Type Conversion section for rules on converting to and from float representations. + +2.3.1.3 Comparison of Floating Point Numbers +The following tables detail the rules for floating point comparison. In the tables, “+/-Fin” stands for a +positive or negative finite precision floating point number. Result is either a true (T) or false (F). Each row +corresponds to a fixed src0 and each column corresponds to a fixed src1. When comparing two positive +finite numbers (or two negative finite numbers), the result can be T or F depending on the values. +Therefore, the corresponding fields in the following tables are marked as T/F. When comparing two +double float numbers, the result can be T or F depending on the values and the denorm mode +(enabled/disabled). The corresponding fields in the following tables are marked T/F*. + +Results of “Greater-Than” Comparison – CMP. + +src0 src1 -inf -Fin -denorm -0 +0 +denorm +Fin +inf NaN + -inf F F F F F F F F F + -Fin T T/F F F F F F F F + -denorm T T T/F* F F F F F F + -0 T T T/F* F F F F F F + +0 T T T/F* F F F F F F ++denorm T T T/F* T/F* T/F* T/F* F F F + +Fin T T T T T T T T/F F + +inf T T T T T T T T F + NaN F F F F F F F F F + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 23 + Results of “Less-Than” Comparison – CMP.L + src0 src1 -inf -Fin -denorm -0 +0 +denorm +Fin +inf NaN + F T T T T T T T F + -inf + + F T/F T T T T T T F + -Fin + + F F T/F* T/F* T/F* T/F* T T F + -denorm + + F F F F F T/F* T T F + -0 + + F F F F F T/F* T T F + +0 + + F F F F F T/F* T T F + +denorm + + F F F F F F T/F T F + +Fin + + F F F F F F F F F + +inf + + F F F F F F F F F + NaN + + +Results of “Equal-To” Comparison – CMP.E + src0 src1 -inf -Fin -denorm -0 +0 +denorm +Fin +inf NaN + -inf T F F F F F F F F + -Fin F T/F F F F F F F F + -denorm F F T/F* T/F* T/F* T/F* F F F + -0 F F T/F* T T T/F* F F F + +0 F F T/F* T T T/F* F F F + +denorm F F T/F* T/F* T/F* T/F* F F F + +Fin F F F F F F T/F F F + +inf F F F F F F F T F + NaN F F F F F F F F F + +Results of “Not-Equal-To” Comparison – CMP.NE + src0 src1 -inf -Fin -denorm -0 +0 +denorm +Fin +inf NaN + -inf FALSE T T T T T T T T + -Fin T T/F T T T T T T T + -denorm T T T/F* T/F* T/F* T/F* T T T + -0 T T T/F* FALSE FALSE T/F* T T T + +0 T T T/F* FALSE FALSE T/F* T T T + +denorm T T T/F* T/F* T/F* T/F* T T T + +Fin T T T T T T T/F T T + +inf T T T T T T T FALSE T + NaN T T T T T T T T T + +Results of “Less-Than Or Equal-To” Comparison – CMP.LE + src0 src1 -inf -Fin -denorm -0 +0 +denorm +Fin +inf NaN + -inf T T T T T T T T F + -Fin F T/F T T T T T T F + -denorm F F T/F* T/F* T/F* T/F* T T F + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 24 + src0 src1 -inf -Fin -denorm -0 +0 +denorm +Fin +inf NaN + -0 F F T/F* T T T/F* T T F + +0 F F T/F* T T T/F* T T F + +denorm F F T/F* T/F* T/F* T/F* T T F + +Fin F F F F F F T/F T F + +inf F F F F F F F T F + NaN F F F F F F F F F + +Results of “Greater-Than or Equal-To” Comparison – CMP.GE + src0 src1 -inf -Fin -denorm -0 +0 +denorm +Fin +inf NaN + -inf T F F F F F F F F + -Fin T T/F F F F F F F F + -denorm T T T/F* T/F* T/F* T/F* F F F + -0 T T T/F* T T T/F* F F F + +0 T T T/F* T T T/F* F F F + +denorm T T T/F* T/F* T/F* T/F* F F F + +Fin T T T T T T T/F F F + +inf T T T T T T T T F + NaN F F F F F F F F F + + +2.3.1.4 Min/Max of Floating Point Numbers +A special comparison called Compare-NaN is introduced in the GEN architecture to handle the difference +of above mentioned floating-point comparison and the rules on supporting MIN/MAX. To compute the +MIN or MAX of two floating-point numbers, if one of the numbers is NaN and the other is not, MIN or MAX +of the two numbers returns the one that is not NaN. When two numbers are NaN, MIN or MAX of the two +numbers returns source1. +Min and Max is supported by conditional select. +Note even though f0.0 is specified in the instruction, the flag register is not touched by this instruction. +The following tables detail the rules for this special compare-NaN operation for floating-point numbers. +Notice that excepting “Not-Equal-To” comparison-NaN, last columns in all other tables have ‘T’. + + +2.3.2 Alternative Floating Point Mode +The key characteristics of the alternative floating point mode is that NaN, Inf and denorm are not +expected for an application to pass into the graphics pipeline, and the graphics hardware must not +generate NaN, Inf or denorm as computation result. For example, a result that is larger than the maximum +representable floating point number is expected to be flushed to the largest representable floating point +number, i.e., +fmax. The fmax has an exponent of 0xFE and a mantissa of all one’s, which is the same for +IEEE floating point mode. +Note that this mode is applicable ONLY to Single Precision Float datatype. +This also implies that ALT mode is not supported when Single precision datatype is involved in format +conversion to double precision of half precision. +Here is the complete list of the differences of legacy graphics mode from the relaxed IEEE-754 floating +point mode. + +  Any +/- INF result must be flushed to +/- fmax, instead of being output as +/- INF. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 25 +  Extended mathematics functions of log(), rsq() and sqrt() take the absolute value of the sources + before computation to avoid generating INF and NaN results. +Alternative Floating Point Mode shows the support of these differences in various hardware units. + +Supported Legacy Float Mode and Impacted Units + IEEE-754 Deviations VF Clipper SF WIZ EU EM Sampler RC + Y Y Y Y Y Y Y Y + Any +/- INF result flushed to + +/- fmax +Log, rsq, sqrt take abs() of sources N/A N/A N/A N/A N/A Y N/A N/A + +Alternative Floating Point Mode shows some of the desired or recommended alternative floating point +mode behaviors that do not have hardware design impact. The reasons of not needing special hardware +support for these items are also provided. This is based on the compliance requirement that can be +found in the DirectX 9 specification: “Handling of NaNs, Infs, and denorms is undefined. Applications +should not pass in such values into the graphics pipeline.” + +Dismissed legacy behaviors + Suggested IEEE-754 Deviations Reason for Dismiss +Mov forces (+/-)INF to (+/-)fmax (+/-)INF is never present as input +(+/-)INF – (+/-)INF = +/- fmax instead of NaN (+/-)INF is never present as input +Denorm must be flushed to zero in all cases (including Denorm is never present as input +trivial mov and point sampling) +Anything*0=0 (including NaN*0=0 and INF*0=0) NaN and INF are never present as input +Except propagated NaN, NaN is never generated NaN is never present as input and GEN never generates + NaN based on rules in the previous table +An input NaN gets propagated excepting (a)-(d) NaN is never present as input +(a) Rcp (and rsq) of 0 yields fmax N/A, as it is already covered by the general rule “Any +/- INF + result flushed to +/- fmax” +(b) Sampler honors 0/0 = 0 as if (1/0)*0 There is no divide in Sampler +I Rcp (and rsq) of INF yields +/- 0 (+/-)INF is never present as input +(d) Sampler honors INF/INF = 0 as if (1/INF)=0 There is no divide in Sampler +followed by Anything*0 = 0 + + + +2.4 Type Conversion + +2.4.1 Float to Integer +Converting from float to integer is based on rounding toward zero. If the floating point value is +0, -0, ++Denorm, -Denorm, +NaN –r -NaN, the resulting integer value is always 0. If the floating point value is +positive infinity (or negative infinity), the conversion result takes the largest (or the smallest) represent- +able integer value. If the floating point value is larger (or smaller) than the largest (or the smallest) +represent-able integer value, the conversion result takes the largest (or the smallest) represent-able +integer value. The following table shows these special cases. The last two rows are just examples. They +can be any number outside the represent-able range of the output integer type (UD, D, UW, W, UB and +B). + Input Format Output Format + F UD D UW W UB B + +/- Zero 00000000 00000000 00000000 00000000 00000000 00000000 + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 26 + Input Format Output Format + F UD D UW W UB B + +/- Denorm 00000000 00000000 00000000 00000000 00000000 00000000 + NAN 00000000 00000000 00000000 00000000 00000000 00000000 + -NAN 00000000 00000000 00000000 00000000 00000000 00000000 + INF FFFFFFFF 7FFFFFFF 0000FFFF 00007FFF 000000FF 0000007F + -INF 00000000 80000000 00000000 00008000 00000000 00000080 + FFFFFFFF 7FFFFFFF 0000FFFF 00007FFF 000000FF 0000007F + +232 (*) + 00000000 80000000 00000000 00008000 00000000 00000080 + -232-1 (*) + + + +2.4.2 Integer to Integer with Same or Higher Precision +Converting an unsigned integer to a signed or an unsigned integer with higher precision is based on zero +extension. +Converting an unsigned integer to a signed integer with the same precision is based on modular wrap- +around. Without saturation, a larger than represent-able number becomes a negative number. With +saturation, a larger than represent-able number is saturated to the largest positive represent-able +number. +Converting a signed integer to a signed integer with higher precision is based on sign extension. +Converting a signed integer to an unsigned integer with higher precision is based on sign extension. +Without saturation, a negative number becomes a large positive number with the sign bit wrapped-up. +With saturation, a negative number is saturated to zero. + + +2.4.3 Integer to Integer with Lower Precision +Converting a signed or an unsigned integer to a signed or an unsigned integer with lower precision is +based on bit truncation. Without saturation, only the lower bits are kept in the output regardless of the +sign-ness of input and output. With saturation, a number that is outside the represent-able range is +saturated to the closest represent-able value. + + +2.4.4 Integer to Float +Converting a signed or an unsigned integer to a single precision float number is to round to the closest +representable float number. For any integer number with magnitude less than or equal to 24 bits, resulting +float number is a precise representation of the input. However, if it is more than 24 bits, by default a +“round to nearest even” is performed. + + +2.4.5 Double Precision Float to Single Precision Float +Converting a double precision floating-point number to a single precision floating-point number uses the +round to zero rounding mode. + Double Precision Float Single Precision Float +-inf -inf + +-finite -finite/-denorm/-0 + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 27 + Double Precision Float Single Precision Float +-denorm -0 + +-0 -0 + ++0 +0 + ++denorm +0 + ++finite +finite/+denorm/+0 + ++inf +inf + +NaN NaN + +The upper Dword of every Qword will be written with undefined value when converting DF to F. + + +2.4.6 Single Precision Float to Double Precision Float +Converting a single precision floating-point number to a double precision floating-point number will +produce a precise representation of the input. + Single Precision Float Double Precision Float +-inf -inf +-finite -finite +-denorm -finite +-0 -0 ++0 +0 ++denorm +finite ++finite +finite ++inf +inf +NaN NaN + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 28 + 3. Execution Environment +3.1 EU Overview +The GEN instruction set is a general-purpose data-parallel instruction set optimized for graphics and +media computations. Support for 3D graphics API (Application Programming Interface) Shader +instructions is mostly native, meaning that GEN efficiently executes Shader programs. Depending on +Shader program operation modes (for example, a Vertex Shader may be executed on a base of a vertex +pair, while a Pixel Shader may be executed on a base of a 16-pixel group), translation from 3D graphics +API Shader instruction streams into GEN native instructions may be required. In addition, there are many +specific capabilities that accelerate media applications. The following feature list summarizes the GEN +instruction set architecture: + +  SIMD (single instruction multiple data) instructions. The maximum number of data elements per + instruction depends on the data type. +  SIMD parallel arithmetic, vector arithmetic, logical, and SIMD control/branch instructions. +  Instruction level variable-width SIMD execution. +  Conditional SIMD execution via destination mask, predication, and execution mask. +  Instruction compaction. +  An instruction may executed in multiple cycles over a SIMD execution pipeline. +  Most GEN instructions have three operands. Some instructions have additional implied source or + destination operands. Some instructions have explicit dual destinations. +  Region-based register addressing. +  Direct or indirect (indexed) register addressing. +  Scalar or vector immediate source operand. +  Higher precision accumulator registers are architecturally visible. +  Self-modifying code is not allowed (instruction streams, including instruction caches, are read-only). + +CoIssue/Dual Issue: +The Gen7 generation of EU allows two instructions to be issued at the same time (sometimes referred to +as “dual-issue” or more generally “co-issue”). The two instructions issued are always from different +threads. The terms “FPU Pipe” and “EM Pipe” are the terms used when refering to the two simultaneous +pipes. The Gen7 implementation dual-issue capability is limited to only the most popular instructions and +source operand modes. Later generations of EU expand on this concept to allow more operations. + +Description: + +Opcodes: add, mov, mad, mul, cmp +  Datatype: single precision floats. +  Accessmode: + o Align1: +  No Scattering or Gathering data. This means data in source and destination registers are + aligned and packed (data is contiguous in a register). + //Example: + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 29 + // allowed, data is contiguous and source and destination regioning + map one to one. + mov (8) r10.0:f r11.0<8;8,1>:f + // not allowed, data from source is strided and requires gathering to + write to destination + mov (8) r10.0:f r11.0<4;4,2>:f + // not allowed, data from source is contiguous but not aligned with + destination. Destination register requires scattering + mov (8) r10.0<2>:w r11.0<8;8,1>:w + //not allowed, data from source is contiguous but destination is not + aligned to source + mov (8) r10.1:f r11.0<4;4,1>:f + // allowed. Source and destination have stride but are aligned + mov (4) r10.1:f r11.1<4;4,1>:f + +  A single precision float scalar is allowed. + o Align16 + +  Addressmode: Direct Addressing +  Register File: GRF/NULL. No access to Accumulator. +  Condition modifiers supported only for cmp. + + +3.2 Primary Usage Models +In describing the usage models of the GEN instruction set, the following sections forward reference +terminology, syntax, and instructions described later in this specification. For clarity reasons, not all +forward references are explained at the point of reference. See the Instruction Set Summarychapter for +information about instruction fields and syntax. + + +3.2.1 AOS and SOA Data Structures +With the Align1 and Align16 access modes, the GEN instruction set provides effective SIMD computation +whether data is arranged in array of structures (AOS) form or in structure of arrays (SOA) form. The AOS +and SOA data structures are illustrated by the examples in AOS and SOA Data Structures. The example +shows two different ways of storing four vectors in four SIMD registers. For simplicity, the data vector and +the SIMD register both have four data elements. The four data elements in a vector are denoted by X, Y, +Z, and W just as for a vertex in 3D geometry. The AOS structure stores one vector in a register and the +next vector in another register. The SOA structure stores one data element of each vector in a register +and the next element of each vector in the next register and so on. The two structures can be related by a +matrix transpose operation. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 30 + AOS and SOA Data Structures + + + + +GEN 3D and media applications take advantage of such broad architecture support and use both AOS +and SOA data arrangements. + +  Vertices in 3D Geometry (Vertex Shader and Geometry Shader) are arranged in AOS form and use + SIMD4x2 and SIMD4 modes, respectively, as detailed below. +  Pixels in 3D Rasterization (Pixel Shader) are arranged in SOA form and use SIMD8 and SIMD16 + modes as detailed below. +  Pixels in media are primarily arranged in SOA form, and occasionally in AOS form with possibly + mixed modes of operation that uses region-based addressing extensively. + +These are preferred methods; alternative arrangements may also be possible. Shared function resources +provide data transpose capability to support both modes of operations: The sampler has a transpose for +sample reads, the data port has a transpose for render cache writes, and the URB unit has a transpose +for URB writes. +The following 3D graphics API Shader instruction is used in the following sections to illustrate various +operation modes: + add dst.xyz src0.yxzw src1.zwxy + + +This example is a SIMD instruction that takes two source operands src0 and src1, adds them, and stores +the result to the destination operand dst. Each operand contains four floating-point data elements. The +data type is determined by the instruction opcode. This instruction also uses source swizzles (.yxzw for +src0 and .zwxy for src1) and a destination mask (.xyz). Please refer to the programming specifications of +3D graphics API Shader instructions for more details. +A general register has 256 bits, which can store 8 floating point data elements. For 3D graphics, the +mode of operation is (loosely) termed after the data structure as SIMDmxn, where m is the size of the +vector and n is the number of concurrent program flows executed in SIMD. +Execution with AOS data structures: + +  SIMD4 (short for SIMD4x1) indicates that a SIMD instruction operates on 4-element vectors storedin + registers. There is one program flow. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 31 +  SIMD4x2 indicates that a SIMD instruction operates on a pair of 4-element vectors in registers. + There are effectively two programs running side by side with one vector per program. + +Execution with SOA data structures, also referred to as “channel serial” execution, mostly uses: + +  SIMD8 (short for SIMD1x8) indicates a SIMD instruction based on the SOA data structure where one + register contains one data element (the same one) for each of 8 vectors. Effectively, there are 8 + concurrent program flows. +  SIMD16 (short for SIMD1x16) indicates that a SIMD instruction operates on a pair of registers that + contain one data element (the same one) for each of 16 vectors. SIMD16 has 16 concurrent + program flows. + + +3.2.2 SIMD4 Mode of Operation +With a register mapping of src0 to doublewords 0-3 of r2, src1 to doublewords 4-7 of r2 and dst to +doublewords 0-3 of r3, the example 3D graphics API Shader instruction can be translated into the +following GEN instruction: +add (4) r3<4>.xyz:f r2<4>.yzwx:f r2.4<4>.zwxy:f {NoMask} +Without diving too much into the syntax definition of a GEN instruction, it is clear that a GEN instruction +also takes two source operands and one destination operands. The second term, (4), is the execution +size that determines the number of data elements processed by the SIMD instruction. It is similar to the +term SIMD Width used in the literature. Each operand is described by the register region parameters such +as ‘<4>’ and data type (e.g. “:f”). These will be detailed in the SIMD8 Mode of Operation section. The +instruction option field, {NoMask}, ensure that the execution occurs for the execution channels shown in +the instruction, instead of, possibly, being masked out by the conditional masks of the thread (See +Instruction Summary chapter for definition of MaskCtrl instruction field). +The operation of this GEN instruction is illustrated in the following figure. In this example, both source +operands share the same physical GRF register r2. The two are distinguished by the subregister number. +The source swizzles control the routing of source data elements to the parallel adders corresponding to +the destination data elements. The shaded areas in the destination register r3 are not modified. In +particular, doublewords 4-7 are unchanged as the execution size is 4; doubleword 3 is unchanged due to +the destination mask setting. +In this mode of operation, there is only one program flow – any branch decision will be based on a scalar +condition and apply to the whole vector of four elements. Option {NoMask} ensures that the instruction is +not subject to the masks. In fact, most of the instructions in a thread should have {NoMask} set. +Even though the execution only performs four parallel add operations, the GEN instruction still executes +in 2 cycles (with no useful computation in the second cycle). + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 32 + A SIMD4 Example + + + + +3.2.3 SIMD4x2 Mode of Operation +In this mode, two corresponding vectors from the two program flows fill a GEN register. With a register +mapping of src0 to r2, src1 to r3 and dst to r4, the example 3D graphics API Shader instruction can be +translated into the following GEN instruction: +add (8) r4<4>.xyz:f r2<4>.yxzw:f r3<4>.zwxy:f +This instruction is subject to the execution mask, which initiated from the dispatch mask. If both program +flows are available (e.g. Vertex Shader executed with two active vertices), the dispatch mask is set to +0x00FF. The operation of this GEN instruction is illustrated in SIMD4x2 Mode of Operation (a). The +source swizzles control the routing of source data elements to the parallel adders corresponding to the +destination data elements. The shaded areas in the destination register r3 (doublewords 3 and 7) are +unchanged due to the destination mask setting. If only one program flow is available (e.g. the same +SIMD4x2 Vertex Shader with only one active vertex), the dispatch mask is set to 0x000F. The operation +of the same instruction is shown in SIMD4x2 Mode of Operation (b). + +SIMD4x2 Examples with Different Emasks + + + + +The two source operands only need to be 16-byte aligned, not have to be GRF register aligned. For +example, the first source operand could be a 4-element vector (e.g. a constant) stored in doublewords 0-3 + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 33 + in r2, which is shared by the two program flows. The example 3D graphics API Shader instruction can +then be translated into the following GEN instruction: + add (8) r4<4>.xyz:f r2<0>.yzwx:f r3<4>.zwxy:f +The only difference here is that the vertical stride of the first source is 0. The operation of this GEN +instruction is illustrated in SIMD4x2 Mode of Operation. + +A SIMD4x2 Example with a Constant Vector Shared by Two Program Flows + + + + +3.2.4 SIMD16 Mode of Operation +With 16 concurrent program flows, one element of a vector would take two GRF registers. In this mode, +two corresponding vectors from the two program flows fill a GEN register. +With the following register mappings, +src0:r2-r9 (with 16 X data elements in r2-r3, Y in r4-5, Z in r6-7 and W in r8-9), +src1: r10-r17, +dst:r18-r25, +the example 3D graphics API Shader instruction can be translated into the following three GEN +instructions: +add (16) r18<1>:f r4<8;8,1>:f r14<8;8,1>:f// dst.x = src0.y + src1.z +add (16) r20<1>:f r6<8;8,1>:f r16<8;8,1>:f// dst.y = src0.z + src1.w +add (16) r22<1>:f r8<8;8,1>:f r10<8;8,1>:f // dst.z = src0.w + src1.x +The three GEN instructions correspond to the three enabled destination masks As there is no output for +the W elements of dst, no instruction is needed for that element. The first instruction inputs the Y +elements of src0 and the Z elements of src1 and outputs the X elements of dst. The operation of this +instruction is shown in SIMD16 Mode of Operation. +With more than one program flow, the above instructions are also subject to the execution mask. The 16- +bit dispatch mask is partitioned into four groups with four bits each. For Pixel Shader generated by the +Windower, each 4-bit group corresponds to a 2x2 pixel subspan. If a subspan is not valid for a Pixel +Shader instance, the corresponding 4-bit group in the dispatch mask is not set. Therefore, the same + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 34 + instructions can be used independent of the number of available subspans without creating bogus data in +the subspans that are not valid. + +A SIMD16 Example + + + + +Similar to SIMD4x2 mode, a constant may also be shared for the 16 program flows. For example, the first +source operand could be a 4-element vector (e.g. a constant) stored in doublewords 0-3 in r2 (AOS +format). The example 3D graphics API Shader instruction can then be translated into the following GEN +instruction: +add (16) r18<1>:f r2.1<0;1,0>:f r14<8;8,1>:f {Compr}// dst.x = src0.y + src1.z +add (16) r20<1>:f r2.2<0;1,0>:f r16<8;8,1>:f {Compr}// dst.y = src0.z + src1.w +add (16) r22<1>:f r2.3<0;1,0>:f r10<8;8,1>:f {Compr}// dst.z = src0.w + src1.x +The register region of the first source operand represents a replicated scalar. The operation of the first +GEN instruction is illustrated in SIMD16 Mode of Operation. + +Another SIMD16 Example with an AOS Shared Constant + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 35 + 3.2.5 SIMD8 Mode of Operation +Each compressed instruction has two corresponding native instructions. Taking the example instruction +shown in SIMD16 Mode of Operation, it is equivalent to the following two instructions. + add (8) r18<1>:f r4<8;8,1>:f r14<8;8,1>:f // dst.x[7:0] = src0.y + src1.z + add (8) r19<1>:f r5<8;8,1>:f r15<8;8,1>:f {SecHalf}// dst.x[15:8] = src0.y + src1.z +Therefore, SIMD8 can be viewed as a special case for SIMD16. +There are other reasons that SIMD8 instructions may be used. Within a program with 16 concurrent +program flows, some time SIMD8 instruction must be used due to architecture restrictions. For example, +the address register a0 only have 8 elements, if an indirect GRF addressing is used, SIMD16 instructions +are not allowed. + + +3.3 Registers and Register Regions + +3.3.1 Register Files +GEN registers are grouped into different name spaces called register files. There are two register files, +the General Register File and the Architecture Register File. A third encoding of some register file +instruction fields indicates immediate operands within instructions rather than a register file. + +  General Register File (GRF): The GRF contains general-purpose read-write registers. +  Architecture Register File (ARF): The ARF contains all architectural registers defined for specific + purposes, including address registers (a#), accumulators (acc#), flags (f#), notification count (n#), + instruction pointer (ip), null register (null), etc. +  Immediate: Certain instructions can take immediate source operands. A distinct register file field + encoding indicates an immediate operand. + +Each thread executed in an EU has its own thread context, a dedicated register space that is not shared +between threads, whether executing on a common EU or on a different EU. In the rest of the chapters in +this volume, register access is relative to a given thread. + + +3.3.2 GRF Registers +Number of Registers: Various +Default Value: None +Normal Access: RW +Elements: Various +Element Size: Various +Element Type: Various +Access Granularity: Byte +Write Mask Granularity: Byte +Indexable? Yes +Registers in the General Register File are the most commonly used read-write registers. During the +execution of a thread, GRF registers are used to store the temporary data, and serve as the destination to + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 36 + receive data from shared function units (and some times from a fixed function unit). They are also used to +store the input (initialization) data when a thread is created. By allowing fixed function hardware to +initialize some portion of GRF registers during thread dispatch time, GEN architecture can achieve better +parallelism. A thread’s execution efficiency can also be improved as some data are already in the register +to be executed upon. Besides these registers containing thread’s payload, the rest of GRF registers of a +thread are not initialized. + +Summary of GRF Registers + Register File Register Name Description + General purpose read write registers +General Register File (GRF) r# + +Each execution unit has a fixed size physical GRF register RAM. The GRF register RAM is shared by all +threads on the EU. Each thread has a dedicated space of 128 register, r0 through r127. +GRF registers can be accessed using region-based addressing at byte granularity (both read and write). +A source operand must be contained within two adjacent registers. A destination operand must be +contained within one register. GRF registers support direct addressing and register-indirect addressing. +Register-indirect addressing uses the address registers (ARF registers a#) and an immediate address +offset value. +When accessing (read and/or write) outside the GRF register range allocated for a given thread either +through direct or indirect addressing, the result is unpredictable. + + +3.3.3 ARF Registers + +3.3.3.1 ARF Registers Overview +Besides GRF and MRF registers that are directly indicated by unique register file coding, all other +registers belong to the Architecture Register File (ARF). Encodings of architecture register types are +based on the MSBs of the register number field, RegNum, in the instruction word. The RegNum field has +8 bits. The 4 MSBs, RegNum[7:4], represent the architecture register type. This is summarized in the +following table. + +Summary of Architecture Registers + Register + Type + (RegNum Register Register + [7:4]) Name Count Description + 0000b null 1 Null register + 0001b a0.# 1 Address register + 0010b acc# 2 Accumulator register + 0011b f#.# 2 Flag register + 0101b Reserved Reserved + 0110b Reserved Reserved + 0111b sr0.# 1 State register + 1000b cr0.# 1 Control register + 1001b n# 2 Notification Count register + 1010b ip 1 Instruction Pointer register + 1011b tdr 1 Thread Dependency register + 1100b tm0 1 TimeStamp register + 1101b Reserved Reserved + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 37 + Register + Type + (RegNum Register Register + [7:4]) Name Count Description + 1110b Reserved Reserved + +The remaining register number field RegNum[3:0] is used to identify the register number of a given +architecture register type. Therefore, the maximum number of registers for a given architecture register +type is limited to 16. The subregister number field, SubRegNum, in the instruction word has 5 bits. It is +used to address subregister regions for an architecture register supporting register subdivision. The +SubRegNum field is in units of bytes. Therefore, the maximum number of bytes of an architecture register +is limited to 32. Depending on the alignment restriction of a register type, only certain encodings of +SubRegNum field apply for an architecture register. The detailed definitions are provided in the following +sections. +In general an ARF register can be dst (destination) or src0 (source 0, first source operand) for an +instruction. Depending on the register and the instruction, other restrictions may apply. + +3.3.3.2 Access Granularity +ARF registers may be accessed with subregister granularity according to the descriptions below and +following the same rule of region-based addressing for GRF. The machine code for register number and +subregister number of ARF follows the same rule as for other register files with byte granularity. For an +ARF as a source operand, the region-based address controls the source swizzle mux. The destination +subregister number and destination horizontal stride can be used to generate the destination write mask +at byte level. +A special restriction on region-based addressing for ARF is that the register region cannot cross a register +boundary. +Subregister fields of an ARF register may not all be populated (indicated by the subregister being +indicated as reserved). Writes to unpopulated subregisters are dropped; there are no side effect. Reads +from unpopulated subregisters, if not specified, return unpredictable data. +Some ARF registers are read-only. Writes to read-only ARF registers are dropped and there are no side +effects. + +3.3.3.3 Null Register + +Null Register Summary + Attribute Value +ARF Register Type Encoding (RegNum[7:4]): 0000b +Number of Registers: 1 +Default Value: N/A +Normal Access: N/A +Elements: N/A +Element Size: N/A +Element Type: N/A +Access Granularity: N/A +Write Mask Granularity: N/A +SecHalf Control? N/A +Indexable? No + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 38 + The null register is a special encoding for an operand that does not have a physical mapping. It is +primarily used in instructions to indicate non-existent operands. Writing to the null register has no side +effect. Reading from the null register returns an undefined result. +The null register can be used where a source operand is absent. For example, for a single source +operand instruction such as MOV or NOT, the second source operand src1 must be a null register. +When the null register is used as the destination operand of an instruction, it indicates the computed +results are not stored in any registers. However, implied writes to the accumulator register, if applicable, +may still occur for the instruction. When the conditional modifier is present, updates to the selected flag +register also occur. In this case, the register region fields of the ‘null’ operand are valid. +Another example use is to use the null register as the posted destination of a send instruction for data +write to indicate that no write completion acknowledgement is required. In this case, however, the register +region fields are still valid. The null register can also be the first source operand for a send instruction +indicating the absent of the implied move. See the send instruction for details. + +3.3.3.4 Address Register + +Address Register Summary + Attribute Value +ARF Register Type Encoding (RegNum[7:4]): 0001b +Number of Registers: 1 +Default Value: None +Normal Access: RW +Elements: + 8 +Element Size: 16 bits +Element Type: UW or UD +Access Granularity: Word +Write Mask Granularity: Word +SecHalf Control? N/A +Indexable? No + +There are eight address subregisters forming an 8-element vector. Each address subregister contains 16 +bits. Address subregisters can be used as regular source and destination operands, as the indexing +addresses for register-indirect-addressed access of GRF registers, and also as the source of the +message descriptor for the send instruction. + +Register and Subregister Numbers for Address Register + RegNum[3:0] SubRegNum[4:0] +0000b = a0 When register a0 or subregisters in a0 are used as the address register for register-indirect + addressing, the address subregisters must be accessed as unsigned word integers. Therefore, +All other encodings + the subregister number field must also be word-aligned. +are reserved. + 00000b = a0.0:uw + 00010b = a0.1:uw + 00100b = a0.2:uw + 00110b = a0.3:uw + 01000b = a0.4:uw + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 39 + RegNum[3:0] SubRegNum[4:0] + 01010b = a0.5:uw + 01100b = a0.6:uw + 01110b = a0.7:uw + All other encodings are reserved. + However, when register a0 or subregisters in a0 are explicit source and/or destination + registers, other data types are allowed as long as the register region falls in the 128-bit range. + + +Address Register Fields +DWord Bits Description + 7 31:16 Address subregister a0.15:uw. Follows the same format as a0.3. + 15:0 Address subregister a0.14:uw. Follows the same format as a0.2. + 6 31:16 Address subregister a0.13:uw. Follows the same format as a0.3. + 15:0 Address subregister a0.12:uw. Follows the same format as a0.2. + 5 31:16 Address subregister a0.11:uw. Follows the same format as a0.3. + 15:0 Address subregister a0.10:uw. Follows the same format as a0.2. + 4 31:16 Address subregister a0.9:uw. Follows the same format as a0.3. + 15:0 Address subregister a0.8:uw. Follows the same format as a0.2. + 3 31:16 Address subregister a0.7:uw. Follows the same format as a0.3. + 15:0 Address subregister a0.6:uw. Follows the same format as a0.2. + 2 31:16 Address subregister a0.5:uw. Follows the same format as a0.3. + 15:0 Address subregister a0.4:uw. Follows the same format as a0.2. + 1 31:16 + Address subregister a0.3:uw. This field, with only the lower 12 bits populated, can be used as an + unsigned integer for register-indirect register addressing. + Format: U12 + 15:0 + Address subregister a0.2:uw. This field, with only the lower 12 bits populated, can be used as an + unsigned integer for register-indirect register addressing. + Format: U12 + + 0 31:16 + Address subregister a0.1:uw. This field can be used for register-indirect register addressing or serve + as message descriptor for a send instruction. When used for register-indirect register addressing, it is a + 12-bit unsigned integer. For a send instruction, it provides the higher 16 bits of . + Format: U12 or U16. + 15:0 + Address subregister a0.0:uw. This field can be used for register-indirect register addressing or serve + as message descriptor for a send instruction. When used for register-indirect register addressing, it is a + 12-bit unsigned integer. For a send instruction, it provides the lower 16 bits of . + Format: U12 or U16. + +When used as a source or destination operand, the address subregisters can be accessed individually or +as a group. In the following example, the first instruction moves 8 address subregisters to the first half of +GRF register r1, the second instruction replicates a0.4:uw as an unsigned word to the second half of r1, +the third instruction moves the first 4 words in r1 into the first 4 address subregisters, and the fourth +instruction replicates r1.4 as a unsigned word to the next 4 address subregisters. + mov (8) r1.0<1>:uw a0.0<8;8,1>:uw // r1.n = a0.n for n = 0 to 7 in words mov (8) +r1.8<1>:uw a0.4<0;1,0>:uw // r1.m = a0.4 for m = 8 to 15 in words mov (4) a0.0<1>:uw + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 40 + r1.0<4;4,1>:uw // a0.n = r1.n for n = 0 to 3 in words mov (4) a0.4<1>:uw +r1.4<0;1,0>:uw // a0.m = r1.4 for m = 4 to 7 in words + +When used as the register-indirect addressing for GRF registers, the address subregisters can be +accessed individually or as a group. When accessed as a group, the address subregisters must be group- +aligned. For example, when two address subregisters are used for register indirect addressing, they must +be aligned to even address subregisters. In the following example, the first instruction is legal. However, +the second one is not. As ExecSize = 8 and the width of src0 is 4, two address subregisters are used as +row indices, each pointing to 4 data elements spaced by HorzStride = 1 dword. For the first instruction, +the two address subregisters are a0.2:uw and a0.3:uw. The two align to a DWord group in the address +register. However, the two address subregisters for the second instruction are a0.3:uw and a0.4:uw. They +are not DWord-aligned in the address register and therefore violate the above mentioned alignment rule. + mov (8) r1.0<1>:d r[a0.2]<4,1>:d // a0.2 and a0.3 are used for src1 mov (8) r1.0<1>:d +r[a0.3]<4,1>:d // ILLEGAL use of register indirect + +Implementation restriction: GEN ISA supports per channel indexing for a source operand. As there are +only 8 sub-fields in the address register (to save hardware cost), the execution size of an instruction using +per-channel indexing is limited to 8. Software may reload the address register and use compression +control SecHalf to complete a 16-channel computation. +Implementation restriction: When used as the source operand for the send instruction, only the +first dword subregister of a0 register is allowed (i.e. a0.0:ud, which can be viewed as the combination of +a0.0:uw and a0.1:uw). In addition, it must be of UD type and in the following form = +a0.0<0;1,0>:ud. +Implementation restriction: Elements a0.0 and a0.1 have 16 bits each, but the rest of the elements +(a0.2:uw through a0.7:uw) only have 12 bits populated each. 12-bit precision supports full indirect- +addressing capability for the largest GRF register range. Software must observe the asymmetry of the +implementation. When a0.0:uw and a0.1:uw are the source or destination, full 16-bit precision is +preserved. However, when a0.2:uw to a0.7:uw are the destination, the high 4 bits for each element are +dropped; when they are the source, hardware inserts zero to the high 4 bits for each element. +Performance Note: There is only one scoreboard for the whole address register. When a write to some +subregisters is in flight, hardware stalls any instruction writing to other subregisters. Software may use the +destination dependency control {NoDDChk, NoDDClr} to improve performance in this case. Similarly, +when a write to some subregisters is in flight, hardware stalls any instruction sourcing other subregisters +until the write retires. + +3.3.3.5 Accumulator Registers + +Accumulator Registers Summary + Attribute Value +ARF Register Type Encoding (RegNum[7:4]): 0010b +Number of Registers: + 2 + +Default Value: None +Normal Access: RW + +Accumulator registers can be accessed either as explicit or implied source and/or destination registers. +To a programmer, each accumulator register may contain either 8 DWords or 16 Words of data elements. +However, as described in the Implementation Precision Restriction notes below, each data element may +have higher precision with added guard bits not indicated by the numeric data type. +Accumulator capabilities vary by data type, not just data size, as described in the Accumulator Channel +Precision table below. For example, D and F are both 32-bit data types, but differ in accumulator support. + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 41 + See the Accumulator Restrictions section for information about additional general accumulator restrictions +and also accumulator restrictions for specific instructions. +There are two accumulator registers, acc0 and acc1. + +Register and Subregister Numbers for Accumulator Registers + RegNum[3:0] SubRegNum[4:0] +0000b = acc0 Reserved: MBZ. +0001b = acc1 +All other encodings are reserved. + +  Accumulators are updated implicitly only if the AccWrCtrl bit is set in the instruction. The + Accumulator Disable bit in control register cr0.0 allows software to disable the use of AccWrCtrl for + implicit accumulator updates. The write enable in word granularity for the instruction is used to + update the accumulator. Data in disabled channels is not updated. +  When an accumulator register is an implicit source or destination operand, hardware always uses + acc0 by default and also uses acc1 if the execution size exceeds the number of elements in acc0. + When implicit access to acc1 is required, QtrCtrl is used. Note that QtrCtrl can be used only if acc1 + is accessible for a given data type. If acc1 is not accessible for a given data type, QtrCtrl defaults to + acc0. + acc0 and acc1 are supported for single-precision Float (F) only. Use QtrCtrl of Q2 or Q4 to access + acc1. + Examples: + // Updates acc0 and acc1 because it is SIMD16: + add (16) r10:f r11:f r12:f {AccWrEn} + // Updates acc0 because it is SIMD8: + add (8) r10:f r11:f r12:f {AccWrEn} + // Updates acc1. Implicit access to acc1 using QtrCtrl: + add (8) r10:f r11:f r12:f {AccWrEn, Q2} + // Updates acc1 for Half Floats using QtrCtrl: + add (16) r10:hf r11:hf r12:hf {AccWrEn, H2} + + +  It is illegal to specify different accumulator registers for source and destination operands in an + instruction (e.g. “add (8) acc1:f acc0:f”). The result of such an instruction is unpredictable. +  Some processor generations or steppings limit SIMD16 Float operations, as follows: +  SIMD16 execution on Floats is not allowed when an accumulator is an explicit source or + destination operand. +  Accumulator registers may be accessed explicitly as src0 operands only. +  Swizzling is not allowed when an accumulator is used as an implicit source or an explicit source in + an instruction. +  For any DWord operation, including DWord multiply, accumulator can store up to 8 channels of data, + with only acc0 supported. +  When an accumulator register is an explicit destination, it follows the rules of a destination register. If + an accumulator is an explicit source operand, its register region must match that of the destination + register with the exception described below. + +Implementation Precision Restriction: As there are only 64 bits per channel in DWord mode (D and +UD), it is sufficient to store the multiplication result of two DWord operands as long as the post source + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 42 + modified sources are still within 32 bits. If any one source is type UD and is negated, the negated result +becomes 33 bits. The DWord multiplication result is then 65 bits, bigger than the storage capacity of +accumulators. Consequently, the results are unpredictable. +Implementation Precision Restriction: As there are only 33 bits per channel in Word mode (W and +UW), it is sufficient to store the multiplication result of two Word operands with and without source +modifier as the result is up to 33 bits. Integers are stored in accumulator in 2's complement form with bit +32 as the sign bit. As there is no guard bit left, the accumulator can only be sourced once before running +into a risk of overflowing. When overflow occurs, only modular addition can generate a correct result. But +in this case, conditional flags may be incorrect. When saturation is used, the output is unpredictable. This +is also true for other operations that may result in more than 33 bits of data. For example, adding UD +(FFFFFFFFh) with D (FFFFFFFFh) results in 1FFFFFFFEh. The sign bit is now at bit 34 and is lost when +stored in the accumulator. When it is read out later from the accumulator, it becomes a negative number +as bit 32 now becomes the sign bit. + +Accumulator Channel Precision + Number +Data Accumulator of Bits Per +Type Number Channels Channel Description + DF acc0 4 64 When accumulator is used for Double Float, it has the exact same precision + as any GRF register. + F acc0/acc1 8 32 When accumulator is used for Float, it has the exact same precision as any + GRF register. + D acc0 8 33/64 When the internal execution data type is doubleword integer, each +(UD) accumulator register contains 8 channels of (extended) doubleword integer + values. The data are always stored in accumulator in 2's complement form + with 64 bits total regardless of the source data type. This is sufficient to + construct the 64-bit D or UD multiplication results using an instruction macro + sequence consisting of mul, mach, and shr (or mov). + W acc0 16 33 When the internal execution data type is word integer, each accumulator +(UW) register contains 16 channels of (extended) word integer values. The data + are always stored in accumulator in 2's complement form with 33 bits total. + This supports single instruction multiplication of two word sources in W + and/or UW format. + B N/A N/A N/A Not supported data type. +(UB) + + +3.3.3.6 Flag Register + +Flag Register Summary + Attribute Value +ARF Register Type Encoding (RegNum[7:4]): 0011b +Number of Registers: + 2 +Default Value: None +Normal Access: RW +Elements: + 2 +Element Size: 32 bits +Element Type: UD +Access Granularity: Word +Write Mask Granularity: Word + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 43 + Attribute Value +SecHalf Control? Yes +Indexable? No + +There are two flag registers, f0 and f1. +Each flag register contains two 16-bit subregisters. Each flag bit corresponds to a data channel. +Predication uses flag values to enable or disable channels. Conditional modifiers assign flag values. If an +instruction uses both predication and conditional modifiers, both features use the same flag register or +subregisters. +Flags can be split to halfs, quarters, or eighths using the QtrCtrl and NibCtrl instruction fields. Those fields +affect the selection of flags for predication and conditional modifiers, but do not affect reading or writing +flags as explicit instruction operands. +The values held in the individual bits of a flag register are the result of the most recent instruction with a +conditional modifier and specifying that flag register. For example: + add.nz.f0.0 ... + + +Updates flag subregister f0.0 with the per-channel results of the not zero condition. +The flag register has per-bit write enables. When being updated as the secondary destination associated +with a conditional modifier, only the bits corresponding to the enabled channels in EMask are updated. +Other bits in the flag subregister are unchanged. +Flag registers and subregisters can also be explicit source or destination operands. +The sel instruction does not update flags. +Note: When branching instructions are predicated, branching is evaluated on all channels enabled at +dispatch. This means, the appropriate number of flag register bits must be initialized or used in +predication depending on the execution mask (EMask). Uninitalized flags may result in undesired +branching. For example, if using DMask as EMask and if all 32 channels of DMask are enabled, a SIMD8 +kernel must initialize unused flag bits so that predication on branching is evaluated correctly. + +Register and Subregister Numbers for Flag Register + RegNum[3:0] SubRegNum[4:0] +0000b = f0:ud 00000b = fn.0:uw +0001b = f1:ud 00010b = fn.1:uw +Other encodings are reserved. Other encodings are reserved. + +Reference an entire flag register as f0:ud or f1:ud. Reference the flag subregisters as f0.0:uw, f0.1:uw, +f1.0:uw, and f1.1:uw. + +3.3.3.7 State Register + +State Register Summary + Attribute Value +ARF Register Type Encoding (RegNum[7:4]): 0111b +Number of Registers: 1 +Default Value: Provided by the Dispatcher +Normal Access: RW + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 44 + Attribute Value +Elements: 4 +Element Size: 32 bits +Element Type: UD +Access Granularity: Byte +Write Mask Granularity: N/A +SecHalf Control? No +Indexable? No + +Register and Subregister Numbers for State Register + RegNum[3:0] SubRegNum[4:0] +0000b = sr0 Valid encoding range: +All other encodings are reserved. 00000b – 01100b + All other encodings are reserved. + + +State Register Fields + DWord Bits Description + 31:28 Reserved. MBZ. + 0 + 27:24 FFID (Fixed Function Identifier). Specifies which fixed function unit generates the current thread. +(sr0.0:ud) This field is set at thread dispatch and is forwarded on the message bus for all out-going messages + from this thread. + 23 + Priority Class. This field, when set, indicates the thread belongs to the high priority class, which + has higher scheduling priority over any thread with this field cleared. The priority field below + determines the relative priority within the same priority class. This field is initialized by the thread + dispatcher at thread dispatch time and stays unchanged throughout the life span of the thread. + This field is forwarded on the message bus to the message bus arbiter for all out-going messages. + It serves as a priority hint for the target shared function. See the Shared Function chapters for + whether and how a shared function uses this priority hint. + 0 = Low priority class. + 1 = High priority class. + + 22:19 Reserved. MBZ. + 18:16 + Priority. This field is the relative aging priority of the thread. This field indicates the ‘age’ of this + thread relative to other threads within the EU. No two threads in the same EU can have the same + priority number (independent of the priority class value). Within the same priority class, an older + thread (with a larger priority number) has higher schedule priority over a younger thread. + This field is set to zero at a thread’s dispatch. + During a thread’s run time, this field may or may not be incremented when a new thread is + dispatched to the same EU. It is only incremented when another thread’s priority number is + incremented and reaches the same value. For example, if currently there is a thread with priority 0 + on an EU, then dispatching a new thread to that EU causes the old thread’s priority number to + increment to 1. However, if the active thread (assuming for simplicity that there is only one) on an + EU has a priority number 1 (or 2 or 3), then dispatching a new thread to this EU does not change + the old thread’s priority number. As threads on an EU may terminate in arbitrary order, the exact + number for a thread depends on the dynamic execution of threads. + 15:8 + : + [15:13] Reserved. MBZ. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 45 + DWord Bits Description + [12] HSID. HalfSlice Identifier for the EU. + [11:8] EUID[3:0]. Execution Unit Identifier. The MSB of this field is the RowID. + 7:3 Reserved. MBZ. + 2:0 TID (The thread identifier). Specifies the thread slot that the current thread is assigned to. This field + is set at thread dispatch. + 31:24 FFTID (Fixed Function Thread ID). There is no connection between this thread ID, assigned in fixed + 1 + functions, and the TID assigned in the EUs. +(sr0.1:ud) 23:0 Reserved. MBZ. + + + 31:23 + 1 +(sr0.1:ud) + + 31:0 + 2 Dispatch Mask (DMask). This 32-bit field specifies which channels are active at Dispatch time. + This field is used by hardware to initialize the mask register. +(sr0.2:ud) + Format: U32 + 31:0 + 3 Vector Mask (VMask). This 32-bit field contains, for each 4-bit group, the OR of the corresponding + 4-bit group in the dispatch mask. This field is used by hardware to initialize the mask register. +(sr0.3:ud) + Format: U32 + + +3.3.3.8 Control Register + +Control Register Summary + Attribute Value +ARF Register Type Encoding (RegNum[7:4]): 1000b +Number of Registers: 1 +Default Value: Provided by the Dispatcher +Normal Access: RW +Elements: 4 +Element Size: 32 bits +Element Type: UD +Access Granularity: DWord +Write Mask Granularity: DWord +SecHalf Control? No +Indexable? No + +The Control register is a read-write register. It contains four 32-bit subregisters that can be accessed +individually. +Subregister cr0.0:ud contains normal operation control fields such as the floating-point mode and the +accumulator disable. It also contains the master exception status/control field that allows software to +switch back to the application thread from the System Routine. +Subregister cr0.1:ud contains the mask and status/control fields for all exceptions. The exception fields +are arranged in significance-decreasing order from MSB to LSB. This arrangement allows the System +Routine to use the lzd instruction to find the high priority exceptions and handle them first. As each +exception is mapped to a single bit, another exception priority order may be implemented by software. +The System Routine may choose to handle one exception at a time, by handling the exception detected + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 46 + by an lzdinstruction and returning to the application thread. Or it may choose to handle all the concurrent +exceptions, by looping through the exception fields until all outstanding exceptions are handled before +returning back to the application thread. +Exception enable bits (bits 15:0 in cr0.1:ud) control whether an exception causes hardware to jump to the +System Routine or not. Exception status and control bits (bits 31:16 in cr0.1:ud) indicate which exceptions +have occurred, and are used by the system routine to clear the exception. Even if a given exception is +disabled, the corresponding exception status and control bit still reflects its status, whether an exception +event has occurred or not. +cr0.2:ud contains the Application IP (AIP) indicating the current thread IP when an exception occurs. +cr0.3:ud is reserved. Values written to this subregister are dropped; the result of reading from this +subregister is unpredictable. +Fields in Control registers also reference a virtual register called System IP (SIP). SIP is the virtual +register holding the global System IP, which is the initial instruction pointer for the System Routine. There +is only one SIP for the whole system. It is virtual only from a thread’s point of view, as it is not visible (i.e. +not readable and not writeable) to the thread software executed on a GEN EU. It can only be accessed +indirectly by the hardware to respond to exception events. Upon an exception, hardware performs some +bookkeeping (e.g. saving the current IP into AIP) and then jumps to SIP. Upon finishing exception +handling, the System Routine may return back to the application by clearing the Master Exception Status +and Control field in cr0, which causes the hardware to load AIP to IP register. See the STATE_SIP +command for how to set SIP. + +Register and Subregister Numbers for Control Register + RegNum[3:0] SubRegNum[4:0] +0000b = cr0 00000b = cr0.0:ud. It contains general thread control fields. +All other encodings are reserved. 00100b = cr0.1:ud. It contains exception status and control. + 01000b = cr0.2:ud. It contains AIP. + All other encodings are reserved. + + +Control Register Fields + DWord Bits Description + 0 31 Master Exception State and Control. This bit is the master state and control for all exceptions. + Reading a 0 indicates that the thread is in normal operation state and a 1 means the thread is in + exception handle state. Upon an exception event, hardware sets this bit to 1 and switches to SIP. + Writing 1 to this bit has no effect. Writing 0 to this bit also has no effect if the previous value is 0. In + both cases, the bit keeps the previous value. If the previous value of this bit is 1, software writing a 0 + causes the thread to return to AIP. This transition is automatic – software does not have to move AIP + to IP. The value of this bit then stays as 0. This bit is initialized to 0. + 0 = The thread is in normal state. + 1 = The thread is in exception state. + 30:16 Reserved. MBZ. + 15 + Breakpoint Suppress. This bit specifies whether breakpoint exception is suppressed or not. This + bit is normally set by software and cleared by hardware. If Master Exception Status and Control bit + is 1, this bit is ignored by hardware. If Master Exception Status and Control bit is 0 (i.e. not in + System Routine) and Breakpoint is enabled: If this bit is set, breakpoint is temporally ignored + (suppressed); Upon a breakpoint condition, the instruction is executed and this bit is automatically + reset by hardware. + This bit is provided to prevent infinite loops of jumping to the System Routine on a breakpoint + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 47 + DWord Bits Description + condition. The System Routine must set this bit (and also clear the corresponding status and control + bit) before returning to the application thread. + This bit has no effect when Breakpoint Enable bits are cleared. This bit is initialized to 0. + 0 = Breakpoint exception is not suppressed. + 1 = Breakpoint exception is suppressed. + 14:10 Reserved. MBZ. + 7 + Reserved. + + 6 + Double Precision Denorm Mode. This bit determines how denormal numbers are handled for the + DF (Double Float) type. It is initialized by Thread Dispatch. + 0 = Flush denorms to zero when reading source operands and flush denorm calculation results to + zero. Denorm flushing preserves sign. + 1 = Allow denorm source values and denorm results. + 5:4 + Rounding Mode. This field specifies the FPU rounding mode. It is initialized by Thread Dispatch. + 00b = Round to Nearest or Even (RTNE) + 01b = Round Up, toward +inf (RU) + 10b = Round Down, toward -inf (RD) + 11b = Round Toward Zero (RTZ) + 3 Vector Mask Enable (VME). This bit indicates DMask or Vmask should be used by EU for + execution. This bit is set by the Thread Dispatch. + 0: Use Dispatch Mask (DMASK) 1: Use Vector Mask (VMASK) + 2 + Single Program Flow (SPF). Specifies whether the thread has a single program flow (SIMDnxm + with m = 1) or multiple program flows (SIMDnxm with m > 1). This bit affects the operation of all + branch instructions. In Single Program Flow mode, all execution channels branch and/or loop + identically. This bit is initialized by the Thread Dispatch. + 0: Multiple Program Flows + 1: Single Program Flow + Programming Restrictions: + + + Only H1/Q1/N1 are allowed in SPF mode. + Power Optimization: If an entire shader does not do SIMD branching, the driver can set the SPF bit + to 1 to save power in HW. + 1 + Accumulator Disable. This bit controls the update of the accumulator by the instruction field + AccWrCtrl. If this bit is cleared, the accumulator is updated for all instructions with AccWrCtrl + enabled. If set, the accumulator is disabled for all update operations, maintaining its value prior to + being disabled. Setting this bit has no effect if the accumulator is the explicit destination operand for + an instruction. This bit is initialized to 0. + 0: Enable accumulator update. + 1: Disable accumulator update. + Usage Notes: + This control bit is primarily designed for the System Routine. That routine is not expected to use the + accumulator,though it may need to use instructions that implicitly update the accumulator. To use + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 48 + DWord Bits Description + such instructions in the System Routine, but still preserve the accumulator contents on returning to + the application kernel, the System Routine would either (a) save and restore the accumulator, or (b) + prevent the accumulator from being unintentionally modified. This control bit has been added for the + latter method. + Software has the option to limit the setting of this control bit to strictly within the System Routine. If, + by convention, this bit is clear within application kernels, the System Routine can simply set the bit + upon entry and clear it before returning control to the application kernel. This usage model would + not necessarily require cr0.0 to be saved/ restored in the System Routine. However, if by + convention application kernels are permitted to set this bit, then the System Routine is required to + preserve the content of this bit. + 0 + Single Precision Floating Point Mode (FP Mode). This bit specifies whether the current single- + precision floating-point operation mode is IEEE mode (IEEE Standard 754) or the ALT (alternative + mode). This bit does not affect the floating-point mode used for other floating-point data types. This + bit is also forwarded on the message sideband for all out-going messages, for example, to control + the floating-point mode of the Sampler. Software may modify this bit to dynamically switch between + the two floating-point modes. This bit is initialized by Thread Dispatch. + 0 = IEEE floating-point mode for the F (Float) type. + 1 = ALT (alternative) floating-point mode for the F (Float) type. + + 30 + External Halt Exception Status and Control. This bit indicates the External Halt exception. It is + set by EU hardware on receiving the broadcast External Halt signal. The System Routine should + reset this bit before returning to an application routine to avoid infinite loops. + This bit may be set or cleared by software. This bit is initialized to 0. + 29 + Software Exception Control. This bit is the control bit for software exceptions. Setting this bit to 1 + in an application routine causes an exception. Clearing this bit in an application routine has no + effect. Upon entering the system routine, the hardware maintains this bit as 1 to signify a software + exception. The System Routine should reset this bit before returning to an application routine. + This bit may be set or cleared by software. This bit is initialized to 0. + 28 + Illegal Opcode Exception Status. This bit, when set, indicates an illegal opcode exception. The + exception handler routine normally does not return back to the application thread upon an illegal + opcode exception. Leaving this bit set has no effect on hardware; if system software adversely + returns to an application routine leaving this bit set, it doesn’t cause any exception. This bit should + not be set by software or left set by the system routine to avoid confusion. + This bit is initialized to 0. + + 27 + Stack Overflow Exception Status. This bit when set, indicates a stack overflow exception. The + exception handler routine normally does not return back to the application thread upon a stack + overflow exception. Leaving this bit set has no effect on hardware; if system software adversely + returns to an application routine leaving this bit set, it doesn’t cause any exception. This bit should + not be set by software or left set by the system routine to avoid confusion. + This bit is initialized to 0. + 26:24 Reserved + 23:16 Reserved. MBZ. + 15 + Breakpoint Enable. Specifies whether the breakpoint exception is enabled or not. + This bit is initialized by the Thread Dispatcher. + Format = ENABLED: + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 49 + DWord Bits Description + 0: Disabled + 1: Enabled + 13 + Software Exception Enable. This bit enables or disables the software exception. Enabling or + disabling this bit may allow host software to turn on/off certain features (such as profiling) without + changing the kernel program. + This bit is initialized by the Thread Dispatcher. + Format = ENABLED: + 0: Disabled + 1: Enabled + + 12 + Illegal Opcode Exception Enable. This bit specifies whether the illegal opcode exception is + enabled or not. The Illegal opcode exception includes illegal opcodes and undefined opcodes, + caused by bad programs or run-time data corruption. + This bit is initialized by the Thread Dispatcher. + Software should normally assign this bit in the interface descriptor. Even though this mechanism is + provided to disable the illegal opcode exception, it should be used with extreme caution. + Format = ENABLED: + 0: Disabled + 1: Enabled + 11 + Stack Overflow Exception Enable. This bit specifies whether the stack overflow exception is + enabled or not. The stack overflow exception includes an overflow or an underflow in the stack + space allocated for the thread. + This bit is initialized by the Thread Dispatcher. + Software should normally assign this bit in the interface descriptor. + Format = ENABLED: + 0: Disabled + 1: Enabled + 10:0 Reserved. MBZ. + 31:3 + 2 Application IP (AIP). This is the register storing the instruction pointer before an exception is + handled. Upon an exception, hardware automatically saves the current IP into the AIP register, and +(cr0.2:ud) + then sets the Master Exception State and Control field to 1, which forces a switch to the System + IP (SIP). The AIP register may contain either the pointer to the instruction that causes the exception + or the one after (such as masked stack overflow/underflow exceptions). This is shown in the + following table, where IP is the instruction that generated the exception. + + + + Exception Type AIP Value + Breakpoint IP + External Halt N/A (1) + Software Exception IP + 1 + Illegal Opcode IP + (1) External Halt exception is asynchronous and not associated with an instruction. + When the System Routine changes the Master Exception State and Control field from 1 to 0, + hardware restores IP from this register. This field is writable allowing the returning IP to be altered + after an exception is handled. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 50 + DWord Bits Description + 2:0 Reserved. MBZ. + +Implementation Restriction on Register Access:When the control register is used as an explicit source +and/or destination, hardware does not ensure execution pipeline coherency. Software must set the thread +control field to ‘switch’ for an instruction that uses control register as an explicit operand. This is important +as the control register is an implicit source for most instructions. For example, fields like FPMode and +Accumulator Disable control the arithmetic and/or logic instructions. Therefore, if the instruction updating +the control register doesn’t set ‘switch’, subsequent instructions may have undefined results. + +3.3.3.9 Notification Registers + +Notification Registers Summary + Attribute Value +ARF Register Type Encoding (RegNum[7:4]): 1001b +Number of Registers: 3 +Default Value: No +Normal Access: RO (RW – Context save/restore only) +Elements: 3 +Element Size: 32 bits +Element Type: UD +Access Granularity: DWord +Write Mask Granularity: DWord +SecHalf Control? No +Indexable? No + +There are three notification registers (n0.0:ud, n0.1:ud, and n0.2:ud) used by the wait instruction. These +registers are read-only, except under context restore, and can be accessed in 32-bit granularity. Write +access to this register is allowed only when context is restored. +It should be noted that in the extreme case, it is possible to have more notifications to a thread than the +maximum allowed number of concurrent threads in the system. Therefore, the range of the thread-to- +thread notification count in n0, is larger than the maximum number of threads computed by EUID * TID. +There is only one bit for the host-to-thread notification count in n1. +When directly accessed, this register is read-only. If the value is non zero, the only way to alter the value +is to use the wait instruction to decrement the value until zero is reached. A wait instruction on a zero +notification subregister causes the thread to stall, waiting for a notification signal from outside targeting +the same subregister. See the wait instruction for details. +Implementation Restriction: The notification registers are initialized to 0 after hardware/software reset. +However, these registers are not reset at thread dispatch time. + +Register and Subregister Numbers for Notification Registers + RegNum[3:0] SubRegNum[4:0] +0000b = n0 00000b = n0.0:ud +All other encodings are reserved. 00100b = n0.1:ud + 01000b = n0.2:ud + All other encodings are reserved. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 51 + Notification Register 0 Fields +DWord Bits Description + 0 31:16 Reserved. MBZ. + 15:0 + Thread to Thread Notification Count. This register is used by the WAIT instruction for thread-to- + thread synchronization. The value read from this register specifies the outstanding notifications + received from other threads. It can be changed indirectly by using the WAIT instruction. See the WAIT + instruction for details. + Format: U16 + + +Notification Register 1 Fields +DWord Bits Description + 0 31:1 Reserved. MBZ. + +Notification Register 2 Fields +DWord Bits Description + 0 31:16 Reserved. MBZ. + 15:0 + Thread to Thread Notification Count. This register is used by the WAIT instruction for thread-to- + thread synchronization. The value read from this register specifies the outstanding notifications + received from other threads. It can be changed indirectly by using the WAIT instruction. See the WAIT + instruction for details. + Format: U16 + + +Format of the Notification Register + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 52 + 3.3.3.10 IP Register + +IP Register Summary + Attribute Value +ARF Register Type Encoding (RegNum[7:4]): 1010b +Number of Registers: 1 +Default Value: Provided by the Dispatcher +Normal Access: RW +Elements: 1 +Element Size: 32 bits +Element Type: UD +Access Granularity: DWord +Write Mask Granularity: DWord +SecHalf Control? No +Indexable? No + +The ip register can be accessed as a 32-bit quantity. It is a read-write register, containing the current +instruction pointer, which is relative to the Generate State Base Address. Reading this register returns +the instruction pointer of the current instruction. The 3 LSBs are always read as zero. Writing this register +causes program flow to jump to the new address. When it is written, the 3 LSBs are dropped by +hardware. + +Register and Subregister Numbers for IP Register + RegNum[3:0] SubRegNum[4:0] +0000b = ip 00000b = ip:ud +All other encodings are reserved. All other encodings are reserved. + + +IP Register Fields +DWord Bits Subfield Description + 0 31:3 Ip. Specifies the current instruction pointer. This pointer is relative to the General State Base Address. + 2:0 Reserved. MBZ. + + +3.3.3.11 TDR Registers + +TDR Registers Summary + Attribute Value +ARF Register Type Encoding (RegNum[7:4]): 1011b +Number of Registers: 8 +Default Value: No +Normal Access: RO/CW +Elements: 8 +Element Size: 16 bits +Element Type: UW +Access Granularity: Word +Write Mask Granularity: Word +SecHalf Control? No +Indexable? No + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 53 + There are 8 thread dependency registers (tdr0.0:uw to tdr0.7:uw) used by HW for the sendc instruction. +These registers are read-only and can be accessed in 16-bit granularity. +When accessed explicitly, each thread dependency register has FFTID in the lower 8 bits, bits 8 to 14 are +forced to zero by HW. Bit 15 is the valid bit, which indicate whether the current thread has a dependency +on the dependency thread stored in this thread dependency register. +The thread dependency registers are read only, the valids can only be set with a thread dispatch, and are +reset by broadcasting end of thread messages after a thread retired. The FFTID’s can only be changed +with a therad dispatch. Any write into any of the TDR registers will clear the valid bit for the particular TDR +if the write enable is true, the FFTID portion is strictly read only. + +Register and Subregister Numbers for TDR Registers + RegNum[3:0] SubRegNum[4:0] +1011b = tdr0 00000b = tdr0.0:uw +All other encodings are reserved. 00010b = tdr0.1:uw + 00100b = tdr0.2:uw + 00110b = tdr0.3:uw + 01000b = tdr0.4:uw + 01010b = tdr0.5:uw + 01100b = tdr0.6:uw + 01110b = tdr0.7:uw + All other encodings are reserved. + + +TDR Registers Fields +DWord Bits Description + 3 31 Valid7. This field indicates whether the thread specified by FFTID7 is still in-flight. + 30:24 Reserved. MBZ + 23:16 + FFTID7. This field is the FFTID of the third thread that the current thread depends on. It can be + changed by the end of thread broadcasting messages. + Format: U8 + 15 Valid6. This field indicates whether the thread specified by FFTID6 is still in-flight. + 14:8 Reserved. MBZ + 7:0 + FFTID6. This field is the FFTID of the third thread that the current thread depends on. It can be + changed by the end of thread broadcasting messages. + Format: U8 + + 2 31 Valid5. This field indicates whether the thread specified by FFTID5 is still in-flight. + 30:24 Reserved. MBZ + 23:16 + FFTID5. This field is the FFTID of the third thread that the current thread depends on. It can be + changed by the end of thread broadcasting messages. + Format: U8 + 15 Valid4. This field indicates whether the thread specified by FFTID4 is still in-flight. + 14:8 Reserved. MBZ + 7:0 + FFTID4. This field is the FFTID of the third thread that the current thread depends on. It can be + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 54 + DWord Bits Description + changed by the end of thread broadcasting messages. + Format: U8 + 1 31 Valid3. This field indicates whether the thread specified by FFTID3 is still in-flight. + 30:24 Reserved. MBZ + 23:16 + FFTID3. This field is the FFTID of the third thread that the current thread depends on. It can be + changed by the end of thread broadcasting messages. + Format: U8 + + 15 Valid2. This field indicates whether the thread specified by FFTID2 is still in-flight. + 14:8 Reserved. MBZ + 7:0 + FFTID2. This field is the FFTID of the third thread that the current thread depends on. It can be + changed by the end of thread broadcasting messages. + Format: U8 + 0 31 Valid1. This field indicates whether the thread specified by FFTID1 is still in-flight. + 30:24 Reserved. MBZ + 23:16 + FFTID1. This field is the FFTID of the third thread that the current thread depends on. It can be + changed by the end of thread broadcasting messages. + Format: U8 + 15 Valid0. This field indicates whether the thread specified by FFTID0 is still in-flight. + 14:8 Reserved. MBZ + 7:0 + FFTID0. This field is the FFTID of the third thread that the current thread depends on. It can be + changed by the end of thread broadcasting messages. + Format: U8 + + +3.3.3.12 Performance Registers + +Performance Registers Summary + Attribute Value +ARF Register Type Encoding (RegNum[7:4]): 1100b +Number of Registers: 1 +Default Value: 0h +Normal Access: RO +Elements: 2 +Element Size: 32 bits +Element Type: UD +Access Granularity: Byte +Write Mask Granularity: N/A +SecHalf Control? No +Indexable? No + +Starting with, a block of ARF register space is allocated for per-thread performance information. Currently +only a timestamp register is defined within this space, although it is anticipated that future performance- +related information would be located here also. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 55 + Register and Subregister Numbers for Performance Registers + RegNum[3:0] SubRegNum[4:0] +1100b = timestamp Valid encoding range: +All other encodings are reserved. 00000b – 00111b (in units of bytes) + All other encodings are reserved. + +Timestamp Register +This generation defines a new low latency timestamp source, “TM”, available as part of a thread's +Architectural Register File (ARF). This is a is free running counter, 64b in size, and exposed to the ISA as +individual 32b high ‘TmHigh’ and low ‘TmLow’ unsigned integer source operands. As part of the EU's +register space, access to the timestamp has a low and deterministic latency and therefore can be used +for intra-kernel high resolution performance profiling. +The TM counter is free running based on the EU’s clock and continues to increment across all time. +Given a base EU clock frequency of 1.25 GHz and the counter’s 64b size, rollover of the lower 32b +occurs approximately every 3.3 seconds, with the upper 32b value rollover measured as ~450 years. The +TM count continues to increment during a thread's active/standby state transitions as well as context +switches. It is read-only and not pre- or resettable under any software control, either kernel or driver, +other than a full gfx reset. The 64b TM value is expected to be identical across all EUs of the system +unless DOP clock gating is enabled. +The TM features provides a 1-bit indicator ‘TmEvent’ which identifies the occurrence of a time-impacting +event such as context switch or frequency change since the last time any portion of the Timestamp +register value was read by that thread. Software that uses the Timestamp capability should check this bit +to identify when a relative time calculation may be suspect. To properly use this additional information, +the instrumentation code should operate on the Timestamp register value as a whole (i.e. as an 8 dword +register) so that the 64b time and this 1b value are captured simultaneously, as opposed to 32b portions, +to eliminate a the chance of missing a TmEvent that might occur between accesses to 32b portions of this +register. +Note: The Timestamp register is saved as part of thread state on context-save, but only ‘TmEvent’ is +restored (and technically always restored to ‘1’ as a context switch had occurred). + +Timestamp Register Fields +DWord Bits Description + 7:3 31:0 Undefined. + 2 31:29 Undefined. + 0 TmEvent. Indicates a discontinuous time-impacting event (e.g. context switch, frequency change) + occurred since any portion of the Timestamp register was last read, thus making any relative duration + calculation based on this counter suspect. This bit is reset at the time a new thread is loaded, and on + each read of any portion of the ‘Timestamp’ register. + 1 31:0 + TmHigh. The upper 32b of the 64b timestamp value sourced from Cr clock. Read-only. + Format: U32 + + 0 31:0 + TmLow. The lower 32b of the 64b timestamp value sourced from Cr clock. Read-only. + Format: U32 + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 56 + 3.3.4 Immediate +Two forms of immediate are provided as a source operand: scalar and vector. +The immediate field in a GEN instruction has 32 bits. For a word or an unsigned word immediate data, +software must replicate the same 16-bit immediate value to both the lower word and the high word of the +32-bit immediate field in a GEN instruction. +For a scalar immediate, it can be of any of the specified numeric data types from a word to a dword. Byte +and unsigned byte are not supported as the smallest internal type of the execution pipeline is word. +These two numeric types are reserved for future extensions. +The immediate form of vector allows a constant vector to be in-lined in the instruction stream. Both integer +and float immediate vectors are supported. +An immediate integer vector is denoted by type v or uv as imm32:v or imm32:uv, where the 32-bit +immediate field is partitioned into 8 4-bit subfields. Refer to the Numeric DataType Section for description +of the packing of vector integers to a dword. +An immediate float vector is denoted by type vf as imm32:vf, where the 32-bit immediate field is +partitioned into 4 8-bit subfields. Refer to the Numeric DataType Section for the description of the packing +of vector floats to a dword. +Restriction: When an immediate vector is used in an instruction, the destination must be 128-bit aligned +with destination horizontal stride equivalent to a word for an immediate integer vector (v) and equivalent +to a dword for an immediate float vector (vf). + + +3.3.5 Region Parameters +Unlike conventional SIMD architectures where an N-bit wide SIMD instruction can only operate on N-bit +aligned SIMD data registers, a region-based register addressing scheme is employed in GEN +architecture. The region-based register addressing capability significantly improves the SIMD +computation efficiency by providing per-instruction-based multiple data gathering from register file. This +avoids instruction overhead to perform data pack, unpack, and shuffling, which has been observed on +other SIMD architectures. One benefit of such capability is allowing various kinds of 3D Graphics API +Shader compute models to run efficiently on GEN. Another benefit is allowing high throughput of media +applications, which tend to operate on byte or word data elements. +This can be illustrated by the example shown in Region Parameters and Region Parameters. As shown in +Region Parameters, a sequence of SIMD instruction is executed on a conventional load/store based +superscalar machine with SIMD instruction extension. The data parallelism can be achieved by first level +of loop unrolling. As shown, there is a second level of loop for the task. Before a given SIMD compute +instruction, Process (i), can proceed, there might be a load, a data rearrange and a data unpack (and +conversion) instruction to load and prepare the input data. After the compute instruction is complete, it +might also require pack, re-arrange and store instructions, to format and save the same to memory. At the +loop, other scalar computations such as loop count and address generation may be needed. For the +same program, when the data can fit in the large GEN GRF register file, the outer loop may be unrolled +for GEN. Here one or a few block loads (using send instruction) may be sufficient to move the working set +into GRF. Then the data shuffle can be combined with the processing operation with region-based +addressing capability. Per operand float type and mixed data type operation may also allow GEN to +combine data conditioning operations with computing operations. These techniques in GEN architecture +help to achieve high compute efficiency and throughput for graphics and media applications. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 57 + Conventional SIMD Instruction Sequence + + + + +GEN SIMD Instruction Sequence for the Same Program + + + + +In a GEN instruction, each operand defines a region in the register file. A region may contain multiple +data elements. Each data element is assigned to an execution channel in the EU. The total number of + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 58 + data elements of a region is called the size of the region, or the size of the operand. The number of +execution channels is called the execution size (ExecSize), which is specified in the instruction word. +ExecSize determines the size of region for source and destination operands in an instruction. + +  For an instruction with two source operands, the sizes of the two source operands must be the + same. +  The size of a destination operand generally matches the execution size, therefore equals to + the number of source operand(s) in the same instruction. + o Exception of this rule is present for the integer reduction instructions (such as sad2 + and sada2) where the destination area is smaller than the source area. + +Regions are generalized 2-dimensional (2D) arrays in row-major order. The first dimension is named +the horizontal dimension (data elements within a row) and the second dimension is termed the vertical +dimension (data elements in a column). Here, horizontal/vertical and row/column are just symbolic +notations. When the GRF registers are viewed as a row-major 2D array of memory, such a notation +normally matches well with the geometric locations of the data elements of an operand. However, as the +register region is fully described by the parameters discussed below, the data elements of a register +region may not form a regular rectangular shape. For example, Vertical Stride parameter is allowed to be +smaller than Horizontal Stride, making the rows of a register region interleave with each other. It should +also note that the meanings of horizontal/vertical here is different than that used for the flag control in the +Flag Registers section. +Specifically, a region-based description of a source operand can take the following format +RegFile RegNum.SubRegNum:type +Parameters are as the follows. +  Register Region Origin (RegFile, RegNum and SubRegNum): This set of parameters, + including the register file, RegFile, the register number, RegNum, and the subregister number, + SubRegNum, describes the register region origin, which is the location of the first data + element of the operand. RegNum is in unit of 256-bit and SubRegNum is in unit of the data + element size. +  Width (Width): Width specifies the number of data elements along the horizontal dimension, or + the number of data elements of a row. +  Horizontal Stride (HorzStride): HorzStride specifies the step size between two adjacent data + elements within a row. It is in unit of data element size, which is determined by the data + element Type. +  Vertical Stride (VertStride): VertStride specifies the step size between two adjacent data + elements along the vertical dimension (or the step size between two rows). It is again in unit of + data element size, which is determined by the data element Type. +  Data Element Type (Type): Type specifies numeric data type (float, word, byte, etc.) of the + data elements. All data elements within a region must have the same type. + +GRF register file consists of a sequence of 256-bit registers. When viewing the register file (GRF for +example) as a sequence of 256-bit aligned registers, RegNum field provides the register number, thus for +the name. SubRegNum provides the sub-field addressing within a register. However, when viewing the +register file as a byte addressable memory array, (RegNum and SubRegNum) is just a byte address +within the register file with SubRegNum providing the lower 5 bits and RegNum providing the higher bits. +The execution size is specified for each instruction by the parameter ExecSize. The size of the vertical +dimension is ExecSize/Width, based on the rule that the size of regions must equal to the execution size. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 59 + Region Parameters depicts the register region description. The example shows a register region of +r4.1<16;8,2>:w, where the shaded fields denote the data elements in the region and the numbers in these +fields are the execution channel assignments. The register region assumes that an ExecSize of 16 is set +for the instruction. Each data element is a word (as noted by the type field “:w”). The origin of the region is +at the second word of r4, denoted by r4.1. Each row of the region has 8 data elements (words) that are 2 +data elements (words) apart. The distance between two rows is 16 words. Note that the region shown is +for illustration purpose only. It does not represent a typical usage model nor a performance optimized +mode. + +An example of a register region (r4.1<16;8,2>:w) with 16 elements + + + + +Region Parameters shows another example where the rows are interleaved. The region, having word +data elements, starts at location r5.0:w. HorzStride, the distance within a row, is 2 words. So the second +element (channel number 1) is at location 5.2:w. And there are 8 elements per row. VertStride, the +distance between two rows, is only 1 word, which is less than HorzStride. Therefore, the first element of +the second row (channel number 8) is at r5.1:w, just next to channel number 0. It is clear from the picture +that the two rows are interleaved. +By varying the region parameters, reader may construct other configurations. The next section provides +more details on the region-based register addressing. However, there are restrictions imposed by +hardware implementation, which can be found in the later sections of this chapter. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 60 + A 16-element register region with interleaved rows (r5.0<1;8,2>:w) + + + + +Without considering the source channel swizzle and destination register region description, the above +row-major-order region description provides the data assignment to each execution channel. The +following pseudo code computes the addresses of data elements assigned to execution channels for a +special case when the destination register is aligned to 256-bit register boundary. +// Input: Type: ub | b | uw | w | ud | d | f | v +//RegNum: In unit of 256-bit register +//SubRegNum: In unit of data element size +//ExecSize, Width, VertStride, HorzStride: In unit of data elements +// Output: Address[0:ExecSize-1] for execution channels +int ElementSize = (Type==“b”||Type==“ub”) ? 1 : (Type==“w”|Type==“uw”) ? 2 : 4; +int Height = ExecSize / Width; +int Channel = 0; +int RowBase = RegNum<<5 + SubRegNum * ElementSize; +for (int y=0; y:type +The destination operand is only allowed to have a 1 dimensional region. The Register Region Origin and +Type are the same as for a source operand. The total number of elements is given by ExecSize. +However, only HorzStride is required to describe the 1D region, not VertStride and Width. +As a source register region may cross multiple physical GRF registers, an instruction with such source +operands may take more than two execution cycles to gather source data elements for execution. The +destination register region is restricted to be within a physical GRF register. In other words, destination +scatter writes over multiple registers are not supported. + + +3.3.6 Region Addressing Modes +There are two different register addressing modes: Direct register addressing and register-indirect register +addressing. Depending on the register region description, the register-indirect register addressing mode +can be further divided into three usages: 1x1 index region where only the origin of register region is +provided by the address register, Vx1 index region where the offset of each row of the register region is +provided by an address register, VxH index region where the offset of each data element is provided by +an address register. + +3.3.6.1 Direct Register Addressing +In this mode, all register region parameters are specified for an operand using fields in the instruction +word. +Direct Register Addressing and Direct Register Addressing are two examples of direct register +addressing. +For the example in Direct Register Addressing, all operands are 2D rectangular regions having the same +size of 16 data elements. The two source operands, Src0 and Src1, have 16 bytes. The destination +operand, Dst, has 16 words. There are 8 elements in a row for Src0 and Src1. The vertical stride of 16 +bytes for Src0 and Src1 indicates that the first element and the 9’th element are 16 bytes apart in the +register file. Note that Src0 falls into the 256-bit physical GRF register starting at r1.0, but Src1 crosses +the 256-bit physical GRF register boundary between r2 and r3. The numbers in the shaded regions are +the values of the data elements. Observing the upper right corners of the source/destination regions (first +data element), we have C = 3+9. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 62 + A region description example in direct register addressing + + + + +For the example in Direct Register Addressing, the sizes of areas of Src0 and Src1 are the same, but +Src0 contains a vector of replicated scalars. With HorzStride = 0 and Width = 8, the first row of 8 elements +in Src0 is a replication of the byte at r1.14. Comparing ExecSize of 16 to Width of 8 indicates that there is +a second row of 8 elements in Src0. With VertStride = 16, the second row in Src0 is a replication of the +byte at r1.20 (20 = 14+16). Effectively, the 16 data elements of Src0 are {1,1,1,1,1,1,1,1, 4,4,4,4,4,4,4,4}. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 63 + A region description example in direct register addressing with src0 as a vector of replicated +scalars + + + + +3.3.6.2 Register-Indirect Register Addressing with a 1x1 Index Region +In the register-indirect register addressing mode with 1x1 index region, the region origin is provided by the +content of the address register, the rest of region parameters are provided by the fields in the instruction +word. +Register indirect Register Addressing with a 1x1 Index Region depicts an example for this addressing +mode. For example, the presence of a full region description <16;8,1> for Src0 indicates that only the +origin of the region is provided by the address register a0.0. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 64 + An example illustrating register-indirect register addressing mode with a 1x1 index region + + + + +3.3.6.3 Register-Indirect Register Addressing with a Vx1 Index Region +In the register-indirect register addressing mode with Vx1 index region, the horizontal dimension is +described by the fields in the instruction word and the vertical dimension is described by an address +register region. Specifically, the origin of each row of the data region is provided by the contents of an +address register region. The rows are described by the width and the horizontal stride. The first address +register is provided and the following contiguous address registers are for the following rows. The total +number of address registers used is inferred from the parameters ExecSize and Width. +Within the 16-bit address register, bits 15:5 determine RegNum and bits 4:0 determine SubRegNum. +An example is provided in Register-Indirect Register Addressing with a Vx1 Index Region. The assembly +syntax notion of a register region without vertical stride, <4,1>, corresponding to the special encoding of +vertical stride of 0xF in the instruction word, indicates the VxH or Vx1 mode of indirect register +addressing. In this case, the origin for each row of src0 is provided by the address register. As +ExecSize/Width = 2, there are two address registers a0.0 and a0.1, each pointing to a row of 4 data +elements. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 65 + An example illustrating register-indirect-register addressing mode with a Vx1 index region (src0) + + + + +3.3.6.4 Register-indirect Register Addressing with a VxH Index Region +In the register-indirect register addressing mode with VxH index region, the position of each data element +is provided by the contexts in an address register region. This mode has the identical syntax as the Vx1 +index region mode, and in fact, can be viewed as a special case of the Vx1 mode. When Width of the +region is 1, the number of address registers used equals ExecSize. +An example is provided in Register indirect Register Addressing with a VxH Index Region. The absent of +vertical stride in the region description <1,0> with width = 1 indicates that the origin for each row of 1 data +element of Src0 is provided by the address register. As ExecSize/Width = 8, there are 8 address registers +from a0.0 to a0.7, each pointing to a single data elements. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 66 + An example illustrating register-indirect register addressing mode with a VxH index region (Src0). + + + + +3.3.7 Access Modes +There are two basic GEN register access modes controlled by a single bit instruction subfield called +Access Mode. + +  16-byte Aligned Access Mode (align16): In this mode, the origins of all operands (sources and + destination), whether it is by direct addressing or register-indirect addressing, are 16-byte aligned. + For example a row in the region description starts at 16-bype aligned and the width the row must be + 4 and the 4 data elements within a row must span 16-bytes. In this access mode (and with other + restrictions put forward later), full-channel swizzle for both source operands and per-channel mask + for destination operand are supported on a 4-component basis. In other words, the control and + setting of full source swizzle and destination mask are repeated for every 4 components up to total + of ExecSize channels. + o The align16 access mode can be used for AOS operations. See examples provided in + the Primary Usage Model section for SIMD4x2 and SIMD4x1 modes of operation to + support 3D API Vertex Shader and Geometric Shader execution. + +  1-byte Aligned Access Mode (align1): In this mode, the origins of all operands may be aligned to + their data type and could be 1-byte if the operand is of byte type. In this access mode, full region + register descriptions are supported, however, source swizzle or destination mask are not supported. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 67 + o The align1 access mode can be used for SOA operations. See examples provided in + the Primary Usage Model section for SIMD8 and SIMD16 modes of operation to + support 3D API Pixel Shader. Many media applications also operate well in align1 + access mode. + + +3.3.8 Execution Data Type +The GEN architecture carries out arithmetic and logical operations using a smaller set of data types than +the variety supported as source or destination operands. These are the execution data types. A particular +arithmetic or logical instruction has one execution data type, from those listed in the table. + +Execution Data Types +Type Description + W Word. 16-bit signed integer. + D Doubleword. 32-bit signed integer. + F Float. 32-bit single precision floating-point number. + DF Double Float. 64-bit double precision floating-point number. + +The following rules explain the conversion of multiple source operand types, possibly a mix of different +types, to one common execution type: + +  For floating-point sources, all source operands must have the same floating-point type, with the + exception that a two-source floating-point instruction can have Float as the src0 type and VF + (Packed Restricted Float Vector) as the immediate src1 type. +  Mixing floating-point and integer source types is not allowed. Either all source types must be one + floating-point type or all source types must be integer types. +  Unsigned integers are converted to signed integers. +  Byte (B) or Unsigned Byte (UB) values are converted to a Word or wider integer execution type. +  If source operands have different integer widths, use the widest width specified to choose the signed + integer execution type. + +Note that when the execution data type is an integer type, it is always a signed integer type. For integer +execution types, extra precision is provided within the hardware, including the accumulators, so that +conversions from unsigned to signed do not affect instruction correctness. + + +3.3.9 Register Region Restrictions +A register region is described as packed if its elements are adjacent in memory, with no intervening +space, no overlap, and no replicated values. If there is more than one element in a row, elements must be +adjacent. If there is more than one row, rows must be adjacent. When two registers are used, the +registers must be adjacent and both must exist. +The following register region rules apply to the GEN implementation. Rules and restrictions for +compressed instructions are in the Instruction Compression section. +1. General Restrictions Based on Operand Types + There are these general restrictions based on operand types: + A. Where n is the largest element size in bytes for any source or destination operand type, ExecSize + * n must be <= 64. + B. When the Execution Data Type is wider than the destination data type, the destination must be + aligned as required by the wider execution data type and specify a HorzStride equal to the ratio + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 68 + in sizes of the two data types. For example, a mov with a D source and B destination must use + a 4-byte aligned destination and a Dst.HorzStride of 4. +2. General Restrictions on Regioning Parameters + The mapping of data elements within the region of a source operand is in row-major order and is + determined by the region description of the source operand, the destination operand, and the + ExecSize, with these restrictions: + A. ExecSize must be greater than or equal to Width. + B. If ExecSize = Width and HorzStride ≠ 0, VertStride must be set to Width * HorzStride. + C. If ExecSize = Width and HorzStride = 0, there is no restriction on VertStride. + D. If Width = 1, HorzStride must be 0 regardless of the values of ExecSize and VertStride. + E. If ExecSize = Width = 1, both VertStride and HorzStride must be 0. This defines a scalar. + F. If VertStride = HorzStride = 0, Width must be 1 regardless of the value of ExecSize. + G. Dst.HorzStride must not be 0. + H. VertStride must be used to cross GRF register boundaries. This rule implies that elements within + a ‘Width’ cannot cross GRF boundaries. +3. Region Alignment Rules + A. In Direct Addressing mode, a source cannot span more than 2 adjacent GRF registers. + B. A destination cannot span more than 2 adjacent GRF registers. + C. When an instruction has a source region spanning two registers and a destination region + contained in one register, one of the following must be true: + i. The destination region is entirely contained in the lower OWord of a register. + ii. The destination region is entirely contained in the upper OWord of a register. + iii. The destination elements are evenly split between the two OWords of a register. + + + D. When an instruction has a source region that spans two registers and the destination spans two + registers, the destination elements must be evenly split between the two registers and each + destination register must be entirely derived from one source register. Note: In such cases, the + regioning parameters must ensure that the offset from the two source registers is the same. + The examples below illustrate the behavior of the cases permitted: + + // Case (a) First 8 elements are from r12 to r10 and second from r13 to r11: + mov (16) r10.0<2>:w r12<16;8,1>:w + // The above instruction behaves the same as the following two instructions: + mov (8) r10.0<2>:w r12<16;8,1>:w + mov (8) r11.0<2>:w r13<16;8,1>:w + + // Case (b) First 8 elements from r12.8 to r10 and second from r13 to r11: + mov (16) r10.0<2>:w r12.8<16;8,1>:w + // The above instruction behaves the same as the following two instructions: + mov (8) r10.0<2>:w r12.8<16;8,1>:w + mov (8) r11.0<2>:w r13.8<16;8,1>:w + + + The following examples indicate cases that are not allowed: + // Not allowed, because the source has 12 elements from r12 and 4 from r13: + mov (16) r10.0<2>:w r12.4<4;4,1>:w + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 69 + // Not allowed, because the destination has 6 elements in r10 and 10 in r11: + mov (16) r10.2<2>:w r12<16;8,1>:w + + // Not allowed, because the source has only one GRF register + // but the destination spans two registers: + mov (16) r10.0<2>:w r12.0<8;8,1>:w + + + E. When destination spans two registers, the source MUST span two registers. The exception to the + above rule: + i. When source is scalar, the source registers are not incremented. + ii. When source is packed integer Word and destination is packed integer DWord, the source + register is not incremented by the source sub register is incremented. + The examples below illustrate the behavior of the cases permitted: + + // Case (a) Scalar source: + mov (16) r10.0<2>:w r12.0<0;1,0>:w + // The above instruction behaves the same as the following two instructions: + mov (8) r10.0<2>:w r12.0<0;1,0>:w + mov (8) r11.0<2>:w r12.0<0;1.0>:w + + // Case (b) First 8 elements from r12 to r10 and second from r12.8 to r11: + mov (16) r10.0<1>:d r12<8;8,1>:w + // The above instruction behaves the same as the following two instructions: + mov (8) r10.0<1>:d r12<8;8,1>:w + mov (8) r11.0<1>:d r12.8<8;8,1>:w + + + F. With the exception of the two rules in “Special Cases for Byte Operations” below, all destination + data elements must be aligned to the size for the execution data type of the instruction. For + example, if one of the source operands is in DWord mode (a float, a signed or unsigned DWord + integer), the execution data type is either float or signed DWord integer. Therefore the + destination data type must be DWord-aligned. This rule has the following two implications: + i. The destination sub-register must be aligned to the size of the execution data type. + ii. If ExecSize is greater than 1, Dst.HorzStride * sizeof(Dst.DstType) must be greater than or + equal to the size of the execution data type. +4. Special Cases for Byte Operations + A. When the destination type is byte (UB or B) only a ‘raw move’ using the mov instruction supports + a packed byte destination register region: Dst.HorzStride = 1 and Dst.DstType = (UB or B). This + packed byte destination register region is not allowed for any other instructions, including a ‘raw + move’ using the selinstruction, because the sel instruction is based on Word or DWord wide + execution channels. + B. There is a relaxed alignment rule for byte destinations. When the destination type is byte (UB or + B), destination data types can be aligned to either the lowest byte or the second lowest byte of + the execution channel. For example, if one of the source operands is in word mode (a signed or + unsigned word integer), the execution data type will be signed word integer. In this case the + destination data bytes can be either all in the even byte locations or all in the odd byte + locations. This rule has two implications illustrated by this example: + + // Example: + mov (8) r10.0<2>:b r11.0<8;8,1>:w + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 70 + mov (8) r10.1<2>:b r11.0<8;8,1>:w + + // Dst.HorzStride must be 2 in the above example so that the destination + // subregisters are aligned to the execution data type, which is :w. + // However, the offset may be .0 or .1. + // This special handling applies to byte destinations ONLY. +5. Special Requirements for Handling Double Precision Data Types + A. In Align1 mode, all regioning parameters like stride, execution size, and width must use the + syntax of a pair of packed floats. The offsets for these data types must be 64-bit aligned. The + execution size and regioning parameters are in terms of floats. + + // Example: + mov (8) r10.0<1>:df r11.0<8;8,1>:df + // The above instruction moves four double floats. + + + B. In Align16 mode, all regioning parameters must use the syntax of a pair of packed floats, + including channel selects and channel enables. + + // Example: + mov (8) r10.0.xyzw:df r11.0.xyzw:df + // The above instruction moves four double floats. The .x picks the + // low 32 bits and the .y picks the high 32 bits of the double float. + + + C. When using Align16 mode for conversion of data elements of different sizes, both source and + destination must be one register each. +6. Regioning Rules for Register Indirect Addressing + A. When the execution size and destination regioning parameters require two registers, each + register is pointed to by adjacent index registers. + + // Example: + mov (16) r[a0.0]:f r10:f + // The above instruction behaves the same as the following two instructions: + mov (8) r[a0.0]:f r10:f + mov (8) r[a0.1]:f r11:f + + + B. When the destination requires two registers and the sources are indirect, the sources must use + 1x1 regioning mode. In addition, the sources are assembled from two GRF registers each + accessed by adjacent index registers in 1x1 regioning modes. The data for each destination + GRF register is entirely derived from one source register. + Note: There is an exception to this rule. When source is scalar, the indirect address is not + incremented. + + // Example: + // Case (a): + add (16) r[a0.0]:f r[a0.2]:f r[a0.4]:f + // The above instruction behaves the same as the following two instructions: + add (8) r[a0.0]:f r[a0.2]:f r[a0.4]:f + add (8) r[a0.1]:f r[a0.3]:f r[a0.5]:f + // Each access, source and destination, is a 1x1 regioning access. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 71 + // Case (b): + add (16) r[a0.0]:f r[a0:2]:f r[a0.4]<0;1,0>:f + // The above instruction behaves the same as the following two instructions: + add (8) r[a0.0]:f r[a0.2]:f r[a0.4]<0;1,0>:f + add (8) r[a0.1]:f r[a0.3]:f r[a0.4]<0;1,0>:f + // Note that the src1 indirect address does not change. + + + C. Indirect addressing on src1 must be a 1x1 indexed region mode. + D. When a Vx1 or a VxH addressing mode is used on src0, the destination must use ONLY one + register. + E. Indirect addressing on the destination must be a 1x1 indexed region mode. + F. Data elements referenced by a single index within a source region cannot cross a 256-bit register + boundary. This applies to a register region with a single index or with multiple indices. + G. A register region with multiple indices may access multiple registers if the data elements + associated with each index follow the above-mentioned rule. + + // Example: + mov (16) r10.0:w r[a0.0]<2,2>:w + // This instruction gathers source elements pointed to by up to 8 + // different physical GRF registers, where two elements accessed + // by each indirect access are from one physical GRF register. + + +7. Special Restrictions + A. In Align16 access mode, SIMD16 is not allowed for DW operations and SIMD8 is not allowed for + DF operations. + B. When an instruction is SIMD32, the low 16 bits of the execution mask are applied for both halves + of the SIMD32 instruction. If different execution mask channels are required, split the instruction + into two SIMD16 instructions. + C. Instructions with condition modifiers must not use SIMD32. + D. All flow control (branching) instructions must use the Align1 access mode. + + +3.3.10 Destination Operand Description + +3.3.10.1 Destination Region Parameters +Based on the above restrictions, a subset of register region parameters are sufficient to describe the +destination operand: + +  Destination Register Origin + o Destination Register Number and Destination Subregister Number for direct register + addressing mode + o A Scalar Destination Register Index for register-indirect-register addressing mode + +  Destination Register ‘Region’ – Note that destination register region does not have full region + description parameters + o Destination Horizontal Stride + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 72 + 3.4 SIMD Execution Control + +3.4.1 Predication +Predication is the conditional SIMD channel selection for execution on a per instruction basis. It is an +efficient way of dynamic SIMD channel enabling without paying branch instruction overhead. When +predication is enabled for an instruction, a Predicate Mask (PMask), which contains 16-bit channel +enables, is generated internally in EU. Note that PMask is not a software visible register. It is provided +here to explain how SIMD execution control works. PMask generation is based on the Predication Control +(PredCtrl) field, Predication Inversion (PredInv) field and the flag source register in the instruction word. +See Instruction Summary chapter for definition of these fields. +Predication shows the block diagram of the hardware logic to generate PMask. PMask is generated +based on combinatory logic operation of the bits in the flag register. Instruction field PredCtrl controls the +horizontal evaluation unit and vertical evaluation unit. MUX A in the figure selects whether horizontally- +evaluated results or vertically-evaluated results are sent to the Predication Invertion unit. The PredInv +field controls the Prediction Inversion unit. Either one 16-bit flag subregister or the whole flag register may +be selected to generate the PMask depending on the predication control modes. MUX B indicates that +predication can be enabled and disabled. Predication can be grouped into the following three categories. +Predication functionality also depends on the Access Mode of the instruction. + +  No predication: Of course, predication can be disabled. This is the most commonly used case. +  Predication with horizontal combination: the predicate mask is generated based on combinatory + logic operation of bits within a selected flag subregister. +  Predication with vertical combination: the predicate mask is generated based on combinatory logic + operation of bits across flag multiple subregisters. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 73 + Generation of predication mask + + + + +3.4.2 No Predication +When PredCtrl field of a given instruction is set to 0 (“no predication”), it indicates that no predication is +applied to this instruction. Effectively, the resulting PMask is all 1’s. This is shown by the 2:1 multiplexer B +controlled by the Pred Enable signal in Predication. Where predication is not enabled for an instruction, +multiplex B is selected to output 0xFF to PMask. + + +3.4.3 Predication with Horizontal Combination +Predication with horizontal combination inputs the 16 bits of a single flag subregister (f0.0:uw or f0.1:uw) +and passes them through combinatory logic of the Horizontal Evaluation unit to create PMask. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 74 + The simplest combination is ‘no combination’ – the same 16 bits from selected flag subregister are output +to MUX A. In this case, a bit in the selected flag subregister controls the conditional execution of the +corresponding execution channel. Let the selected flag subregister be denoted as f0.#, the following +pseudo code describes the predicate mask generation for predication with sequential flag channel +mapping. + If (PredCtrl == “Sequential flag channel mapping”) { +For (ch=0; ch<16; ch++) +PMask[ch] = (PredInv == TRUE) ? ~f0.#[ch] : f0.#[ch]; + } +More complex horizontal evaluation is based on channel grouping. A group of adjacent channels (bits +from flag subregister) are evaluated together and a single bit is replicated to the group. The size of groups +is in power of 2. The supported combination depends on the Access Mode of an instruction. +In Align16 access mode, horizontal combination is based on 4-channel groups. + +  Channel replication: PredCtrl of ‘.x’, ‘.y’, ‘.z’ and ‘.w’ select a single channel from each 4-channel + group and replicate it as the output for the group. For example, PredCtrl = ‘.x’ means that channel 0 + in each group is replicated. +  OR combination: PredCtrl of ‘.any4h’ means that if any of the channel in a group is enabled, outputs + for the 4 channels in the group are all enabled. +  AND combination: PredCtrl of ‘.all4h’ means that only when all of the channels in a group are + enabled, the output for the group is enabled. + +These combinations in Align16 mode can be described by the following pseudo-code. + If (Access Mode == Align16) { +For (ch = 0; ch < 16; ch += 4) +Switch (PredCtrl) { +Case ‘.x’: bTmp = f0.#[ch]; break; +Case ‘.y’: bTmp = f0.#[ch+1]; break; +Case ‘.z’: bTmp = f0.#[ch+2]; break; +Case ‘.w’: bTmp = f0.#[ch+3]; break; +Case ‘.any4h’: bTmp = f0.#[ch] | f0.#[ch+1] | f0.#[ch+2] | f0.#[ch+3]; break; +Case ‘.all4h’: bTmp = f0.#[ch] & f0.#[ch+1] & f0.#[ch+2] & f0.#[ch+3]; break; + } + bTmp = (PredInv == TRUE) ? ~bTmp : bTmp; + PMask[ch] = PMask[ch+1] = PMask[ch+2] = PMask[ch+3] = bTmp; + } + } +In Align1 access mode, horizontal combination is based on AND combination ‘.any#h’ and OR +combination ‘.all#h’ on channel groups with various sizes, where # is the number of channels in a group +ranging from 2 to 16. This is described by the following pseudo-code. + If (Access Mode == Align1) { + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 75 + Switch (PredCtrl) { +Case ‘.any2h’: groupSize = 2; = ‘|’; break; +Case ‘.all2h’: groupSize = 2; = ‘&’; break; +Case ‘.any4h’: groupSize = 4; = ‘|’; break; +Case ‘.all4h’: groupSize = 4; = ‘&’; break; +Case ‘.any8h’: groupSize = 8; = ‘|’; break; +Case ‘.all8h’: groupSize = 8; = ‘&’; break; +Case ‘.any16h’: groupSize = 16; = ‘|’; break; +Case ‘.all16h’: groupSize = 16; = ‘&’; break; +} +For (ch = 0; ch < 16; ch += groupSize) { +For (inc = 0, bTmp = FALSE; inc < groupSize; inc ++) + bTmp = bTmp f0.#[ch+inc]; + For (inc = 0; inc < groupSize; inc ++) +PMask[ch+inc] = bTmp; + } + } + + +3.4.4 Predication with Vertical Combination +Predication with vertical combination uses both flag subregister as inputs. The AND or OR combination is +across the subregisters on a channel by channel basis. This is shown by the following pseudo-code. + If (Access Mode == Align1) { +For (ch = 0; ch < 16; ch ++) { +If (PredCtrl == ‘any2v’) +PMask[ch] = f0.0[ch] | f0.1[ch] +Else If (PredCtrl == ‘any2h’) +PMask[ch] = f0.0[ch] & f0.1[ch] +} + } + + +3.5 End of Thread +There is no special instruction opcode (such as an END instruction) to cause the thread to terminate +execution. Instead, the end of thread is signified by a send instruction with the end-of-thread (EOT) +sideband bit set. Upon executing a send instruction with EOT set, the EU stops on the thread. Upon +observing an EOT signal on the output message bus, the Thread Dispatcher makes the thread’s resource +available. If a thread uses pre-allocated resource managed by a fixed function, such as URB handles and + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 76 + scratch memory, some fixed function protocol also requires the thread to terminate with the message +header phase to carry the information in order for the fixed function to release the pre-allocated resource. +EU hardware guarantees that if a terminated thread has in-flight read messages or loads at the time of +‘end’ that their writebacks will not interfere with either other threads in the system or new threads loaded +in the system in the future. +More details can be found in the send instruction description in Instruction Reference chapter. + + +3.6 Assigning Conditional Flags +Instructions can output two sets of conditional signals, one set from before the outputs clamping/re- +normalizing/format conversion logic, we call this the pre conditional signals. The second set is generated +from the final results after clamping and re-normalizing/format conversion logic, and we call this the post +conditional signals. The post conditional signals are used for fusing the DirectX compare instruction. +Note: The flags generated from the post conditional signals should be equivalent to the flags generated +by a separate cmp instruction after the current arithmetic instruction. +The pre conditional signals are used to generated flags for cmp/cmpn instructions only, this logically does +the compare of the two input sources. The post conditional signals are used to generated flags for all the +other arithmetic instructions, this logically does the compare of the result with zero. +cmpn with both sources as NaNs is a don't care case as this doesn't impact the MIN/MAX operations. +The pre conditional signals include the following: + +  pre_sign bit: This bit reflects the sign of the computed result before going through any kind of + clamping, normalizing, or format conversion logic. +  pre_zero bit: This bit reflects whether the computed result is zero before any kind of clamping, + normalizing, or format conversion logic. + +The post conditional signals include the following: + +  post_sign bit: This bit reflects the sign of the final result after all the clamping, normalizing, or format + conversion logic. +  post_zero bit: This bit reflects whether the final result is zero after all the clamping, normalizing, or + format conversion logic. +  OF bit: This bit reflects whether an overflow occured in any of the computation of the current + instruction, including clamping, re-normalizing, and format conversion. +  NC bit: The NaN computed bit indicates whether the computed result is not a number. It carries valid + information for instructions operating on floating point values. For an operation on integer operands, + this bit is always 0. +  NS0 bit: The NaN Source 0 bit indicates whether src0 of an execution channel is not a number. It + carries valid information for instructions operating on floating point values. For an operation on + integer operands, this bit is always 0. +  NS1 bit: The NaN Source 1 bit indicates whether src1 of an execution channel is not a number. It + carries valid information for instructions operating on floating point values. For an operation on + integer operands, this bit is always 0. For an operation with one source operand, this bit is also set to + 0. This bit is only used for the comparison instruction cmpn, which is specifically provided to emulate + MIN/MAX operations. For any other instructions, this bit is undefined. +  Note that the bits generated at the output of a compute are before the .sat. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 77 + Flag Generation for cmp Instructions (The Supported Conditional Modifiers are .e, .ne, .g, .ge, .l, +and .le.) + Conditional + Modifier Meaning Resulting Flag Value (for an execution channel) + .e Equal-to + (pre_zero & ! (NS0 | NS1)). This conditional modifier tests whether the two + sources are equal. + If either source is NaN (i.e. NC is true), the flag is forced to false. + .ne Not-Equal-to + ! (pre_zero & ! (NS0 | NS1)). This conditional modifier test whether the two + sources are equal. It takes exactly the reverse polarity as the modifier .e. + .g Greater-than + ( ! pre_sign & ! pre_zero & ! (NS0 | NS1)). This conditional modifier tests + whether src0 is greater than src1. + If either source is a NaN (i.e. NC is true), the flag is forced to false. + .ge Greater-than-or- + ((! pre_sign | pre_zero) & ! (NS0 | NS1)). This conditional modifier tests whether + equal-to + src0 is greater than or equal to src1. + If either source is a NaN (i.e. NC is true), the flag is forced to false. + .l Less-than + (pre_sign & !pre_zero & ! (NS0 | NS1)). This conditional modifier tests whether + src0 is less than src1. + If either source is a NaN (i.e. NC is true), the flag is forced to false. + .le Less-than-or- + ((pre_sign | pre_zero) & ! (NS0 | NS1)). This conditional modifier tests whether + equal-to + src0 is less than or equal to src1. + If either source is a NaN (i.e. NC is true), the flag is forced to false. + + +Flag Generation for cmpn Instructions (The Supported Conditional Modifiers are .ge, and .l) + Conditional + Modifier Meaning Resulting Flag Value (for an execution channel) + .ge Greater-than- + (! pre_sign | (NS1 & (Opcode == cmpn | Opcode == sel with CMod))) & ! (NS0 & + or-equal-to + (Opcode == cmpn)). This conditional modifier tests whether src0 is greater than or + equal to src1. + If src1 is a NaN (i.e. NS is true), the flag is forced to true. + .l Less-than + (pre_sign | (NS1 & (Opcode == cmpn | Opcode == sel with CMod))) & ! (NS0 & + (Opcode == cmpn)). This conditional modifier tests whether src0 is less than src1. + If src1 is a NaN (i.e. NS is true), the flag is forced to true. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 78 + Flag Generation for All Instructions Other than cmp/cmpn Instructions (The Supported +Conditional Modifiers are .e, .ne, .g, .ge, .l, .le, .o, and .u.) + Conditional + Modifier Meaning Resulting Flag Value (for an execution channel) + .e Equal-to + (post_zero & ! NC). This conditional modifier tests whether the result is equal to + zero. + If either source is NaN (i.e. NC is true), the flag is forced to false. + .ne Not-Equal-to + ! (post_zero & ! NC). This conditional modifier test whether the result is not + equal to zero. + It takes exactly the reverse polarity as modifier .e. + .g Greater-than + (! post_sign & ! post_zero & ! NC). This conditional modifier tests whether + result is greater than zero. + If either source is a NaN (i.e. NC is true), the flag is forced to false. + .ge Greater-than-or- + ((! post_sign | post_zero) & ! NC). This conditional modifier tests whether result + equal-to + is greater than or equal to zero. + If either source is a NaN (i.e. NC is true), the flag is forced to false. + .l Less-than + (post_sign & ! post_zero & ! NC). This conditional modifier tests whether result + is equal to zero. + If either source is a NaN (i.e. NC is true), the flag is forced to false. + .le Less-than-or- + ((post_sign | post_zero) & ! NC). This conditional modifier tests whether result + equal-to + is equal to or less than zero. + If either source is a NaN (i.e. NC is true), the flag is forced to false. + .o Overflow + OF. This conditional modifier tests whether the computed result causes overflow + – the computed result is outside the range of the destination data type. + All other internal conditional signals are ignored. + .u Unordered + NC. This conditional modifier tests whether the computed result is a NaN + (unordered). + All other internal conditional signals are ignored. + + + +3.7 Destination Hazard +The architecture has built-in hardware to avoid destination hazard. +Destination Hazard stands for the risk condition when multiple operations are trying to write to the same +destination and the result of the destination may be ambiguous. This may or may not happen on GEN for +two instructions with the same destination, or with destinations that have overlapped register region, +depending on the ordering of the arrival of destination results. Let’s consider two instructions in a thread +with potential destination hazard. There may be other instruction between them as long as there is no +instruction sourcing the same destination. Using register scoreboards, GEN hardware automatically takes +care of the destination hazard by not issuing the second instruction until the destination scoreboard is +cleared. However, for certain cases, in fact for most cases, such destination hazard indicated by the + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 79 + register scoreboard is false, causing unnecessary delay of instruction issuing. This may result in lower +performance. The destination dependency control field in the instruction word {NoDDClr, NoDDhk} allows +software to selectively override such hardware destination dependency mechanism. Such performance +optimization hooks must be used with extreme caution. When it is not certain that it is a false destination +hazard, the programmer should rely on hardware to resolve the dependency. +As the destination dependency control field does not apply to send instruction, there is only one condition +that a programmer may use the {NoDDClr, NoDDChk} capability. + +  If none of the two instructions is send, there CANNOT be any destination hazard. This is because + instructions within a thread are dispatched in order (single-issued) and the execution pipeline is in- + order and has a fixed latency. + +When a sequence of NoDDChk and NoDDClr are used, the last instruction that completes the scoreboard +clear must have a non-zero execution mask. This means, if any kind of predication can change the +execution mask or channel enable of the last instruction, the optimization must be avoided. This is to +avoid instructions being shot down the pipeline when no writes are required. +Example: +(f0.0) mov r10.0 r11.0 {NoDDClr} +(-f0.0) mov r10.0 r11.0 {NoDDChk, NoDDClr} +In the above case, if predication can disable all writes to r10 for the second instructions, the instruction +maybe shot down the pipeline resulting in un-deterministic behavior. Hence, This optimization must not +be used in these cases. + + +3.8 Non-present Operands +Some instructions do not have two source operands and one destination operand. If an operand is not +present for an instruction the operand field in the binary instruction must be filed with null. Otherwise, +results are unpredictable. +Specifically, for instructions with a single source, it only uses the first source operand src0. In this case, +the second source operand src1 must be set to null and also with the same type as the first source +operand src0. It is a special case when src0 is an immediate, as an immediate src0 uses DW3 of the +instruction word, which is normally used by src1. In this case, src1 must be programmed with register file +ARF and the same data type as src0. + + +3.9 Instruction Prefetch +Due to prefetch of the instruction stream, the EUs may attempt to access up to 8 instructions (128 bytes) +beyond the end of the kernel program – possibly into the next memory page. Although these instructions +will not be executed, software must account for the prefetch in order to avoid invalid page access faults. +One possible (though inefficient) solution would be to pad the end of all kernel programs with 8 NOOP +instructions. A more efficient approach would be to ensure that the page after all kernel programs is at +least valid (even if mapped to a dummy page). Note that the General State Access Upper Bound field +of the STATE_BASE_ADDRESS command can be used to prevent memory accesses past the end of the +General State heap (where kernel programs must reside). + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 80 + 4. Exceptions +The Architecture defines a basic exception handling mechanism for several exception cases. This +mechanism supports both normal operations such as extensions of the mask-stack depth, as well as +detecting some illegal conditions . + +Exception Types + Type Trigger / Source Sync/Async Recognition +Software Exception Thread code Synchronous +Breakpoint  A bit in the instruction word Synchronous + +  Breakpoint IP match +  Breakpoint Opcode match + + Hardware Synchronous +Illegal Opcode +Halt MMIO register write Asynchronous +Context Save/Restore Preemption Interrupt Asynchronous + +Threads may choose which exceptions to recognize and which to ignore. This mask information is +specified on a per-kernel basis in fixed function state generated by the driver, and delivered to the EU as +part of a new thread dispatch. Upon arrival at the EU, the exception-mask information is used to initialize +the exception enable fields of that thread's cr0.1 register, which controls exception recognition. This +register is instantiated on a per-thread basis, allowing independent control of exception type recognition +across hardware threads. The exception enable bits in the cr0.1 register are read/write, and thus can be +enabled/disabled via software at any time during thread execution. +The exception handling mechanism relies on the System Routine, a single subroutine that provides +common exception handling for all threads on all EUs in the system. This System Routine is defined per- +context and is identified via a System IP (SIP) register in context state. At the time of each context switch, +the appropriate SIP for that context is loaded into each EU, allowing each context to have custom +implementation of exception handling routines if so desired. + + +4.1 Exception-Related Architecture Registers +Exception-related registers are architecture registers cr0.0 through cr0.2. These registers are instantiated +on a per-thread basis providing each hardware thread with unique control over exception recognition and +handling. The registers provide the capability to mask exception types, determine the type of raised +exception, store the return address, and control exiting from the System Routine back to the application +thread. +Many of the bits in these registers are manipulated by both hardware and software. In all cases, the +read/write operations by hardware and software occur at exclusive times in a thread's lifetime, thus there +is no need for atomic read-modify-write operations when accessing these registers. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 81 + 4.2 System Routine +The following diagram illustrates the basic flow of exception handling and the structure of the System +Routine. + + + + +4.2.1 Invoking the System Routine +The System Routine is invoked in response to a raised exception. Once an exception is raised, no further +instructions from the application thread are issued until the System Routine has executed and returned +control back to the application thread. +After an exception is recognized by hardware, the EU saves the thread's IP into its AIP register (cr0.2), +and then moves the System Routine offset, SIP, into the thread's IP register. At this point the next +instruction issued for that thread is the first instruction of the System Routine. +The System Routine maintains the same execution priority, GRF register space, and thread state as the +application thread from which it is invoked. Due to assuming the same priority, there may be significant + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 82 + absolute time between an exception being raised and invoking the System Routine, as other higher +priority threads within the EU continue to execute. From a thread's perspective, once an exception is +recognized, the next instruction issued is from the System Routine. +At the time of System Routine invocation, there may still be outstanding registers in-flight from the +application thread. Depending on the instruction sequence in the System Routine, an in-flight register +may be referenced by the System Routine and cause a register-in-flight dependency. These +dependencies are honored by the System Routine and may cause the System Routine to be suspended +until the register retires. +Exception processing is not nested within the System Routine. If a future exception is detected while +executing the System Routine, the exception is latched into cr0.1, but does not cause a nested re- +invocation of the System Routine. The exception recognition hardware recognizes only one outstanding +exception of each type; i.e., once a specific exception type is detected and latched in cr0.1, and until the +exception is cleared, any further exception of that type is lost. +Accumulators are not natively preserved across the System Routine. To make sure the accumulators are +in the identical state once control is returned to the application thread, the System Routine must either set +the Accumulator Disable bit of cr0.0 before using any instruction that modifies an accumulator, or save +and restore the accumulators (using GRF registers or system thread scratch memory) around the System +Routine. Saving and restoring accumulators, including their extended precision bits, can be accomplished +by a short series of moves and shifts of the accumulator register. Also note that the state of the +Accumulator Disable bit itself must be preserved unless, by convention, the driver software limits its +manipulation to only the System Routine. +Further, upon System Routine entry, the execution-related masks (Continue, Loop, If, and Active masks, +contained in the Mask Register) will remain set as they were in the application thread. Thus only a subset +of channels may be active for execution. To enable execution on all channels, the System Routine may +choose to use the instruction option ‘NoMask’, or may choose to set the mask registers to the desired +value so long as it saves/restores the original masks upon System Routine entry/exit. +Similarly there is no hardware mechanism to preserve flags, mask-stacks, or other architecture registers +across the System Routine. The System Routine must ensure that these values are preserved (see the +Conditional Instructions Within the System Routine section for related information). + + +4.2.2 Returning to the Application Thread +Prior to returning control to the application thread, the System Routine should clear the proper Exception +Status and Control bit in cr0.1. Failure to do so forces the thread's execution to reenter the System +Routine before any further instructions are executed from the application thread. (Note that single- +stepping functionality is the one exception where the exception's Status and Control bit is not reset before +exit.) +The System Routine may choose to loop within a single invocation of the System Routine until all pending +exceptions are serviced, or may choose to service exceptions one at a time (a simpler solution, but less +efficient). +The System Routine is exited, and control returned to the application thread, via a write to the Master +Exception State and Control bit in cr0.0. Upon clearing this bit, the value of AIP (cr0.2) is restored to the +thread’s IP register and, with no further exceptions pending, execution resumes at that address. The +System Routine must follow any write to the Master Exception State and Control bit with at least one +SIMD-16 nop instruction to allow control to transition. Throughout the System Routine, the AIP register +maintains its value at the time the exception was raised unless directly modified by the System Routine. +(See the AIP register definition for specifics on the IP value saved to AIP). + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 83 + 4.2.3 System IP (SIP) +The System IP (SIP) is the 16 byte-aligned offset of the first instruction of the System Routine, relative to +the General State Base Address. SIP is assigned by the STATE_SIP command to the command +streamer which updates SIP in the EU. +When the System Routine is invoked, the application thread's current IP is first saved into the AIP field of +cr0.2. The SIP address is then loaded into the thread's IP register and execution continues within the +System Routine. Thus each invocation of the System Routine has a common entry point. Returning from +the System Routine loads IP from AIP, continuing thread execution. + + +4.2.4 System Routine Register Space +The System Routine uses the same GRF space as the thread that invokes it. As such all of the calling +thread's registers and their contents are visible to the System Routine. Further, the System Routine must +only use r0..r15 of the GRF, as a minimal thread may have requested and been allocated this few. If the +System Routine requires more registers than this, the driver should establish a higher minimum allocation +for all threads. +The System Routine may encounter any residual register dependencies of the calling thread until such +time that they clear by the return of in-flight writebacks. +Only one 32-bit GRF location, r0.4, is reserved for System Routine use. This location is sufficient to allow +the System Routine to calculate the appropriate offset of its private scratch memory in the larger system +scratch memory space (as dictated by binding table entry 254). The offset is left as a driver convention, +but is likely based on a combination of Thread and EU IDs (see the example system handler in the +System Scratch Memory Space) section. Other than the reserved r0.4 register field, there is no explicit +GRF register space dedicated to the System Routine, and any GRF needs must be accomplished via (a) +convention between the System Routine and application code, or (b) the System Routine temporarily +spilling the thread's GRF register contents to scratch memory and restoring those contents before System +Routine exit. +No persistent storage is automatically allocated to the System Routine, although a driver implementation +may set aside part of system scratch memory for the System Routine. +Any parameter passing to the System Routine (for use by software exceptions) is done via the GRF +based on system thread/application thread convention. + + +4.2.5 System Scratch Memory Space +There is a single unified system scratch memory space per context shared by all EUs. It is anticipated +that block is further partitioned into a unique scratch sub-space per thread via conventions implemented +in the System Routine, with each hardware thread having a uniform block size at a calculated offset from +the base address. The block address for a thread can be based on an offset derived from the thread's +execution unit ID and thread ID made available through the TID and EUID field of architecture register +sr0.0. + Per_Thread_Block_Size = System_Scratch_Block_Size / (EU_Count * Thread_Per_EU); + Offset = (sr0.0.EID * Threads_Per_EU + sr0.0.TID) * Per_Thread_Block_Size; +where in GEN: +Threads_Per_EU = 4 +EU_Count = 8 + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 84 + System_Scratch_Block_Size is a driver choice. +Access to system scratch memory is performed through the Data Port via linear single register or block- +based read/write messages. The driver may choose to use any binding table index for system scratch +surface description. As a practical matter, the same index is expected to be used across all binding +tables, as the index is typically hard coded in Data Port messages used within the System Routine +coupled with the fact that a single System Routine is used for all threads. Read/write messages to the +Data Port contain the address of the binding table (provided in r0 of all threads) and an offset, from which +the Data Port calculates the final target address. +It is expected that the system scratch memory space is allocated by the driver at context-create time and +remains persistent at a constant memory address throughout a context's lifetime. + + +4.2.6 Conditional Instructions Within the System Routine +It is expected that most, if not all, control flow within the System Routine is scalar in nature. If so, the +System Routine should set SPF (Single Program Flow, cr0.0) to enable scalar branching. In this mode, +conditional/loop instructions do not update the mask stacks and therefore do not have restrictions on their +use nor require the save/restore of hardware mask stack registers. +If SIMD branching is desired within the System Routine, special considerations must be taken. Upon +entry to the System Routine, the depth of the mask stacks is unknown at that point, and may be near full. +If so, a subsequent conditional instruction and its associated mask ‘push’ may cause a stack overflow. +This would generate an exception within the system routine, an unsupported occurrence. To prevent this, +if the System Routine uses SIMD conditional instructions, it must save the mask stacks prior to the first +SIMD conditional instruction, and restore them after the last SIMD conditional instruction. As a general +solution, it may be easiest to simply implement the save/restore as part of the entry/exit code sequence, +using an available GRF register pair as a storage location. Once saved, the stacks should be reset to +their empty condition, namely depth = 0 and top of stack = 0xFFFFFFFF. + + +4.2.7 Use of NoDDClr +The instruction word defines an instruction option NoDDClr that overrides the native register dependency +clearing mechanism of the typical instruction. When specified, NoDDClr does not clear, at register +writeback time, the dependency placed on the destination register of the instruction. Use of this +mechanism may provided increased performance when a kernel can guarantee no dependency issues +between instructions, but may cause issues with exception handling in some circumstances as discussed +here. +Typically NoDDClr is used in an instruction series to enable a sequence of writes to sub-fields of a GRF +register without paying a dependency penalty on each instruction. In this case, NoDDClr and NoDDChk +are used across an instruction sequence to allow the first instruction to set the destination dependency, +interior instructions to write to the GRF register without dependency checks, and the last instruction to +clear the dependency. (This sequence is referred to as a NoDDClr code block going forward). By only +allowing the last instruction to clear the dependency, program execution is prevented from going beyond +a certain point until all writes of that sequence are known to retire. +The problem arises if an exception is raised within a NoDDClr code block. In this case, there exists the +potential for the System Routine to hang while attempting to save/restore a register used as a destination +register by the NoDDCLr code block, as the outstanding dependency on that register will not clear until +the final instruction of the NoDDCLr block is executed, sometime after the System Routine returns. +Should the System Routine attempt to use that register, it hangs waiting on a dependency to be cleared +by an instruction not yet issued. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 85 + Note: This is a known condition and will in some cases not allow the full GRF contents to be externally +visible in System Routine scratch space during a break or halt exception. +To avoid this condition, guidelines are provided below for consideration. (Note that these are general +guidelines, some of which can be alleviated through careful coding and register usage conventions and +restrictions.) + +  NoDDClr code blocks should only be used where absolutely necessary. +  Instructions that may generate exceptions should not be placed within NoDDClr blocks. This + includes most conditional branch instructions (if, do, while, ...) . +  If possible, use NoDDClr on registers high in the thread's register allocation (e.g. r120), thus even if + a System Routine hang occurs, as much of the GRF is visible as possible. (Note that this would also + require the System Routine to update the progress of the GRF dump, perhaps with each GRF block + written, or to initialize the System Routine's scratch space to a known value, to be able to distinguish + valid/locations from unwritten locations). + +Also a driver implementation may consider a disable-NoDDclr option in which jitted code does not use the +NoDDClr capability. In this case, there is no change to the code that is jitted other than removal of the +NoDDClr instruction option. The code executes as normal, but with a higher number of thread switches in +what would have been a NoDDClr code block. + + +4.3 Exception Descriptions +This section describes conditions that can cause exceptions and transfer control to the System Routine. + + +4.3.1 Illegal Opcode +The ISA defines a single illegal opcode. The byte value of the illegal opcode is 0x00 due to it being a +likely byte value encountered by a wayward instruction pointer value. The illegal instruction signals an +exception if exception handling is enabled and invokes the system interrupt routine. If exception handling +is NOT enabled, the illegal opcode is executed resulting in undetermined behavior including a system +hang. Hardware decodes all legal opcodes supported. Any byte value that is not in the legal opcode list is +decoded as an illegal opcode to trigger exception. + + +4.3.2 Undefined Opcodes +All undefined opcodes in the 8-bit opcode space (which includes instruction bit 7, reserved for future +opcode expansion) are detected by hardware. If an undefined opcode is detected, the opcode is +overridden by hardware, forcing the opcode value within the pipeline to the defined illegal opcode. The +offending instruction, should it eventually be issued down the execution unit’s pipeline, generates an +Illegal Opcode exception as described in the section Illegal Opcode. The memory location of the +offending opcode keeps its original value. That location can be queried to determine the opcode value. + + +4.3.3 Software Exception +A mechanism is provided to allow an application thread to invoke an exception and is triggered using the +Software Exception Set and Clear bit of cr0.1. Sub-function determination and parameter passing into +and out of the exception handler is left to convention between the system-thread and application-thread. +The thread's IP is incremented before saving AIP and entering the System Routine, causing execution to +resume at the next application-thread instruction after returning from the System Routine. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 86 + 4.3.4 Context Save and Restore +The System Routine is also used to save and restore the context of the Execution Unit. This feature is +enabled in GPGPU workloads only. +When the execution engine receives a preemption or an interrupt, the application thread invokes the +System Routine. The System Routine is invoked only when all in-flight registers have retired. The system +routine is used to save all the state of the EU to memory. When the sequence is complete, the master +exception control bit is cleared. This action stops all execution for the given thread and invalidates the +thread. This means a new thread from a different context may be loaded. When the master exception +control bit is cleared, software must ensure that all outstanding messages from the EU are dispatched out +of the execution message pipeline. This is achieved by creating a dependency on the last send that is +saving EU state. A dummy instruction before clearing the master exception control bit ensures that this is +achieved. +The System Routine is also invoked on a context restore request. In this case a dummy thread is loaded +into the EU which starts with the System Routine. This routine now restores the state of the EU. The +restore sequence used in such a case should be consistent with the save sequence to ensure that state +is restored correctly. After completing the restore sequence, the System Routine must clear the master +exception control bit in the Control Register. This enables hardware to switch to the application thread +which continues execution. + + +4.4 Events That Do Not Generate Exceptions +The conditions described in this section are either not recognized or do not generate an exception. + + +4.4.1 Illegal Instruction Format +This condition includes malformed instructions in which the opcode is legal, but the source or destination +operands or other instruction attributes do not comply with the instruction specification. There is no direct +hardware support to detect these cases and the outcome of issuing a malformed instruction is undefined. +Note that GEN does not support self-modifying code, therefore the driver has an opportunity to detect +such cases before the thread is placed in service. + + +4.4.2 Malformed Message +A message's contents, destination registers, lengths, and descriptors are not interpreted in any way by +the execution unit. Errors in specifying message fields do not raise exceptions in the EU but may be +detected and reported by the shared functions . + + +4.4.3 GRF Register Out of Bounds +Unique GRF storage is allocated to each thread which, at a minimum, satisfies the register requirements +specified in the thread's declaration. References to GRF register numbers beyond that called for in the +thread's declaration do not generate exceptions. Depending on the implementation, out-of-bounds +register numbers may be remapped to r0..r15, although this functionality should not be relied upon by the +thread. The hardware guarantees the isolation of each thread's register space, thus there is no possibility +of direct register manipulation via an out-of-bounds register access. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 87 + 4.4.4 Hung Thread +There is no hardware mechanism in the EU to detect a hung thread and such a thread may remain hung +indefinitely. It is expected that one or more hung threads will eventually cause the driver to recognize a +context timeout and take appropriate recovery action. + + +4.4.5 Instruction Fetch Out of Bounds +The EU implements a full 32-bit instruction address range (with the 4 LSBs don’t care), making it possible +for a thread to attempt to jump to any 16-byte aligned offset in the 32-bit instruction address range. +(Instruction addresses are offsets from the General State Base Address.) The EU does not provide any +type of address checking on instruction fetch requests sent to the memory/cache hierarchy, although +error conditions for memory addresses are reported via the Page Table Error Register and other memory +interface registers. + + +4.4.6 FPU Math Errors +The EU's floating point units (FPUs) have defined behaviors for traditional floating point errors and do not +generate exceptions. There is no support for signaling FPU math errors as exceptions. + + +4.4.7 Computational Overflow +Depending on source operand types and values, destination type, and the operation being performed, +overflows may occur in the execution pipelines. Many instructions support the overflow (.o) conditional +modifier that assigns flag bits based on whether or not an overflow occurs. +The EU never signals exceptions for overflows. Software must provide any overflow handling. + + +4.5 System Routine Example +The following code sequence illustrates some concepts of the System Routine. It is intended to be just a +shell, without getting into the specifics of each exception handler. +This example contains code for the message registers in the MRF. All message register and MRF +references are specific to DevSNB. Other code in this example is useful for other processor generations. +The example frees enough MRF and GRF space to get the routine started, then jumps to the handler for +the specific exception. Many other implementations are also valid, including single exception servicing (as +opposed to looping) per invocation, and saving only the GRF or MRF space required by the exception +being serviced. + #define ACC_DISABLE_MASK 0xFFFFFFFD + #define MASTER_EXCP_MASK 0x7FFFFFFF + #define SYSROUTINE_SCRATCH_BLKSIZE 16384 // for example + + // Shared function IDs: + #define DPR 0x04000000 + #define DPW 0x05000000 + + // Message lengths: + #define ML5 0x00500000 + #define ML9 0x00900000 + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 88 + // Response lengths: + #define RL0 0x00000000 + #define RL4 0x00040000 + #define RL8 0x00080000 + + // Data port block sizes: + #define BS1_LOW 0x0000 + #define BS1_HIGH 0x0100 + #define BS2 0x0200 + #define BS4 0x0300 + + // Scratch Layout: + #define SCR_OFFSET_MRF 0 // MRF is specific to DevSNB. + #define SCR_OFFSET_GRF 512 // + 16 MRF registers + #define SCR_OFFSET_ARF 512 + 4096 // + 16 MRF + 128 GRF registers + + // Write data port constants: + // target=dcache, type= oword_block_wr, binding_tbl_offset=0 + #define DPW 0x000 + + // Read data port constants: + // target=dcache, type= oword_block_rd, binding_tbl_offset=0 + #define DPR 0x000 + + Sys_Entry: // Entry point to the System Routine. + + // Disable accumulator for system routine: + and (1) cr0.0 cr0.0 ACC_DISABLE_MASK {NoMask} + + // Calc scratch offset for this thread into r0.4: + shr (1) r0.4 sr0.0:uw 6 {NoMask} + add (1) r0.4 r0.4 sr0.0:ub {NoMask} + mul (1) r0.4 r0.4 SYSROUTINE_SCRATCH_BLKSIZE {NoMask} + + // Setup m0 with block offset: + mov (8) m0 r0{NoMask} + + // Save MRF 7..0 (may choose to save the whole MRF). MRF is specific to DevSNB: + add (1) m0.2 r0.4 SCR_OFFSET_MRF {NoMask} + send (8) null m0 null DPW|ML9|RL0 {NoMask} + + // Save MRF 8..15 (optional; req’ed if sys-routine stays w/in mrf7-0). MRF is +specific to DevSNB. + mov (8) m7 r0 {NoMask} + add (1) m7.2 r0.4 (SCR_OFFSET_MRF + 256) {NoMask} + send (8) null m7 null DPW|ML9|RL0 {NoMask} + + // Save r0..r1 to system scratch: + // Note: done as a single register to guarantee external visibility + // See Use of NoDDClr mov (16) m1 r0 {NoMask} + send (8) m0 null null DPW|ML2|RL0 {NoMask} + + // Save r2..r3 to free some room: + mov (16) m3 r2 {NoMask} + add (1) m0.2 r0.4 SCR_OFFSET_GRF + 64 {NoMask} + send (8) m0 null null DPW|ML4|RL0 {NoMask} + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 89 + // Save r4..r7 to free some room (optional, depending on needs): + mov (16) m8 r4 {NoMask} + mov (16) m10 r6 {NoMask} + add (1) m7.2 r0.4 (SCR_OFFSET_GRF + 128) {NoMask} + send (8) m7 null null DPW|ML5|RL0 {NoMask} + + // Save r8..r11 to free some room (optional, depending on needs): + mov (16) m1 r8 {NoMask} + mov (16) m3 r10 {NoMask} + add (1) m0.2 r0.4 (SCR_OFFSET_GRF + 256) {NoMask} + send (8) m0 null null DPW|ML5|RL0 {NoMask} + + // Save r12..r15 to free some room (optional, depending on needs): + mov (16) m8 r12 {NoMask} + mov (16) m10 r14 {NoMask} + add (1) m7.2 r0.4 (SCR_OFFSET_GRF + 384) {NoMask} + send (8) m7 null null DPW|ML5|RL0 {NoMask} + + // Save selected ARF registers (optional, depending on use): + // flags, others ... + // Save f0.0: + mov (1) r1.0:uw f0.0 {NoMask} + + Next: // Exceptions pending? If not, exit. + + cmp.e (1) f0.0 cr0.4:uw 0:uw {NoMask} + (f0.0) mov (1) IP EXIT {NoMask} + + // Find highest priority exception: + lzd (1) r1.1:uw cr0.4:uw {NoMask} + + // Jump table to service routine: + jmpi (1) r1.1:uw{NoMask} + mov (1) IP CRService_0 {NoMask} + mov (1) IP CRService_1 {NoMask} + mov (1) IP CRService_2 {NoMask} + ... + mov (1) IP CRService_15{NoMask} + mov (1) IP Next + + Service_0: + // Clear exception from cr0.1. + // Perform service routine. + // Jump to exit (or if looping on exceptions, go to next loop). + ... + Service_15: + // Clear exception from cr0.1. + // Perform service routine. + // Jump to exit (or if looping on exceptions, go to next loop). + + Exit: + // Restore f0.0. + // Restore other ARF registers (as required). + // Restore r12..r15. + // Restore r8..r11. + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 90 + // Restore r4..r7. + // Restore r0..r3. + // Restore m8..m15. + // Restore m0..m7. + // Clear Master Exception State bit in cr0.0: + and (1) cr0.0 cr0.0 MASTER_EXCP_MASK + nop (16) + + +Below is a code sequence to programmatically clear the GRF scoreboard in case of a timeout waiting on +a register that may never return. +At this point, all we know is we have a hung thread. We’d like to copy the GRF to scratch memory to +make it visible , but there may be a register that is hung with an outstanding dependency. To get around +any hung dependency, walk the GRF using NoDDChk, using an execution mask of f0 == 0 so we don’t +touch the register contents. + + Clear_Dep: + mov f0 0x00 + (f0) mov r0 0x00 {NoDDChk} + (f0) mov r1 0x00 {NoDDChk} + (f0) mov r2 0x00 {NoDDChk} + ... + (f0) mov r127 0x00 {NoDDChk} + // GRF scoreboard now cleared. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 91 + 5. Instruction Set Summary +5.1 Instruction Set Characteristics + +5.1.1 5nstruction Operands and Register Regions +Most instructions may have up to three operands, two sources and one destination. Each operand is able +to address a register region. Source operands support negate and absolute modifier and channel swizzle, +and the destination operand supports channel mask. +Dual destination instructions are also supported (four-operand instructions in a general sense): One case +is for the implied destination – flag register, where the conditional modifiers and the predicate modifiers +may apply. Another case is the message header creation (implied move or implied assembling of the +header) in the send instruction. +Each execution channel contains an accumulator that is wider than the input data to support back-to-back +accumulation operations with increased precision. The added precision (see accumulator register +description in Execution Environment chapter) determines the maximum number of accumulations before +possible overflow. The accumulator can be pre-loaded through the use of mov. It can also be pre-loaded +by arithmetic instructions such as add or mul, since the result of these instructions can go to the +accumulator. The accumulator registers are per thread and therefore safe for thread switching. +Register access can be direct or register-indirect. Register-indirect register access uses address registers +plus an immediate offset term to compute the register addresses, and only applies to the first source +operand (src0) and/or the destination operand. +There is one address register. There are 8 address sub-registers.Each sub-register contains a 16-bit +unsigned value. The leading two sub-registers form a special doubleword that can be used as the +descriptor for the send instruction. +Source operand can also be immediate value (also referred to as inline constants). For instructions with +two source operands, only the second operand src1 is allowed to be immediate. For instructions with only +one source operand, the source operand src0 is used and it can be an immediate. +An immediate source operand can be a scalar value of specified type up to 32-bit wide, which is +replicated to create a vector with length of Execution Size. An immediate operand can also be a special +32-bit vector with 8 elements each of 4-bit signed integer value, or a 32-bit vector with 4 elements each of +8-bit restricted float value. + + +5.1.2 Instruction Execution +It is implied that all instructions operate across all channels of data unless otherwise specified either via +destination mask, predication, execution mask (caused by SIMD branch and loop instructions), or +execution size. +Instruction execution size can be specified per instruction, from scalar (ExecSize = 1) up to the maximal +execution size supported for the data type, with the restriction that execution size can only be in power of +2. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 92 + 5.2 Instruction Machine Formats +This section shows the machine formats of the instruction set. The instructions in the architecture have a +fixed length of 128 bits in the native format. A compact format, discussed separately in this volume, can +represent some instructions using 64 bits. Out of the 128 bits in the native format, there are 120 bits in +use, and the remaining bits are reserved for future extensions. One instruction consists of instruction +fields that control various stages of execution. These fields are roughly grouped into the 4 DWords as +follows: + +  Instruction Operation Doubleword (DW0) contains the Opcode and other general instruction control + fields. +  Instruction Destination Doubleword (DW1) specifies the destination operand (dst) and the register + file and type of source operands. +  Instruction Source 0 Doubleword (DW2) contains the first source operand (src0). +  Instruction Source 1 Doubleword (DW3) contains the second source operand (src1) and is used to + hold any 32-bit immediate source (imm32 as src0 or src1). + +Most instructions have 1 or 2 source operands and use a common instruction format. Within that format, +there are variations based on AddrMode and AccessMode. There is a separate instruction format for a +small number of instructions with 3 source operands. Send, math, and branching instructions have format +variations described separately. +The 3-source instructions have the following restrictions: +  Only GRF registers can be sources, and only GRF registers can be the destination. +  Subregister numbers have DWord granularity. +  AccessMode is Align16, uses Align16-style swizzling, with extra replication control. There is no other + regioning support. + +The next two subsections describe the instruction formats for various processor generations using tables. +The following diagrams provide another view of the same information. The first two diagrams are for +native instructions with one or two source operands. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 93 + Instruction Format – 1-src and 2-src + + + + +The next two diagrams are for instructions with three source operands. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 94 + Instruction Format – 3-src + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 95 + 5.2.1 EU Instruction Formats +This section covers the layout of instruction fields, not changes in allowed field encodings from generation +to generation. For example, adds new data types and instructions which add new allowed values for +particular fields, but those changes do not change field positions or layout. +DWord 0, bits 31:0 of the 128-bit instruction, has the same format regardless of the number of source +operands. +The following three tables cover the most common instruction format, for instructions with 1 or 2 source +operands; then the format for the few instructions with 3 source operands; and finally format variations +used by a few exceptional instructions. + +Execution Unit Instruction Format for 1 or 2 Source Operands + AddrMode and AccessMode Variations + AddrMode = Direct AddrMode = Indirect + Bits Description Align16 Align1 Align16 Align1 + Any Imm32 32-bit immediate operand uses bits 127:96, replacing the following fields. +127:121 Reserved +120:117 Src1.VertStride + 116 Varies based on AccessMode Reserved Src1.Width Reserved Src1.Width +115:114 Src1.ChanSel[7:4] Src1.ChanSel[7:4] +113:112 Src1.HorzStride + 111 Src1.AddrMode +110:109 Src1.SrcMod +108:106 Varies based on AddrMode and Src1.RegNum Src1.AddrSubRegNum +105:101 AccessMode Src1.AddrImm[9:4] Src1.AddrImm[9:0] + 100 + + 99:96 Src1.ChanSel[3:0] Src1.ChanSel[3:0] + + 95:91 Reserved + 90 + FlagRegNum + 89 FlagSubRegNum + 88:85 Src0.VertStride + 84 Varies based on AccessMode Reserved Src0.Width Reserved Src0.Width + 83:82 Src0.ChanSel[7:4] Src0.ChanSel[7:4] + 81:80 Src0.HorzStride + 79 Src0.AddrMode + 78:77 Src0.SrcMod + 76:74 Varies based on AddrMode and Src0.RegNum Src0.AddrSubRegNum + 73:69 AccessMode Src0.AddrImm[9:4] Src0.AddrImm[9:0] + 68 + + 67:64 Src0.ChanSel[3:0] Src0.ChanSel[3:0] + + 63 Dst.AddrMode + 62:61 Varies based on AccessMode Reserved Dst.HorzStride Reserved Dst.HorzStride + 60:58 Varies based on AddrMode and Dst.RegNum Dst.AddrSubRegNum + 57:53 AccessMode Dst.AddrImm[9:4] Dst.AddrImm[9:0] + 52 + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 96 + AddrMode and AccessMode Variations + AddrMode = Direct AddrMode = Indirect + Bits Description Align16 Align1 Align16 Align1 + 51:48 Dst.ChanEn[3:0] Dst.ChanEn[3:0] + + 47 + NibCtrl + 46:44 Src1.SrcType + 43:42 Src1.RegFile + 41:39 Src0.SrcType + 38:37 Src0.RegFile + 36:34 Dst.DstType + 33:32 Dst.RegFile + 31 Saturate + 29 CmptCtrl + 28 AccWrCtrl + 27:24 CondModifier + 23:21 ExecSize + 20 PredInv + 19:16 PredCtrl + 15:14 ThreadCtrl + 13:12 QtrCtrl + 11:10 DepCtrl + 9 MaskCtrl + 8 AccessMode + 7 Reserved (for future Opcode + expansion) + 6:0 Opcode + +The 3-source operand instructions are: +bfe - Bit Field Extract +bfi2 - Bit Field Insert 2 +lrp - Linear Interpolation +mad - Multiply Add + +In the 3-source instruction format, the upper QWord contains three groups of 21 bits for the three source +operands, where each group contains four fields in 20 bits and otherwise adjacent groups are separated +by single reserved bits. + +Execution Unit Instruction Format for 3 Source Operands + Bits Description +127:126 Reserved +125:118 Src2.RegNum +117:115 Src2.SubRegNum +114:107 Src2.ChanSel + 106 Src2.RepCtrl + 105 Reserved + 104:97 Src1.RegNum + 96 Src1.SubRegNum[2] + 95:94 Src1.SubRegNum[1:0] + 93:86 Src1.ChanSel + 85 Src1.RepCtrl + 84 Reserved + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 97 + Bits Description + 83:76 Src0.RegNum + 75:73 Src0.SubRegNum + 72:65 Src0.ChanSel + 64 Src0.RepCtrl + 63:56 Dst.RegNum + 55:53 Dst.SubRegNum + 52:49 Dst.ChanEnable + 48 Reserved + 47 + NibCtrl + 46 Reserved + 45:44 + DstType + + 43:42 + SrcType + 41:40 Src2.Modifier + 39:38 Src1.Modifier + 37:36 Src0.Modifier + 35 Reserved + 34 + FlagRegNum + 33 FlagSubRegNum + 32 + Reserved + 31 Saturate + 29 CmptCtrl + 28 AccWrCtrl + 27:24 CondModifier + 23:21 ExecSize + 20 PredInv + 19:16 PredCtrl + 15:14 ThreadCtrl + 13:12 QtrCtrl + 11:10 DepCtrl + 9 MaskCtrl + 8 AccessMode + 7 Reserved (for future Opcode expansion) + 6:0 Opcode + +Specific instructions have different instruction formats as described below. These instructions include +send / sendc, math, and branch instructions. + +Execution Unit Instruction Format for Specific Instructions + Regular 1 or 2 Empty white areas mean Same, use the regular description + Source Operands Branch + Bits Description send / sendc math Instructions + 127 Reserved EOT UIP[15:0] +126:125 (2-offset +124:121 Imm[28:0] / branches) +120:117 Reg32 Src1.VertStride +116:112 Varies based on + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 98 + Regular 1 or 2 Empty white areas mean Same, use the regular description + Source Operands Branch + Bits Description send / sendc math Instructions + AccessMode + 111 Src1.AddrMode JIP[15:0] +110:109 Src1.SrcMod + 108:96 Varies based on AddrMode and + AccessMode + 95:91 Reserved + 90 + FlagRegNum + 89 FlagSubRegNum + 88:85 Src0.VertStride + 84:80 Varies based on AccessMode + 79 Src0.AddrMode + 78:77 Src0.SrcMod + 76:64 Varies based on AddrMode and + AccessMode + 63 Dst.AddrMode + Any branch instruction: + 62:61 Varies based on AccessMode Same as regular + 60:48 Varies based on AddrMode and + AccessMode + 47 + NibCtrl + 46:44 Src1.SrcType + 43:42 Src1.RegFile + 41:39 Src0.SrcType + 38:37 Src0.RegFile + 36:34 Dst.DstType + 33:32 Dst.RegFile + 31 Saturate + 29 CmptCtrl + 28 AccWrCtrl + 27:24 CondModifier SFID[3:0] FC[3:0] + Any branch instruction: + MBZ + 23:21 ExecSize + 20 PredInv + 19:16 PredCtrl + 15:14 ThreadCtrl + + 13:12 QtrCtrl + 11:10 DepCtrl + 9 MaskCtrl + 8 AccessMode + 7 Reserved (for future Opcode + expansion) + 6:0 Opcode + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 99 + 5.2.2 Common Instruction Fields +As shown in the table below, the meanings (encoding) of certain bit fields in the 128-bit native instruction +format varies depending on the values of other bit fields. +Common Instruction Fields provides the definition of common fields in the native instruction format. The +‘Width’ column specifies the width of the field in bits. These common fields are referenced in describing +the fields of different doublewords of the instruction. The definition for fields that have unique +representations can be found in the sections for the corresponding instruction DWords. + +Definitions of Common Instruction Fields + Field Description Width + 4 +CondModifier Conditional Modifier. This field sets the flag register based on the internal conditional + signals output from the execution pipe such as sign, zero, overflow and NaNs, etc. If this + field is set to 0000, no flag registers are updated. Flag registers are not updated for + instructions with embedded compares. + This field applies to all instructions except send, sendc, and math. + 0000 = Do not modify the flag register (normal) + 0001 = Zero or Equal (.z or .e) + 0010 = Not Zero or Not Equal (.nz or .ne) + 0011 = Greater-than (.g) + 0100 = Greater-than-or-equal (.ge) + 0101 = Less-than (.l) + 0110 = Less-than-or-equal (.le) + 0111 = Reserved + 1000 = Overflow (signed overflow) (.o) + 1001 = Unordered with Computed NaN (.u) + 1010 -1111 = Reserved + 1 +AddrMode Addressing Mode. This field determines the addressing method of the operand. Normally + the destination operand and each source operand each have a distinct addressing mode + field. + When it is cleared, the register address of the operand is directly provided by bits in the + instruction word. It is called a direct register addressing mode. When it is set, the register + address of the operand is computed based on the address register value and an address + immediate field in the instruction word. This is referred to as a register-indirect register + addressing mode. + This field applies to the destination operand and the first source operand, src0. Support for + src1 is device dependent. See Table XX (Indirect source addressing support available in + device hardware) in ISA Execution Environment for details. + 0 = “Direct”. Direct register addressing + 1 = “Register-Indirect” (or in short “Indirect”). Register-indirect register addressing + + 8 +RegNum Register Number. This field provides the register number for the operand. For GRF + register operand, it provides the portion of register address aligning to 256-bit. For an ARF + register operand, this field is encoded such that MSBs identify the architecture register type + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 100 + Field Description Width + and LSBs provide its register number. + This field together with the corresponding SubRegNum field provides the byte aligned + address for the origin of the register region. Specifically, this field provides bits [12:5] of the + byte address, while SubRegNum field provides bits [4:0]. + This field applies to the destination operand and the source operands. It is ignored (or not + present in the instruction word) for an immediate source operand. + This field is present if the operand is in direct addressing mode; it is not present if the + operand is register-indirect addressed. + Format = U8, if RegFile = GRF. + 0x00 to 0x7F = Register number in the range of [0, 127] + 0x80 to 0xFF = Reserved + 0x00 to 0x0F = Register number in the range of [0, 15] + 0x10 to 0xFF = Reserved + Format = 8-bit encoding, if RegFile = ARF. + This field is used to encode the architecture register as well as providing the register + number. See GEN Execution Environment chapter for details. + 5 +SubRegNum Sub-Register Number. This field provides the sub-register number for the operand. For a + GRF register operand, it provides the byte address within a 256-bit register. For an ARF + register operand, this field also provides the sub-register number according to the encoding + defined for the given architecture register. + This field together with the corresponding RegNum field provides the byte aligned address + for the origin of the register region. Specifically, this field provides bits [4:0] of the byte + address, while the RegNum field provides bits [12:5]. + This field applies to the destination operand and the source operands. It is ignored (or not + present in the instruction word) for an immediate source operand. + This field is present if the operand is in direct addressing mode; it is not present if the + operand is register-indirect addressed. + Note: The recommended instruction syntax uses subregister numbers within the GRF in + units of actual data element size, corresponding to the data type used. For example for the + F (Float) type, the assembler syntax uses subregister numbers 0 to 7, corresponding to + subregister byte addresses of 0 to 28 in steps of 4, the element size. + Format = U5, if RegFile = GRF + 0x00 to 0x1F = Sub-Register number in the range of [0, 31] + Format = 5-bit encoding, if RegFile = ARF. + This field is used to encode the architecture register as well as providing the register + number. See GEN Execution Environment chapter for details. + 3 +AddrSubRegNum Address Sub-Register Number. This field provides the subregister number for the + address register. The address register contains 8 sub-registers. The size of each + subregister is one word. The address register contains the register address of the operand, + when the operand is in register-indirect addressing mode. + This field applies to the destination operand and the source operands. It is ignored (or not + present in the instruction word) for an immediate source operand. + This field is present if the operand is in register-indirect addressing mode; it is not present if + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 101 + Field Description Width + the operand is directly addressed. + An address subregister used for indirect addressing is often called an index register. + Format = U3 + 0x0 to 0x7 = Address Sub-Register number in the range [0, 7] + 10 +AddrImm Address Immediate. This field provides the immediate value in units of bytes added to the + address register to compute the register address (byte-aligned region origin) for the + operand. It is a signed integer. + This field is present if the operand is in register-indirect addressing mode; it is not present if + the operand is directly addressed. + Note: that the address immediate field may not be able to cover the whole GRF register + range for a thread, as the maximum GRF register space for a thread is 4KB. + Format = S9 + Valid range: [-512, 511] + + 2 +SrcMod Source Modifier. This field specifies the numeric modification of a source operand. The + value of each data element of a source operand can optionally have its absolute value + taken and/or its sign inverted prior to delivery to the execution pipe. The absolute value is + prior to negate such that a guaranteed negative value can be produced. + This field only applies to source operand. It does not apply to destination. + This field is not present for an immediate source operand. + 00 = No modification (normal) + 01 = “(abs)”. Absolute + 10 = “–”. Negate + 11 = “–(abs)”. Negate of the absolute (forced negative value) + + 4 +VertStride Vertical Stride. The field provides the vertical stride of the register region in unit of data + elements for an operand. + Encoding of this field provides values of 0 or powers of 2, ranging from 1 to 32 elements. + Larger values are not supported due to the restriction that a source operand must reside + within two adjacent 256-bit registers (64 bytes total). + Special encoding 1111b (0xF) is only valid when the operand is in register-indirect + addressing mode (AddrMode = 1). If this field is set to 0xF, one or more sub-registers of + the address registers may be used to compute the addresses. Each address sub-register + provides the origin for a row of data element. The number of address sub-registers used is + determined by the division of ExecSize of the instruction by the Width fields of the operand. + This field only applies to source operand. It does not apply to destination. + This field is not present for an immediate source operand. + Note 1: Vertical Stride larger than 32 is not allowed due to the restriction that a source + operand must reside within two adjacent 256-bit registers (64 bytes total). + Note 2: In Align16 access mode, as encoding 0xF is reserved, only single-index indirect + addressing is supported. + Note 3: If indirect address is supported for src1, encoding 0xF is reserved for src1 – only + single-index indirect addressing is supported. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 102 + Field Description Width + 0000 = 0 Elements + 0001 = 1 Element + 0010 = 2 Elements + 0011 = 4 Elements + 0100 = 8 Elements + 0101 = 16 Elements (applies to byte or word operand only) + 0110 = 32 Elements (applies to byte operand only) + 0111-1110 = Reserved + 1111 = VxH or Vx1 mode (only valid for register-indirect addressing in Align1 mode) + + 3 +Width Width. This field specifies the number of elements in the horizontal dimension of the region + for a source operand. This field cannot exceed the ExecSize field of the instruction. + This field only applies to source operand. It does not apply to destination. + This field is not present for an immediate source operand. + 000 = 1 Elements + 001 = 2 Elements + 010 = 4 Elements + 011 = 8 Elements + 100 = 16 Elements + 101-111 = Reserved + 2 +HorzStride Horizontal Stride. This field provides the distance in unit of data elements between two + adjacent data elements within a row (horizontal) in the register region for the operand. + This field applies to both destination and source operands. + This field is not present for an immediate source operand. + 00 = 0 Elements + 01 = 1 Element + 10 = 2 Elements + 11 = 4 Elements + 32 +Imm32 32-bit Immediate. The 32-bit immediate data field for the operand. It may contain any legal + bit pattern for its associated type. Only one 32-bit immediate value may be present in an + instruction, therefore binary operations only support src1 as an immediate value. + The low order bits are directly used when fewer than 32-bits are needed to describe the + desired type; the 32-bits are not coerced into the designated type. + For UW and W data types, programmer is required to replicate the lower word to the upper + word of this field. + This field only applies to the last source operand. + Signed and unsigned byte integer data types are not supported for an immediate operand. + See the Numeric Data Types section for information about data types and their ranges. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 103 + Field Description Width + 4 +ChanEn Channel Enable. Four channel enables are defined for controlling which channels will be + written into the destination region. These channel mask bits are applied in a modulo-four + manner to all ExecSize channels. There is 1-bit Channel Enable for each channel within + the group of 4. If the bit is cleared, the write for the corresponding channel is disabled. If + the bit is set, the write is enabled. Mnemonic for the bit being set for the group of 4 is “x”, + “y”, “z”, and “w”, respectively, where “x” corresponds to Channel 0 in the group and “w” + corresponds to channel 3 in the group. + This field only applies to destination operand. + This field is only present in Align16 mode. + 0 = Write Disabled + 1 = Write Enabled (normal) + 8 +ChanSel Channel Select. This field controls the channel swizzle for a source operand. The normally + sequential channel assignment can be altered by explicitly identifying neighboring data + elements for each channel. Out of the 8-bit field, 2 bits are assigned for each channel + within the group of 4. ChanSel[1:0], [3.2], [5.4] and [7,6] are for channel 0 (“x”), 1 (“y”), 2 + (“z”), and 3 (“w”) in the group, respectively. + For example with an execution size of 8, r0.0<4>.zywz:f would assign the channels as + follows: Chan0 = Data2, Chan1 = Data1, Chan2 = Data3, Chan3 = Data2; Chan4 = Data6, + Chan5 = Data5, Chan6 = Data7, Chan7 = Data6. + This field only applies to source operand. + This field is only present in Align16 mode. It is not present for an immediate source + operand. + The 2-bit Channel Selection field for each channel within the group of 4 is defined as the + following. + 00 = “x”. Channel 0 is selected for the corresponding execution channel + 01 = “y”. Channel 1 is selected for the corresponding execution channel + 10 = “z”. Channel 2 is selected for the corresponding execution channel + 11 = “w”. Channel 3 is selected for the corresponding execution channel + + 1 +RepCtrl Replicate Control. This field controls the replication of the starting channel to all channels + in the execution size. + This field applies to all three source operands. + 0 = No replication + 1 = Replicate across all channels + [Errata Astep] Replicate Control is not supported. As a WorkAround, Break 3 source + instructions to simd4 and use channel select when replicate control is required. + + 31 +MsgDscpt31 Message Description. This field, containing 31-bit immediate values, provides the + description of the message to be sent. + This field only applies to the send instruction. It is not present for other instructions. + The meaning of the field depends on the type of message as well as the message shared + function target. + Format: U31 + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 104 + Field Description Width + 1 +EOT End of Thread. This field controls the termination of the thread. For a send instruction, if + this field is set, EU will terminate the thread and also set the EOT bit in the message + sideband. + This field only applies to the send instruction. It is not present for other instructions. + 0 = The thread is not terminated + 1 = EOT + + + +5.2.3 Instruction Operation Doubleword (DW0) +Most fields in Instruction Operation Doubleword (DW0) apply to all instructions. Bit field [27:24] is one +exception. It is CondModifier for most instructions but is SFID[3:0] field for the send instruction. +The descriptions in the table below are shared between the 1-src/2-src instructions and 3-src instructions. + +Definitions of Fields in Operation Doubleword (DW0) +Bits Description + 31 + Saturate. This field controls the destination saturation. + When it is set, output data to the destination register are saturated. The saturation operation depends on the + destination data type. Saturation is the operation that converts any data that is outside the saturation target + range for the data type to the closest represented value with the target range. If destination type is float, + saturation target range is [0, 1]. For example, any positive number greater than 1 (including +INF) is saturated + to 1 and any negative number (including –INF) is saturated to 0. A NaN is saturated to 0, For integer data + types, the maximum range for the given numeric data type is the saturation target range. + When it is not set, output data to the destination register are not saturated. For example, a wrapped result + (modular) is output to the destination for an overflowed integer data. + More details can be found in the Data Types chapter. + 0 = No destination modification (normal) + 1 = “sat”. Saturate the output + Destination Saturation Target Range + Type (inclusive) + Float (F) [0.0, 1.0] + Byte (UB) [0, 255] + Signed Byte (B) [-128, 127] + Word (UW) [0, 65535] + Signed Word (W) [-32768, 32767] + Double Word + [0, 232-1] + (UD) + Signed Double + [-231, 231-1] + (D) + Reserved: MBZ + 29 + 28 + AccWrCtrl. This field allows per instruction accumulator write control. + 0 = don’t write result into accumulator + 1 = “AccWrCtrl”. write result into accumulator, and destination + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 105 + Bits Description +27:24 + CondModifier or CurrDst.RegNum[3:0] + Definition of this bit field depends on whether the instruction is a send/math or not. + + Opcode != ‘send’ Opcode = ‘send’ + + CondModifier: CurrDst.RegNum[3:0] + This field sets the This field sets the MRF register + flag register based number for the current + on the internal destination operand in the send + conditional signals instruction. No flag registers are + output from the updated for the send instruction. + execution pipe. The 4-bit field provides full + access of the 16 MRF registers. + (See Instruction Reference + chapter for CurrDst.) + +23:21 + ExecSize – Execution Size. This field determines the number of channels operating in parallel for this + instruction. The size cannot exceed the maximum number of channels allowed for the given data type. + 000b = 1 channel (scalar operation) + 001b = 2 channels + 010b = 4 channels + 011b = 8 channels + 100b = 16 channels + 101 = 32 channels + 110-111 = Reserved + + 20 + PredInv – Predicate Inverse. This field, together with PredCtrl, enables and controls the generation of the + predication mask for the instruction. When it is set, the predication uses the inverse of the predication bits + generated according to setting of Predicate Control. In other words, effect of PredInv happens after PredCtrl. + This field is ignored by hardware if Predicate Control is set to 0000 – there is no predication. + 0 = “+”. Positive polarity of predication. + 1 = “–”. Negative polarity of predication. + +19:16 + PredCtrl – Predicate Control. This field, together with PredInv, enables and controls the generation of the + predication mask for the instruction. It allows per-channel conditional execution of the instruction based on the + content of the selected flag register. Encoding depends on the access mode. + In Align16 access mode, there are eight encodings (including no predication). All encodings are based on + group-of-4 predicate bits, including channel sequential, replication swizzles and horizontal any|all operations. + The same configuration is repeated for each group-of-4 execution channels. + See the Predication section for more informatio about predication. + In Align1 access mode, there are twelve encodings (including no predication). The encodings applies to all + execution channels with explicit channel grouping from single channel up to group of 16 channels. + Predicate Control in Align16 access mode + 0000 = No predication (normal) + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 106 + Bits Description + 0001 = Predication with sequential flag channel mapping + 0010 = Predication with replication swizzle ‘.x’ + 0011 = Predication with replication swizzle ‘.y’ + 0100 = Predication with replication swizzle ‘.z’ + 0101 = Predication with replication swizzle ‘.w’ + 0110 = Predication with ‘.any4h’ + 0111 = Predication with ‘.all4h’ + 1000 -1111 = Reserved + Predicate Control in Align1 access mode + 0000 = No predication (normal) + 0001 = Predication with sequential flag channel mapping + 0010 = Predication with .anyv (any from f0.0-f0.1 on the same channel) + 0011 = Predication with .allv (all of f0.0-f0.1 on the same channel) + 0100 = Predication with .any2h (any in group of 2 channels) + 0101 = Predication with .all2h (all in group of 2 channels) + 0110 = Predication with .any4h (any in group of 4 channels) + 0111 = Predication with .all4h (all in group of 4 channels) + 1000 = Predication with .any8h (any in group of 8 channels) + 1001 = Predication with .all8h (all in group of 8 channels) + 1010 = Predication with .any16h (any in group of 16 channels) + 1011 = Predication with .all16h (all in group of 16 channels) + 1100 = Predication with .any32h (any in group of 32 channels) + 1101 = Predication with .all32h (all in group of 32 channels) + 1110 -1111 = Reserved + +15:14 + ThreadCtrl – Thread Control. This field provides explicit control for thread switching. + If this field is set to 00b, it is up to the GEN execution units to manage thread switching. This is the normal + (and unnamed) mode. In this mode, for example, if the current instruction cannot proceed due to operand + dependencies, the EU switches to the next available thread to fill the compute pipe. In another example, if the + current instruction is ready to go, however, there is another thread with higher priority that also has an + instruction ready, the EU switches to that thread. + If this field is set to Switch, a forced thread switch occurs after the current instruction is executed and before + the next instruction. In addition, a long delay (longer than the execution pipe latency) is introduced for the + current thread. Particularly, the instruction queue of the current thread is flushed after the current instruction is + dispatched for execution. Switch is designed primarily as a safety feature in case there are race conditions for + certain instructions. + If this field is set to Atomic, the next instruction gets highest priority in thread arbitration for the execution + pipeline. + 00b = Normal thread control + 10b = “Switch” + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 107 + Bits Description + 01b = “Atomic” + 11b = Reserved +13:12 + QtrCtrl – Quarter Control. This field provides explicit control for ARF selection. + This filed combines with ExecSize determines which channels are used for the ARF registers. + Along with NibCtrl in DW1, 1/8 DMask/VMask and ARF can be selected. + + QtrCtrl NibCtrl ExecSize Description BNF + + 00 x 8 + use first quarter for 1Q + DMask/VMask + use first half for + everything else + 01 x 8 + use second 2Q + quarter for + DMask/VMask + use second half + for everything else + 10 x 8 + use third quarter 3Q + for DMask/VMask + use first half for + everything else + 11 x 8 + use forth quarter 4Q + for DMask/VMask + use second half + for everything else + 0x x 16 + use first half for 1H + DMask/VMask + use all channels + for everything else + 1x x 16 + use second half 2H + for DMask/VMask + use all channels + for everything else + + 00 0 4 use first 1/8 for + 1N + DMask/VMask and + ARF + 00 1 4 use second 1/8 for + 2N + DMask/VMask and + ARF + 01 0 4 use third 1/8 for + 3N + DMask/VMask and + ARF + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 108 + Bits Description + 01 1 4 use fourth 1/8 for + 4N + DMask/VMask and + ARF + 10 0 4 use fifth 1/8 for + 5N + DMask/VMask and + ARF + 10 1 4 use sixth 1/8 for + 6N + DMask/VMask and + ARF + 11 0 4 use seventh 1/8 for + 7N + DMask/VMask and + ARF + 11 1 4 use eighth 1/8 for + 8N + DMask/VMask and + ARF + 2H is only allowed for SIMD16 instruction in Single Program Flow mode (SPF=1). + NibCtrl is only allowed for SIMD4 instructions with (DF) double precision source and/or destination. + + +11:10 + DepCtrl – Destination Dependency Control. This field selectively disables destination dependency check + and clear for this instruction. + When it is set to 00, normal destination dependency control is performed for the instruction – hardware checks + for destination hazards to ensure data integrity. Specifically, destination register dependency check is + conducted before the instruction is made ready for execution. After the instruction is executed, the destination + register scoreboard will be cleared when the destination operands retire. + When bit 10 is set (NoDDClr), the destination register scoreboard will NOT be cleared when the destination + operands retire. When bit 11 is set (NoDDChk), hardware does not check for destination register dependency + before the instruction is made ready for execution. NoDDClr and NoDDChk are not mutual exclusive. + When this field is not all-zero, hardware does not protect against destination hazards for the instruction. This is + typically used to assemble data in a fine grained fashion (e.g. matrix-vector compute with dot-product + instructions), where the data integrity is guaranteed by software based on the intended usage of instruction + sequences. + 00 = Destination dependency checked and cleared (normal) + 01 = “NoDDClr”. Destination dependency checked but not cleared + 10 = “NoDDChk”. Destination dependency not checked but cleared + 11 = “NoDDClr, NoDDChk”. Destination dependency not checked and not cleared + + 9 + MaskCtrl – Mask Control (formerly Write Enable Control). This field determines if the per channel write + enables are used to generate the final write enable. This field should be normally “0”. + 0 = use normal write enables (normal) + 1 = write all channels, except channels killed with predication control. ChanEn is ignored in this case. + MaskCtrl = NoMask skips the check for PcIP[n] == ExIP before enabling a channel, as described in the + Evaluate Write Enable section. + + 8 + AccessMode – Access Mode. This field determines the operand access for the instruction. It applies to all + source and destination operands. + When it is cleared (Align1), the instruction uses byte-aligned addressing for source and destination operands. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 109 + Bits Description + Source swizzle control and destination mask control are not supported. + When it is set (Align16), the instruction uses 16-byte-aligned addressing for all source and destination + operands. Source swizzle control and destination mask control are supported in this mode. + 0 = “Align1” + 1 = “Align16” + + Reserved: MBZ (for future opcode extension) + 7 + + 6:0 + Opcode – Instruction Operation Code. This field contains the instruction operation code. Each opcode is + given a unique mnemonic. For example, opcode 0x01 is for a move operation. Mnemonic for this opcode is + mov. + + + +5.2.4 Instruction Destination Doubleword (DW1) + +5.2.4.1 DW1 1-src and 2-src Instructions +Destination Doubleword (DW1) contains the register file and numeric type of all operands, as well as the +register region parameters of the destination operand. See the Region Parameters section and the +sections following it for more information about those parameters. + +Instruction Destination Doubleword + Bits Description +31:16 + Destination Register Region. This word contains the parameters describing the register region of the + destination operand. Subfield definition depends on the AccessMode. + See the Region Parameters section and the sections following it for more information about these parameters. + Programming Notes: + Allthough Dst.HorzStride is a don’t care for Align16, HW needs this to be programmed as “01”. + + Reserved: MBZ + 15 + +14:12 + Src1.SrcType – Source 1 Data Type. This field specifies the numeric data type of the source operand src1. + The bits of a source operand are interpreted as the identified numeric data type, rather than coerced into a + type implied by the operator. Depending on RegFile field of the source operand, there are two different + encoding for this field. If a source is a register operand, this field follows the Source Register Type Encoding. If + a source is an immediate operand, this field follows the Source Immediate Type Encoding. + Source Register Type Encoding is identical to that for Destination Type. + Source Immediate Type Encoding differs in two areas. First, it does not support byte and unsigned numeric + data types. Second, it has three packed vector types, the V, UV, and VF types. + Implementation Note 1: Both source operands, src0 and src1, support immediate types, but only one + immediate is allowed for a given instruction and it must be the last operand. + Implementation Note 2: Halfbyte integer vector (v) type can only be used in instructions in packed-word + execution mode. Therefore, in a two-source instruction where src1 is of type :v, src0 must be of type :b, :ub, + :w, or :uw. + + + Source Register Type Encoding + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 110 + Bits Description + 000 = “UD”. Unsigned Doubleword integer + 001 = “D”. Signed Doubleword integer + 010 = “UW”. Unsigned Word integer + 011 = “W”. Signed Word integer + 100 = “UB”. Unsigned Byte integer + 101 = “B”. Signed Byte integer + 110 = Reserved + 110 = “DF”. Double precision Float (64-bit) + 111 = “F”. Single precision Float (32-bit) + Source Immediate Type Encoding: + 000 = “UD” + 001 = “D” + 010 = “UW” + 011 = “W” + 100 = “UV”. 32-bit halfbyte Unsigned Integer Vector + 101 = “VF”. 32-bit restricted Vector Float + 110 = “V”. 32-bit halfbyte integer Vector + 111 = “F” + +11:10 + Src1.RegFile – Source 1 Register File. This field identifies the register file of source operand src1. + 00 = “ARF”. Architecture Register File (a#, acc#, f#, n#, null, ip, etc.) + 01 =“GRF”. General Register File (r#) + 10 = “MRF”. Message Register File (m#) + 10 = Reserved. Reserved. Do not use this encoding. + 11 = “IMM”. Immediate + + 9:7 + Src0.SrcType – Source 0 Data Type. This field is the SrcType for src0 operand. It has the same definitions + as Src1.SrcType. + + 6:5 + Src0.RegFile – Source 0 Register File. This field is the RegFile for src0 operand. It has the same definitions + as Src1.RegFile. + + 4:2 + Dst.DstType – Destination Data Type. This field specifies the numeric data type of the destination operand + dst. The bits of the destination operand are interpreted as the identified numeric data type, rather than coerced + into a type implied by the operator. For a send instruction, this field applies to the CurrDst – the current + destination operand. + Encoding: + 000 = “UD”. Unsigned Doubleword integer + 001 = “D”. Signed Doubleword integer + 010 = “UW”. Unsigned Word integer + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 111 + Bits Description + 011 = “W”. Signed Word integer + 100 = “UB”. Unsigned Byte integer + 101 = “B”. Signed Byte integer + 110 = Reserved + 110 = ["DF"] Double Precision Float (64-bit) + 111 = “F”. Single precision Float (32-bit) + + 1:0 + Dst.RegFile – Destination Register File. This field identifies the register file of the destination operand dst. + Note that it is obvious that immediate cannot be a destination operand. + For a send instruction, this field applies to the PostDst – the post destination operand. + Encoding: + 00 = “ARF”. Architecture Register File (a#, acc#, f#, n#, null, ip, etc.) + 01 =“GRF”. General Register File (r#) + 10 = “MRF”. Message Register File (m#) + 10 = Reserved. Reserved. Do not use this encoding. + 11 = reserved + +The following tables describe the Destination Register Region based on the access mode and addressing +mode. + +Destination Register Region in Direct + Align16 mode + Bits Description + 15 + Dst.AddrMode – Destination Address Mode. This field is the AddrMode for the destination operand. + For a send instruction, this field applies to PostDst – the post destination operand. Addressing mode for + CurrDst (current destination operand) is fixed as Direct. (See Instruction Reference chapter for CurrDst and + PostDst.) + + Reserved: MBZ +14:13 +12:5 + Dst.RegNum – Destination Register Number. This field is the RegNum field for the destination operand. + For a send instruction, this field applies to PostDst. + + 4 + Dst.SubRegNum[4]. This is the 16-byte aligned sub-register address. + For a send instruction, this field applies to CurrDst. + + 3:0 + Dst.ChanEn – Destination Channel Enable. The channel enable field for the destination operand. + For a send instruction, this field applies to the CurrDst. + + +Destination Register Region in Direct+Align1 mode +Bits Description + 15 + Dst.AddrMode – Destination Address Mode. This field is the AddrMode for the destination operand. + For a send instruction, it applies to PostDst. Addressing mode for CurrDst is fixed as Direct. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 112 + Bits Description +14:13 + Dst.HorzStride – Destination Horizontal Stride. This field is the HorzStride for the destination operand. + For a send instruction, this field applies to CurrDst. PostDst only uses the register number. + +12:5 + Dst.RegNum – Destination Register Number. This field is the RegNum field for the destination operand. + For a send instruction, this field applies to PostDst. + + 4:0 + Dst.SubRegNum – Destination Sub-Register Number. This field is the SubRegNum for the destination + operand.) + Note: The recommended instruction syntax uses GRF subregister numbers in units of element size, which the + assembler translates to the appropriate value for this field. + For a send instruction, this field applies to CurrDst. + + +Destination Register Region in Indirect+Align16 mode + Bits Description + 15 + Dst.AddrMode – Destination Address Mode. This field is the AddrMode for the destination operand. + For a send instruction, this field applies to PostDst. Addressing mode for CurrDst is fixed as Direct. + + Reserved: MBZ +14:13 +12:10 + Dst.AddrSubRegNum – Destination Address Sub-Register Number. This field is the AddrSubRegNum for + the destination operand. + For a send instruction, this field applies to PostDst. + + 9:4 + Dst.AddrImm[9:4] + This is the half-register aligned AddrImm field for the destination operand. + For a send instruction, this field applies to PostDst. + + 3:0 + Dst.ChanEn – Destination Channel Enable. The channel enable field for the destination operand. + For a send instruction, this field applies to the CurrDst. + + +Destination Register Region in Indirect+Align1 mode +Bits Description + 15 + Dst.AddrMode – Destination Address Mode. This field is the AddrMode for the destination operand. + For a send instruction, this field applies to PostDst. Addressing mode for CurrDst is fixed as Direct. + +14:13 + Dst.HorzStride – Destination Horizontal Stride + This field is the HorzStride for the destination operand. + For a send instruction, this field applies to CurrDst. PostDst only uses the register number. + +12:10 + Dst.AddrSubRegNum – Destination Address Sub-Register Number. This field is the AddrSubRegNum for + the destination operand. + For a send instruction, this field applies to PostDst. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 113 + Bits Description +9:0 + Dst.AddrImm – Destination Address Immediate. This field is the byte-aligned AddrImm for the destination + operand. + For a send instruction, this field applies to PostDst. + + + +5.2.4.2 DW1 3-src Instructions +This section describes the field in DW1 for the 3-src instruction format. + +Instruction DW1 + Bits Description +31:24 Destination Register Number. This field contains the destination register number. +23:21 + Destination Subregister Number. This field contains the destination subregister number. + Note: The recommended instruction syntax uses GRF subregister numbers in units of element size, which the + assembler translates to the appropriate value for this field. +20:17 + Destination Channel Enable. Four channel enables are defined for controlling which channels are written + into the destination region. These channel mask bits are applied in a modulo-four manner to all ExecSize + channels. There is 1-bit Channel Enable for each channel within the group of 4. If the bit is cleared, the write + for the corresponding channel is disabled. If the bit is set, the write is enabled. Mnemonics for the bit being set + for the group of 4 are “x”, “y”, “z”, and “w”, respectively, where “x” corresponds to Channel 0 in the group and + “w” corresponds to channel 3 in the group. + 0: Write Disabled + 1: Write Enabled (normal) +16:15 + Dst Type. This field contains the data type for the destination. + 00b = Single Precision Float + 01b = DWord + 10b = Unsigned DWord + 11b = Double Precision Float +14:13 + Src Type. This field contains the data type for all three sources. + 00b = Single Precision Float + 01b = DWord + 10b = Unsigned DWord + 11b = Double Precision Float + +12:10 Reserved: MBZ + 9:8 + Source2 Modifier. This field contains the modifier for source2. + Refer to Table 5-5 for the encoding. + 7:6 + Source1 Modifier. This field contains the modifier for source1. + Refer to Table 5-5 for the encoding. + 5:4 + Source0 Modifier. This field contains the modifier for source0. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 114 + Bits Description + Refer to Table 5-5 for the encoding. + 3 Reserved: MBZ + 2 + Flag Register Number. This field contains the flag register number for instructions with a non-zero + Conditional Modifier. + + 1 Flag Subregister Number. This field contains the flag subregister number for instructions with a non-zero + Conditional Modifier. + 0 + Reserved + + + +5.2.5 Instruction Source 0 Doubleword 2 (DW2) + +5.2.5.1 DW2 1-src and 2-src Instructions +Instruction Source 0 Doubleword 2 (DW2) contains the first source operand and also flag register +number. + +  Instruction Source 0 Doubleword 2 (DW2) shows the field definition for Direct Addressing with + Align16. +  Instruction Source 0 Doubleword 2 (DW2) shows the field definition for Direct Addressing with + Align1. +  Instruction Source 0 Doubleword 2 (DW2) shows the field definition for Indirect Addressing with + Align16. +  Instruction Source 0 Doubleword 2 (DW2) shows the field definition for Indirect Addressing with + Align1. + +Instruction Source 0 Doubleword in Direct+Align16 mode + Bits Description + Reserved: MBZ +31:26 + + 25 + FlagSubRegNum – Flag Sub-Register Number. This field specifies the sub-register number for a flag + register operand. There are two sub-registers in the flag register. Each sub-register contains 16 flag bits. + The selected flag sub-register is the source for predication if predication is enabled for the instruction. It is the + destination to store conditional flag bits if conditional modifier is enabled for the instruction. The same flag + sub-register can be both the predication source and conditional destination, if both predication and + conditional modifier are enabled. +24:21 + Src0.VertStride – Source 0 Vertical Stride. This field is the VertStride for src0 operand. + It is ignored if src0 is an immediate operand. + 20 Reserved: MBZ +19:16 + Src0.ChanSel[7:4] + This is bits [7:4] of the ChanSel field for src0 operand. + + 15 + Src0.AddrMode – Source 0 Address Mode. This field is the AddrMode for src0 operand. + It is ignored if src0 is an immediate operand. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 115 + Bits Description +14:13 + Src0.SrcMod – Source 0 Source Modifier. This field is the SrcMod for source operand src0. + +12:5 + Src0.RegNum – Source 0 Register Number + This is the RegNum field for source operand src0. + It is ignored if src0 is an immediate operand. + + 4 + Src0.SubRegNum[4] + This is the 16-byte aligned sub-register address for source operand src0. + It is ignored if src0 is an immediate operand. + Note: The recommended instruction syntax uses GRF subregister numbers in units of element size, which + the assembler translates to the appropriate value for this field. For example, using the F (Float) type the + possible subregister numbers in Align16 mode are 0 or 4, corresponding to 0 or 1 for this field. + 3:0 + Src0.ChanEn – Source 0 Channel Enable + This is the ChanEn field for source operand src0. + It is ignored if src0 is an immediate operand. + + +Instruction Source 0 Doubleword in Direct+Align1 mode +Bits Description + Reserved: MBZ +31:26 + 25 + FlagSubRegNum – Flag Sub-Register Number. This field specifies the sub-register number for a flag + register operand. +24:21 + Src0.VertStride – Source 0 Vertical Stride + This is the VertStride field for src0 operand. + It is ignored if src0 is an immediate operand. + +20:18 + Src0.Width. This is the Width field for source operand src0. + It is ignored if src0 is an immediate operand. +17:16 + Src0.HorzStride. This is the HorzStride field for source operand src0. + It is ignored if src0 is an immediate operand. + 15 + Src0.AddrMode – Source 0 Address Mode. This is the AddrMode for source operand src0. + It is ignored if src0 is an immediate operand. +14:13 + Src0.SrcMod – Source 0 Source Modifier. This is the SrcMod field for source operand src0. + It is ignored if src0 is an immediate operand. + +12:5 + Src0.RegNum – Source 0 Register Number. This is the RegNum field for source operand src0. + It is ignored if src0 is an immediate operand. + 4:0 + Src0.SubRegNum – Source 0 Sub-Register Number. This is the SubRegNum field for source operand + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 116 + Bits Description + src0. + It is ignored if src0 is an immediate operand. + Note: The recommended instruction syntax uses GRF subregister numbers in units of element size, which + the assembler translates to the appropriate value for this field. + + +Instruction Source 0 Doubleword in Indirect+Align16 mode +Bits Description + Reserved: MBZ +31:26 + 25 + FlagSubRegNum – Flag Sub-Register Number. This field specifies the sub-register number for a flag + register operand. + +24:21 + Src0.VertStride – Source 0 Vertical Stride. This is the VertStride field for src0 operand. + It is ignored if src0 is an immediate operand. + 20 Reserved: MBZ +19:16 + Src0.ChanSel[7:4] – Source 0 Channel Select. This is bits [7:4] of the ChanSel field for src0 operand. + It is ignored if src0 is an immediate operand. + 15 + Src0.AddrMode – Source 0 Address Mode. This is the AddrMode for source operand src0. + It is ignored if src0 is an immediate operand. +14:13 + Src0.SrcMod – Source 0 Source Modifier. This is the SrcMod field for source operand src0. + It is ignored if src0 is an immediate operand. + +12:10 + Src0.AddrSubRegNum – Source 0 Address Sub-Register Number. This is the AddrSubRegNum field for + source operand src0. + It is ignored if src0 is an immediate operand. + 9:4 + Src0.AddrImm[9:4] – Source 0 Address Immediate. This contains the half-register aligned AddrImm field + ((bits [9:4]) for src0. + It is ignored if src0 is an immediate operand. + 3:0 + Src0.ChanEn – Source 0 Channel Enable . This is the ChanEnfield for source operand src0. + It is ignored if src0 is an immediate operand. + + +Instruction Source 0 Doubleword in Indirect+Align1 mode +Bits Description + Reserved: MBZ +31:26 + 25 + FlagSubRegNum – Flag Sub-Register Number. This field specifies the sub-register number for a flag + register operand. + +24:21 + Src0.VertStride – Source 0 Vertical Stride. This is the VertStride field for src0 operand. + It is ignored if src0 is an immediate operand. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 117 + Bits Description +20:18 + Src0.Width. This is the Width field for source operand src0. + It is ignored if src0 is an immediate operand. +17:16 + Src0.HorzStride. This is the HorzStride field for source operand src0. + It is ignored if src0 is an immediate operand. + + 15 + Src0.AddrMode – Source 0 Address Mode. This is the AddrMode for source operand src0. + It is ignored if src0 is an immediate operand. +14:13 + Src0.SrcMod – Source 0 Source Modifier. This is the SrcMod field for source operand src0. + It is ignored if src0 is an immediate operand. +12:10 + Src0.AddrSubRegNum – Source 0 Address Sub-Register Number. This is the AddrSubRegNum field for + source operand src0. + It is ignored if src0 is an immediate operand. + 9:0 + Src0.AddrImm – Source 0 Address Immediate. This is the byte aligned AddrImm field for src0. + It is ignored if src0 is an immediate operand. + +This section describes the field in DW2 and DW3 of the 3-src instruction format. + +Instruction DW2 and DW3 3-Source + DW Bits Description + Reserved: MBZ +DW3 31:30 + + 29:22 + Source2 Register Number. This field contains the register number for source2. + + 21:19 + Source2 Subregister Number. This field contains the subregister number for source2. + Note: The recommended instruction syntax uses GRF subregister numbers in units of element size, + which the assembler translates to the appropriate value for this field. + 18:11 + Source2 Channel Select. This field contains the swizzle control for source2. + See ChanSel in the Common Instruction Fieldssection for a description of the Source Swizzle + encodings. + 10:10 + Source2 Replication Control. This field controls replication for source2. + See RepCtrl in the Common Instruction Fieldssection for a description of the Source Replication + Control encodings. + + Reserved: MBZ + 9:9 + 8:1 + Source1 Register Number. This field contains the register number for source1. + + 0 + Source1 Subregister Number. This field contains the subregister number for source1. + Note: The recommended instruction syntax uses GRF subregister numbers in units of element size, + which the assembler translates to the appropriate value for this field. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 118 + DW Bits Description + 31:30 +DW2 Source1 Subregister Number. This field contains the subregister number for source1. + Note: The recommended instruction syntax uses GRF subregister numbers in units of element size, + which the assembler translates to the appropriate value for this field. + 29:22 + Source1 Channel Select. This field contains the swizzle control for source1. + See ChanSel in the Common Instruction Fieldssection for a description of the Source Swizzle + encodings. + + 21:21 + Source1 Replication Control. This field controls replication for source1. + See RepCtrl in the Common Instruction Fieldssection for a description of the Source Replication + Control encodings. + Reserved: MBZ + 20:20 + 19:12 + Source0 Register Number. This field contains the register number for source0. + + 11:9 + Source0 Subregister Number. This field contains the subregister number for source0. + Note: The recommended instruction syntax uses GRF subregister numbers in units of element size, + which the assembler translates to the appropriate value for this field. + + 8:1 + Source0 Channel Select. This field contains the swizzle control for source0. + See ChanSel in the Common Instruction Fieldssection for a description of the Source Swizzle + encodings. + 0:0 + Source0 Replication Control. This field controls replication for source0. + See RepCtrl in the Common Instruction Fieldssection for a description of the Source Replication + Control encodings. + + + +5.2.6 Instruction Source 1 Doubleword 3 (DW3) +Instruction Source 1 Doubleword 3 (DW3) contains the second source operand (src1) and is used to hold +the 32-bit immediate source (imm32 as src0 or src1). Instruction Source 1 Doubleword 3 (DW3) and +Instruction Source 1 Doubleword 3 (DW3) define the fields in this doubleword with the following +exceptions: + +  If src0 is an immediate operand, this doubleword contains imm32 for src0. +  If src1 is an immediate operand, this doubleword contains imm32 for src1. +  If the instruction is a send, bit 31 of this doubleword contains EOT field. + o If src1 is immediate, the remaining 31 bits in this doubleword is MsgDescpt31. + o If src1 is a register, src1 must be a0.0. The rest of this doubleword will be configured + accordingly. + +  If indirect address is supported for src1, Instruction Source 1 Doubleword 3 (DW3) and Instruction + Source 1 Doubleword 3 (DW3) define the fields in DW3 for indirectly addressed src1 in Align16 and + Align1 modes. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 119 + Instruction Source 1 Doubleword in Direct + Align16 mode +Bits Description + Reserved: MBZ +31:25 +24:21 + Src1.VertStride – Source 1 Vertical Stride. This field is the VertStride for src1 operand. + It is ignored if src1 is an immediate operand. + + 20 Reserved: MBZ +19:16 + Src1.ChanSel[7:4] + This contains bits [7:6] of the ChanSel field for src1 operand. + It is ignored if src1 is an immediate operand. + Reserved: MBZ + 15 +14:13 + Src1.SrcMod – Source 1 Source Modifier. This field is the SrcMod for src1 operand. + It is ignored if src1 is an immediate operand. +12:5 + Src1.RegNum. This field is the RegNum field for src1 operand. + It is ignored if src1 is an immediate operand. + + 4 + Src1.SubRegNum[4]. This field is bit [4] of the SubRegNum field for src1. + It is ignored if src1 is an immediate operand. + Note: The recommended instruction syntax uses GRF subregister numbers in units of element size, which + the assembler translates to the appropriate value for this field. For example, using the F (Float) type the + possible subregister numbers in Align16 mode are 0 or 4, corresponding to 0 or 1 for this field. + 3:0 + Src1.ChanEn – Source 1 Channel Enable. It is the channel enable field for src1. It is ignored if src1 is an + immediate operand. + + +Instruction Source 1 Doubleword in Direct + Align1 mode +Bits Description + Reserved: MBZ +31:25 +24:21 + Src1.VertStride – Source 1 Vertical Stride. This field is the VertStride for src1 operand. + It is ignored if src1 is an immediate operand. +20:18 + Src1.Width. This is the Width field for source operand src1. + It is ignored if src1 is an immediate operand. + +17:16 + Src1.HorzStride. This is the HorzStride field for source operand src1. + It is ignored if src1 is an immediate operand. + Reserved: MBZ + 15 +14:13 + Src1.SrcMod – Source 1 Source Modifier. This field is the SrcMod for src1 operand. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 120 + Bits Description + It is ignored if src1 is an immediate operand. +12:5 + Src1.RegNum – Source 1 Register Number. This is the RegNum field for source operand src1. + It is ignored if src1 is an immediate operand. + + 4:0 + Src1.SubRegNum – Source 1 Sub-Register Number. This is the SubRegNum field for source operand + src1. + It is ignored if src1 is an immediate operand. + Note: The recommended instruction syntax uses GRF subregister numbers in units of element size, which + the assembler translates to the appropriate value for this field. + + +Instruction Source 1 Doubleword in Indirect+Align16 mode + Bits Description + Reserved: MBZ + 31:25 + 24:21 + Src1.VertStride – Source 1 Vertical Stride + This is the VertStride field for src1 operand. + It is ignored if src1 is an immediate operand. + 20 Reserved: MBZ + 19:16 + Src1.ChanSel[7:4] – Source 1 Channel Select + This is bits [7:4] of the ChanSel field for src1 operand. + It is ignored if src1 is an immediate operand. + 15 + Src1.AddrMode – Source 1 Address Mode + This is the AddrMode for source operand src1. + It is ignored if src1 is an immediate operand. + + 14:13 + Src1.SrcMod – Source 1 Source Modifier + This is the SrcMod field for source operand src1. + It is ignored if src1 is an immediate operand. + 12:10 + Src1.AddrSubRegNum – Source 1 Address Sub-Register Number + This is the AddrSubRegNum field for source operand src1. + It is ignored if src1 is an immediate operand. + 9:4 + Src1.AddrImm[9:4] – Source 1 Address Immediate + This contains the half-register aligned AddrImm field ((bits [9:4]) for src1. + It is ignored if src1 is an immediate operand. + 3:0 + Src1.ChanEn – Source 1 Channel Enable + This is the ChanEnfield for source operand src1. + It is ignored if src1 is an immediate operand. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 121 + Instruction Source 1 Doubleword in Indirect+Align1 mode + Bits Description + Reserved: MBZ + 31:25 + 24:21 + Src1.VertStride – Source 1 Vertical Stride + This is the VertStride field for src1 operand. + It is ignored if src1 is an immediate operand. + + 20:18 + Src1.Width + This is the Width field for source operand src1. + It is ignored if src1 is an immediate operand. + 17:16 + Src1.HorzStride + This is the HorzStride field for source operand src1. + It is ignored if src1 is an immediate operand. + 15 + Src1.AddrMode – Source 1 Address Mode + This is the AddrMode for source operand src1. + It is ignored if src1 is an immediate operand. + 14:13 + Src1.SrcMod – Source 1 Source Modifier + This is the SrcMod field for source operand src1. + It is ignored if src1 is an immediate operand. + + 12:10 + Src1.AddrSubRegNum – Source 1 Address Sub-Register Number + This is the AddrSubRegNum field for source operand src1. + It is ignored if src1 is an immediate operand. + 9:0 + Src1.AddrImm – Source 1 Address Immediate + This is the byte aligned AddrImm field for src1. + It is ignored if src1 is an immediate operand. + + + + +5.3 EU Compact Instructions +On receiving an instruction with bit 29 (CmptCtrl) set, HW recognizes it as a 64-bit compact instruction. +Hardware then uses the index fields inside the compact instruction to lookup values in the associated +compaction tables, then uses the table outputs along with other fields in the compact instruction to +reconstruct the 128-bit native-sized instruction. +In flow control instructions, IP offsets, such as the JIP and UIP instruction fields, are measured in 64-bit +QWords. Thus a compact 64-bit instruction is 1 unit for IP offset calculations and a native 128-bit +instruction is 2 units for IP offset calculations. +The native 128-bit instruction format provides access to all instruction options. Only some instruction +options and combinations of instruction options can be represented in the compact instruction formats. + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 122 + Which native instructions can be represented as compact instructions and the details of the compact +instruction formats and the compaction tables used may change with each processor generation. +In the following instruction format tables the Mapping Bits and Mapping Description columns describe the +mappings into native instruction fields. + + +5.3.1 EU Compact Instruction Format +The following table describes the EU compact instruction format. For this processor, instructions with +three source operands cannot be compacted. + +Compact Instruction Format + Mapping Compact + Bits Size Bits Name Mapping Description +63:56 8 108:101 Src1.RegNum Src1.RegNum in 108:101 if not immediate. Imm32[7:0] in 103:96 if immediate. + (Not + Imm.) + or 103:96 + (Imm.) +55:48 8 76:69 Src0.RegNum Src0.RegNum. +47:40 8 60:53 Dst.RegNum Dst.RegNum. +39:35 5 120:109 Src1Index Lookup one of 32 12-bit values. If not an immediate operand, maps to bits + (Not 120:109, covering the Src1.AddrMode, Src1.ChanSel[7:4], Src1.HorzStride, + Imm.) Src1.SrcMod, Src1.VertStride, and Src1.Width bit fields. If an immediate + or operand, does not do any lookup. The 5-bit value directly maps to bits 108:104 + 127:104 (Imm32[12:8]) and the upper bit (bit 39 in the compact format, bit 108 in the + (Imm.) native format) is replicated to provide bits 127:109 (Imm32[31:13]) in the native + format. +34:30 5 88:77 Src0Index Lookup one of 32 12-bit values. That value is used (from MSB to LSB) for the + Src0.AddrMode, Src0.ChanSel[7:4], Src0.HorzStride, Src0.SrcMod, + Src0.VertStride, and Src0.Width bit fields. Note that this field spans a DWord + boundary within the QWord compacted instruction. + 29 1 29 CmptCtrl + Compaction Control. The same in both the compact and native formats: + 0: Regular instruction, not compacted. + 1: Compacted instruction. + + 28 1 + Not Reserved Not mapped. MBZ. + mapped. +27:24 4 27:24 CondModifier CondModifier. The same in both the compact and native formats. + 23 1 28 AccWrCtrl AccWrCtrl. +22:18 5 100:96, SubRegIndex Lookup one of 32 15-bit values. That value is used (from MSB to LSB) for various + 68:64, fields for Src1, Src0, and Dst, including ChanEn/ChanSel, SubRegNum, and + 52:48 AddrImm[4] or AddrImm[4:0], depending on AddrMode and AccessMode. +17:13 5 63:61, DataTypeIndex Lookup one of 32 18-bit values. That value is used (from MSB to LSB) for the + 46:32 Dst.AddrMode, Dst.HorzStride, Dst.DstType, Dst.RegFile, Src0.SrcType, + Src0.RegFile, Src1.SrcType, and Src1.RegType bit fields. +12:8 5 ControlIndex + 90:89, Lookup one of 32 19-bit values. That value is used (from MSB to LSB) for the + 31, 23:8 FlagRegNum, FlagSubRegNum, Saturate, ExecSize, PredInv, PredCtrl, + ThreadCtrl, QtrCtrl, DepCtrl, MaskCtrl, and AccessMode bit fields. + 6:0 7 6:0 Opcode Opcode. The same in both the compact and native formats. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 123 + 5.3.1.1 EU Instruction Compaction Tables +The following four tables describe the mappings for the ControlIndex, DataTypeIndex, SubRegIndex, +Src0Index, and Src1Index fields in the compact instruction format. + +ControlIndex Compact Instruction Field Mappings +ControlIndex 19-Bit Mapping Mapped Meaning + 0 0000000000000000010 Align1 | We | (1) | f0.0 + 1 0000100000000000000 Align1 | (4) | f0.0 + 2 0000100000000000001 Align16 | (4) | f0.0 + 3 0000100000000000010 Align1 | We | (4) | f0.0 + 4 0000100000000000011 Align16 | We | (4) | f0.0 + 5 0000100000000000100 Align1 | NoDDClr | (4) | f0.0 + 6 0000100000000000101 Align16 | NoDDClr | (4) | f0.0 + 7 0000100000000000111 Align16 | We | NoDDClr | (4) | f0.0 + 8 0000100000000001000 Align1 | NoDDChk | (4) | f0.0 + 9 0000100000000001001 Align16 | NoDDChk | (4) | f0.0 + 10 0000100000000001101 Align16 | NoDDClr, NoDDChk | (4) | f0.0 + 11 0000110000000000000 Align1 | Q1 | (8) | f0.0 + 12 0000110000000000001 Align16 | Q1 | (8) | f0.0 + 13 0000110000000000010 Align1 | We | Q1 | (8) | f0.0 + 14 0000110000000000011 Align16 | We | Q1 | (8) | f0.0 + 15 0000110000000000100 Align1 | NoDDClr | Q1 | (8) | f0.0 + 16 0000110000000000101 Align16 | NoDDClr | Q1 | (8) | f0.0 + 17 0000110000000000111 Align16 | We | NoDDClr | Q1 | (8) | f0.0 + 18 0000110000000001001 Align16 | NoDDChk | Q1 | (8) | f0.0 + 19 0000110000000001101 Align16 | NoDDClr, NoDDChk | Q1 | (8) | f0.0 + 20 0000110000000010000 Align1 | Q2 | (8) | f0.0 + 21 0000110000100000000 Align1 | Q1 | +f.xyzw | (8) | f0.0 + 22 0001000000000000000 Align1 | H1 | (16) | f0.0 + 23 0001000000000000010 Align1 | We | H1 | (16) | f0.0 + 24 0001000000000000100 Align1 | NoDDClr | H1 | (16) | f0.0 + 25 0001000000100000000 Align1 | H1 | +f.xyzw | (16) | f0.0 + 26 0010110000000000000 Align1 | Q1 | (8) | .sat | f0.0 + 27 0010110000000010000 Align1 | Q2 | (8) | .sat | f0.0 + 28 0011000000000000000 Align1 | H1 | (16) | .sat | f0.0 + 29 0011000000100000000 Align1 | H1 | +f.xyzw | (16) | .sat | f0.0 + 30 0101000000000000000 Align1 | H1 | (16) | f0.1 + 31 0101000000100000000 Align1 | H1 | +f.xyzw | (16) | f0.1 + +DataTypeIndex Compact Instruction Field Mappings +DataTypeIndex 18-Bit Mapping Mapped Meaning + 0 001000000000000001 r:ud | a:ud | a:ud | <1> | dir | + 1 001000000000100000 a:ud | r:ud | a:ud | <1> | dir | + 2 001000000000100001 r:ud | r:ud | a:ud | <1> | dir | + 3 001000000001100001 r:ud | i:ud | a:ud | <1> | dir | + 4 001000000010111101 r:f | r:d | a:ud | <1> | dir | + 5 001000001011111101 r:f | i:vf | a:ud | <1> | dir | + 6 001000001110100001 r:ud | r:f | a:ud | <1> | dir | + 7 001000001110100101 r:d | r:f | a:ud | <1> | dir | + 8 001000001110111101 r:f | r:f | a:ud | <1> | dir | + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 124 + DataTypeIndex 18-Bit Mapping Mapped Meaning + 9 001000010000100001 r:ud | r:ud | r:ud | <1> | dir | + 10 001000110000100000 a:ud | r:ud | i:ud | <1> | dir | + 11 001000110000100001 r:ud | r:ud | i:ud | <1> | dir | + 12 001001010010100101 r:d | r:d | r:d | <1> | dir | + 13 001001110010100100 a:d | r:d | i:d | <1> | dir | + 14 001001110010100101 r:d | r:d | i:d | <1> | dir | + 15 001111001110111101 r:f | r:f | a:f | <1> | dir | + 16 001111011110011101 r:f | a:f | r:f | <1> | dir | + 17 001111011110111100 a:f | r:f | r:f | <1> | dir | + 18 001111011110111101 r:f | r:f | r:f | <1> | dir | + 19 001111111110111100 a:f | r:f | i:f | <1> | dir | + 20 000000001000001100 a:w | a:ub | a:ud | <0> | dir | + 21 001000000000111101 r:f | r:ud | a:ud | <1> | dir | + 22 001000000010100101 r:d | r:d | a:ud | <1> | dir | + 23 001000010000100000 a:ud | r:ud | r:ud | <1> | dir | + 24 001001010010100100 a:d | r:d | r:d | <1> | dir | + 25 001001110010000100 a:d | a:d | i:d | <1> | dir | + 26 001010010100001001 r:uw | a:uw | r:uw | <1> | dir | + 27 001101111110111101 r:f | r:f | i:vf | <1> | dir | + 28 001111111110111101 r:f | r:f | i:f | <1> | dir | + 29 001011110110101100 a:w | r:w | i:w | <1> | dir | + 30 001010010100101000 a:uw | r:uw | r:uw | <1> | dir | + 31 001010110100101000 a:uw | r:uw | i:uw | <1> | dir | + +SubRegIndex Compact Instruction Field Mappings +SubRegIndex 15-Bit Mapping Mapped Meaning + 0 000000000000000 0 | 0 | 0 | + 1 000000000000001 0.x | 0.xx | 0.xx + 2 000000000001000 8 | 0 | 0 | + 3 000000000001111 0.xyzw | 0.xx | 0.xx + 4 000000000010000 16 | 0 | 0 | + 5 000000010000000 0 | 4 | 0 | + 6 000000100000000 0 | 8 | 0 | + 7 000000110000000 0 | 12 | 0 | + 8 000001000000000 0 | 16 | 0 | + 9 000001000010000 16 | 16 | 0 | + 10 000001010000000 0 | 20 | 0 | + 11 001000000000000 0 | 0 | 4 | + 12 001000000000001 0.x | 0.xx | 0.xy + 13 001000010000001 0.x | 0.xy | 0.xy + 14 001000010000010 0.y | 0.xy | 0.xy + 15 001000010000011 0.xy | 0.xy | 0.xy + 16 001000010000100 0.z | 0.xy | 0.xy + 17 001000010000111 0.xyz | 0.xy | 0.xy + 18 001000010001000 0.w | 0.xy | 0.xy + 19 001000010001110 0.yzw | 0.xy | 0.xy + 20 001000010001111 0.xyzw | 0.xy | 0.xy + 21 001000110000000 0 | 12 | 4 | + 22 001000111101000 0.w | 0.ww | 0.xy + 23 010000000000000 0 | 0 | 8 | + 24 010000110000000 0 | 12 | 8 | + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 125 + SubRegIndex 15-Bit Mapping Mapped Meaning + 25 011000000000000 0 | 0 | 12 | + 26 011110010000111 0.xyz | 0.xy | 0.ww + 27 100000000000000 0 | 0 | 16 | + 28 101000000000000 0 | 0 | 20 | + 29 110000000000000 0 | 0 | 24 | + 30 111000000000000 0 | 0 | 28 | + 31 111000000011100 28 | 0 | 28 | + +Src0Index or Src1Index Compact Instruction Field Mappings +Src0Index or + Src1Index 12-Bit Mapping Mapped Meaning + 0 000000000000 dir | <0;1,0> + 1 000000000010 (-) | dir | <0;1,0> + 2 000000010000 dir | <0;>.zx + 3 000000010010 (-) | dir | <0;>.zx + 4 000000011000 dir | <0;>.wx + 5 000000100000 dir | <0;>.xy + 6 000000101000 dir | <0;>.yy + 7 000001001000 dir | <0;4,1> + 8 000001010000 dir | <0;>.zz + 9 000001110000 dir | <0;>.zw + 10 000001111000 dir | <0;8,4> / dir | <0;>.ww + 11 001100000000 dir | <4;>.xx + 12 001100000010 (-) | dir | <4;>.xx + 13 001100001000 dir | <4;>.yx + 14 001100010000 dir | <4;>.zx + 15 001100010010 (-) | dir | <4;>.zx + 16 001100100000 dir | <4;>.xy + 17 001100101000 dir | <4;>.yy + 18 001100111000 dir | <4;>.wy + 19 001101000000 dir | <4;4,0> + 20 001101000010 (-) | dir | <4;4,0> + 21 001101001000 dir | <4;>.yz + 22 001101010000 dir | <4;>.zz + 23 001101100000 dir | <4;>.xw + 24 001101101000 dir | <4;>.yw + 25 001101110000 dir | <4;>.zw + 26 001101110001 (abs) | dir | <4;>.zw + 27 001101111000 dir | <4;>.ww + 28 010001101000 dir | <8;8,1> + 29 010001101001 (abs) | dir | <8;8,1> + 30 010001101010 (-) | dir | <8;8,1> + 31 010110001000 dir | <16;16,1> + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 126 + 5.4 Opcode Encoding +Byte 0 of the 128-bit instruction word contains the opcode. The opcode uses 7 bits. Bit location 7 in byte 0 +is reserved for future opcode extension. +The opcodes are encoded and organized into five groups based on the type of operations: Special +instructions, move/logic instructions (opcode=00xxxxxb), flow control instructions (opcode=010xxxxb), +miscellaneous instructions (opcode=011xxxxb), parallel arithmetic instructions (opcode=100xxxxb), and +vector arithmetic instructions (opcode=101xxxxb). Opcodes 110xxxb are reserved. +Note: Opcodes appear in the overall Instruction Set Summary Table as well. The following subsections +still serve the purpose of describing various instruction groups. + + +5.4.1 Move and Logic Instructions +This instruction group has an opcode format of 00xxxxxb. + +  The opcodes for move instructions (mov, sel and movi) share the common 5 MSBs in the form of + 00000xxb. +  The opcodes for logic instructions (not, and, or, and xor) share the common 5 MSBs in the form of + 00001xxb. +  The opcodes for shift instructions (shr, shl, and asr) share the common 4 MSBs in the form of + 0001xxxb. Bit 2 indicates arithmetic or logic shift (0 = logic, 1 = arithmic). Bit 1 is always 0 (which is + reserved for future extension to support rotation shift as 0 = shift, 1 = rotate). Bit 0 indicates the shift + direction (0 = right, 1 = left). +  The opcodes for compare instructions (cmp and cmpn) share the common 6 MSBs in the form of + 001000xb. Bit 0 indicates whether it is a normal compare, cmp, or a special compare-NaN, cmpn. + +Move and Logic Instructions + Opcode + dec hex Instruction Description #src #dst + 1 0x01 Component-wise move 1 1 + mov + 2 0x02 Component-wise selective move based on predication 2 1 + sel + 3 0x03 Fast component-wise indexed move 1 1 + movi + 4 0x04 Component-wise one's complement (bitwise not) 1 1 + not + + 5 0x05 Component-wise logical AND (bitwise and) 2 1 + and + 6 0x06 Component-wise logical OR (bitwise or) 2 1 + or + 7 0x07 Component-wise logical XOR (bitwise xor) 2 1 + xor + 8 0x08 Component-wise logical shift right 2 1 + shr + + 9 0x09 Component-wise logical shift left 2 1 + shl + + 11 0x0A Reserved + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 127 + Opcode + dec hex Instruction Description #src #dst + 12 0x0C Component-wise arithmetic shift right 2 1 + asr + + 13 0x0D Reserved + + 14 0x0E Reserved + + 15 0x0F Reserved + + 16 0x10 Component-wise compare, store condition code in destination 2 1 + cmp + 17 0x11 Component-wise compare-NaN, store condition code in destination 2 1 + cmpn + 18 0x12 + Reserved + + 19 0x13 f32tof16 Single precision float to half precision float conversion + 20 0x14 f16to32 Half precision float to single precision float conversion + 21 0x15 + Reserved + + 22 0x16 Reserved + 23 0x17 Reverse bits 1 1 + bfrev + + 24 0x18 Bitfield exact 3 1 + bfe + + 25 0x19 Bitfield insert macro instruction 1, generate mask 2 1 + bfi1 + + 26 0x1A + bfi2 + +27-31 0x1B-0x1F Reserved + + + +5.4.2 Flow Control Instructions +This instruction group has an opcode format of 010xxxxb. + +Flow Control Instructions + Opcode +dec hex Instruction Description #src #dst + 32 0x20 Jump indexed 1 0 + jmpi + + 0x21 Branch - Diverging 1 0 + 33 brd +34 0x22 If 0/2 0 + if +35 0x23 Branch - Converging 1 - + brc +36 0x24 Else 1 0 + else + +37 0x25 End if 0 0 + endif + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 128 + Opcode +dec hex Instruction Description #src #dst + 38 0x26 Case – Inside Switch block 0/2 0 + case +39 0x27 While 1 0 + while +40 0x28 Break 1 0 + break +41 0x29 Continue 1 0 + cont + +42 0x2A Halt 1 0 + halt +43 0x2B + Reserved + + +44 0x2C Subroutine call 1 1 + call +45 0x2D Subroutine return 1 1 + return + +46 0x2E + Reserved +47 0x2F + Reserved + + + +5.4.3 Miscellaneous Instructions +This instruction group has an opcode format of 011xxxxb. + +Miscellaneous Instructions + Opcode Instruction #dst + + dec hex Description #src + 48 0x30 Wait for (external) notification 1 0 + wait + 49 0x31 Send 1 1 + send + 50 0x32 Conditional Send (based on TDR) 1 1 + sendc + +51-55 0x33-0x37 Reserved + + 56 0x38 Math functions for extended math pipeline 1/2 1/2 + math + +57-63 0x39-0x3F Reserved + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 129 + 5.4.4 Parallel Arithmetic Instructions +This instruction group has an opcode format of 100xxxxb. + +Parallel Arithmetic Instructions + Opcode Instruction #dst + + dec hex Description #src + 64 0x40 Component-wise addition 2 1 + add + 65 0x41 Component-wise multiply 2 1 + mul + 66 0x42 Component-wise average of the two source operands 2 1 + avg + + 67 0x43 Component-wise floating point truncate-to-minus-infinity 1 1 + frc + fraction + 68 0x44 Component-wise floating point rounding up (ceiling) 1 1 + rndu + 69 0x45 Component-wise floating point rounding down (floor) 1 1 + rndd + 70 0x46 Component-wise floating point rounding toward nearest even 1 1 + rnde + + 71 0x47 Component-wise floating point rounding toward zero 1 1 + rndz + 72 0x48 Component-wise multiply accumulate 2 1 + mac + 73 0x49 multiply accumulate high 2 1 + mach + 74 0x4A leading zero detection 1 1 + lzd + + 75 0x4B Find first 1 for UD from msb side, or first 1/0 for D. 1 1 + fbh + + + 76 0x4C First first 1 for UD from lsb side 1 1 + fbl + + + 77 0x4D Count bits set 1 1 + cbit + + + 78 0x4E Integer add with carry 2 1+ + addc + acc. + + + 79 0x4F integer subtract with borrow 2 1+ + subb + acc. + + +75-79 0x4B- Reserved + 0x4F + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 130 + 5.4.5 Vector Arithmetic Instructions + This instruction group has an opcode format of 101xxxxb. + +Vector Arithmetic Instructions + Opcode +dec hex Instruction Description #src #dst + 80 0x50 2-wide sum of absolute difference 2 1 + sad2 + 81 0x51 2-wide sad accumulate 2 1 + sada2 + 82- 0x52-0x53 + reserved + 83 + 84 0x54 4-wide dot product for 4-vector 2 1 + dp4 + + 85 0x55 4-wide homogenous dot product for 4-vector 2 1 + dph + 86 0x56 3-wide dot product for 4-vector 2 1 + dp3 + 87 0x57 2-wide dot product for 4-vector 2 1 + dp2 + 88 0x58 + reserved + + 89 0x59 Component-wise line equation computation (a multiply-add) 2 1 + line + 90 0x5A Component-wise floating point plane equation computation (a multiply-multiply- 2 1 + pln + add) + 91 0x5B Component-wise floating point mad computation (a multiple-add) 3 1 + fma(mad) + 92 0x5C Component-wise floating point lrp computation (blend) 3 1 + lrp + + 93 0x5D reserved + 94- 0x5D- + reserved + 95 0x5F + + +5.4.6 Special Instructions +There are two special instructions, namely, nop (opcode = 0x7E) and illegal (opcode = 0x00). + +  Nop instruction may be used for instruction padding in memory between two normal instructions to + force alignment or to introduce instruction execution delay. Currently, there is no need for between- + instruction padding. +  Illegal instruction may be used for instruction padding in memory outside the normal instruction + sequence such as before or after the kernel program as well as between subroutines. +  Nop and illegal instructions do not have source operands or destination operand. Therefore, they do + not implicitly update the accumulator register. They cannot be compressed. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 131 + Special Instructions + Opcode + dec hex Instruction Description #src #dst + 0 0x00 Illegal instruction 0 0 + illegal + + 96-124 0x60-0x7D Reserved + + 126 0x7E No-op 0 0 + nop + (may be used as an extension code) + 127 0x7F Reserved + + + +5.5 Native Instruction BNF +The Backus-Naur Form (BNF) grammar identifies the assembly language syntax, which is native to the +hardware. It does not include intelligent defaults, assembler pragmas, etc. + + +5.5.1 Instruction Groups +::= + + +| +| +| +| +| +| +| +| +| +| +| +| +| +| +::= dst +::= +::= “mov” | “frc” | “rndu” | “rndd” | “rnde” | “rndz” | “not” | “lzd” +::= dst +::= +::= “mul” | “mac” | “mach” | “line”” | “pln” +|“sad2” | “sada2” | “dp4” | “dph” | “dp3” | “dp2”” | “Irp”” | “bfi1”” | “addc”” | “subb” +::= dst + + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 132 + ::= +::= “avg” | “add” | “sel” +|“and” | “or” | “xor” +|“shr” | “shl” | “asr” +|“cmp” | “cmpn” +::= + +::= +::= “send” + ::= dst + ::= +, ::= “bfe”| “bfi2”|”mad” + ::= < RelativeLocation2> + ::= “brc” + ::= < RelativeLocation3> + ::= “brd” + ::= dst< RelativeLocation2> + ::= “call” |”CALLA” + ::= < Dst>< Src>< Src> + ::= + ::= “math” + ::= “INV” | “LOG” | “EXP” | “SQRT” |”RSQ” | “POW” | “SIN” | “COS” | “INT DIV” + ::= +::= “jmpi” +::= < RelativeLocation> +::=“if” | “iff” | “while” +::= < RelativeLocation> +::=“else” +::= +::=“break” | “cont” | “halt” +::= +::=“wait” +::=“do” | “endif” |“nop” | “illegal” + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 133 + 5.5.2 Destination Register +dst::= + + +| +::= +::= +| +| +| +| +| +| +| +| +| +| +::= | +| | +::= +| +::= | +::= + + +5.5.3 Source Register +Source with Accumulator Access and with Immediate +::= + + +| +::= + + +| +::= +| +| +::= +| + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 134 + | +| +| +| +| +| +| +| +::= +Source without Accumulator Access +::= + + +| +< DirectSrcOperand>::= +| +::= + + +| +::= + + +| +::= +Source without Accumulator Access or IP Access +::= + + +| + + +5.5.4 Address Registers +::= +::= “” +| “,” + + +5.5.5 Register Files and Register Numbers +Note: The recommended instruction syntax uses subregister numbers within the GRF in units of actual +data element size, corresponding to the data type used. For example for the F (Float) type, the assembler +syntax uses subregister numbers 0 to 7, corresponding to subregister byte addresses of 0 to 28 in steps +of 4, the element size. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 135 + ::= +::= “[“ “]” +::=“r” +:: =“0”…“127” +:: = “” +| “.0”…”.3” //incase of DF +| “.0”...“.7” +| “.0”...“.15” +| “.0”...“.31” +::= +::= +::= “[“ “]” +::=“m” +:: =“0”…“15” +:: = +::= +::=“a0” +:: = “” +| “.0” … “.7” +::=“acc” +:: =“0” | “1” +:: = + ::= “f” + :: = “0” | “1” +::=“f0” +:: =“” +| “.0”...“.1” +::=“n” +:: =“0”...“2” +::=“sr0” +:: =“.0”... “.1” +::=“cr0” +:: =“.0” ...“.2” +::=“ip” +::=“null” + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 136 + ::= “tdr0” + ::= “.0”…“.7” + ::= “tm0” + ::= “ce0.0” + + +5.5.6 Relative Location and Stack Control +::= +::= | + ::= | +::= + + +5.5.7 Regions +::=“<” “>” +::= | | +::=“<” “;” “,” “>” +::=“<” “,” “>” +::=“<” “>” +::= “0” | “1” | “2” | “4” | “8” | “16” | “32” +::=“1” | “2” | “4” | “8” | “16” +::=“0” | “1” | “2” | “4” + + +5.5.8 Types + ::= “:df” | “:f” | “:ud” | “:d” | “:uw” | “:w” | “:ub” | “:b” + ::= | “:v” | “:vf” | “:uv” + ::= + + +5.5.9 Write Mask +::= “” +| “.” “x” | “.” “y” | “.” “z” | “.” “w” +| “.” “xy” | “.” “xz” | “.” “xw” | “.” “yz” | “.” “yw” | “.” “zw” +| “.” “xyz” | “.” “xyw” | “.” “xzw” | “.” “yzw” +| “.” “xyzw” + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 137 + 5.5.10 Swizzle Control +::=“” +| “.” +| “.” +::= “x” | “y” | “z” | “w” + + +5.5.11 Immediate Values +::=“-512”… “511” + ::= “0.0”… “±1.0*2-1024…1023” | “0”…”264-1” | “-263”…”263-1” +::=“0.0”… “±1.0*2-128…127” | “0”…”232-1” | “-231”…”231-1” +::=“0”…”216-1” | “-215”…”215-1” +::=“0”…”232-1” + + +5.5.12 Predication and Modifiers +Instruction Predication +::=“” +|“(” “)” +::=“” +|“+” +|“-“ +::=“” +|“.x” | “.y” | “.z” | “.w” +|“.any2h” | “.all2h” +|“.any4h” | “.all4h” +|“.any8h” | “.all8h” +|“.any16h” | “.all16h” +|“.anyv” | “.allv” +| “.any32h”| “.all32h” +Source Modification +::=“” +|“-” +|“(abs)” +|“-” “(abs)” +Instruction Modification +::=“” + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 138 + | “. ” +::=“.z” | “.e”|“.nz” | “.ne”|“.g”|“.ge”|“.l”|“.le”|“.o” |“.r” |“.u” +::=“” +|“.sat” +Execution Size +::=“(“ “)” +::=“1” | “2” | “4” | “8” | “16” | “32” + + +5.5.13 Instruction Options + ::= “” +| “{” “}” +| “{” “}” + ::= “” +| “,” + ::= +| +| +| +| +| +| + ::= “Align1” | “Align16” + ::= “AccWrEn” + ::= “SecHalf” | “Compr” + ::= “NoDDChk” | “NoDDClr” + ::= “NoMask” + ::= “EOT” + ::= “Switch” ++: | “Atomic” +Note for Assembler: Compression control “Compr” has a direct map to the binary instruction word. It +may be omitted if the Assembler can determine whether an instruction is compressable. + + +5.6 Instruction Set Summary Tables +The columns in the following tables specify instruction mnemonics, hex opcodes, full names, instruction +groups, the number of source operands, whether the instruction supports predication, any support for + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 139 + source modifiers, an indication of supported data types, whether the instruction supports saturation, and +any support for conditional modifiers. +See the separate Accumulator Restrictions table for information about how instructions are allowed to use +accumulators. +N and Y indicate No (no support for a feature) and Yes (full support for a feature) respectively. +A SrcMod (source modifier) value of Y indicates that a numeric source modifier is allowed, optionally +specifying abolute value, negation, or a forced negative value. The value N indicates no source modifier +support. +A SrcMod value of ** indicates a numeric source modifier. +In the Src Types and Dst Type columns, Int means any integer type and * means such an extensive list of +types that you must refer to the detailed instruction description. + +Instruction Set Summary Table A to B (Listed by Instruction Mnemonic) + Hex +Mnem. Opcode Name Group Srcs Pred? SrcMod Src Types Dst Type Sat? CondMod? + add 40 Addition Parallel Arithmetic 2 Y Y * * Y Y + addc 4E Integer Addition with Carry Parallel Arithmetic 2 Y N UD UD N Y + and 05 Logic And Move and Logic 2 Y ** Int Int N Equality only + asr 12 Arithmetic Shift Right Move and Logic 2 Y Y Int Int Y Y + avg 42 Average Parallel Arithmetic 2 Y Y B, UB B, UB Y Y + W, UW W, UW + D, UD D, UD + bfe 18 Bit Field Extract Move and Logic 3 Y N UD, D UD, D N N + bfi1 19 Bit Field Insert 1 Move and Logic 2 Y N UD, D UD, D N N + bfi2 1A Bit Field Insert 2 Move and Logic 3 Y N UD, D UD, D N N + bfrev 17 Bit Field Reverse Move and Logic 1 Y N UD UD N N + brc 23 Branch Converging Flow Control 0 or 1 Y N D N N + brd 21 Branch Diverging Flow Control 0 or 1 Y N D N N +break 28 Break Flow Control 0 Y N N N + + +Instruction Set Summary Table C to E (Listed by Instruction Mnemonic) + Hex +Mnem. Opcode Name Group Srcs Pred? SrcMod Src Types Dst Type Sat? CondMod? + call 2C Call Flow Control 0 Y N D, UD N N + cbit 4D Count Bits Set Move and Logic 1 Y N UB, UW, UD UD N N + cmp 10 Compare Move and Logic 2 Y Y * * N Y +cmpn 11 Compare NaN Move and Logic 2 Y Y * * N Y + cont 29 Continue Flow Control 0 Y N N N + dp2 57 Dot Product 2 Vector Arithmetic 2 Y Y F F Y Y + dp3 56 Dot Product 3 Vector Arithmetic 2 Y Y F F Y Y + dp4 54 Dot Product 4 Vector Arithmetic 2 Y Y F F Y Y + dph 55 Dot Product Homogeneous Vector Arithmetic 2 Y Y F F Y Y + else 24 Else Flow Control 0 N N N N + endif 25 End If Flow Control 0 N N N N + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 140 + Instruction Set Summary Table F to L (Listed by Instruction Mnemonic) + Hex +Mnem. Opcode Name Group Srcs Pred? SrcMod Src Types Dst Type Sat? CondMod? +f16to32 14 Half Precision Float to Move and Logic 1 Y Y W F Y Y + Single Precision Float +f32to16 13 Single Precision Float to Move and Logic 1 Y Y F W Y Y + Half Precision Float + fbh 4B Find First Bit from MSB Side Move and Logic 1 Y N D, UD UD N N + fbl 4C Find First Bit from LSB Side Move and Logic 1 Y N UD UD N N + frc 43 Fraction Parallel Arithmetic 1 Y Y F F N Y + halt 2A Halt Flow Control 0 Y N N N + if 22 If Flow Control 0 Y N N N +illegal 00 Illegal Special 0 N N N N + jmpi 20 Jump Indexed Flow Control 1 Y N D N N + line 59 Line Vector Arithmetic 2 Y Y F F Y Y + lrp 5C Linear Interpolation Vector Arithmetic 3 Y Y F F N Y + lzd 4A Leading Zero Detection Move and Logic 1 Y Y D, UD UD Y Y + + +Instruction Set Summary Table M to P (Listed by Instruction Mnemonic) + Hex +Mnem. Opcode Name Group Srcs Pred? SrcMod Src Types Dst Type Sat? CondMod? + mac 48 Multiply Accumulate Parallel Arithmetic 2 Y Y * * Y Y +mach 49 Multiply Accumulate High Parallel Arithmetic 2 Y Y * * Y Y + mad 5B Multiply Add Parallel Arithmetic 3 Y Y * * Y Y + math 38 Extended Math Function Parallel Arithmetic 2 Y N * * Y N + mov 01 Move Move and Logic 1 Y Y * * Y Y + movi 03 Move Indexed Move and Logic 1 Y Y * * Y N + mul 41 Multiply Parallel Arithmetic 2 Y Y * * Y Y + nop 7E No Operation Special 0 N N N N + not 04 Logic Not Move and Logic 1 Y ** Int Int N Equality only + or 06 Logic Or Move and Logic 2 Y ** Int Int N Equality only + pln 5A Plane Vector Arithmetic 2 Y Y F F Y Y + + +Instruction Set Summary Table R to X (Listed by Instruction Mnemonic) + Hex +Mnem. Opcode Name Group Srcs Pred? SrcMod Src Types Dst Type Sat? CondMod? + ret 2D Return Flow Control 1 Y N D, UD N N + rndd 45 Round Down Parallel Arithmetic 1 Y Y F F Y Y + rnde 46 Round to Nearest or Even Parallel Arithmetic 1 Y Y F F Y Y + rndu 44 Round Up Parallel Arithmetic 1 Y Y F F Y Y + rndz 47 Round to Zero Parallel Arithmetic 1 Y Y F F Y Y + sad2 50 Sum of Absolute Difference 2 Vector Arithmetic 2 Y Y B, UB W, UW Y Y +sada2 51 Sum of Absolute Difference Accumulate 2 Vector Arithmetic 2 Y Y B, UB W, UW Y Y + sel 02 Select Move and Logic 2 Y Y * * Y Y + send 31 Send Message Miscellaneous 1 Y N * * N N +sendc 32 Conditional Send Message Miscellaneous 1 Y N * * N N + shl 09 Shift Left Move and Logic 2 Y Y Int Int Y Y + shr 08 Shift Right Move and Logic 2 Y Y Int Int Y Y + subb 4F Integer Subtraction with Borrow Parallel Arithmetic 2 Y N UD UD N Y + wait 30 Wait Miscellaneous 1 N N UD UD N N + while 27 While Flow Control 0 or 2 Y N * * N Y + while 27 While Flow Control 0 Y N N N + xor 06 Logic Xor Move and Logic 2 Y ** Int Int N Equality only + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 141 + 5.7 Accumulator Restrictions +This section describes restrictions on accumulator access: general restrictions, restrictions for specific +instructions, and how those specific restrictions vary for processor generations. See Accumulator +Registersfor a description of the accumulator registers. +Accumulator registers can be accessed as explicit source or destination operands, as an implicit source +value when specified for a particular instruction (sada2 for example), and as an implicit destination when +the AccWrEn instruction option is used. +These general rules apply to accumulator access: +1. Flow control, send, sendc, and wait instructions cannot use accumulators. +2. Instructions with three source operands cannot use explicit accumulator operands. AccWrEn may be + allowed for implicitly updating the accumulator. +3. Instructions that use the accumulator as an implicit source value cannot specify an explicit + accumulator source operand. +4. Instructions that specify an implicit accumulator destination (with AccWrEn) cannot specify an + explicit accumulator destination operand. +5. An instruction with both an explicit accumulator source operand and an explicit accumulator + destination operand must specify the same accumulator register as the source and the destination. +These descriptions are frequently used in this table: + +  No restrictions. +  No accumulator access, implicit or explicit. +  Source operands cannot be accumulators. +  Source modifier is not allowed if source is an accumulator. +  Accumulator is an implicit source and thus cannot be an explicit source operand. +  Accumulator cannot be destination, implicit or explicit. +  AccWrEn is required. The accumulator is an implicit destination and thus cannot be an explicit + destination operand. + +These minor cases occur occasionally in the table: + +  Integer source operands cannot be accumulators. +  No explicit accumulator access because this is a three-source instruction. AccWrEn is allowed for + implicitly updating the accumulator. +  An accumulator can be a source or destination operand but not both. + +A few instructions use more than one of the listed restrictions. + +Accumulator Restrictions +Instruction Description + add No restrictions. + addc AccWrEn is required. The + accumulator is an implicit + destination and thus cannot be + an explicit destination operand. + and Source modifier is not allowed if + source is an accumulator. + asr No restrictions. + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 142 + Instruction Description + avg No restrictions. + bfe No accumulator access, implicit + or explicit. + bfi1 No accumulator access, implicit + or explicit. + bfi2 No accumulator access, implicit + or explicit. + bfrev No accumulator access, implicit + or explicit. + cbit No accumulator access, implicit + or explicit. + cmp Accumulator cannot be + destination, implicit or explicit. + cmpn Accumulator cannot be + destination, implicit or explicit. + dp2 Source operands cannot be + accumulators. + dp3 Source operands cannot be + accumulators. + dp4 Source operands cannot be + accumulators. + dph Source operands cannot be + accumulators. + f16to32 No accumulator access, implicit + or explicit. + f32to16 No accumulator access, implicit + or explicit. + fbh No accumulator access, implicit + or explicit. + fbl No accumulator access, implicit + or explicit. + frc No restrictions. + line Source operands cannot be + accumulators. + lrp No explicit accumulator access + because this is a three-source + instruction. AccWrEn is allowed + for implicitly updating the + accumulator. + lzd Accumulator cannot be + destination, implicit or explicit. + mac Accumulator is an implicit source + and thus cannot be an explicit + source operand. + mach + Accumulator is an implicit + source and thus cannot be an + explicit source operand. + AccWrEn is required. The + accumulator is an implicit + destination and thus cannot be + an explicit destination operand. + mad No explicit accumulator access + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 143 + Instruction Description + because this is a three-source + instruction. AccWrEn is allowed + for implicitly updating the + accumulator. + math No accumulator access, implicit + or explicit. + mov An accumulator can be a source + or destination operand but not + both. + movi Source operands cannot be + accumulators. + mul Source operands cannot be + accumulators. + not Source modifier is not allowed if + source is an accumulator. + or Source modifier is not allowed if + source is an accumulator. + pln Source operands cannot be + accumulators. + rndd No accumulator access, implicit + or explicit. + rnde No accumulator access, implicit + or explicit. + rndu No accumulator access, implicit + or explicit. + rndz No accumulator access, implicit + or explicit. + sad2 Source operands cannot be + accumulators. + sada2 Source operands cannot be + accumulators. + sel No restrictions. + shl Accumulator cannot be + destination, implicit or explicit. + shr No restrictions. + subb AccWrEn is required. The + accumulator is an implicit + destination and thus cannot be + an explicit destination operand. + xor Source modifier is not allowed if + source is an accumulator. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 144 + 6. Instruction Set Reference +This chapter describes the functions of instructions. Each instruction is sorted in alphabetical order +according to assembly language mnemonic. + + +6.1 Conventions +This section describes conventions used in instruction reference pages. +For each instruction that has source or destination types, a table lists the allowed type combinations and +may also indicate the processor generations that support certain combinations. A notation like *W +indicates that UW and W are both allowed. Multiple types listed together mean that any combination +(Cartesian product) of the listed types is allowed. +If a source operand is floating-point, all source operands must have the same floating-point data type. +Accumulator restrictions are described in the Accumulator Restrictions section and also appear in +instruction descriptions. + + +6.1.1 Pseudo Code Format +Instructions are explained in the following pseudo-code format that resembles the GEN assembly +instruction format. + [(pred)] opcode (exec_size) dst src0 [src1] + + +Square brackets “[ ]” indicate that a field is optional. Saturation modifiers and instruction options are +omitted for simplicity. + + +6.1.2 General Macros and Definitions +INST_MIN_SIZE is defined as a constant of 8 bytes. + #define INST_MIN_SIZE 8 // Instruction minimum size in bytes (for the compact +instruction format) + + +The floor function converts a floating point value to an integral floating point value. For a given floating +point value, from its closest two integral float values, floor returns the one that is closer to negative infinity. +For example, floor(1.3f) = 1.0f and floor(-1.3f) = -2.0f. + float floor(float g) + { + return maximum(any integral float f: f <= g) + } + + +The Condition function takes the conditional signals {SN, ZR, OF, IN, NC} of result, generates a Boolean +value according to a conditional evaluation controlled by the conditional modifier cmod, and returns the +Boolean. + Bool Condition(result, cmod) + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 145 + The ConditionNaN function takes the conditional signals {SN, ZR, OF, IN, NC, NS} of result, generates a +Boolean value according to a conditional evaluation controlled by the conditional modifier cmod, and +returns the Boolean. The only difference between Condition and ConditionNaN is that ConditionNaN uses +the NS (NaN of the second source) signal. + Bool ConditionNaN(result, cmod) + + +The Jump function jumps the instruction sequence from the current instruction location by InstCount 8- +byte units, where each 16-byte native instruction is two units and each 8-byte compact instruction is one +unit. If InstCount is positive and greater than zero, is an unconditional jump forward. If InstCount is +negative, is an unconditional jump backward. If InstCount is zero, IP stays on the current instruction in an +infinite loop. + void Jump(int InstCount) + { + IP = IP + (InstCount * INST_MIN_SIZE) + } + + + + +6.2 Evaluate Write Enable +The WrEn should be evaluated as below. +Note: MaskCtrl = NoMask (1) skips the check for PcIP[n] == ExIP before enabling a channel. + if ( MaskCtrl == 1 ) { + for ( n = 0; n < exec_size; n++ ) { + WrEn[n] = 1; + } + } + else { + for ( n = 0; n < exec_size; n++ ) { + if ( PcIP[n] == ExIP ) { + WrEn[n] = 1; + } + else { + WrEn[n] = 0; + } + } + } + + if ( PredCtrl != 0000b ) { + for ( n = 0; n < exec_size; n++ ) { + WrEn[n] = WrEn[n] & PMask[n]; + } + } + + for ( n = exec_size; n < 32; n++ ) { + WrEn[n] = 0; + } + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 146 + 6.3 Instruction Description +The rest of the chapter contains the description of instructions. + + +6.4 add – Addition + Opcode Instruction Description + 64 (0x40) add dst src0 src1 Add src0 and src1 storing the result in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Types Dst Type +*B, *W, *D *B, *W, *D +*B, *W, *D F + F F + DF DF + +Format: +[(pred)] add[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] add[.cmod] (exec_size) reg reg reg + [(pred)] add[.cmod] (exec_size) reg reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src0.chan[n] + src1.chan[n]; + } + } + + +Description: +The add instruction performs component-wise addition of src0 and src1 and stores the results in dst. +Addition of two floating-point numbers follows rules in add – Addition or add – Addition). +Note: Use a source modifier with add to implement subtraction. + +Floating-Point Addition of A (Column) and B (Row) in IEEE Mode + –inf –finite –denorm –0 +0 +denorm +finite +inf NaN + –inf –inf –inf –inf –inf –inf –inf –inf NaN NaN + –finite –inf * A A A A ** +inf NaN + –inf B B +inf NaN + –0/ –0/ +0/ +0/ + -denorm/ +denorm/ + -denorm^ -denorm^ + -finite^ -denorm^ + –denorm + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 147 + –inf B –0 +0 B +inf NaN + –0/ +0/ + -denorm^ +denorm + –0 + –inf B +0 +0 B +inf NaN + +0/ +0/ + -denorm^ +denorm + +0 + –inf B B +inf NaN + +0/ +0/ +0/ +0/ + +denorm/ +denorm^ +denorm^ +denorm/ + -denorm^ +finite^ + +denorm + +finite –inf ** A A A A *** +inf NaN + +inf NaN +inf +inf +inf +inf +inf +inf +inf NaN + NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN + Notes: + ^ Non zero results are applicable when denorm is enabled. + * Result can be { –finite}. + ** Result can be {–finite, –0, +0, +finite}. + *** Result can be { +finite}. + +Floating-Point Addition of A (Column) and B (Row) in ALT Mode + –fmax –finite –denorm –0 +0 +denorm +finite +fmax **** + –fmax –fmax –fmax –fmax –fmax –fmax –fmax –finite +0 + –finite –fmax * A A A A ** +fmax + –denorm –fmax B –0 –0 +0 +0 B +fmax + –0 –fmax B –0 –0 +0 +0 B +fmax + +0 –fmax B +0 +0 +0 +0 B +fmax + +denorm –fmax B +0 +0 +0 +0 B +fmax + +finite –finite ** A A A A *** +fmax + +fmax +0 +fmax +fmax +fmax +fmax +fmax +fmax +fmax + **** + Notes: + * Result can be { –fmax, –finite}. + ** Result can be {–finite, –0, +0, +finite}. + *** Result can be { +fmax, +finite}. + **** Result is undefined if A or B is {–inf, +inf, NaN}. + + + +6.5 addc – Integer Addition with Carry + Opcode Instruction Description + 78 (0x4E) addc dst src0 src1 Add 32-bit unsigned integers src0 and src1. Store the 32-bit result in dst. + Store the carry out (0 or 1) as a 32-bit value in the accumulator. + + +Pred Sat Cond Mod Src Mod + Y N Y N + + +Src Types Dst Type + UD UD + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 148 + Format: +[(pred)] addc[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] addc[.cmod] (exec_size) reg reg reg + [(pred)] addc[.cmod] (exec_size) reg reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src0.chan[n] + src1.chan[n]; + acc.chan[n] = carry(src0.chan[n] + src1.chan[n]); + } + } + + +Description: +The addc instruction performs component-wise addition of src0 and src1 and stores the results in dst; it +also stores the carry into acc. +If the operation produces a carry out, 0x00000001 is stored in acc, else 0x00000000 is stored in acc. +Restrictions: +AccWrEn is required. The accumulator is an implicit destination and thus cannot be an explicit destination +operand. + + +6.6 and – Logic And + Opcode Instruction Description + 5 (0x05) and dst src0 src1 Performing component-wise logic AND of src0 and src1 and storing the + results in dst. + + +Pred Sat Cond Mod Src Mod + Y N Y Y + + +Generation Src Types Dst Type + *B, *W, *D *B, *W, *D + +Format: +[(pred)] and[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] and[.cmod] (exec_size) reg reg reg + [(pred)] and[.cmod] (exec_size) reg reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src0.chan[n] & src1.chan[n]; + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 149 + } + } + + +Description: +The and instruction performs component-wise logic AND operation between src0 and src1 and stores the +results in dst. +Register source operands can use source modifiers: + +  Any source modifier is numeric, optionally changing a source value s to -s, abs(s), or -abs(s) before + the AND operation. +This operation does not produce sign or overflow conditions. Only the .e/.z or .ne/.nz conditional +modifiers should be used. + + +Restrictions: +Source modifier is not allowed if source is an accumulator. + + +6.7 asr – Arithmetic Shift Right + Opcode Instruction Description + 12 (0x0C) asr dst src0 src1 Arithmetic shift the bits in src0 right by the number of bits indicated in src1. + Store the result in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Generation Src Types Dst Type + *B, *W, *D *B, *W, *D + +Format: +[(pred)] asr[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] asr[.cmod] (exec_size) reg reg reg + [(pred)] asr[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.channel[n] ) { + shiftCnt = src1.chan[n] & 0x1F; // Always use low 5 bits for shift count. if +(src0.chan[n] >= 0) { + dst.chan[n] = src0.chan[n] >> shiftCnt; + } + else { + int maskLSB = pow(2, shiftCnt) – 1; + if ( maskLSB & src0.chan[n] == 0 ) { + dst.chan[n] = sign(src0.chan[n]) * ((abs)src0.chan[n] >> shiftCnt); + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 150 + } + else { + dst.chan[n] = sign(src0.chan[n]) * ((abs)src0.chan[n] >> shiftCnt) – 1; + } + } + } + } + + +Description: +Perform component-wise arithmetic right shift of the bits in src0 by the shift count indicated in src1, storing +the results in dst. If src0 has a signed type, insert copies of src0's sign bit in the number of MSBs +indicated by the shift count. Otherwise insert 0 bits. +The shift count is taken from the low five bits of src1, regardless of the src1 type and treated as an +unsigned integer in the range 0 to 31. +For positive values, this operation is src0 / 2shiftCount and for negative values, this operation is src0 / 2shiftCount - +1. +Note: If src0 is -1, the result is -1 regardless of the shift count. +Note: For unsigned src0 types, asr and shr produce the same result. + + +6.8 avg – Average + Opcode Instruction Description + 66 (0x42) avg dst src0 src1 Integer average of two source operands, rounding up. Store the result in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Types Dst Type +*B, *W, *D *B, *W, *D + +Format: +[(pred)] avg[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] avg[.cmod] (exec_size) reg reg reg + [(pred)] avg[.cmod] (exec_size) reg reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = (src0.chan[n] + src1.chan[n] + 1) >> 1; // Use arithmetic shift +right. + } + } + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 151 + Description: +The avg instruction performs component-wise integer average of src0 and src1 and stores the results in +dst. An integer average uses integer upward rounding. It is equivalent to increment one to the addition of +src0 and src1 and then apply an arithmetic right shift to this intermediate value. + + +6.9 bfe – Bit Field Extract + Opcode Instruction Description + 24 (0x18) bfe dst src0 src1 src2 Extract a bit field defined by src0 and src1 from src2 and store + in dst. + + +Pred Sat Cond Mod Src Mod + Y N N N + + +Src Type Dst Type + UD UD + D D + +Format: +[(pred)] bfe (exec_size) dst src0 src1 src2 + +Syntax: +[(pred)] bfe (exec_size) reg reg reg reg + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + UD width = src0.chan[n][4:0]; + UD offset = src1.chan[n][4:0]; + if ( width == 0 ) { + dst.chan[n] = 0x00000000; + } + else if ( (width + offset) < 32 ) { + dst.chan[n] = src2.chan[n] << (32 - width - offset); + if (src2 is signed) { + dst.chan[n] = dst.chan[n] >> (32 - width); // pad sign bit of dst.chan + } + else { + dst.chan[n] = dst.chan[n] >> (32 - width); // pad 0 + } + } + else { + if ( src2 is signed ) { + dst.chan[n] = src2.chan[n] >> offset; // pad sign bit + } + else { + dst.chan[n] = src2.chan[n] >> offset; // pad 0 + } + } + } + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 152 + } + + +Description: +Component-wise extract a bit field from src2 using the bit field width from src0 and the bit field offset from +src1. Store the extracted bit field value in the low bits of dst and sign extend (if D type) or zero extend (if +UD type). +The width and offset values are from the low five bits of src0 and src1 respectively, or src0 & 0x1f and +src1 & 0x1f. +If width is zero, the result is zero. +If offset + width > 32 then the extracted bit field is bits offset to 31 of src2, extracting only 32 - offset bits, +less than width as the bit field cannot extend past the MSB of the source value. Otherwise extract width +bits extending from bit positions offset to offset + width - 1. + + +Restrictions: +No accumulator access, implicit or explicit. +All three-source instructions have certain restrictions, described in Instruction Machine Formats. + + +6.9.1 bfi1 – Bit Field Insert 1 + Opcode Instruction Description + 25 (0x19) bfi1 dst src0 src1 Create a bit mask defined by src0 and src1 and store in dst. + + +Pred Sat Cond Mod Src Mod + Y N N N + + +Src Types Dst Type + UD UD + D D + +Format: +[(pred)] bfi1 (exec_size) dst src0 src1 + +Syntax: +[(pred)] bfi1 (exec_size) reg reg reg + [(pred)] bfi1 (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + UD width = src0.chan[n][4:0]; + UD offset = src1.chan[n][4:0]; + dst = ((1 << width) - 1) << offset; + } + } + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 153 + Description: +The bfi1 instruction is the first instruction in a two-instruction macro for bfi (Bit Field Insert). +The bfi1 instruction component-wise generates mask with control from src0 and src1 and stores the +results in dst. The mask is used in the bfi2 instruction to generate the final result of bfi. +Create a bit mask corresponding to the bit field width and offset in src0 and src1. Store the bit mask in +dst. The mask has all bits in the bit field set to 1 and all other bits as 0. +The width and offset values are from the low five bits of src0 and src1 respectively, or src0 & 0x1f and +src1 & 0x1f. +If width is zero, the result is zero. +The bfi macro has four source operands: src0 - bit field width in low five bits, src1 - bit field offset/starting +bit position in low five bits, src2 - bit field value to insert, using only the number of least significant bits +given by width in src0, and src3 - overall value into which the bit field is inserted, providing all bits other +than the inserted bits for the result value. + bfi dst src0 src1 src2 src3 + + // Translates to these two instructions: + bfi1 dst src0 src1 + bfi2 dst dst src2 src3 + + +Restrictions: +No accumulator access, implicit or explicit. + + +6.10 bfi2 – Bit Field Insert 2 + Opcode Instruction Description + 26 (0x1A) bfi2 dst src0 src1 src2 Extract a bit field defined by src0 and src1 from src2 and store + in dst. + + +Pred Sat Cond Mod Src Mod + Y N N N + + +Src Type Dst Type + UD UD + D D + +Format: +[(pred)] bfi2 (exec_size) dst src0 src1 src2 + +Syntax: +[(pred)] bfi2 (exec_size) reg reg reg reg + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + UD offset = LZD(reverse(src0.chan[n]))-1; + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 154 + // offset is the number of LSB zero bits below the bit mask which has all 1s. + // width (implied by the logic) is the number of 1 bits in the mask value, which +should be all 1s. + dst.chan[n] = ((src1.chan[n] << offset) & src0.chan[n]) | (src2.chan[n] & ! +src0.chan[n]); + } + + +Description: +The bfi2 instruction is the second instruction in a two-instruction macro for bfi (Bit Field Insert). +The bfi2 instruction component-wise performs the bitfield insert operation on src1 and src2 based on the +mask in src0. +Use the mask in src0 to take a bit field value from the low bits of src1 and combine it with the value from +src2 (so src2 provides all bits other than those masked out and replaced by the bit field value). Store the +result in dst. +The bfi macro has four source operands: src0 - bit field width in low five bits, src1 - bit field offset/starting +bit position in low five bits, src2 - bit field value to insert, using only the number of least significant bits +given by width in src0, and src3 - overall value into which the bit field is inserted, providing all bits other +than the inserted bits for the result value. + bfi dst src0 src1 src2 src3 + + // Translates to these two instructions: + bfi1 dst src0 src1 + bfi2 dst dst src2 src3 + + +Restrictions: +No accumulator access, implicit or explicit. +All three-source instructions have certain restrictions, described in Instruction Machine Formats. + + +6.11 bfrev – Reverse Bits + Opcode Instruction Description + 23 (0x17) bfrev dst src0 Reverse all bits in src0 and store in dst. + + +Pred Sat Cond Mod Src Mod + Y N N N + + +Src Type Dst Type + UD UD + +Format: +[(pred)] bfrev (exec_size) dst src0 + +Syntax: +[(pred)] bfrev (exec_size) reg reg + [(pred)] bfrev (exec_size) reg imm32 + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 155 + Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + for ( idx = 0; idx < 32; idx++ ) { + dst.chan[n][idx] = src0.chan[n][31-idx]; + } + } + } + + +Description: +The bfrev instruction component-wise reverses all the bits in src0 and stores the results in dst. +Restrictions: +No accumulator access, implicit or explicit. + + +6.12 brc – Branch Converging + Opcode Instruction Description + 35 (0x23) brc JIP UIP Redirect channel execution to the instruction referenced by UIP. + + +Pred Sat Cond Mod Src Mod + Y N N N + + +Src Types Dst Type + D + +Format: +[(pred)] brc (exec_size) JIP UIP + +Syntax: + [(pred)] brc (exec_size) imm16 imm16 + [(pred)] brc (exec_size) reg32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < 32; n++ ) { + if ( WrEn[n] ) { + PcIP[n] = IP + UIP; + } + else { + PcIP[n] = IP + 1; + } + } + if ( all PcIP != IP + 1 ) { // for all channels + Jump(IP + JIP); + } + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 156 + Description: +The brc instruction redirects the execution forward or backward to the instruction pointed by (current IP + +offset). The jump will occur if all channels are branched away. +UIP should reference the instruction where all channels are expected to come together. JIP should +reference the end of the innermost conditional block. + +Immediate Offset + Bits Description + 31:16 + UIP (Update Target Offset) + The relative offset in 64-bit units if a jump is taken for the channel. + Format = S15. + 15:0 + JIP (Jump Target Offset) + The relative offset in 64-bit units if a jump is taken for the instruction. + Format = S15. + + +Register Offset + Bits Description + 31:16 + UIP (Update Target Offset) + The relative offset in 64-bit units if a jump is taken for the channel. + Format = S15. + + 15:0 + JIP (Jump Target Offset) + The relative offset in 64-bit units if a jump is taken for the instruction. + Format = S15. + +In the architecture binary, JIP and UIP are at location src1 when immediates and at location src0 when +reg32, where reg32 is accessed as a scalar DWord containing both JIP and UIP. The null register must +be used (for example, by the assembler) as dst. When offsets are immediate, src0 must be null. +Restrictions: +A brc instruction must use the Switch instruction option. +Erratum: brc instructions cannot be used with offsets in registers, but only with immediate offsets. +Erratum: brc instructions cannot be used within if-endif or if-else-endif conditional blocks. + + +6.13 brd – Branch Diverging + Opcode Instruction Description + 33 (0x21) brd JIP Redirect program execution to the instruction referenced by JIP. + + +Pred Sat Cond Mod Src Mod + Y N N N + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 157 + Src Types Dst Type + D + +Format: +[(pred)] brd (exec_size) JIP + +Syntax: + [(pred)] brd (exec_size) imm16 + [(pred)] brd (exec_size) reg32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < 32; n++ ) { + if ( WrEn[n] ) { + PcIP[n] = IP + JIP; + } + else { + PcIP[n] = IP + 1; + } + } + + if ( any PcIP == ExIP + JIP ) { // any channel + Jump(ExIP + JIP); + } + + +Description: +The brd instruction redirects the execution forward or backward to the instruction pointed by (current IP + +offset). The jump will occur if any channels are branched away. + +Immediate Offset ] + Bits Description + 31:16 Reserved. MBZ. + 15:0 + JIP (Jump Target Offset) + The relative offset in 64-bit units if a jump is taken for the instruction. + Format = S15. + + +Register Offset + Bits Description + 31:16 Reserved. MBZ. + 15:0 + JIP (Jump Target Offset) + The relative offset in 64-bit units if a jump is taken for the instruction. + Format = S15. + +In GEN binary, JIP is at location src1 when immediate and at location src0 when reg32, where reg32 is +accessed as a scalar DWord. The null register must be used at dst locations. +Restrictions: + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 158 + A brd instruction must use the Switch instruction option. +Erratum: brd instructions cannot be used with offsets in registers, but only with immediate offsets. + + +6.14 break – Break + Opcode Instruction Description + 40 (0x28) break JIP UIP Terminate enabled execution channels and conditionally break out from the + inner most loop. + + +Pred Sat Cond Mod Src Mod + Y N N N + +Format: +[(pred)] break (exec_size) JIP UIP + +Syntax: +[(pred)] break (exec_size) imm16 imm16 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.channel[n] ) { + PcIP[n] = IP + UIP; + else { + PcIP[n] = IP + 1; + } + } + + if ( PcIP != (IP + 1) ) { // all channels + Jump(IP + JIP); + } + + +Description: +The break instruction is used to early-out from the inner most loop, or early out from the inner most switch +block. +When used in a loop, upon execution, the break instruction terminates the loop for all execution channels +enabled. If all the enabled channels hit the break instruction, jump to the instruction referenced by JIP. +JIP should be the offset to the end of the inner most conditional or loop block, UIP should be the offset to +the while instruction of the loop block. +]: The following table describes the two 16-bit instruction pointer offsets. Both the JIP and UIP are signed +16-bit numbers, added to IP pre-increment. In GEN binary, JIP and UIP are at location src1 and must be +of type W (signed word integer). + +Relative Instruction Offsets ] + Bits Description +31:16 + UIP (Update Target Offset). The jump distance in number of eight-byte units if a jump is taken for the + channel. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 159 + Bits Description + Format = S15. +15:0 + JIP (Jump Target Offset). The jump distance in number of eight-byte units if a jump is taken for the + instruction. + Format = S15. + + + +If SPF is ON, the UIP must be used to update IP; JIP is not used in this case. +Restrictions: +The execution size must be the same for the while, break, and cont instructions of the same code block. + + +6.15 call – Call + Opcode Instruction Description + 44 (0x2C) call dst JIP Subroutine call. + + +Pred Sat Cond Mod Src Mod + Y N N N + + +Src Types Dst Type + D, UD + +Format: +[(pred)] call (exec_size) dst JIP + +Syntax: +[(pred)] call (exec_size) reg imm16 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if (WrEn.chan[n] ) { + PcIP[n] = IP + JIP; + CallMask[n] = 1; + } + else { + PcIP[n] = IP + 1; + CallMask[n] = 0; + } + } + + if ( PcIP[n] != (IP + 1) ) { // any channel jumped + dst.chan[0] = IP + 1; + dst.chan[1] = CallMask; + Jump(IP + JIP); + } + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 160 + Description: +The call instruction jumps to a subroutine. It can be predicated or non-predicated. If non-predicated, all +enabled channels jump to the subroutine. If predicated, only the channels enabled by PMask jump to the +subroutine; the rest of the channels move to the next instruction after the call instruction. If none of the +channels jump into the subroutine, the call instruction is treated as a nop. +In case of a jump, the call instruction stores the return IP onto the first DWord of the destination register +and stores the CallMask in the second DWord of the destination register. +When SPF is on, the predication control must be scalar. +The following table describes JIP, the jump offset, for. JIP must be a signed immediate operand. When a +jump occurs, this value is added to IP pre-increment. + +Immediate Instruction Offset + Bits Description +31:16 Reserved: MBZ + 15:0 + JIP (Jump Instruction Count). The jump distance in number of 64-bit units if a jump is taken for the + instruction. + Format = S15. + +Restrictions: +The call instruction must have DWord source and destination type, and the destination must be QWord +aligned. +] The source0 regioning control must be <2;2,1>. +The execution size must be 2. +Workaround: A call instruction before a send with EOT should: + +  Have no predication. +  Should use {NoMask}. +  Should specify for the destination any general register that is not part of the final send. +  Should specify a JIP value referencing the send instruction that has EOT. + +Example: + call (2) r1 0x2 {NoMask} + send ... {EOT} + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 161 + 6.16 cbit – Count Bits Set + Opcode Instruction Description + 77 (0x4D) cbit dst src0 Count the number of bits set (1) in src0 and store that count in dst. + + +Pred Sat Cond Mod Src Mod + Y N N N + + + Src Type Dst Type +UB, UW, UD UD + +Format: +[(pred)] cbit (exec_size) dst src0 + +Syntax: +[(pred)] cbit (exec_size) reg reg + [(pred)] cbit (exec_size) reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + UD cnt = 0; + UD val = src0.chan[n]; + while ( val ) { + if ( val & 1 ) { + cnt ++; + } + val = val >> 1; + } + dst.chan[n] = cnt; + } + } + + +Description: +The cbit instruction counts component-wise the total bits set in src0 and stores the resulting counts in dst. +Restrictions: +No accumulator access, implicit or explicit. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 162 + 6.17 cmp – Compare + Opcode Instruction Description + 16 (0x10) cmp.cmod dst src0 src1 Compare src0 and src1 as specified by the conditional modifier and store + the resulting flags in dst and in the flag register. + + +Pred Sat Cond Mod Src Mod + Y N Y Y + + +Src Types Dst Type +*B, *W, *D *B, *W, *D +*B, *W, *D F + F F + DF DF + +Format: +[(pred)] cmp[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] cmp[.cmod] (exec_size) reg reg reg + [(pred)] cmp[.cmod] (exec_size) reg reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + bitMask[n] = 0; + if ( WrEn.chan[n] ) { + results[n] = src0.chan[n] - src1.chan[n]; + bitMask[n] = Condition(results[n]); + dst.chan[n] = bitMask[n]; // All bits for dst channel + } + } + flag# = bitMask; + + +Description: +The cmp instruction performs component-wise comparison of src0 and src1 and stores the results in the +selected flag register and in dst. It takes component-wise subtraction of src0 and src1, evaluating the +conditional code (excluding NS signal) based on the conditional modifier, and storing the conditional bits +in bit-packed form in the destination flag register and all bits of dst channels. If the dst is not null, for the +enabled channels, then all bits of the destination channel will contain the flag value for the channel. When +the instruction operates on packed word format, one general register may store up to 16 such comparison +results. In DWord format, one general register may store up to 8 results. +A conditional modifier must be specified; the conditional modifier field cannot be 0000b. The comparison +does not use the NS (NaN source) signals, as described in the Creating Conditional Flags section. +Accordingly the conditional modifier should not be .u (unordered). +For each enabled channel 0b or 1b is assigned to the appropriate flag bit and 0/all zeros or all ones (e.g, +byte 0xFF, word 0xFFFF, DWord 0xFFFFFFFF) is assigned to dst. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 163 + When any source type is floating-point, the cmp instruction obeys the rules described in the tables in the +Floating Point Modes section of the Data Types chapter. +Restrictions: +Accumulator cannot be destination, implicit or explicit. The destination must be a general register or the +null register. +A SIMD16 instruction is not allowed for DWord data types. Use two SIMD8 instructions. +If the destination is the null register, the {Switch} instruction option must be used. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 164 + 6.18 cmpn – Compare NaN + Opcode Instruction Description + 17 (0x11) cmpn.cmod dst src0 src1 Compare src0 and src1 with a special NaN comparison as specified by the + conditional modifier and store the resulting flags in dst and in the flag + register. + + +Pred Sat Cond Mod Src Mod + Y N Y Y + + +Src Types Dst Type +*B, *W, *D *B, *W, *D +*B, *W, *D F + F F + DF DF + +Format: +[(pred)] cmpn[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] cmpn[.cmod] (exec_size) reg reg reg + [(pred)] cmpn[.cmod] (exec_size) reg reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + bitMask[n] = 0; + if ( WrEn.chan[n] ) { + results[n] = src0.chan[n] - src1.chan[n]; + bitMask[n] = ConditionNaN(results[n]); + dst.chan[n][0] = bitMask[n]; // All bits for dst channel + } + } + flag# = bitMask; + + +Description: +The cmpn instruction performs component-wise special-NaN comparison of src0 and src1 and stores the +results in the selected flag register and in dst. It takes component-wise subtraction of src0 and src1, +evaluating the conditional signals including NS based on the conditional modifier, and storing the +conditional flag bits in bit-packed form in the destination flag register and all bits of dst channels. If the dst +is not null, for the enabled channels, then all bits of the destination channel will contain the flag value for +the channel. When the instruction operates on packed word format, one general register may store up to +16 such comparison results. In DWord format, one general register may store up to 8 results. +A conditional modifier must be specified; the conditional modifier field cannot be 0000b. More information +about the conditional signals used is in the Creating Conditional Flags section. +For each enabled channel 0b or 1b is assigned to the appropriate flag bit and 0/all zeros or all ones (e.g, +byte 0xFF, word 0xFFFF, DWord 0xFFFFFFFF) is assigned to dst. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 165 + This instruction is similar to cmp. The only difference is that if the second source operand src1 is a NaN, +the result for any conditional modifier except .nz is true (see the Min/Max of Floating Point Numbers +section for details). +Restrictions: +Accumulator cannot be destination, implicit or explicit. The destination must be a general register or the +null register. +]: A SIMD16 instruction is not allowed for DWord data types. Use two SIMD8 instructions. +]: If the destination is the null register, the {Switch} instruction option must be used. + + +6.19 cont – Continue + Opcode Instruction Description + 41 (0x29) cont JIP UIP Temporarily disable enabled execution channels for the remainder of the + inner most loop and conditionally jump to the last instruction (while) of the + loop. + + +Pred Sat Cond Mod Src Mod + Y N N N + +Format: +[(pred)] cont (exec_size) JIP UIP + +Syntax: +:[(pred)] cont (exec_size) imm16 imm16 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.channel[n] ) { + if ( PMask[n] ) { // PMask is for all channels enabled for the cont instruction. + PcIP[n] = IP + UIP; + } + else { + PcIP[n] = IP + 1; + } + } + } + for ( n = exec_size; n < 32; n++ ) { + PcIP[n] = IP + 1; + } + if ( PcIP != (IP + 1) ) { // all channels true + Jump(IP + JIP); + } + + +Description: +The cont instruction disables execution for the subset of channels for the remainder of the current loop +iteration. Channels remain disabled until right before the while instuction or right before the condition +check code block for the while instruction. If all enabled channels hit this instruction, jump to the +instruction referenced by JIP where execution continues. + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 166 + UIP should always reference the loop's associated while instruction. JIP should point to the last +instruction of the inner most conditional block if the cont instruction is inside a conditional block. In case of +the break instruction directly under the loop, the JIP and the UIP are the same. +The following table describes the two 16-bit instruction pointer offsets. Both the JIP and UIP are signed +16-bit numbers, added to IP pre-increment. In GEN binary, JIP and UIP are at location src1 and must be +of type W (signed word integer). + +Relative Instruction Offsets + Bits Description +31:16 + UIP (Update Target Offset). The jump distance in number of eight-byte units if a jump is taken for the + channel. + Format = S15. +15:0 + JIP (Jump Target Offset). The jump distance in number of eight-byte units if a jump is taken for the + instruction. + Format = S15. + + + +6.20 dp2 – Dot Product 2 + Opcode Instruction Description + 87 (0x57) dp2 dst src0 src1 Perform two-wide dot product using the first two elements of each four-tuple + from src0 and src1 and store the four-wide replicated results in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Types Dst Type + F F + +Format: +[(pred)] dp2[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] dp2[.cmod] (exec_size) reg reg reg + [(pred)] dp2[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n += 4 ) { + fTmp = src0.chan[n] * src1.chan[n] + + src0.chan[n+1] * src1.chan[n+1]; + if ( WrEn.chan[n] ) dst.chan[n] = fTmp; + if ( WrEn.chan[n+1] ) dst.chan[n+1] = fTmp; + if ( WrEn.chan[n+2] ) dst.chan[n+2] = fTmp; + if ( WrEn.chan[n+3] ) dst.chan[n+3] = fTmp; + } + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 167 + Description: +The dp2 instruction performs a two-wide dot product on four-tuple vector basis and storing the same +scalar result per four tuple to all four channels in dst. This instruction is similar to dp4 except that every +third and fourth element of src0 (post-source-swizzle if present) are not involved in the computation. +The dot product of two vectors of equal length is the sum of the products of each pair of corresponding +elements. +The dp4 instruction includes all four elements of each vector in the dot product. The dp3 instruction +includes the first three elements of each vector in the dot product. +Restrictions: +Execution size cannot be less than 4. +Horizontal strides must be 1. +Source operands cannot be accumulators. + + +6.21 dp3 – Dot Product 3 + Opcode Instruction Description + 86 (0x56) dp3 dst src0 src1 Perform three-wide dot product using the first three elements of each four- + tuple from src0 and src1 and store the four-wide replicated results in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Types Dst Type + F F + +Format: +[(pred)] dp3[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] dp3[.cmod] (exec_size) reg reg reg + [(pred)] dp3[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n += 4 ) { + fTmp = src0.chan[n] * src1.chan[n] + + src0.chan[n+1] * src1.chan[n+1]; + + src0.chan[n+2] * src1.chan[n+2]; + if ( WrEn.chan[n] ) dst.chan[n] = fTmp; + if ( WrEn.chan[n+1] ) dst.chan[n+1] = fTmp; + if ( WrEn.chan[n+2] ) dst.chan[n+2] = fTmp; + if ( WrEn.chan[n+3] ) dst.chan[n+3] = fTmp; + } + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 168 + Description: +The dp3 instruction performs a three-wide dot product on four-tuple vector basis and storing the same +scalar result per four tuple to all four channels in dst. This instruction is similar to dp4 except that every +fourth element of src0 (post-source-swizzle if present) is not involved in the computation. +The dot product of two vectors of equal length is the sum of the products of each pair of corresponding +elements. +The dp4 instruction includes all four elements of each vector in the dot product. The dp2 instruction +includes the first two elements of each vector in the dot product. +Restrictions: +Execution size cannot be less than 4. +Horizontal strides must be 1. +Source operands cannot be accumulators. + + +6.22 dp4 – Dot Product 4 + Opcode Instruction Description + 84 (0x54) dp4 dst src0 src1 Perform four-wide dot product of src0 and src1 and store the four-wide + replicated results in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Types Dst Type + F F + +Format: +[(pred)] dp4[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] dp4[.cmod] (exec_size) reg reg reg + [(pred)] dp4[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n += 4 ) { + fTmp = src0.chan[n] * src1.chan[n] + + src0.chan[n+1] * src1.chan[n+1] + + src0.chan[n+2] * src1.chan[n+2] + + src0.chan[n+3] * src1.chan[n+3]; + if ( WrEn.chan[n] ) dst.chan[n] = fTmp; + if ( WrEn.chan[n+1] ) dst.chan[n+1] = fTmp; + if ( WrEn.chan[n+2] ) dst.chan[n+2] = fTmp; + if ( WrEn.chan[n+3] ) dst.chan[n+3] = fTmp; + } + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 169 + Description: +The dp4 instruction performs a four-wide dot product on four-tuple vector basis and storing the same +scalar result per four tuple to all four channels in dst. +The dot product of two vectors of equal length is the sum of the products of each pair of corresponding +elements. +Restrictions: +Execution size cannot be less than 4. +Horizontal strides must be 1. +Source operands cannot be accumulators. + + +6.23 dph – Dot Product Homogeneous + Opcode Instruction Description + 85 (0x55) dph dst src0 src1 Perform four-wide homogeneous dot product of src0 and src1 and store the + four-wide replicated results in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Types Dst Type + F F + +Format: +[(pred)] dph[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] dph[.cmod] (exec_size) reg reg reg + [(pred)] dph[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n += 4 ) { + fTmp = src0.chan[n] * src1.chan[n] + + src0.chan[n+1] * src1.chan[n+1] + + src0.chan[n+2] * src1.chan[n+2] + + src1.chan[n+3]; // Use 1.0f in place of src0.chan[n+3]. + if ( WrEn.chan[n] ) dst.chan[n] = fTmp; + if ( WrEn.chan[n+1] ) dst.chan[n+1] = fTmp; + if ( WrEn.chan[n+2] ) dst.chan[n+2] = fTmp; + if ( WrEn.chan[n+3] ) dst.chan[n+3] = fTmp; + } + + +Description: +The dph instruction performs a four-wide homogeneous dot product on four-tuple vector basis and storing +the same scalar result per four tuple to all four channels in dst. This instruction is similar to dp4 except +that every fourth element of src0 (post-source-swizzle if present) is forced to 1.0f. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 170 + Use the dp4 instruction to do a four-wide dot product that includes all elements of src0 and src1. +Restrictions: +Execution size cannot be less than 4. +Horizontal strides must be 1. +Source operands cannot be accumulators. + + +6.24 else – Else + Opcode Instruction Description + 36 (0x24) else JIP An optional statement within an if/else/endif block of code. + + +Pred Sat Cond Mod Src Mod + N N N N + +Format: +else (exec_size) JIP + +Syntax: +else (exec_size) imm16 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < 32; n++ ) { + if ( WrEn.channel[n] ) { + PcIP[n] = IP + JIP; + } + } + if ( PcIP != ( IP + 1) ) { // for all channels + Jump(IP + JIP); + } + + +Description: +The else instruction is an optional statement within an if/else/endif block of code. It restricts execution +within the else/endif portion to the opposite set of channels enabled under the if/else portion. Channels +which were inactive before entering the if/endif block remain inactive throughout the entire block. +All enabled channels upon arriving at the else instruction are redirected to the matching endif. If all +channels are redirected (by else or before else), a relative jump is performed to the location specified by +JIP. The jump target should be the the matching endif instruction for that conditional block. + The following table describes the 16-bit JIP. In GEN binary, JIP is at location src1 and must be of type W +(signed word integer). JIP must be an immediate operand, it is a signed 16-bit number and is intended to +be forward referencing. This value is added to IP pre-increment. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 171 + Relative Instruction Offset + Bits Description +31:16 Reserved: MBZ. + 15:0 + JIP (Jump Target Offset). The jump distance in number of eight-byte units if a jump is taken for the + instruction. + Format = S15. + +Restrictions: +Predication is not allowed. +The execution size must be the same for the if, else, and endif instructions of the same code block. + + +6.25 endif – End If + Opcode Instruction Description + 37 (0x25) endif JIP Restore execution to the channels that were active prior to the if/else/endif + block. Jump to next hop point if all channels are disabled. + + +Pred Sat Cond Mod Src Mod + N N N N + +Format: +endif JIP + +Syntax: +endif (exec_size) imm16 + +Pseudocode: +Evaluate(WrEn); + if ( WrEn == 0 ) { // all channels false + Jump(IP + JIP); + } + + +Description: +The endif instruction terminates an if/else/endif block of code. It restores execution to the channels that +were active prior to the if/else/endif block. +The endif instruction is also used to hop out of nested conditionals by jumping to the end of the next outer +conditional block when all channels are disabled. +The following table describes the 16-bit JIP. In GEN binary, JIP is at location src1 and must be of type W +(signed word integer). JIP must be an immediate operand, it is a signed 16-bit number. This value is +added to IP pre-increment. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 172 + Relative Instruction Offset + Bits Description +31:16 Reserved: MBZ. + 15:0 + JIP (Jump Target Offset). The jump distance in number of eight-byte units if a jump is taken for the + instruction. + Format = S15. + + + + +Restrictions: +Predication is not allowed. +The execution size must be the same for the if, else, and endif instructions of the same code block. + + +6.26 f16to32 – Half Precision Float to Single Precision Float + Opcode Instruction Description + 20 (0x14) f16to32 dst src0 Convert a 16-bit half precision floating-point value to a 32-bit Float value and + store in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Type Dst Type + W F + +Format: +[(pred)] f16to32[.cmod] (exec_size) dst src0 + +Syntax: +[(pred)] f16to32[.cmod] (exec_size) reg reg + [(pred)] f16to32[.cmod] (exec_size) reg imm16 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = convert half precision float to single precision +float(src0.chan[n]); + } + } + + +Description: +The f16to32 instruction converts the half precision float in src0 to single precision float and storing in dst. +Because this instruction does not have a 16-bit floating-point type, the source data type must be Word +(W). The destination type must be F (Float). + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 173 + Restrictions: +The FP Mode (Single Precision Floating Point Mode in cr0) must be IEEE mode. +No accumulator access, implicit or explicit. + +Floating-Point Conversion in IEEE mode +Half Precision Float to Single Precision Float ] +Half Precision Float Single Precision Float + -inf -inf + -finite -finite + -denorm -finite + -0 -0 + +0 +0 + +denorm +finite + +finite +finite + +inf +inf + NaN NaN + + + +6.27 f32to16 – Single Precision Float to Half Precision Float + Opcode Instruction Description + 19 (0x13) f32to16 dst src0 Convert a 32-bit Float value to a 16-bit half precision floating-point value and + store in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Type Dst Type + F W + +Format: +[(pred)] f32to16[.cmod] (exec_size) dst src0 + +Syntax: +[(pred)] f32to16[.cmod] (exec_size) reg reg + [(pred)] f32to16[.cmod] (exec_size) reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = convert single precision float to half precision +float(src0.chan[n]); + } + } + + +Description: +The f32to16 instruction converts the single precision float in src0 to half precision float and storing in the +lower word of each channel in dst. + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 174 + Because this instruction does not have a 16-bit floating-point type, the destination data type must be +Word (W). +Restrictions: +The destination must be DWord-aligned and specify a horizontal stride (HorzStride) of 2. The 16-bit result +is stored in the lower word of each destination channel and the upper word is not modified. +The FP Mode (Single Precision Floating Point Mode in cr0) must be IEEE mode. +No accumulator access, implicit or explicit. + +Floating-Point Conversion in IEEE mode +Single Precision Float to Half Precision Float ] +Single Precision Float Half Precision Float + -inf -inf + -finite -finite/-denorm/-0 + -denorm -0 + -0 -0 + +0 +0 + +denorm +0 + +finite +finite/+denorm/+0 + +inf +inf + NaN NaN + + + +6.28 fbh – Find First Bit from MSB Side + Opcode Instruction Description + 75 (0x4B) fbh dst src0 Find the first significant bit searching from the high bits in src0 and store the + result in dst. + + +Pred Sat Cond Mod Src Mod + Y N N N + + +Src Type Dst Type + D, UD UD + +Format: +[(pred)] fbh (exec_size) dst src0 + +Syntax: +[(pred)] fbh (exec_size) reg reg + [(pred)] fbh (exec_size) reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + UD cnt = 0; + if ( src0 is unsigned ) { + UD udScalar = src0.chan[n]; + while ( (udScalar & (1 << 31)) == 0 && cnt != 32 ) { + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 175 + cnt ++; + udScalar = udScalar << 1; + } + if ( src0.chan[n] == 0x00000000 ) { + dst.chan[n] = 0xFFFFFFFF; + } + else { + dst.chan[n] = cnt; + } + } + else { // src0 is signed. + D dScalar = src0.chan[n]; + bit cval = dScalar[31]; + while ((dScalar & (1 << 31)) == cval && cnt != 32 ) { + cnt ++; + dScalar = dScalar << 1; + } + if ( (src0.chan[n] == 0xFFFFFFFF) || (src0.chan[n] == 0x00000000) ) { + dst.chan[n] = 0xFFFFFFFF; + } + else { + dst.chan[n] = cnt; + } + } + } + } + + +Description: +If src0 is unsigned, the fbh instruction counts component-wise the leading zeros from src0 and stores the +resulting counts in dst. +If src0 is signed and positive, the fbh instruction counts component-wise the leading zeros from src0 and +stores the resulting counts in dst. +If src0 is signed and negative, the fbh instruction counts component-wise the leading ones from src0 and +stores the resulting counts in dst. +Special Cases: +If src0 is zero, store 0xFFFFFFFF in dst. +If src0 is signed and is -1 (0xFFFFFFFF), store 0xFFFFFFFF in dst. +Restrictions: +No accumulator access, implicit or explicit. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 176 + 6.29 fbl – Find First Bit from LSB Side + Opcode Instruction Description + 76 (0x4C) fbl dst src0 Find the first 1 bit searching from the low bits in src0 and store the result in + dst. + + +Pred Sat Cond Mod Src Mod + Y N N N + + +Src Type Dst Type + UD UD + +Format: +[(pred)] fbl (exec_size) dst src0 + +Syntax: +[(pred)] fbl (exec_size) reg reg + [(pred)] fbl (exec_size) reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + UD cnt = 0; + UD udScalar = src0.chan[n]; + while ( (udScalar & 1) == 0 && cnt != 32 ) { + cnt ++; + udScalar = udScalar >> 1; + } + if ( src0.chan[n] == 0x00000000 ) { + dst.chan[n] = 0xFFFFFFFF; + } + else { + dst.chan[n] = cnt; + } + } + } + + +Description: +The fbl instruction counts component-wise the number of LSB 0 bits before the first 1 bit in src0, storing +that number in dst. If src0 contains no 1 bits, store 0xFFFFFFFF in dst. +Restrictions: +No accumulator access, implicit or explicit. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 177 + 6.30 frc – Fraction + Opcode Instruction Description + 67 (0x43) frc dst src0 Truncate toward minus infinity fraction part of src0 and store in dst. + + +Pred Sat Cond Mod Src Mod + Y N Y Y + + +Src Type Dst Type + F F + +Format: +[(pred)] frc[.cmod] (exec_size) dst src0 + +Syntax: +[(pred)] frc[.cmod] (exec_size) reg reg + [(pred)] frc[.cmod] (exec_size) reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src0.chan[n] - floor(src0.chan[n]); + } + } + + +Description: +The frc instruction computes, component-wise, the truncate-to-minus-infinity fractional values of src0 and +stores the results in dst. The results, in the range of [0.0, 1.0], are the fractional portion of the source +data. The result is in the range [0.0, 1.0] irrespective of the rounding mode. +Floating-point fraction computation follows the rules in the following tables, based on the current floating- +point mode. + +Floating-Point Fraction Computation in IEEE mode + src0 -inf -finite -denorm -0 +0 +denorm +finite +inf NaN + dst NaN * +0 +0 +0 +0 * NaN NaN +Notes: + * Result is in the range [+0.0, 1.0), not including 1.0. + +Floating-Point Fraction Computation in ALT mode + src0 -fmax -finite -denorm -0 +0 +denorm +finite +fmax ** + dst +0 * +0 +0 +0 +0 * +0 +Notes: + * Result is in the range [+0.0, 1.0), not including 1.0. + ** Result is undefined if src0 is {–inf, +inf, or NaN}. + +Restrictions: + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 178 + Erratum: When the Rounding Mode in cr0.0 is Round Down, the result from frc must be negated to bring +it into the range [0.0, 1.0) not including 1.0. +Workaround: When the Rounding Mode in cr0.0 is not Round Down, the result from frc must be followed +by compare and select instructions to avoid a result of 1.0. Those latter instructions must use the :ud +type. For example: + cmp.ne.f0.0 null r4:ud 0x3f800000:ud + (f0.0)sel r5:f r4:ud 0x3f7fffff:ud + + + + +6.31 halt – Halt + Opcode Instruction Description + 42 (0x2A) halt JIP UIP Temporarily suspend execution for all enabled execution channels. + + +Pred Sat Cond Mod Src Mod + Y N N N + +Format: +[(pred)] halt (exec_size) JIP UIP + +Syntax: +[(pred)] halt (exec_size) imm16 imm16 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < 32; n++ ) { + if ( WrEn.channel[n] ) { + PcIP[n] = IP + UIP; + else { + PcIP[n] = IP + 1; + } + } + + if ( PcIP != (IP + 1) ) { // for all channels + Jump(IP + JIP); + } + + +Description: +The halt instruction temporarily suspends execution for all enabled compute channels. Upon execution, +the enabled channels are sent to the instruction at (IP + UIP), if all channels are enabled at HALT, jump to +the instruction at (IP + JIP). +If the halt instruction is not inside any conditional code block, the values of JIP and UIP should be the +same. If the halt instruction is inside a conditional code block, the UIP should be the end of the program +and the JIP should be the end of the inner most conditional code block. +The following table describes the two 16-bit instruction pointer offsets. Both the JIP and UIP are signed +16-bit numbers, added to IP pre-increment. In GEN binary, JIP and UIP are at location src1 and must be +of type W (signed word integer). + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 179 + Relative Instruction Offsets + Bits Description +31:16 + UIP (Update Target Offset). The jump distance in number of eight-byte units if a jump is taken for the + channel. + Format = S15. +15:0 + JIP (Jump Target Offset). The jump distance in number of eight-byte units if a jump is taken for the + instruction. + Format = S15. + + + +If SPF is ON, the UIP must be used to update IP; JIP is not used in this case. +Restrictions: +dst and src0 must be NULL. +Workaround:: When SPF is ON, the JIP must point to a nop instruction. + + +6.32 if – If + Opcode Instruction Description + 34 (0x22) if JIP UIP Indicate the start of an if/else/endif block of code. + + +Pred Sat Cond Mod Src Mod + Y N N N + +Format: +[(pred)] if (exec_size) JIP UIP + +Syntax: +[(pred)] if (exec_size) imm16 imm16 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < 32; n++ ) { + if ( WrEn.channel[n] == 0 ) { + PcIP[n] = IP + JIP; + } + else { + PcIP[n] = IP + 1; + } + } + + if ( PcIP != (IP + 1) ) { // for all channels + Jump(IP + JIP); + } + + +Description: + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 180 + An if instruction starts an if/endif or an if/else/endif block of code. It restricts execution within the +conditional block to only those channels that were enabled via the predicate control. +Each if instruction must have a matching endif instruction and may have up to one matching else +instruction before the matching endif. +If all channels are inactive (for the if/endif or if/else/endif block), a jump is performed to the instruction +referenced by JIP. This jump must be to right after the matching else instruction when present, or +otherwise to the matching endif instruction of the conditional block. +The following table describes the two 16-bit instruction pointer offsets. Both the JIP and UIP are signed +16-bit numbers, added to IP pre-increment. In GEN binary, JIP and UIP are at location src1 and must be +of type W (signed word integer). + +Relative Instruction Offsets + Bits Description +31:16 + UIP (Update Target Offset). The jump distance in number of eight-byte units if a jump is taken for the + channel. + Format = S15. +15:0 + JIP (Jump Target Offset). The jump distance in number of eight-byte units if a jump is taken for the + instruction. + Format = S15. + +If SPF is ON, the UIP must be used to update IP; JIP is not used in this case. +Restrictions: +The execution size must be the same for the if, else, and endif instructions of the same code block. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 181 + 6.33 illegal – Illegal + Opcode Instruction Description + 0 (0x0) illegal Signal an illegal opcode exception, possibly transferring to the System + Routine. If the exception is disabled, perform no operation. + + +Pred Sat Cond Mod Src Mod + N N N N + +Format: +illegal + +Syntax: +illegal + +Pseudocode: + { + Set the Illegal Opcode Exception Status bit in cr0.1. + if ( Illegal Opcode Exception Enable is set in cr0.1 ) { + Transfer control to the System Routine (return address to AIP, IP = SIP). + } + } + + +Description: +The Illegal Opcode Exception Enable flag in cr0.1 is normally set so the normal processing of an illegal +opcode is to transfer control to the System Routine. +Instruction dispatch treats any unused 8-bit opcode (including bit 7 of the instruction, reserved for future +opcode expansion) as if it is the illegal opcode. +The illegal opcode is zero because that byte value is more likely than most to be read via a wayward +instruction pointer. +The illegal instruction is an instruction only in the same way that a NULL pointer in software is a pointer. +Both are special values indicating invalid instances. +Restrictions: +The illegal instruction takes no instruction options. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 182 + 6.34 jmpi – Jump Indexed + Opcode Instruction Description + 32 (0x20) jmpi index Redirect program execution based on an index relative to the post- + incremented instruction pointer. + + +Pred Sat Cond Mod Src Mod + Y N N N + + +Src Type Dst Type + D + +Format: +[(pred)] jmpi (1) index {NoMask} + +Syntax: +[(pred)] jmpi (1) reg32 {NoMask} + [(pred)] jmpi (1) imm32 {NoMask} + +Pseudocode: +Evaluate(WrEn); + if ( WrEn != 0 ) { + Jump(IP + 1 + index ); // IP + 1 is a pseudocode idiom for the IP of the following +instruction. + } + + +Description: +The jmpi instruction redirects program execution to an index offset relative to the post-incremented +instruction pointer. The index is a signed integer value, with positive or zero integers for forward jumps, +and negative integers for backward jumps. +Note: Unlike other flow control instructions, the offset used by jmpi is relative to the incremented +instruction pointer rather than the IP value for the instruction itself. +In GEN binary, index is at location src1. The ip register must be put (for example, by the assembler) at the +dst and src0 locations. +Predication is allowed to provide conditional jump with a scalar condition. As the execution size is 1, the +first channel of PMASK (flags post prediction control and negate) is used to determine whether the jump +is taken or not. If the condition is false, the jump is not taken and execution continues with the next +instruction. + +Index + Bits Description +31:16 Reserved: MBZ +15:0 + index (Jump Index) + This field specifies the jump distance in number of 64-bit units if a jump is taken for the instruction. + Format = S15. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 183 + Restrictions: +The execution size must be 1. +The {NoMask} instruction option must be specified. +The index data type must be D (Signed DWord Integer). +Programming Notes: +An index of 0 does nothing, continuing execution with the next instruction. +An index of -2 (if the jmpi instruction is in native format) or -1 (if the jmpi instruction is in compact format) +is an infinite loop on the jmpi instruction. + + +6.35 line – Line + Opcode Instruction Description + 89 (0x59) line dst src0 src1 Compute a line equation (v = p * u + q) of src0 and src1 and store the result + in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Types Dst Type + F F + +Format: +[(pred)] line[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] line[.cmod] (exec_size) reg reg reg + [(pred)] line[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + dwP = src0.RegNum.SubRegNum[bits4:2]; // A DWord-aligned scalar. + dwQ = src0.RegNum.(SubRegNum[bit4] | 0x8); // Fourth component. + if ( WrEn.chan[n] ) { + dst.chan[n] = dwP * src1.chan[n] + dwQ; + } + } + +Description: +The line instruction computes a component-wise line equation (v = p * u + q where u, v are vectors and p, +q are scalars) of src0 and src1 and stores the results in dst. src1 is the input vector u. src0 provides input +scalars p and q, where p is the scalar value based on the region description of src0 and q is the scalar +value implied from src0 region. Specifically, q is the fourth component of the 4-tuple (128-bit aligned) that +p belongs to. +Restrictions: +This is a specialized instruction that only supports an execution size (ExecSize) of 8 or 16. + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 184 + The src0 region must be a replicated scalar (with HorzStride == VertStride == 0). +src0 must specify .0 or .4 as the subregister number, corresponding to a subregister byte offset of 0 or 16. +Source operands cannot be accumulators. + + +6.36 lrp – Linear Interpolation + Opcode Instruction Description + 92 (0x5c) lrp dst src0 src1 src2 Compute the linear interpolation equation (w = u*x + v*(1 - x)) + of vectors (x, u, v) from src0, src1, and src2, storing the results + in dst. + + +Pred Sat Cond Mod Src Mod + Y N Y Y + + +Src Type Dst Type + F F + +Format: +[(pred)] lrp[.cmod] (exec_size) dst src0 src1 src2 + +Syntax: +[(pred)] lrp[.cmod] (exec_size) reg reg reg + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src1.chan[n] * src0.chan[n] + src2.chan[n] * (1.0 – src0.chan[n]); + } + } + + +Description: +The lrp instruction takes component-wise multiplication of src0 and src1, and adds the result to the +component-wise multiplication of src2 and (1 - src0), and then stores the final results in dst. +Restrictions: +The vertical stride (VertStride) is overloaded to 4 in HW for 3-source instructions. +The overflow conditional modifier (.o) is not allowed. +No explicit accumulator access because this is a three-source instruction. AccWrEn is allowed for +implicitly updating the accumulator. +All three-source instructions have certain restrictions, described in Instruction Machine Formats. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 185 + 6.37 lzd – Leading Zero Detection + Opcode Instruction Description + 74 (0x4A) lzd dst src0 Count the number of leading 0 bits (from MSB) in src0 and store that count + in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Type Dst Type + D, UD UD + +Format: +[(pred)] lzd[.cmod] (exec_size) dst src0 + +Syntax: +[(pred)] lzd[.cmod] (exec_size) reg reg + [(pred)] lzd[.cmod] (exec_size) reg reg + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + UD udScalar = src0.chan[n]; + UD cnt = 0; + while ( (udScalar & (1 << 31)) == 0 && cnt != 32 ) { + cnt ++; + udScalar = udScalar << 1; + } + dst.chan[n] = cnt; + } + } + + +Description: +The lzd instruction counts component-wise the leading zeros from src0 and stores the resulting counts in +dst. +If src0 is zero, store 32 in dst. +Restrictions: +If the source is signed, the abs source modifier must be used to convert any negative source value to a +positive value. +Accumulator cannot be destination, implicit or explicit. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 186 + 6.38 mac – Multiply Accumulate + Opcode Instruction Description + 72 (0x48) mac dst src0 src1 Multiply src0 and src1, add to accumulator, and store the result in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + + Src Types Dst Type + *B, *W *B, *W, *D + F F + DF DF + +Format: +[(pred)] mac[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] mac[.cmod] (exec_size) reg reg reg + [(pred)] mac[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src0.chan[n] * src1.chan[n] + acc0.chan[n]; + } + } + + +Description: +The mac instruction takes component-wise multiplication of src0 and src1, adds the results with the +corresponding accumulator values, and then stores the final results in dst. +Restrictions: +Accumulator is an implicit source and thus cannot be an explicit source operand. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 187 + 6.39 mach – Multiply Accumulate High + Opcode Instruction Description + 73 (0x49) mach dst src0 src1 Multiply the upper word of src0 (masking off the lower word) times src1, + adding the 64-bit product to the 64-bit accumulator value, storing the 64-bit + result in the accumulator and storing the high DWord of the result in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y + + +Src Types Dst Type + D D + UD UD + +Format: +[(pred)] mach[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] mach[.cmod] (exec_size) reg reg reg + [(pred)] mach[.cmod] (exec_size) reg reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + acc.chan[n][63:0] = (src0.chan[n][31:16] * src1.chan[n][31:0]) << 16 + + acc.chan[n][63:0]; + if ( WrEn.chan[n] ) { + dst.chan[n][31:0] = acc.chan[n][63:32]; + } + } + + +Description: +The mach instruction performs DWord integer multiply-accumulate operation and outputs the high DWord +(bits 63:32). +For each enabled channel, this instruction multiplies the DWord in src1 with the high word of the DWord +in src0, left shifts the result by 16 bits, adds it with the corresponding accumulator values, and keeps the +whole 64-bit result in the accumulator. It then stores the high DWord (bits 63:32) of the results in dst. +This instruction is intended to be used to emulate 32-bit DWord integer multiplication by using the large +number of bits available in the accumulator. For example, the following four instructions perform vector +multiplication of two 32-bit signed integer sources from r2 and r3 and store the resulting vectors with the +high 32 bits in r5 and the low 32 bits in r6. +mul (8) acc0:d r2.0<8;8,1>:d r3.0<8;8,1>:d //All channels must be enabled +mach (8) rTemp<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d //All channels must be enabled +mov (8) r5.0<1>:d rTemp<8;8,1>:d // High 32 bits + mov (8) r6.0<1>:d acc0:d // Low 32 bits + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 188 + The mul and mach instructions must have all channels enabled. The first mov should have channel +enable from the destHI of IMUL, the second mov should have the channel enable from the destLO of +IMUL. +As mach is used to generate part of the 64-bit DWord integer results, saturation modifier should not be +used. In fact, saturation modifier should not be used for any of these four instructions. +Source and destination operands must be DWord integers. Source and destination must be of the same +type, signed integer or unsigned integer. +If dst is UD, src0 and src1 may be UD and/or D. However, if any of src0 and src1 is D, source modifier +(abs) must be present to convert it to match with dst. +If dst is D, src0 and src1 must also be D. They cannot be UD as it may cause unexpected overflow +because the computed results are limited to 64 bits. +Restrictions: +Accumulator is an implicit source and thus cannot be an explicit source operand. +AccWrEn is required. The accumulator is an implicit destination and thus cannot be an explicit destination +operand. + + +6.40 mad – Multiply Add + Opcode Instruction Description + 91 (0x5B) mad dst src0 src1 src2 Add src1 times src2 to src0 and store the result in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Type Dst Type + F F + DF DF + +Format: +[(pred)] mad[.cmod] (exec_size) dst src0 src1 src2 + +Syntax: +[(pred)] mad[.cmod] (exec_size) reg reg reg reg + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src1.chan[n] * src2.chan[n] + src0.chan[n]; + } + } + + +Description: +The mad instruction takes component-wise multiplication of src1 and src2, adds the results with the +corresponding src0 values, and then stores the final results in dst. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 189 + Restrictions: +No explicit accumulator access because this is a three-source instruction. AccWrEn is allowed for +implicitly updating the accumulator. +All three-source instructions have certain restrictions, described in Instruction Machine Formats. + + +6.41 math – Extended Math Function + Opcode Instruction Description + 56 (0x38) math dst src0 src1 Component-wise extended math function on src0 (and src1) to dst based on + the . + + + + Src Types Dst Type +Pred Sat Cond Mod Src Mod + Y Y F F + Y Y D D + Y Y UD UD + +Format: +[(pred)] math (exec_size) dst src0 src1 + +Syntax: +[(pred)] math (exec_size) reg reg reg imm4 + +Pseudocode: +Evaluate(WrEn); + for (n = 0; n < exec_size; n++) { + if (WrEn.channel[n] == 1) { + switch FC[3:0] { + case 1h: + dst.channel[n] = rcp(src0.channel[n]); + case 2h: + dst.channel[n] = log(src0.channel[n]); + case 3h: + dst.channel[n] = exp(src0.channel[n]); + case 4h: + dst.channel[n] = sqrt(src0.channel[n]); + case 5h: + dst.channel[n] = rsq(src0.channel[n]); + case 6h: + dst.channel[n] = sin(src0.channel[n]); + case 7h: + dst.channel[n] = cos(src0.channel[n]); + case 9h: // src0 / src1 + dst.channel[n] = fdiv(src0.channel[n], src1.channel[n]); + case Ah: + dst.channel[n] = pow(src0.channel[n], src1/channel[n]); + case Bh: // src0 / src1 + idiv(src0.channel[n], src1.channel[n]); + dst.channel[n] = quotient; + dst+1.channel[n] = remainder; + case Ch: + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 190 + idiv(src0.channel[n], src1.channel[n]); + dst.channel[n] = quotient; + case Dh: + idiv(src0.channel[n], src1.channel[n]); + dst.channel[n] = remainder; + } + } + } + +Description: +The math instruction performs extended math function on the components in src0, or src0 and src1, and +write the output to the channels of dst. The type of extended math function are based on the FC[3:0] +encoding in the table below. +Function Control[3:0] Description +[3:0] + Function Description: + 0h: Reserved + 1h: INV (reciprocal) + 2h: LOG + 3h: EXP + 4h: SQRT + 5h: RSQ + 6h: SIN + 7h: COS + 8h: Reserved + 9h: FDIV + Ah: POW + Bh: INT DIV – return quotient and remainder + Ch: INT DIV – return quotient only + Dh: INT DIV – return remainder + Eh: Reserved + Fh: Reserved + + + +Restrictions: +No accumulator access, implicit or explicit. +The math instruction must use GRF registers as source(s) and destination. +The math instruction does not support indirect addressing modes. +The only supported rounding mode for math instruction is Round to Nearest Even. +For INTDIV with both quotient and remainder, the second destination register is implied from the first +destination register with “+1” to get the register number. +Mixed DW and UD sources are not allowed for the INT DIV function. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 191 + INT DIV function does not support SIMD16. +The FDIV function is not supported in ALT_MODE. + + +6.41.1 INV - Inverse +Precision:1 ULP + Src-> +inf +0 / +Denorm - 0 / -Denorm -inf NaN +Dest – IEEE mode +0 +inf -inf -0 NaN +Dest – ALT mode +fmax -fmax NaN + + +6.41.2 LOG – Logarithm +Precision: +DirectX 10 and below +If src0 is [0.5..2], absolute error must be no more than 2-21. If src0 is (0..0.5) or (2..+INF], relative error +must be no more than 2-21 +Note:In ALT mode log is computed as Log2 (abs (src0)) + Src-> +inf +0 / +Denorm -0 / -Denorm -inf -F NaN +Dest – IEEE mode + +inf -inf -inf NaN NaN NaN + +Dest – ALT mode + -fmax -fmax +F NaN + + + +6.41.3 EXP - Exponent +Precision: +DirectX 10 Relative error <= 3 ULP + Src-> +inf +0 / +Denorm -0 / -Denorm -inf -F NaN +Dest – IEEE mode + +inf 1 1 0 +F NaN + +Dest – ALT mode + 1 1 +F NaN + + + +6.41.4 SQRT +Precision: +DirectX 10 (and below) Relative error <= 1 ULP +Notes:In ALT mode SQRT is computed as SQRT(abs (src0)) + Src-> +inf +0 / +Denorm -0 / -Denorm -inf -F NaN +Dest – IEEE mode + +inf 0 -0 NaN NaN NaN + +Dest – ALT mode + 0 0 +F NaN + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 192 + 6.41.5 RSQ +Precision: +DirectX 10 and below Relative error <= 3 ULP +Notes:In ALT mode RSQ is computed as RSQ(abs (src0)) + Src-> +inf +0 / +Denorm -0 / -Denorm -inf -F NaN +Dest – IEEE mode + +0 +inf -inf NaN NaN NaN + +Dest – ALT mode + +fmax +fmax +F NaN + + + +6.41.6 POW + +Precision: +POWR, POWN is not supported in hardware. +IEEE Mode: +Src0-> +Src1 abs(F > 1) abs(F < 1) abs(+F = = 1) +inf +0 / +Denorm -Denorm / -0 -inf NaN ++inf +inf 0 NaN +inf 0 0 +inf NaN ++0 / Denorm 1 1 1 NaN NaN NaN NaN NaN +-0 / Denorm 1 1 1 NaN NaN NaN NaN NaN +-inf 0 +inf NaN 0 +inf +inf 0 NaN +-F +F +F +F 0 +inf +inf 0 NaN +NaN NaN NaN NaN NaN NaN NaN NaN NaN ++F +F +inf 0 0 NaN NaN + +ALT Mode: +Src0-> +Src1 +F +inf +0 / +Denorm -0 / -Denorm -inf -F NaN ++inf ++0 / Denorm 1 1 1 1 NaN +-0 / Denorm 1 1 1 1 NaN +-inf +-F +F +fmax +fmax +F NaN +NaN NaN NaN NaN NaN ++F +F 0 0 +F NaN + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 193 + 6.41.7 SIN +Precision: +DirectX 10 and below Absolute error <= 0.0008 for the range of +/- 100* pi +Outside of the above range the function will remain periodic, producing values between -1 and 1. +However, the period of SIN is determined by the internal representation of Pi, meaning that as the +magnitude of input increases the absolute error will, in general, also increase. + Src-> +inf +0 / +Denorm -0 / -Denorm -inf -F NaN +Dest – IEEE mode NaN +0 -0 NaN -1 to 1 NaN +Dest – ALT mode +0 -0 -1 to 1 NaN + + +6.41.8 COS +Precision: +DirectX 10 and below: Absolute error <= 0.0008 for the range of +/- 100* pi +Outside of the above range the function will remain periodic, producing values between -1 and 1. +However, the period of COS is determined by the internal representation of Pi, meaning that as the +magnitude of input increases the absolute error will, in general, also increase. + Src-> +inf +0 / +Denorm -0 / -Denorm -inf -F NaN +Dest – IEEE mode NaN +0 -0 NaN -1 to 1 NaN +Dest – ALT mode +1 +1 -1 to 1 NaN + + +6.41.9 INT DIV +Precision:32-bit integer +For signed inputs, INT DIV behavior is illustrated by the table below: + +Inputs: Numerator + + - - + + Denominator + - + - + +Outputs: Quotient + - - + + + Remainder + + - - + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 194 + 6.41.10 mov – Move + Opcode Instruction Description + 1 (0x01) mov dst src0 Copy the value from src0 to dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Type Dst Type +*B, *W, *D *B, *W, *D +*B, *W, *D F + F *B, *W, *D + F F + *W, *D DF + F DF + DF *W, *D + DF F + DF DF + +Format: +[(pred)] mov[.cmod] (exec_size) dst src0 + +Syntax: +[(pred)] mov[.cmod] (exec_size) reg reg + [(pred)] mov[.cmod] (exec_size) reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src0.chan[n]; + } + } + + +Description: +The mov instruction moves the components in src0 into the channels of dst. If src0 and dst are of different +types, format conversion is performed. If src0 is a scalar immediate, the immediate value is loaded into +enabled channels of dst. +A mov with the same source and destination type, no source modifier, and no saturation is a raw move. A +packed byte destination region (B or UB type with HorzStride == 1 and ExecSize > 1) can only be written +using raw move. +Restrictions: +Raw move is not supported for Float values in ALT mode if any values are infinities or NaNs. +An accumulator can be a source or destination operand but not both. +If the source type and destination type differ, conditional modifiers are not allowed. +Programming Notes: + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 195 + There is no direct conversion from B/UB to DF or DF to B/UB. Use two instructions and a word or DWord +intermediate type. + + +6.42 6movi – Move Indexed + Opcode Instruction Description + 3 (0x3) movi dst src0 Fast indexed move from src0 to dst. + + +Pred Sat Cond Mod Src Mod + Y Y N Y + + +Generation Src Type Dst Type + B B + UB UB + W W + UW UW + D D + UD UD + F F + +Note: As shown in the table, the source and destination type must be the same. +Format: +[(pred)] movi[.cmod] (exec_size) dst src0 + +Syntax: +[(pred)] movi[.cmod] (exec_size) reg reg + +Pseudocode: +Evaluate(WrEn); + srcregfile = regfile(src0); + srcreg = reg(address[0]); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + srcsubreg = subreg(address[n] + addr_imm); + dst.chan[n] = srcregfile.srcreg.srcsubreg; + } + } + + +Description: +The movi instruction performs a fast component-wise indexed move for subfields from src0 to dst. The +source operand must be an indirectly-addressed register. All channels of the source operand share the +same register number, which is provided by the register field of the first address subregister, with a +possible immediate address offset. The register fields of the subsequent address subregisters are ignored +by hardware. The subregister number of a source channel is provided by the subregister field of the +corresponding address subregister. +The destination register may be either a directly-addressed or an indirectly-addressed register. +This instruction effectively performs a subfield shuffling from one register to another. Up to eight subfields +can be selected by an instruction. + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 196 + Restrictions: +Source operand cannot be accumulators. The source operand must be a general register. +The source and destination must have the same type. +The execution size must be <= 8 (1, 2, 4, or 8). +The address register for the source must be aligned to the base (a0.0). +The destination register (directly or indirectly addressed) must be 16-byte aligned. +The destination stride in bytes must equal the source element size in bytes. +The Align16 access mode is not allowed. +All the index registers (address subregisters) used must point to the same GRF register. +The instruction must use 1x1 indirect regioning. +movi is always based on register offset zero no matter what the destination offset is. The destination +offset is used in HW only to create channel enables. The first index register (a0.0) is always used to +select the first element of the destination start from offset zero. Each index register is used to select 1 +element if type is byte, 2 elements if type is Word, or 4 elements if type is DWord. +Conditional Modifier is not allowed for this instruction. +HW Implementation Details: +The destination offset of the movi instruction is only used in HW to generate destination write enables. +Each element of the destination is directly mapped to the index registers for the movi instruction. +For byte movi, byte0 of the destination is selected by (a0.0[4:0]), byte1 is selected by (a0.1[4:0]), ..., and +byte7 is selected by (a0.7[4:0]). The rest of the bytes are undefined. +For word movi, byte0 of the destination is selected by (a0.0[4:1] & 0), byte1 is selected by (a0.0[4:1] & 1), +byte2 is selected by (a0.1[4:1] & 0), byte3 is selected by (a0.1[4:1] & 1), ..., and byte15 is selected by +(a0.7[4:1] & 1). The rest of the bytes are undefined. +For DWord or float movi, byte0 of the destination is selected by (a0.0[4:2] & 00b), byte1 is selected by +(a0.0[4:2] & 01b), byte2 is selected by (a0.0[4:2] & 10b), byte3 is selected by (a0.0[4:2] & 11b), byte4 is +selected by (a0.1[4:2] & 00b), byte5 is selected by (a0.1[4:2] & 01b), ..., byte31 is selected by (a0.7[4:2] & +11b). +For all 3 conditions above, a0.n[4:0] = a0.n[4:0] + addr_imm[4:0]. + + +6.43 mul – Multiply + Opcode Instruction Description + 65 (0x41) mul dst src0 src1 Multiply src0 and src1 storing the result in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Types Dst Type + W W + W D + W, D D + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 197 + Src Types Dst Type + F F + DF DF + +Format: +[(pred)] mul[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] mul[.cmod] (exec_size) reg reg reg + [(pred)] mul[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src0.chan[n] * src1.chan[n]; + } + } + + +Description: +The mul instruction performs component-wise multiplication of src0 and src1 and stores the results in dst. +]: When both src0 and src1 are of type D or UD, only the low 16 bits of each element of src1 are used. +The accumulator maintains full 48-bit precision. The macro described in the mach instruction should be +used to obtain the full precision 64-bit multiplication result. +Multiplication of two floating-point numbers follows the rules in mul – Multiply or mul – Multiply) based on +the applicable floating-point mode. + +Floating-Point Multiplication of A (Column) and B (Row) in IEEE Mode + –inf –finite -1.0 –denorm –0 +0 +denorm +1.0 +finite +inf NaN + –inf +inf +inf +inf NaN NaN NaN NaN –inf –inf –inf NaN + –finite +inf * –A +0 +0 –0 –0 A ** –inf NaN + –1.0 +inf –B +1.0 +0 +0 –0 –0 –1.0 –B –inf NaN + –denorm NaN +0 +0 +0 +0 –0 –0 –0 –0 NaN NaN + –0 NaN +0 +0 +0 +0 –0 –0 –0 –0 NaN NaN + +0 NaN –0 –0 –0 –0 +0 +0 +0 +0 NaN NaN + +denorm NaN –0 –0 –0 –0 +0 +0 +0 +0 NaN NaN + +1.0 –inf B –1.0 –0 –0 +0 +0 +1.0 B +inf NaN + +finite –inf ** –A –0 –0 +0 +0 A * +inf NaN + +inf –inf –inf –inf NaN NaN NaN NaN +inf +inf +inf NaN + NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN NaN + Note: + * Result may be {+finite, +inf (overflow)}. + ** Result may be {–inf (overflow), –finite}. + +Floating-Point Multiplication of A (Column) and B (Row) in ALT Mode + –fmax –finite –1.0 –denorm –0 +0 +denorm +1.0 +finite +fmax *** + –fmax +fmax +fmax +fmax –0 –0 +0 +0 –fmax –fmax –fmax + –finite +fmax * –A +0 +0 –0 –0 A ** –fmax + –1.0 +fmax –B +1.0 +0 +0 –0 –0 –1.0 –B –fmax + –denorm +0 +0 +0 +0 +0 –0 –0 –0 –0 –0 + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 198 + –0 +0 +0 +0 +0 +0 –0 –0 –0 –0 –0 + +0 –0 –0 –0 –0 –0 +0 +0 +0 +0 +0 + +denorm –0 –0 –0 –0 –0 +0 +0 +0 +0 +0 + +1.0 –fmax B –1.0 –0 –0 +0 +0 +1.0 B +fmax + +finite –fmax ** –A –0 –0 +0 +0 A * +fmax + +fmax –fmax –fmax –fmax –0 –0 +0 +0 +fmax +fmax +fmax + *** + Note: + * Result may be {+finite, +fmax (overflow)}. + ** Result may be {–fmax (overflow), –finite}. + *** Result is undefined if A or B is {–inf, +inf, NaN}. + +Restrictions: +Source operands cannot be accumulators. +When operating on integers with at least one of the source being a DWord type (signed or unsigned), the +destination cannot be floating-point (implementation note: the data converter only looks at the low 34 bits +of the result). +When operating on integers with at least one source having a DWord type (signed or unsigned), the +Overflow and Sign flags are undefined. Therefore, conditional modifiers and saturation (.sat) cannot be +used in this case. +]: When multiplying a DW and a W, the W has to be on src1, and the DW has to be on src0. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 199 + 6.44 nop – No Operation + Opcode Instruction Description + 126 (0x7E) nop Issue a dummy instruction and perform no operation. + + +Pred Sat Cond Mod Src Mod + N N N N + +Format: +nop + +Syntax: +nop + +Pseudocode: + { + ; // The null statement, which does nothing. + } + + +Description: +Do nothing. The nop instruction takes an instruction dispatch but performs no operation. It can be used +for assembly patching in memory, or to insert a delay in the program sequence. +Restrictions: +The nop instruction takes no instruction options other than Breakpoint. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 200 + 6.45 not – Logic Not + Opcode Instruction Description + 4 (0x04) not dst src0 Bitwise NOT of src0 storing the result in dst. + + +Pred Sat Cond Mod Src Mod + Y N Y Y + + +Generation Src Type Dst Type + *B, *W, *D *B, *W, *D + +Format: +[(pred)] not[.cmod] (exec_size) dst src0 + +Syntax: +[(pred)] not[.cmod] (exec_size) reg reg + [(pred)] not[.cmod] (exec_size) reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = ~ src0.chan[n]; + } + } + + +Description: +The not instruction performs logical NOT operation (or one's complement) of src0 and storing the results +in dst. +A register source operand can use a source modifier: + +  Any source modifier is numeric, optionally changing a source value s to -s, abs(s), or -abs(s) before + the NOT operation. + +This operation does not produce sign or overflow conditions. Only the .e/.z or .ne/.nz conditional +modifiers should be used. + + +Restrictions: +Source modifier is not allowed if source is an accumulator. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 201 + 6.46 or – Logic Or + Opcode Instruction Description + 6 (0x06) or dst src0 src1 Bitwise OR of src0 and src1 storing the result in dst. + + +Pred Sat Cond Mod Src Mod + Y N Y Y + + +Generation Src Types Dst Type + *B, *W, *D *B, *W, *D + +Format: +[(pred)] or[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] or[.cmod] (exec_size) reg reg reg + [(pred)] or[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src0.chan[n] | src1.chan[n]; + } + } + + +Description: +The or instruction performs component-wise logic OR operation between src0 and src1 and stores the +results in dst. +Register source operands can use source modifiers: + +  Any source modifier is numeric, optionally changing a source value s to -s, abs(s), or -abs(s) before + the OR operation. + +This operation does not produce sign or overflow conditions. Only the .e/.z or .ne/.nz conditional +modifiers should be used. + + +Restrictions: +Source modifier is not allowed if source is an accumulator. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 202 + 6.47 pln – Plane + Opcode Instruction Description + 90 (0x5A) pln dst src0 src1 Compute a plane equation (w = p*u + q*v + r) of scalar (p, q, r) from src0 + and vector src1 (and implied vector src2). Store the result in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y + + +Src Types Dst Type + F F + +Format: +[(pred)] pln[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] pln[.cmod] (exec_size) reg reg reg + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + float dwP = src0.RegNum.SubRegNum[bits4:2]; // A DWord-aligned scalar. + float dwQ = src0.RegNum.(SubRegNum[bit4:2] | 0x1); // Second component. + float dwR = src0.RegNum.(SubRegNum[bit4:2] | 0x3); // Fourth component. + if ( ExecSize == 8 ) + src2 = src1.(RegNum + 1) // Next GRF register. + else // ExecSize == 16 + src2 = src1.(RegNum + 2) // The two GRF registers after RegNum and RegNum + 1. + if ( WrEn.chan[n] ) { + dst.chan[n] = dwP * src1.chan[n] + dwQ * src2.chan[n] + dwR; + } + } + + +Description: +The pln instruction computes a component-wise plane equation (w = p*u+q*v+r where u/v/w are vectors +and p/q/r are scalars) of src0 and src1 and stores the results in dst. src1 is the input vector u. +If ExecSize is 8 then the second input vector v is implied from src1 as the next adjacent GRF register. +If ExecSize is 16 then the second input vector v is implied from src1 as the two GRF registers after the +two registers used by input vector u. +src0 provides input scalars p, q, and r, where p is the scalar value based on the region description of src0 +and q and r are the scalar values implied from the src0 region. Specifically, q is the second component +and r is the fourth component of the 4-tuple (128-bit aligned) that p belongs to. +Restrictions: +This is a specialized instruction that only supports an execution size (ExecSize) of 8 or 16. +The src0 region must be a replicated scalar (with HorzStride == VertStride == 0). + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 203 + src0 must specify .0 or .4 as the subregister number, corresponding to a subregister byte offset of 0 or 16. +Source operands cannot be accumulators. + + +6.48 ret – Return + Opcode Instruction Description + 45 (0x2d) ret null src0 Return from a subroutine. + + +Pred Sat Cond Mod Src Mod + Y N N N + + +Src Type Dst Type + D, UD + +Format: +[(pred)] ret (exec_size) null src0 + +Syntax: +[(pred)] ret (exec_size) null reg + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + PcIP[n] = src0.chan[0]; + CallMask[n] = 0; + } + else { + PcIP[n] = IP + 1; + } + } + for ( n = exec_size; n < 32; n++ ) { + PcIP[n] = IP + 1; + } + + if ( CallMask[n:0] == 0) ) { // all channels are zero + Jump(src0.chan[0]); + CallMask = src0.chan[1]; + } + + +Description: +Return execution to the code sequence that called a subroutine. +The ret instruction can be predicated or non-predicated. If non-predicated, all channels jump to the return +IP in the first channel of src0 and restore CallMask from the second channel of src0. If predicated, the +enabled channels jump to the return IP from the first channel of src0 and the corresponding bits in the +CallMask are cleared to zero; if all CallMask bits are zero after the ret instruction, then execution jumps to +the return IP from the first channel of src0. +When SPF is on, the predication control must be scalar. + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 204 + Restrictions: +This instruction cannot take accumulator as source. +The src0 regioning control must be <2;2,1>, + + +6.49 rndd – Round Down + Opcode Instruction Description + 69 (0x45) rndd dst src0 Round floating-point src0 down to an integral floating-point value and store + in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Type Dst Type + F F + +Format: +[(pred)] rndd[.cmod] (exec_size) dst src0 + +Syntax: +[(pred)] rndd[.cmod] (exec_size) reg reg + [(pred)] rndd[.cmod] (exec_size) reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = floor(src0.chan[n]); + } + } + +Description: +The rndd instruction takes component-wise floating point downward rounding (to the integral float number +closer to negative infinity) of src0 and storing the rounded integral float results in dst. This is commonly +referred to as the floor() function. +Each result follows the rules in the following tables based on the floating-point mode. + +Floating-Point Round Down in IEEE mode + src0 –inf –finite –denorm –0 +0 +denorm +finite +inf NaN + dst –inf -finite ^ –0 +0 +0 ** +inf NaN +Notes: + ^ + -0 as denorms are flushed to zero. + ** Result may be {+finite, +0}. + +Floating-Point Round Down in ALT mode +src0 –fmax –finite –denorm –0 +0 +denorm +finite +fmax *** + dst –fmax -finite –0 –0 +0 +0 ** +fmax + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 205 + src0 –fmax –finite –denorm –0 +0 +denorm +finite +fmax *** + dst –fmax -finite –0 –0 +0 +0 ** +fmax +Notes: + ** Result may be {+finite, +0}. + *** Result is undefined if src0 is {–inf, +inf, NaN}. + +Restrictions: +No accumulator access, implicit or explicit. + + +6.50 rnde – Round to Nearest or Even + Opcode Instruction Description + 70 (0x46) rnde dst src0 Round floating-point src0 to the nearest or even integral floating-point value + and store in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Type Dst Type + F F + +Format: +[(pred)] rnde[.cmod] (exec_size) dst src0 + +Syntax: +[(pred)] rnde[.cmod] (exec_size) reg reg + [(pred)] rnde[.cmod] (exec_size) reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + if ( src0.chan[n] - floor(src0.chan[n]) > 0.5f ) { + dst.chan[n] = floor(src0.chan[n]) + 1; + } + else if ( src0.chan[n] - floor(src0.chan[n]) < 0.5f ) { + dst.chan[n] = floor(src0.chan[n]); + } + else { + if ( floor(src0.chan[n]) is odd ) { + dst.chan[n] = floor(src0.chan[n]) + 1; + } + else { + dst.chan[n] = floor(src0.chan[n]); + } + } + } + } + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 206 + Description: +The rnde instruction takes component-wise floating point round-to-even operation of src0 with results in +two pieces – a downward rounded integral float results stored in dst and the round-to-even increments +stored in the rounding increment bits. The round-to-even increment must be added to the results in dst to +create the final round-to-even values to emulate the round-to-even operation, commonly known as the +round() function. The final results are the one of the two integral float values that is nearer to the input +values. If the neither possibility is nearer, the even alternative is chosen. +Each result follows the rules in the following tables based on the floating-point mode. + +Floating-Point Round to Nearest or Even in IEEE mode + src0 –inf –finite –denorm –0 +0 +denorm +finite +inf NaN + dst –inf * –0 –0 +0 +0 ** +inf NaN +Notes: + * Result may be {–finite, –0}. + ** Result may be {+finite, +0}. + +Floating-Point Round to Nearest or Even in ALT mode + src0 –fmax –finite –denorm –0 +0 +denorm +finite +fmax *** + dst –fmax * –0 –0 +0 +0 ** +fmax +Notes: + * Result may be {–finite, –0}. + ** Result may be {+finite, +0}. + *** Result is undefined if src0 is {–inf, +inf, NaN}. + +Restrictions: +No accumulator access, implicit or explicit. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 207 + 6.51 rndu – Round Up + Opcode Instruction Description + 68 (0x44) rndu dst src0 Round floating-point src0 up to an integral floating-point value and store in + dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Type Dst Type + F F + +Format: +[(pred)] rndu[.cmod] (exec_size) dst src0 + +Syntax: +[(pred)] rndu[.cmod] (exec_size) reg reg + [(pred)] rndu[.cmod] (exec_size) reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + if ( src0.chan[n] - floor(src0.chan[n]) > 0.0f ) { + dst.chan[n] = floor(src0.chan[n]) + 1; + } + else { + dst.chan[n] = src0.chan[n]; + } + } + } + + +Description: +The rndu instruction takes component-wise floating point upward rounding (to the integral float number +closer to positive infinity) of src0, commonly known as the ceiling() function. +Each result follows the rules in the following tables based on the floating-point mode. + +Floating-Point Round Up in IEEE mode + src0 –inf –finite –denorm –0 +0 +denorm +finite +inf NaN + dst –inf * –0 –0 +0 ^ +finite +inf NaN +Notes: + * Result may be {–finite, –0}. + ^ + +0 as denorms are flushed to zero. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 208 + Floating-Point Round Up in ALT mode + src0 –fmax –finite –denorm –0 +0 +denorm +finite +fmax *** + dst –fmax * –0 –0 +0 +0 +finite +fmax +Notes: + * Result may be {–finite, –0}. + *** Result is undefined if src0 is {–inf, +inf, NaN}. + +Restrictions: +No accumulator access, implicit or explicit. + + +6.52 rndz – Round to Zero + Opcode Instruction Description + 71 (0x47) rndz dst src0 Round floating-point src0 toward zero to an integral floating-point value and + store in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Type Dst Type + F F + +Format: +[(pred)] rndz[.cmod] (exec_size) dst src0 + +Syntax: +[(pred)] rndz[.cmod] (exec_size) reg reg + [(pred)] rndz[.cmod] (exec_size) reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = floor(src0.chan[n]); + if ( abs(src0.chan[n]) < abs(dst.chan[n]) ) { + dst.chan[n] = floor(src0.chan[n]) + 1; + } + else { + dst.chan[n] = floor(src0.chan[n]); + } + } + } + + +Description: +The rndz instruction takes component-wise floating point round-to-zero operation of src0 with results in +two pieces – a downward rounded integral float results stored in dst and the round-to-zero increments +stored in the rounding increment bits. The round-to-zero increment must be added to the results in dst to + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 209 + create the final round-to-zero values to emulate the round-to-zero operation, commonly known as the +truncate() function. The final results are the one of the two closest integral float values to the input values +that is nearer to zero. + +Floating-Point Round to Zero in IEEE mode + src0 –inf –finite –denorm –0 +0 +denorm +finite +inf NaN + dst –inf * –0 –0 +0 +0 ** +inf NaN +Notes: + * Result may be {–finite, –0}. + ** Result may be {+finite, +0}. + +Floating-Point Round to Zero in ALT mode + src0 –fmax –finite –denorm –0 +0 +denorm +finite +fmax *** + dst –fmax * –0 –0 +0 +0 ** +fmax +Notes: + * Result may be {–finite, –0}. + ** Result may be {+finite, +0}. + *** Result is undefined if src0 is {–inf, +inf, NaN}. + +Restrictions: +No accumulator access, implicit or explicit. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 210 + 6.53 sad2 – Sum of Absolute Difference 2 + Opcode Instruction Description + 80 (0x50) sad2 dst src0 src1 Perform a two-wide sum-of-absolute-difference operation on a 2-tuple basis + of src0 and src1, and store the scalar result to the first channel per 2-tuple in + dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Types Dst Type + B, UB W, UW + +Format: +[(pred)] sad2[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] sad2[.cmod] (exec_size) reg reg reg + [(pred)] sad2[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n += 2 ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = abs(src0.chan[n] - src1.chan[n]) + + abs(src0.chan[n+1] - src1.chan[n+1]); + } + } + + +Description: +The sad2 instruction takes source data channels from src0 and src1 in groups of 2-tuples. For each 2- +tuple, it computes the sum-of-absolute-difference (SAD) between src0 and src1 and stores the scalar +result in the first channel of the 2-tuple in dst. +The results are also stored in the accumulator register. The destination operand and the accumulator +maintain 16 bits per channel precision. +The destination register must be aligned to even word (DWord). The even words in the destination region +will contain the correct data. The odd words are also written but with undefined values. +Restrictions: +Source operands cannot be accumulators. +The execution size cannot be 1 as the computation requires at least two data channels. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 211 + 6.54 sada2 – Sum of Absolute Difference Accumulate 2 + Opcode Instruction Description + 81 (0x51) sada2 dst src0 src1 Perform a two-wide sum-of-absolute-difference operation on a 2-tuple basis + of src0 and src1, added to that from the accumulator, and store the scalar + result to the first channel per 2-tuple in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Types Dst Type + B, UB W, UW + +Format: +[(pred)] sada2[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] sada2[.cmod] (exec_size) reg reg reg + [(pred)] sada2[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n += 2 ) { + uwTmp = abs(src0.chan[n] - src1.chan[n]) + + abs(src0.chan[n+1] - src1.chan[n+1]); + if ( WrEn.chan[n] ) { + dst.chan[n] = uwTmp + acc[n]; + } + } + + +Description: +The sada2 instruction takes source data channels from src0 and src1 in groups of 2-tuples. For each 2- +tuple, it computes the sum-of-absolute-difference (SAD) between src0 and src1, adds the intermediate +result with the accumulator value corresponding to the first channel, and stores the scalar result in the +first channel of the 2-tuple in dst. +The destination operand and the accumulator maintain 16 bits per channel precision. Higher precision +(guide bits) stored in the accumulator allows up to 64 rounds of sada2 instructions to be issued back to +back without overflowing the accumulator. +The destination register must be aligned to even word (DWord). The even words in the destination region +will contain the correct data. The odd words are also written but with undefined values. +Restrictions: +Source operands cannot be accumulators. +The execution size cannot be 1 as the computation requires at least two data channels. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 212 + 6.55 sel – Select + Opcode Instruction Description + 2 (0x02) (pred) sel dst src0 src1 Copy either src0 or src1 to dst based on predication or conditional modifier. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Src Types Dst Type +*B, *W, *D *B, *W, *D + F F + DF DF + +Format: +(pred) sel[.cmod] (exec_size) dst src0 src1 + +Syntax: +(pred) sel[.cmod] (exec_size) reg reg reg + (pred) sel[.cmod] (exec_size) reg reg imm32 + +Pseudocode: + Evaluate(WrEn, NoPMask); + if (cmod == “0000”) { // no CMod + Evaluate(PMask); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + if ( PMask.channel[n] ) { + dst.chan[n] = src0.chan[n]; + } + else { + dst.chan[n] = src1.chan[n]; + } + } + } + } + else { // with CMod + Evaluate(CMod); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + if ( CMod.chan[n] ) { + dst.chan[n] = src0.chan[n]; + } + else { + dst.chan[n] = src1.chan[n]; + } + } + } + } + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 213 + Description: +The sel instruction selectively moves the components in src0 or src1 into the channels of dst based on +the predication. On a channel by channel basis, if the channel condition is true, data in src0 is moved into +dst. Otherwise, data in src1 is moved into dst. +As the predication is used to select the two sources, it is not included in the evaluation of WrEn. The +predicate clause is mandatory if cmod is omitted/0000b. If both predication and the conditional modifier +are omitted, the results are undefined. +If the conditional modifier is specified (not 0000b, a compare is performed and the resulting condition flag +is used for the sel instruction. Conditional modifiers .ge and .l follow the cmpn rules, and all other +conditional modifiers follow the cmp rules. Predication is not allowed in this mode. +A sel instruction with cmod .l is used to emulate a MIN instruction. +A sel instruction with cmod .ge is used to emulate a MAX instruction. +For a sel instruction with a .l or .ge conditional modifier, if one source is NaN and the other not NaN, the +non-NaN source is the result. If both sources are NaNs, the result is NaN. For all other conditional +modifiers, if either source is NaN then src1 is selected. +A sel instruction without a conditional modifier always copies a denorm source value to a denorm +destination value (in the manner of a raw move). +A sel instruction with a conditional modifier flushes any selected denorm source value to a zero +destination value. +Format conversion is not allowed. +The sel instruction uses any conditional modifier internally and does not update the flag register if a +conditional modifier is used. +Restrictions: +]: The maximum execution size is 16. + + +6.56 send Message + Opcode Instruction Description + 49 (0x31) send Send a message stored in GRF starting at to a shared function + identified by along with control from with a GRF + writeback location at . + + +Pred Sat Cond Mod Src Mod Src Types Dst Type + Y [FLT] [INT] + +Format: +[(pred)] send (exec_size) + +Syntax: +[(pred)] send (exec_size) reg greg imm6 reg32a + [(pred)] send (exec_size) reg greg imm6 imm32 + +Pseudocode: +Evaluate(WrEn); + = WrEn; + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 214 + = .RegNum; + MessageEnqueue(, , , , ); + +Description: +The send instruction performs data communication between a thread and external function units, +including shared functions (Sampler, Data Port Read, Data Port Write, URB, and Message Gateway) and +some fixed functions (e.g. Thread Spawner, who also have an unique Shared Function ID). The send +instruction adds an entry to the EU’s message request queue. The request message is stored in a block +of contiguous GRF registers. The response message, if present, will be returned to a block of contiguous +GRF registers. The return GRF writes may be in any order depending on the external function units. + is the lead GRF register for request. is the lead GRF register for response. The message +descriptor field contains the Message Length (the number of consecutive GRF registers) and the +Response Length (the number of consecutive GRF registers). It also contains the header present bit, and +the function control signals. The extend mesage descriptor field contains the target function +ID. WrEn is forwarded to the target function in the message sideband. +The send instruction is the only way to terminate a thread. When the EOT (End of Thread) bit of +is set, it indicates the end of thread to the EU, the Thread Dispatcher and, in most cases, the parent fixed +function. +Message descriptor field can be a 32-bit immediate, imm32, or a 32-bit scalar register, . +GEN restricts that the 32-bit scalar register must be the leading dword of the address register. +It should be in the form of a0.0<0;1,0>:ud. When is a register operand, only the lower 29 bits of + are used. + is a 6-bit immediate, imm6. The lower 4bits of the specifies the SFID for the +message. The MSb of the message descriptor, the EOT field, always comes from bit 127 of the +instruction word, which is the MSb of imm6. A thread must terminate with a send instruction with EOT +turned on. + is a 256-bit aligned GRF register. It serves as the leading GRF register of the request. + serves for two purposes: to provide the leading GRF register location for the response message if +present, and to provide parameters to form the channel enable sideband signals. + signals whether there is a response to the message request. It can be either a null register, a +direct-addressed GRF register or a register-indirect GRF register. Otherwise, hardware behavior is +undefined. +If is null, there is no response to the request. Meanwhile, the Response Length field in +must be 0. Certain types of message requests, such as memory write (store) through the Data Port, do +not want response data from the function unit. If so, the posted destination operand can be null. +If is a GRF register, the register number is forwarded to the shared function. In this case, the +target function unit must send one or more response message phases back to the requesting thread. The +number of response message phases must match the Response Length field in , which of course +cannot be zero. For some cases, it could be an empty return message. An empty return message is +defined as a single phase message with all channel enables turned off. +The subregister number, horizontal stride, destination mask and type fields of are always valid +and are used in part to generate the WrEn. This is true even if is a null register (this is an +exception for null as for most cases these fields are ignored by hardware). +The 16-bit channel enables of the message sideband are formed based the WrEn. Interpretation of the +channel enable sideband signals is subject to the target external function. In general for a ‘send’ +instruction with return messages, they are used as the destination dword write mask for the GRF registers + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 215 + starting at . For a message that has multiple return phases, the same set of channel enable signals +applies to all the return phases. +Thread managed memory coherency: A special usage of using non-null is to support write-commit +signaling for memory write service by the Data Port Write unit. If is not null for a memory +write request, the Data Port along with the Data Cache or Render Cache will wait until all the posted +writes for the request have reached the coherent domain before sending back to the requesting thread an +empty message to register. A memory write reaching the coherent domain, also referred to as +reaching the global observable state, means that subsequent read to the same memory location, no +matter which thread issues the read, must return the data of the write. +The destination dependency control, {NoDDClr}, can be used in this instruction. This allows software to +control the destination dependencies for multiple ‘read’-type messages similar to that for multiple +instructions using EU execution pipeline. As send does not check register dependencies for the post +destination, {NoDDChk} should not be used for this instruction. + +Message Descriptor Definition + Bit Description + 31 Reserved : MBZ + 30 Reserved : MBZ + 29 Reserved : MBZ +28:25 + Message Length. This field specifies the number of 256-bit GRF registers starting from to be sent out + on the request message payload. Valid value ranges from 1 to 15. A value of 0 is considered erroneous. + Format = U4 + Range = [1,15] +24:20 + Response Length. This field indicates the number of 256-bit registers expected in the message response. + The valid value ranges from 0 to 16. A value 0 indicates that the request message does not expect any + response. The largest response supported is 16 GRF registers. + Format = U5 + Range = [0,16] + + 19 + Header Present. If set, indicates that the message includes a header. Depending on the target shared + function, this field may be restricted to either enabled or disabled. Refer to the specific shared function section + for details. + Format = Enable +18:0 + Function Control + This field is intended to control the target function unit. Refer to the section on the specific target function unit + for details on the contents of this field. + + +Extended Message Descriptor Definition +Bit Description + 5 + End Of Thread + This field, if set, indicates that this is the final message of the thread and the thread’s resources can be + reclaimed. +4 reserved + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 216 + Bit Description +3:0 + Target Function ID + This field indicates the function unit for which the message is intended. + Refer to “GPU Overview” document for the mapping of Shared Function IDs + +Sideband Signals Associated with Each Message Sent to the Shared Function provides a summary of the +signals associated with each message that is sent to the shared function. It contains fields from the send +instruction as well as fields from control register cr0 and state register sr0. + +Sideband Signals Associated with Each Message Sent to the Shared Function +Signal Bits Source + EOT 1 + End of Thread: Sourced from the EOT bit in send instruction word + + SFID 3 + Shared Function Identifier: Sourced from the target function ID field in of send + +MLEN 4 + Message Length: Sourced from the message length field in of send + +RLEN 5 + Response Length: Sourced from the response length field in of send + + FC 19 + Function Control: Sourced from the function control field in of send + + REG 7 + Destination Register: Sourced from the 256-bit register aligned register number of the field of + send + + CE 16 + Channel Enable: Sourced from the write enable of send + +CLEAR 1 + Destination Register Clear: Source from the Destination Dependency Control field (inverse of NoDDClr) + in send instruction word + + FFID 4 + Fixed Function Identifier: Sourced from the Fixed Function ID field in sr0 + + EUID 4 + Execution Unit Identifier: Sourced from the EUID field in sr0 + + TID 2 + Thread Identifier: Sourced from the TID field in sr0 + +Restrictions: +Software must obey the following rules in signaling the end of thread using the send instruction: + +  The posted destination operand must be null. + o No acknowledgement is allowed for the send instruction that signifies the end + of thread. This is to avoid deadlock as the EU is expecting to free up the + terminated thread’s resource. + +  A thread must terminate with a send instruction with message to a shared function on + the output message bus; therefore, it cannot terminate with a send instruction with + message to the following shared functions: Sampler unit, NULL function + o For example, a thread may terminate with a URB write message or a render + cache write message. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 217 +  A root thread originated from the media (generic) pipeline must terminate with a send + instruction with message to the Thread Spawner unit. A child thread should also + terminate with a send to TS. Please refer to the Media Chapter for more detailed + description. +The send instruction can not update accumulator registers. +Saturate is not supported for send instruction. +ThreadCtrl are not supported for send instruction. +The send with EOT should use register space R112-R127 for . This is to enable loading of a new +thread into the same slot while the message with EOT for current thread is pending dispatch. + + +6.57 sendc – Conditional Send Message + Opcode Instruction Description + 50 (0x32) sendc dst src desc exdesc Wait for dependencies in the TDR Register to clear, then send a message + stored in registers starting at src to a shared function identified by exdesc + along with control from desc with a general register writeback location at dst. + + +Pred Sat Cond Mod Src Mod + Y N N N + + +Src Type Dst Type + [FLT], [INT] + +Format: +[(pred)] sendc (exec_size) dst src0 exdesc desc + +Syntax: +[(pred)] sendc (exec_size) reg reg reg32a imm4 + [(pred)] sendc (exec_size) reg reg imm32 imm4 + +Pseudocode: + if ( TDR[7] ... || TDR[2] || TDR[1] || TDR[0] ) { + wait; + } + Evaluate(WrEn); + MsgChEnable = WrEn; + SourceReg = src0.RegNum; + MessageEnqueue(MsgChEnable, ResponseReg, SourceReg, desc, exdesc); + + +Description: +The sendc instruction has the same behavior as the send instruction except the following. +sendc first checks the dependent threads inside the Thread Dependency Register. There are up to 8 +dependent threads in the TDR register. The sendc instruction executes only when all the dependent +threads in the TDR register are retired. +Restrictions: +The sendc instruction has the same restrictions as the send instruction. + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 218 + 6.58 shl – Shift Left + Opcode Instruction Description + 9 (0x09) shl dst src0 src1 Shift the bits in src0 left by the number of bits indicated in src1. Store the + result in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Generation Src Types Dst Type + *B, *W, *D *B, *W, *D + +Format: +[(pred)] shl[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] shl[.cmod] (exec_size) reg reg reg + [(pred)] shl[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + shiftCnt = src1.chan[n] & 0x1F; // Always use low 5 bits for shift count. + dst.chan[n] = src0.chan[n] << shiftCnt; + } + } + + +Description: +Perform component-wise logical left shift of the bits in src0 by the shift count indicated in src1, storing the +results in dst, inserting zero bits in the number of LSBs indicated by the shift count. +The shift count is taken from the low five bits of src1, regardless of the src1 type and treated as an +unsigned integer in the range 0 to 31. +Hardware detects overflow properly and uses it to perform any saturation operation on the result, as long +as the shifted result is within 33 bits. Otherwise, the result is undefined. +Note: For word and DWord operands, the accumulators have 33 bits. +Restrictions: +Accumulator cannot be destination, implicit or explicit. +Results of saturation in packed-DWord mode are unpredicable. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 219 + 6.59 shr – Shift Right + Opcode Instruction Description + 8 (0x08) shr dst src0 src1 Shift the bits in src0 right by the number of bits indicated in src1. Store the + result in dst. + + +Pred Sat Cond Mod Src Mod + Y Y Y Y + + +Generation Src Types Dst Type + UB, UW, UD UB, UW, UD + +Format: +[(pred)] shr[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] shr[.cmod] (exec_size) reg reg reg + [(pred)] shr[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + shiftCnt = src1.chan[n] & 0x1F; // Always use low 5 bits for shift count. + dst.chan[n] = src0.chan[n] >> shiftCnt; + } + } + + +Description: +Perform component-wise logical right shift with zero insertion of the bits in src0 by the shift count +indicated in src1, storing the results in dst. Insert zero bits in the number of MSBs indicated by the shift +count. +The shift count is taken from the low five bits of src1, regardless of the src1 type and treated as an +unsigned integer in the range 0 to 31. +src0 and dst can have different types and can be signed or unsigned. +Note: For word and DWord operands, the accumulators have 33 bits. +Note: For unsigned src0 types, shr and asr produce the same result. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 220 + 6.60 subb – Integer Subtraction with Borrow + Opcode Instruction Description + 79 (0x4F) subb dst src0 src1 Subtract unsigned integer src1 from src0. Store the result in dst and store + the borrow (0 or 1) as a 32-bit value in acc. + + +Pred Sat Cond Mod Src Mod + Y N Y N + + +Src Types Dst Type + UD UD + +Format: +[(pred)] subb[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] subb[.cmod] (exec_size) reg reg reg + [(pred)] subb[.cmod] (exec_size) reg reg imm32 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src0.chan[n] - src1.chan[n]; + acc.chan[n] = borrow(src.chan[n] - src1.chan[n]); + } + } + +Description: +The subb instruction performs component-wise subtraction of src0 and src1 and stores the results in dst, +it also stores the borrow into acc. +If the operation produces a borrow (src0 < src1), write 0x00000001 to acc, else write 0x00000000 to acc. +. +Restrictions: +AccWrEn is required. The accumulator is an implicit destination and thus cannot be an explicit destination +operand. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 221 + 6.61 wait – Wait Notification + Opcode Instruction Description + 48 (0x30) wait nreg Wait for notification on the notification register nreg. + + +Pred Sat Cond Mod Src Mod + N N N N + + +Src Type Dst Type + UD UD + +Format: +wait (exec_size) nreg + +Syntax: +wait (1) n# + +Pseudocode: +N/A + +Description: +The wait instruction evaluates the value of the notification count register nreg. If nreg is zero, thread +execution is suspended and the thread is put in ‘wait_for_notification’ state. If nreg is not zero (i.e., one or +more notifications have been received), nreg is decremented by one and the thread continues executing +on the next instruction. If a thread is in the ‘wait_for_notification’ state, when a notification arrives, the +notification count register is incremented by one. As the notification count register becomes nonzero, the +thread wakes up to continue execution and at the same time the notification register is decremented by +one. If only one notification arrived, the notification register value becomes zero. However, during the +above mentioned time period, it is possible that more notifications may arrive, making the notification +register nonzero again. +When multiple notifications are received, software must use wait instructions to decrement notification +count registers for each notification. +Notification register n0:ud is for thread to thread communication (via the Message Gateway shared +function) and n1:ud for host to thread communication (through MMIO registers). See the Message +Gateway chapter for thread-thread communication . +Restrictions: +src0 and dst must be n0, n1, or n2. +Execution size must be 1 as the notification registers are scalar. +Predication is not allowed. +Two back-to-back wait instructions are not allowed. At minimum, a nop instruction must be inserted +between two wait instructions. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 222 + 6.62 while – While + Opcode Instruction Description + 39 (0x27) while JIP Mark the end of a do-while block of code. + + +Pred Sat Cond Mod Src Mod + Y N N N + +Format: +[(pred)] while (exec_size) JIP + +Syntax: +]: [(pred)] while (exec_size) imm16 + +Pseudocode: +Evaluate(WrEn); + for ( n = 0; n < 32; n++ ) { + if (WrEn.chan[n] ) { + PcIP[n] = IP + JIP; + } + else { + PcIP[n] = IP + 1; + } + } + + if (cmod == 0) { + if ( | PMask == 1 ) { // any enabled channel true + Jump(IP + JIP); + } + } + + +Description: +The while instruction marks the end of a do-while block. The instruction first evaluates the loop +termination condition for each channel based on the current channel enables and the predication flags +specified in the instruction. If any channel has not terminated, a branch is taken to a destination address +specified in the instruction, and the loop continues for those channels. Otherwise, execution continues to +the next instruction. +]: The following table describes the 16-bit jump target offset JIP. JIP is a signed 16-bit number, added to +IP pre-increment, and should point to the first instruction with the do label of the do-while block of code. It +should be a negative number for the backward referencing. In GEN binary, JIP is at location src1 and +must be of type W (signed word integer). + +JIP + Bits Description +31:16 Reserved: MBZ. + 15:0 + JIP (Jump Target Offset). Specifies the jump distance in 64-bit units if a jump is taken for the instruction. + Format = S15. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 223 + If SPF is ON, none of the PcIP are updated. +Restrictions: +The execution size must be the same for the while instruction and any break and cont instructions of the +same code block. + + +6.63 xor – Logic Xor + Opcode Instruction Description + 7 (0x07) xor dst src0 src1 Bitwise XOR of src0 and src1 storing the result in dst. + + +Pred Sat Cond Mod Src Mod + Y N Y Y + + +Generation Src Types Dst Type + *B, *W, *D *B, *W, *D + +Format: +[(pred)] xor[.cmod] (exec_size) dst src0 src1 + +Syntax: +[(pred)] xor[.cmod] (exec_size) reg reg reg + [(pred)] xor[.cmod] (exec_size) reg reg imm32 + +Pseudocode: + Evaluate(WrEn); + for ( n = 0; n < exec_size; n++ ) { + if ( WrEn.chan[n] ) { + dst.chan[n] = src0.chan[n] ^ src1.chan[n]; + } + } + + +Description: +The xor instruction performs component-wise logic XOR operation between src0 and src1 and stores the +results in dst. +Register source operands can use source modifiers: + +  Any source modifier is numeric, optionally changing a source value s to -s, abs(s), or -abs(s) before + the XOR operation. + +This operation does not produce sign or overflow conditions. Only the .e/.z or .ne/.nz conditional +modifiers should be used. + + +Restrictions: +Source modifier is not allowed if source is an accumulator. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 224 + 7. EU Programming Guide +7.1 Assembler Pragmas + +7.2 Declarations +A register or a register region can be declared as a symbol using the following form +.declare Base=RegFile RegBase {.SubRegBase} ElementSize=ElementSize +{SrcRegion=DefaultSrcRegion} {DstRegion=DefaultDstRegion} {Type=DefaultType} +The register file, the base of the register origin and the element size (in unit of bytes) are the mandatory +parameters for a declared register region. Optionally, the base of the sub-register address, the default +source region, the default destination region and the default type can be provided in the declaration for +the symbol. +For immediate register addressing mode, the declared symbol can be used in the following Cartesian +form +(RegOff, SubRegOff)<=RegNum = RegBase+ RegOff; SubRegNum = SubRegBase+ +SubRegOff +or in the following simplified row-aligned form +(RegOff)<=RegNum = RegBase+ RegOff; SubRegNum = SubRegBase +For register-indirect-register-addressing mode, the declared symbol can be used to provide immediate +address term in the following Cartesian form +[IdxReg, RegOff, SubRegOff]<= RegNum (byte-aligned) = [IdxReg]+(RegBase+ RegOff)*32 ++ (SubRegBase + SubRegOff)*ElementSize +or in the following simplified row-aligned form +[IdxReg, RegOff]<= RegNum (byte-aligned) = [IdxReg]+(RegBase+ RegOff)*32 +or in the form without the immediate address term +[IdxReg]<= RegNum (byte-aligned) = [IdxReg]+ RegBase + + +7.2.1 Defaults and Defines +The default execution size is set according to the destination register type as the following + Destination Register Type Default Execution Size + UB | B (16) + UW | W (16) + F | UD | D (8) + +The default execution size can be overwritten globally for all instructions using +.default_execution_size(Execution_Size) +or be set according the destination register type using +.default_execution_size_Type(Execution_Size) + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 225 + The default register type can be set for all register files using +.default_register_typeType +or be set per register file using +.default_register_type_RegFileType +The default source register region for all symbols can be set using +.default_source_register_region +or be set per register type using +.default_source_register_region_type +The default destination register region for all symbols can be set using +.default_destination_register_region< HorzStride> +or be set per register type using +.default_destination_register_region_type< HorzStride> +Finally, the precompiler supports the string replacement statement of .define in the following form +.defineExpression +Notes: + +  .declare does not support nesting. In other words, each symbol in .declare must be self defined. + This would allow the pre-processor to expand all symbols in one pass. +  .define does support nesting. Only string substitution is supported (currently). +  White space within square, angle and round brackets are allowed for easy source code alignment. + + +7.2.2 Example Pragma Usages +Example: Declaration for 8x4=32-Byte Regions: +The following symbol Block can be used to address any 8x4 byte region within the Cartisian system of a +16x8 byte GRF register area starting from r0. +Declaration +// 32x4 Byte Array.declare BlockBase=r0 ElementSize=1 Region=<32;8,1>Type=b + +Fully-Expressed Instr +mov(32)?:br0.16<32;8,1>:b// r0 xxxxxxxxxxxxxxxxooooooooxxxxxxxx// r1 +xxxxxxxxxxxxxxxxooooooooxxxxxxxx// r2 xxxxxxxxxxxxxxxxooooooooxxxxxxxx// r3 +xxxxxxxxxxxxxxxxooooooooxxxxxxxx + +Short-handed Instr +Mov?:bBlock(0,16)// (0,16): RegNum=0, SubRegNum=16 +Example: Declaration for 8x1 Float Regions: +The following symbol Trans can be used to address any 8x1 float region within the +Cartisian system of a 8x4 float GRF register area starting from r5. + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 226 + Declaration +// 8x4 float Array starting at r5.declare Trans Base=r5 ElementSize=4 Region=<0;8,1> +Type=f + +Fully-Expressed Instr +mov(8)?:fr6.0<0;8,1>:f// 2nd 16x1 Row of Trans. Matrix // r5 FFFFFFFF// r6 OOOOOOOO// +r7 FFFFFFFF// r8 FFFFFFFF + +Short-handed Instr +mov?:fTrans(1) // RegNum = 5+1 = 6 +Example: Declaration for 8x1 Float Regions with 1x1 Indirect Addressing: +Trans region defined (same as in the previous example) is used in conjunction with the +address register. + +Declaration +//8x4 float data array and 16x1 word address array.declare TransBase=r5 ElementSize=4 +Region=<0;8,1> Type=f + +Fully-Expressed Instr +mov(8)?:fr[a0.0,224]<0;8,1>:f +Short-handed Instr +mov?:fTrans[a0.0,2] // [a0.0 + 5*32 + 2*32] +Example: Declaration with VxH Indirect Addressing: +The VxH register-indirect-register-addressing for Trans can be provided in the +following short-hand form + +Declaration +//8x4 float data array and word indices.declare TransBase=r5 ElementSize=4 +Region=<0;8,1> Type=f + +Fully-Expressed Instr +mov(8)?:fr[a0.0,224]<1,0>:f +Short-handed Instr +mov?:fTrans[a0.0,2]<1,0> // [a0.0+224] [a0.1+224] … [a0.7+224] +Example: Declaration with Vx1 Indirect Addressing: +As width (4) is smaller than the execution region size (8), multiple indexed registers +are used. + +Declaration +//8x4 float data array and word address array.declare TransBase=r5 ElementSize=4 +Region=<0;8,1> Type=f + +Fully-Expressed Instr +mov(8)?:fr[a0.0,244]<4,1>:f +Short-handed Instr +mov?:fTrans[a0.0,2]<4,1>// [a0.0+224] [a0.1+224] + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 227 + 7.2.3 Assembly Programming Guideline +The following program skeleton illustrates the basic structure of a typical assembly program. +// single line comment /* block comment*/ // macros, +include, etc. Are global – handled by the pre-processor// applies +to all code that follows in sequence // ------------ some kernel --------------------- +------.kernel // [REQUIRED]// ------- Register requirements ------ +-- .reg_count_total // [REQUIRED] a more direct way to specify the exact +parameters require .reg_count_payload // [REQUIRED] rather than to have to +indirectly do that by adding the// the payload and temps together to get the total +(as is the case now)// Note: no more “reg-count-temp” // -------------- Defaults ----- +---------- // these should be specified per-kernel and have only kernel- +scope // Same defaults as those already defined in the ISA doc, but just +// moved within the kernel to make each kernel completely self- +sufficient// and not impacted defaults of earlier kernels // --------- Memory +Requirements ---------// [optional] memory block info (just a placeholder for now...) +// memory block descriptor a (TBD) // memory block descriptor b +(TBD) // memory block descriptor c (TBD) // memory block descriptor +d (TBD) // ---------------- Code ---------------- .code// +[REQUIRED]// labels are code-block +scope .end_code// [REQUIRED] .end_kernel// [REQUIRED] // -- +------- next kernel ------------- // --------- next kernel ------------- // ... + + + +7.3 Usage Examples + +7.3.1 Vector Immediate +The immediate form of vector allows a constant vector to be in-lined in the instruction stream. An +immediate vector is denoted by type v as imm32:v, where the 32-bit immediate field is partitioned into 8 4- +bit subfields. Each 4-bit subfield contains a signed integer value. Therefore each 4-bit subfield has a +range of [-8, +7]. This is depicted in the following figure. +31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 +V7 V6 V5 V4 V3 V2 V1 V0 + + +7.3.1.1 Supporting DirectX 10 Pixel Shader Indexing +When a DirectX 10 Pixel Shader program is converted to run on GEN in channel-serial mode at 16 pixels +in parallel, the per-pixel index must be translated into 16 indices with per channel offset. The creation of +the per-channel offset can be achieved using the vector immediate. +Consider a generic DirectX 10 Pixel Shader instruction in the form of +opr4r[ind]r2 +and assume that r0-r1 contain the 16 indices packed every other words, and r2-r3 contains source 1 and +r4-r5 contain the destination. This instruction can be converted into the following GEN instructions. The +corresponding operations are illustrated in Supporting DirectX 10 Pixel Shader Indexing. +mov (16) r11.0<1>:w 0x01234567:v// assigning a ramp vector, repeated once +mul (16)acc0:wr11.0<0;16,1>:w4:w// expand ramp range to 4 bytes per step +mac (16)r10.0<1>:wr0.0<16;8,2>:w32:w// r10 = index*32 + 0|4|…|28|0|4…|28 + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 228 + mov (8)a0.0<1>:wr10.0<0;8,1>:w +op (8)r4.0<1>:fr[a0.0]<1,0>:fr2.0<0;8,1>:w// Operate on the first half +mov (8)a0.0<1>:wr10.8<0;8,1>:w// Index values are off by a reg (32b) +op (8)r5.0<1>:fr[a0.0+32]<1,0>:fr3.0<0;8,1>:w// Operate on the second half. + +Pixel Shader example using vector immediate. + + + + +Without vector immediate support, such translation has to either use a long sequence of scalar +instructions which is very inefficient or use a constant load which requires additional constant to be +managed in memory. + +7.3.1.2 Supporting OpenGL Vertex Shader Instruction SWZ +When an OpenGL Vertex Shader program is converted to run on GEN in Vertex Pair, i.e. two 4-wide +vectors in parallel, the special OpenGL Shader instruction SWZ (Swizzle) needs to be emulated. OpenGL +SWZ instruction uses an extended swizzle control field that, in addition to the 4-wide full swizzle control, +also includes constant 0 and 1 replacement as well as per channel sign reversal. The later two are not +supported by the GEN native instruction. The vector immediate can significantly reduce the overhead of +emulating such OpenGL instruction. +Consider an OpenGL Shader instruction in the form of +SWZr1r0.0-zx-1// Expected results: r1.x = 0; r1.y = -r0.z; r1.z = r0.x; r1.w = -1 +It can be emulated by the following three GEN instructions. +mul(8)r1.0<1>:fr0.xzxz0x1F111F11:v// Constant vector of (1 -1 1 1 1 -1 1 1) +mov (1)f0.08b’10011001// Set flag & masked out channels y and z +(f0.0)mov(8) r1.0<1>:f 0x000F000F:v// Constant vector of (0 0 0 -1 0 0 0 -1) +In case that only 0, 1, -1 channel replacement is used and there is no signed swizzle, it may be emulated +in two GEN instructions. This is illustrated by the following example: +OpenGL: + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 229 + SWZr1r0.0zx-1// Expected results: r1.x = 0; r1.y = r0.z; r1.z = r0.x; r1.w = -1 +GEN: +mov (1)f0.08b’01100110// Set flag and masked out channels x and w +(f0.0)sel (8) r1.0<1>:f r0.yzxy0x000F000F:v// Constant vector of (0 0 0 -1 0 0 0 -1) + + +7.3.2 Destination Mask for DP4 and Destination Dependency Control +The following example demonstrates the use of destination mask mode of floating point dot-product +instruction as well as the use of destination dependency control to improve performance (i.e., avoiding +unnecessary thread switch due to possible false dependencies). +Consider a generic DirectX 10 Vertex Shader macro of matrix-vector product that is implemented on GEN +in the pair of 4-component vector mode. The DirectX 10 equivalent Shader instructions are as the +following. +dp4 r5.x r0 r4 +dp4 r5.y r1 r4 +dp4 r5.z r2 r4 +dp4 r5.w r3 r4 +With destination dependency control, the GEN instructions are as the following. The first instruction in the +sequence checks for the destination dependency, but does not clear the dependency bit. The subsequent +two instructions would do neither of them. The last instruction avoids checking the destination +dependency, but at completion, it clears the destination scoreboard. It ensures that the content of the +destination register is coherent, if any of the following instructions uses the same register as source. +dp4 (8) r5.0<1>.x:f r0.0<4;4,1>:f r4.0<4;4,1>:f {NoDDClr} +dp4 (8) r5.0<1>.y:f r1.0<4;4,1>:f r4.0<4;4,1>:f {NoDDClr, NoDDCChk} +dp4 (8) r5.0<1>.z:f r2.0<4;4,1>:f r4.0<4;4,1>:f {NoDDClr, NoDDCChk} +dp4 (8) r5.0<1>.w:f r3.0<4;4,1>:f r4.0<4;4,1>:f {NoDDChk} +Just as a comparison, IF GEN DP4 implies reduction at the destination; additional shifted moves are +required to achieve the same results. The corresponding codes are as the following. The lower +performance due to the additional three move instruction as well as added back-to-back dependencies +shows that why we choose to implement the destination channel replication for floating point DP4. +dp4 (8) r5.0<1>.y:f r1.0<4;4,1>:f r4.0<4;4,1>:f +mov (1) r5.1<1>:f r8.0<1;1,1>:f +dp4 (8) r5.0<1>.z:f r2.0<4;4,1>:f r4.0<4;4,1>:f +mov (1) r5.2<1>:f r8.0<1;1,1>:f +dp4 (8) r5.0<1>.w:f r3.0<4;4,1>:f r4.0<4;4,1>:f +mov (1) r5.3<1>:f r8.0<1;1,1>:f +dp4 (8) r5.0<1>.x:f r0.0<4;4,1>:f r4.0<4;4,1>:f + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 230 + 7.3.3 Null Register as the Destination +Null register can be used as the destination for most of the instructions. Here are some example usages. + +  Null as destination for regular ALU instructions: As all ALU instructions can be configured to update + the flag registers using the conditional modifiers, it is not necessary to have a destination register if + the programmer only cares about the conditionals of the operation. In that case, a null in the + destination operand field saves register space as well as one less dependency checking. +  Null as the destination for SEND/STOR instructions: for the send instruction that only send + messages out to an external unit and does not require any return data or feedback, a null in the + destination register field signifies the case. + o One extension of such case is that even though the operation does not have any + return values, a return phase with no payload but simply updating the scoreboard flag + for a non-null register can provide a signaling mechanism between the thread and the + target external unit. One application of this usage is to allow software to manage the + coherency of shared memory resources such like the many caches in the system + (particularly, valuable for read/write caches). This is not currently the POR for GEN + though. + + +7.3.4 Use of LINE Instruction +LINE instruction is specifically designed to speed up floating point vector/matrix computation when a +program operates in channel serial. +The following example demonstrates how to use LINE instruction to compute Line Equations for DirectX +10 Pixel Shader. In this example, 2 sets of (Cx#, Cy#, Don’t Care, C0#) 4-tuple coefficient vectors are +stored in registers R1. + R1: Cx0 Cy0 DC Co0 Cx1 Cy1 DC Co1 +8 sets of coordinate 2-D vectors (X, Y) are stored in R2 and R3 in the channel serial mode as + R2: X0 X1 … X7 + R3: Y0 Y1 … Y7 +The objective is to compute the following two line equations for each set of 2D coordinate and store the +results in R4 and R5 as + R4: (X0*Cx0 + Y0*Cy0+Co0) ... (X7*Cx0 + Y7*Cy0+Co0) + R5: (X0*Cx1 + Y0*Cy1+Co1) ... (X7*Cx1 + Y7*Cy1+Co1) + +Example LINE Equations +//------------------------------------------------------------------- +// Example compute LINE equation in channel serial scenario +//------------------------------------------------------------------- +line (8) acc:f r1<0;1,0>:f r2<0;8,1>:f// does acc = X# * Cx0 + Co0 +mac (8) r4<1>:f r1.1<0;1,0>:f r3<0;8,1>:f// does r4.# = Y# * Cy0 + acc.# +line (8) acc:f r1<0;1,0>:f r2<0;8,1>:f// does acc = X# * Cx0 + Co0 +mac (8) r4<1>:f r1.1<0;1,0>:f r3<0;8,1>:f// does r4.# = Y# * Cy0 + acc.# + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 231 + The next example is to compute homogeneous dot product for OpenGL pixel shader running in Channel +Serial. In this example, an original OpenGL PS instruction is like + dph R2.x R0 R1 +With register remapping, we can store the input coefficient vector R0 in original format in r0, but 8 sets of +input coordinate vectors in channel serial format in r2, r3, r4 and r5, and the destination R2.x component +in r6. + r0: Cx0 Cy0 Cz0 Co0 DC DC DC DC + r2: X0 X1 … X7 + r3: Y0 Y1 … Y7 + r4: Z0 Z1 … Z7 + r5: W0 W1 … W7 +The objective is to compute the following DPH equations and store the results in r6 as + R6: (X0*Cx0+Y0*Cy0+Z0*Cz0+Co0) ... (X7*Cx0+Y7*Cy0+Z7*Cz0+Co0) + +Example Homogeneous Dot Product in Channel Serial +//------------------------------------------------------------------- +// Example compute homogeneous dot product in channel serial scenario +//------------------------------------------------------------------- +line (8) acc:f r0<0;1,0>:f r2<0;8,1>:f// does acc = X# * Cx0 + Co0 +mac (8) acc:f r0.1<0;1,0>:f r3<0;8,1>:f// does acc.# = Y# * Cy0 + acc.# +mac (8) r6<1>:f r0.2<0;1,0>:f r4<0;8,1>:f// does r6.# = Z# * Cz0 + acc.# + + +7.3.5 Mask for SEND Instruction +Execution mask (upto 16 bits) for the SEND instruction is transferred to the Shared Function. This +provides optimized implementation of DirectX Shader instructions. + +7.3.5.1 Channel Enables for Extended Math Unit +The following example demonstrates how to use the SEND instruction to get service from the Extended +Math unit. +Let’s consider COS instruction in DirectX 10 in the following form +[([!]p0.{select|any|all})] cos[_sat] dest[.mask], [-]src0[_abs][.swizzle] +For a SIMD4x2 VS implementation with the following register mappings +p0 =>f0.0 +src0 =>r0 +dest =>r1 +The equivalent GEN instruction is as the following +[([!]f0.0.{select|any4h|all4h})] SEND (8) r1[.mask]:f m0 [-][(abs)]r0[.swizzle]:f MATHBOX|COS[|SAT] + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 232 + If the source swizzle is replication, the message description field can be modified to +MATHBOX|COS|SCALAR to take advantage of the fast mode (scalar mode) supported by the Extended +Math. The implied move of the SEND instruction is equivalent to the following instruction: +MOV (8) m0[.mask]:f [-][(abs)]r0.0[.swizzle]:f {NoMask} +For a SIMD16 PS implementation, the register mappings are as the followings +p0 =>f0…f3 // in order of R, G, B, A +src0 =>r0,r1; r2,r3; r4,r5; r6,r7 +dest =>r8,r9; r10,r11; r12,r13; r14,r15 +There are several ways to translate the DirectX instruction, depending on the operand/instruction +modifiers present in the DirectX instruction. If predicate is not present and the source swizzle is +replication, say, src0.y, which is r2-r3, the translation could be as the following instructions +send (8) r8:f m0 -(abs)r2:f MATHBOX|COS +send (8) r9:f m1 -(abs)r3:f MATHBOX|COS {SecHalf}// use the second half of 8 flag bits +mov (16) r10:fr8:f // All destination color chan’s are same +mov (16) r12:fr8:f // MOV is faster than most MathBox func’s +mov (16) r14:fr8:f // These MOV’s are compressed instructions +Notice that instead of issuing Extended Math messages with the same input data, destination color +channel replication is performed by the MOV instructions. This is faster for the thread for most cases as +many Extended Math functions consume multiple cycles. This also conserves message bus bandwidth as +well as the usage of the shared resource – Extended Math. The destination mask in the DirectX 10 +instruction indicates which of the r8 to r15 registers are updated. If the source swizzle is not replication, +there will be 8 SEND instructions. +With predication on, if the predication modifier is p0.select, translation is to take the selected flag register +f#. The other predication modifiers ‘.any’ and ‘.all’ are translated into ‘.any4v’ and ‘.all4v’, respectively. +Notice that with predication on, it is not required to run all 4 pixels in a subspan in the same way, so no +need to enforce .any4h/.any4v. The following example shows the instruction with predication (but without +.select modifier). +(f0[.any4v|.all4v]) send (8) r8:f m0 -(abs)r2:f MATHBOX|COS +(f0[.any4v|.all4v]) send (8) r9:f m1 -(abs)r3:f MATHBOX|COS {SecHalf} +(f1[.any4v|.all4v]) mov (16) r10:fr8:f // All destination color chan’s are same +(f2[.any4v|.all4v]) mov (16) r12:fr8:f // MOV is faster than most MathBox func’s +(f3[.any4v|.all4v]) mov (16) r14:fr8:f // These MOV’s are compressed instructions +The same instructions works also for predication with select component modifier. We simply replase f0 to +f3 above by the selected flag register, say, f1. The modifier of any4h/all4v would also work. + +7.3.5.2 Channel Enables for Scratch Memory +The following example demonstrates how to use the SEND instruction to get service from the Data Port +for scratch memory access. +Let’s consider general instruction in DirectX 10 that uses scratch memory as a source operand +[([!]p0.{select|any|all})] add dest[.mask], [-]src0[_abs][.swizzle], [-]src1[_abs][.swizzle] + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 233 + For a SIMD4x2 VS implementation with the following register mappings +p0 =>f0 +src0 =>r0 +src1 =>s2 / r10 +dest =>r1 +In this example, the scratch memory offset is provided by an immediate and a GRF register r10 is used as +the intermediate GRF location for spill/fill of scratch buffer accesses. This arithmetic instruction is +converted into a Data Port read followed by an arithmetic instruction. +mov (8) r3:d r0:d {NoMask}// move scratch base address to be assembled with offset values +mov (1) r3.0:d 2*32 {NoMask}// s2 for vertex 0 +mov (1) r3.1:d 2*32+16 {NoMask}// s2 for vertex 1 +send (8) r10 m0 r3 DATAPORT|RC|READ_SIMD2 +[([!]f0.{sel|any4h|all4h})] add (8) r1[.mask]:f [-][(abs)]r0[.swizzle]:f [-][(abs)]r10[.swizzle]:f +So if scratch register is the source, there is no need to use the channel enable side band. This is also true +for channel-serial PS cases. +Now, let’s consider the case when a scratch register is the destination of an instruction. +p0 =>f0 +src0 =>r0 +src1 =>r1 +dest =>s2 / r10 +We have +add (8) m1:f [-][(abs)]r0[.swizzle]:f [-][(abs)]r1[.swizzle]:f +mov (8) r3:d r0:d {NoMask}// move scratch base address to be assembled with offset values +mov (1) r3.0:d 2*32 {NoMask}// s2 for vertex 0 +mov (1) r3.1:d 2*32+16 {NoMask}// s2 for vertex 1 +[([!]f0.{sel|any4h|all4h})] send (8) null[.mask] m0 r3 DATAPORT|RC|WRITE_SIMD2 + + +Notice that with a null as the posted destination register, we are able to transfer the [.mask] over the +message channel enables. In many cases for scratch memory assess, a write-with-commit is required, +therefore, the posted destination register could be r10. +Now, let’s consider the PS case when a scratch register is the destination of an instruction. +p0 =>f0-f4 +src0 =>r0-r7 +src1 =>r8-r15 +dest =>s16-s23 / r16-r23 +When predication is not on (or predication with swizzle control on), we have +add (16) m4:f [-][(abs)]r0/2/4/6_BasedOnSwizzle:f [-][(abs)] r8/10/12/14_BasedOnSwizzle:f + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 234 + add (16) m6:f [-][(abs)]r0/2/4/6_BasedOnSwizzle:f [-][(abs)] r8/10/12/14_BasedOnSwizzle:f +add (16) m8:f [-][(abs)]r0/2/4/6_BasedOnSwizzle:f [-][(abs)] r8/10/12/14_BasedOnSwizzle:f +add (16) m10:f [-][(abs)]r0/2/4/6_BasedOnSwizzle:f [-][(abs)] r8/10/12/14_BasedOnSwizzle:f +mov (8) r3:d 0x76543210:v {NoMask}// ramp function +mul (16) acc0:d r3:d 16 {NoMask}// ramp function +add (8) acc0:d acc0:d 64 {NoMask,SecHalf}// ramp function +add (16) m2:d acc0:d 2*256 {NoMask}// ramp function +send (16) null m1 r3 DATAPORT|RC|WRITE_SIMD16 + + +As there is no bit left from the unit specified descriptor field, the 4 bit mask must be put into the header +field in m1, which requires at least two more instructions. +Alternatively, or for the case that predication without modifier is on, we can do a read-modify-write. +mov (8) r3:d 0x76543210:v {NoMask}// ramp function +mul (16) acc0:d r3:d 16 {NoMask}// ramp function +add (8) acc0:d acc0:d 64 {NoMask,SecHalf}// ramp function +add (16) m2:d acc0:d 2*256 {NoMask}// ramp function +send (16) r16 m1 r3 DATAPORT|RC|READ_SIMD16 // read from scratch + + +// some of the following four instructions may be omitted based on [.mask] field +[([!]f0.{sel|any4v|all4v})] add (16) r16:f [-][(abs)]r0/2/4/6_BasedOnSwizzle:f [-][(abs)] +r8/10/12/14_BasedOnSwizzle:f +[([!]f0.{sel|any4v|all4v})] add (16) r18:f [-][(abs)]r0/2/4/6_BasedOnSwizzle:f [-][(abs)] +r8/10/12/14_BasedOnSwizzle:f +[([!]f0.{sel|any4v|all4v})] add (16) r20:f [-][(abs)]r0/2/4/6_BasedOnSwizzle:f [-][(abs)] +r8/10/12/14_BasedOnSwizzle:f +[([!]f0.{sel|any4v|all4v})] add (16) r22:f [-][(abs)]r0/2/4/6_BasedOnSwizzle:f [-][(abs)] +r8/10/12/14_BasedOnSwizzle:f +mov (16) m4:f r16:f {NoMask} +mov (16) m6:f r18:f {NoMask} +mov (16) m8:f r20:f {NoMask} +mov (16) m10:f r22:f {NoMask} +send (16) null m1 null DATAPORT|RC|WRITE_SIMD16 {NoMask}// write back to scratch + + +7.3.6 Flow Control Instructions +Unconditional branches are performed through direct manipulation of the 32-bit IP architectural register. +For example: +mov (1) IP // jump absoluteadd (1) IP IP // jump relative + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 235 + Note that jump distances are specified in terms of bytes, as opposed to instruction counts in the case of +break, halt, etc. To minimize confusion, an assembler-only instruction ‘jmp ’, where + is an immediate term, may be defined which takes an instruction count for a distance. The +jmp pseudo-opcode can be mapped to an “add (1) ip ip * 16” instruction. +IP is aligned to an 8-byte boundary, thus the 3 LSBs are not maintained in the IP architectural register +and should not be relied upon by software. +IP, when used as a source operand, reflects the memory address of the instruction in which it is used. +The following are examples illustrating the use of IP: +add (1) IP4*16// jumps to HERE_1 +add (1) IP0x35// jumps to HERE_1 (4 lsb’s don’t-care) + + + +HERE_1:HERE_2: + + add (1) IP -2*16// jumps to HERE_2 ... + add (1) IP 0// infinite loopadd (1) IP 0xF// infinite loop ... + +Note for Assembler: The if/iff/else/while/break instructions identify relative addresses as the targets of an +implicit jump associated with the instruction. These are optional in the assembly syntax as the jitter can +determine the location of the matching instruction (e.g. matching endif instruction for a given if +instruction). + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 236 + 7.3.7 Execution Masking + +7.3.7.1 Branching +Example. If / Else / EndIf +//------------------------------------------------------------------- +// Example if/else/endif scenario +// “if (r5==r4) ...else ... end-if” +//------------------------------------------------------------------- +... +cmp.e.f0 (8) null r5 r4// does r5 == r4? +(f0) if (8) HERE_1// “if” part - save then update IMASK; +// or goto the ‘else’ if all false +... +... +HERE_1:// now do the ‘else’ part +else (8) HERE_2// “else” part - invert IMASK +// or goto the ‘endif’ if all false +... +... +HERE_2: +endif// “end-if” part – restore IMASK +....// and continue... +If it is known that the code has no nested conditionals, a predicate can be used for a lower overhead, +more efficient if/else/endif. (One must consider the probability of all channels taking the same branch, and +the number of instructions under the if/else blocks as to which conditional method, predicate or mask, is +most efficient). + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 237 + 7.3.7.2 Fast-If +Below is an example of a fast-if instruction. For the ‘iff’ instruction, only and iff-endif construct is allowed, +as opposed to a if-else-endif. Note that the target address for branching if all enabled channels fail is one +instruction beyond the endif, as the ‘iff’ does not push and update the IMask unless the branch is taken +for at least one execution channel. + +Example Fast If +//------------------------------------------------------------------- +// Example – Fast If +//One instruction overhead conditional +//------------------------------------------------------------------- +... +cmp.e.f0 (8) null r5 r4// any flag update +... +(f0)iff (8) HERE_1// “fast-if” – only pushes IMask; +// if execution falls through, +// else go to HERE_1 +... +... +endif// “end-if” part – restores IMask +HERE_1: +...// and continue... + + +7.3.7.3 Cascade Branching +As there is no ‘elseif’ instruction, a C-like cascade branching such as if / elseif / else / endif, can be +realized using the basic building blocks of if / else / endif as shown in the following example. Notice that +two ‘endif’s’ are required in order to pop the IStack correctly. + +Example. If / Elseif / Else / EndIf +//------------------------------------------------------------------- +// Example if/elseif/else/endif scenario +// “if (r5==r4) ...elseif (r6>r7) else ... end-if” +//------------------------------------------------------------------- +... +cmp.e.f0 (8) null r5 r4// does r5 == r4? +(f0)if (8) HERE_1// “if” part - save then update IMask; +// or go to the ‘else’ part if all false +... + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 238 + ... +HERE_1:// now do the ‘else’ part +else (8) HERE_2// “else if” part - invert IMask +// or go to the ‘else’ part if all false +cmp.g.f0 (8) null r6 r7// is r6 > r7? +(f0)if (8) HERE_3// “if” part - save then update IMask; +// or go to the ‘else’ part if all false +... +... +HERE_3:// now do the ‘else’ part +else (8) HERE_4// “else” part - invert IMask +// or go to the ‘end-if’ part if all false +... +... +HERE_4: +endif// “end-if” part – restore IMask for elseif +HERE_2: +endif// “end-if” part – restore IMask for if +.... + +7.3.7.4 Compound Branches +Compound branches are supported through the ability logically combine flag registers for each +intermediate result. + +Example Compound Branch +//------------------------------------------------------------------- +// Example: “if (r0 > r1) OR (r2 <= r3)” +//------------------------------------------------------------------- +... +cmp.g.f0 (8) null r0:d r1:d// r0 > r1? +cmp.le.f1 (8) null r2:d r3:d// r2 <= r3? +or (1) f0:w f0:w f1:w// combine f0 and f1 +(f0) if (8) HERE_1// Can now do normal if/else +... +... +HERE_1:endif + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 239 + ... + +Example Compound Branch Using 'Any' or 'All' +//------------------------------------------------------------------- +// Example: assuming we’re doing a channel-serial vector in r0-r3 +// We want to know if all components of the vector are > 0x80 +//------------------------------------------------------------------- +... +cmp.g.f0 (16) null r0 0x80// r0 > 0x80? +cmp.g.f1 (16) null r1 0x80// r1 > 0x80? +cmp.g.f2 (16) null r2 0x80// r0 > 0x80? +cmp.g.f3 (16) null r3 0x80// r1 > 0x80? + (f0.all4v) if (16) HERE_1 +... +...// code executed only for those channels +...// where per-channel r0,r1,r2,r3 all > 0x80 +... +HERE_1:endif +...// and continue... + +7.3.7.5 Looping +Due to GEN’s SIMD-16 architecture, it must support the case of up to 16 loops running in parallel. These +must be handled as independent loops, each with its own loop-exit condition which could occur after a +different number of loop iterations. To account for each channel’s progress, a 16b loop-mask ‘LMask’ is +defined with 1b associated to each execution channel. This mask keeps track of which channels remain +active inside a loop block. +Basic Do-While Loop +Looping illustrates the most basic loop. Two operations must be accomplished before loop entry. (1) Prior +to loop entry, there is some subset of enabled channels as dictated by the code sequence prior. In +general, the active status of each channel is indicated in the virtual EMask any point in time. These active +channels will become the channels over which the loop is run, and LMask must be initialized with the +EMask value. (2) Since a given loop may be nested within another loop, the previous LMask & CMask +must be saved to the LStack for later restoration upon loop completion. The ‘msave’ instruction performs +both the save and update in a single instruction, and thus all loop-blocks should be fronted with a “msave +LStack LMask” and “msave LStack CMask” operation. +Note that the LMask and CMask share the same mask-stack. Thus, CMask must always be a 1’s-subset +of the LMask for proper stack operation. This is the case if CMask is updated to LMask each pass +through the loop (see Looping) and through the ‘break’ instruction updating both masks. +Each pass through the loop, a loop terminating operation must be evaluated and stored in a flag register. +This condition must be evaluated on a channel-by-channel basis as exemplified: +cmp.z.f0(8) null r2 d3// any operation that updates a flag + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 240 + The result of this operation sets a bit per channel in the specified flag register, which is then used in the +‘while’ instruction. As loops are performed, channels may become disabled as their termination condition +is met. +‘While’ termination is determined on a channel-by-channel basis by the logical AND of corresponding bit +positions of AMask, CMask and the specified flag. If the result is ‘1’ the channel remains enabled for the +next pass of the loop; if ‘0’ the channel is disabled until loop fall-through. The ‘while’ instruction causes +the LMask to be updated with the latest result of enabled channels. If any channel remains enabled +(LMask != ...000b), an additional pass through the loop is made. Once a channel is terminated for the +loop operation, it remains terminated until the loop is complete for all channels. +Upon fall through, the ‘while’ instruction causes the previously saved LMask & CMask to be popped from +the LStack, enabling execution on the same subset of channels enabled prior to loop entry (unless a +channel had been otherwise terminate inside the loop via ‘halt’). + +Example Basic Loop Construct +//-------------------------------------------------- +//Example: Basic do-while loop structure +//-------------------------------------------------- +... +do// save L/CMask & update +BEGIN_LOOP: +mov (1) CMask LMask{NoMask}// update CMask for this pass +... +... + +(

)while (8) BEGIN_LOOP// cond. branch +// + restores LMask on fall-through +... +Do-While Loop with Break +A loop may also be terminated for any channel via the ‘break’ instruction. The ‘break’ instruction causes +the corresponding bit positions of enabled channels to be cleared in the LMask. If the updated LMask = +...000b, a branch is made to the specified instruction location. An example is shown below in which the +‘break’ is at the same conditional-nesting level as the terminating ‘while’. Its primary value may simply be +to support a “do...break.. while (true)” –type structure for a more direct 1:1 translation from higher-level +source code. + +Example Loop Construct With Non-Nested ‘Break’ +//------------------------------------------------------------- +//Example: While-true loop +//------------------------------------------------------------- +#define BrkCode(i,d)(i << 16) + d +do// save L/CMask & update + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 241 + BEGIN_LOOP: +mov (1) CMask LMask{NoMask} // update CMask for this pass +... + +(

)break (8) BrkCode(0,HERE_1)// Restores LMask when all +// channels complete loop. +... +... +while (8) BEGIN_LOOP// while true +HERE_1: +... +A break condition may occur from various levels of nested-ifs. This gives rise to the possibility that a the +loop may terminate from within nested ‘if’s, and due to the jump inherent in the ‘break’ instruction, the +associated ‘endif’s are not encountered to clean-up the IStack as nesting levels are exited. + +Example Loop Construct With ‘Break’ From Within Nested If’s +//------------------------------------------------------------- +//Example: General Loop Structure w/ break inside if’s +//------------------------------------------------------------- +#define BrkCode(i,d)(i << 16) + d +do// save L/CMask & update +BEGIN_LOOP: +mov (1) CMask LMask{NoMask} // update CMask for this pass +... +if ... +if ... +if ... +... +(

)break (8) BrkCode(3,HERE_1)// we’re 3 levels deep, so +... +endif +endif +endif +... +(

)break (8) BrkCode(0,HERE_1) +... + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 242 + while (8) BEGIN_LOOP// cond. branch +// + restores C/LMask on fall-through +HERE_1: +Do-While Loop with Continue +A continue instruction ‘cont’ is provided skip to the next iteration of the loop. Because not all channels +participating in the loop may be enabled at the time this instruction is executed, some channels may +require continuation of the loop. A special mask ‘CMask’ is defined which accounts for channels +temporarily disabled for the current loop pass. +Since loops may nested, the CMask must be saved and restored around a loop similar to LMask. Since +the CMask value within a properly constructed loop is always a subset of the LMask, it can share the +LStack for storage, so long as it is pushed after LMask as shown in Looping. This save/restore operations +are not required if the loop being entered does not have any occurrence of a continue instruction. + +Example Do-While with Continue +//------------------------------------------------------------- +//Example: General Loop Structure w/ basic break and cont. +//------------------------------------------------------------- +#define ContCode(i,d)(i << 16) + d +do// save L/CMask & update +BEGIN_LOOP: +mov (1) CMask EMask// re-initialize CMask for this pass +... +... +(

) cont (8) ContCode(0,HERE_1) +... +HERE_1: +(

)while (8) BEGIN_LOOP// cond. branch +// + restores C/LMask on fall-through +... + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 243 + 7.3.7.6 Indexed Jump +Example Indexed Jump +//------------------------------------------------------------------- + // Code example shows the use of jmpi to perform a case statement + // of any number of options in 3 jumps + //------------------------------------------------------------------- +.default_execution_size 8 + ... +jmpi r0<0,1,0>// jump relative, based on r0.a.x +// ----- Jump Table ------ +jmp HERE_0// redirect for case 0 +jmp HERE_1// redirect for case 1 +jmp HERE_2// redirect for case 2 +jmp HERE_3// redirect for case 3 + ... +HERE_0:// ... case 0 ... +... + jmp DONE +HERE_1:// ... case 1 ... +... + jmp DONE +HERE_2:// ... case 2 ... +... + jmp DONE +HERE_3:// ... case 3 ... +... +DONE: +...// and continue... + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 244 + Revision History +Revision Number Description Revision Date + +1.0 First 2012 OpenSource edition May 2012 + + + + + §§ + + + + +Doc Ref #: IHD-OS-V4 Pt 3 – 05 12 5/31/2012 245 + \ No newline at end of file diff --git a/encode/.icd-vendors/pocl.icd b/encode/.icd-vendors/pocl.icd new file mode 120000 index 0000000..66b0e83 --- /dev/null +++ b/encode/.icd-vendors/pocl.icd @@ -0,0 +1 @@ +/nix/store/jr8wwd19z6yvsfxykva6brazipm06r9b-pocl-7.1/etc/OpenCL/vendors/pocl.icd \ No newline at end of file diff --git a/encode/hasvk_encode_test b/encode/hasvk_encode_test new file mode 100755 index 0000000..e106e63 Binary files /dev/null and b/encode/hasvk_encode_test differ diff --git a/encode/hasvk_encode_test.c b/encode/hasvk_encode_test.c new file mode 100644 index 0000000..79b6c3f --- /dev/null +++ b/encode/hasvk_encode_test.c @@ -0,0 +1,964 @@ +/* vulkan H.264 encode test for hasvk. + * ./hasvk_encode_test # flat-gray 176x144, dumps /tmp/hasvk_enc_out.h264 + * HASVK_ENC_GRADIENT=1 ./hasvk_encode_test # luma gradient (real residuals) + * HASVK_ENC_GRADIENT=1 HASVK_ENC_CHROMA=1 ./... # + chroma gradient + * validate the output with ffmpeg: + * ffmpeg -i /tmp/hasvk_enc_out.h264 -f rawvideo -pix_fmt yuv420p out.yuv + * The stream prepends the driver's own SPS/PPS + * (vkGetEncodedVideoSessionParametersKHR) so it decodes standalone. + */ +#include +#include +#include +#include + +#include +#include +#include + +#define CHECK(x) do { \ + VkResult _r = (x); \ + if (_r != VK_SUCCESS) { \ + fprintf(stderr, "FAIL %s:%d: %s -> %d\n", __FILE__, __LINE__, #x, _r); \ + exit(1); \ + } \ + } while (0) + +#define WIDTH 176 +#define HEIGHT 144 +#define WIDTH_MBS (WIDTH / 16) +#define HEIGHT_MBS (HEIGHT / 16) +#define LUMA_SZ (WIDTH * HEIGHT) +#define CHROMA_SZ ((WIDTH / 2) * (HEIGHT / 2) * 2) +#define FRAME_SZ (LUMA_SZ + CHROMA_SZ) + +static int +load_frame(const char *path, int idx, int i420, uint8_t *dst) +{ + FILE *f = fopen(path, "rb"); + if (!f) { fprintf(stderr, "cannot open '%s'\n", path); return 0; } + if (fseek(f, (long)idx * FRAME_SZ, SEEK_SET) != 0) { + fprintf(stderr, "'%s': cannot seek to frame %d\n", path, idx); + fclose(f); return 0; + } + uint8_t buf[FRAME_SZ]; + size_t n = fread(buf, 1, FRAME_SZ, f); + fclose(f); + if (n != FRAME_SZ) { + fprintf(stderr, "'%s': frame %d short read (%zu of %d)\n", path, idx, n, FRAME_SZ); + return 0; + } + memcpy(dst, buf, LUMA_SZ); + if (i420) { + const uint8_t *cb = buf + LUMA_SZ, *cr = cb + CHROMA_SZ / 2; + for (int i = 0; i < CHROMA_SZ / 2; i++) { + dst[LUMA_SZ + i * 2 + 0] = cb[i]; + dst[LUMA_SZ + i * 2 + 1] = cr[i]; + } + } else { + memcpy(dst + LUMA_SZ, buf + LUMA_SZ, CHROMA_SZ); + } + return 1; +} + +static void +shift_frame(const uint8_t *src, uint8_t *dst, int dx, int dy) +{ + for (int y = 0; y < HEIGHT; y++) { + int sy = y - dy; sy = sy < 0 ? 0 : (sy >= HEIGHT ? HEIGHT - 1 : sy); + for (int x = 0; x < WIDTH; x++) { + int sx = x - dx; sx = sx < 0 ? 0 : (sx >= WIDTH ? WIDTH - 1 : sx); + dst[y * WIDTH + x] = src[sy * WIDTH + sx]; + } + } + int cw = WIDTH / 2, ch = HEIGHT / 2, cdx = dx / 2, cdy = dy / 2; + for (int y = 0; y < ch; y++) { + int sy = y - cdy; sy = sy < 0 ? 0 : (sy >= ch ? ch - 1 : sy); + for (int x = 0; x < cw; x++) { + int sx = x - cdx; sx = sx < 0 ? 0 : (sx >= cw ? cw - 1 : sx); + dst[LUMA_SZ + (y * cw + x) * 2 + 0] = src[LUMA_SZ + (sy * cw + sx) * 2 + 0]; + dst[LUMA_SZ + (y * cw + x) * 2 + 1] = src[LUMA_SZ + (sy * cw + sx) * 2 + 1]; + } + } +} + +static PFN_vkGetPhysicalDeviceVideoCapabilitiesKHR pGetPhysicalDeviceVideoCapabilitiesKHR; +static PFN_vkGetPhysicalDeviceVideoFormatPropertiesKHR pGetPhysicalDeviceVideoFormatPropertiesKHR; +static PFN_vkCreateVideoSessionKHR pCreateVideoSessionKHR; +static PFN_vkDestroyVideoSessionKHR pDestroyVideoSessionKHR; +static PFN_vkGetVideoSessionMemoryRequirementsKHR pGetVideoSessionMemoryRequirementsKHR; +static PFN_vkBindVideoSessionMemoryKHR pBindVideoSessionMemoryKHR; +static PFN_vkCreateVideoSessionParametersKHR pCreateVideoSessionParametersKHR; +static PFN_vkDestroyVideoSessionParametersKHR pDestroyVideoSessionParametersKHR; +static PFN_vkGetEncodedVideoSessionParametersKHR pGetEncodedVideoSessionParametersKHR; +static PFN_vkCmdBeginVideoCodingKHR pCmdBeginVideoCodingKHR; +static PFN_vkCmdEndVideoCodingKHR pCmdEndVideoCodingKHR; +static PFN_vkCmdEncodeVideoKHR pCmdEncodeVideoKHR; + +static uint32_t +find_memory_type(VkPhysicalDeviceMemoryProperties *mp, uint32_t type_bits, VkMemoryPropertyFlags want) +{ + for (uint32_t i = 0; i < mp->memoryTypeCount; i++) { + if ((type_bits & (1u << i)) && + (mp->memoryTypes[i].propertyFlags & want) == want) + return i; + } + /* fall back: any type in the mask */ + for (uint32_t i = 0; i < mp->memoryTypeCount; i++) { + if (type_bits & (1u << i)) + return i; + } + fprintf(stderr, "FAIL: no matching memory type for bits 0x%x\n", type_bits); + exit(1); +} + +static VkDeviceMemory +alloc_and_bind_buffer(VkDevice dev, VkPhysicalDeviceMemoryProperties *mp, + VkBuffer buf, VkMemoryPropertyFlags want) +{ + VkMemoryRequirements req; + vkGetBufferMemoryRequirements(dev, buf, &req); + VkMemoryAllocateInfo ai = { + .sType = VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO, + .allocationSize = req.size, + .memoryTypeIndex = find_memory_type(mp, req.memoryTypeBits, want), + }; + VkDeviceMemory mem; + CHECK(vkAllocateMemory(dev, &ai, NULL, &mem)); + CHECK(vkBindBufferMemory(dev, buf, mem, 0)); + return mem; +} + +static VkDeviceMemory +alloc_and_bind_image(VkDevice dev, VkPhysicalDeviceMemoryProperties *mp, VkImage img) +{ + VkMemoryRequirements req; + vkGetImageMemoryRequirements(dev, img, &req); + VkMemoryAllocateInfo ai = { + .sType = VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO, + .allocationSize = req.size, + .memoryTypeIndex = find_memory_type(mp, req.memoryTypeBits, VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT), + }; + VkDeviceMemory mem; + CHECK(vkAllocateMemory(dev, &ai, NULL, &mem)); + CHECK(vkBindImageMemory(dev, img, mem, 0)); + return mem; +} + +int +main(void) +{ + /* instance */ + VkApplicationInfo app = { + .sType = VK_STRUCTURE_TYPE_APPLICATION_INFO, + .apiVersion = VK_API_VERSION_1_3, + }; + VkInstanceCreateInfo ici = { + .sType = VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO, + .pApplicationInfo = &app, + }; + VkInstance instance; + CHECK(vkCreateInstance(&ici, NULL, &instance)); + + uint32_t pdev_count = 0; + CHECK(vkEnumeratePhysicalDevices(instance, &pdev_count, NULL)); + if (pdev_count == 0) { fprintf(stderr, "no physical devices\n"); return 1; } + VkPhysicalDevice *pdevs = calloc(pdev_count, sizeof(*pdevs)); + CHECK(vkEnumeratePhysicalDevices(instance, &pdev_count, pdevs)); + VkPhysicalDevice pdev = pdevs[0]; + + VkPhysicalDeviceProperties pprops; + vkGetPhysicalDeviceProperties(pdev, &pprops); + printf("Device: %s\n", pprops.deviceName); + + VkPhysicalDeviceMemoryProperties mem_props; + vkGetPhysicalDeviceMemoryProperties(pdev, &mem_props); + + /* find encode queue family */ + uint32_t qf_count = 0; + vkGetPhysicalDeviceQueueFamilyProperties2(pdev, &qf_count, NULL); + VkQueueFamilyVideoPropertiesKHR *video_props = calloc(qf_count, sizeof(*video_props)); + VkQueueFamilyProperties2 *qfs = calloc(qf_count, sizeof(*qfs)); + for (uint32_t i = 0; i < qf_count; i++) { + video_props[i].sType = VK_STRUCTURE_TYPE_QUEUE_FAMILY_VIDEO_PROPERTIES_KHR; + qfs[i].sType = VK_STRUCTURE_TYPE_QUEUE_FAMILY_PROPERTIES_2; + qfs[i].pNext = &video_props[i]; + } + vkGetPhysicalDeviceQueueFamilyProperties2(pdev, &qf_count, qfs); + + int32_t encode_qf = -1; + int32_t transfer_qf = -1; + for (uint32_t i = 0; i < qf_count; i++) { + if ((qfs[i].queueFamilyProperties.queueFlags & VK_QUEUE_VIDEO_ENCODE_BIT_KHR) && + (video_props[i].videoCodecOperations & VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR)) { + encode_qf = (int32_t)i; + } + if ((qfs[i].queueFamilyProperties.queueFlags & VK_QUEUE_TRANSFER_BIT) && transfer_qf < 0) + transfer_qf = (int32_t)i; + } + if (encode_qf < 0) { fprintf(stderr, "no H.264 encode queue family found\n"); return 1; } + if (transfer_qf < 0) { fprintf(stderr, "no transfer-capable queue family found\n"); return 1; } + printf("encode queue family = %d, transfer queue family = %d\n", encode_qf, transfer_qf); + + /* ---- Device ---- */ + const char *dev_exts[] = { + "VK_KHR_video_queue", + "VK_KHR_video_encode_queue", + "VK_KHR_video_encode_h264", + "VK_KHR_synchronization2", + }; + float qprio = 1.0f; + VkDeviceQueueCreateInfo qcis[2] = { + { + .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_CREATE_INFO, + .queueFamilyIndex = (uint32_t)transfer_qf, + .queueCount = 1, + .pQueuePriorities = &qprio, + }, + { + .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_CREATE_INFO, + .queueFamilyIndex = (uint32_t)encode_qf, + .queueCount = 1, + .pQueuePriorities = &qprio, + }, + }; + VkDeviceCreateInfo dci = { + .sType = VK_STRUCTURE_TYPE_DEVICE_CREATE_INFO, + .queueCreateInfoCount = (encode_qf == transfer_qf) ? 1 : 2, + .pQueueCreateInfos = qcis, + .enabledExtensionCount = sizeof(dev_exts) / sizeof(dev_exts[0]), + .ppEnabledExtensionNames = dev_exts, + }; + VkDevice dev; + CHECK(vkCreateDevice(pdev, &dci, NULL, &dev)); + +#define LOAD(name) p##name = (PFN_vk##name)vkGetDeviceProcAddr(dev, "vk" #name) + LOAD(GetPhysicalDeviceVideoCapabilitiesKHR); + LOAD(GetPhysicalDeviceVideoFormatPropertiesKHR); + LOAD(CreateVideoSessionKHR); + LOAD(DestroyVideoSessionKHR); + LOAD(GetVideoSessionMemoryRequirementsKHR); + LOAD(BindVideoSessionMemoryKHR); + LOAD(CreateVideoSessionParametersKHR); + LOAD(DestroyVideoSessionParametersKHR); + LOAD(GetEncodedVideoSessionParametersKHR); + LOAD(CmdBeginVideoCodingKHR); + LOAD(CmdEndVideoCodingKHR); + LOAD(CmdEncodeVideoKHR); + pGetPhysicalDeviceVideoCapabilitiesKHR = + (PFN_vkGetPhysicalDeviceVideoCapabilitiesKHR)vkGetInstanceProcAddr(instance, "vkGetPhysicalDeviceVideoCapabilitiesKHR"); + pGetPhysicalDeviceVideoFormatPropertiesKHR = + (PFN_vkGetPhysicalDeviceVideoFormatPropertiesKHR)vkGetInstanceProcAddr(instance, "vkGetPhysicalDeviceVideoFormatPropertiesKHR"); +#undef LOAD + + VkQueue queue; + vkGetDeviceQueue(dev, (uint32_t)encode_qf, 0, &queue); + VkQueue transfer_queue; + vkGetDeviceQueue(dev, (uint32_t)transfer_qf, 0, &transfer_queue); + + int use_cabac = getenv("HASVK_ENC_CABAC") ? 1 : 0; + int use_pframe = getenv("HASVK_ENC_PFRAME") ? 1 : 0; + + /* H.264 encode, 4:2:0, 8-bit */ + VkVideoEncodeH264ProfileInfoKHR h264_profile = { + .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_H264_PROFILE_INFO_KHR, + .stdProfileIdc = use_cabac ? STD_VIDEO_H264_PROFILE_IDC_MAIN + : STD_VIDEO_H264_PROFILE_IDC_BASELINE, + }; + VkVideoProfileInfoKHR profile = { + .sType = VK_STRUCTURE_TYPE_VIDEO_PROFILE_INFO_KHR, + .pNext = &h264_profile, + .videoCodecOperation = VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR, + .chromaSubsampling = VK_VIDEO_CHROMA_SUBSAMPLING_420_BIT_KHR, + .lumaBitDepth = VK_VIDEO_COMPONENT_BIT_DEPTH_8_BIT_KHR, + .chromaBitDepth = VK_VIDEO_COMPONENT_BIT_DEPTH_8_BIT_KHR, + }; + VkVideoProfileListInfoKHR profile_list = { + .sType = VK_STRUCTURE_TYPE_VIDEO_PROFILE_LIST_INFO_KHR, + .profileCount = 1, + .pProfiles = &profile, + }; + + /* capability */ + VkVideoEncodeH264CapabilitiesKHR h264_caps = { .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_H264_CAPABILITIES_KHR }; + VkVideoEncodeCapabilitiesKHR enc_caps = { .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_CAPABILITIES_KHR, .pNext = &h264_caps }; + VkVideoCapabilitiesKHR caps = { .sType = VK_STRUCTURE_TYPE_VIDEO_CAPABILITIES_KHR, .pNext = &enc_caps }; + CHECK(pGetPhysicalDeviceVideoCapabilitiesKHR(pdev, &profile, &caps)); + printf("caps: minBitstreamBufferOffsetAlignment=%llu minBitstreamBufferSizeAlignment=%llu maxDpbSlots=%u\n", + (unsigned long long)caps.minBitstreamBufferOffsetAlignment, + (unsigned long long)caps.minBitstreamBufferSizeAlignment, + caps.maxDpbSlots); + printf("enc caps: supportedEncodeFeedbackFlags=0x%x rateControlModes=0x%x\n", + enc_caps.supportedEncodeFeedbackFlags, enc_caps.rateControlModes); + + /* src/dpb images */ + VkPhysicalDeviceVideoFormatInfoKHR fmt_info = { + .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VIDEO_FORMAT_INFO_KHR, + .pNext = &profile_list, + .imageUsage = VK_IMAGE_USAGE_VIDEO_ENCODE_SRC_BIT_KHR | VK_IMAGE_USAGE_VIDEO_ENCODE_DPB_BIT_KHR, + }; + uint32_t fmt_count = 0; + CHECK(pGetPhysicalDeviceVideoFormatPropertiesKHR(pdev, &fmt_info, &fmt_count, NULL)); + if (fmt_count == 0) { fprintf(stderr, "no video formats reported\n"); return 1; } + VkVideoFormatPropertiesKHR *fmts = calloc(fmt_count, sizeof(*fmts)); + for (uint32_t i = 0; i < fmt_count; i++) + fmts[i].sType = VK_STRUCTURE_TYPE_VIDEO_FORMAT_PROPERTIES_KHR; + CHECK(pGetPhysicalDeviceVideoFormatPropertiesKHR(pdev, &fmt_info, &fmt_count, fmts)); + VkFormat pic_format = fmts[0].format; + printf("picture format = %d\n", pic_format); + + /* video sessions */ + VkExtensionProperties std_hdr = { + .extensionName = VK_STD_VULKAN_VIDEO_CODEC_H264_ENCODE_EXTENSION_NAME, + .specVersion = VK_STD_VULKAN_VIDEO_CODEC_H264_ENCODE_SPEC_VERSION, + }; + VkVideoSessionCreateInfoKHR sess_ci = { + .sType = VK_STRUCTURE_TYPE_VIDEO_SESSION_CREATE_INFO_KHR, + .queueFamilyIndex = (uint32_t)encode_qf, + .pVideoProfile = &profile, + .pictureFormat = pic_format, + .maxCodedExtent = { WIDTH, HEIGHT }, + .referencePictureFormat = pic_format, + .maxDpbSlots = 1, + .maxActiveReferencePictures = 0, + .pStdHeaderVersion = &std_hdr, + }; + VkVideoSessionKHR session; + CHECK(pCreateVideoSessionKHR(dev, &sess_ci, NULL, &session)); + + uint32_t req_count = 0; + CHECK(pGetVideoSessionMemoryRequirementsKHR(dev, session, &req_count, NULL)); + printf("video session memory requirement count = %u\n", req_count); + VkVideoSessionMemoryRequirementsKHR *reqs = calloc(req_count, sizeof(*reqs)); + for (uint32_t i = 0; i < req_count; i++) + reqs[i].sType = VK_STRUCTURE_TYPE_VIDEO_SESSION_MEMORY_REQUIREMENTS_KHR; + CHECK(pGetVideoSessionMemoryRequirementsKHR(dev, session, &req_count, reqs)); + + VkDeviceMemory *sess_mems = calloc(req_count, sizeof(*sess_mems)); + VkBindVideoSessionMemoryInfoKHR *binds = calloc(req_count, sizeof(*binds)); + for (uint32_t i = 0; i < req_count; i++) { + VkMemoryAllocateInfo ai = { + .sType = VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO, + .allocationSize = reqs[i].memoryRequirements.size, + .memoryTypeIndex = find_memory_type(&mem_props, reqs[i].memoryRequirements.memoryTypeBits, + VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT), + }; + CHECK(vkAllocateMemory(dev, &ai, NULL, &sess_mems[i])); + binds[i] = (VkBindVideoSessionMemoryInfoKHR) { + .sType = VK_STRUCTURE_TYPE_BIND_VIDEO_SESSION_MEMORY_INFO_KHR, + .memoryBindIndex = reqs[i].memoryBindIndex, + .memory = sess_mems[i], + .memoryOffset = 0, + .memorySize = reqs[i].memoryRequirements.size, + }; + printf(" bindIndex=%u size=%llu\n", reqs[i].memoryBindIndex, + (unsigned long long)reqs[i].memoryRequirements.size); + } + CHECK(pBindVideoSessionMemoryKHR(dev, session, req_count, binds)); + + /* SPS / PPS */ + int crop_r = getenv("HASVK_ENC_CROP_R") ? atoi(getenv("HASVK_ENC_CROP_R")) : 0; + int crop_b = getenv("HASVK_ENC_CROP_B") ? atoi(getenv("HASVK_ENC_CROP_B")) : 0; + crop_r &= ~1; crop_b &= ~1; + + StdVideoH264SequenceParameterSet sps = { + .profile_idc = use_cabac ? STD_VIDEO_H264_PROFILE_IDC_MAIN + : STD_VIDEO_H264_PROFILE_IDC_BASELINE, + .level_idc = getenv("HASVK_ENC_LEVEL0") ? STD_VIDEO_H264_LEVEL_IDC_1_0 + : STD_VIDEO_H264_LEVEL_IDC_3_0, + .chroma_format_idc = STD_VIDEO_H264_CHROMA_FORMAT_IDC_420, + .seq_parameter_set_id = 0, + .log2_max_frame_num_minus4 = getenv("HASVK_ENC_LOG2MAXFN") + ? atoi(getenv("HASVK_ENC_LOG2MAXFN")) : 0, + .pic_order_cnt_type = getenv("HASVK_ENC_POC2") ? STD_VIDEO_H264_POC_TYPE_2 + : STD_VIDEO_H264_POC_TYPE_0, + .log2_max_pic_order_cnt_lsb_minus4 = 0, + .max_num_ref_frames = 0, + .pic_width_in_mbs_minus1 = WIDTH_MBS - 1, + .pic_height_in_map_units_minus1 = HEIGHT_MBS - 1, + .frame_crop_right_offset = (uint32_t)(crop_r / 2), + .frame_crop_bottom_offset = (uint32_t)(crop_b / 2), + }; + sps.flags.frame_mbs_only_flag = 1; + sps.flags.direct_8x8_inference_flag = 1; + sps.flags.frame_cropping_flag = (crop_r || crop_b) ? 1 : 0; + + StdVideoH264PictureParameterSet pps = { + .seq_parameter_set_id = 0, + .pic_parameter_set_id = 0, + .num_ref_idx_l0_default_active_minus1 = 0, + .num_ref_idx_l1_default_active_minus1 = 0, + .weighted_bipred_idc = STD_VIDEO_H264_WEIGHTED_BIPRED_IDC_DEFAULT, + .pic_init_qp_minus26 = 0, /* pic_init_qp = 26 */ + .pic_init_qs_minus26 = 0, + .chroma_qp_index_offset = 0, + .second_chroma_qp_index_offset = 0, + }; + pps.flags.deblocking_filter_control_present_flag = + getenv("HASVK_ENC_NODEBLOCKCTRL") ? 0 : 1; + pps.flags.entropy_coding_mode_flag = use_cabac ? 1 : 0; + + VkVideoEncodeH264SessionParametersAddInfoKHR add_info = { + .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_H264_SESSION_PARAMETERS_ADD_INFO_KHR, + .stdSPSCount = 1, + .pStdSPSs = &sps, + .stdPPSCount = 1, + .pStdPPSs = &pps, + }; + VkVideoEncodeH264SessionParametersCreateInfoKHR h264_params_ci = { + .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_H264_SESSION_PARAMETERS_CREATE_INFO_KHR, + .maxStdSPSCount = 1, + .maxStdPPSCount = 1, + .pParametersAddInfo = &add_info, + }; + VkVideoSessionParametersCreateInfoKHR params_ci = { + .sType = VK_STRUCTURE_TYPE_VIDEO_SESSION_PARAMETERS_CREATE_INFO_KHR, + .pNext = &h264_params_ci, + .videoSession = session, + }; + VkVideoSessionParametersKHR params; + CHECK(pCreateVideoSessionParametersKHR(dev, ¶ms_ci, NULL, ¶ms)); + + static uint8_t hdr_buf[512]; + size_t hdr_size = 0; + { + VkVideoEncodeH264SessionParametersGetInfoKHR h264_get = { + .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_H264_SESSION_PARAMETERS_GET_INFO_KHR, + .writeStdSPS = VK_TRUE, + .stdSPSId = 0, + .writeStdPPS = VK_TRUE, + .stdPPSId = 0, + }; + VkVideoEncodeSessionParametersGetInfoKHR get_info = { + .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_SESSION_PARAMETERS_GET_INFO_KHR, + .pNext = &h264_get, + .videoSessionParameters = params, + }; + size_t data_size = 0; + VkResult gr = pGetEncodedVideoSessionParametersKHR(dev, &get_info, NULL, + &data_size, NULL); + printf("GetEncoded SPS+PPS: result=%d size=%zu\n", gr, data_size); + if (gr == VK_SUCCESS && data_size > 0 && data_size <= sizeof(hdr_buf)) { + gr = pGetEncodedVideoSessionParametersKHR(dev, &get_info, NULL, + &data_size, hdr_buf); + if (gr == VK_SUCCESS) hdr_size = data_size; + } + } + + /* source + recon/DPB */ + VkImageCreateInfo img_ci = { + .sType = VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO, + .pNext = &profile_list, + .imageType = VK_IMAGE_TYPE_2D, + .format = pic_format, + .extent = { WIDTH, HEIGHT, 1 }, + .mipLevels = 1, + .arrayLayers = 1, + .samples = VK_SAMPLE_COUNT_1_BIT, + .tiling = VK_IMAGE_TILING_OPTIMAL, + .usage = VK_IMAGE_USAGE_VIDEO_ENCODE_SRC_BIT_KHR, + .sharingMode = VK_SHARING_MODE_EXCLUSIVE, + .initialLayout = VK_IMAGE_LAYOUT_UNDEFINED, + }; + VkImage src_image; + CHECK(vkCreateImage(dev, &img_ci, NULL, &src_image)); + VkDeviceMemory src_image_mem = alloc_and_bind_image(dev, &mem_props, src_image); + + VkImageCreateInfo dpb_ci = img_ci; + dpb_ci.usage = VK_IMAGE_USAGE_VIDEO_ENCODE_DPB_BIT_KHR; + VkImage dpb_image; + CHECK(vkCreateImage(dev, &dpb_ci, NULL, &dpb_image)); + VkDeviceMemory dpb_image_mem = alloc_and_bind_image(dev, &mem_props, dpb_image); + + VkImageViewCreateInfo src_view_ci = { + .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO, + .image = src_image, + .viewType = VK_IMAGE_VIEW_TYPE_2D, + .format = pic_format, + .subresourceRange = { VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }, + }; + VkImageView src_view; + CHECK(vkCreateImageView(dev, &src_view_ci, NULL, &src_view)); + + VkImageViewCreateInfo dpb_view_ci = src_view_ci; + dpb_view_ci.image = dpb_image; + VkImageView dpb_view; + CHECK(vkCreateImageView(dev, &dpb_view_ci, NULL, &dpb_view)); + + VkImage dpb_image2 = VK_NULL_HANDLE; + VkImageView dpb_view2 = VK_NULL_HANDLE; + if (use_pframe) { + CHECK(vkCreateImage(dev, &dpb_ci, NULL, &dpb_image2)); + alloc_and_bind_image(dev, &mem_props, dpb_image2); + VkImageViewCreateInfo v = dpb_view_ci; + v.image = dpb_image2; + CHECK(vkCreateImageView(dev, &v, NULL, &dpb_view2)); + } + + int shift_px = getenv("HASVK_ENC_SHIFT") ? atoi(getenv("HASVK_ENC_SHIFT")) : 0; + int src_step = getenv("HASVK_ENC_SRC_STEP") ? atoi(getenv("HASVK_ENC_SRC_STEP")) : 0; + int two_src = use_pframe && (shift_px || src_step); + VkImage src_image2 = VK_NULL_HANDLE; + VkImageView src_view2 = VK_NULL_HANDLE; + if (two_src) { + CHECK(vkCreateImage(dev, &img_ci, NULL, &src_image2)); + alloc_and_bind_image(dev, &mem_props, src_image2); + VkImageViewCreateInfo v = src_view_ci; + v.image = src_image2; + CHECK(vkCreateImageView(dev, &v, NULL, &src_view2)); + } + + /* fill source image with flat gray via staging buffer */ + VkDeviceSize luma_size = (VkDeviceSize)WIDTH * HEIGHT; + VkDeviceSize chroma_size = (VkDeviceSize)(WIDTH / 2) * (HEIGHT / 2) * 2; + VkDeviceSize frame_size = luma_size + chroma_size; + VkDeviceSize staging_size = frame_size * (two_src ? 2 : 1); + VkBufferCreateInfo staging_ci = { + .sType = VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO, + .size = staging_size, + .usage = VK_BUFFER_USAGE_TRANSFER_SRC_BIT, + .sharingMode = VK_SHARING_MODE_EXCLUSIVE, + }; + VkBuffer staging_buf; + CHECK(vkCreateBuffer(dev, &staging_ci, NULL, &staging_buf)); + VkDeviceMemory staging_mem = alloc_and_bind_buffer(dev, &mem_props, staging_buf, + VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | VK_MEMORY_PROPERTY_HOST_COHERENT_BIT); + void *staging_map; + CHECK(vkMapMemory(dev, staging_mem, 0, staging_size, 0, &staging_map)); + const char *src_in = getenv("HASVK_ENC_SRC_IN"); + int src_i420 = getenv("HASVK_ENC_SRC_I420") ? 1 : 0; + int src_frame = getenv("HASVK_ENC_SRC_FRAME") ? atoi(getenv("HASVK_ENC_SRC_FRAME")) : 0; + if (src_in) { + if (!load_frame(src_in, src_frame, src_i420, (uint8_t *)staging_map)) + return 1; + } else if (getenv("HASVK_ENC_GRADIENT")) { + uint8_t *sm = (uint8_t *)staging_map; + for (uint32_t yy = 0; yy < HEIGHT; yy++) + for (uint32_t xx = 0; xx < WIDTH; xx++) + sm[yy * WIDTH + xx] = (uint8_t)((xx * 255) / (WIDTH - 1)); + if (getenv("HASVK_ENC_CHROMA")) { + uint8_t *ch = sm + luma_size; + uint32_t cw = WIDTH / 2, chh = HEIGHT / 2; + for (uint32_t cy = 0; cy < chh; cy++) + for (uint32_t cx = 0; cx < cw; cx++) { + ch[(cy * cw + cx) * 2 + 0] = (uint8_t)((cx * 255) / (cw - 1)); + ch[(cy * cw + cx) * 2 + 1] = (uint8_t)((cy * 255) / (chh - 1)); + } + } else { + memset(sm + luma_size, 128, (size_t)chroma_size); + } + } else { + memset(staging_map, 128, (size_t)frame_size); + } + + if (two_src) { + uint8_t *f0 = (uint8_t *)staging_map, *f1 = f0 + frame_size; + if (shift_px) { + shift_frame(f0, f1, shift_px, 0); + } else if (!src_in) { + fprintf(stderr, "HASVK_ENC_SRC_STEP needs HASVK_ENC_SRC_IN\n"); + return 1; + } else if (!load_frame(src_in, src_frame + src_step, src_i420, f1)) { + return 1; + } + } + + const char *src_out = getenv("HASVK_ENC_SRC_OUT"); + if (src_out) { + const uint8_t *sm = (const uint8_t *)staging_map; + const uint8_t *ch = sm + luma_size; + uint32_t cw = WIDTH / 2, chh = HEIGHT / 2; + FILE *sf = fopen(src_out, "wb"); + if (sf) { + fwrite(sm, 1, (size_t)luma_size, sf); + for (uint32_t i = 0; i < cw * chh; i++) + fputc(ch[i * 2 + 0], sf); + for (uint32_t i = 0; i < cw * chh; i++) + fputc(ch[i * 2 + 1], sf); + fclose(sf); + } + } + vkUnmapMemory(dev, staging_mem); + + VkDeviceSize dst_align = caps.minBitstreamBufferSizeAlignment ? caps.minBitstreamBufferSizeAlignment : 4096; + VkDeviceSize dst_size = ((VkDeviceSize)1 << 20); + dst_size = (dst_size + dst_align - 1) & ~(dst_align - 1); + VkBufferCreateInfo dst_ci = { + .sType = VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO, + .pNext = &profile_list, + .size = dst_size, + .usage = VK_BUFFER_USAGE_VIDEO_ENCODE_DST_BIT_KHR, + .sharingMode = VK_SHARING_MODE_EXCLUSIVE, + }; + VkBuffer dst_buf; + CHECK(vkCreateBuffer(dev, &dst_ci, NULL, &dst_buf)); + VkDeviceMemory dst_mem = alloc_and_bind_buffer(dev, &mem_props, dst_buf, + VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT | VK_MEMORY_PROPERTY_HOST_COHERENT_BIT); + void *dst_map; + CHECK(vkMapMemory(dev, dst_mem, 0, dst_size, 0, &dst_map)); + memset(dst_map, 0xCD, (size_t)dst_size); + + VkCommandPoolCreateInfo xfer_pool_ci = { + .sType = VK_STRUCTURE_TYPE_COMMAND_POOL_CREATE_INFO, + .flags = VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT, + .queueFamilyIndex = (uint32_t)transfer_qf, + }; + VkCommandPool xfer_pool; + CHECK(vkCreateCommandPool(dev, &xfer_pool_ci, NULL, &xfer_pool)); + VkCommandBufferAllocateInfo xfer_cb_ai = { + .sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_ALLOCATE_INFO, + .commandPool = xfer_pool, + .level = VK_COMMAND_BUFFER_LEVEL_PRIMARY, + .commandBufferCount = 1, + }; + VkCommandBuffer xfer_cmd; + CHECK(vkAllocateCommandBuffers(dev, &xfer_cb_ai, &xfer_cmd)); + + VkCommandBufferBeginInfo xfer_begin_info = { .sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_BEGIN_INFO }; + CHECK(vkBeginCommandBuffer(xfer_cmd, &xfer_begin_info)); + + VkImageMemoryBarrier to_xfer = { + .sType = VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, + .srcAccessMask = 0, + .dstAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT, + .oldLayout = VK_IMAGE_LAYOUT_UNDEFINED, + .newLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL, + .srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .image = src_image, + .subresourceRange = { VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }, + }; + VkImageMemoryBarrier to_xfer_both[2] = { to_xfer, to_xfer }; + to_xfer_both[1].image = src_image2; + vkCmdPipelineBarrier(xfer_cmd, VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, VK_PIPELINE_STAGE_TRANSFER_BIT, + 0, 0, NULL, 0, NULL, two_src ? 2 : 1, to_xfer_both); + + VkBufferImageCopy regions[2] = { + { /* luma plane */ + .bufferOffset = 0, + .imageSubresource = { VK_IMAGE_ASPECT_PLANE_0_BIT, 0, 0, 1 }, + .imageExtent = { WIDTH, HEIGHT, 1 }, + }, + { /* chroma plane (interleaved UV, half res) */ + .bufferOffset = luma_size, + .imageSubresource = { VK_IMAGE_ASPECT_PLANE_1_BIT, 0, 0, 1 }, + .imageExtent = { WIDTH / 2, HEIGHT / 2, 1 }, + }, + }; + vkCmdCopyBufferToImage(xfer_cmd, staging_buf, src_image, VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL, 2, regions); + if (two_src) { + VkBufferImageCopy r2[2] = { regions[0], regions[1] }; + r2[0].bufferOffset = frame_size; + r2[1].bufferOffset = frame_size + luma_size; + vkCmdCopyBufferToImage(xfer_cmd, staging_buf, src_image2, VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL, 2, r2); + } + + VkImageMemoryBarrier to_encode_src = to_xfer; + to_encode_src.srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT; + to_encode_src.dstAccessMask = 0; + to_encode_src.oldLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL; + to_encode_src.newLayout = VK_IMAGE_LAYOUT_VIDEO_ENCODE_SRC_KHR; + VkImageMemoryBarrier to_encode_dpb = { + .sType = VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, + .oldLayout = VK_IMAGE_LAYOUT_UNDEFINED, + .newLayout = VK_IMAGE_LAYOUT_VIDEO_ENCODE_DPB_KHR, + .srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .image = dpb_image, + .subresourceRange = { VK_IMAGE_ASPECT_COLOR_BIT, 0, 1, 0, 1 }, + }; + VkImageMemoryBarrier barriers2[4] = { to_encode_src, to_encode_dpb }; + uint32_t barrier2_count = 2; + if (use_pframe) { + VkImageMemoryBarrier to_encode_dpb2 = to_encode_dpb; + to_encode_dpb2.image = dpb_image2; + barriers2[barrier2_count++] = to_encode_dpb2; + } + if (two_src) { + VkImageMemoryBarrier to_encode_src2 = to_encode_src; + to_encode_src2.image = src_image2; + barriers2[barrier2_count++] = to_encode_src2; + } + vkCmdPipelineBarrier(xfer_cmd, VK_PIPELINE_STAGE_TRANSFER_BIT, VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, + 0, 0, NULL, 0, NULL, barrier2_count, barriers2); + + CHECK(vkEndCommandBuffer(xfer_cmd)); + + /* HASVK_ENC_SEMSYNC */ + int use_semsync = getenv("HASVK_ENC_SEMSYNC") ? 1 : 0; + VkSemaphore xfer_sem = VK_NULL_HANDLE; + if (use_semsync) { + VkSemaphoreCreateInfo sci = { .sType = VK_STRUCTURE_TYPE_SEMAPHORE_CREATE_INFO }; + CHECK(vkCreateSemaphore(dev, &sci, NULL, &xfer_sem)); + } + + VkFenceCreateInfo xfer_fence_ci = { .sType = VK_STRUCTURE_TYPE_FENCE_CREATE_INFO }; + VkFence xfer_fence; + CHECK(vkCreateFence(dev, &xfer_fence_ci, NULL, &xfer_fence)); + VkSubmitInfo xfer_submit = { + .sType = VK_STRUCTURE_TYPE_SUBMIT_INFO, + .commandBufferCount = 1, + .pCommandBuffers = &xfer_cmd, + .signalSemaphoreCount = use_semsync ? 1u : 0u, + .pSignalSemaphores = use_semsync ? &xfer_sem : NULL, + }; + printf("submitting transfer prep...\n"); + fflush(stdout); + CHECK(vkQueueSubmit(transfer_queue, 1, &xfer_submit, xfer_fence)); + if (!use_semsync) { + VkResult xfer_wait = vkWaitForFences(dev, 1, &xfer_fence, VK_TRUE, 10ull * 1000 * 1000 * 1000); + printf("transfer wait result = %d\n", xfer_wait); + if (xfer_wait != VK_SUCCESS) { fprintf(stderr, "transfer prep failed/hung\n"); return 3; } + } else { + printf("transfer submitted (semaphore sync, no CPU wait)\n"); + } + + VkCommandPoolCreateInfo pool_ci = { + .sType = VK_STRUCTURE_TYPE_COMMAND_POOL_CREATE_INFO, + .flags = VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT, + .queueFamilyIndex = (uint32_t)encode_qf, + }; + VkCommandPool pool; + CHECK(vkCreateCommandPool(dev, &pool_ci, NULL, &pool)); + VkCommandBufferAllocateInfo cb_ai = { + .sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_ALLOCATE_INFO, + .commandPool = pool, + .level = VK_COMMAND_BUFFER_LEVEL_PRIMARY, + .commandBufferCount = 1, + }; + VkCommandBuffer cmd; + CHECK(vkAllocateCommandBuffers(dev, &cb_ai, &cmd)); + + VkQueryPoolVideoEncodeFeedbackCreateInfoKHR fb_ci = { + .sType = VK_STRUCTURE_TYPE_QUERY_POOL_VIDEO_ENCODE_FEEDBACK_CREATE_INFO_KHR, + .pNext = &profile, + .encodeFeedbackFlags = + VK_VIDEO_ENCODE_FEEDBACK_BITSTREAM_BUFFER_OFFSET_BIT_KHR | + VK_VIDEO_ENCODE_FEEDBACK_BITSTREAM_BYTES_WRITTEN_BIT_KHR, + }; + VkQueryPoolCreateInfo qp_ci = { + .sType = VK_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO, + .pNext = &fb_ci, + .queryType = VK_QUERY_TYPE_VIDEO_ENCODE_FEEDBACK_KHR, + .queryCount = 2, + }; + VkQueryPool qpool; + CHECK(vkCreateQueryPool(dev, &qp_ci, NULL, &qpool)); + + VkCommandBufferBeginInfo begin_info = { .sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_BEGIN_INFO }; + CHECK(vkBeginCommandBuffer(cmd, &begin_info)); + + vkCmdResetQueryPool(cmd, qpool, 0, 2); + + if (getenv("HASVK_BISECT_TRULY_EMPTY")) { + CHECK(vkEndCommandBuffer(cmd)); + VkFenceCreateInfo fci = { .sType = VK_STRUCTURE_TYPE_FENCE_CREATE_INFO }; + VkFence f; + CHECK(vkCreateFence(dev, &fci, NULL, &f)); + VkSubmitInfo si = { .sType = VK_STRUCTURE_TYPE_SUBMIT_INFO, .commandBufferCount = 1, .pCommandBuffers = &cmd }; + printf("submitting TRULY EMPTY (no video calls at all)...\n"); + fflush(stdout); + CHECK(vkQueueSubmit(queue, 1, &si, f)); + VkResult r = vkWaitForFences(dev, 1, &f, VK_TRUE, 15ull * 1000 * 1000 * 1000); + printf("truly-empty wait result = %d\n", r); + return r == VK_SUCCESS ? 0 : 2; + } + + int qp = getenv("HASVK_ENC_QP") ? atoi(getenv("HASVK_ENC_QP")) : 26; + uint64_t bitrate = getenv("HASVK_ENC_BITRATE") + ? strtoull(getenv("HASVK_ENC_BITRATE"), NULL, 10) : 0; + if (qp < 0) qp = 0; + if (qp > 51) qp = 51; + + int num_slices = getenv("HASVK_ENC_SLICES") ? atoi(getenv("HASVK_ENC_SLICES")) : 1; + if (num_slices < 1) num_slices = 1; + if (num_slices > HEIGHT_MBS) num_slices = HEIGHT_MBS; + + VkVideoPictureResourceInfoKHR src_res = { + .sType = VK_STRUCTURE_TYPE_VIDEO_PICTURE_RESOURCE_INFO_KHR, + .codedExtent = { WIDTH, HEIGHT }, .baseArrayLayer = 0, .imageViewBinding = src_view, + }; + VkVideoPictureResourceInfoKHR src_res2 = src_res; + src_res2.imageViewBinding = two_src ? src_view2 : src_view; + VkVideoPictureResourceInfoKHR dpb_res0 = { + .sType = VK_STRUCTURE_TYPE_VIDEO_PICTURE_RESOURCE_INFO_KHR, + .codedExtent = { WIDTH, HEIGHT }, .baseArrayLayer = 0, .imageViewBinding = dpb_view, + }; + VkVideoPictureResourceInfoKHR dpb_res1 = { + .sType = VK_STRUCTURE_TYPE_VIDEO_PICTURE_RESOURCE_INFO_KHR, + .codedExtent = { WIDTH, HEIGHT }, .baseArrayLayer = 0, .imageViewBinding = dpb_view2, + }; + + int num_frames = use_pframe ? 2 : 1; + VkDeviceSize base_off = getenv("HASVK_ENC_DSTOFF") + ? (VkDeviceSize)atoi(getenv("HASVK_ENC_DSTOFF")) : 0; + VkDeviceSize frame_dst_offset[2] = { base_off, dst_size / 2 }; + + for (int frame = 0; frame < num_frames; frame++) { + bool is_p_frame = (frame == 1) && !getenv("HASVK_ENC_FORCE_I"); + + VkVideoReferenceSlotInfoKHR begin_slots[2]; + uint32_t begin_slot_count = 0; + if (is_p_frame) { + begin_slots[begin_slot_count++] = (VkVideoReferenceSlotInfoKHR){ + .sType = VK_STRUCTURE_TYPE_VIDEO_REFERENCE_SLOT_INFO_KHR, + .slotIndex = 0, .pPictureResource = &dpb_res0 }; + begin_slots[begin_slot_count++] = (VkVideoReferenceSlotInfoKHR){ + .sType = VK_STRUCTURE_TYPE_VIDEO_REFERENCE_SLOT_INFO_KHR, + .slotIndex = 1, .pPictureResource = &dpb_res1 }; + } else { + begin_slots[begin_slot_count++] = (VkVideoReferenceSlotInfoKHR){ + .sType = VK_STRUCTURE_TYPE_VIDEO_REFERENCE_SLOT_INFO_KHR, + .slotIndex = 0, .pPictureResource = &dpb_res0 }; + } + VkVideoEncodeH264RateControlLayerInfoKHR h264_rc_layer = { + .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_H264_RATE_CONTROL_LAYER_INFO_KHR, + }; + VkVideoEncodeRateControlLayerInfoKHR rc_layer = { + .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_RATE_CONTROL_LAYER_INFO_KHR, + .pNext = &h264_rc_layer, + .averageBitrate = bitrate, + .maxBitrate = bitrate, + .frameRateNumerator = 30, + .frameRateDenominator = 1, + }; + VkVideoEncodeRateControlInfoKHR rc_info = { + .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_RATE_CONTROL_INFO_KHR, + .rateControlMode = getenv("HASVK_ENC_VBR") + ? VK_VIDEO_ENCODE_RATE_CONTROL_MODE_VBR_BIT_KHR + : VK_VIDEO_ENCODE_RATE_CONTROL_MODE_CBR_BIT_KHR, + .layerCount = 1, + .pLayers = &rc_layer, + }; + VkVideoBeginCodingInfoKHR begin_coding = { + .sType = VK_STRUCTURE_TYPE_VIDEO_BEGIN_CODING_INFO_KHR, + .pNext = bitrate ? &rc_info : NULL, + .videoSession = session, + .videoSessionParameters = params, + .referenceSlotCount = begin_slot_count, + .pReferenceSlots = begin_slots, + }; + pCmdBeginVideoCodingKHR(cmd, &begin_coding); + + StdVideoEncodeH264PictureInfo std_pic_info = { + .seq_parameter_set_id = 0, + .pic_parameter_set_id = 0, + .idr_pic_id = 0, + .primary_pic_type = is_p_frame ? STD_VIDEO_H264_PICTURE_TYPE_P + : STD_VIDEO_H264_PICTURE_TYPE_IDR, + .frame_num = (uint16_t)frame, + .PicOrderCnt = (int32_t)(frame * 2), + }; + std_pic_info.flags.IdrPicFlag = is_p_frame ? 0 : 1; + std_pic_info.flags.is_reference = 1; + + StdVideoEncodeH264SliceHeader std_slice_hdr[HEIGHT_MBS]; + VkVideoEncodeH264NaluSliceInfoKHR nalu_slice[HEIGHT_MBS]; + for (int s = 0; s < num_slices; s++) { + uint32_t start_row = (uint32_t)s * HEIGHT_MBS / num_slices; + std_slice_hdr[s] = (StdVideoEncodeH264SliceHeader){ + .first_mb_in_slice = start_row * WIDTH_MBS, + .slice_type = is_p_frame ? STD_VIDEO_H264_SLICE_TYPE_P + : STD_VIDEO_H264_SLICE_TYPE_I, + .slice_qp_delta = qp - 26, + .cabac_init_idc = STD_VIDEO_H264_CABAC_INIT_IDC_0, + /* value 1 ("_ENABLED") == H.264 disable_deblocking_filter_idc==1. */ + .disable_deblocking_filter_idc = STD_VIDEO_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLED, + }; + nalu_slice[s] = (VkVideoEncodeH264NaluSliceInfoKHR){ + .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_H264_NALU_SLICE_INFO_KHR, + .constantQp = qp, + .pStdSliceHeader = &std_slice_hdr[s], + }; + } + + VkVideoEncodeH264PictureInfoKHR h264_pic_info = { + .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_H264_PICTURE_INFO_KHR, + .naluSliceEntryCount = (uint32_t)num_slices, + .pNaluSliceEntries = nalu_slice, + .pStdPictureInfo = &std_pic_info, + }; + + VkVideoReferenceSlotInfoKHR setup_slot = { + .sType = VK_STRUCTURE_TYPE_VIDEO_REFERENCE_SLOT_INFO_KHR, + .slotIndex = is_p_frame ? 1 : 0, + .pPictureResource = is_p_frame ? &dpb_res1 : &dpb_res0, + }; + VkVideoReferenceSlotInfoKHR ref_slot = { + .sType = VK_STRUCTURE_TYPE_VIDEO_REFERENCE_SLOT_INFO_KHR, + .slotIndex = 0, + .pPictureResource = &dpb_res0, + }; + + VkVideoEncodeInfoKHR encode_info = { + .sType = VK_STRUCTURE_TYPE_VIDEO_ENCODE_INFO_KHR, + .pNext = &h264_pic_info, + .dstBuffer = dst_buf, + .dstBufferOffset = frame_dst_offset[frame], + .dstBufferRange = dst_size / 2, + .srcPictureResource = is_p_frame ? src_res2 : src_res, + .pSetupReferenceSlot = &setup_slot, + .referenceSlotCount = is_p_frame ? 1 : 0, + .pReferenceSlots = is_p_frame ? &ref_slot : NULL, + }; + vkCmdBeginQuery(cmd, qpool, frame, 0); + pCmdEncodeVideoKHR(cmd, &encode_info); + vkCmdEndQuery(cmd, qpool, frame); + + VkVideoEndCodingInfoKHR end_coding = { .sType = VK_STRUCTURE_TYPE_VIDEO_END_CODING_INFO_KHR }; + pCmdEndVideoCodingKHR(cmd, &end_coding); + } + + CHECK(vkEndCommandBuffer(cmd)); + + VkFenceCreateInfo fence_ci = { .sType = VK_STRUCTURE_TYPE_FENCE_CREATE_INFO }; + VkFence fence; + CHECK(vkCreateFence(dev, &fence_ci, NULL, &fence)); + + VkPipelineStageFlags enc_wait_stage = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT; + VkSubmitInfo submit = { + .sType = VK_STRUCTURE_TYPE_SUBMIT_INFO, + .commandBufferCount = 1, + .pCommandBuffers = &cmd, + .waitSemaphoreCount = use_semsync ? 1u : 0u, + .pWaitSemaphores = use_semsync ? &xfer_sem : NULL, + .pWaitDstStageMask = use_semsync ? &enc_wait_stage : NULL, + }; + printf("submitting...\n"); + fflush(stdout); + CHECK(vkQueueSubmit(queue, 1, &submit, fence)); + + VkResult wait_result = vkWaitForFences(dev, 1, &fence, VK_TRUE, 15ull * 1000 * 1000 * 1000); + printf("wait result = %d (%s)\n", wait_result, + wait_result == VK_SUCCESS ? "SUCCESS" : + wait_result == VK_TIMEOUT ? "TIMEOUT" : + wait_result == VK_ERROR_DEVICE_LOST ? "DEVICE_LOST" : "OTHER"); + + if (wait_result == VK_SUCCESS) { + const uint8_t *bytes = (const uint8_t *)dst_map; + const char *out_path = getenv("HASVK_ENC_OUT"); + if (!out_path) out_path = "/tmp/hasvk_enc_out.h264"; + FILE *of = fopen(out_path, "wb"); + if (of && hdr_size > 0) + fwrite(hdr_buf, 1, hdr_size, of); + + for (int f = 0; f < num_frames; f++) { + struct { uint32_t offset; uint32_t bytesWritten; } fb = { 0, 0 }; + VkResult qr = vkGetQueryPoolResults(dev, qpool, f, 1, sizeof(fb), &fb, + sizeof(fb), VK_QUERY_RESULT_WAIT_BIT); + printf("frame %d (%s): bytesWritten=%u (query result %d)\n", + f, f == 0 ? "I" : "P", fb.bytesWritten, qr); + if (of && qr == VK_SUCCESS) + fwrite(bytes + frame_dst_offset[f], 1, fb.bytesWritten, of); + } + if (of) { + fclose(of); + printf("wrote %zu (SPS/PPS) + %d frame(s) to %s\n", + hdr_size, num_frames, out_path); + } + } + + vkUnmapMemory(dev, dst_mem); + printf("done.\n"); + return wait_result == VK_SUCCESS ? 0 : 2; +} diff --git a/flake.lock b/flake.lock new file mode 100644 index 0000000..379045c --- /dev/null +++ b/flake.lock @@ -0,0 +1,27 @@ +{ + "nodes": { + "nixpkgs": { + "locked": { + "lastModified": 1786106723, + "narHash": "sha256-zDSUbpoeo/9ZmD2+wXnzxoo1+uhL8vxc0b8yuYMKYq0=", + "owner": "NixOS", + "repo": "nixpkgs", + "rev": "f13ff45afd1bb73e640eaa08a7066dbed07e3238", + "type": "github" + }, + "original": { + "owner": "NixOS", + "ref": "nixos-unstable", + "repo": "nixpkgs", + "type": "github" + } + }, + "root": { + "inputs": { + "nixpkgs": "nixpkgs" + } + } + }, + "root": "root", + "version": 7 +} diff --git a/flake.nix b/flake.nix new file mode 100644 index 0000000..dba7818 --- /dev/null +++ b/flake.nix @@ -0,0 +1,174 @@ +{ + description = "gen7-lab — Ivy Bridge (HD 4000) driver test lab"; + inputs.nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; + + outputs = + { self, nixpkgs }: + let + system = "x86_64-linux"; + pkgs = import nixpkgs { inherit system; }; + + pciId = "8086:0166"; + + packages = with pkgs; [ + # CL + clinfo + clpeak + ocl-icd + opencl-headers + pocl + + # VK + vulkan-tools + vulkan-headers + vulkan-loader + vulkan-validation-layers + shaderc + glslang + spirv-tools + + # build + gcc + pkg-config + cmake + (python3.withPackages ( + ps: with ps; [ + pyopencl + numpy + opencv4 + ] + )) + # media + ffmpeg + mpv + + # debug + gdb + strace + jq + patchelf + binutils + libdrm + ]; + + runtimeLibs = with pkgs; [ + libxshmfence + xorg.xcbutilkeysyms + llvmPackages_21.llvm.lib + llvmPackages_21.libclang.lib + spirv-llvm-translator + vulkan-loader + libdrm + expat + zlib + zstd + elfutils + ]; + + paths = '' + export LAB_ROOT="''${LAB_ROOT:-$PWD}" + if [ ! -f "$LAB_ROOT/ivb-test/runner.py" ]; then + echo "warning: LAB_ROOT=$LAB_ROOT does not look like the gen7-lab checkout" + fi + export DRIVERS_ROOT="''${DRIVERS_ROOT:-$(dirname "$LAB_ROOT")}" + + export MESA_SRC="''${MESA_SRC:-$DRIVERS_ROOT/intel-hard-graphics}" + export MESA_BUILD="''${MESA_BUILD:-$MESA_SRC/build}" + export CLVK_SRC="''${CLVK_SRC:-$DRIVERS_ROOT/clvk}" + export CLVK_BUILD="''${CLVK_BUILD:-$CLVK_SRC/build}" + export CTS_DIR="''${CTS_DIR:-$MESA_SRC/VK-GL-CTS/build-cts/external/vulkancts/modules/vulkan}" + export CTS_MUSTPASS="''${CTS_MUSTPASS:-$MESA_SRC/VK-GL-CTS/external/vulkancts/mustpass/main/vk-default}" + export ICD_VENDORS="$LAB_ROOT/.icd-vendors" + + export LD_LIBRARY_PATH="${pkgs.lib.makeLibraryPath runtimeLibs}:''${LD_LIBRARY_PATH:-}" + ''; + + vulkanEnv = '' + export HASVK_ICD="$MESA_BUILD/src/intel/vulkan_hasvk/intel_hasvk13_devenv_icd.x86_64.json" + if [ -f "$HASVK_ICD" ]; then + export VK_DRIVER_FILES="$HASVK_ICD" + export VK_ICD_FILENAMES="$HASVK_ICD" + else + echo "warning: hasvk ICD not found: $HASVK_ICD" + unset HASVK_ICD + fi + export MESA_VK_DEVICE_SELECT="${pciId}" + ''; + + openclEnv = '' + mkdir -p "$ICD_VENDORS/lib" + ln -sf ${pkgs.pocl}/etc/OpenCL/vendors/pocl.icd "$ICD_VENDORS/pocl.icd" + + if [ -f "$MESA_BUILD/src/gallium/targets/rusticl/rusticl.icd" ]; then + ln -sf "$MESA_BUILD/src/gallium/targets/rusticl/rusticl.icd" "$ICD_VENDORS/rusticl.icd" + export LD_LIBRARY_PATH="$MESA_BUILD/src/gallium/targets/rusticl:''${LD_LIBRARY_PATH:-}" + else + rm -f "$ICD_VENDORS/rusticl.icd" + echo "warning: rusticl.icd not found under $MESA_BUILD" + fi + + if [ -f "$CLVK_BUILD/libOpenCL.so.1" ]; then + _clvk_lib="$ICD_VENDORS/lib/libclvk.so.1" + if [ "$CLVK_BUILD/libOpenCL.so.1" -nt "$_clvk_lib" ]; then + cp -L "$CLVK_BUILD/libOpenCL.so.1" "$_clvk_lib.tmp" + chmod u+w "$_clvk_lib.tmp" + patchelf --set-soname libclvk.so.1 "$_clvk_lib.tmp" + mv "$_clvk_lib.tmp" "$_clvk_lib" + fi + echo "$_clvk_lib" > "$ICD_VENDORS/clvk.icd" + else + rm -f "$ICD_VENDORS/clvk.icd" + echo "warning: clvk libOpenCL.so.1 not found under $CLVK_BUILD" + fi + + export OCL_ICD_VENDORS="$ICD_VENDORS" + export OCL_ICD_ASSUME_ICD_EXTENSION=1 + export RUSTICL_ENABLE=crocus + ''; + + runner = '' + ivb() { python3 "$LAB_ROOT/ivb-test/runner.py" "$@"; } + export -f ivb + ''; + + banner = name: ocl: '' + echo "=== ${name} ===" + printf '%-18s %s\n' \ + "MESA_BUILD" "$MESA_BUILD" \ + "CLVK_BUILD" "$CLVK_BUILD" \ + "CTS_DIR" "$CTS_DIR" \ + "VK_DRIVER_FILES" "''${VK_DRIVER_FILES:-(none)}" \ + "OpenCL" "${ocl}" + echo + echo "ivb list | ivb run | ivb doctor" + echo + ''; + in + { + devShells.${system} = { + default = pkgs.mkShell { + inherit packages; + shellHook = '' + ${paths} + ${vulkanEnv} + ${openclEnv} + ${runner} + ${banner "gen7-lab" "$(ls \"$ICD_VENDORS\"/*.icd 2>/dev/null | xargs -rn1 basename | sed 's/\\.icd//' | tr '\\n' ' ')"} + ''; + }; + + clvk = pkgs.mkShell { + inherit packages; + shellHook = '' + ${paths} + ${vulkanEnv} + ${runner} + export LD_LIBRARY_PATH="$CLVK_BUILD:''${LD_LIBRARY_PATH:-}" + export CLVK_MAX_COMPUTE_UNITS="''${CLVK_MAX_COMPUTE_UNITS:-16}" + unset OCL_ICD_VENDORS + ${banner "gen7-lab (clvk only)" "clvk (libOpenCL.so.1 shadows the loader)"} + ''; + }; + }; + }; +} diff --git a/ivb-test/.icd-vendors/pocl.icd b/ivb-test/.icd-vendors/pocl.icd new file mode 120000 index 0000000..66b0e83 --- /dev/null +++ b/ivb-test/.icd-vendors/pocl.icd @@ -0,0 +1 @@ +/nix/store/jr8wwd19z6yvsfxykva6brazipm06r9b-pocl-7.1/etc/OpenCL/vendors/pocl.icd \ No newline at end of file diff --git a/ivb-test/baseline.json b/ivb-test/baseline.json new file mode 100644 index 0000000..0d9d144 --- /dev/null +++ b/ivb-test/baseline.json @@ -0,0 +1,156 @@ +{ + "conditional_rendering": { + "pass": 233, + "fail": 8, + "skip": 789, + "aborted": false, + "rc": 1, + "group": "vulkan-ext", + "touched": "anv_conditional_rendering.c \u2014 genX_conditional_rendering()" + }, + "host_image_copy_linear": { + "pass": 223, + "fail": 0, + "skip": 1053, + "aborted": false, + "rc": 0, + "group": "vulkan-ext", + "touched": "anv_host_image_copy.c \u2014 isl linear_to_tiled / bounce buffer" + }, + "host_image_copy_optimal": { + "pass": 223, + "fail": 0, + "skip": 1053, + "aborted": false, + "rc": 0, + "group": "vulkan-ext", + "touched": "anv_host_image_copy.c \u2014 isl tiled_to_tiled / bounce buffer" + }, + "border_color_swizzle": { + "pass": 32, + "fail": 0, + "skip": 32, + "aborted": false, + "rc": 0, + "group": "vulkan-ext", + "touched": "anv_sampler.c \u2014 border color swizzle" + }, + "map_memory2": { + "pass": 4466, + "fail": 0, + "skip": 0, + "aborted": false, + "rc": 0, + "group": "vulkan-ext", + "touched": "anv_memory.c \u2014 genX_map_memory2()" + }, + "load_store_op_none": { + "pass": 209, + "fail": 0, + "skip": 64, + "aborted": false, + "rc": 0, + "group": "vulkan-ext", + "touched": "anv_render_pass.c \u2014 genX_load_store_op_none()" + }, + "feature_structs": { + "pass": 181, + "fail": 0, + "skip": 1, + "aborted": false, + "rc": 0, + "group": "vulkan-ext", + "touched": "anv_api_info.c \u2014 genX_get_physical_device_properties2()" + }, + "line_stipple": { + "pass": 8, + "fail": 0, + "skip": 40, + "aborted": false, + "rc": 0, + "group": "vulkan-ext", + "touched": "3DSTATE_WM LineStippleEnable (Gen7)" + }, + "line_rasterization": { + "pass": 41, + "fail": 0, + "skip": 67, + "aborted": false, + "rc": 0, + "group": "vulkan-ext", + "touched": "3DSTATE_SF / line rendering rules (Gen7)" + }, + "h264_decode": { + "frames": 488, + "errors": 0, + "rc": 0, + "group": "video", + "touched": "anv_video_decode.c + vme_kernels.h \u2014 VME dispatch, binding table, IDRT" + }, + "h264_encode": { + "psnr": 54.826539, + "min_psnr": 38.0, + "rc": 0, + "group": "video", + "touched": "anv_video_encode.c + vme_kernels.h \u2014 VME dispatch, binding table, IDRT" + }, + "h264_roundtrip": { + "psnr": null, + "min_psnr": 36.0, + "rc": -6, + "err": "Assertion slot_index >= 0 failed at libavcodec/vulkan_encode.c:216", + "group": "video", + "touched": "anv_video_encode.c + anv_video_decode.c \u2014 encode then decode back" + }, + "opencl_parity": { + "backends": { + "rusticl": { + "ok": true, + "device": "Mesa Intel(R) HD Graphics 4000 (IVB GT2)" + }, + "clvk": { + "ok": true, + "device": "Intel(R) HD Graphics 4000 (IVB GT2)" + }, + "pocl": { + "ok": true, + "device": "cpu-ivybridge-Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz" + } + }, + "ok_count": 3, + "total": 3, + "rc": 0, + "group": "opencl", + "touched": "rusticl (crocus) vs clvk (hasvk) vs pocl (cpu reference)" + }, + "cl_workgroup_limits": { + "ok": true, + "rc": 0, + "group": "opencl", + "touched": "crocus compute limits \u2014 max workgroup size" + }, + "cl_image_formats": { + "ok": true, + "rc": 0, + "group": "opencl", + "touched": "crocus supported image formats" + }, + "cl_atomics": { + "ok": true, + "rc": 0, + "group": "opencl", + "touched": "crocus atomic ops across multiple workgroups" + }, + "enc_standalone_i": { + "ok": true, + "rc": 0, + "group": "video", + "touched": "anv_video_mfc.c \u2014 I frame PAK objects, intra DC prediction" + }, + "enc_standalone_ip": { + "ok": true, + "rc": 0, + "group": "video", + "touched": "anv_video_mfc.c \u2014 P_Skip path, DPB slot 0/1, reference picture address" + } +} \ No newline at end of file diff --git a/ivb-test/manifest.toml b/ivb-test/manifest.toml new file mode 100644 index 0000000..f5785fd --- /dev/null +++ b/ivb-test/manifest.toml @@ -0,0 +1,197 @@ +# ivb-test manifest +# +# ${VAR} is expanded from the environment; `nix develop` exports all of them. +# Override any of them on the command line to test a different tree. + +[config] +mesa_build = "${MESA_BUILD}" +clvk_build = "${CLVK_BUILD}" +vk_driver_files = "${MESA_BUILD}/src/intel/vulkan_hasvk/intel_hasvk13_devenv_icd.x86_64.json" +icd_vendors = "${OCL_ICD_VENDORS}" +rusticl_enable = "crocus" + +cts_dir = "${CTS_DIR}" +cts_cmd = "./deqp-vk --deqp-case={filter} --deqp-log-filename={log} --deqp-surface-type=fbo" +cts_timeout = 3600 + +vulkan_device = "vk:0" +asset_width = 640 +asset_height = 480 +asset_frames = 488 + + +# Low-level capture profiles. INTEL_DEBUG flag names differ between mesa +# versions — check yours if a profile comes back empty. + +[capture.bat] +desc = "batchbuffer dump" +env = { INTEL_DEBUG = "bat" } + +[capture.submit] +desc = "batch submit + sync + stall" +env = { INTEL_DEBUG = "submit,sync,stall" } + +[capture.shaders] +desc = "shader disassembly (VS/FS/CS)" +env = { INTEL_DEBUG = "vs,fs,cs" } + +[capture.aub] +desc = "AUB dump" +wrapper = "intel_dump_gpu -o {out}/dump.aub" + +[capture.validate] +desc = "Vulkan validation layer" +env = { VK_INSTANCE_LAYERS = "VK_LAYER_KHRONOS_validation", MESA_VK_ABORT_ON_DEVICE_LOSS = "1" } + +[capture.nocache] +desc = "disable the shader cache" +env = { MESA_SHADER_CACHE_DISABLE = "1" } + + +# ------------------------------------------------------------ vulkan (CTS) + +[[test]] +name = "conditional_rendering" +group = "vulkan-ext" +touched = "anv_conditional_rendering.c — genX_conditional_rendering()" +kind = "cts" +filter = "dEQP-VK.conditional_rendering.*" + +[[test]] +name = "host_image_copy_linear" +group = "vulkan-ext" +touched = "anv_host_image_copy.c — isl linear_to_tiled / bounce buffer" +kind = "cts" +filter = "dEQP-VK.image.host_image_copy.simple.*.linear.*" + +[[test]] +name = "host_image_copy_optimal" +group = "vulkan-ext" +touched = "anv_host_image_copy.c — isl tiled_to_tiled / bounce buffer" +kind = "cts" +filter = "dEQP-VK.image.host_image_copy.simple.*.optimal.*" + +[[test]] +name = "border_color_swizzle" +group = "vulkan-ext" +touched = "anv_sampler.c — border color swizzle" +kind = "cts" +filter = "dEQP-VK.pipeline.monolithic.sampler.border_swizzle.r8g8b8a8_unorm.*.custom.no_gather.*" + +[[test]] +name = "map_memory2" +group = "vulkan-ext" +touched = "anv_memory.c — genX_map_memory2()" +kind = "cts" +filter = "dEQP-VK.memory.mapping.*" + +[[test]] +name = "load_store_op_none" +group = "vulkan-ext" +touched = "anv_render_pass.c — genX_load_store_op_none()" +kind = "cts" +filter = "dEQP-VK.renderpasses.*.load_store_op_none.*" + +[[test]] +name = "feature_structs" +group = "vulkan-ext" +touched = "anv_api_info.c — genX_get_physical_device_properties2()" +kind = "cts" +filter = "dEQP-VK.api.info.get_physical_device_properties2.features.*" + +[[test]] +name = "line_stipple" +group = "vulkan-ext" +touched = "3DSTATE_WM LineStippleEnable (Gen7)" +kind = "cts" +filter = "dEQP-VK.pipeline.monolithic.extended_dynamic_state.*.line_stipple_*" + +[[test]] +name = "line_rasterization" +group = "vulkan-ext" +touched = "3DSTATE_SF / line rendering rules (Gen7)" +kind = "cts" +filter = "dEQP-VK.rasterization.primitives.*lines*" + + +# ------------------------------------------------------------------- video + +[[test]] +name = "h264_decode" +group = "video" +touched = "anv_video_decode.c + vme_kernels.h — VME dispatch, binding table, IDRT" +kind = "video" +op = "decode" + +[[test]] +name = "h264_encode" +group = "video" +touched = "anv_video_encode.c + vme_kernels.h — VME dispatch, binding table, IDRT" +kind = "video" +op = "encode" +min_psnr = 38.0 + +[[test]] +name = "h264_roundtrip" +group = "video" +touched = "anv_video_encode.c + anv_video_decode.c — encode then decode back" +kind = "video" +op = "roundtrip" +min_psnr = 36.0 + + +# ------------------------------------------------------------------ opencl + +[[test]] +name = "opencl_parity" +group = "opencl" +touched = "rusticl (crocus) vs clvk (hasvk) vs pocl (cpu reference)" +kind = "opencl" +backends = ["rusticl", "clvk", "pocl"] + +[[test]] +name = "cl_workgroup_limits" +group = "opencl" +touched = "crocus compute limits — max workgroup size" +kind = "cmd" +cwd = "opencl_tests/16x16" +build = "gcc -O2 wg_size_probe.c -o {out}/probe -lOpenCL" +cmd = "{out}/probe" + +[[test]] +name = "cl_image_formats" +group = "opencl" +touched = "crocus supported image formats" +kind = "cmd" +cwd = "opencl_tests/16x16" +build = "gcc -O2 cl_image_format_probe.c -o {out}/probe -lOpenCL" +cmd = "{out}/probe" + +[[test]] +name = "cl_atomics" +group = "opencl" +touched = "crocus atomic ops across multiple workgroups" +kind = "cmd" +cwd = "opencl_tests/atomic" +build = "gcc -O2 multi_atomic_test.c -o {out}/probe -lOpenCL" +cmd = "{out}/probe" + +[[test]] +name = "enc_standalone_i" +group = "video" +touched = "anv_video_mfc.c — I frame PAK objects, intra DC prediction" +kind = "cmd" +cwd = "encode" +build = "gcc -O1 -g hasvk_encode_test.c -o {out}/enctest -lvulkan" +cmd = "{out}/enctest" +match = "frame 0 \\(I\\): bytesWritten=[1-9]" + +[[test]] +name = "enc_standalone_ip" +group = "video" +touched = "anv_video_mfc.c — P_Skip path, DPB slot 0/1, reference picture address" +kind = "cmd" +cwd = "encode" +build = "gcc -O1 -g hasvk_encode_test.c -o {out}/enctest -lvulkan" +cmd = "env HASVK_ENC_PFRAME=1 {out}/enctest" +match = "frame 1 \\(P\\): bytesWritten=[1-9]" diff --git a/ivb-test/runner.py b/ivb-test/runner.py new file mode 100755 index 0000000..a860695 --- /dev/null +++ b/ivb-test/runner.py @@ -0,0 +1,605 @@ +#!/usr/bin/env python3 +"""Ivy Bridge (Gen7) driver test runner. + +Reads manifest.toml, runs the tests against the driver trees the nix shell +points at, and diffs the result against baseline.json. +""" + +import argparse +import json +import os +import re +import shlex +import shutil +import subprocess +import sys +import tomllib +from datetime import datetime +from pathlib import Path +from typing import Any + +ROOT = Path(__file__).resolve().parent +LAB = ROOT.parent +MANIFEST = ROOT / "manifest.toml" +BASELINE = ROOT / "baseline.json" +RESULT = ROOT / "result" + +C_OK, C_BAD, C_DIM, C_OFF = "\033[32m", "\033[31m", "\033[90m", "\033[0m" +if not sys.stdout.isatty(): + C_OK = C_BAD = C_DIM = C_OFF = "" + + +# ---------------------------------------------------------------- manifest + +def expand(v: Any) -> Any: + if isinstance(v, str): + return os.path.expandvars(os.path.expanduser(v)) + if isinstance(v, dict): + return {k: expand(x) for k, x in v.items()} + if isinstance(v, list): + return [expand(x) for x in v] + return v + + +def load_manifest(): + with open(MANIFEST, "rb") as f: + return expand(tomllib.load(f)) + + +def select(man, only=None, group=None): + tests = man["test"] + if only: + tests = [t for t in tests if t["name"] in only] + if group: + tests = [t for t in tests if t.get("group") in group] + return tests + + +# ----------------------------------------------------------------- process + +def run(cmd, outdir, tag, env=None, timeout=3600, cwd=None): + full_env = dict(os.environ) + if env: + full_env.update({k: str(v) for k, v in env.items()}) + outdir.mkdir(parents=True, exist_ok=True) + try: + p = subprocess.run( + cmd if isinstance(cmd, list) else shlex.split(cmd), + capture_output=True, text=True, env=full_env, timeout=timeout, + cwd=cwd or None, + ) + text, rc = p.stdout + p.stderr, p.returncode + except subprocess.TimeoutExpired: + text, rc = "TIMEOUT\n", 124 + except FileNotFoundError as e: + text, rc = f"NOT FOUND: {e}\n", 127 + (outdir / f"{tag}.log").write_text(text) + return rc, text + + +def driver_env(cfg): + icd = cfg.get("vk_driver_files", "") + if not icd: + return {} + return {"VK_DRIVER_FILES": icd, "VK_ICD_FILENAMES": icd} + + +# ------------------------------------------------------------------ checks + +def probe_env(cfg): + """Everything the runner depends on, and whether it is actually there.""" + icd_dir = Path(cfg.get("icd_vendors", "")) + vendors = sorted(p.stem for p in icd_dir.glob("*.icd")) if icd_dir.is_dir() else [] + cts = Path(cfg.get("cts_dir", "")) + return [ + ("mesa build", cfg.get("mesa_build", ""), Path(cfg.get("mesa_build", "/x")).is_dir()), + ("hasvk ICD", cfg.get("vk_driver_files", ""), Path(cfg.get("vk_driver_files", "/x")).is_file()), + ("clvk build", cfg.get("clvk_build", ""), Path(cfg.get("clvk_build", "/x")).is_dir()), + ("cts dir", cfg.get("cts_dir", ""), cts.is_dir()), + ("deqp-vk", str(cts / "deqp-vk"), (cts / "deqp-vk").is_file()), + ("icd vendors", f"{icd_dir} [{' '.join(vendors) or 'empty'}]", bool(vendors)), + ("ffmpeg", shutil.which("ffmpeg") or "-", bool(shutil.which("ffmpeg"))), + ] + + +def check_config(cfg): + """The Vulkan loader silently falls back to the system ICD when the file + it is pointed at is missing, which quietly tests the wrong driver.""" + icd = cfg.get("vk_driver_files", "") + if icd and not Path(icd).is_file(): + sys.exit(f"vk_driver_files missing: {icd}\n" + f"the loader would fall back to the system ICD — refusing to run") + cts = cfg.get("cts_dir", "") + if cts and not Path(cts).is_dir(): + sys.exit(f"cts_dir missing: {cts}") + + +# ------------------------------------------------------------------ assets + +def make_assets(cfg, outdir): + w, h, n = cfg["asset_width"], cfg["asset_height"], cfg["asset_frames"] + assets = outdir / "assets" + assets.mkdir(parents=True, exist_ok=True) + ref, src = assets / "ref.y4m", assets / "src.h264" + + if not ref.exists(): + rc, _ = run(f"ffmpeg -y -f lavfi -i testsrc2=size={w}x{h}:rate=30 " + f"-frames:v {n} -pix_fmt yuv420p {ref}", assets, "gen_ref") + if rc != 0 or not ref.exists(): + sys.exit(f"could not generate ref.y4m — {assets}/gen_ref.log") + + if not src.exists(): + # B-frames on purpose: the decoder has to handle reordering + rc, _ = run(f"ffmpeg -y -i {ref} -c:v libx264 -preset medium " + f"-bf 3 -b_strategy 2 -refs 4 -g 30 -crf 20 {src}", + assets, "gen_src") + if rc != 0 or not src.exists(): + sys.exit(f"could not generate src.h264 — {assets}/gen_src.log") + + return ref, src + + +# ----------------------------------------------------------------- runners + +def run_cts(t, cfg, outdir): + qpa = outdir / "TestResults.qpa" + cmd = cfg["cts_cmd"].format(filter=t["filter"], log=qpa) + rc, text = run(cmd, outdir, "cts", env=driver_env(cfg), cwd=cfg.get("cts_dir"), + timeout=t.get("timeout", cfg.get("cts_timeout", 3600))) + + blob = text + (qpa.read_text(errors="ignore") if qpa.exists() else "") + count = lambda w: len(re.findall(rf'StatusCode="{w}"', blob)) + + passed = count("Pass") + failed = count("Fail") + count("QualityWarning") + count("InternalError") + skipped = count("NotSupported") + + if passed == 0 and failed == 0: # some wrappers only print the summary + m = re.search(r"Passed:\s*(\d+).*?Failed:\s*(\d+).*?Not supported:\s*(\d+)", + blob, re.S) + if m: + passed, failed, skipped = (int(x) for x in m.groups()) + + aborted = "ABORTED" in blob + return {"pass": passed, "fail": failed, "skip": skipped, + "aborted": aborted, "rc": rc} + + +def last_error(text): + """The line worth putting in the summary when ffmpeg gives up.""" + for line in reversed(text.strip().splitlines()): + if re.search(r"assert|error|failed|invalid|not implemented|no such", + line, re.I) and "Task finished" not in line: + return line.strip()[:120] + return "" + + +def parse_psnr(text): + m = re.search(r"average:([\d.]+)", text) or \ + re.search(r"PSNR.*?average:\s*([\d.]+)", text) + return float(m.group(1)) if m else None + + +def run_video(t, cfg, outdir, assets): + ref, src = assets + env = driver_env(cfg) + op = t["op"] + + # h264_vulkan takes Vulkan frames, so the software frames have to be + # uploaded explicitly — without this ffmpeg dies in the filter graph and + # the encoder is never reached. + dev = cfg.get("vulkan_device", "vk:0") + hw = f"-init_hw_device vulkan={dev} -filter_hw_device vk" + upload = "-vf format=nv12,hwupload" + + if op == "decode": + rc, text = run(f"ffmpeg -v info -hwaccel vulkan -i {src} -f null -", + outdir, "decode", env=env) + hits = re.findall(r"frame=\s*(\d+)", text) + return {"frames": max((int(x) for x in hits), default=0), + "errors": len(re.findall(r"\[h264.*?\] (error|Error|corrupt)", text)), + "rc": rc} + + if op == "encode": + out = outdir / "enc.h264" + rc, text = run(f"ffmpeg -y {hw} -i {ref} {upload} " + f"-c:v h264_vulkan -qp 18 -g 1 {out}", + outdir, "encode", env=env) + if rc != 0 or not out.exists() or out.stat().st_size == 0: + return {"psnr": None, "min_psnr": t.get("min_psnr"), "rc": rc, + "err": last_error(text)} + _, text = run(f"ffmpeg -i {out} -i {ref} -lavfi psnr -f null -", outdir, "psnr") + return {"psnr": parse_psnr(text), "min_psnr": t.get("min_psnr"), "rc": rc} + + if op == "roundtrip": + enc, dec = outdir / "rt.h264", outdir / "rt.y4m" + rc, text = run(f"ffmpeg -y {hw} -i {ref} {upload} " + f"-c:v h264_vulkan -qp 18 {enc}", + outdir, "rt_encode", env=env) + if rc != 0 or not enc.exists() or enc.stat().st_size == 0: + return {"psnr": None, "min_psnr": t.get("min_psnr"), "rc": rc, + "err": last_error(text)} + rc, text = run(f"ffmpeg -y -hwaccel vulkan -i {enc} {dec}", + outdir, "rt_decode", env=env) + if rc != 0 or not dec.exists(): + return {"psnr": None, "min_psnr": t.get("min_psnr"), "rc": rc, + "err": last_error(text)} + _, text = run(f"ffmpeg -i {dec} -i {ref} -lavfi psnr -f null -", outdir, "rt_psnr") + return {"psnr": parse_psnr(text), "min_psnr": t.get("min_psnr"), "rc": 0} + + return {"rc": 1, "err": f"unknown video op: {op}"} + + +CL_PROBE = r''' +import json, sys +import numpy as np, pyopencl as cl + +out = [] +for p in cl.get_platforms(): + for d in p.get_devices(): + r = {"platform": p.name.strip(), "device": d.name.strip(), "ok": False} + try: + ctx = cl.Context([d]) + q = cl.CommandQueue(ctx) + prg = cl.Program(ctx, open(sys.argv[1]).read()).build() + a = np.arange(4096, dtype=np.float32) + b = a * 2.0 + mf = cl.mem_flags + ba = cl.Buffer(ctx, mf.READ_ONLY | mf.COPY_HOST_PTR, hostbuf=a) + bb = cl.Buffer(ctx, mf.READ_ONLY | mf.COPY_HOST_PTR, hostbuf=b) + bc = cl.Buffer(ctx, mf.WRITE_ONLY, a.nbytes) + prg.vec_add(q, a.shape, None, ba, bb, bc) + got = np.empty_like(a) + cl.enqueue_copy(q, got, bc) + q.finish() + r["ok"] = bool(np.allclose(got, a + b)) + if not r["ok"]: + r["err"] = "result mismatch" + except Exception as e: + r["err"] = f"{type(e).__name__}: {e}"[:200] + out.append(r) +print("__CLPROBE__" + json.dumps(out)) +''' + +CL_KERNEL = """__kernel void vec_add(__global const float *a, __global const float *b, + __global float *c) { + int i = get_global_id(0); + c[i] = a[i] + b[i]; +} +""" + + +def run_opencl(t, cfg, outdir): + """Each backend runs on its own, with a vendor dir holding only its ICD, + so a backend that fails to load cannot be masked by another one.""" + outdir.mkdir(parents=True, exist_ok=True) + kernel = outdir / "vec_add.cl" + kernel.write_text(CL_KERNEL) + probe = outdir / "probe.py" + probe.write_text(CL_PROBE) + + icd_dir = Path(cfg.get("icd_vendors", "")) + backends = t.get("backends", ["rusticl", "clvk", "pocl"]) + results = {} + + for name in backends: + icd = icd_dir / f"{name}.icd" + if not icd.exists(): + results[name] = {"ok": False, "err": f"no {name}.icd in {icd_dir}"} + continue + vend = outdir / "vendors" / name + vend.mkdir(parents=True, exist_ok=True) + target = vend / f"{name}.icd" + if target.is_symlink() or target.exists(): + target.unlink() + target.symlink_to(icd.resolve()) + + env = dict(driver_env(cfg)) + env.update({"OCL_ICD_VENDORS": str(vend), + "OCL_ICD_ASSUME_ICD_EXTENSION": "1", + "PYOPENCL_COMPILER_OUTPUT": "1"}) + if name == "rusticl": + env["RUSTICL_ENABLE"] = cfg.get("rusticl_enable", "crocus") + + rc, text = run([sys.executable, str(probe), str(kernel)], outdir, + f"cl_{name}", env=env, timeout=t.get("timeout", 600)) + m = re.search(r"__CLPROBE__(.*)", text) + if rc != 0 or not m: + results[name] = {"ok": False, "err": f"probe failed (rc={rc})"} + continue + devs = json.loads(m.group(1)) + if not devs: + results[name] = {"ok": False, "err": "no device"} + continue + d = devs[0] + results[name] = {"ok": d["ok"], "device": d["device"], + **({"err": d["err"]} if d.get("err") else {})} + + return {"backends": results, + "ok_count": sum(1 for r in results.values() if r["ok"]), + "total": len(backends), + "rc": 0 if all(r["ok"] for r in results.values()) else 1} + + +def run_cmd(t, cfg, outdir): + """Generic escape hatch: build (optionally) and run a probe from the lab + tree. Probes are compiled per run — checked-in binaries go stale as soon + as the nix store is garbage collected.""" + outdir.mkdir(parents=True, exist_ok=True) + cwd = t.get("cwd") + cwd = str(LAB / cwd) if cwd and not os.path.isabs(cwd) else cwd + fmt = lambda s: s.format(lab=LAB, out=outdir) + + if t.get("build"): + rc, _ = run(fmt(t["build"]), outdir, "build", cwd=cwd, timeout=600) + if rc != 0: + return {"ok": False, "rc": rc, "err": "build failed"} + + rc, text = run(fmt(t["cmd"]), outdir, "cmd", env=driver_env(cfg), + cwd=cwd, timeout=t.get("timeout", 600)) + ok = rc == t.get("expect_rc", 0) + if ok and t.get("match"): + ok = bool(re.search(t["match"], text, re.S)) + return {"ok": ok, "rc": rc} + + +KINDS = {"cts": run_cts, "video": run_video, "opencl": run_opencl, "cmd": run_cmd} + + +# -------------------------------------------------------------- formatting + +def fmt_one(r): + if "pass" in r: + s = f"{r['pass']}/{r['fail']}" + return s + (f" {C_BAD}aborted{C_OFF}" if r.get("aborted") else "") + if "frames" in r: + return f"{r['frames']} frames, {r['errors']} errors" + if "psnr" in r: + if not r["psnr"]: + why = f" — {r['err']}" if r.get("err") else "" + return f"{C_BAD}failed{C_OFF}{C_DIM}{why}{C_OFF}" + lo = r.get("min_psnr") + flag = f" {C_BAD}<{lo}{C_OFF}" if lo and r["psnr"] < lo else "" + return f"psnr {r['psnr']}{flag}" + if "ok_count" in r: + up = [n for n, b in r["backends"].items() if b["ok"]] + down = [n for n, b in r["backends"].items() if not b["ok"]] + s = "+".join(up) if up else "none" + return f"{s} ok" + (f", {C_BAD}{'+'.join(down)} down{C_OFF}" if down else "") + if "both_up" in r: # pre-0.2 baselines + return "both up" if r["both_up"] else f"{C_BAD}missing{C_OFF}" + if "ok" in r: + return "ok" if r["ok"] else f"{C_BAD}fail (rc={r.get('rc')}){C_OFF}" + return "?" + + +def score(r): + if "pass" in r: + return r["pass"] - r["fail"] * 1000 + if "frames" in r: + return r["frames"] - r["errors"] * 1000 + if "psnr" in r: + return r["psnr"] or -1 + if "ok_count" in r: + return r["ok_count"] + if "both_up" in r: + return 2 if r["both_up"] else 0 + if "ok" in r: + return 1 if r["ok"] else 0 + return -1 + + +def comparable(a, b): + """Result shapes must match, otherwise the scores mean different things.""" + keys = lambda r: next((k for k in ("pass", "frames", "psnr", "ok_count", + "both_up", "ok") if k in r), None) + ka, kb = keys(a), keys(b) + return ka == kb or {ka, kb} == {"ok_count", "both_up"} + + +def below_floor(r): + lo = r.get("min_psnr") + return bool(lo) and (r.get("psnr") or 0) < lo + + +def has_regression(base, cur): + for n, v in cur.items(): + if below_floor(v): + return True + old = base.get(n) + if old and comparable(old, v) and score(v) < score(old): + return True + return False + + +def row(name, r, old): + val = fmt_one(r) + if old is None or not comparable(old, r): + return f" {C_DIM}new{C_OFF} {name:<28} {val}" + cur_s, old_s = score(r), score(old) + if cur_s > old_s: + return f" {C_OK}^{C_OFF} {name:<28} {val} (was {fmt_one(old)})" + if cur_s < old_s: + return f" {C_BAD}v{C_OFF} {name:<28} {val} (was {fmt_one(old)})" + return f" = {name:<28} {val}" + + +def diff_report(base, cur, group_by="group"): + if group_by != "group": + return "\n".join(row(n, r, base.get(n)) for n, r in cur.items()) + groups = {} + for n, r in cur.items(): + groups.setdefault(r.get("group", "other"), []).append((n, r)) + lines = [] + for g in sorted(groups): + lines.append(f"\n{C_DIM}[{g}]{C_OFF}") + lines += [row(n, r, base.get(n)) for n, r in groups[g]] + return "\n".join(lines) + + +def strip_color(s): + return re.sub(r"\033\[[0-9;]*m", "", s) + + +# ---------------------------------------------------------------- commands + +def new_result_dir(): + d = RESULT / datetime.now().strftime("%Y-%m-%d_%H-%M-%S") + d.mkdir(parents=True, exist_ok=True) + latest = RESULT / "latest" + if latest.is_symlink() or latest.exists(): + latest.unlink() if latest.is_symlink() else shutil.rmtree(latest) + latest.symlink_to(d.name) + return d + + +def do_run(args): + man = load_manifest() + cfg = man["config"] + check_config(cfg) + + tests = select(man, args.only, args.group) + if not tests: + sys.exit("no test matches") + + rundir = new_result_dir() + assets = (make_assets(cfg, RESULT) + if any(t["kind"] == "video" for t in tests) else (None, None)) + + results = {} + for t in tests: + name = t["name"] + print(f"{C_DIM}..{C_OFF} {name} ", end="", flush=True) + fn = KINDS.get(t["kind"]) + if not fn: + r = {"rc": 1, "err": f"unknown kind: {t['kind']}"} + elif t["kind"] == "video": + r = fn(t, cfg, rundir / name, assets) + else: + r = fn(t, cfg, rundir / name) + r["group"] = t.get("group", "other") + r["touched"] = t.get("touched", "") + results[name] = r + print(fmt_one(r)) + + (rundir / "results.json").write_text(json.dumps(results, indent=2)) + + base = json.loads(BASELINE.read_text()) if BASELINE.exists() else {} + report = diff_report(base, results, args.group_by) + (rundir / "summary.txt").write_text(strip_color(report)) + print("\n" + report) + print(f"{C_DIM}-> {rundir}{C_OFF}") + + if args.update_baseline: + BASELINE.write_text(json.dumps(results if not (args.only or args.group) + else {**base, **results}, indent=2)) + print(f"{C_DIM}baseline updated{C_OFF}") + + return 1 if has_regression(base, results) else 0 + + +def do_capture(args): + man = load_manifest() + cfg = man["config"] + check_config(cfg) + + prof = man.get("capture", {}).get(args.profile) + if not prof: + sys.exit(f"profile not found: {args.profile}\n" + f"available: {', '.join(man.get('capture', {}))}") + t = next((x for x in man["test"] if x["name"] == args.name), None) + if not t: + sys.exit(f"test not found: {args.name}") + + outdir = new_result_dir() / args.name / "capture" + outdir.mkdir(parents=True, exist_ok=True) + + env = dict(driver_env(cfg)) + env.update(prof.get("env", {})) + print(f"{C_DIM}profile: {args.profile} — {prof.get('desc', '')}{C_OFF}") + for k, v in env.items(): + print(f"{C_DIM} {k}={v}{C_OFF}") + + if t["kind"] == "cts": + cmd = cfg["cts_cmd"].format(filter=t["filter"], log=outdir / "TestResults.qpa") + cwd = cfg.get("cts_dir") + elif t["kind"] == "video": + ref, src = make_assets(cfg, RESULT) + dev = cfg.get("vulkan_device", "vk:0") + cmd = (f"ffmpeg -v verbose -hwaccel vulkan -i {src} -f null -" + if t.get("op") == "decode" else + f"ffmpeg -y -v verbose -init_hw_device vulkan={dev} " + f"-filter_hw_device vk -i {ref} -vf format=nv12,hwupload " + f"-c:v h264_vulkan -qp 18 -g 1 {outdir}/enc.h264") + cwd = None + else: + sys.exit(f"capture does not support kind={t['kind']}") + + wrapper = prof.get("wrapper", "").format(out=outdir) + rc, _ = run(f"{wrapper} {cmd}".strip(), outdir, "capture", env=env, cwd=cwd) + + print(f"rc={rc} -> {outdir}") + for f in sorted(outdir.iterdir()): + print(f" {f.name} {f.stat().st_size} B") + return rc + + +def do_doctor(args): + cfg = load_manifest()["config"] + bad = 0 + for label, value, ok in probe_env(cfg): + mark = f"{C_OK}ok {C_OFF}" if ok else f"{C_BAD}MISSING{C_OFF}" + bad += not ok + print(f" {mark:<12} {label:<14} {value}") + if bad: + print(f"\n{C_DIM}enter the lab shell with 'nix develop' so the paths " + f"get exported, or override them in the environment{C_OFF}") + return 1 if bad else 0 + + +def do_list(args): + man = load_manifest() + groups = {} + for t in man["test"]: + groups.setdefault(t.get("group", "other"), []).append(t) + for g in sorted(groups): + print(f"\n{C_DIM}[{g}]{C_OFF}") + for t in groups[g]: + print(f" {t['name']:<28} {C_DIM}{t.get('touched', '')}{C_OFF}") + print(f"\n{C_DIM}capture profiles:{C_OFF}") + for k, v in man.get("capture", {}).items(): + print(f" {k:<12} {C_DIM}{v.get('desc', '')}{C_OFF}") + + +def do_clean(args): + if RESULT.exists(): + shutil.rmtree(RESULT) + print("result/ removed") + + +def main(): + ap = argparse.ArgumentParser(prog="ivb") + sub = ap.add_subparsers(dest="cmd", required=True) + + r = sub.add_parser("run", help="run tests and diff against the baseline") + r.add_argument("--only", nargs="+", metavar="NAME") + r.add_argument("--group", nargs="+", metavar="G") + r.add_argument("--group-by", choices=["group", "none"], default="group") + r.add_argument("--update-baseline", action="store_true") + r.set_defaults(fn=do_run) + + c = sub.add_parser("capture", help="run one test under a low-level profile") + c.add_argument("name") + c.add_argument("--profile", default="bat") + c.set_defaults(fn=do_capture) + + sub.add_parser("doctor", help="check the driver trees the lab points at").set_defaults(fn=do_doctor) + sub.add_parser("list", help="list tests and capture profiles").set_defaults(fn=do_list) + sub.add_parser("clean", help="remove result/").set_defaults(fn=do_clean) + + args = ap.parse_args() + sys.exit(args.fn(args) or 0) + + +if __name__ == "__main__": + main() diff --git a/media/.gitkeep b/media/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/misc/parked-pak-access-upper-bound.patch b/misc/parked-pak-access-upper-bound.patch new file mode 100644 index 0000000..d1f1bb9 --- /dev/null +++ b/misc/parked-pak-access-upper-bound.patch @@ -0,0 +1,46 @@ +diff --git a/src/intel/vulkan_hasvk/genX_cmd_video.c b/src/intel/vulkan_hasvk/genX_cmd_video.c +index 68878e71a24..93f27eb56db 100644 +--- a/src/intel/vulkan_hasvk/genX_cmd_video.c ++++ b/src/intel/vulkan_hasvk/genX_cmd_video.c +@@ -1191,6 +1191,16 @@ anv_h264_encode_video(struct anv_cmd_buffer *cmd_buffer, + { .bo = dst_buffer->address.bo, .offset = bs_abs & ~4095ull }; + uint32_t dst_page_off = (uint32_t)(bs_abs & 4095); + ++ /* The PAK gets an access upper bound so it cannot write past the ++ * allocation. dstBufferRange is what the client declares it needs, and ++ * clients do leave it at zero -- both the CTS and the Vulkan video sample ++ * encoder do -- which taken literally bounds the writes to nothing. Use ++ * what the buffer actually holds instead. */ ++ uint64_t dst_avail = dst_buffer->vk.size - encode_info->dstBufferOffset; ++ uint64_t dst_range = encode_info->dstBufferRange; ++ if (dst_range == 0 || dst_range > dst_avail) ++ dst_range = dst_avail; ++ + /* Reconstructed picture (pre-deblocking destination). PAK requires a valid + * target since PreDeblockingOutputEnable is set, so the setup DPB slot is + * mandatory; there is no internal recon-image fallback. */ +@@ -1251,7 +1261,7 @@ anv_h264_encode_video(struct anv_cmd_buffer *cmd_buffer, + /* Frame-level static state, emitted once before any slice. */ + genX(hasvk_mfc_emit_static_state)(cmd_buffer, img, recon_address, sps, pps, + dst_address, dst_page_off, +- encode_info->dstBufferRange, ++ dst_range, + width_in_mbs, height_in_mbs, is_p, &refs); + + /* Intra refresh, if the session was created with a mode and this picture + +--- NOT --- +Park edildi. Bkz. docs/vulkan_hasvk.md §10o ve §10q. + +Ne yapiyor: dstBufferRange sifir geldiginde PAK'in erisim ust sinirini +tamponun kalan boyutuna kelepceliyor. Istemciler o alani sifir birakiyor +(hem CTS hem Vulkan ornek encoder'i), sifir alininca sinir tabana esitleniyor +ve donanima "sifir bayt yazabilirsin" denmis oluyor. + +Olculen etki (ikisinde de B frame acik, 60 testlik ayri-DPB listesi): + yamasiz 48 Pass 0 Fail 0 Warning | bagimsiz istemci BOZUK (64 bayt iniyor) + yamali 6 Pass 0 Fail 42 Warning | bagimsiz istemci CALISIYOR (45 dB) +Uyarilar fail degil: I frame 29,81 dB, esik 30. + +Cozulmemis soru: bir erisim bariyerinin kodlama kalitesini nicin 0,2 dB +etkiledigi. Anlasilmadan hangisinin dogru oldugu secilemez.